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Merge branch 'release/v3.1' into feature/cmake_v3.1

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This commit is contained in:
Angus Gratton
2018-08-16 12:58:31 +10:00
committed by Angus Gratton
parent 810aa5427c 53509c7bfd
commit 7f50bb7e7f
645 changed files with 16850 additions and 19460 deletions
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4
components/esp32/CMakeLists.txt
View File

@@ -38,7 +38,9 @@ else()
target_linker_script(esp32
"ld/esp32.common.ld"
"ld/esp32.rom.ld"
"ld/esp32.peripherals.ld")
"ld/esp32.peripherals.ld"
"ld/esp32.rom.libgcc.ld"
)
if(CONFIG_SPIRAM_CACHE_WORKAROUND)
add_compile_options(-mfix-esp32-psram-cache-issue)

8
components/esp32/Makefile.projbuild
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@@ -4,8 +4,8 @@ PHY_INIT_DATA_OBJ = $(BUILD_DIR_BASE)/phy_init_data.o
PHY_INIT_DATA_BIN = $(BUILD_DIR_BASE)/phy_init_data.bin
# Command to flash PHY init data partition
PHY_INIT_DATA_FLASH_CMD = $(ESPTOOLPY_SERIAL) write_flash $(CONFIG_PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
ESPTOOL_ALL_FLASH_ARGS += $(CONFIG_PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
PHY_INIT_DATA_FLASH_CMD = $(ESPTOOLPY_SERIAL) write_flash $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
ESPTOOL_ALL_FLASH_ARGS += $(PHY_DATA_OFFSET) $(PHY_INIT_DATA_BIN)
ESP32_COMPONENT_PATH := $(COMPONENT_PATH)
@@ -38,3 +38,7 @@ CFLAGS+=-mfix-esp32-psram-cache-issue
CXXFLAGS+=-mfix-esp32-psram-cache-issue
endif
# Enable dynamic esp_timer overflow value if building unit tests
ifneq ("$(TEST_COMPONENTS_LIST)","")
CPPFLAGS += -DESP_TIMER_DYNAMIC_OVERFLOW_VAL
endif

2
components/esp32/clk.c
View File

@@ -88,7 +88,7 @@ void esp_clk_init(void)
break;
default:
freq_mhz = 80;
/* no break */
/* falls through */
case 80:
freq = RTC_CPU_FREQ_80M;
break;

3
components/esp32/component.mk
View File

@@ -13,6 +13,9 @@ endif
#specifies its own scripts.
LINKER_SCRIPTS += esp32.common.ld esp32.rom.ld esp32.peripherals.ld
#Force pure functions from libgcc.a to be linked from ROM
LINKER_SCRIPTS += esp32.rom.libgcc.ld
#SPI-RAM incompatible functions can be used in when the SPI RAM
#workaround is not enabled.
ifndef CONFIG_SPIRAM_CACHE_WORKAROUND

2
components/esp32/crosscore_int.c
View File

@@ -44,7 +44,7 @@ static volatile uint32_t reason[ portNUM_PROCESSORS ];
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
*/
static void esp_crosscore_isr_handle_yield()
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield()
{
portYIELD_FROM_ISR();
}

1
components/esp32/dport_panic_highint_hdl.S
View File

@@ -16,7 +16,6 @@
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include <xtensa/simcall.h>
#include "freertos/xtensa_context.h"
#include "esp_panic.h"
#include "sdkconfig.h"

35
components/esp32/esp_err_to_name.c
View File

@@ -55,43 +55,43 @@ typedef struct {
static const esp_err_msg_t esp_err_msg_table[] = {
// components/esp32/include/esp_err.h
# ifdef ESP_FAIL
ERR_TBL_IT(ESP_FAIL), /* -1 */
ERR_TBL_IT(ESP_FAIL), /* -1 Generic esp_err_t code indicating failure */
# endif
# ifdef ESP_OK
ERR_TBL_IT(ESP_OK), /* 0 */
ERR_TBL_IT(ESP_OK), /* 0 esp_err_t value indicating success (no error) */
# endif
# ifdef ESP_ERR_NO_MEM
ERR_TBL_IT(ESP_ERR_NO_MEM), /* 257 0x101 */
ERR_TBL_IT(ESP_ERR_NO_MEM), /* 257 0x101 Out of memory */
# endif
# ifdef ESP_ERR_INVALID_ARG
ERR_TBL_IT(ESP_ERR_INVALID_ARG), /* 258 0x102 */
ERR_TBL_IT(ESP_ERR_INVALID_ARG), /* 258 0x102 Invalid argument */
# endif
# ifdef ESP_ERR_INVALID_STATE
ERR_TBL_IT(ESP_ERR_INVALID_STATE), /* 259 0x103 */
ERR_TBL_IT(ESP_ERR_INVALID_STATE), /* 259 0x103 Invalid state */
# endif
# ifdef ESP_ERR_INVALID_SIZE
ERR_TBL_IT(ESP_ERR_INVALID_SIZE), /* 260 0x104 */
ERR_TBL_IT(ESP_ERR_INVALID_SIZE), /* 260 0x104 Invalid size */
# endif
# ifdef ESP_ERR_NOT_FOUND
ERR_TBL_IT(ESP_ERR_NOT_FOUND), /* 261 0x105 */
ERR_TBL_IT(ESP_ERR_NOT_FOUND), /* 261 0x105 Requested resource not found */
# endif
# ifdef ESP_ERR_NOT_SUPPORTED
ERR_TBL_IT(ESP_ERR_NOT_SUPPORTED), /* 262 0x106 */
ERR_TBL_IT(ESP_ERR_NOT_SUPPORTED), /* 262 0x106 Operation or feature not supported */
# endif
# ifdef ESP_ERR_TIMEOUT
ERR_TBL_IT(ESP_ERR_TIMEOUT), /* 263 0x107 */
ERR_TBL_IT(ESP_ERR_TIMEOUT), /* 263 0x107 Operation timed out */
# endif
# ifdef ESP_ERR_INVALID_RESPONSE
ERR_TBL_IT(ESP_ERR_INVALID_RESPONSE), /* 264 0x108 */
ERR_TBL_IT(ESP_ERR_INVALID_RESPONSE), /* 264 0x108 Received response was invalid */
# endif
# ifdef ESP_ERR_INVALID_CRC
ERR_TBL_IT(ESP_ERR_INVALID_CRC), /* 265 0x109 */
ERR_TBL_IT(ESP_ERR_INVALID_CRC), /* 265 0x109 CRC or checksum was invalid */
# endif
# ifdef ESP_ERR_INVALID_VERSION
ERR_TBL_IT(ESP_ERR_INVALID_VERSION), /* 266 0x10a */
ERR_TBL_IT(ESP_ERR_INVALID_VERSION), /* 266 0x10a Version was invalid */
# endif
# ifdef ESP_ERR_INVALID_MAC
ERR_TBL_IT(ESP_ERR_INVALID_MAC), /* 267 0x10b */
ERR_TBL_IT(ESP_ERR_INVALID_MAC), /* 267 0x10b MAC address was invalid */
# endif
// components/nvs_flash/include/nvs.h
# ifdef ESP_ERR_NVS_BASE
@@ -132,7 +132,7 @@ static const esp_err_msg_t esp_err_msg_table[] = {
ERR_TBL_IT(ESP_ERR_NVS_KEY_TOO_LONG), /* 4361 0x1109 Key name is too long */
# endif
# ifdef ESP_ERR_NVS_PAGE_FULL
ERR_TBL_IT(ESP_ERR_NVS_PAGE_FULL), /* 4362 0x110a Internal error; never returned by nvs_ API
ERR_TBL_IT(ESP_ERR_NVS_PAGE_FULL), /* 4362 0x110a Internal error; never returned by nvs API
functions */
# endif
# ifdef ESP_ERR_NVS_INVALID_STATE
@@ -157,6 +157,11 @@ static const esp_err_msg_t esp_err_msg_table[] = {
# ifdef ESP_ERR_NVS_PART_NOT_FOUND
ERR_TBL_IT(ESP_ERR_NVS_PART_NOT_FOUND), /* 4367 0x110f Partition with specified name is not found
in the partition table */
# endif
# ifdef ESP_ERR_NVS_NEW_VERSION_FOUND
ERR_TBL_IT(ESP_ERR_NVS_NEW_VERSION_FOUND), /* 4368 0x1110 NVS partition contains data in new format
and cannot be recognized by this version of
code */
# endif
// components/ulp/include/esp32/ulp.h
# ifdef ESP_ERR_ULP_BASE
@@ -473,7 +478,7 @@ const char *esp_err_to_name_r(esp_err_t code, char *buf, size_t buflen)
return buf;
}
snprintf(buf, buflen, "Unknown error %d", code);
snprintf(buf, buflen, "%s 0x%x(%d)", esp_unknown_msg, code, code);
return buf;
}

2
components/esp32/esp_err_to_name.c.in
View File

@@ -58,7 +58,7 @@ const char *esp_err_to_name_r(esp_err_t code, char *buf, size_t buflen)
return buf;
}
snprintf(buf, buflen, "Unknown error %d", code);
snprintf(buf, buflen, "%s 0x%x(%d)", esp_unknown_msg, code, code);
return buf;
}

51
components/esp32/esp_timer_esp32.c
View File

@@ -82,7 +82,18 @@
* ISR happens follow set_alarm, so change the ALARM_OVERFLOW_VAL to resolve this problem.
* Set it to 0xefffffffUL. The remain 0x10000000UL(about 3 second) is enough to handle ISR.
*/
#define ALARM_OVERFLOW_VAL 0xefffffffUL
#define DEFAULT_ALARM_OVERFLOW_VAL 0xefffffffUL
/* Provision to set lower overflow value for unit testing. Lowering the
* overflow value helps check for race conditions which occur near overflow
* moment.
*/
#ifndef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
#define ALARM_OVERFLOW_VAL DEFAULT_ALARM_OVERFLOW_VAL
#else
static uint32_t s_alarm_overflow_val = DEFAULT_ALARM_OVERFLOW_VAL;
#define ALARM_OVERFLOW_VAL (s_alarm_overflow_val)
#endif
static const char* TAG = "esp_timer_impl";
@@ -216,18 +227,6 @@ void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp)
// Adjust current time if overflow has happened
bool overflow = timer_overflow_happened();
uint64_t cur_count = REG_READ(FRC_TIMER_COUNT_REG(1));
uint32_t offset = s_timer_ticks_per_us * 2; //remain 2us for more safe
//If overflow is going to happen in 1us, let's wait until it happens,
//else we think it will not happen before new alarm set.
//And we should wait current timer count less than ALARM_OVERFLOW_VAL,
//maybe equals to 0.
if (cur_count + offset >= ALARM_OVERFLOW_VAL) {
do {
overflow = timer_overflow_happened();
cur_count = REG_READ(FRC_TIMER_COUNT_REG(1));
} while(!overflow || cur_count == ALARM_OVERFLOW_VAL);
}
if (overflow) {
assert(time_after_timebase_us > s_timer_us_per_overflow);
@@ -237,13 +236,17 @@ void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp)
// Calculate desired timer compare value (may exceed 2^32-1)
uint64_t compare_val = time_after_timebase_us * s_timer_ticks_per_us;
uint32_t alarm_reg_val = ALARM_OVERFLOW_VAL;
// Use calculated alarm value if it is less than 2^32-1
// Use calculated alarm value if it is less than ALARM_OVERFLOW_VAL.
// Note that if by the time we update ALARM_REG, COUNT_REG value is higher,
// interrupt will not happen for another ALARM_OVERFLOW_VAL timer ticks,
// so need to check if alarm value is too close in the future (e.g. <2 us away).
const uint32_t offset = s_timer_ticks_per_us * 2;
if (compare_val < ALARM_OVERFLOW_VAL) {
// If we by the time we update ALARM_REG, COUNT_REG value is higher,
// interrupt will not happen for another 2^32 timer ticks, so need to
// check if alarm value is too close in the future (e.g. <1 us away).
if (compare_val < cur_count + offset) {
compare_val = cur_count + offset;
if (compare_val > ALARM_OVERFLOW_VAL) {
compare_val = ALARM_OVERFLOW_VAL;
}
}
alarm_reg_val = (uint32_t) compare_val;
}
@@ -387,3 +390,17 @@ uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us()
{
return 50;
}
#ifdef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
uint32_t esp_timer_impl_get_overflow_val()
{
return s_alarm_overflow_val;
}
void esp_timer_impl_set_overflow_val(uint32_t overflow_val)
{
s_alarm_overflow_val = overflow_val;
/* update alarm value */
esp_timer_impl_update_apb_freq(esp_clk_apb_freq() / 1000000);
}
#endif // ESP_TIMER_DYNAMIC_OVERFLOW_VAL

8
components/esp32/fast_crypto_ops.c
View File

@@ -36,6 +36,8 @@
* we recommend, so as the API in WPS default and WPA2 default.
*/
const wpa_crypto_funcs_t g_wifi_default_wpa_crypto_funcs = {
.size = sizeof(wpa_crypto_funcs_t),
.version = ESP_WIFI_CRYPTO_VERSION,
.aes_wrap = (esp_aes_wrap_t)fast_aes_wrap,
.aes_unwrap = (esp_aes_unwrap_t)fast_aes_unwrap,
.hmac_sha256_vector = (esp_hmac_sha256_vector_t)fast_hmac_sha256_vector,
@@ -58,6 +60,8 @@ const wpa_crypto_funcs_t g_wifi_default_wpa_crypto_funcs = {
};
const wps_crypto_funcs_t g_wifi_default_wps_crypto_funcs = {
.size = sizeof(wps_crypto_funcs_t),
.version = ESP_WIFI_CRYPTO_VERSION,
.aes_128_encrypt = (esp_aes_128_encrypt_t)fast_aes_128_cbc_encrypt,
.aes_128_decrypt = (esp_aes_128_decrypt_t)fast_aes_128_cbc_decrypt,
.crypto_mod_exp = (esp_crypto_mod_exp_t)fast_crypto_mod_exp,
@@ -85,6 +89,8 @@ const wps_crypto_funcs_t g_wifi_default_wps_crypto_funcs = {
* crypto_hash_finish, so do crypto_cipher.
*/
const wpa2_crypto_funcs_t g_wifi_default_wpa2_crypto_funcs = {
.size = sizeof(wpa2_crypto_funcs_t),
.version = ESP_WIFI_CRYPTO_VERSION,
.crypto_hash_init = (esp_crypto_hash_init_t)fast_crypto_hash_init,
.crypto_hash_update = (esp_crypto_hash_update_t)fast_crypto_hash_update,
.crypto_hash_finish = (esp_crypto_hash_finish_t)fast_crypto_hash_finish,
@@ -100,6 +106,8 @@ const wpa2_crypto_funcs_t g_wifi_default_wpa2_crypto_funcs = {
.eap_peer_blob_deinit = (esp_eap_peer_blob_deinit_t)eap_peer_blob_deinit,
.eap_peer_config_init = (esp_eap_peer_config_init_t)eap_peer_config_init,
.eap_peer_config_deinit = (esp_eap_peer_config_deinit_t)eap_peer_config_deinit,
.eap_peer_register_methods = (esp_eap_peer_register_methods_t)eap_peer_register_methods,
.eap_peer_unregister_methods = (esp_eap_peer_unregister_methods_t)eap_peer_unregister_methods,
.eap_deinit_prev_method = (esp_eap_deinit_prev_method_t)eap_deinit_prev_method,
.eap_peer_get_eap_method = (esp_eap_peer_get_eap_method_t)eap_peer_get_eap_method,
.eap_sm_abort = (esp_eap_sm_abort_t)eap_sm_abort,

8
components/esp32/include/esp_attr.h
View File

@@ -47,4 +47,12 @@
// Forces read-only data into RTC slow memory. See "docs/deep-sleep-stub.rst"
#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
// Forces data into noinit section to avoid initialization after restart.
#define __NOINIT_ATTR __attribute__((section(".noinit")))
// Forces data into RTC slow memory of .noinit section.
// Any variable marked with this attribute will keep its value
// after restart or during a deep sleep / wake cycle.
#define RTC_NOINIT_ATTR __attribute__((section(".rtc_noinit")))
#endif /* __ESP_ATTR_H__ */

29
components/esp32/include/esp_err.h
View File

@@ -24,21 +24,20 @@ extern "C" {
typedef int32_t esp_err_t;
/* Definitions for error constants. */
#define ESP_OK 0 /*!< esp_err_t value indicating success (no error) */
#define ESP_FAIL -1 /*!< Generic esp_err_t code indicating failure */
#define ESP_OK 0
#define ESP_FAIL -1
#define ESP_ERR_NO_MEM 0x101
#define ESP_ERR_INVALID_ARG 0x102
#define ESP_ERR_INVALID_STATE 0x103
#define ESP_ERR_INVALID_SIZE 0x104
#define ESP_ERR_NOT_FOUND 0x105
#define ESP_ERR_NOT_SUPPORTED 0x106
#define ESP_ERR_TIMEOUT 0x107
#define ESP_ERR_INVALID_RESPONSE 0x108
#define ESP_ERR_INVALID_CRC 0x109
#define ESP_ERR_INVALID_VERSION 0x10A
#define ESP_ERR_INVALID_MAC 0x10B
#define ESP_ERR_NO_MEM 0x101 /*!< Out of memory */
#define ESP_ERR_INVALID_ARG 0x102 /*!< Invalid argument */
#define ESP_ERR_INVALID_STATE 0x103 /*!< Invalid state */
#define ESP_ERR_INVALID_SIZE 0x104 /*!< Invalid size */
#define ESP_ERR_NOT_FOUND 0x105 /*!< Requested resource not found */
#define ESP_ERR_NOT_SUPPORTED 0x106 /*!< Operation or feature not supported */
#define ESP_ERR_TIMEOUT 0x107 /*!< Operation timed out */
#define ESP_ERR_INVALID_RESPONSE 0x108 /*!< Received response was invalid */
#define ESP_ERR_INVALID_CRC 0x109 /*!< CRC or checksum was invalid */
#define ESP_ERR_INVALID_VERSION 0x10A /*!< Version was invalid */
#define ESP_ERR_INVALID_MAC 0x10B /*!< MAC address was invalid */
#define ESP_ERR_WIFI_BASE 0x3000 /*!< Starting number of WiFi error codes */
#define ESP_ERR_MESH_BASE 0x4000 /*!< Starting number of MESH error codes */
@@ -76,6 +75,7 @@ const char *esp_err_to_name(esp_err_t code);
*/
const char *esp_err_to_name_r(esp_err_t code, char *buf, size_t buflen);
/** @cond */
void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression) __attribute__((noreturn));
#ifndef __ASSERT_FUNC
@@ -88,6 +88,7 @@ void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const cha
#define __ASSERT_FUNC "??"
#endif
#endif
/** @endcond */
/**
* Macro which can be used to check the error code,

1
components/esp32/include/esp_flash_data_types.h
View File

@@ -21,7 +21,6 @@ extern "C"
{
#endif
#define ESP_PARTITION_TABLE_ADDR 0x8000
#define ESP_PARTITION_MAGIC 0x50AA
#define ESP_PARTITION_MAGIC_MD5 0xEBEB

12
components/esp32/include/esp_mesh.h
View File

@@ -936,7 +936,7 @@ bool esp_mesh_get_self_organized(void);
* be expected to find to replace the current one.
* If no desired root candidate, the vote will try a specified attempts(at least 10 times), if no better
* root candidate is found, keep the current one. If a better candidate is found, the new better one will
* send a root switch request to the current root, current root will respond with a root switch acknowledgement.
* send a root switch request to the current root, current root will respond with a root switch acknowledgment.
* After that, the new candidate will connect to the router to be a new root, the previous root will disconnect
* with the router and choose another parent instead.
* So far, root switch is completed with minimal disruption to the whole mesh network.
@@ -951,6 +951,8 @@ bool esp_mesh_get_self_organized(void);
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_QUEUE_FULL
* - ESP_ERR_MESH_DISCARD
* - ESP_FAIL
*/
esp_err_t esp_mesh_waive_root(const mesh_vote_t *vote, int reason);
@@ -1310,6 +1312,14 @@ esp_err_t esp_mesh_scan_get_ap_ie_len(int *len);
*/
esp_err_t esp_mesh_scan_get_ap_record(wifi_ap_record_t *ap_record, void *buffer);
/**
* @brief flush upstream packets pending in to_parent queue and to_parent_p2p queue
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_flush_upstream_packets(void);
#ifdef __cplusplus
}
#endif

110
components/esp32/include/esp_mesh_internal.h
View File

@@ -33,22 +33,31 @@ extern "C" {
* Structures
*******************************************************/
typedef struct {
int scan; /**< minimum scan times before being a root, default:10 */
int vote; /**< max vote times in self-healing, default:10000 */
int fail; /**< parent selection fail times, if the scan times reach this value,
will disconnect with associated children and join self-healing. default:60 */
int monitor_ie; /**< acceptable times of parent ie change before update self ie, default:3 */
int scan; /**< minimum scan times before being a root, default:10. */
int vote; /**< max vote times in self-healing, default:1000. */
int fail; /**< parent selection fail times. If the scan times reach this value,
device will disconnect with associated children and join self-healing, default:120. */
int monitor_ie; /**< acceptable times of parent networking IE change before update self networking IE, default:10. */
} mesh_attempts_t;
typedef struct {
int duration_ms; /* parent weak RSSI monitor duration, if the RSSI continues to be weak during this duration_ms,
will switch to a better parent */
int cnx_rssi; /* RSSI threshold for keeping a good connection with parent */
int select_rssi; /* RSSI threshold for parent selection, should be a value greater than switch_rssi */
int switch_rssi; /* RSSI threshold for action to reselect a better parent */
int duration_ms; /* parent weak RSSI monitor duration. If the RSSI with current parent is less than cnx_rssi continuously
within this duration_ms, device will search for a better parent. */
int cnx_rssi; /* RSSI threshold for keeping a good connection with parent.
If set a value greater than -120 dBm, device will arm a timer to monitor current RSSI at a period time of
duration_ms. */
int select_rssi; /* RSSI threshold for parent selection, should be a value greater than switch_rssi. */
int switch_rssi; /* RSSI threshold for parent switch. Device will disassociate current parent and switch to a new parent when
the RSSI with the new parent is greater than this set threshold. */
int backoff_rssi; /* RSSI threshold for connecting to the root */
} mesh_switch_parent_t;
typedef struct {
int high;
int medium;
int low;
} mesh_rssi_threshold_t;
/**
* @brief mesh networking IE
*/
@@ -58,8 +67,8 @@ typedef struct {
uint8_t len; /**< element length */
uint8_t oui[3]; /**< organization identifier */
/**< mesh networking IE content */
uint8_t type; /** mesh networking IE type */
uint8_t encryped : 1; /**< if mesh networking IE is encrypted */
uint8_t type; /** ESP defined IE type */
uint8_t encryped : 1; /**< whether mesh networking IE is encrypted */
uint8_t version : 7; /**< mesh networking IE version */
/**< content */
uint8_t mesh_type; /**< mesh device type */
@@ -74,13 +83,13 @@ typedef struct {
uint16_t self_cap; /**< self capacity */
uint16_t layer2_cap; /**< layer2 capacity */
uint16_t scan_ap_num; /**< the number of scanned APs */
int8_t rssi; /**< rssi of the parent */
int8_t router_rssi; /**< rssi of the router */
int8_t rssi; /**< RSSI of the parent */
int8_t router_rssi; /**< RSSI of the router */
uint8_t flag; /**< flag of networking */
uint8_t rc_addr[6]; /**< root address */
int8_t rc_rssi; /**< root rssi */
int8_t rc_rssi; /**< root RSSI */
uint8_t vote_addr[6]; /**< voter address */
int8_t vote_rssi; /**< vote rssi of the router */
int8_t vote_rssi; /**< vote RSSI of the router */
uint8_t vote_ttl; /**< vote ttl */
uint16_t votes; /**< votes */
uint16_t my_votes; /**< my votes */
@@ -115,9 +124,9 @@ esp_err_t esp_mesh_set_beacon_interval(int interval_ms);
esp_err_t esp_mesh_get_beacon_interval(int *interval_ms);
/**
* @brief set attempts for mesh self-organized networking
* @brief set attempts for mesh self-organized networking
*
* @param attempts
* @param attempts
*
* @return
* - ESP_OK
@@ -132,7 +141,7 @@ esp_err_t esp_mesh_set_attempts(mesh_attempts_t *attempts);
*
* @return
* - ESP_OK
* - ESP_FAIL
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_get_attempts(mesh_attempts_t *attempts);
@@ -143,7 +152,7 @@ esp_err_t esp_mesh_get_attempts(mesh_attempts_t *attempts);
*
* @return
* - ESP_OK
* - ESP_FAIL
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_set_switch_parent_paras(mesh_switch_parent_t *paras);
@@ -154,10 +163,46 @@ esp_err_t esp_mesh_set_switch_parent_paras(mesh_switch_parent_t *paras);
*
* @return
* - ESP_OK
* - ESP_FAIL
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_get_switch_parent_paras(mesh_switch_parent_t *paras);
/**
* @brief set RSSI threshold
* The default high RSSI threshold value is -78 dBm.
* The default medium RSSI threshold value is -82 dBm.
* The default low RSSI threshold value is -85 dBm.
*
* @param threshold RSSI threshold
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_set_rssi_threshold(const mesh_rssi_threshold_t *threshold);
/**
* @brief get RSSI threshold
* @param threshold RSSI threshold
*
* @return
* - ESP_OK
* - ESP_ERR_MESH_ARGUMENT
*/
esp_err_t esp_mesh_get_rssi_threshold(mesh_rssi_threshold_t *threshold);
/**
* @brief enable the minimum rate to 6Mbps
*
* @attention This API shall be called before WiFi start.
*
* @param is_6m enable or not
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_set_6m_rate(bool is_6m);
/**
* @brief print the number of txQ waiting
*
@@ -195,6 +240,29 @@ esp_err_t esp_mesh_set_passive_scan_time(int time_ms);
*/
int esp_mesh_get_passive_scan_time(void);
/**
* @brief set announce interval
* The default short interval is 500 milliseconds.
* The default long interval is 3000 milliseconds.
*
* @param short_ms shall be greater than the default value
* @param long_ms shall be greater than the default value
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_set_announce_interval(int short_ms, int long_ms);
/**
* @brief get announce interval
*
* @param short_ms short interval
* @param long_ms long interval
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_get_announce_interval(int *short_ms, int *long_ms);
#ifdef __cplusplus
}

8
components/esp32/include/esp_phy_init.h
View File

@@ -58,6 +58,7 @@ typedef enum{
MODEM_WIFI_STATION_MODULE, //!< Wi-Fi Station used
MODEM_WIFI_SOFTAP_MODULE, //!< Wi-Fi SoftAP used
MODEM_WIFI_SNIFFER_MODULE, //!< Wi-Fi Sniffer used
MODEM_WIFI_NULL_MODULE, //!< Wi-Fi Null mode used
MODEM_USER_MODULE, //!< User used
MODEM_MODULE_COUNT //!< Number of items
}modem_sleep_module_t;
@@ -73,7 +74,8 @@ typedef enum{
*/
#define MODEM_WIFI_MASK ((1<<MODEM_WIFI_STATION_MODULE) | \
(1<<MODEM_WIFI_SOFTAP_MODULE) | \
(1<<MODEM_WIFI_SNIFFER_MODULE))
(1<<MODEM_WIFI_SNIFFER_MODULE) | \
(1<<MODEM_WIFI_NULL_MODULE))
/**
* @brief Modules needing to call phy_rf_init
@@ -200,6 +202,10 @@ esp_err_t esp_modem_sleep_exit(modem_sleep_module_t module);
/**
* @brief Register module to make it be able to require to enter/exit modem sleep
* Although the module has no sleep function, as long as the module use RF,
* it must call esp_modem_sleep_regsiter. Otherwise, other modules with sleep
* function will disable RF without checking the module which doesn't call
* esp_modem_sleep_regsiter.
*/
esp_err_t esp_modem_sleep_register(modem_sleep_module_t module);

3
components/esp32/include/esp_sleep.h
View File

@@ -113,6 +113,9 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
* to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
* source is used.
*
* @note The FSM mode of the touch button should be configured
* as the timer trigger mode.
*
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if wakeup triggers conflict

14
components/esp32/include/esp_wifi.h
View File

@@ -428,24 +428,24 @@ esp_err_t esp_wifi_scan_get_ap_records(uint16_t *number, wifi_ap_record_t *ap_re
esp_err_t esp_wifi_sta_get_ap_info(wifi_ap_record_t *ap_info);
/**
* @brief Set current power save type
* @brief Set current WiFi power save type
*
* @attention Default power save type is WIFI_PS_NONE.
* @attention Default power save type is WIFI_PS_MIN_MODEM.
*
* @param type power save type
*
* @return ESP_ERR_NOT_SUPPORTED: not supported yet
* @return ESP_OK: succeed
*/
esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
/**
* @brief Get current power save type
* @brief Get current WiFi power save type
*
* @attention Default power save type is WIFI_PS_NONE.
* @attention Default power save type is WIFI_PS_MIN_MODEM.
*
* @param[out] type: store current power save type
*
* @return ESP_ERR_NOT_SUPPORTED: not supported yet
* @return ESP_OK: succeed
*/
esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
@@ -981,7 +981,7 @@ esp_err_t esp_wifi_80211_tx(wifi_interface_t ifx, const void *buffer, int len, b
* Each time a CSI data is received, the callback function will be called.
*
* @param ctx context argument, passed to esp_wifi_set_csi_rx_cb() when registering callback function.
* @param data CSI data received.
* @param data CSI data received. The memory that it points to will be deallocated after callback function returns.
*
*/
typedef void (* wifi_csi_cb_t)(void *ctx, wifi_csi_info_t *data);

12
components/esp32/include/esp_wifi_crypto_types.h
View File

@@ -27,6 +27,8 @@
extern "C" {
#endif
#define ESP_WIFI_CRYPTO_VERSION 0x00000001
/*
* Enumeration for hash operations.
* When WPA2 is connecting, this enum is used to
@@ -605,7 +607,7 @@ typedef void (*esp_uuid_gen_mac_addr_t)(const unsigned char *mac_addr, unsigned
* @brief free the message after finish DH
*
*/
typedef void * (*esp_dh5_free_t)(void *ctx);
typedef void (*esp_dh5_free_t)(void *ctx);
/**
* @brief Build WPS IE for (Re)Association Request
@@ -697,6 +699,8 @@ typedef int (*esp_wps_is_selected_pbc_registrar_t)(const void *msg, unsigned cha
* hardware.
*/
typedef struct {
uint32_t size;
uint32_t version;
esp_aes_wrap_t aes_wrap; /**< station connect function used when send EAPOL frame */
esp_aes_unwrap_t aes_unwrap; /**< station connect function used when decrypt key data */
esp_hmac_sha256_vector_t hmac_sha256_vector; /**< station connect function used when check MIC */
@@ -724,6 +728,8 @@ typedef struct {
* hardware.
*/
typedef struct{
uint32_t size;
uint32_t version;
esp_aes_128_encrypt_t aes_128_encrypt; /**< function used to process message when do WPS */
esp_aes_128_decrypt_t aes_128_decrypt; /**< function used to process message when do WPS */
esp_crypto_mod_exp_t crypto_mod_exp; /**< function used to calculate public key and private key */
@@ -750,6 +756,8 @@ typedef struct{
* hardware.
*/
typedef struct {
uint32_t size;
uint32_t version;
esp_crypto_hash_init_t crypto_hash_init; /**< function used to initialize a crypto_hash structure when use TLSV1 */
esp_crypto_hash_update_t crypto_hash_update; /**< function used to calculate hash data when use TLSV1 */
esp_crypto_hash_finish_t crypto_hash_finish; /**< function used to finish the hash calculate when use TLSV1 */
@@ -765,6 +773,8 @@ typedef struct {
esp_eap_peer_blob_deinit_t eap_peer_blob_deinit;
esp_eap_peer_config_init_t eap_peer_config_init;
esp_eap_peer_config_deinit_t eap_peer_config_deinit;
esp_eap_peer_register_methods_t eap_peer_register_methods;
esp_eap_peer_unregister_methods_t eap_peer_unregister_methods;
esp_eap_deinit_prev_method_t eap_deinit_prev_method;
esp_eap_peer_get_eap_method_t eap_peer_get_eap_method;
esp_eap_sm_abort_t eap_sm_abort;

22
components/esp32/include/esp_wifi_internal.h
View File

@@ -138,6 +138,28 @@ esp_err_t esp_wifi_internal_set_sta_ip(void);
*/
esp_err_t esp_wifi_internal_osi_funcs_md5_check(const char *md5);
/**
* @brief Check the MD5 values of the crypto types header files in IDF and WiFi library
*
* @attention 1. It is used for internal CI version check
*
* @return
* - ESP_OK : succeed
* - ESP_WIFI_INVALID_ARG : MD5 check fail
*/
esp_err_t esp_wifi_internal_crypto_funcs_md5_check(const char *md5);
/**
* @brief Check the git commit id of WiFi library
*
* @attention 1. It is used for internal CI WiFi library check
*
* @return
* - ESP_OK : succeed
* - ESP_FAIL : fail
*/
esp_err_t esp_wifi_internal_git_commit_id_check(void);
/**
* @brief Allocate a chunk of memory for WiFi driver
*

74
components/esp32/include/esp_wifi_types.h
View File

@@ -97,8 +97,8 @@ typedef enum {
typedef enum {
WIFI_SECOND_CHAN_NONE = 0, /**< the channel width is HT20 */
WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the second channel is above the primary channel */
WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the second channel is below the primary channel */
WIFI_SECOND_CHAN_ABOVE, /**< the channel width is HT40 and the secondary channel is above the primary channel */
WIFI_SECOND_CHAN_BELOW, /**< the channel width is HT40 and the secondary channel is below the primary channel */
} wifi_second_chan_t;
typedef enum {
@@ -155,7 +155,7 @@ typedef struct {
uint8_t bssid[6]; /**< MAC address of AP */
uint8_t ssid[33]; /**< SSID of AP */
uint8_t primary; /**< channel of AP */
wifi_second_chan_t second; /**< second channel of AP */
wifi_second_chan_t second; /**< secondary channel of AP */
int8_t rssi; /**< signal strength of AP */
wifi_auth_mode_t authmode; /**< authmode of AP */
wifi_cipher_type_t pairwise_cipher; /**< pairwise cipher of AP */
@@ -186,6 +186,8 @@ typedef struct {
wifi_auth_mode_t authmode; /**< The weakest authmode to accept in the fast scan mode */
}wifi_fast_scan_threshold_t;
typedef wifi_fast_scan_threshold_t wifi_scan_threshold_t; /**< wifi_fast_scan_threshold_t only used in fast scan mode once, now it enabled in all channel scan, the wifi_fast_scan_threshold_t will be remove in version 4.0 */
typedef enum {
WIFI_PS_NONE, /**< No power save */
WIFI_PS_MIN_MODEM, /**< Minimum modem power saving. In this mode, station wakes up to receive beacon every DTIM period */
@@ -226,7 +228,7 @@ typedef struct {
uint8_t channel; /**< channel of target AP. Set to 1~13 to scan starting from the specified channel before connecting to AP. If the channel of AP is unknown, set it to 0.*/
uint16_t listen_interval; /**< Listen interval for ESP32 station to receive beacon when WIFI_PS_MAX_MODEM is set. Units: AP beacon intervals. Defaults to 3 if set to 0. */
wifi_sort_method_t sort_method; /**< sort the connect AP in the list by rssi or security mode */
wifi_fast_scan_threshold_t threshold; /**< When scan_method is set to WIFI_FAST_SCAN, only APs which have an auth mode that is more secure than the selected auth mode and a signal stronger than the minimum RSSI will be used. */
wifi_scan_threshold_t threshold; /**< When scan_method is set, only APs which have an auth mode that is more secure than the selected auth mode and a signal stronger than the minimum RSSI will be used. */
} wifi_sta_config_t;
/** @brief Configuration data for ESP32 AP or STA.
@@ -304,33 +306,33 @@ typedef struct {
/** @brief Received packet radio metadata header, this is the common header at the beginning of all promiscuous mode RX callback buffers */
typedef struct {
signed rssi:8; /**< signal intensity of packet */
unsigned rate:5; /**< data rate */
unsigned :1; /**< reserve */
unsigned sig_mode:2; /**< 0:is not 11n packet; 1:is 11n packet */
unsigned :16; /**< reserve */
unsigned mcs:7; /**< if is 11n packet, shows the modulation(range from 0 to 76) */
unsigned cwb:1; /**< if is 11n packet, shows if is HT40 packet or not */
unsigned :16; /**< reserve */
unsigned smoothing:1; /**< reserve */
unsigned not_sounding:1; /**< reserve */
unsigned :1; /**< reserve */
unsigned aggregation:1; /**< Aggregation */
unsigned stbc:2; /**< STBC */
unsigned fec_coding:1; /**< Flag is set for 11n packets which are LDPC */
unsigned sgi:1; /**< SGI */
signed noise_floor:8; /**< noise floor */
unsigned ampdu_cnt:8; /**< ampdu cnt */
unsigned channel:4; /**< which primary channel this packet in */
unsigned second_channel:4;/**< which second channel this packet in */
unsigned :8; /**< reserve */
unsigned timestamp:32; /**< timestamp, unit: microsecond */
unsigned :32; /**< reserve */
unsigned :31; /**< reserve */
unsigned ant:1; /**< antenna number from which this packet is received */
unsigned sig_len:12; /**< length of packet */
unsigned :12; /**< reserve */
unsigned rx_state:8; /**< rx state */
signed rssi:8; /**< Received Signal Strength Indicator(RSSI) of packet. unit: dBm */
unsigned rate:5; /**< PHY rate encoding of the packet. Only valid for non HT(11bg) packet */
unsigned :1; /**< reserve */
unsigned sig_mode:2; /**< 0: non HT(11bg) packet; 1: HT(11n) packet; 3: VHT(11ac) packet */
unsigned :16; /**< reserve */
unsigned mcs:7; /**< Modulation Coding Scheme. If is HT(11n) packet, shows the modulation, range from 0 to 76(MSC0 ~ MCS76) */
unsigned cwb:1; /**< Channel Bandwidth of the packet. 0: 20MHz; 1: 40MHz */
unsigned :16; /**< reserve */
unsigned smoothing:1; /**< reserve */
unsigned not_sounding:1; /**< reserve */
unsigned :1; /**< reserve */
unsigned aggregation:1; /**< Aggregation. 0: MPDU packet; 1: AMPDU packet */
unsigned stbc:2; /**< Space Time Block Code(STBC). 0: non STBC packet; 1: STBC packet */
unsigned fec_coding:1; /**< Flag is set for 11n packets which are LDPC */
unsigned sgi:1; /**< Short Guide Interval(SGI). 0: Long GI; 1: Short GI */
signed noise_floor:8; /**< noise floor of Radio Frequency Module(RF). unit: 0.25dBm*/
unsigned ampdu_cnt:8; /**< ampdu cnt */
unsigned channel:4; /**< primary channel on which this packet is received */
unsigned secondary_channel:4; /**< secondary channel on which this packet is received. 0: none; 1: above; 2: below */
unsigned :8; /**< reserve */
unsigned timestamp:32; /**< timestamp. The local time when this packet is received. It is precise only if modem sleep or light sleep is not enabled. unit: microsecond */
unsigned :32; /**< reserve */
unsigned :31; /**< reserve */
unsigned ant:1; /**< antenna number from which this packet is received. 0: WiFi antenna 0; 1: WiFi antenna 1 */
unsigned sig_len:12; /**< length of packet including Frame Check Sequence(FCS) */
unsigned :12; /**< reserve */
unsigned rx_state:8; /**< state of the packet. 0: no error; others: error numbers which are not public */
} wifi_pkt_rx_ctrl_t;
/** @brief Payload passed to 'buf' parameter of promiscuous mode RX callback.
@@ -387,10 +389,10 @@ typedef struct {
*
*/
typedef struct {
bool lltf_en; /**< enable to receive legacy long training field(lltf) data */
bool htltf_en; /**< enable to receive HT long training field(htltf) data */
bool stbcltf2_en; /**< enable to receive space time block code long training field(stbcltf2) data */
bool manu_scale; /**< manually scale the CSI data by left shifting or automatically scale the CSI data. If set true, please set the shift bits. false: automatically. true: manually */
bool lltf_en; /**< enable to receive legacy long training field(lltf) data. Default enabled */
bool htltf_en; /**< enable to receive HT long training field(htltf) data. Default enabled */
bool stbc_htltf2_en; /**< enable to receive space time block code HT long training field(stbc-htltf2) data. Default enabled */
bool manu_scale; /**< manually scale the CSI data by left shifting or automatically scale the CSI data. If set true, please set the shift bits. false: automatically. true: manually. Default false */
uint8_t shift; /**< manually left shift bits of the scale of the CSI data. The range of the left shift bits is 0~15 */
} wifi_csi_config_t;
@@ -402,7 +404,7 @@ typedef struct {
wifi_pkt_rx_ctrl_t rx_ctrl;/**< received packet radio metadata header of the CSI data */
uint8_t mac[6]; /**< source MAC address of the CSI data */
bool last_word_invalid; /**< last four bytes of the CSI data is invalid or not */
uint8_t *buf; /**< buffer of CSI data */
int8_t *buf; /**< buffer of CSI data */
uint16_t len; /**< length of CSI data */
} wifi_csi_info_t;

2
components/esp32/include/rom/gpio.h
View File

@@ -20,6 +20,7 @@
#include "esp_attr.h"
#include "soc/gpio_reg.h"
#include "soc/gpio_pins.h"
#ifdef __cplusplus
extern "C" {
@@ -35,7 +36,6 @@ extern "C" {
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_PIN_COUNT 40
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)

28
components/esp32/include/xtensa/board.h
View File

@@ -1,28 +0,0 @@
/* This header is supposed to be obtained from <board>/xtensa/board.h
using a -I directive passed to the compiler. */
#error "Unspecified board. Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/<BOARD> (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)"
/*
* Copyright (c) 2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

1758
components/esp32/include/xtensa/c6x-compat.h
View File

File diff suppressed because it is too large Load Diff

4
components/esp32/include/xtensa/core-macros.h
View File

@@ -335,7 +335,7 @@
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
} while(0)
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
__asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
__asm__ __volatile__("rsr.interrupt %0" : "=a"(__interrupt)); \
__interrupt; })
# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
@@ -344,7 +344,7 @@
__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_GET_CCOUNT() ({ int __ccount; \
__asm__("rsr.ccount %0" : "=a"(__ccount)); \
__asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
__ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \

93
components/esp32/include/xtensa/debugfs.h
View File

@@ -1,93 +0,0 @@
/* Xtensa Debug-FileSystem definitions */
/*
* Copyright (c) 2005-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __DEBUGFS_H__
#define __DEBUGFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <unistd.h>
#include <fcntl.h>
#include <stdlib.h>
int xt_dbfs_open(const char *pathname, int flags, mode_t mode);
int xt_dbfs_ftruncate(int fd, off_t length);
int xt_dbfs_truncate(const char * filename, off_t length);
int xt_dbfs_creat(const char *pathname, mode_t mode);
int xt_dbfs_errno(void);
int xt_dbfs_lseek(int fd, off_t offset, int whence);
ssize_t xt_dbfs_write(int fd, const void * buf, size_t bytes);
ssize_t xt_dbfs_open_append_close(const char * filename, int align,
const void * buf, size_t bytes);
ssize_t xt_dbfs_read(int fd, void * buf, size_t bytes);
int xt_dbfs_close(int fd);
int xt_dbfs_unlink(const char *pathname);
/* By default, this function is a wrapper around sbrk, and follows
sbrk semantics:
On success, it returns increment bytes of memory allocated from
system memory.
On failure, it returns 0xFFFFFFFF
If you want to use a method of allocating memory other than sbrk,
implement xt_dbfs_sbrk in your own sources, and the linker will
automatically use that copy.
*/
void * xt_dbfs_sbrk(int increment);
#ifdef REPLACE_FS_WITH_DBFS
#define open xt_dbfs_open
#define close xt_dbfs_close
#define creat xt_dbfs_creat
#define lseek xt_dbfs_lseek
#define write xt_dbfs_write
#define read xt_dbfs_read
#define close xt_dbfs_close
#define unlink xt_dbfs_unlink
#define rmdir NOT_IMPLEMENTED_IN_DBFS
#define opendir NOT_IMPLEMENTED_IN_DBFS
#define closedir NOT_IMPLEMENTED_IN_DBFS
#define dirfs NOT_IMPLEMENTED_IN_DBFS
#define readdir NOT_IMPLEMENTED_IN_DBFS
#define scandir NOT_IMPLEMENTED_IN_DBFS
#define seekdir NOT_IMPLEMENTED_IN_DBFS
#define telldir NOT_IMPLEMENTED_IN_DBFS
#define fcntl NOT_IMPLEMENTED_IN_DBFS
#define dup2 NOT_IMPLEMENTED_IN_DBFS
#define dup NOT_IMPLEMENTED_IN_DBFS
#define flock NOT_IMPLEMENTED_IN_DBFS
#define lockf NOT_IMPLEMENTED_IN_DBFS
#define link NOT_IMPLEMENTED_IN_DBFS
#define stat NOT_IMPLEMENTED_IN_DBFS
#define fstat NOT_IMPLEMENTED_IN_DBFS
#define lstat NOT_IMPLEMENTED_IN_DBFS
#define chmod NOT_IMPLEMENTED_IN_DBFS
#define fchmod NOT_IMPLEMENTED_IN_DBFS
#define chmown NOT_IMPLEMENTED_IN_DBFS
#define lchown NOT_IMPLEMENTED_IN_DBFS
#define fchown NOT_IMPLEMENTED_IN_DBFS
#endif
#ifdef __cplusplus
}
#endif
#endif

45
components/esp32/include/xtensa/feedback.h
View File

@@ -1,45 +0,0 @@
/*
* Copyright (c) 2013 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __XT_FEEDBACK_INCLUDED__
#define __XT_FEEDBACK_INCLUDED__
#ifdef __cplusplus
extern "C" {
#endif
/* xt_feedback_save_and_reset
Save and reset the accumulated feedback data.
*/
extern void xt_feedback_save_and_reset(void);
/* xt_feedback_enable
Turn on feedback accumulation. Ordinarily, feedback accumulation is on
by default. If you turn it off using xt_feedback_disable, You can turn
it on again via this function.
*/
extern void xt_feedback_enable (void);
/* xt_feedback_disable
Turn off feedback accumulation. If you don't want to gather feedback for a
portion of your code, use this function and then xt_feedback_enable when
you want to start again.
*/
extern void xt_feedback_disable (void);
#ifdef __cplusplus
}
#endif
#endif /* __XT_FEEDBACK_INCLUDED__ */

80
components/esp32/include/xtensa/gdbio.h
View File

@@ -1,80 +0,0 @@
/* Xtensa Debug-FileSystem definitions
*
* Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __DEBUGFS_H__
#define __DEBUGFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <unistd.h>
#include <fcntl.h>
#include <stdlib.h>
#include <errno.h>
int _gdbio_open_r(void * ptr, const char *pathname, int flags, mode_t mode);
int _gdbio_creat_r(void * ptr, const char *pathname, mode_t mode);
int _gdbio_lseek_r(void * ptr, int fd, off_t offset, int whence);
ssize_t _gdbio_write_r(void * ptr, int fd, const void * buf, size_t bytes);
ssize_t _gdbio_read_r(void * ptr, int fd, void * buf, size_t bytes);
int _gdbio_close_r(void * ptr, int fd);
int _gdbio_unlink_r(void * ptr, const char * pathname);
static inline
int gdbio_open(const char *pathname, int flags, mode_t mode) {
return _gdbio_open_r(&errno, pathname, flags, mode);
}
static inline int
gdbio_creat(const char *pathname, mode_t mode) {
return _gdbio_open_r(&errno, pathname, O_CREAT|O_WRONLY|O_TRUNC, mode);
}
static inline int
gdbio_errno(void) {
return errno;
}
static inline int
gdbio_lseek(int fd, off_t offset, int whence) {
return _gdbio_lseek_r(&errno, fd, offset, whence);
}
static inline
ssize_t gdbio_write(int fd, const void * buf, size_t bytes) {
return _gdbio_write_r(&errno, fd, buf, bytes);
}
static inline
ssize_t gdbio_read(int fd, void * buf, size_t bytes) {
return _gdbio_read_r(&errno, fd, buf, bytes);
}
static inline int
gdbio_close(int fd) {
return _gdbio_close_r(&errno, fd);
}
static inline int
gdbio_unlink(const char * pathname) {
return _gdbio_unlink_r(&errno, pathname);
}
#ifdef REPLACE_FS_WITH_GDBIO
#define open gdbio_open
#define close gdbio_close
#define creat gdbio_creat
#define lseek gdbio_lseek
#define write gdbio_write
#define read gdbio_read
#define close gdbio_close
#define unlink gdbio_unlink
#endif
#ifdef __cplusplus
}
#endif
#endif

99
components/esp32/include/xtensa/jtag-xtensa.h
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/* Copyright (c) 2011-2012 Tensilica Inc. ALL RIGHTS RESERVED.
// These coded instructions, statements, and computer programs are the
// copyrighted works and confidential proprietary information of Tensilica Inc.
// They may not be modified, copied, reproduced, distributed, or disclosed to
// third parties in any manner, medium, or form, in whole or in part, without
// the prior written consent of Tensilica Inc.
*/
#ifndef _JTAG_XTENSA_H_
#define _JTAG_XTENSA_H_
/* ---------------- JTAG registers ------------------ */
/* -- ER and later JTAG registers */
typedef enum {
regIR,
regBypass,
regNAR,
regNDR,
regIdcode,
regPWRCTL,
regPWRSTAT,
regJtagMAX,
} xtensaJtagReg;
/* -- pre-ER JTAG registers */
typedef enum {
regOldIR,
regOldBypass,
regOldDIRW,
regOldDIR,
regOldDDR,
regOldDOSR,
regOldESR,
regOldDCR,
regOldTraxNDR,
regOldTraxNAR,
regOldMAX
} xtensaOldJtagReg;
/* ---------------- JTAG Instructions ------------------ */
/* -- pre-ER JTAG instructions */
typedef enum {
ji_EnableOCD = 0x11,
ji_DebugInt,
ji_RetDebugInt, // TBD: remove
ji_DisRetOCD, // TBD: remove
ji_ExecuteDI,
ji_LoadDI,
ji_ScanDDR,
ji_ReadDOSR,
ji_ScanDCR,
ji_LoadWDI,
ji_TRAX = 0x1c,
ji_BYPASS = 0x1f,
} xtensaJtagInstruction;
typedef enum {
OCDNormalMode,
OCDRunMode,
OCDHaltMode,
OCDStepMode
} xtensaMode;
typedef struct {
xtensaMode mode;
int DRsel;
XTMP_core core;
XTMP_tap tap;
int core_num;
jtagReg_t *jtagRegs;
void *dap; // used for ARM DAP only
bool isBig;
int dir_array_option; // used by pre-ER devices only
// for testing, below - FIXME - delete later
int ocdReg;
unsigned int wr_data;
XTMP_event start_OCD_trans;
bool data_cycle;
bool data_pending;
} coreSlaveData_t;
enum OCD_ACCESS_TYPE{
NEXUS_ACCESS,
CS_ACCESS,
};
// pre-ER Xtensa initializiation
EXTERN XTMP_deviceStatus
XTMP_jtagCoreSlaveEX(XTMP_component component, XTMP_jtagSlave slave, void* mydata);
extern char *OCDrd;
extern char *OCDwr;
#endif

62
components/esp32/include/xtensa/lcd-splc780d-4bitmode-board.h
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/*******************************************************************************
Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-splc780d-4bitmode-board.h Board-specific LCD info for these boards:
Avnet AV110 (XT-AV110)
Xilinx ML605 (XT-ML605)
Xilinx KC705 (XT-KC705)
Interface between board-independent driver and board-specific header.
This is used by a board-independent SPLC780D LCD controller (4 bit mode)
driver to obtain board-specific information about LCD displays on the board,
such as the controller register base address and spacing (a function of how
the address lines are connected on the board) and length of the visible window
of the display (a function of the LCD panel the controller drives).
The driver doesnot refer directly to the board-specific header, which therefore is not
constrained to use macro names consistent with other boards.
!! Must not contain any board-specific macro names (only controller specific) !!
Included at compile-time via an include path specific to the board.
The listed boards contain a single MYTech MOC-16216B-B display driven by
a Sunplus SPLC870D controller.
*******************************************************************************/
#ifndef _LCD_SPLC780D_4BIT_BOARD_H
#define _LCD_SPLC780D_4BIT_BOARD_H
#include <xtensa/board.h> /* Board info */
/* Base address of the controller's registers. */
#ifdef SPLC780D_4BIT_VADDR
#define SPLC780D_4BIT_REGBASE SPLC780D_4BIT_VADDR
#endif
/*
The controller's registers are connected at word addresses on these boards.
Each byte-wide register appears as the least-significant-byte (LSB) of the
word regardless of the endianness of the processor (so if using word accesses
then endianness doesn't matter).
*/
#define SPLC780D_4BIT_REGSPACING 4
typedef unsigned splc780d_4bit_reg_t;
/* Include generic information shared by all boards that use this device. */
#include <xtensa/lcd-splc780d-4bitmode.h>
/* Display limits of the LCD panel. */
#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */
#endif /* _LCD_SPLC780D_4BIT_BOARD_H */

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components/esp32/include/xtensa/lcd-splc780d-4bitmode.h
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/*******************************************************************************
Copyright (c) 2009-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-SPLC780D-4bitmode.h Generic definitions for Sunplus SPLC780D LCD Controller
operating in 4 bit mode.
This is used by board-support-packages with one or more LCD displays that use
a SPLC780D controller in 4 bit mode. A BSP provides a base address for each
instance of an SPLC780D LCD controller on the board.
Note that LCD display operation is almost totally independent of the LCD
display, depending almost entirely on the controller. However the display
may limit the number of characters of the controller's RAM buffer that are
actually visible at one time. The length of the display's visible window
is not specifified in this controller-specific header, but comes to the
driver from the board-specific "display.h" header.
*******************************************************************************/
#ifndef _LCD_SPLC780D_4BIT_H_
#define _LCD_SPLC780D_4BIT_H_
/* Offsets to controller registers from base. */
#define SPLC780D_4BIT_INST 0
#define SPLC780D_4BIT_DATA (SPLC780D_4BIT_INST + SPLC780D_4BIT_REGSPACING)
#define SPLC780D_4BIT_INST_INIT1 0xFF /* First command in
init sequence */
#define SPLC780D_4BIT_INST_INIT2 0x30 /* Second command in
init sequence,
issued 3 times */
#define SPLC780D_4BIT_INST_INIT3 0x20 /* Third and last command
in init sequence */
#define SPLC780D_4BIT_INST_CLEAR 0x01 /* clear (blank) display) */
#define SPLC780D_4BIT_INST_SET_MODE 0x28 /* Set LCD mode. Supported
setting is 4 bit data
length, 2 lines, 5*8 */
#define SPLC780D_4BIT_INST_DSPLY_ON 0x0C /* Set Display ON */
#define SPLC780D_4BIT_INST_CRSR_INC 0x06 /* Set cursor moving direction
as increment */
#define SPLC780D_4BIT_LINET_ADDR 0x80 /* clear (blank) display) */
#define SPLC780D_4BIT_LINEB_ADDR 0xC0 /* clear (blank) display) */
#ifndef __ASSEMBLER__
/* C interface to controller registers. */
struct splc780d_4bit_s {
splc780d_4bit_reg_t inst; /* instruction register */
splc780d_4bit_reg_t data; /* data register */
};
typedef volatile struct splc780d_4bit_s splc780d_4bit_t;
/*
Prototypes of high level driver functions.
*/
/* Write an instruction byte to LCD, result in two back to back writes since the
* LCD is hooked up in 4 bit mode*/
extern void lcd_write_inst_byte(splc780d_4bit_t *lcd, unsigned char inst);
/* Write a data byte to LCD, result in two back to back writes since the
* LCD is hooked up in 4 bit mode*/
extern void lcd_write_data_byte(splc780d_4bit_t *lcd, unsigned char data);
/*
Initialize the display with default settings.
*/
extern void splc780d_4bit_init_default(splc780d_4bit_t *lcd);
/*
Write a single character at a given position (chars from left, starting at 0).
Wait long enough afterward for the controller to be ready for more input.
Positions beyond the end of the display are ignored.
*/
extern void splc780d_4bit_write_char(splc780d_4bit_t *lcd, unsigned pos, const char c);
/*
Write a string to the display starting at the left (position 0).
Blank-pad to or truncate at the end of the display (overwrites any previous
string so don't need to blank the display first).
Wait long enough after each char for the controller to be ready for more input.
*/
extern void splc780d_4bit_write_string(splc780d_4bit_t *lcd, const char *s);
/*
Blank (clear) the entire display.
Wait long enough afterward for the controller to be ready for more input.
*/
extern void splc780d_4bit_blank(splc780d_4bit_t *lcd);
#endif /* __ASSEMBLER__ */
#endif /* _LCD_SPLC780D_4BIT_H_ */

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components/esp32/include/xtensa/lcd-splc780d.h
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/*******************************************************************************
Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-SPLC780D.h Generic definitions for Sunplus SPLC780D LCD Controller
This is used by board-support-packages with one or more LCD displays that use
a SPLC780D controller. A BSP provides a base address for each instance of an
SPLC780D LCD controller on the board.
Note that LCD display operation is almost totally independent of the LCD
display, depending almost entirely on the controller. However the display
may limit the number of characters of the controller's RAM buffer that are
actually visible at one time. The length of the display's visible window
is not specifified in this controller-specific header, but comes to the
driver from the board-specific "display.h" header.
*******************************************************************************/
#ifndef _LCD_SPLC780D_H_
#define _LCD_SPLC780D_H_
/* Offsets to controller registers from base. */
#define SPLC780D_INST 0
#define SPLC780D_DATA (SPLC780D_INST + SPLC780D_REGSPACING)
/*
Bit fields and their values in the instruction register.
These fields are NOT orthogonal - they overlap!
Thus only one field may be written at a time, determined by the
most-significant 1 bit in the pattern (the field selector).
All less significant bits are part of the value of the selected field.
The fields and their values are grouped together to emphasize this format.
Field selector macro names end in '_' (implying something more needs
to be ORed) and the value macros are indented. The pattern written to a
bitfield is a bitwise OR of a field selector and one or more values, eg.
(SPLC780D_INST_ON_ | SPLC780D_INST_ON_DISPLAY | SPLC780D_INST_ON_CURSOR)
A single bit field (eg. SPCL780D_INST_HOME) need not have a value.
NOTE: Controller requires a software delay after writing to the control
or data registers. For the data register it is 38us. For the control
register it is 38us for most bit fields, with the following exceptions:
SPLC780D_FUNC_ 100us.
SPLC780D_INST_CLEAR, SPLC780D_INST_HOME 1520us.
For more details and reset timing, see the SUNPLUS SPLC780D data sheet.
*/
#define SPLC780D_INST_CLEAR_ 0x1 /* clear (blank) display) */
#define SPLC780D_INST_HOME_ 0x2 /* home cursor and shift pos */
#define SPLC780D_INST_ENTRY_ 0x4 /* combine *ENTRY_* flags below */
#define SPLC780D_INST_ENTRY_SHIFT 0x1 /* display shift on entry / not */
#define SPLC780D_INST_ENTRY_INCR 0x2 /* cursor incr / decr */
#define SPLC780D_INST_ENTRY_DECR 0 /* cursor incr / decr */
#define SPLC780D_INST_ON_ 0x8 /* combine *ON_* flags below */
#define SPLC780D_INST_ON_DISPLAY 0x4 /* display on / off */
#define SPLC780D_INST_ON_CURSOR 0x2 /* cursor on / off */
#define SPLC780D_INST_ON_BLINK 0x1 /* blink on / off */
#define SPLC780D_INST_SHIFT_ 0x10 /* combine *SHIFT_* flags below */
#define SPLC780D_INST_SHIFT_DISP 0x8 /* shift display / move cursor */
#define SPLC780D_INST_SHIFT_CURS 0 /* shift display / move cursor */
#define SPLC780D_INST_SHIFT_RIGHT 0x4 /* shift right / left */
#define SPLC780D_INST_SHIFT_LEFT 0 /* shift right / left */
#define SPLC780D_INST_FUNC_ 0x20 /* combine *FUNC_* flags below */
#define SPLC780D_INST_FUNC_8BIT 0x10 /* data length 8 bit / 4 bit */
#define SPLC780D_INST_FUNC_4BIT 0 /* data length 8 bit / 4 bit */
#define SPLC780D_INST_FUNC_2LINE 0x08 /* display lines 2 / 1 */
#define SPLC780D_INST_FUNC_1LINE 0 /* display lines 2 / 1 */
#define SPLC780D_INST_FUNC_F5x10 0x04 /* character font 5x10 / 5x8 */
#define SPLC780D_INST_FUNC_F5x8 0 /* character font 5x10 / 5x8 */
/* font must be 5x8 for 2 lines */
#define SPLC780D_INST_CGEN_ 0x40 /* set char generator address */
#define SPLC780D_INST_CGEN_ADDR 0x3F /* to address in this field */
#define SPLC780D_INST_DRAM_ 0x80 /* set display data RAM address */
#define SPLC780D_INST_DRAM_ADDR 0x7F /* to address in this field */
#define SPLC780D_INST_DRAM_LINE2 0x40 /* address offset to line 2 */
/* Controller limits */
#define SPLC780D_RAMLEN_1LINE 0x50 /* length of line in RAM (1 line) */
#define SPLC780D_RAMLEN_2LINE 0x28 /* length of line in RAM (2 line) */
#ifndef __ASSEMBLER__
/* C interface to controller registers. */
struct splc780d_s {
splc780d_reg_t inst; /* instruction register */
splc780d_reg_t data; /* data register */
};
typedef volatile struct splc780d_s splc780d_t;
/*
Prototypes of high level driver functions.
*/
/*
Initialize the display with the FUNC_, ENTRY_ and ON_ fields as specified in
terms of the values above. The splc780d_init_default() macro is an example.
*/
extern void splc780d_init(splc780d_t *lcd,
unsigned func, unsigned entry, unsigned on);
/*
Initialize the display to default mode: 8-bit interface, 2 line, 5x8 font,
increment cursor on entry, display on (cursor and blinking off).
*/
#define splc780d_init_default(lcd) \
splc780d_init( lcd, \
SPLC780D_INST_FUNC_8BIT \
| SPLC780D_INST_FUNC_2LINE \
| SPLC780D_INST_FUNC_F5x8, \
SPLC780D_INST_ENTRY_INCR, \
SPLC780D_INST_ON_DISPLAY \
)
/*
Write a single character at a given position (chars from left, starting at 0).
Wait long enough afterward for the controller to be ready for more input.
Positions beyond the end of the display are ignored.
*/
extern void splc780d_write_char(splc780d_t *lcd, unsigned pos, const char c);
/*
Write a string to the display starting at the left (position 0).
Blank-pad to or truncate at the end of the display (overwrites any previous
string so don't need to blank the display first).
Wait long enough after each char for the controller to be ready for more input.
*/
extern void splc780d_write_string(splc780d_t *lcd, const char *s);
/*
Blank (clear) the entire display.
Wait long enough afterward for the controller to be ready for more input.
*/
extern void splc780d_blank(splc780d_t *lcd);
#endif /* __ASSEMBLER__ */
#endif /* _LCD_SPLC780D_H_ */

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components/esp32/include/xtensa/overlay.h
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// overlay.h -- Overlay manager header file
// $Id$
// Copyright (c) 2013 Tensilica Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef OVERLAY_H
#define OVERLAY_H
#include <xtensa/xtruntime.h>
#ifdef __cplusplus
extern "C" {
#endif
// Define this to turn off overlay support
#ifdef XT_DISABLE_OVERLAYS
#define OVERLAY(n)
#define DECLARE_OVERLAY(n)
#define xt_overlay_map(ov_id)
#define xt_overlay_map_async(ov_id) 0
#define xt_overlay_map_in_progress() 0
#define xt_overlay_get_id() 0
#define xt_overlay_get_state(pc) 0
#define xt_overlay_check_map(pc,ps,ovstate,sp) 0
#else
// Shorthand for convenience and portability.
#define OVERLAY(n) __attribute__((overlay(n)))
// Structure of the overlay table required by gdb and the overlay
// manager. Should not be accessed by user code unless overriding
// the load process.
struct ovly_table {
void * vma; // The overlay's mapped address.
unsigned int size; // The size of the overlay, in bytes.
void * lma; // The overlay's load address.
unsigned int mapped; // Non-zero if overlay is currently mapped; zero otherwise.
};
// Constructed by the linker. Required for gdb and for the overlay
// manager. Should not be accessed by user code unless overriding
// the load process.
extern struct ovly_table _ovly_table[];
// Functions.
void xt_overlay_map(int ov_id);
int xt_overlay_map_async(int ov_id);
int xt_overlay_map_in_progress(void);
unsigned int xt_overlay_get_state(unsigned int pc);
unsigned int xt_overlay_check_map(unsigned int * pc, unsigned int * ps,
unsigned int ovstate, unsigned int sp);
int xt_overlay_start_map(void * dst, void * src, unsigned int len, int ov_id);
int xt_overlay_is_mapping(int ov_id);
void xt_overlay_fatal_error(int ov_id);
// Returns the current overlay ID. If no overlay is mapped or an overlay
// is in the middle of being mapped, returns -1. Inlined to avoid calling
// out of overlay (wastes cycles, can end up reading wrong ID on interrupt
// activity).
//
static inline int xt_overlay_get_id(void)
{
#pragma always_inline
extern short _mapping_id;
extern short _ovly_id;
int ret;
unsigned int flags = XTOS_SET_INTLEVEL(15);
if (_mapping_id >= 0) {
ret = -1;
}
else {
ret = _ovly_id;
}
XTOS_RESTORE_INTLEVEL(flags);
return ret;
}
// The following macros are used to declare numbered overlays and generate
// the corresponding call stubs. Use as follows:
//
// DECLARE_OVERLAY(n)
//
// See documentation for more details.
//#include <xtensa/config/core-isa.h>
// At this time overlays are not supported without windowing.
#if defined(__XTENSA_WINDOWED_ABI__)
#define xstr(x) str(x)
#define str(x) #x
// At entry, register a8 holds the return address and a9 holds the target
// function address. This stub saves a8 on the stack at (SP - 20) which
// is the only location that is safe for us to use. Then it allocates 32
// bytes on the stack for working storage, loads the overlay number into
// a8, and jumps to the common handler. The common handler will make sure
// that the called function is loaded into memory before calling it.
// NOTE: we are using the stack area normally reserved for nested functions.
// This means nested functions cannot be used when overlays are in use.
#define CALL_IN(num) \
asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
".global _overlay_call_in_" xstr(num) "_\n" \
".align 4\n" \
"_overlay_call_in_" xstr(num) "_:\n" \
"s32e a8, a1, -20\n" \
"addi a8, a1, -32\n" \
"movsp a1, a8\n" \
"movi a8, " xstr(num) "\n" \
"j _overlay_call_in_common\n" \
".size _overlay_call_in_" xstr(num) "_, . - _overlay_call_in_" xstr(num) "_\n");
// The call-out stub first calls the target function, then loads the overlay
// number into register a14 and jumps to the common handler. The handler will
// make sure that the caller function is present in memory before returning.
// Note that registers a10-a13 may contain return values so must be preserved.
//
// Because we came here via a call4, the return address is in a4, and the top
// 2 bits are set to the window increment. We'll restore the top 2 bits of
// the return address from the called function's address, assuming that both
// are in the same 1 GB segment. For now this is always true.
#define CALL_OUT(num) \
asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
".global _overlay_call_out_" xstr(num) "_\n" \
".align 4\n" \
"_overlay_call_out_" xstr(num) "_:\n" \
"slli a4, a4, 2\n" \
"srli a4, a4, 2\n" \
"extui a8, a9, 30, 2\n" \
"slli a8, a8, 30\n" \
"or a4, a4, a8\n" \
"callx8 a9\n" \
"movi a14, " xstr(num) "\n" \
"j _overlay_call_out_common\n" \
".size _overlay_call_out_" xstr(num) "_, . - _overlay_call_out_" xstr(num) "_\n");
// Generate a call-in and a call-out stub for each overlay.
#define DECLARE_OVERLAY(num) \
CALL_IN(num) \
CALL_OUT(num)
#endif // defined(__XTENSA_WINDOWED_ABI__)
#endif // XT_DISABLE_OVERLAYS
#ifdef __cplusplus
}
#endif
#endif // OVERLAY_H

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// overlay_os_asm.h -- Overlay manager assembly macros for OS use.
// $Id$
// Copyright (c) 2013 Tensilica Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef OVERLAY_OS_ASM_H
#define OVERLAY_OS_ASM_H
// The macros in here are intended to be used by RTOS task switch code
// to check overlay status. Such code is usually in assembly and cannot
// call C code without penalty. For C code usage, it is best to use the
// corresponding C functions from the library.
// Inline assembly version of xt_overlay_get_state(). The arguments are
// three AR registers (a0-a15):
//
// "pcreg" - should contain the outgoing task's PC, i.e. the point at
// which the task got interrupted. The return value is also
// returned in this register.
// "sr1/2" - Scratch registers. These must be distinct from "pcreg".
//
// The return value is a 32-bit result that should be saved with the
// task context and passed as-is to xt_overlay_check_map.
.macro _xt_overlay_get_state pcreg sr1 sr2
movi \sr1, _mapping_id
movi \sr2, _ovly_id
l16si \sr1, \sr1, 0
l16ui \sr2, \sr2, 0
slli \sr1, \sr1, 16
or \pcreg, \sr1, \sr2
.endm
// Inline assembly version of xt_overlay_check_map(). It requires 5 AR
// registers (a0-a15) as arguments.
//
// "pcreg" - should contain the interrupted task's PC, i.e. the point
// at which the task got interrupted. This will be adjusted
// if required.
// "psreg" - should contain the interrupted task's PS. This will be
// adjusted if required.
// "ovreg" - should contain the overlay state on entry. Contents may
// be clobbered.
// "spreg" - should contain the tasks stack pointer on entry.
// "sr1" - Scratch register. Must be distinct from any of the above.
//
// The return values are "pcreg" and "psreg" and these must be used
// to update the task's PC and PS.
// Note that this macro may store data below the "spreg" pointer. If
// it does, then it will also disable interrupts via the PS, so that
// the task resumes with all interrupts disabled (to avoid corrupting
// this data).
//
// (SP - 24) Overlay ID to restore
// (SP - 28) Task PC
// (SP - 32) Task PS
.macro _xt_overlay_check_map pcreg psreg ovreg spreg sr1
// There are four cases to deal with:
//
// _ovly_id = -1, _mapping_id = -1
// No overlay is mapped or mapping, nothing to do.
//
// _ovly_id >= 0, _mapping_id = -1
// An overlay was mapped, check PC to see if we need a restore.
//
// _ovly_id = -1, _mapping_id >= 0
// An overlay is being mapped. Either it belongs to this task, which
// implies that the PC is in the mapping function, or it does not
// belong to this task. Either way there is nothing to do.
//
// _ovly_id >= 0, _mapping_id >= 0
// Illegal, cannot happen by design. Don't need to handle this.
//
// So, the logic is to check _ovly_id first. If this is >= 0, then
// we check the task PC. If the PC is in the regions of interest then
// we'll patch the return PC to invoke xt_overlay_restore.
.L1:
extui \sr1, \ovreg, 0, 16 // Extract _ovly_id
bbsi.l \sr1, 15, .Lno // If -1 then we're done
mov \ovreg, \sr1 // Restore this one
// Next check the PC to see if it falls within the ranges of interest.
.L2:
movi \sr1, _overlay_vma // Is PC < VMA range ?
bltu \pcreg, \sr1, .L3
movi \sr1, _overlay_vma_end // Is PC > VMA range ?
bgeu \pcreg, \sr1, .L3
j .L4 // PC is in VMA range
.L3:
movi \sr1, _overlay_call_stubs_start // Is PC < call stubs range ?
bltu \pcreg, \sr1, .Lno
movi \sr1, _overlay_call_stubs_end // Is PC > call stubs range ?
bgeu \pcreg, \sr1, .Lno
// If we get here then a restore is needed. Save the overlay ID, PC and PS.
// Return modified PC and PS so that xt_overlay_restore() will execute in
// the context of the task when resumed. Note that the OS resumption code
// may expect PS.EXCM to be set so we leave it as is in the return value.
.L4:
s32e \ovreg, \spreg, -24 // Save overlay ID
s32e \pcreg, \spreg, -28 // Save task PC
s32e \psreg, \spreg, -32 // Save task PS
movi \pcreg, xt_overlay_restore // Adjust resumption PC
movi \sr1, 15
or \psreg, \psreg, \sr1 // Set intlevel to highest
.Lno:
.endm
#endif // OVERLAY_OS_ASM_H

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components/esp32/include/xtensa/sim.h
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/* Copyright (c) 2004-2006 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* sim.h
*
* Definitions and prototypes for specific ISS SIMCALLs
* (ie. outside the standard C library).
*/
#ifndef _INC_SIM_H_
#define _INC_SIM_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Shortcuts for enabling/disabling profiling in the Xtensa ISS */
extern void xt_iss_profile_enable(void);
extern void xt_iss_profile_disable(void);
/* Shortcut for setting the trace level in the Xtensa ISS */
extern void xt_iss_trace_level(unsigned level);
/* Generic interface for passing client commands in the Xtensa ISS:
* returns 0 on success, -1 on failure.
*/
extern int xt_iss_client_command(const char *client, const char *command);
/* Interface for switching simulation modes in the Xtensa ISS:
* returns 0 on success, -1 on failure.
*/
#define XT_ISS_CYCLE_ACCURATE 0
#define XT_ISS_FUNCTIONAL 1
extern int xt_iss_switch_mode(int mode);
/* Interface for waiting on a system synchronization event */
extern void xt_iss_event_wait(unsigned event_id);
/* Interface for firing a system synchronization event */
extern void xt_iss_event_fire(unsigned event_id);
/* Interface for invoking a user simcall action,
* which can be registered in XTMP or XTSC.
*/
extern int xt_iss_simcall(int arg1, int arg2, int arg3,
int arg4, int arg5, int arg6);
#ifdef __cplusplus
}
#endif
#endif /*_INC_SIM_H_*/

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components/esp32/include/xtensa/simboard.h
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/*
* Copyright (c) 2001 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* simboard.h - Xtensa ISS "Board" specific definitions */
#ifndef _INC_SIMBOARD_H_
#define _INC_SIMBOARD_H_
#include <xtensa/config/core.h>
#include <xtensa/config/system.h>
/*
* Device addresses.
*/
/* System ROM: */
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
#ifdef XSHAL_ROM_VADDR
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
#endif
#ifdef XSHAL_ROM_PADDR
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
#endif
/* System RAM: */
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
#ifdef XSHAL_RAM_VADDR
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
#endif
#ifdef XSHAL_RAM_PADDR
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
#endif
/*
* Things that depend on device addresses.
*/
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU
#define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
#define XTBOARD_BUSINT_PIPE_REGIONS 0
#define XTBOARD_BUSINT_SDRAM_REGIONS 0
#endif /*_INC_SIMBOARD_H_*/

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components/esp32/include/xtensa/simcall-errno.h
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/* Error numbers for Xtensa ISS semihosting. */
/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc. */
#ifndef _SIMCALL_ERRNO_H
#define _SIMCALL_ERRNO_H
/* Define the error numbers (using the default newlib values) with prefixes
so they can be used in ISS without conflicting with the host values. */
#define _SIMC_EPERM 1
#define _SIMC_ENOENT 2
#define _SIMC_ESRCH 3
#define _SIMC_EINTR 4
#define _SIMC_EIO 5
#define _SIMC_ENXIO 6
#define _SIMC_E2BIG 7
#define _SIMC_ENOEXEC 8
#define _SIMC_EBADF 9
#define _SIMC_ECHILD 10
#define _SIMC_EAGAIN 11
#define _SIMC_ENOMEM 12
#define _SIMC_EACCES 13
#define _SIMC_EFAULT 14
#define _SIMC_ENOTBLK 15
#define _SIMC_EBUSY 16
#define _SIMC_EEXIST 17
#define _SIMC_EXDEV 18
#define _SIMC_ENODEV 19
#define _SIMC_ENOTDIR 20
#define _SIMC_EISDIR 21
#define _SIMC_EINVAL 22
#define _SIMC_ENFILE 23
#define _SIMC_EMFILE 24
#define _SIMC_ENOTTY 25
#define _SIMC_ETXTBSY 26
#define _SIMC_EFBIG 27
#define _SIMC_ENOSPC 28
#define _SIMC_ESPIPE 29
#define _SIMC_EROFS 30
#define _SIMC_EMLINK 31
#define _SIMC_EPIPE 32
#define _SIMC_EDOM 33
#define _SIMC_ERANGE 34
#define _SIMC_ENOMSG 35
#define _SIMC_EIDRM 36
#define _SIMC_ECHRNG 37
#define _SIMC_EL2NSYNC 38
#define _SIMC_EL3HLT 39
#define _SIMC_EL3RST 40
#define _SIMC_ELNRNG 41
#define _SIMC_EUNATCH 42
#define _SIMC_ENOCSI 43
#define _SIMC_EL2HLT 44
#define _SIMC_EDEADLK 45
#define _SIMC_ENOLCK 46
#define _SIMC_EBADE 50
#define _SIMC_EBADR 51
#define _SIMC_EXFULL 52
#define _SIMC_ENOANO 53
#define _SIMC_EBADRQC 54
#define _SIMC_EBADSLT 55
#define _SIMC_EDEADLOCK 56
#define _SIMC_EBFONT 57
#define _SIMC_ENOSTR 60
#define _SIMC_ENODATA 61
#define _SIMC_ETIME 62
#define _SIMC_ENOSR 63
#define _SIMC_ENONET 64
#define _SIMC_ENOPKG 65
#define _SIMC_EREMOTE 66
#define _SIMC_ENOLINK 67
#define _SIMC_EADV 68
#define _SIMC_ESRMNT 69
#define _SIMC_ECOMM 70
#define _SIMC_EPROTO 71
#define _SIMC_EMULTIHOP 74
#define _SIMC_ELBIN 75
#define _SIMC_EDOTDOT 76
#define _SIMC_EBADMSG 77
#define _SIMC_EFTYPE 79
#define _SIMC_ENOTUNIQ 80
#define _SIMC_EBADFD 81
#define _SIMC_EREMCHG 82
#define _SIMC_ELIBACC 83
#define _SIMC_ELIBBAD 84
#define _SIMC_ELIBSCN 85
#define _SIMC_ELIBMAX 86
#define _SIMC_ELIBEXEC 87
#define _SIMC_ENOSYS 88
#define _SIMC_ENMFILE 89
#define _SIMC_ENOTEMPTY 90
#define _SIMC_ENAMETOOLONG 91
#define _SIMC_ELOOP 92
#define _SIMC_EOPNOTSUPP 95
#define _SIMC_EPFNOSUPPORT 96
#define _SIMC_ECONNRESET 104
#define _SIMC_ENOBUFS 105
#define _SIMC_EAFNOSUPPORT 106
#define _SIMC_EPROTOTYPE 107
#define _SIMC_ENOTSOCK 108
#define _SIMC_ENOPROTOOPT 109
#define _SIMC_ESHUTDOWN 110
#define _SIMC_ECONNREFUSED 111
#define _SIMC_EADDRINUSE 112
#define _SIMC_ECONNABORTED 113
#define _SIMC_ENETUNREACH 114
#define _SIMC_ENETDOWN 115
#define _SIMC_ETIMEDOUT 116
#define _SIMC_EHOSTDOWN 117
#define _SIMC_EHOSTUNREACH 118
#define _SIMC_EINPROGRESS 119
#define _SIMC_EALREADY 120
#define _SIMC_EDESTADDRREQ 121
#define _SIMC_EMSGSIZE 122
#define _SIMC_EPROTONOSUPPORT 123
#define _SIMC_ESOCKTNOSUPPORT 124
#define _SIMC_EADDRNOTAVAIL 125
#define _SIMC_ENETRESET 126
#define _SIMC_EISCONN 127
#define _SIMC_ENOTCONN 128
#define _SIMC_ETOOMANYREFS 129
#define _SIMC_EPROCLIM 130
#define _SIMC_EUSERS 131
#define _SIMC_EDQUOT 132
#define _SIMC_ESTALE 133
#define _SIMC_ENOTSUP 134
#define _SIMC_ENOMEDIUM 135
#define _SIMC_ENOSHARE 136
#define _SIMC_ECASECLASH 137
#define _SIMC_EILSEQ 138
#define _SIMC_EOVERFLOW 139
#endif /* ! _SIMCALL_ERRNO_H */

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components/esp32/include/xtensa/simcall-fcntl.h
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/* File control operations for Xtensa ISS semihosting. */
/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc. */
#ifndef _SIMCALL_FCNTL_H
#define _SIMCALL_FCNTL_H
#define _SIMC_O_APPEND 0x0008
#define _SIMC_O_NONBLOCK 0x0080
#define _SIMC_O_CREAT 0x0100
#define _SIMC_O_TRUNC 0x0200
#define _SIMC_O_EXCL 0x0400
#define _SIMC_O_TEXT 0x4000
#define _SIMC_O_BINARY 0x8000
#endif /* ! _SIMCALL_FCNTL_H */

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components/esp32/include/xtensa/simcall.h
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/*
* simcall.h - Simulator call numbers
*
* Software that runs on a simulated Xtensa processor using
* the instruction set simulator (ISS) can invoke simulator
* services using the SIMCALL instruction. The a2 register
* is set prior to executing SIMCALL to a "simcall number",
* indicating which service to invoke. This file defines the
* simcall numbers defined and/or supported by the Xtensa ISS.
*
* IMPORTANT NOTE: These numbers are highly subject to change!
*
* Copyright (c) 2002-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef SIMCALL_INCLUDED
#define SIMCALL_INCLUDED
/*
* System call like services offered by the simulator host.
* These are modeled after the Linux 2.4 kernel system calls
* for Xtensa processors. However not all system calls and
* not all functionality of a given system call are implemented,
* or necessarily have well defined or equivalent semantics in
* the context of a simulation (as opposed to a Unix kernel).
*
* These services behave largely as if they had been invoked
* as a task in the simulator host's operating system
* (eg. files accessed are those of the simulator host).
* However, these SIMCALLs model a virtual operating system
* so that various definitions, bit assignments etc
* (eg. open mode bits, errno values, etc) are independent
* of the host operating system used to run the simulation.
* Rather these definitions are specific to the Xtensa ISS.
* This way Xtensa ISA code written to use these SIMCALLs
* can (in principle) be simulated on any host.
*
* Up to 6 parameters are passed in registers a3 to a8
* (note the 6th parameter isn't passed on the stack,
* unlike windowed function calling conventions).
* The return value is in a2. A negative value in the
* range -4096 to -1 indicates a negated error code to be
* reported in errno with a return value of -1, otherwise
* the value in a2 is returned as is.
*/
/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
#define SYS_nop 0 /* n/a - setup; used to flush register windows */
#define SYS_exit 1 /*x*/
#define SYS_fork 2
#define SYS_read 3 /*x*/
#define SYS_write 4 /*x*/
#define SYS_open 5 /*x*/
#define SYS_close 6 /*x*/
#define SYS_rename 7 /*x 38 - waitpid */
#define SYS_creat 8 /*x*/
#define SYS_link 9 /*x (not implemented on WIN32) */
#define SYS_unlink 10 /*x*/
#define SYS_execv 11 /* n/a - execve */
#define SYS_execve 12 /* 11 - chdir */
#define SYS_pipe 13 /* 42 - time */
#define SYS_stat 14 /* 106 - mknod */
#define SYS_chmod 15
#define SYS_chown 16 /* 202 - lchown */
#define SYS_utime 17 /* 30 - break */
#define SYS_wait 18 /* n/a - oldstat */
#define SYS_lseek 19 /*x*/
#define SYS_getpid 20
#define SYS_isatty 21 /* n/a - mount */
#define SYS_fstat 22 /* 108 - oldumount */
#define SYS_time 23 /* 13 - setuid */
#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
#define SYS_socket 26
#define SYS_sendto 27
#define SYS_recvfrom 28
#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */
#define SYS_bind 30
#define SYS_ioctl 31
/*
* Other...
*/
#define SYS_iss_argc 1000 /* returns value of argc */
#define SYS_iss_argv_size 1001 /* bytes needed for argv & arg strings */
#define SYS_iss_set_argv 1002 /* saves argv & arg strings at given addr */
#define SYS_memset 1004 /* fill a range of memory (fast) */
/*
* SIMCALLs for the ferret memory debugger. All are invoked by
* libferret.a ... ( Xtensa/Target-Libs/ferret )
*/
#define SYS_ferret 1010
#define SYS_malloc 1011
#define SYS_free 1012
#define SYS_more_heap 1013
#define SYS_no_heap 1014
#define SYS_enter_ferret 1015
#define SYS_leave_ferret 1016
/*
* SIMCALLs for ISS client commands
*/
#define SYS_profile_enable 1020
#define SYS_profile_disable 1021
#define SYS_trace_level 1022
#define SYS_client_command 1023
/*
* SIMCALL for simulation mode switching
*/
#define SYS_sim_mode_switch 1030
/*
* SIMCALLs for XTMP/XTSC event notify and core stall
*/
#define SYS_event_fire 1040
#define SYS_event_stall 1041
/*
* SIMCALLs for callbacks registered in XTMP/XTSC
*/
#define SYS_callback_first 100
#define SYS_callback_last 999
/*
* User defined simcall
*/
#define SYS_user_simcall 100
#define SYS_xmpa_errinfo 200
#define SYS_xmpa_proc_status 201
#define SYS_xmpa_proc_start 202
#define SYS_xmpa_proc_stop 203
#define SYS_xmpa_proc_mem_read 204
#define SYS_xmpa_proc_mem_write 205
#define SYS_xmpa_proc_mem_fill 206
#define SYS_xmpa_proc_reg_read 207
#define SYS_xmpa_proc_reg_write 208
/*
* Extra SIMCALLs for GDB:
*/
#define SYS_gdb_break -1 /* invoked by XTOS on user exceptions if EPC points
to a break.n/break, regardless of cause! */
#define SYS_xmon_out -2 /* invoked by XMON: ... */
#define SYS_xmon_in -3 /* invoked by XMON: ... */
#define SYS_xmon_flush -4 /* invoked by XMON: ... */
#define SYS_gdb_abort -5 /* invoked by XTOS in _xtos_panic() */
#define SYS_gdb_illegal_inst -6 /* invoked by XTOS for illegal instructions (too deeply) */
#define SYS_xmon_init -7 /* invoked by XMON: ... */
#define SYS_gdb_enter_sktloop -8 /* invoked by XTOS on debug exceptions */
#define SYS_unhandled_kernel_exc -9 /* invoked by XTOS for unhandled kernel exceptions */
#define SYS_unhandled_user_exc -10 /* invoked by XTOS for unhandled user exceptions */
#define SYS_unhandled_double_exc -11 /* invoked by XTOS for unhandled double exceptions */
#define SYS_unhandled_highpri_interrupt -12 /* invoked by XTOS for unhandled high-priority interrupts */
#define SYS_xmon_close -13 /* invoked by XMON: ... */
/*
* SIMCALLs for vxWorks xtiss BSP:
*/
#define SYS_setup_ppp_pipes -83
#define SYS_log_msg -84
/*
* SYS_select_one specifiers
*/
#define XTISS_SELECT_ONE_READ 1
#define XTISS_SELECT_ONE_WRITE 2
#define XTISS_SELECT_ONE_EXCEPT 3
/*
* SIMCALL for client calling arbitrary code in a client plug in.
* see clients/xcc_instr to see how this works.
*/
#define SYS_client 0xC0DECAFE
#endif /* !SIMCALL_INCLUDED */

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components/esp32/include/xtensa/tie/xt_DFP_assist.h
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/* Definitions for the xt_DFP_assist TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_DFP_assist_HEADER
#define _XTENSA_xt_DFP_assist_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_DFP_assist_F64ITER(unsigned arr /*inout*/, unsigned ars, unsigned art, immediate oper, immediate noshift);
extern unsigned _TIE_xt_DFP_assist_F64RND(unsigned ars, unsigned art, immediate mode);
extern void _TIE_xt_DFP_assist_F64ADDC(unsigned art /*inout*/, unsigned ars, immediate immZ, immediate immC);
extern void _TIE_xt_DFP_assist_F64SUBC(unsigned art /*inout*/, unsigned ars, immediate immZ, immediate immC);
extern unsigned _TIE_xt_DFP_assist_F64SIG(unsigned ars);
extern unsigned _TIE_xt_DFP_assist_F64CMPL(unsigned ars, unsigned art);
extern unsigned _TIE_xt_DFP_assist_F64CMPH(unsigned ars, unsigned art, immediate oper);
extern unsigned _TIE_xt_DFP_assist_F64NORM(unsigned ars, unsigned art, immediate mode);
extern unsigned _TIE_xt_DFP_assist_F64SEXP(unsigned ars, unsigned art);
extern unsigned _TIE_xt_DFP_assist_RF64R(immediate hilo);
extern void _TIE_xt_DFP_assist_WF64R(unsigned ars, unsigned art, immediate hilo);
extern unsigned _TIE_xt_DFP_assist_RUR_F64R_LO(void);
extern unsigned _TIE_xt_DFP_assist_RUR_F64R_HI(void);
extern void _TIE_xt_DFP_assist_WUR_F64R_LO(unsigned art);
extern void _TIE_xt_DFP_assist_WUR_F64R_HI(unsigned art);
extern unsigned _TIE_xt_DFP_assist_RUR_F64S(void);
extern void _TIE_xt_DFP_assist_WUR_F64S(unsigned art);
#define F64ITER _TIE_xt_DFP_assist_F64ITER
#define F64RND _TIE_xt_DFP_assist_F64RND
#define F64ADDC _TIE_xt_DFP_assist_F64ADDC
#define F64SUBC _TIE_xt_DFP_assist_F64SUBC
#define F64SIG _TIE_xt_DFP_assist_F64SIG
#define F64CMPL _TIE_xt_DFP_assist_F64CMPL
#define F64CMPH _TIE_xt_DFP_assist_F64CMPH
#define F64NORM _TIE_xt_DFP_assist_F64NORM
#define F64SEXP _TIE_xt_DFP_assist_F64SEXP
#define RF64R _TIE_xt_DFP_assist_RF64R
#define WF64R _TIE_xt_DFP_assist_WF64R
#define RUR_F64R_LO _TIE_xt_DFP_assist_RUR_F64R_LO
#define RF64R_LO _TIE_xt_DFP_assist_RUR_F64R_LO
#define RUR234 _TIE_xt_DFP_assist_RUR_F64R_LO
#define RUR_F64R_HI _TIE_xt_DFP_assist_RUR_F64R_HI
#define RF64R_HI _TIE_xt_DFP_assist_RUR_F64R_HI
#define RUR235 _TIE_xt_DFP_assist_RUR_F64R_HI
#define WUR_F64R_LO _TIE_xt_DFP_assist_WUR_F64R_LO
#define WF64R_LO _TIE_xt_DFP_assist_WUR_F64R_LO
#define WUR234 _TIE_xt_DFP_assist_WUR_F64R_LO
#define WUR_F64R_HI _TIE_xt_DFP_assist_WUR_F64R_HI
#define WF64R_HI _TIE_xt_DFP_assist_WUR_F64R_HI
#define WUR235 _TIE_xt_DFP_assist_WUR_F64R_HI
#define RUR_F64S _TIE_xt_DFP_assist_RUR_F64S
#define RF64S _TIE_xt_DFP_assist_RUR_F64S
#define RUR236 _TIE_xt_DFP_assist_RUR_F64S
#define WUR_F64S _TIE_xt_DFP_assist_WUR_F64S
#define WF64S _TIE_xt_DFP_assist_WUR_F64S
#define WUR236 _TIE_xt_DFP_assist_WUR_F64S
#ifndef RUR
#define RUR(NUM) RUR##NUM()
#endif
#ifndef WUR
#define WUR(VAL, NUM) WUR##NUM(VAL)
#endif
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_DFP_assist_HEADER */

197
components/esp32/include/xtensa/tie/xt_FP.h
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@@ -1,197 +0,0 @@
/* Definitions for the xt_FP TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_FP_HEADER
#define _XTENSA_xt_FP_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_booleans.h>
typedef float _TIE_xt_FP_xtfloat;
typedef _TIE_xt_FP_xtfloat xtfloat;
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_FP_RUR_FCR(void);
extern void _TIE_xt_FP_WUR_FCR(unsigned v);
extern unsigned _TIE_xt_FP_RUR_FSR(void);
extern void _TIE_xt_FP_WUR_FSR(unsigned v);
extern xtfloat _TIE_xt_FP_xtfloat_loadi(const xtfloat * p, immediate imm8x4);
extern void _TIE_xt_FP_xtfloat_storei(xtfloat t, xtfloat * p, immediate imm8x4);
extern void _TIE_xt_FP_xtfloat_loadip(xtfloat t /*out*/, const xtfloat * p /*inout*/, immediate imm8x4);
extern void _TIE_xt_FP_xtfloat_storeip(xtfloat t, xtfloat * p /*inout*/, immediate imm8x4);
extern xtfloat _TIE_xt_FP_xtfloat_loadx(const xtfloat * p, int imm8x4);
extern void _TIE_xt_FP_xtfloat_storex(xtfloat t, xtfloat * p, int imm8x4);
extern void _TIE_xt_FP_xtfloat_loadxp(xtfloat t /*out*/, const xtfloat * p /*inout*/, int imm8x4);
extern void _TIE_xt_FP_xtfloat_storexp(xtfloat t, xtfloat * p /*inout*/, int imm8x4);
extern xtfloat _TIE_xt_FP_xtfloat_move(xtfloat r);
extern int _TIE_xt_FP_ROUND_S(xtfloat s, immediate t);
extern int _TIE_xt_FP_TRUNC_S(xtfloat s, immediate t);
extern unsigned _TIE_xt_FP_UTRUNC_S(xtfloat s, immediate t);
extern int _TIE_xt_FP_FLOOR_S(xtfloat s, immediate t);
extern int _TIE_xt_FP_CEIL_S(xtfloat s, immediate t);
extern xtfloat _TIE_xt_FP_LSI(const xtfloat * p, immediate imm8x4);
extern void _TIE_xt_FP_SSI(xtfloat t, xtfloat * p, immediate imm8x4);
extern void _TIE_xt_FP_LSIP(xtfloat t /*out*/, const xtfloat * p /*inout*/, immediate imm8x4);
extern void _TIE_xt_FP_SSIP(xtfloat t, xtfloat * p /*inout*/, immediate imm8x4);
extern xtfloat _TIE_xt_FP_LSX(const xtfloat * p, int imm8x4);
extern void _TIE_xt_FP_SSX(xtfloat t, xtfloat * p, int imm8x4);
extern void _TIE_xt_FP_LSXP(xtfloat t /*out*/, const xtfloat * p /*inout*/, int imm8x4);
extern void _TIE_xt_FP_SSXP(xtfloat t, xtfloat * p /*inout*/, int imm8x4);
extern xtfloat _TIE_xt_FP_ABS_S(xtfloat s);
extern xtfloat _TIE_xt_FP_NEG_S(xtfloat s);
extern xtfloat _TIE_xt_FP_MOV_S(xtfloat s);
extern void _TIE_xt_FP_MOVEQZ_S(xtfloat r /*inout*/, xtfloat s, int t);
extern void _TIE_xt_FP_MOVNEZ_S(xtfloat r /*inout*/, xtfloat s, int t);
extern void _TIE_xt_FP_MOVLTZ_S(xtfloat r /*inout*/, xtfloat s, int t);
extern void _TIE_xt_FP_MOVGEZ_S(xtfloat r /*inout*/, xtfloat s, int t);
extern void _TIE_xt_FP_MOVF_S(xtfloat r /*inout*/, xtfloat s, xtbool t);
extern void _TIE_xt_FP_MOVT_S(xtfloat r /*inout*/, xtfloat s, xtbool t);
extern unsigned _TIE_xt_FP_RFR(xtfloat s);
extern xtfloat _TIE_xt_FP_WFR(unsigned s);
extern xtfloat _TIE_xt_FP_FLOAT_S(int s, immediate t);
extern xtfloat _TIE_xt_FP_UFLOAT_S(unsigned s, immediate t);
extern xtbool _TIE_xt_FP_OEQ_S(xtfloat s, xtfloat t);
extern xtbool _TIE_xt_FP_OLE_S(xtfloat s, xtfloat t);
extern xtbool _TIE_xt_FP_OLT_S(xtfloat s, xtfloat t);
extern xtbool _TIE_xt_FP_UEQ_S(xtfloat s, xtfloat t);
extern xtbool _TIE_xt_FP_ULE_S(xtfloat s, xtfloat t);
extern xtbool _TIE_xt_FP_ULT_S(xtfloat s, xtfloat t);
extern xtbool _TIE_xt_FP_UN_S(xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_ADD_S(xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_SUB_S(xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_MUL_S(xtfloat s, xtfloat t);
extern void _TIE_xt_FP_MADD_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
extern void _TIE_xt_FP_MSUB_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_RECIP0_S(xtfloat s);
extern xtfloat _TIE_xt_FP_DIV0_S(xtfloat s);
extern xtfloat _TIE_xt_FP_NEXP01_S(xtfloat s);
extern xtfloat _TIE_xt_FP_CONST_S(immediate s);
extern void _TIE_xt_FP_MKDADJ_S(xtfloat r /*inout*/, xtfloat s);
extern xtfloat _TIE_xt_FP_MKSADJ_S(xtfloat s);
extern void _TIE_xt_FP_ADDEXPM_S(xtfloat r /*inout*/, xtfloat s);
extern void _TIE_xt_FP_ADDEXP_S(xtfloat r /*inout*/, xtfloat s);
extern void _TIE_xt_FP_DIVN_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_RSQRT0_S(xtfloat s);
extern xtfloat _TIE_xt_FP_SQRT0_S(xtfloat s);
extern void _TIE_xt_FP_MADDN_S(xtfloat r /*inout*/, xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_DIV_S(xtfloat s, xtfloat t);
extern xtfloat _TIE_xt_FP_SQRT_S(xtfloat s);
extern xtfloat _TIE_xt_FP_RECIP_S(xtfloat s);
extern xtfloat _TIE_xt_FP_RSQRT_S(xtfloat s);
extern xtfloat _TIE_xt_FP_FSQRT_S(xtfloat s);
#define XT_RUR_FCR _TIE_xt_FP_RUR_FCR
#define RFCR _TIE_xt_FP_RUR_FCR
#define RUR232 _TIE_xt_FP_RUR_FCR
#define XT_WUR_FCR _TIE_xt_FP_WUR_FCR
#define WFCR _TIE_xt_FP_WUR_FCR
#define WUR232 _TIE_xt_FP_WUR_FCR
#define XT_RUR_FSR _TIE_xt_FP_RUR_FSR
#define RFSR _TIE_xt_FP_RUR_FSR
#define RUR233 _TIE_xt_FP_RUR_FSR
#define XT_WUR_FSR _TIE_xt_FP_WUR_FSR
#define WFSR _TIE_xt_FP_WUR_FSR
#define WUR233 _TIE_xt_FP_WUR_FSR
#define XT_xtfloat_loadi _TIE_xt_FP_xtfloat_loadi
#define XT_xtfloat_storei _TIE_xt_FP_xtfloat_storei
#define XT_xtfloat_loadip _TIE_xt_FP_xtfloat_loadip
#define XT_xtfloat_storeip _TIE_xt_FP_xtfloat_storeip
#define XT_xtfloat_loadx _TIE_xt_FP_xtfloat_loadx
#define XT_xtfloat_storex _TIE_xt_FP_xtfloat_storex
#define XT_xtfloat_loadxp _TIE_xt_FP_xtfloat_loadxp
#define XT_xtfloat_storexp _TIE_xt_FP_xtfloat_storexp
#define XT_xtfloat_move _TIE_xt_FP_xtfloat_move
#define XT_ROUND_S _TIE_xt_FP_ROUND_S
#define XT_TRUNC_S _TIE_xt_FP_TRUNC_S
#define XT_UTRUNC_S _TIE_xt_FP_UTRUNC_S
#define XT_FLOOR_S _TIE_xt_FP_FLOOR_S
#define XT_CEIL_S _TIE_xt_FP_CEIL_S
#define XT_LSI _TIE_xt_FP_LSI
#define XT_SSI _TIE_xt_FP_SSI
#define XT_LSIP _TIE_xt_FP_LSIP
#define XT_SSIP _TIE_xt_FP_SSIP
#define XT_LSX _TIE_xt_FP_LSX
#define XT_SSX _TIE_xt_FP_SSX
#define XT_LSXP _TIE_xt_FP_LSXP
#define XT_SSXP _TIE_xt_FP_SSXP
#define XT_ABS_S _TIE_xt_FP_ABS_S
#define XT_NEG_S _TIE_xt_FP_NEG_S
#define XT_MOV_S _TIE_xt_FP_MOV_S
#define XT_MOVEQZ_S _TIE_xt_FP_MOVEQZ_S
#define XT_MOVNEZ_S _TIE_xt_FP_MOVNEZ_S
#define XT_MOVLTZ_S _TIE_xt_FP_MOVLTZ_S
#define XT_MOVGEZ_S _TIE_xt_FP_MOVGEZ_S
#define XT_MOVF_S _TIE_xt_FP_MOVF_S
#define XT_MOVT_S _TIE_xt_FP_MOVT_S
#define XT_RFR _TIE_xt_FP_RFR
#define XT_WFR _TIE_xt_FP_WFR
#define XT_FLOAT_S _TIE_xt_FP_FLOAT_S
#define XT_UFLOAT_S _TIE_xt_FP_UFLOAT_S
#define XT_OEQ_S _TIE_xt_FP_OEQ_S
#define XT_OLE_S _TIE_xt_FP_OLE_S
#define XT_OLT_S _TIE_xt_FP_OLT_S
#define XT_UEQ_S _TIE_xt_FP_UEQ_S
#define XT_ULE_S _TIE_xt_FP_ULE_S
#define XT_ULT_S _TIE_xt_FP_ULT_S
#define XT_UN_S _TIE_xt_FP_UN_S
#define XT_ADD_S _TIE_xt_FP_ADD_S
#define XT_SUB_S _TIE_xt_FP_SUB_S
#define XT_MUL_S _TIE_xt_FP_MUL_S
#define XT_MADD_S _TIE_xt_FP_MADD_S
#define XT_MSUB_S _TIE_xt_FP_MSUB_S
#define XT_RECIP0_S _TIE_xt_FP_RECIP0_S
#define XT_DIV0_S _TIE_xt_FP_DIV0_S
#define XT_NEXP01_S _TIE_xt_FP_NEXP01_S
#define XT_CONST_S _TIE_xt_FP_CONST_S
#define XT_MKDADJ_S _TIE_xt_FP_MKDADJ_S
#define XT_MKSADJ_S _TIE_xt_FP_MKSADJ_S
#define XT_ADDEXPM_S _TIE_xt_FP_ADDEXPM_S
#define XT_ADDEXP_S _TIE_xt_FP_ADDEXP_S
#define XT_DIVN_S _TIE_xt_FP_DIVN_S
#define XT_RSQRT0_S _TIE_xt_FP_RSQRT0_S
#define XT_SQRT0_S _TIE_xt_FP_SQRT0_S
#define XT_MADDN_S _TIE_xt_FP_MADDN_S
#define XT_DIV_S _TIE_xt_FP_DIV_S
#define XT_SQRT_S _TIE_xt_FP_SQRT_S
#define XT_RECIP_S _TIE_xt_FP_RECIP_S
#define XT_RSQRT_S _TIE_xt_FP_RSQRT_S
#define XT_FSQRT_S _TIE_xt_FP_FSQRT_S
#ifndef RUR
#define RUR(NUM) RUR##NUM()
#endif
#ifndef WUR
#define WUR(VAL, NUM) WUR##NUM(VAL)
#endif
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_FP_HEADER */

239
components/esp32/include/xtensa/tie/xt_MAC16.h
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@@ -1,239 +0,0 @@
/* Definitions for the xt_MAC16 TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_MAC16_HEADER
#define _XTENSA_xt_MAC16_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_mul.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_MAC16_UMUL_AA_HH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_UMUL_AA_LH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_UMUL_AA_HL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_UMUL_AA_LL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MUL_AA_HH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MUL_AA_LH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MUL_AA_HL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MUL_AA_LL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MUL_AD_HH(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MUL_AD_LH(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MUL_AD_HL(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MUL_AD_LL(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MUL_DA_HH(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MUL_DA_LH(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MUL_DA_HL(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MUL_DA_LL(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MUL_DD_HH(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MUL_DD_LH(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MUL_DD_HL(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MUL_DD_LL(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULS_AA_HH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULS_AA_LH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULS_AA_HL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULS_AA_LL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULA_AA_HH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULA_AA_LH(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULA_AA_HL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULA_AA_LL(unsigned ars, unsigned art);
extern void _TIE_xt_MAC16_MULS_AD_HH(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULS_AD_LH(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULS_AD_HL(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULS_AD_LL(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULA_AD_HH(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULA_AD_LH(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULA_AD_HL(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULA_AD_LL(unsigned ars, immediate my);
extern void _TIE_xt_MAC16_MULS_DA_HH(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULS_DA_LH(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULS_DA_HL(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULS_DA_LL(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULA_DA_HH(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULA_DA_LH(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULA_DA_HL(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULA_DA_LL(immediate mx, unsigned art);
extern void _TIE_xt_MAC16_MULS_DD_HH(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULS_DD_LH(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULS_DD_HL(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULS_DD_LL(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULA_DD_HH(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULA_DD_LH(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULA_DD_HL(immediate mx, immediate my);
extern void _TIE_xt_MAC16_MULA_DD_LL(immediate mx, immediate my);
extern unsigned _TIE_xt_MAC16_RSR_M0(void);
extern void _TIE_xt_MAC16_WSR_M0(unsigned art);
extern void _TIE_xt_MAC16_XSR_M0(unsigned art /*inout*/);
extern unsigned _TIE_xt_MAC16_RSR_M1(void);
extern void _TIE_xt_MAC16_WSR_M1(unsigned art);
extern void _TIE_xt_MAC16_XSR_M1(unsigned art /*inout*/);
extern unsigned _TIE_xt_MAC16_RSR_M2(void);
extern void _TIE_xt_MAC16_WSR_M2(unsigned art);
extern void _TIE_xt_MAC16_XSR_M2(unsigned art /*inout*/);
extern unsigned _TIE_xt_MAC16_RSR_M3(void);
extern void _TIE_xt_MAC16_WSR_M3(unsigned art);
extern void _TIE_xt_MAC16_XSR_M3(unsigned art /*inout*/);
extern unsigned _TIE_xt_MAC16_RSR_ACCLO(void);
extern void _TIE_xt_MAC16_WSR_ACCLO(unsigned art);
extern void _TIE_xt_MAC16_XSR_ACCLO(unsigned art /*inout*/);
extern unsigned _TIE_xt_MAC16_RSR_ACCHI(void);
extern void _TIE_xt_MAC16_WSR_ACCHI(unsigned art);
extern void _TIE_xt_MAC16_XSR_ACCHI(unsigned art /*inout*/);
extern void _TIE_xt_MAC16_MULA_DA_LL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_LL_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_HL_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_LH_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_LH_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_HH_LDDEC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DA_HH_LDINC(immediate w, const short * s /*inout*/, immediate x, int t);
extern void _TIE_xt_MAC16_MULA_DD_LL_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_LL_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_HL_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_HL_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_LH_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_LH_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_HH_LDDEC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_MULA_DD_HH_LDINC(immediate w, const short * s /*inout*/, immediate x, immediate y);
extern void _TIE_xt_MAC16_LDDEC(immediate w, const short * p /*inout*/);
extern void _TIE_xt_MAC16_ULDDEC(immediate w, const unsigned short * p /*inout*/);
extern void _TIE_xt_MAC16_SLDDEC(immediate w, const short * p /*inout*/);
extern void _TIE_xt_MAC16_LDINC(immediate w, const short * p /*inout*/);
extern void _TIE_xt_MAC16_ULDINC(immediate w, const unsigned short * p /*inout*/);
extern void _TIE_xt_MAC16_SLDINC(immediate w, const short * p /*inout*/);
extern int _TIE_xt_MAC16_RSR16(void);
extern void _TIE_xt_MAC16_WSR16(int t);
extern void _TIE_xt_MAC16_XSR16(int t /*inout*/);
extern int _TIE_xt_MAC16_RSR17(void);
extern void _TIE_xt_MAC16_WSR17(int t);
extern void _TIE_xt_MAC16_XSR17(int t /*inout*/);
#define XT_UMUL_AA_HH _TIE_xt_MAC16_UMUL_AA_HH
#define XT_UMUL_AA_LH _TIE_xt_MAC16_UMUL_AA_LH
#define XT_UMUL_AA_HL _TIE_xt_MAC16_UMUL_AA_HL
#define XT_UMUL_AA_LL _TIE_xt_MAC16_UMUL_AA_LL
#define XT_MUL_AA_HH _TIE_xt_MAC16_MUL_AA_HH
#define XT_MUL_AA_LH _TIE_xt_MAC16_MUL_AA_LH
#define XT_MUL_AA_HL _TIE_xt_MAC16_MUL_AA_HL
#define XT_MUL_AA_LL _TIE_xt_MAC16_MUL_AA_LL
#define XT_MUL_AD_HH _TIE_xt_MAC16_MUL_AD_HH
#define XT_MUL_AD_LH _TIE_xt_MAC16_MUL_AD_LH
#define XT_MUL_AD_HL _TIE_xt_MAC16_MUL_AD_HL
#define XT_MUL_AD_LL _TIE_xt_MAC16_MUL_AD_LL
#define XT_MUL_DA_HH _TIE_xt_MAC16_MUL_DA_HH
#define XT_MUL_DA_LH _TIE_xt_MAC16_MUL_DA_LH
#define XT_MUL_DA_HL _TIE_xt_MAC16_MUL_DA_HL
#define XT_MUL_DA_LL _TIE_xt_MAC16_MUL_DA_LL
#define XT_MUL_DD_HH _TIE_xt_MAC16_MUL_DD_HH
#define XT_MUL_DD_LH _TIE_xt_MAC16_MUL_DD_LH
#define XT_MUL_DD_HL _TIE_xt_MAC16_MUL_DD_HL
#define XT_MUL_DD_LL _TIE_xt_MAC16_MUL_DD_LL
#define XT_MULS_AA_HH _TIE_xt_MAC16_MULS_AA_HH
#define XT_MULS_AA_LH _TIE_xt_MAC16_MULS_AA_LH
#define XT_MULS_AA_HL _TIE_xt_MAC16_MULS_AA_HL
#define XT_MULS_AA_LL _TIE_xt_MAC16_MULS_AA_LL
#define XT_MULA_AA_HH _TIE_xt_MAC16_MULA_AA_HH
#define XT_MULA_AA_LH _TIE_xt_MAC16_MULA_AA_LH
#define XT_MULA_AA_HL _TIE_xt_MAC16_MULA_AA_HL
#define XT_MULA_AA_LL _TIE_xt_MAC16_MULA_AA_LL
#define XT_MULS_AD_HH _TIE_xt_MAC16_MULS_AD_HH
#define XT_MULS_AD_LH _TIE_xt_MAC16_MULS_AD_LH
#define XT_MULS_AD_HL _TIE_xt_MAC16_MULS_AD_HL
#define XT_MULS_AD_LL _TIE_xt_MAC16_MULS_AD_LL
#define XT_MULA_AD_HH _TIE_xt_MAC16_MULA_AD_HH
#define XT_MULA_AD_LH _TIE_xt_MAC16_MULA_AD_LH
#define XT_MULA_AD_HL _TIE_xt_MAC16_MULA_AD_HL
#define XT_MULA_AD_LL _TIE_xt_MAC16_MULA_AD_LL
#define XT_MULS_DA_HH _TIE_xt_MAC16_MULS_DA_HH
#define XT_MULS_DA_LH _TIE_xt_MAC16_MULS_DA_LH
#define XT_MULS_DA_HL _TIE_xt_MAC16_MULS_DA_HL
#define XT_MULS_DA_LL _TIE_xt_MAC16_MULS_DA_LL
#define XT_MULA_DA_HH _TIE_xt_MAC16_MULA_DA_HH
#define XT_MULA_DA_LH _TIE_xt_MAC16_MULA_DA_LH
#define XT_MULA_DA_HL _TIE_xt_MAC16_MULA_DA_HL
#define XT_MULA_DA_LL _TIE_xt_MAC16_MULA_DA_LL
#define XT_MULS_DD_HH _TIE_xt_MAC16_MULS_DD_HH
#define XT_MULS_DD_LH _TIE_xt_MAC16_MULS_DD_LH
#define XT_MULS_DD_HL _TIE_xt_MAC16_MULS_DD_HL
#define XT_MULS_DD_LL _TIE_xt_MAC16_MULS_DD_LL
#define XT_MULA_DD_HH _TIE_xt_MAC16_MULA_DD_HH
#define XT_MULA_DD_LH _TIE_xt_MAC16_MULA_DD_LH
#define XT_MULA_DD_HL _TIE_xt_MAC16_MULA_DD_HL
#define XT_MULA_DD_LL _TIE_xt_MAC16_MULA_DD_LL
#define XT_RSR_M0 _TIE_xt_MAC16_RSR_M0
#define XT_WSR_M0 _TIE_xt_MAC16_WSR_M0
#define XT_XSR_M0 _TIE_xt_MAC16_XSR_M0
#define XT_RSR_M1 _TIE_xt_MAC16_RSR_M1
#define XT_WSR_M1 _TIE_xt_MAC16_WSR_M1
#define XT_XSR_M1 _TIE_xt_MAC16_XSR_M1
#define XT_RSR_M2 _TIE_xt_MAC16_RSR_M2
#define XT_WSR_M2 _TIE_xt_MAC16_WSR_M2
#define XT_XSR_M2 _TIE_xt_MAC16_XSR_M2
#define XT_RSR_M3 _TIE_xt_MAC16_RSR_M3
#define XT_WSR_M3 _TIE_xt_MAC16_WSR_M3
#define XT_XSR_M3 _TIE_xt_MAC16_XSR_M3
#define XT_RSR_ACCLO _TIE_xt_MAC16_RSR_ACCLO
#define XT_WSR_ACCLO _TIE_xt_MAC16_WSR_ACCLO
#define XT_XSR_ACCLO _TIE_xt_MAC16_XSR_ACCLO
#define XT_RSR_ACCHI _TIE_xt_MAC16_RSR_ACCHI
#define XT_WSR_ACCHI _TIE_xt_MAC16_WSR_ACCHI
#define XT_XSR_ACCHI _TIE_xt_MAC16_XSR_ACCHI
#define XT_MULA_DA_LL_LDDEC _TIE_xt_MAC16_MULA_DA_LL_LDDEC
#define XT_MULA_DA_LL_LDINC _TIE_xt_MAC16_MULA_DA_LL_LDINC
#define XT_MULA_DA_HL_LDDEC _TIE_xt_MAC16_MULA_DA_HL_LDDEC
#define XT_MULA_DA_HL_LDINC _TIE_xt_MAC16_MULA_DA_HL_LDINC
#define XT_MULA_DA_LH_LDDEC _TIE_xt_MAC16_MULA_DA_LH_LDDEC
#define XT_MULA_DA_LH_LDINC _TIE_xt_MAC16_MULA_DA_LH_LDINC
#define XT_MULA_DA_HH_LDDEC _TIE_xt_MAC16_MULA_DA_HH_LDDEC
#define XT_MULA_DA_HH_LDINC _TIE_xt_MAC16_MULA_DA_HH_LDINC
#define XT_MULA_DD_LL_LDDEC _TIE_xt_MAC16_MULA_DD_LL_LDDEC
#define XT_MULA_DD_LL_LDINC _TIE_xt_MAC16_MULA_DD_LL_LDINC
#define XT_MULA_DD_HL_LDDEC _TIE_xt_MAC16_MULA_DD_HL_LDDEC
#define XT_MULA_DD_HL_LDINC _TIE_xt_MAC16_MULA_DD_HL_LDINC
#define XT_MULA_DD_LH_LDDEC _TIE_xt_MAC16_MULA_DD_LH_LDDEC
#define XT_MULA_DD_LH_LDINC _TIE_xt_MAC16_MULA_DD_LH_LDINC
#define XT_MULA_DD_HH_LDDEC _TIE_xt_MAC16_MULA_DD_HH_LDDEC
#define XT_MULA_DD_HH_LDINC _TIE_xt_MAC16_MULA_DD_HH_LDINC
#define XT_LDDEC _TIE_xt_MAC16_LDDEC
#define XT_ULDDEC _TIE_xt_MAC16_ULDDEC
#define XT_SLDDEC _TIE_xt_MAC16_SLDDEC
#define XT_LDINC _TIE_xt_MAC16_LDINC
#define XT_ULDINC _TIE_xt_MAC16_ULDINC
#define XT_SLDINC _TIE_xt_MAC16_SLDINC
#define XT_RSR16 _TIE_xt_MAC16_RSR16
#define XT_WSR16 _TIE_xt_MAC16_WSR16
#define XT_XSR16 _TIE_xt_MAC16_XSR16
#define XT_RSR17 _TIE_xt_MAC16_RSR17
#define XT_WSR17 _TIE_xt_MAC16_WSR17
#define XT_XSR17 _TIE_xt_MAC16_XSR17
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_MAC16_HEADER */

24
components/esp32/include/xtensa/tie/xt_MUL32.h
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/* Definitions for the 32-bit Integer Multiply Option. */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2009 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* NOTE: This file exists only for backward compatibility with RB-200X.x
and earlier Xtensa releases. Starting with RC-2009.0 you should use
<xtensa/tie/xt_mul.h>. */
#ifndef _XTENSA_xt_MUL32_HEADER
#define _XTENSA_xt_MUL32_HEADER
#ifdef __XTENSA__
#include <xtensa/tie/xt_mul.h>
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_MUL32_HEADER */

69
components/esp32/include/xtensa/tie/xt_booleans.h
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/* Definitions for the xt_booleans TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_booleans_HEADER
#define _XTENSA_xt_booleans_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
typedef _TIE_xtbool xtbool;
typedef _TIE_xtbool2 xtbool2;
typedef _TIE_xtbool4 xtbool4;
typedef _TIE_xtbool8 xtbool8;
typedef _TIE_xtbool16 xtbool16;
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern xtbool _TIE_xt_booleans_XORB(xtbool bs, xtbool bt);
extern xtbool _TIE_xt_booleans_ORBC(xtbool bs, xtbool bt);
extern xtbool _TIE_xt_booleans_ORB(xtbool bs, xtbool bt);
extern xtbool _TIE_xt_booleans_ANDBC(xtbool bs, xtbool bt);
extern xtbool _TIE_xt_booleans_ANDB(xtbool bs, xtbool bt);
extern xtbool _TIE_xt_booleans_ALL4(xtbool4 bs4);
extern xtbool _TIE_xt_booleans_ANY4(xtbool4 bs4);
extern xtbool _TIE_xt_booleans_ALL8(xtbool8 bs8);
extern xtbool _TIE_xt_booleans_ANY8(xtbool8 bs8);
extern void _TIE_xt_booleans_MOVT(unsigned arr /*inout*/, unsigned ars, xtbool bt);
extern void _TIE_xt_booleans_MOVF(unsigned arr /*inout*/, unsigned ars, xtbool bt);
#define XT_XORB _TIE_xt_booleans_XORB
#define XT_ORBC _TIE_xt_booleans_ORBC
#define XT_ORB _TIE_xt_booleans_ORB
#define XT_ANDBC _TIE_xt_booleans_ANDBC
#define XT_ANDB _TIE_xt_booleans_ANDB
#define XT_ALL4 _TIE_xt_booleans_ALL4
#define XT_ANY4 _TIE_xt_booleans_ANY4
#define XT_ALL8 _TIE_xt_booleans_ALL8
#define XT_ANY8 _TIE_xt_booleans_ANY8
#define XT_MOVT _TIE_xt_booleans_MOVT
#define XT_MOVF _TIE_xt_booleans_MOVF
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_booleans_HEADER */

48
components/esp32/include/xtensa/tie/xt_coprocessors.h
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@@ -1,48 +0,0 @@
/* Definitions for the xt_coprocessors TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_coprocessors_HEADER
#define _XTENSA_xt_coprocessors_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_coprocessors_RSR_CPENABLE(void);
extern void _TIE_xt_coprocessors_WSR_CPENABLE(unsigned art);
extern void _TIE_xt_coprocessors_XSR_CPENABLE(unsigned art /*inout*/);
#define XT_RSR_CPENABLE _TIE_xt_coprocessors_RSR_CPENABLE
#define XT_WSR_CPENABLE _TIE_xt_coprocessors_WSR_CPENABLE
#define XT_XSR_CPENABLE _TIE_xt_coprocessors_XSR_CPENABLE
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_coprocessors_HEADER */

395
components/esp32/include/xtensa/tie/xt_core.h
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@@ -1,395 +0,0 @@
/* Definitions for the xt_core TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_core_HEADER
#define _XTENSA_xt_core_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_core_ILL(void);
extern void _TIE_xt_core_NOP(void);
extern void _TIE_xt_core_SIMCALL(void);
extern void _TIE_xt_core_MEMW(void);
extern void _TIE_xt_core_EXTW(void);
extern void _TIE_xt_core_ISYNC(void);
extern void _TIE_xt_core_DSYNC(void);
extern void _TIE_xt_core_ESYNC(void);
extern void _TIE_xt_core_RSYNC(void);
extern unsigned _TIE_xt_core_RSR_LBEG(void);
extern void _TIE_xt_core_WSR_LBEG(unsigned art);
extern void _TIE_xt_core_XSR_LBEG(unsigned art /*inout*/);
extern unsigned _TIE_xt_core_RSR_CONFIGID0(void);
extern void _TIE_xt_core_WSR_CONFIGID0(unsigned art);
extern unsigned _TIE_xt_core_RSR_CONFIGID1(void);
extern unsigned _TIE_xt_core_RUR_THREADPTR(void);
extern void _TIE_xt_core_WUR_THREADPTR(unsigned v);
extern unsigned _TIE_xt_core_uint32_loadi(const unsigned * p, immediate o);
extern void _TIE_xt_core_uint32_storei(unsigned c, unsigned * p, immediate o);
extern unsigned _TIE_xt_core_uint32_move(unsigned b);
extern int _TIE_xt_core_ADDI(int s, immediate i);
extern int _TIE_xt_core_OR(int s, int t);
extern int _TIE_xt_core_L32I(const int * p, immediate i);
extern void _TIE_xt_core_S32I(int r, int * p, immediate i);
extern void _TIE_xt_core_S32NB(int r, int * p, immediate i);
extern unsigned char _TIE_xt_core_L8UI(const unsigned char * p, immediate i);
extern void _TIE_xt_core_S8I(signed char r, signed char * p, immediate i);
extern unsigned short _TIE_xt_core_L16UI(const unsigned short * p, immediate i);
extern short _TIE_xt_core_L16SI(const short * p, immediate i);
extern void _TIE_xt_core_S16I(short r, short * p, immediate i);
extern int _TIE_xt_core_ADDMI(int s, immediate i);
extern int _TIE_xt_core_ADD(int s, int t);
extern int _TIE_xt_core_ADDX2(int s, int t);
extern int _TIE_xt_core_ADDX4(int s, int t);
extern int _TIE_xt_core_ADDX8(int s, int t);
extern int _TIE_xt_core_SUB(int s, int t);
extern int _TIE_xt_core_SUBX2(int s, int t);
extern int _TIE_xt_core_SUBX4(int s, int t);
extern int _TIE_xt_core_SUBX8(int s, int t);
extern int _TIE_xt_core_AND(int s, int t);
extern int _TIE_xt_core_XOR(int s, int t);
extern unsigned _TIE_xt_core_EXTUI(unsigned t, immediate i, immediate o);
extern int _TIE_xt_core_MOVI(immediate i);
extern void _TIE_xt_core_MOVEQZ(int r /*inout*/, int s, int t);
extern void _TIE_xt_core_MOVNEZ(int r /*inout*/, int s, int t);
extern void _TIE_xt_core_MOVLTZ(int r /*inout*/, int s, int t);
extern void _TIE_xt_core_MOVGEZ(int r /*inout*/, int s, int t);
extern int _TIE_xt_core_NEG(int t);
extern int _TIE_xt_core_ABS(int t);
extern void _TIE_xt_core_SSR(int s);
extern void _TIE_xt_core_SSL(int s);
extern void _TIE_xt_core_SSA8L(int s);
extern void _TIE_xt_core_SSA8B(int s);
extern void _TIE_xt_core_SSAI(immediate i);
extern int _TIE_xt_core_SLL(int s);
extern int _TIE_xt_core_SRC(int s, int t);
extern unsigned _TIE_xt_core_SRL(unsigned t);
extern int _TIE_xt_core_SRA(int t);
extern int _TIE_xt_core_SLLI(int s, immediate i);
extern int _TIE_xt_core_SRAI(int t, immediate i);
extern unsigned _TIE_xt_core_SRLI(unsigned t, immediate i);
extern int _TIE_xt_core_SSAI_SRC(int src1, int src2, immediate amount);
extern int _TIE_xt_core_SSR_SRC(int src1, int src2, int amount);
extern int _TIE_xt_core_WSR_SAR_SRC(int src1, int src2, int amount);
extern int _TIE_xt_core_SSR_SRA(int src, int amount);
extern unsigned _TIE_xt_core_SSR_SRL(unsigned src, int amount);
extern int _TIE_xt_core_SSL_SLL(int src, int amount);
extern int _TIE_xt_core_RSIL(immediate t);
extern int _TIE_xt_core_RSR_LEND(void);
extern void _TIE_xt_core_WSR_LEND(int t);
extern void _TIE_xt_core_XSR_LEND(int t /*inout*/);
extern int _TIE_xt_core_RSR_LCOUNT(void);
extern void _TIE_xt_core_WSR_LCOUNT(int t);
extern void _TIE_xt_core_XSR_LCOUNT(int t /*inout*/);
extern unsigned _TIE_xt_core_RSR_SAR(void);
extern void _TIE_xt_core_WSR_SAR(unsigned t);
extern void _TIE_xt_core_XSR_SAR(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_MEMCTL(void);
extern void _TIE_xt_core_WSR_MEMCTL(unsigned t);
extern void _TIE_xt_core_XSR_MEMCTL(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_LITBASE(void);
extern void _TIE_xt_core_WSR_LITBASE(unsigned t);
extern void _TIE_xt_core_XSR_LITBASE(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_PS(void);
extern void _TIE_xt_core_WSR_PS(unsigned t);
extern void _TIE_xt_core_XSR_PS(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC1(void);
extern void _TIE_xt_core_WSR_EPC1(unsigned t);
extern void _TIE_xt_core_XSR_EPC1(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE1(void);
extern void _TIE_xt_core_WSR_EXCSAVE1(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE1(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC2(void);
extern void _TIE_xt_core_WSR_EPC2(unsigned t);
extern void _TIE_xt_core_XSR_EPC2(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE2(void);
extern void _TIE_xt_core_WSR_EXCSAVE2(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE2(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC3(void);
extern void _TIE_xt_core_WSR_EPC3(unsigned t);
extern void _TIE_xt_core_XSR_EPC3(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE3(void);
extern void _TIE_xt_core_WSR_EXCSAVE3(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE3(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC4(void);
extern void _TIE_xt_core_WSR_EPC4(unsigned t);
extern void _TIE_xt_core_XSR_EPC4(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE4(void);
extern void _TIE_xt_core_WSR_EXCSAVE4(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE4(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC5(void);
extern void _TIE_xt_core_WSR_EPC5(unsigned t);
extern void _TIE_xt_core_XSR_EPC5(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE5(void);
extern void _TIE_xt_core_WSR_EXCSAVE5(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE5(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC6(void);
extern void _TIE_xt_core_WSR_EPC6(unsigned t);
extern void _TIE_xt_core_XSR_EPC6(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE6(void);
extern void _TIE_xt_core_WSR_EXCSAVE6(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE6(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPC7(void);
extern void _TIE_xt_core_WSR_EPC7(unsigned t);
extern void _TIE_xt_core_XSR_EPC7(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCSAVE7(void);
extern void _TIE_xt_core_WSR_EXCSAVE7(unsigned t);
extern void _TIE_xt_core_XSR_EXCSAVE7(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_VECBASE(void);
extern void _TIE_xt_core_WSR_VECBASE(unsigned t);
extern void _TIE_xt_core_XSR_VECBASE(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPS2(void);
extern void _TIE_xt_core_WSR_EPS2(unsigned t);
extern void _TIE_xt_core_XSR_EPS2(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPS3(void);
extern void _TIE_xt_core_WSR_EPS3(unsigned t);
extern void _TIE_xt_core_XSR_EPS3(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPS4(void);
extern void _TIE_xt_core_WSR_EPS4(unsigned t);
extern void _TIE_xt_core_XSR_EPS4(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPS5(void);
extern void _TIE_xt_core_WSR_EPS5(unsigned t);
extern void _TIE_xt_core_XSR_EPS5(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPS6(void);
extern void _TIE_xt_core_WSR_EPS6(unsigned t);
extern void _TIE_xt_core_XSR_EPS6(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EPS7(void);
extern void _TIE_xt_core_WSR_EPS7(unsigned t);
extern void _TIE_xt_core_XSR_EPS7(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCCAUSE(void);
extern void _TIE_xt_core_WSR_EXCCAUSE(unsigned t);
extern void _TIE_xt_core_XSR_EXCCAUSE(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_EXCVADDR(void);
extern void _TIE_xt_core_WSR_EXCVADDR(unsigned t);
extern void _TIE_xt_core_XSR_EXCVADDR(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_DEPC(void);
extern void _TIE_xt_core_WSR_DEPC(unsigned t);
extern void _TIE_xt_core_XSR_DEPC(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_MISC0(void);
extern void _TIE_xt_core_WSR_MISC0(unsigned t);
extern void _TIE_xt_core_XSR_MISC0(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_MISC1(void);
extern void _TIE_xt_core_WSR_MISC1(unsigned t);
extern void _TIE_xt_core_XSR_MISC1(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_MISC2(void);
extern void _TIE_xt_core_WSR_MISC2(unsigned t);
extern void _TIE_xt_core_XSR_MISC2(unsigned t /*inout*/);
extern unsigned _TIE_xt_core_RSR_MISC3(void);
extern void _TIE_xt_core_WSR_MISC3(unsigned t);
extern void _TIE_xt_core_XSR_MISC3(unsigned t /*inout*/);
extern int _TIE_xt_core_RSR_PRID(void);
#define XT_ILL _TIE_xt_core_ILL
#define XT_NOP _TIE_xt_core_NOP
#define XT_SIMCALL _TIE_xt_core_SIMCALL
#define XT_MEMW _TIE_xt_core_MEMW
#define XT_EXTW _TIE_xt_core_EXTW
#define XT_ISYNC _TIE_xt_core_ISYNC
#define XT_DSYNC _TIE_xt_core_DSYNC
#define XT_ESYNC _TIE_xt_core_ESYNC
#define XT_RSYNC _TIE_xt_core_RSYNC
#define XT_RSR_LBEG _TIE_xt_core_RSR_LBEG
#define XT_WSR_LBEG _TIE_xt_core_WSR_LBEG
#define XT_XSR_LBEG _TIE_xt_core_XSR_LBEG
#define XT_RSR_CONFIGID0 _TIE_xt_core_RSR_CONFIGID0
#define XT_WSR_CONFIGID0 _TIE_xt_core_WSR_CONFIGID0
#define XT_RSR_CONFIGID1 _TIE_xt_core_RSR_CONFIGID1
#define XT_RUR_THREADPTR _TIE_xt_core_RUR_THREADPTR
#define RTHREADPTR _TIE_xt_core_RUR_THREADPTR
#define RUR231 _TIE_xt_core_RUR_THREADPTR
#define XT_WUR_THREADPTR _TIE_xt_core_WUR_THREADPTR
#define WTHREADPTR _TIE_xt_core_WUR_THREADPTR
#define WUR231 _TIE_xt_core_WUR_THREADPTR
#define XT_uint32_loadi _TIE_xt_core_uint32_loadi
#define XT_uint32_storei _TIE_xt_core_uint32_storei
#define XT_uint32_move _TIE_xt_core_uint32_move
#define XT_ADDI _TIE_xt_core_ADDI
#define XT_OR _TIE_xt_core_OR
#define XT_L32I _TIE_xt_core_L32I
#define XT_S32I _TIE_xt_core_S32I
#define XT_S32NB _TIE_xt_core_S32NB
#define XT_L8UI _TIE_xt_core_L8UI
#define XT_S8I _TIE_xt_core_S8I
#define XT_L16UI _TIE_xt_core_L16UI
#define XT_L16SI _TIE_xt_core_L16SI
#define XT_S16I _TIE_xt_core_S16I
#define XT_ADDMI _TIE_xt_core_ADDMI
#define XT_ADD _TIE_xt_core_ADD
#define XT_ADDX2 _TIE_xt_core_ADDX2
#define XT_ADDX4 _TIE_xt_core_ADDX4
#define XT_ADDX8 _TIE_xt_core_ADDX8
#define XT_SUB _TIE_xt_core_SUB
#define XT_SUBX2 _TIE_xt_core_SUBX2
#define XT_SUBX4 _TIE_xt_core_SUBX4
#define XT_SUBX8 _TIE_xt_core_SUBX8
#define XT_AND _TIE_xt_core_AND
#define XT_XOR _TIE_xt_core_XOR
#define XT_EXTUI _TIE_xt_core_EXTUI
#define XT_MOVI _TIE_xt_core_MOVI
#define XT_MOVEQZ _TIE_xt_core_MOVEQZ
#define XT_MOVNEZ _TIE_xt_core_MOVNEZ
#define XT_MOVLTZ _TIE_xt_core_MOVLTZ
#define XT_MOVGEZ _TIE_xt_core_MOVGEZ
#define XT_NEG _TIE_xt_core_NEG
#define XT_ABS _TIE_xt_core_ABS
#define XT_SSR _TIE_xt_core_SSR
#define XT_SSL _TIE_xt_core_SSL
#define XT_SSA8L _TIE_xt_core_SSA8L
#define XT_SSA8B _TIE_xt_core_SSA8B
#define XT_SSAI _TIE_xt_core_SSAI
#define XT_SLL _TIE_xt_core_SLL
#define XT_SRC _TIE_xt_core_SRC
#define XT_SRL _TIE_xt_core_SRL
#define XT_SRA _TIE_xt_core_SRA
#define XT_SLLI _TIE_xt_core_SLLI
#define XT_SRAI _TIE_xt_core_SRAI
#define XT_SRLI _TIE_xt_core_SRLI
#define XT_SSAI_SRC _TIE_xt_core_SSAI_SRC
#define XT_SSR_SRC _TIE_xt_core_SSR_SRC
#define XT_WSR_SAR_SRC _TIE_xt_core_WSR_SAR_SRC
#define XT_SSR_SRA _TIE_xt_core_SSR_SRA
#define XT_SSR_SRL _TIE_xt_core_SSR_SRL
#define XT_SSL_SLL _TIE_xt_core_SSL_SLL
#define XT_RSIL _TIE_xt_core_RSIL
#define XT_RSR_LEND _TIE_xt_core_RSR_LEND
#define XT_WSR_LEND _TIE_xt_core_WSR_LEND
#define XT_XSR_LEND _TIE_xt_core_XSR_LEND
#define XT_RSR_LCOUNT _TIE_xt_core_RSR_LCOUNT
#define XT_WSR_LCOUNT _TIE_xt_core_WSR_LCOUNT
#define XT_XSR_LCOUNT _TIE_xt_core_XSR_LCOUNT
#define XT_RSR_SAR _TIE_xt_core_RSR_SAR
#define XT_WSR_SAR _TIE_xt_core_WSR_SAR
#define XT_XSR_SAR _TIE_xt_core_XSR_SAR
#define XT_RSR_MEMCTL _TIE_xt_core_RSR_MEMCTL
#define XT_WSR_MEMCTL _TIE_xt_core_WSR_MEMCTL
#define XT_XSR_MEMCTL _TIE_xt_core_XSR_MEMCTL
#define XT_RSR_LITBASE _TIE_xt_core_RSR_LITBASE
#define XT_WSR_LITBASE _TIE_xt_core_WSR_LITBASE
#define XT_XSR_LITBASE _TIE_xt_core_XSR_LITBASE
#define XT_RSR_PS _TIE_xt_core_RSR_PS
#define XT_WSR_PS _TIE_xt_core_WSR_PS
#define XT_XSR_PS _TIE_xt_core_XSR_PS
#define XT_RSR_EPC1 _TIE_xt_core_RSR_EPC1
#define XT_WSR_EPC1 _TIE_xt_core_WSR_EPC1
#define XT_XSR_EPC1 _TIE_xt_core_XSR_EPC1
#define XT_RSR_EXCSAVE1 _TIE_xt_core_RSR_EXCSAVE1
#define XT_WSR_EXCSAVE1 _TIE_xt_core_WSR_EXCSAVE1
#define XT_XSR_EXCSAVE1 _TIE_xt_core_XSR_EXCSAVE1
#define XT_RSR_EPC2 _TIE_xt_core_RSR_EPC2
#define XT_WSR_EPC2 _TIE_xt_core_WSR_EPC2
#define XT_XSR_EPC2 _TIE_xt_core_XSR_EPC2
#define XT_RSR_EXCSAVE2 _TIE_xt_core_RSR_EXCSAVE2
#define XT_WSR_EXCSAVE2 _TIE_xt_core_WSR_EXCSAVE2
#define XT_XSR_EXCSAVE2 _TIE_xt_core_XSR_EXCSAVE2
#define XT_RSR_EPC3 _TIE_xt_core_RSR_EPC3
#define XT_WSR_EPC3 _TIE_xt_core_WSR_EPC3
#define XT_XSR_EPC3 _TIE_xt_core_XSR_EPC3
#define XT_RSR_EXCSAVE3 _TIE_xt_core_RSR_EXCSAVE3
#define XT_WSR_EXCSAVE3 _TIE_xt_core_WSR_EXCSAVE3
#define XT_XSR_EXCSAVE3 _TIE_xt_core_XSR_EXCSAVE3
#define XT_RSR_EPC4 _TIE_xt_core_RSR_EPC4
#define XT_WSR_EPC4 _TIE_xt_core_WSR_EPC4
#define XT_XSR_EPC4 _TIE_xt_core_XSR_EPC4
#define XT_RSR_EXCSAVE4 _TIE_xt_core_RSR_EXCSAVE4
#define XT_WSR_EXCSAVE4 _TIE_xt_core_WSR_EXCSAVE4
#define XT_XSR_EXCSAVE4 _TIE_xt_core_XSR_EXCSAVE4
#define XT_RSR_EPC5 _TIE_xt_core_RSR_EPC5
#define XT_WSR_EPC5 _TIE_xt_core_WSR_EPC5
#define XT_XSR_EPC5 _TIE_xt_core_XSR_EPC5
#define XT_RSR_EXCSAVE5 _TIE_xt_core_RSR_EXCSAVE5
#define XT_WSR_EXCSAVE5 _TIE_xt_core_WSR_EXCSAVE5
#define XT_XSR_EXCSAVE5 _TIE_xt_core_XSR_EXCSAVE5
#define XT_RSR_EPC6 _TIE_xt_core_RSR_EPC6
#define XT_WSR_EPC6 _TIE_xt_core_WSR_EPC6
#define XT_XSR_EPC6 _TIE_xt_core_XSR_EPC6
#define XT_RSR_EXCSAVE6 _TIE_xt_core_RSR_EXCSAVE6
#define XT_WSR_EXCSAVE6 _TIE_xt_core_WSR_EXCSAVE6
#define XT_XSR_EXCSAVE6 _TIE_xt_core_XSR_EXCSAVE6
#define XT_RSR_EPC7 _TIE_xt_core_RSR_EPC7
#define XT_WSR_EPC7 _TIE_xt_core_WSR_EPC7
#define XT_XSR_EPC7 _TIE_xt_core_XSR_EPC7
#define XT_RSR_EXCSAVE7 _TIE_xt_core_RSR_EXCSAVE7
#define XT_WSR_EXCSAVE7 _TIE_xt_core_WSR_EXCSAVE7
#define XT_XSR_EXCSAVE7 _TIE_xt_core_XSR_EXCSAVE7
#define XT_RSR_VECBASE _TIE_xt_core_RSR_VECBASE
#define XT_WSR_VECBASE _TIE_xt_core_WSR_VECBASE
#define XT_XSR_VECBASE _TIE_xt_core_XSR_VECBASE
#define XT_RSR_EPS2 _TIE_xt_core_RSR_EPS2
#define XT_WSR_EPS2 _TIE_xt_core_WSR_EPS2
#define XT_XSR_EPS2 _TIE_xt_core_XSR_EPS2
#define XT_RSR_EPS3 _TIE_xt_core_RSR_EPS3
#define XT_WSR_EPS3 _TIE_xt_core_WSR_EPS3
#define XT_XSR_EPS3 _TIE_xt_core_XSR_EPS3
#define XT_RSR_EPS4 _TIE_xt_core_RSR_EPS4
#define XT_WSR_EPS4 _TIE_xt_core_WSR_EPS4
#define XT_XSR_EPS4 _TIE_xt_core_XSR_EPS4
#define XT_RSR_EPS5 _TIE_xt_core_RSR_EPS5
#define XT_WSR_EPS5 _TIE_xt_core_WSR_EPS5
#define XT_XSR_EPS5 _TIE_xt_core_XSR_EPS5
#define XT_RSR_EPS6 _TIE_xt_core_RSR_EPS6
#define XT_WSR_EPS6 _TIE_xt_core_WSR_EPS6
#define XT_XSR_EPS6 _TIE_xt_core_XSR_EPS6
#define XT_RSR_EPS7 _TIE_xt_core_RSR_EPS7
#define XT_WSR_EPS7 _TIE_xt_core_WSR_EPS7
#define XT_XSR_EPS7 _TIE_xt_core_XSR_EPS7
#define XT_RSR_EXCCAUSE _TIE_xt_core_RSR_EXCCAUSE
#define XT_WSR_EXCCAUSE _TIE_xt_core_WSR_EXCCAUSE
#define XT_XSR_EXCCAUSE _TIE_xt_core_XSR_EXCCAUSE
#define XT_RSR_EXCVADDR _TIE_xt_core_RSR_EXCVADDR
#define XT_WSR_EXCVADDR _TIE_xt_core_WSR_EXCVADDR
#define XT_XSR_EXCVADDR _TIE_xt_core_XSR_EXCVADDR
#define XT_RSR_DEPC _TIE_xt_core_RSR_DEPC
#define XT_WSR_DEPC _TIE_xt_core_WSR_DEPC
#define XT_XSR_DEPC _TIE_xt_core_XSR_DEPC
#define XT_RSR_MISC0 _TIE_xt_core_RSR_MISC0
#define XT_WSR_MISC0 _TIE_xt_core_WSR_MISC0
#define XT_XSR_MISC0 _TIE_xt_core_XSR_MISC0
#define XT_RSR_MISC1 _TIE_xt_core_RSR_MISC1
#define XT_WSR_MISC1 _TIE_xt_core_WSR_MISC1
#define XT_XSR_MISC1 _TIE_xt_core_XSR_MISC1
#define XT_RSR_MISC2 _TIE_xt_core_RSR_MISC2
#define XT_WSR_MISC2 _TIE_xt_core_WSR_MISC2
#define XT_XSR_MISC2 _TIE_xt_core_XSR_MISC2
#define XT_RSR_MISC3 _TIE_xt_core_RSR_MISC3
#define XT_WSR_MISC3 _TIE_xt_core_WSR_MISC3
#define XT_XSR_MISC3 _TIE_xt_core_XSR_MISC3
#define XT_RSR_PRID _TIE_xt_core_RSR_PRID
#ifndef RUR
#define RUR(NUM) RUR##NUM()
#endif
#ifndef WUR
#define WUR(VAL, NUM) WUR##NUM(VAL)
#endif
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_core_HEADER */

116
components/esp32/include/xtensa/tie/xt_debug.h
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@@ -1,116 +0,0 @@
/* Definitions for the xt_debug TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_debug_HEADER
#define _XTENSA_xt_debug_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_debug_BREAK(immediate imms, immediate immt);
extern void _TIE_xt_debug_BREAK_N(immediate imms);
extern unsigned _TIE_xt_debug_RSR_DBREAKA0(void);
extern void _TIE_xt_debug_WSR_DBREAKA0(unsigned art);
extern void _TIE_xt_debug_XSR_DBREAKA0(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_DBREAKC0(void);
extern void _TIE_xt_debug_WSR_DBREAKC0(unsigned art);
extern void _TIE_xt_debug_XSR_DBREAKC0(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_DBREAKA1(void);
extern void _TIE_xt_debug_WSR_DBREAKA1(unsigned art);
extern void _TIE_xt_debug_XSR_DBREAKA1(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_DBREAKC1(void);
extern void _TIE_xt_debug_WSR_DBREAKC1(unsigned art);
extern void _TIE_xt_debug_XSR_DBREAKC1(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_IBREAKA0(void);
extern void _TIE_xt_debug_WSR_IBREAKA0(unsigned art);
extern void _TIE_xt_debug_XSR_IBREAKA0(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_IBREAKA1(void);
extern void _TIE_xt_debug_WSR_IBREAKA1(unsigned art);
extern void _TIE_xt_debug_XSR_IBREAKA1(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_IBREAKENABLE(void);
extern void _TIE_xt_debug_WSR_IBREAKENABLE(unsigned art);
extern void _TIE_xt_debug_XSR_IBREAKENABLE(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_DEBUGCAUSE(void);
extern void _TIE_xt_debug_WSR_DEBUGCAUSE(unsigned art);
extern void _TIE_xt_debug_XSR_DEBUGCAUSE(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_ICOUNT(void);
extern void _TIE_xt_debug_WSR_ICOUNT(unsigned art);
extern void _TIE_xt_debug_XSR_ICOUNT(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_ICOUNTLEVEL(void);
extern void _TIE_xt_debug_WSR_ICOUNTLEVEL(unsigned art);
extern void _TIE_xt_debug_XSR_ICOUNTLEVEL(unsigned art /*inout*/);
extern unsigned _TIE_xt_debug_RSR_DDR(void);
extern void _TIE_xt_debug_WSR_DDR(unsigned art);
extern void _TIE_xt_debug_XSR_DDR(unsigned art /*inout*/);
extern void _TIE_xt_debug_LDDR32_P(const void * ars /*inout*/);
extern void _TIE_xt_debug_SDDR32_P(void * ars /*inout*/);
#define XT_BREAK _TIE_xt_debug_BREAK
#define XT_BREAK_N _TIE_xt_debug_BREAK_N
#define XT_RSR_DBREAKA0 _TIE_xt_debug_RSR_DBREAKA0
#define XT_WSR_DBREAKA0 _TIE_xt_debug_WSR_DBREAKA0
#define XT_XSR_DBREAKA0 _TIE_xt_debug_XSR_DBREAKA0
#define XT_RSR_DBREAKC0 _TIE_xt_debug_RSR_DBREAKC0
#define XT_WSR_DBREAKC0 _TIE_xt_debug_WSR_DBREAKC0
#define XT_XSR_DBREAKC0 _TIE_xt_debug_XSR_DBREAKC0
#define XT_RSR_DBREAKA1 _TIE_xt_debug_RSR_DBREAKA1
#define XT_WSR_DBREAKA1 _TIE_xt_debug_WSR_DBREAKA1
#define XT_XSR_DBREAKA1 _TIE_xt_debug_XSR_DBREAKA1
#define XT_RSR_DBREAKC1 _TIE_xt_debug_RSR_DBREAKC1
#define XT_WSR_DBREAKC1 _TIE_xt_debug_WSR_DBREAKC1
#define XT_XSR_DBREAKC1 _TIE_xt_debug_XSR_DBREAKC1
#define XT_RSR_IBREAKA0 _TIE_xt_debug_RSR_IBREAKA0
#define XT_WSR_IBREAKA0 _TIE_xt_debug_WSR_IBREAKA0
#define XT_XSR_IBREAKA0 _TIE_xt_debug_XSR_IBREAKA0
#define XT_RSR_IBREAKA1 _TIE_xt_debug_RSR_IBREAKA1
#define XT_WSR_IBREAKA1 _TIE_xt_debug_WSR_IBREAKA1
#define XT_XSR_IBREAKA1 _TIE_xt_debug_XSR_IBREAKA1
#define XT_RSR_IBREAKENABLE _TIE_xt_debug_RSR_IBREAKENABLE
#define XT_WSR_IBREAKENABLE _TIE_xt_debug_WSR_IBREAKENABLE
#define XT_XSR_IBREAKENABLE _TIE_xt_debug_XSR_IBREAKENABLE
#define XT_RSR_DEBUGCAUSE _TIE_xt_debug_RSR_DEBUGCAUSE
#define XT_WSR_DEBUGCAUSE _TIE_xt_debug_WSR_DEBUGCAUSE
#define XT_XSR_DEBUGCAUSE _TIE_xt_debug_XSR_DEBUGCAUSE
#define XT_RSR_ICOUNT _TIE_xt_debug_RSR_ICOUNT
#define XT_WSR_ICOUNT _TIE_xt_debug_WSR_ICOUNT
#define XT_XSR_ICOUNT _TIE_xt_debug_XSR_ICOUNT
#define XT_RSR_ICOUNTLEVEL _TIE_xt_debug_RSR_ICOUNTLEVEL
#define XT_WSR_ICOUNTLEVEL _TIE_xt_debug_WSR_ICOUNTLEVEL
#define XT_XSR_ICOUNTLEVEL _TIE_xt_debug_XSR_ICOUNTLEVEL
#define XT_RSR_DDR _TIE_xt_debug_RSR_DDR
#define XT_WSR_DDR _TIE_xt_debug_WSR_DDR
#define XT_XSR_DDR _TIE_xt_debug_XSR_DDR
#define XT_LDDR32_P _TIE_xt_debug_LDDR32_P
#define XT_SDDR32_P _TIE_xt_debug_SDDR32_P
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_debug_HEADER */

58
components/esp32/include/xtensa/tie/xt_density.h
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@@ -1,58 +0,0 @@
/* Definitions for the xt_density TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_density_HEADER
#define _XTENSA_xt_density_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_density_ILL_N(void);
extern void _TIE_xt_density_NOP_N(void);
extern int _TIE_xt_density_L32I_N(const int * p, immediate i);
extern void _TIE_xt_density_S32I_N(int t, int * p, immediate i);
extern int _TIE_xt_density_ADD_N(int s, int t);
extern int _TIE_xt_density_ADDI_N(int s, immediate i);
extern int _TIE_xt_density_MOV_N(int s);
extern int _TIE_xt_density_MOVI_N(immediate i);
#define XT_ILL_N _TIE_xt_density_ILL_N
#define XT_NOP_N _TIE_xt_density_NOP_N
#define XT_L32I_N _TIE_xt_density_L32I_N
#define XT_S32I_N _TIE_xt_density_S32I_N
#define XT_ADD_N _TIE_xt_density_ADD_N
#define XT_ADDI_N _TIE_xt_density_ADDI_N
#define XT_MOV_N _TIE_xt_density_MOV_N
#define XT_MOVI_N _TIE_xt_density_MOVI_N
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_density_HEADER */

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components/esp32/include/xtensa/tie/xt_exceptions.h
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/* Definitions for the xt_exceptions TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_exceptions_HEADER
#define _XTENSA_xt_exceptions_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_exceptions_EXCW(void);
extern void _TIE_xt_exceptions_SYSCALL(void);
#define XT_EXCW _TIE_xt_exceptions_EXCW
#define XT_SYSCALL _TIE_xt_exceptions_SYSCALL
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_exceptions_HEADER */

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components/esp32/include/xtensa/tie/xt_externalregisters.h
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/* Definitions for the xt_externalregisters TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_externalregisters_HEADER
#define _XTENSA_xt_externalregisters_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_externalregisters_RER(unsigned ars);
extern void _TIE_xt_externalregisters_WER(unsigned art, unsigned ars);
#define XT_RER _TIE_xt_externalregisters_RER
#define XT_WER _TIE_xt_externalregisters_WER
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_externalregisters_HEADER */

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components/esp32/include/xtensa/tie/xt_integerdivide.h
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/* Definitions for the xt_integerdivide TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_integerdivide_HEADER
#define _XTENSA_xt_integerdivide_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_integerdivide_REMS(unsigned ars, unsigned art);
extern unsigned _TIE_xt_integerdivide_REMU(unsigned ars, unsigned art);
extern unsigned _TIE_xt_integerdivide_QUOS(unsigned ars, unsigned art);
extern unsigned _TIE_xt_integerdivide_QUOU(unsigned ars, unsigned art);
#define XT_REMS _TIE_xt_integerdivide_REMS
#define XT_REMU _TIE_xt_integerdivide_REMU
#define XT_QUOS _TIE_xt_integerdivide_QUOS
#define XT_QUOU _TIE_xt_integerdivide_QUOU
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_integerdivide_HEADER */

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components/esp32/include/xtensa/tie/xt_interrupt.h
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/* Definitions for the xt_interrupt TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_interrupt_HEADER
#define _XTENSA_xt_interrupt_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_interrupt_WAITI(immediate s);
extern unsigned _TIE_xt_interrupt_RSR_INTERRUPT(void);
extern void _TIE_xt_interrupt_WSR_INTSET(unsigned art);
extern void _TIE_xt_interrupt_WSR_INTCLEAR(unsigned art);
extern unsigned _TIE_xt_interrupt_RSR_INTENABLE(void);
extern void _TIE_xt_interrupt_WSR_INTENABLE(unsigned art);
extern void _TIE_xt_interrupt_XSR_INTENABLE(unsigned art /*inout*/);
#define XT_WAITI _TIE_xt_interrupt_WAITI
#define XT_RSR_INTERRUPT _TIE_xt_interrupt_RSR_INTERRUPT
#define XT_WSR_INTSET _TIE_xt_interrupt_WSR_INTSET
#define XT_WSR_INTCLEAR _TIE_xt_interrupt_WSR_INTCLEAR
#define XT_RSR_INTENABLE _TIE_xt_interrupt_RSR_INTENABLE
#define XT_WSR_INTENABLE _TIE_xt_interrupt_WSR_INTENABLE
#define XT_XSR_INTENABLE _TIE_xt_interrupt_XSR_INTENABLE
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_interrupt_HEADER */

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components/esp32/include/xtensa/tie/xt_ioports.h
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/* Definitions for the xt_ioports TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_ioports_HEADER
#define _XTENSA_xt_ioports_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_ioports_READ_IMPWIRE(void);
extern void _TIE_xt_ioports_SETB_EXPSTATE(immediate bitindex);
extern void _TIE_xt_ioports_CLRB_EXPSTATE(immediate bitindex);
extern void _TIE_xt_ioports_WRMSK_EXPSTATE(unsigned art, unsigned ars);
extern unsigned _TIE_xt_ioports_RUR_EXPSTATE(void);
extern void _TIE_xt_ioports_WUR_EXPSTATE(unsigned v);
#define READ_IMPWIRE _TIE_xt_ioports_READ_IMPWIRE
#define SETB_EXPSTATE _TIE_xt_ioports_SETB_EXPSTATE
#define CLRB_EXPSTATE _TIE_xt_ioports_CLRB_EXPSTATE
#define WRMSK_EXPSTATE _TIE_xt_ioports_WRMSK_EXPSTATE
#define RUR_EXPSTATE _TIE_xt_ioports_RUR_EXPSTATE
#define REXPSTATE _TIE_xt_ioports_RUR_EXPSTATE
#define RUR230 _TIE_xt_ioports_RUR_EXPSTATE
#define WUR_EXPSTATE _TIE_xt_ioports_WUR_EXPSTATE
#define WEXPSTATE _TIE_xt_ioports_WUR_EXPSTATE
#define WUR230 _TIE_xt_ioports_WUR_EXPSTATE
#ifndef RUR
#define RUR(NUM) RUR##NUM()
#endif
#ifndef WUR
#define WUR(VAL, NUM) WUR##NUM(VAL)
#endif
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_ioports_HEADER */

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components/esp32/include/xtensa/tie/xt_misc.h
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/* Definitions for the xt_misc TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_misc_HEADER
#define _XTENSA_xt_misc_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern int _TIE_xt_misc_CLAMPS(int s, immediate i);
extern int _TIE_xt_misc_MIN(int s, int t);
extern int _TIE_xt_misc_MAX(int s, int t);
extern unsigned _TIE_xt_misc_MINU(unsigned s, unsigned t);
extern unsigned _TIE_xt_misc_MAXU(unsigned s, unsigned t);
extern int _TIE_xt_misc_NSA(int s);
extern unsigned _TIE_xt_misc_NSAU(unsigned s);
extern int _TIE_xt_misc_SEXT(int s, immediate i);
#define XT_CLAMPS _TIE_xt_misc_CLAMPS
#define XT_MIN _TIE_xt_misc_MIN
#define XT_MAX _TIE_xt_misc_MAX
#define XT_MINU _TIE_xt_misc_MINU
#define XT_MAXU _TIE_xt_misc_MAXU
#define XT_NSA _TIE_xt_misc_NSA
#define XT_NSAU _TIE_xt_misc_NSAU
#define XT_SEXT _TIE_xt_misc_SEXT
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_misc_HEADER */

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components/esp32/include/xtensa/tie/xt_mmu.h
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/* Definitions for the xt_mmu TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_mmu_HEADER
#define _XTENSA_xt_mmu_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_mmu_IDTLB(unsigned ars);
extern unsigned _TIE_xt_mmu_RDTLB1(unsigned ars);
extern unsigned _TIE_xt_mmu_RDTLB0(unsigned ars);
extern unsigned _TIE_xt_mmu_PDTLB(unsigned ars);
extern void _TIE_xt_mmu_WDTLB(unsigned art, unsigned ars);
extern void _TIE_xt_mmu_IITLB(unsigned ars);
extern unsigned _TIE_xt_mmu_RITLB1(unsigned ars);
extern unsigned _TIE_xt_mmu_RITLB0(unsigned ars);
extern unsigned _TIE_xt_mmu_PITLB(unsigned ars);
extern void _TIE_xt_mmu_WITLB(unsigned art, unsigned ars);
#define XT_IDTLB _TIE_xt_mmu_IDTLB
#define XT_RDTLB1 _TIE_xt_mmu_RDTLB1
#define XT_RDTLB0 _TIE_xt_mmu_RDTLB0
#define XT_PDTLB _TIE_xt_mmu_PDTLB
#define XT_WDTLB _TIE_xt_mmu_WDTLB
#define XT_IITLB _TIE_xt_mmu_IITLB
#define XT_RITLB1 _TIE_xt_mmu_RITLB1
#define XT_RITLB0 _TIE_xt_mmu_RITLB0
#define XT_PITLB _TIE_xt_mmu_PITLB
#define XT_WITLB _TIE_xt_mmu_WITLB
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_mmu_HEADER */

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components/esp32/include/xtensa/tie/xt_mul.h
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/* Definitions for the xt_mul TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_mul_HEADER
#define _XTENSA_xt_mul_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern int _TIE_xt_mul_MUL16S(short s, short t);
extern unsigned _TIE_xt_mul_MUL16U(unsigned short s, unsigned short t);
extern int _TIE_xt_mul_MULL(int s, int t);
extern unsigned _TIE_xt_mul_MULUH(unsigned s, unsigned t);
extern int _TIE_xt_mul_MULSH(int s, int t);
#define XT_MUL16S _TIE_xt_mul_MUL16S
#define XT_MUL16U _TIE_xt_mul_MUL16U
#define XT_MULL _TIE_xt_mul_MULL
#define XT_MULUH _TIE_xt_mul_MULUH
#define XT_MULSH _TIE_xt_mul_MULSH
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_mul_HEADER */

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components/esp32/include/xtensa/tie/xt_regwin.h
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/* Definitions for the xt_regwin TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_regwin_HEADER
#define _XTENSA_xt_regwin_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_regwin_ENTRY(unsigned ars /*inout*/, immediate uimm12x8);
extern void _TIE_xt_regwin_ROTW(immediate simm4);
extern int _TIE_xt_regwin_MOVSP(int s);
extern int _TIE_xt_regwin_L32E(const int * s, immediate o);
extern void _TIE_xt_regwin_S32E(int t, int * s, immediate o);
extern unsigned _TIE_xt_regwin_RSR_WINDOWBASE(void);
extern void _TIE_xt_regwin_WSR_WINDOWBASE(unsigned t);
extern void _TIE_xt_regwin_XSR_WINDOWBASE(unsigned t /*inout*/);
extern unsigned _TIE_xt_regwin_RSR_WINDOWSTART(void);
extern void _TIE_xt_regwin_WSR_WINDOWSTART(unsigned t);
extern void _TIE_xt_regwin_XSR_WINDOWSTART(unsigned t /*inout*/);
#define XT_ENTRY _TIE_xt_regwin_ENTRY
#define XT_ROTW _TIE_xt_regwin_ROTW
#define XT_MOVSP _TIE_xt_regwin_MOVSP
#define XT_L32E _TIE_xt_regwin_L32E
#define XT_S32E _TIE_xt_regwin_S32E
#define XT_RSR_WINDOWBASE _TIE_xt_regwin_RSR_WINDOWBASE
#define XT_WSR_WINDOWBASE _TIE_xt_regwin_WSR_WINDOWBASE
#define XT_XSR_WINDOWBASE _TIE_xt_regwin_XSR_WINDOWBASE
#define XT_RSR_WINDOWSTART _TIE_xt_regwin_RSR_WINDOWSTART
#define XT_WSR_WINDOWSTART _TIE_xt_regwin_WSR_WINDOWSTART
#define XT_XSR_WINDOWSTART _TIE_xt_regwin_XSR_WINDOWSTART
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_regwin_HEADER */

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components/esp32/include/xtensa/tie/xt_scmpr.h
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/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_scmpr_h_HEADER
#define _XTENSA_xt_scmpr_h_HEADER
/* Header includes start */
/* Header includes end */
#endif /* !_XTENSA_xt_scmpr_h_HEADER */

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components/esp32/include/xtensa/tie/xt_sync.h
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/* Definitions for the xt_sync TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_sync_HEADER
#define _XTENSA_xt_sync_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_sync_RSR_SCOMPARE1(void);
extern void _TIE_xt_sync_WSR_SCOMPARE1(unsigned art);
extern void _TIE_xt_sync_XSR_SCOMPARE1(unsigned art /*inout*/);
extern unsigned _TIE_xt_sync_RSR_ATOMCTL(void);
extern void _TIE_xt_sync_WSR_ATOMCTL(unsigned art);
extern void _TIE_xt_sync_XSR_ATOMCTL(unsigned art /*inout*/);
extern unsigned _TIE_xt_sync_L32AI(const unsigned * p, immediate o);
extern void _TIE_xt_sync_S32RI(unsigned c, unsigned * p, immediate o);
extern void _TIE_xt_sync_S32C1I(unsigned c /*inout*/, const unsigned * p, immediate o);
#define XT_RSR_SCOMPARE1 _TIE_xt_sync_RSR_SCOMPARE1
#define XT_WSR_SCOMPARE1 _TIE_xt_sync_WSR_SCOMPARE1
#define XT_XSR_SCOMPARE1 _TIE_xt_sync_XSR_SCOMPARE1
#define XT_RSR_ATOMCTL _TIE_xt_sync_RSR_ATOMCTL
#define XT_WSR_ATOMCTL _TIE_xt_sync_WSR_ATOMCTL
#define XT_XSR_ATOMCTL _TIE_xt_sync_XSR_ATOMCTL
#define XT_L32AI _TIE_xt_sync_L32AI
#define XT_S32RI _TIE_xt_sync_S32RI
#define XT_S32C1I _TIE_xt_sync_S32C1I
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_sync_HEADER */

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components/esp32/include/xtensa/tie/xt_timer.h
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/* Definitions for the xt_timer TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_timer_HEADER
#define _XTENSA_xt_timer_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern unsigned _TIE_xt_timer_RSR_CCOUNT(void);
extern void _TIE_xt_timer_WSR_CCOUNT(unsigned art);
extern void _TIE_xt_timer_XSR_CCOUNT(unsigned art /*inout*/);
extern unsigned _TIE_xt_timer_RSR_CCOMPARE0(void);
extern void _TIE_xt_timer_WSR_CCOMPARE0(unsigned art);
extern void _TIE_xt_timer_XSR_CCOMPARE0(unsigned art /*inout*/);
extern unsigned _TIE_xt_timer_RSR_CCOMPARE1(void);
extern void _TIE_xt_timer_WSR_CCOMPARE1(unsigned art);
extern void _TIE_xt_timer_XSR_CCOMPARE1(unsigned art /*inout*/);
extern unsigned _TIE_xt_timer_RSR_CCOMPARE2(void);
extern void _TIE_xt_timer_WSR_CCOMPARE2(unsigned art);
extern void _TIE_xt_timer_XSR_CCOMPARE2(unsigned art /*inout*/);
#define XT_RSR_CCOUNT _TIE_xt_timer_RSR_CCOUNT
#define XT_WSR_CCOUNT _TIE_xt_timer_WSR_CCOUNT
#define XT_XSR_CCOUNT _TIE_xt_timer_XSR_CCOUNT
#define XT_RSR_CCOMPARE0 _TIE_xt_timer_RSR_CCOMPARE0
#define XT_WSR_CCOMPARE0 _TIE_xt_timer_WSR_CCOMPARE0
#define XT_XSR_CCOMPARE0 _TIE_xt_timer_XSR_CCOMPARE0
#define XT_RSR_CCOMPARE1 _TIE_xt_timer_RSR_CCOMPARE1
#define XT_WSR_CCOMPARE1 _TIE_xt_timer_WSR_CCOMPARE1
#define XT_XSR_CCOMPARE1 _TIE_xt_timer_XSR_CCOMPARE1
#define XT_RSR_CCOMPARE2 _TIE_xt_timer_RSR_CCOMPARE2
#define XT_WSR_CCOMPARE2 _TIE_xt_timer_WSR_CCOMPARE2
#define XT_XSR_CCOMPARE2 _TIE_xt_timer_XSR_CCOMPARE2
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_timer_HEADER */

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components/esp32/include/xtensa/tie/xt_trace.h
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/* Definitions for the xt_trace TIE package */
/*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 2004-2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
/* Do not modify. This is automatically generated.*/
#ifndef _XTENSA_xt_trace_HEADER
#define _XTENSA_xt_trace_HEADER
#ifdef __XTENSA__
#ifdef __XCC__
#include <xtensa/tie/xt_core.h>
/*
* The following prototypes describe intrinsic functions
* corresponding to TIE instructions. Some TIE instructions
* may produce multiple results (designated as "out" operands
* in the iclass section) or may have operands used as both
* inputs and outputs (designated as "inout"). However, the C
* and C++ languages do not provide syntax that can express
* the in/out/inout constraints of TIE intrinsics.
* Nevertheless, the compiler understands these constraints
* and will check that the intrinsic functions are used
* correctly. To improve the readability of these prototypes,
* the "out" and "inout" parameters are marked accordingly
* with comments.
*/
extern void _TIE_xt_trace_WSR_MMID(unsigned art);
#define XT_WSR_MMID _TIE_xt_trace_WSR_MMID
#endif /* __XCC__ */
#endif /* __XTENSA__ */
#endif /* !_XTENSA_xt_trace_HEADER */

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components/esp32/include/xtensa/trax-api.h
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/* Misc TRAX API function definitions.
Copyright (c) 2007-2012 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _TRAX_API_H_
#define _TRAX_API_H_
#include <xtensa-isa.h>
#include <xtensa-params.h>
#include "tpack.h"
#include "traxreg.h"
#include "xdm-regs.h"
/* Flags for trax_stop(): */
#define TRAX_STOP_HALT 0x0001 /* halt immediately, don't wait for post-stop-trigger capture */
#define TRAX_STOP_QUIET 0x0002 /* don't display informative messages */
/*
* Describes a TRAX channel (based on tpack).
*/
typedef struct {
tpack_channel chan; /* channel structure header */
/* Per TRAX unit information: */
int trax_version; /* TRAX_ID_VER(id), one of TRAX_VER_xxx macros */
unsigned long trax_tram_size; /* size of trace RAM in bytes */
int trax_erratum10; /* set if TRAX 1.0 erratum workarounds needed */
int trax_erratum20; /* set if TRAX 2.0 erratum workaround needed (PR 22161)*/
int trax_erratum20_size;
int trax_has_busy; /* has trace-busy feature */
int trax_has_atb; /* has ATB feature */
/*FIXME: add various features: coresight regs (don't call it that), APB, ATB, TRAM, ... */
} trax_channel;
/* Prototypes: */
/* TRAX Protocol API: */
extern int trax_read_register(tpack_channel *tchan, int regno, unsigned *value);
extern int trax_write_register(tpack_channel *tchan, int regno, unsigned value);
extern int trax_read_memory(tpack_channel *tchan, int address, int size, unsigned char *pdata);
extern int trax_fill_memory(tpack_channel *tchan, int address, int size, tpack_u32 pattern);
extern int trax_enumerate_devices(tpack_channel *tchan, int * buf, int * size);
/* TRAX Network API: */
extern unsigned long trax_ram_size(tpack_channel *traxchan);
extern unsigned long trax_ram_size_addr(tpack_channel *traxchan);
extern int trax_create_tracefile(tpack_channel *traxchan, int size, unsigned char * data,
char *filename, int hflags, const char *toolver);
extern int trax_memaccess_safe(tpack_channel *traxchan, const char *what);
extern int trax_start(tpack_channel *traxchan, int flags);
extern int trax_stop(tpack_channel *traxchan, int flags);
extern int trax_halt(tpack_channel *traxchan, int flags);
extern int trax_save(tpack_channel *traxchan, char *filename, int flags, const char *toolver, int erratum);
/* TRAX Misc API (no network dependencies): */
int trax_fixed_hw(unsigned * regs);
extern int trax_display_id(unsigned id, const char *prefix);
extern int trax_display_summary(unsigned id,
unsigned status,
unsigned control,
unsigned address,
unsigned delay,
unsigned trigger,
unsigned match,
unsigned startaddr,
unsigned endaddr,
const char *prefix);
/* Other: */
#endif /* _TRAX_API_H_ */

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components/esp32/include/xtensa/trax-core-config.h
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/* Definitions for Xtensa processor config info needed for TRAX.
Copyright (c) 2005-2011 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef TRAX_CORE_CONFIG_H
#define TRAX_CORE_CONFIG_H
#include "xtensa-params.h"
/*
* Vector Enumerations.
*/
/* These must match the LX2.0 and later traceport spec: */
#define VEC_NO_VECTOR 0
#define VEC_FIRST VEC_RESET /* first valid vector */
#define VEC_RESET 1
#define VEC_DEBUG 2
#define VEC_NMI 3
#define VEC_USER 4
#define VEC_KERNEL 5
#define VEC_DOUBLE 6
#define VEC_MEMERR 7
#define VEC_RESERVED8 8
#define VEC_RESERVED9 9
#define VEC_WINO4 10
#define VEC_WINU4 11
#define VEC_WINO8 12
#define VEC_WINU8 13
#define VEC_WINO12 14
#define VEC_WINU12 15
#define VEC_INTLEVEL2 16
#define VEC_INTLEVEL3 17
#define VEC_INTLEVEL4 18
#define VEC_INTLEVEL5 19
#define VEC_INTLEVEL6 20
/* These are internal, i.e. don't appear like this on traceport: */
#define VEC_DEBUG_OCD 21
#define VEC_UNKNOWN 22
/* Enumerations 23 through 31 are also reserved, but putting */
/* placeholders here seems wasteful and unnecessary. */
#define VEC_COUNT 23
/* Other branch (change-of-PC-flow) type encodings;
* if PC changes due to an exception or interrupt vector,
* one of the VEC_* values above is used, otherwise
* (or if it's unknown whether it's due to an exception/interrupt)
* one of the following is used: */
#define BRANCH_IS_VEC(n) ((n) < VEC_COUNT) /* is known to be except/interrupt? */
#define BRANCH_OR_VEC 24 /* unknown type of branch (branch/exception/interrupt/etc) */
#define BRANCH_UNKNOWN 25 /* unknown type of branch (anything but except/interrupt) */
#define BRANCH_UNKNOWN_ERR 26 /* like BRANCH_UNKNOWN with known error (non-branch instr) */
#define BRANCH_LOOPBACK 28 /* zero-overhead loopback (from LEND to LBEG) */
#define BRANCH_CONDTAKEN 29 /* conditional branch taken (or LOOP{NEZ,GTZ} loop skip) */
#define BRANCH_JUMP 30 /* jump (unconditional branch, i.e. J or JX) */
#define BRANCH_IS_CALL(n) (((n) & ~3) == 32) /* is a function call? */
#define BRANCH_CALL0 32 /* non-windowed function call (CALL0, CALLX0) */
#define BRANCH_CALL4 33 /* windowed function call (CALL4, CALLX4) */
#define BRANCH_CALL8 34 /* windowed function call (CALL8, CALLX8) */
#define BRANCH_CALL12 35 /* windowed function call (CALL12, CALLX12) */
#define BRANCH_IS_RETURN(n) ((n) >= 36) /* is any kind of return? */
#define BRANCH_IS_CALLRETURN(n) (((n) & ~1) == 36) /* is a function return? */
#define BRANCH_RET 36 /* non-windowed function return (RET or RET.N) */
#define BRANCH_RETW 37 /* windowed function return (RETW or RETW.N) */
#define BRANCH_IS_EIRETURN(n) ((n) >= 38) /* is an except/inter. return? */
#define BRANCH_RFE 38 /* RFE or RFUE */
#define BRANCH_RFDE 39 /* RFDE */
#define BRANCH_RFWO 40 /* RFWO */
#define BRANCH_RFWU 41 /* RFWU */
#define BRANCH_RFI_2 42 /* RFI 2 */
#define BRANCH_RFI_3 43 /* RFI 3 */
#define BRANCH_RFI_4 44 /* RFI 4 */
#define BRANCH_RFI_5 45 /* RFI 5 */
#define BRANCH_RFI_6 46 /* RFI 6 */
#define BRANCH_RFI_NMI 47 /* RFI NMILEVEL */
#define BRANCH_RFI_DEBUG 48 /* RFI DEBUGLEVEL */
#define BRANCH_RFME 49 /* RFME */
#define BRANCH_COUNT 50 /* (number of defined BRANCH_xxx values) */
typedef struct {
unsigned vaddr;
unsigned vaddr2; /* for static vectors only (reloc vectors option) */
int is_configured;
} trax_vector_t;
/*
* This structure describes those portion of a Tensilica processor's
* configuration that are useful for trace.
*/
typedef struct {
char ** isa_dlls;
char * core_name; /* (XPG core name, not necessarily same as XTENSA_CORE) */
int big_endian; /* 0 = little-endian, 1 = big-endian */
int has_loops; /* 1 = zero overhead loops configured */
int has_autorefill; /* 1 = TLB autorefill (MMU) configured */
unsigned max_instr_size; /* in bytes (eg. 3, 4, 8, ...) */
unsigned int_level_max; /* number of interrupt levels configured (without NMI) */
int debug_level; /* debug intlevel, 0 if debug not configured */
int nmi_level; /* NMI intlevel, 0 if NMI not configured */
unsigned targethw_min; /* min. targeted hardware version (XTENSA_HWVERSION_<rel>) */
unsigned targethw_max; /* max. targeted hardware version (XTENSA_HWVERSION_<rel>) */
int reloc_vectors; /* 0 = fixed vectors, 1 = relocatable vectors */
int statvec_select; /* 0 = stat vec base 0, 1 = stat vec base 1 (SW default) */
int vecbase_align; /* number of bits to align VECBASE (32 - bits in VECBASE) */
unsigned statvec_base0; /* static vector base 0 */
unsigned statvec_base1; /* static vector base 1 */
unsigned vecbase_reset; /* reset value of VECBASE */
trax_vector_t vectors[VEC_COUNT]; /* all vectors... */
} trax_core_config_t;
/* Globals: */
//extern const char * const trax_vector_short_names[/*VEC_COUNT*/]; // nobody uses this one
extern const char * const trax_vector_names[/*VEC_COUNT*/];
/* Prototypes: */
extern int trax_read_params (trax_core_config_t *c, xtensa_params p);
extern int trax_vector_from_address(trax_core_config_t *config, unsigned long vaddr, unsigned long *vecbases);
#endif /* TRAX_CORE_CONFIG_H */

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components/esp32/include/xtensa/trax-proto.h
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/* This file contains functions that are hidden from the user. These are
* protocol specific functions used to read and write TRAX registers
* and the trace memory
*/
/*
* Copyright (c) 2012-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _TRAX_PROTO_H
#define _TRAX_PROTO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Function to read register
*
* regno : The register number to be read (not ERI addressed)
* data : Location where the read value is kept
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_read_register_eri (int regno, unsigned *data);
/* Function to write a value into a register
*
* regno : The register number to be written (not ERI addressed)
* value : The value to be written at that register location
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_write_register_eri (int regno, unsigned value);
/* Function to read memory
*
* address : Address of the TraceRAM memory, each location has a word
* len : Amount of memory in bytes, to be read
* data : buffer in which the read memory is stored
* final_address: Next address to be read in the following call to this
* function (trace save mechanism)
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_read_memory_eri (unsigned address, int len, int *data,
unsigned *final_address);
/* Function to write a value to the memory address
*
* address : Address of the TraceRAM memory
* value : The value to be written inside that location
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_write_memory_eri (int address, unsigned value);
/* Function to write to a subfield of the register.
* Called by set and show parameter functions.
*
* regno : Register number
* regmask : Mask in order to toggle appropriate bits
* value : Value to be written in the masked location
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_write_register_field_eri (int regno, unsigned regmask,
unsigned value);
#ifdef __cplusplus
}
#endif
#endif

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components/esp32/include/xtensa/trax-util.h
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/* This file contains utility functions that can be used for polling TRAX
* or executing higher level save functionality
* It assumes that print subroutines and file I/O routines are available
* on the system
*/
/*
* Copyright (c) 2012-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _TRAX_UTIL_H
#define _TRAX_UTIL_H
#ifdef __cplusplus
extern "C" {
#endif
/* User can use this function if he wants to generate a tracefile output.
* Internally it calls trax_get_trace in a loop until it realizes that
* the entire trace has been read.
*
* context : pointer to structure which contains information about the
* current TRAX session
* filename : user specified output trace file name. If the file does not
* exist, it would create the new file, else would append to it
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_save (trax_context *context, char *filename);
/* Displays a brief machine readable status.
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_poll (trax_context *context);
#ifdef __cplusplus
}
#endif
#endif

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components/esp32/include/xtensa/trax.h
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/* Header file for TRAX control Library */
/*
* Copyright (c) 2012-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _TRAX_H
#define _TRAX_H
#ifdef __cplusplus
extern "C" {
#endif
#define TRAX_STOP_HALT 0x0001
#define TRAX_STOP_QUIET 0x0002
/* Flag values to indicate if the user wanted to reverse the pcstop
* parameters */
#define TRAX_PCSTOP_REVERSE 0x0001
#define TRAX_PCSTOP_NO_REVERSE 0x0000
/* Indicating whether postsize should be in terms of bytes, instructions
* or percentage of trace size captured */
#define TRAX_POSTSIZE_BYTES 0x0000
#define TRAX_POSTSIZE_INSTR 0x0001
#define TRAX_POSTSIZE_PERCENT 0x0002
/* Size of the header inside the trace file */
#define TRAX_HEADER_SIZE 256
/* Minimum size between start and end addresses */
#define TRAX_MIN_TRACEMEM 64
/* For basic debugging */
#define DEBUG 0
#include <stdbool.h>
#define ffs(i) __builtin_ffs(i)
/* Data structures */
/* Represents the context of the TRAX unit and the current TRAX session.
* To be used by set and show function calls to set and show appropriate
* parameters of appropriate TRAX unit.
*/
typedef struct {
int trax_version; /* TRAX PC version information */
unsigned long trax_tram_size; /* If trace RAM is present,size of it */
int hflags; /* Flags that can be used to debug,
print info, etc. */
int address_read_last; /* During saving of the trace, this
indicates the address from which
the current trace reading must
resume */
unsigned long bytes_read; /* bytes read uptil now */
unsigned long total_memlen; /* Total bytes to be read based on the
trace collected in the trace RAM */
bool get_trace_started; /* indicates that the first chunk of
bytes (which include the header) has
been read */
} trax_context;
/* -----------------------TRAX Initialization ------------------------------*/
/* Initializing the trax context. Reads registers and sets values for version,
* trace RAM size, total memory length, etc. Most of the other values are
* initialized to their default case.
*
* context : pointer to structure which contains information about the
* current TRAX session
*
* returns : 0 if successful, -1 if unsuccessful, -2 if ram_size if
* incorrect
*/
int trax_context_init_eri (trax_context *context);
/* -----------------Starting/Stopping TRAX session -------------------------*/
/* Start tracing with current parameter setting. If tracing is already in
* progress, an error is reported. Otherwise, tracing starts and any unsaved
* contents of the TraceRAM is discarded
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if successful, 1 if trace is already active,
* -1 if unsuccessful
*/
int trax_start (trax_context *context);
/* This command initiates a stop trigger or halts a trace session based of the
* value of the flag parameter passed. In case stop trigger is initiated, any
* selected post-stop-trigger capture proceeds normally.
* If trace capture was not in progress, or a stop was already triggered, the
* return value indicates appropriately.
*
* context : pointer to structure which contains information about the
* current TRAX session
* flags : To differentiate between stopping trace without any
* post-size-trigger capture (trax_halt) or with that.
* A zero value would stop the trace based on trigger and a
* value of one would halt it
*
* returns : 0 if successful, 1 if already stopped, -1 if unsuccessful
*/
int trax_stop_halt (trax_context *context, int flags);
/* Resets the TRAX parameters to their default values which would internally
* involve resetting the TRAX registers. To invoke another trace session or
* reset the current tracing mechanism, this function needs to be called as
* it resets parameters of the context that deal with tracing information
*
* context : pointer to structure which contains information about the
* current TRAX session
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_reset (trax_context *context);
/* ---------------Set/Get several TRAX parameters --------------------------*/
/* Sets the start address and end address (word aligned) of the trace in the
* TraceRAM. Care must be taken to ensure that the difference between the
* start and the end addresses is atleast TRAX_MIN_TRACEMEM bytes. If not,
* the values are reset to default, which is 0 for startaddr and
* traceRAM_words -1 for endaddr
*
* context : pointer to structure which contains information about the
* current TRAX session
* startaddr : value to which the start address must be set. Can be
* any value between 0 - (traceRAM_words - 1)
* endaddr : value to which the end address must be set. Can be any value
* between 0 - (traceRAM_words - 1)
*
* returns : 0 if successful, -1 if unsuccessful, -2 if the difference
* between the start and end addresses is less than
* TRAX_MIN_TRACEMEM bytes or if they are passed incorrect
* values, -3 if memory shared option is not configured, in
* which case, start and end addresses are set to default
* values instead of those passed by the user
*/
int trax_set_ram_boundaries (trax_context *context, unsigned startaddr,
unsigned endaddr);
/* Shows the start address and end address(word aligned) of the trace in the
* TraceRAM. If incorrect, the startaddress and the endaddress values are
* set to default, i.e. 0 for startaddr and traceRAM_words - 1 for endaddr
*
* context : pointer to structure which contains information about the
* current TRAX session
* startaddr : pointer to value which will contain the start address
* endaddr : pointer to value which will contain the end address
*
* returns : 0 if successful, -1 if unsuccessful
*
*/
int trax_get_ram_boundaries (trax_context *context, unsigned *startaddr,
unsigned *endaddr);
/* Selects stop trigger via cross-trigger input
*
* context : pointer to structure which contains information about the
* current TRAX session
* value : 0 = off (reset value), 1 = on
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_set_ctistop (trax_context *context, unsigned value);
/* Shows if stop-trigger via cross-trigger input is off or on
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if off, 1 if on, -1 if unsuccessful
*/
int trax_get_ctistop (trax_context *context);
/* Selects stop trigger via processor-trigger input
*
* context : pointer to structure which contains information about the
* current TRAX session
* value : 0 = off (reset value), 1 = on
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_set_ptistop (trax_context *context, unsigned value);
/* Shows if stop trigger visa processor-trigger input is off or on
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if off, 1 if on, -1 if unsuccessful
*/
int trax_get_ptistop (trax_context *context);
/* Reports cross trigger output state
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if CTO bit is reset, 1 if CTO bit is set
*/
int trax_get_cto (trax_context *context);
/* Reports processor trigger output state
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if PTO bit is reset, 1 if PTO bit is set
*/
int trax_get_pto (trax_context *context);
/* Selects condition that asserts cross trigger output
*
* context : pointer to structure which contains information about the
* current TRAX session
* option : 0 = off(reset value)/1 = ontrig/2 = onhalt
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_set_ctowhen (trax_context *context, int option);
/* Shows condition that asserted cross trigger output. It can be
* any of: ontrig or onhalt or even off
*
* context : pointer to structure which contains information about the
* current TRAX session
*
* returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful
*/
int trax_get_ctowhen (trax_context *context);
/* Selects condition that asserts processor trigger output
*
* context : pointer to structure which contains information about the
* current TRAX session
* option : 0 = off(reset value)/1 = ontrig/2 = onhalt
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_set_ptowhen (trax_context *context, int option);
/* Shows condition that asserted processor trigger output. It can be
* any of: ontrig or onhalt or even off
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : 0 if off, 1 if ontrig, 2 if onhalt, -1 if unsuccessful
*/
int trax_get_ptowhen (trax_context *context);
/* Selects the trace synchronization message period.
* If ATEN enabled, we cannot allow syncper to be off, set it to reset value.
* Also, if no trace RAM, and ATEN enabled, set syncper to be reset value
* i.e. 256. A value of 1 i.e. on indicates that internally the message
* frequency is set to an optimal value. This option should be preferred
* if the user is not sure what message frequency option to set for the
* trace session.
*
* context : pointer to structure which contains information about the
* current TRAX session
* option : 0 = off, 1 = on, -1 = auto, 8, 16, 32, 64, 128,
* 256 (reset value)
*
* returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
* arguments
*/
int trax_set_syncper (trax_context *context, int option);
/* Shows trace synchronization message period. Can be one of:
* off, on, auto, 8, 16, 32, 64, 128, 256 (reset value)
*
* context : pointer to structure which contains information about the
* current TRAX session
* returns : value of sync period, 0 if off, -1 if unsuccessful
*/
int trax_get_syncper (trax_context *context);
/* Selects stop trigger via PC match. Specifies the address or
* address range to match against program counter. Trace stops when the
* processor executes an instruction matching the specified address
* or range.
*
* context : pointer to structure which contains information about the
* current TRAX session
* index : indicates the number of stop trigger (currently there is
* only one i.e. index = 0)
* startaddress : start range of the address at which the stop trigger
* should be activated
* enaddress : end range of the address at which the stop trigger should
* be activated
* flags : If non-zero, this inverts the range. i.e. trace stops
* when the processor executes an instruction that does not
* match the specified address or range
*
* returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
* arguments (unaligned)
*
* Note : For the current version of TRAX library, the endaddress and
* startaddress can differ by at most 31 bytes and the total
* range i.e. (endaddress - startaddress + 1) has to be a power
* of two
*/
int trax_set_pcstop (trax_context *context, int index, unsigned long startaddress,
unsigned long endaddress, int flags);
/* Shows the stop trigger via PC match
*
* context : pointer to structure which contains information about the
* current TRAX session
* index : container of information about the number of stop triggers
* startaddress : container of start range of stop trigger
* endaddress : container of end range of stop trigger
* flags : container of information whcih indicates whether the
* pc stop range is inverted or not.
*
* returns : 0 if successful, -1 if unsuccessful
*/
int trax_get_pcstop (trax_context *context, int *index,
unsigned long *startaddress,
unsigned long *endaddress, int *flags);
/* This function is used to set the amount of trace to be captured past
* the stop trigger.
*
* context : pointer to structure which contains information about the
* current TRAX session
* count_unit : contains the count of units (instructions or bytes) to be
* captured post trigger. If 0, it implies that this is off
* unit : unit of measuring the count. 0 is bytes, 1 is instructions
* 2 is percentage of trace
*
* returns : 0 if successful, -1 if unsuccessful, -2 if incorrect
* arguments
*
*/
int trax_set_postsize (trax_context *context, int count_unit, int unit);
/* This function shows the amount of TraceRAM in terms of the number of
* instructions or bytes, captured post the stop trigger
*
* context : pointer to structure which contains information about the
* current TRAX session
* count_unit : will contain the count of units(instructions or bytes) post
* trigger
* unit : will contain information about the events that are counted
* 0 implies that the traceRAM words consumed are counted and
* 1 implies that the target processor instructions executed and
* excpetions/interrupts taken are counted
*
* returns : 0 if postsize was got successfully, -1 if unsuccessful
*/
int trax_get_postsize (trax_context *context, int *count_unit, int *unit);
/* -------------------------- TRAX save routines ---------------------------*/
/* This function should be called by the user to return a chunk of
* bytes in buf. It can be a lower layer function of save, or can be
* called by the user explicitly. If bytes_actually_read contains a 0
* after a call to this function has been made, it implies that the entire
* trace has been read successfully.
*
* context : pointer to structure which contains information about
* the current TRAX session
* buf : Buffer that is allocated by the user, all the trace
* data read would be put in this buffer, which can then
* be used to generate a tracefile.
* The first TRAX_HEADER_SIZE of the buffer will always
* contain the header information.
* bytes_to_be_read : Indicates the bytes the user wants to read. The first
* invocation would need this parameter to be
* TRAX_HEADER_SIZE at least.
*
* returns : bytes actually read during the call to this function.
* 0 implies that all the bytes in the trace have been
* read, -1 if unsuccessful read/write of
* registers or memory, -2 if trace was active while
* this function was called, -3 if user enters
* bytes_to_be_read < TRAX_HEADER_SIZE in the first
* pass
*/
int trax_get_trace (trax_context *context, void *buf,
int bytes_to_be_read);
#ifdef __cplusplus
}
#endif
#endif /* _TRAX_H */

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/* TRAX file header definition.
Copyright (c) 2007-2012 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#define TRAX_FHEAD_MAGIC "TRAXdmp"
#define TRAX_FHEAD_VERSION 1
/* Header flags: */
#define TRAX_FHEADF_OCD_ENABLED 0x00000001 /* set if OCD was enabled while capturing trace */
#define TRAX_FHEADF_TESTDUMP 0x00000002 /* set if is a test file
(from 'memsave' instead of 'save') */
#define TRAX_FHEADF_OCD_ENABLED_WHILE_EXIT 0x00000004 /* set if OCD was enabled while capturing trace and
we were exiting the OCD mode */
/* Header at the start of a TRAX dump file. */
typedef struct {
char magic[8]; /* 00: "TRAXdmp\0" (TRAX_FHEAD_MAGIC) */
char endianness; /* 08: 0=little-endian, 1=big-endian */
char version; /* 09: TRAX_FHEAD_VERSION */
char reserved0[2]; /* 0A: ... */
unsigned filesize; /* 0C: size of the trace file, including this header */
unsigned trace_ofs; /* 10: start of trace output, byte offset from start of header */
unsigned trace_size; /* 14: size of trace output in bytes */
unsigned dumptime; /* 18: date/time of capture save (secs since 1970-01-01), 0 if unknown */
unsigned flags; /* 1C: misc flags (TRAX_FHEAD_F_xxx) */
char username[16]; /* 20: user doing the capture/save (up to 15 chars) */
char toolver[24]; /* 30: tool + version used for capture/save (up to 23 chars) */
char reserved2[40]; /* 48: (reserved - could be hostname used for dump (up to 39 chars)) */
unsigned configid[2]; /* 70: processor ConfigID values, 0 if unknown */
unsigned ts_freq; /* 78: timestamp frequency, 0 if not specified */
unsigned reserved3; /* 7C: (reserved) */
unsigned id; /* 80: TRAX registers at time of save (0 if not read) */
unsigned control;
unsigned status;
unsigned reserved4; /* Data register (should not be read) */
unsigned address;
unsigned trigger;
unsigned match;
unsigned delay;
unsigned trax_regs[24]; /*100: (total size) -- dummy allocation (FIXME) */
} trax_file_header;

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components/esp32/include/xtensa/uart-16550-board.h
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/*******************************************************************************
Copyright (c) 2006-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
uart-16550-board.h Board-specific UART info on these boards:
Avnet AV60 (XT-AV60)
Avnet AV110 (XT-AV110)
Avnet AV200 (XT-AV200)
Xilinx ML605 (XT-ML605)
Xilinx KC705 (XT-KC705)
Interface between board-independent driver and board-specific header.
This is used by a board-independent 16550 UART driver to obtain board-specific
information about 1 instance of the 16550 UART on the board, such as the device
register base address and spacing (a function of how the address lines are
connected on the board) and the frequency of the UART clock. The driver does
not refer directly to the board-specific header, which therefore is not
constrained to use macro names consistent with other boards.
!! Must not contain any board-specific macro names (only UART specific). !!
Included at compile-time via an include path specific to the board.
These boards contain a single 16550 UART implemented on the FPGA.
Their clock frequency comes from the board's core clock (not its own crystal)
which depends on the core config so is not a constant. Obtained via the BSP.
*******************************************************************************/
#ifndef _UART_16550_BOARD_H
#define _UART_16550_BOARD_H
#include <xtensa/xtbsp.h> /* BSP API */
#include <xtensa/board.h> /* Board info */
/* Base address of UART's registers. */
#ifdef UART16550_VADDR
#define UART_16550_REGBASE UART16550_VADDR
#endif
/*
The UART's registers are connected at word addresses on these boards.
Each byte-wide register appears as the least-significant-byte (LSB) of the
word regardless of the endianness of the processor.
*/
#define UART_16550_REGSPACING 4
typedef unsigned uart16550_reg_t;
/* UART Clock Frequency in Hz */
#define UART_16550_XTAL_FREQ xtbsp_clock_freq_hz()
/* UART Interrupt Number */
#ifdef UART16550_INTNUM
#define UART_16550_INTNUM UART16550_INTNUM
#endif
/* Include generic information shared by all boards that use this device. */
#include <xtensa/uart-16550.h>
#endif /* _UART_16550_BOARD_H */

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/*******************************************************************************
Copyright (c) 2006-2007 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
--------------------------------------------------------------------------------
uart-16550.h Generic definitions for National Semiconductor 16550 UART
This is used by board-support-packages with one or more 16550 compatible UARTs.
A BSP provides a base address for each instance of a 16550 UART on the board.
Note that a 16552 DUART (Dual UART) is simply two instances of a 16550 UART.
*******************************************************************************/
#ifndef _UART_16550_H_
#define _UART_16550_H_
/* C interface to UART registers. */
struct uart_dev_s {
union {
uart16550_reg_t rxb; /* DLAB=0: receive buffer, read-only */
uart16550_reg_t txb; /* DLAB=0: transmit buffer, write-only */
uart16550_reg_t dll; /* DLAB=1: divisor, LS byte latch */
} w0;
union {
uart16550_reg_t ier; /* DLAB=0: interrupt-enable register */
uart16550_reg_t dlm; /* DLAB=1: divisor, MS byte latch */
} w1;
union {
uart16550_reg_t isr; /* DLAB=0: interrupt status register, read-only */
uart16550_reg_t fcr; /* DLAB=0: FIFO control register, write-only */
uart16550_reg_t afr; /* DLAB=1: alternate function register */
} w2;
uart16550_reg_t lcr; /* line control-register, write-only */
uart16550_reg_t mcr; /* modem control-regsiter, write-only */
uart16550_reg_t lsr; /* line status register, read-only */
uart16550_reg_t msr; /* modem status register, read-only */
uart16550_reg_t scr; /* scratch regsiter, read/write */
};
#define _RXB(u) ((u)->w0.rxb)
#define _TXB(u) ((u)->w0.txb)
#define _DLL(u) ((u)->w0.dll)
#define _IER(u) ((u)->w1.ier)
#define _DLM(u) ((u)->w1.dlm)
#define _ISR(u) ((u)->w2.isr)
#define _FCR(u) ((u)->w2.fcr)
#define _AFR(u) ((u)->w2.afr)
#define _LCR(u) ((u)->lcr)
#define _MCR(u) ((u)->mcr)
#define _LSR(u) ((u)->lsr)
#define _MSR(u) ((u)->msr)
#define _SCR(u) ((u)->scr)
typedef volatile struct uart_dev_s uart_dev_t;
/* IER bits */
#define RCVR_DATA_REG_INTENABLE 0x01
#define XMIT_HOLD_REG_INTENABLE 0x02
#define RCVR_STATUS_INTENABLE 0x04
#define MODEM_STATUS_INTENABLE 0x08
/* FCR bits */
#define _FIFO_ENABLE 0x01
#define RCVR_FIFO_RESET 0x02
#define XMIT_FIFO_RESET 0x04
#define DMA_MODE_SELECT 0x08
#define RCVR_TRIGGER_LSB 0x40
#define RCVR_TRIGGER_MSB 0x80
/* AFR bits */
#define AFR_CONC_WRITE 0x01
#define AFR_BAUDOUT_SEL 0x02
#define AFR_RXRDY_SEL 0x04
/* ISR bits */
#define INT_STATUS(r) ((r)&1)
#define INT_PRIORITY(r) (((r)>>1)&0x7)
/* LCR bits */
#define WORD_LENGTH(n) (((n)-5)&0x3)
#define STOP_BIT_ENABLE 0x04
#define PARITY_ENABLE 0x08
#define EVEN_PARITY 0x10
#define FORCE_PARITY 0x20
#define XMIT_BREAK 0x40
#define DLAB_ENABLE 0x80
/* MCR bits */
#define _DTR 0x01
#define _RTS 0x02
#define _OP1 0x04
#define _OP2 0x08
#define LOOP_BACK 0x10
/* LSR Bits */
#define RCVR_DATA_READY 0x01
#define OVERRUN_ERROR 0x02
#define PARITY_ERROR 0x04
#define FRAMING_ERROR 0x08
#define BREAK_INTERRUPT 0x10
#define XMIT_HOLD_EMPTY 0x20
#define XMIT_EMPTY 0x40
#define FIFO_ERROR 0x80
#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
/* MSR bits */
#define _RDR 0x01
#define DELTA_DSR 0x02
#define DELTA_RI 0x04
#define DELTA_CD 0x08
#define _CTS 0x10
#define _DSR 0x20
#define _RI 0x40
#define _CD 0x80
/* Compute 16-bit divisor for baudrate generator, with rounding: */
#define UART_DIVISOR(clock,baud) (((clock)/16 + (baud)/2)/(baud))
/* Prototypes of driver functions */
extern void uart16550_init( uart_dev_t *u, unsigned baud, unsigned ndata,
unsigned parity, unsigned nstop );
extern void uart16550_out( uart_dev_t *u, char c );
extern char uart16550_in( uart_dev_t *u );
extern unsigned uart16550_measure_sys_clk( uart_dev_t *u );
#endif /* _UART_16550_H_ */

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/* Customer ID=11656; Build=0x5f626; Copyright (c) 2005-2014 by Cadence Design Systems, Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of
* Cadence Design Systems, Inc. They may not be modified, copied, reproduced,
* distributed, or disclosed to third parties in any manner, medium, or form,
* in whole or in part, without the prior written consent of Cadence Design
* Systems Inc.
*/
#ifndef __UDMA_H__
#define __UDMA_H__
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Size of the uDMA descriptor */
#define UDMA_DESC_STRUCT_SIZE 32
/* Request attribute is a bit vector passed to the udma functions - udma_copy,
* udma_2d_copy, udma_add_descs.
* Bit 0 : 1 - trigger an interrupt when done, else do nothing
* Bit 1 : 0 - retry the failed request; abort after programmer specified
* number of retries. Defaults to abort with no retries.
* 1 - abort the failed request (after retries) and all pending requests
*/
#define UDMA_DONE_INTERRUPT 0x1
#define UDMA_ERROR_ABORT 0x0
#define UDMA_ERROR_ABORT_ALL 0x2
/* Enum representing various udma error conditions, udma status, and
* return values
*/
typedef enum {
UDMA_OK = 0,
UDMA_ERROR_QUEUE_FULL = 1,
UDMA_ERROR_BAD_DESC = 2,
UDMA_ERROR_DRAM_CROSSING = 3,
UDMA_ERROR_PIF_ADDR_BUS = 4,
UDMA_ERROR_PIF_DATA_BUS = 5,
UDMA_REQ_PENDING = 6,
UDMA_REQ_DONE = 7,
UDMA_ERROR_BAD_REQUEST = 8,
UDMA_ERROR_INVALID_ARG = 11,
UDMA_ERROR_INIT = 12,
UDMA_ERROR_INTERNAL = -1
} udma_status_t;
#ifndef __UDMA_INTERNAL_H__
/* Opaque structure describing a uDMA descriptor */
struct udma_desc_struct {
char _[UDMA_DESC_STRUCT_SIZE];
} __attribute__ ((aligned (UDMA_DESC_STRUCT_SIZE)));
#endif
typedef struct udma_desc_struct udma_desc_t;
/* Initialize the udma control structure, the uDMA registers with
* the descriptor queue addresses, and the uDMA sync and error interrupt
* handler. This function needs to be invoked prior to using the uDMA.
*
* xmp_udma_sync_intr : Processor interrupt number to flag udma done
* xmp_udma_error_intr : Processor interrupt number to flag udma error
*
* Returns UDMA_ERROR_INIT if there was an error during initialization else
* returns UDMA_OK.
*/
extern udma_status_t
udma_init(uint32_t xmp_udma_sync_intr, uint32_t xmp_udma_error_intr);
/* Performs a copy of a linear block of size bytes from the src
* to the dest address. If the call returns UDMA_OK, status is set to
* UDMA_REQ_PENDING or UDMA_REQ_DONE. If there is a dma error, the error code,
* which could be one of UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING,
* UDMA_ERROR_PIF_ADDR_BUS, UDMA_ERROR_PIF_DATA_BUS is returned in the status.
* Status is set to UDMA_REQ_DONE if the dma completes normally.
* On completion, the callback function is invoked with the callback_data
* and status as parameters. Note, the callback is always invoked even if
* there is a dma error.
*
* src : src address of the copy
* dest : dest address of the copy
* size : number of bytes to copy
* callback_data : optional data to be passed to callback_func
* callback_func : optional callback after copy is done
* request_attr : attribute defining how to process this request
* (see description of the request attribute in top of udma.h)
* status : track status of the copy; this gets also passed
* as the second argument to the callback_func
*
* Returns UDMA_ERROR_QUEUE_FULL if no more requests can be added, else
* returns UDMA_OK.
*/
extern udma_status_t
udma_copy(void *dest,
void *src,
size_t size,
void *callback_data,
void (*callback_func)(void *, udma_status_t *status),
uint32_t request_attr,
udma_status_t *status);
/* Performs a copy of a 2D block of data from the src to the dest
* address. If the call returns UDMA_OK, status is set to UDMA_REQ_PENDING or
* UDMA_REQ_DONE. If there is a dma error, the error code,
* which could be one of UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING,
* UDMA_ERROR_PIF_ADDR_BUS, UDMA_ERROR_PIF_DATA_BUS is returned in the status.
* Status is set to UDMA_REQ_DONE if the dma completes normally.
* On completion, the callback function is invoked with the callback_data
* and status as parameters. Note, the callback is always invoked even if
* there is a dma error.
*
* src : src address of the copy
* dest : dest address of the copy
* row_size : number of bytes per row to copy
* num_rows : number of rows to copy
* src_pitch : src pitch
* dest_pitch : dest pitch
* callback_data : optional data to be passed to callback_func
* callback_func : optional callback after copy is done
* request_attr : attribute defining how to process this request
* (see description of the request attribute in top of udma.h)
* status : track status of the copy; this gets also passed
* as the second argument to the callback_func
*
* Returns UDMA_ERROR_QUEUE_FULL if no more requests can be added, else
* returns UDMA_OK.
*/
extern udma_status_t
udma_2d_copy(void *dest,
void *src,
size_t row_size,
uint32_t num_rows,
uint32_t src_pitch,
uint32_t dest_pitch,
void *callback_data,
void (*callback_func)(void *, udma_status_t *status),
uint32_t request_attr,
udma_status_t *status);
/* Process requests that are done. Any callbacks associated
* with the completed requests gets invoked. If there are any errors,
* the error request is (and any pending request based on the request attribute)
* cancelled and the error code is returned in the status associated with
* all such cancelled requests. Callbacks associated with the cancelled
* requests are also invoked. If all requests terminate normally, the status
* of the completed requests are set to UDMA_REQ_DONE.
*
* Returns void
*/
extern void
udma_process_requests();
/* Sets the udma max PIF block size
*
* max_block_size : max block size to be set
*
* Returns UDMA_ERROR_INVALID_ARG if block_size is > 3, else returns UDMA_OK
*/
udma_status_t
udma_set_max_block_size(uint32_t block_size);
/* Sets the udma max outstanding PIF requests
*
* max_outstanding : max outstanding PIF requests
*
* Returns UDMA_ERROR_INVALID_ARG if max_outstanding is not between 1 and 16
* else returns UDMA_OK
*/
udma_status_t
udma_set_max_outstanding(uint32_t max_outstanding);
/* Initialize a uDMA descriptor using the copy parameters. The descriptor
* is then queued separately using udma_add_desc
*
* src : src address of the copy
* dest : dest address of the copy
* row_size : number of bytes per row to copy
* num_rows : number of rows to copy
* src_pitch : src pitch
* dest_pitch : dest pitch
* notify_with_interrupt : If 1, interrupt when dma is done with this descriptor
* if 0, do nothing, else undefined
*
* Returns void
*/
extern void
udma_set_desc(void *src,
void *dest,
size_t row_size,
uint32_t num_rows,
uint32_t src_pitch,
uint32_t dest_pitch,
uint32_t notify_with_interrupt,
udma_desc_t *desc);
/* Add multiple uDMA descriptors to the descriptor queue. If the call returns
* UDMA_OK, the status is set to UDMA_REQ_PENDING or UDMA_REQ_DONE.
* If there is a dma error, the error code, which could be one of
* UDMA_ERROR_BAD_DESC, UDMA_ERROR_DRAM_CROSSING, UDMA_ERROR_PIF_ADDR_BUS,
* UDMA_ERROR_PIF_DATA_BUS is returned in the status. Status is set
* to UDMA_REQ_DONE, if the dma completes normally.
* On completion, the callback function is invoked with the callback_data
* and status as parameters. Note, the callback is always invoked even if
* there is a dma error.
*
* desc : descriptors to be added
* num_desc : number of descriptors to be added
* callback_data : optional data to be passed to callback_func
* callback_func : optional callback after copy is done
* request_attr : attribute defining how to process this request
* (see description of the request attribute in top of udma.h)
* Note, bit 0 (for enabling interrupt) is ignored in this call.
* To interrupt on dma completion, set the
* notify_with_interrupt parameter when creating descriptors
* using udma_set_desc.
* status : track status of the copy; this gets also passed
* as the second argument to the callback_func
*
* Returns UDMA_ERROR_QUEUE_FULL if no more descriptors can be added,
* UDMA_ERROR_INVALID_ARG if num_descs == 0, else return UDMA_OK
*/
udma_status_t
udma_add_descs(udma_desc_t *descs,
uint32_t num_descs,
void *callback_data,
void (*callback_func)(void *, udma_status_t *status),
uint32_t request_attr,
udma_status_t *status);
/* Wait for udma copy request to complete. Could spin wait or goto waiti
* based on the sleep_wait parameter. Once the request is done, the callback
* associated with this request and any prior completed requests are handled.
* Error code, if any, is returned in the status s, else s is set to
* UDMA_REQ_DONE.
*
* s : status to wait for
* sleep_wait : sleep wait if true, else spin waits
*
* Returns void
*/
extern void
udma_wait_request(volatile udma_status_t *s, uint32_t sleep_wait);
/* Inlined function to set the src, dest address of the descriptor
*
* src : src address of the uDMA
* dest : dest address of the uDMA
* desc : descriptor to be modified
*
* Returns void
*/
void static inline
udma_set_desc_addrs(void *src, void *dest, udma_desc_t *desc) {
uint32_t *d = (uint32_t *)desc;
*d = (uintptr_t)src;
*(d+1) = (uintptr_t)dest;
}
/* Sets the number of retries for a failed dma request
*
* max_retries : max number of retries
*
* Sets the max number of retries for a failed dma request. The default is 0,
* i.e, no retries
*/
void
udma_set_max_retries(uint32_t max_retries);
#ifdef __cplusplus
}
#endif
#endif /* __UDMA_H__ */

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components/esp32/include/xtensa/xmon.h
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/* xmon.h - XMON definitions
*
* $Id: //depot/rel/Eaglenest/Xtensa/OS/xmon/xmon.h#3 $
*
* Copyright (c) 2001-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __H_XMON
#define __H_XMON
/* Default GDB packet size */
#define GDB_PKT_SIZE 4096
/*XMON signals */
#define XMON_SIGINT 2 /*target was interrupted */
#define XMON_SIGILL 4 /*illegal instruction */
#define XMON_SIGTRAP 5 /*general exception */
#define XMON_SIGSEGV 11 /*page faults */
/* Type of log message from XMON to the application */
typedef enum {
XMON_LOG,
XMON_TRACE,
XMON_ERR,
XMON_APP,
XMON_GDB
} xmon_log_t;
/* Return value type for xmon_proc() (see below) */
typedef enum {
XMON_GDB_PEND,
XMON_GDB_PKT,
XMON_NOT_GDB
} xmon_gdb_pkt_t;
#ifdef _cplusplus
extern "C" {
#endif
/*
* THE FOLLOWING ROUTINES ARE USED BY USER
*/
extern int _xmon_init(char* gdbBuf, int gdbPktSize,
void(*xlog)(xmon_log_t type, const char* str));
//Initialize GDB communication and logging to the main app.
//For the logging to work, xlog function needs to be provided.
//gdbBuf - pointer to a buffer XMON can use to comm. with GDB
//gdbPktSize - Size of the allocated buffer for GDB communication.
//xlog - logger handle.
extern void _xmon_close(void);
//Main application can detach from xmon at any time
extern xmon_gdb_pkt_t _xmon_proc(char);
// Give character to XMON to check if GDB message
// Application is supposed to accumulate all the
// character in case the recognition fails and chars
// have to be sent to the original handler
// Return: XMON_GDB_PEND - send me more chars
// XMON_GDB_PKT - GDB message confirmed, C) not
// XMON_NOT_GDB - not GDB message
/*
* THE FOLLOWING ROUTINES NEED TO BE PROVIDED BY USER
*/
extern int _xmon_in(); // wait for character from GDB
extern void _xmon_out(char); // output a character to GDB
extern int _xmon_flush(void); // flush output characters
#ifdef _cplusplus
}
#endif
#endif

789
components/esp32/include/xtensa/xmp-library.h
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@@ -1,789 +0,0 @@
/* Customer ID=11656; Build=0x5f626; Copyright (c) 2008-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc. */
#ifndef _XMP_LIBRARY_H
#define _XMP_LIBRARY_H
#ifdef __cplusplus
extern "C" {
#endif
#include <xtensa/config/core-isa.h>
#include <xtensa/config/core.h>
#include <xtensa/tie/xt_core.h>
#if XCHAL_HAVE_RELEASE_SYNC
#include <xtensa/tie/xt_sync.h>
#endif
#if XCHAL_HAVE_EXTERN_REGS
#include <xtensa/xtensa-xer.h>
#endif
#include <stdlib.h>
#include <stdio.h>
#include "xtensa/system/mpsystem.h"
/*
W A R N I N G:
xmp library clients should treat all data structures in this file
as opaque. They are only public to enable users to declare them
statically.
*/
/* -------------------------------------------------------------------------
When using XMP on cache-incoherent systems, these macros are helpful
to ensure that you are not reading stale data, and to ensure that
the data you write makes it all the way back to main memory.
*/
#if !XCHAL_DCACHE_IS_COHERENT
#define XMP_WRITE_BACK_ELEMENT(x) xthal_dcache_region_writeback((void *)x, sizeof(*x))
#define XMP_INVALIDATE_ELEMENT(x) xthal_dcache_region_invalidate((void *)x, sizeof(*x))
#define XMP_WRITE_BACK_INVALIDATE_ELEMENT(x) xthal_dcache_region_writeback_inv((void *)x, sizeof(*x))
#define XMP_WRITE_BACK_ARRAY(x) xthal_dcache_region_writeback((void *)x, sizeof(x))
#define XMP_INVALIDATE_ARRAY(x) xthal_dcache_region_invalidate((void *)x, sizeof(x))
#define XMP_WRITE_BACK_INVALIDATE_ARRAY(x) xthal_dcache_region_writeback_inv((void *)x, sizeof(x))
#define XMP_WRITE_BACK_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_writeback((void *)x, sizeof(*x) * num_elements)
#define XMP_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_invalidate((void *)x, sizeof(*x) * num_elements)
#define XMP_WRITE_BACK_INVALIDATE_ARRAY_ELEMENTS(x, num_elements) xthal_dcache_region_writeback_inv((void *)x, sizeof(*x) * num_elements)
#else
#define XMP_WRITE_BACK_ELEMENT(x)
#define XMP_INVALIDATE_ELEMENT(x)
#define XMP_WRITE_BACK_INVALIDATE_ELEMENT(x)
#define XMP_WRITE_BACK_ARRAY(x)
#define XMP_INVALIDATE_ARRAY(x)
#define XMP_WRITE_BACK_INVALIDATE_ARRAY(x)
#define XMP_WRITE_BACK_ARRAY_ELEMENTS(x, num_elements)
#define XMP_INVALIDATE_ARRAY_ELEMENTS(x, num_elements)
#define XMP_WRITE_BACK_INVALIDATE_ARRAY_ELEMENTS(x, num_elements)
#endif
/* -------------------------------------------------------------------------
Initialization, error codes, constants and house-keeping
Every core should call xmp_init with the number of cores in the
system.
xmp_init should be called before you use any global synchronization
primitive or shared data.
Further, before you use a dynamically allocated synchronization
primitives, you need to both initialize it by calling the
xmp_*_init function, and you need to have called xmp_init, which
sets up interrupt handlers and interrupt routing.
The second parameter sets the interprocessor interrupt
routing. Passing zero instructs the library to use the default
routing, which will be suitable for most users.
*/
extern void xmp_init (int num_cores, unsigned int interrupt_routing);
/* If you want finer-grained control than that provided by xmp_init,
you can the functions below individually--however, this is more
inconvenient and requires greater understanding of the library's
internals. Don't use them directly unless you have a good reason.
*/
extern void xmp_unpack_shared (void);
extern void xmp_route_interrupts (unsigned int routing);
#if XCHAL_HAVE_MP_INTERRUPTS
extern void xmp_enable_ipi_interrupts (void);
/* Turn off certain things enabled by xmp_init */
extern void xmp_disable_ipi_interrupts (void);
#endif
extern void xmp_end (void);
/* Only valid after xmp_init. */
extern int xmp_num_cores (void);
/* How many cycles should a core wait before rechecking a
synchronization variable? Higher values will reduce memory
transactions, but will also result in higher latency in returning
from synchronization.
*/
extern void xmp_spin_wait_set_cycles (unsigned int limit);
/* If you would prefer to provide your own spin wait function,
to go to sleep, etc. Declare a function of this type, then call
this function. */
typedef void (*xmp_spin_wait_function_t)(void);
extern void xmp_spin_wait_set_function (xmp_spin_wait_function_t func);
extern void xmp_spin(void);
#define XMP_NO_OWNER 0x07
#define XMP_MUTEX_DESTROYED 0xFE
#define XMP_ERROR_FATAL 0xFD
#define XMP_MAX_CORES 0x4
static inline unsigned int xmp_prid (void)
{
#if XCHAL_HAVE_PRID
return XT_RSR_PRID() & 0xFF;
#else
return 0;
#endif
}
/* -------------------------------------------------------------------------
Tracing
A core must set a trace_file if it wants any synchronization
tracing to occur. Sharing file descriptors among cores is very
messy, so don't do it. This, unfortunately, means that two cores
contending for a mutex are not able to trace to the same file.
Any object (except the atomic integer) can have tracing off or on.
*/
extern void xmp_set_trace_file (FILE * file);
extern void xmp_trace (const char * fmt, ...);
/* -------------------------------------------------------------------------
Memory Allocation Functions.
These do what you would expect, only from shared memory instead of
private memory.
*/
#if XCHAL_DCACHE_IS_COHERENT
extern void * xmp_malloc (size_t size);
extern void * xmp_calloc (size_t nmemb, size_t size);
extern void xmp_free (void * ptr);
#endif
extern void * xmp_sbrk(int size);
/* -------------------------------------------------------------------------
xmp_atomic_int_t
The most basic synchronization primitive in the xmp library.
Atomic ints are sharable among processors, and even interrupt
levels on the same processor. However, their semantics are fairly
rudimentary. All other primitives are based on these, therefore,
changing this implementation affects all other primitives.
*/
typedef unsigned int xmp_atomic_int_t;
static inline xmp_atomic_int_t
xmp_coherent_l32ai(xmp_atomic_int_t * address)
{
XMP_INVALIDATE_ELEMENT (address);
return XT_L32AI(address, 0);
}
static inline void
xmp_coherent_s32ri(xmp_atomic_int_t value, xmp_atomic_int_t * address)
{
XT_S32RI (value, address, 0);
XMP_WRITE_BACK_ELEMENT (address);
}
#define XMP_ATOMIC_INT_INITIALIZER(value) (value)
/* xmp_atomic_int_init - Initialize an int prior to use
Nonsynchronizing, Nonblocking
Usage:
value - initial value
integer - points to an uninitialized integer
On exit:
initialized to given value
Errors: none
*/
static inline void
xmp_atomic_int_init (xmp_atomic_int_t * integer, int value)
{
xmp_coherent_s32ri (value, integer);
}
/* xmp_atomic_int_value - Read the value
Nonsynchronizing, Nonblocking
Usage:
integer - points to an int
Returns:
the value
*/
static inline int
xmp_atomic_int_value (xmp_atomic_int_t * integer)
{
return xmp_coherent_l32ai (integer);
}
/* xmp_atomic_int_conditional_increment - Conditionally increment integer
Synchronizing, nonblocking
Usage:
integer - points to an initialized integer
amount - how much to increment
prev - believed value of the integer
eg: prev = xmp_atomic_int_value (integer);
success = xmp_atomic_int_increment (integer, 1, prev);
Returns: current value of integer - user should check if it matches
the previous value of the integer. If it does, then the update
was successful.
*/
#define USE_ASSEMBLY_IMPLEMENTATION 0
static inline int
xmp_atomic_int_conditional_increment (xmp_atomic_int_t * integer, int amount, int prev)
{
int val;
int saved;
#if USE_ASSEMBLY_IMPLEMENTATION
/* %0 = prev
%1 = saved
%2 = atomic integer pointer
%3 = amount
*/
asm volatile ("wsr.scompare1 %0\n"
"mov %1, %0\n"
"add %0, %0, %3\n"
"s32c1i %0, %2, 0\n"
: "+&a" (prev), "+&a"(saved) : "a" (integer), "a" (amount));
return prev;
#else
XT_WSR_SCOMPARE1 (prev);
val = prev + amount;
saved = val;
XT_S32C1I (val, integer, 0);
return val;
#endif
}
/* xmp_atomic_int_increment - Increment integer
Synchronizing, blocking
Usage:
integer - points to an initialized integer
amount - how much to increment
Returns: new value of integer
*/
static inline int
xmp_atomic_int_increment (xmp_atomic_int_t * integer, int amount)
{
int val;
int saved;
#if USE_ASSEMBLY_IMPLEMENTATION
/* %0 = val
%1 = saved
%2 = atomic integer pointer
%3 = amount
*/
asm volatile ("l32ai %0, %2, 0\n"
"1:\n"
"wsr.scompare1 %0\n"
"mov %1, %0\n"
"add %0, %0, %3\n"
"s32c1i %0, %2, 0\n"
"bne %0, %1, 1b\n"
: "+&a" (val), "+&a"(saved) : "a" (integer), "a" (amount));
#else
/* Accurately naming "val" is tricky. Sometimes it will be what we
want to be the new value, but sometimes it contains the value
that is currently at the location. */
/* Load location's current value */
val = xmp_coherent_l32ai (integer);
do {
XT_WSR_SCOMPARE1 (val);
saved = val;
/* Change it to what we would like to store there--"new_val" */
val = val + amount;
/* Possibly store new_val, but reload location's current value no
matter what. */
XT_S32C1I (val, integer, 0);
if (val != saved)
xmp_spin();
} while (val != saved);
#endif
return val + amount;
}
/* xmp_atomic_int_conditional_set - Set the value of an atomic integer
Synchronizing, nonblocking
Usage:
integer - points to an initialized integer
from - believed value of the integer
eg: prev = xmp_atomic_int_value (integer);
success = xmp_atomic_int_conditional_set (integer, 1, prev);
to - new value
Returns: current value of integer - user should check if it matches
the previous value of the integer. If it does, then the update
was successful.
*/
static inline int
xmp_atomic_int_conditional_set (xmp_atomic_int_t * integer, int from, int to)
{
int val;
/* Don't even try to update if the integer's value isn't what we
think it should be. This prevents acquiring this cache-line for
writing and therefore prevents bus transactions when various
cores contend. */
val = xmp_coherent_l32ai(integer);
if (val == from) {
XT_WSR_SCOMPARE1 (from);
val = to;
/* Possibly store to, but reload location's current value no
matter what. */
XT_S32C1I (val, integer, 0);
}
return val;
}
/* Macros to implement trivial spin locks. These are very primitive, but
can be useful when you don't need the higher-overhead synchronization.
To use an xmp_atomic_int_t as a trivial spin lock, you should
initialize it to zero first.
*/
#define XMP_SIMPLE_SPINLOCK_ACQUIRE(atomic_int_ptr) \
{ while (xmp_atomic_int_conditional_set (atomic_int_ptr, 0, xmp_prid() + 1) != 0) \
xmp_spin(); }
#define XMP_SIMPLE_SPINLOCK_RELEASE(atomic_int_ptr) \
{ while (xmp_atomic_int_conditional_set (atomic_int_ptr, xmp_prid() + 1, 0) != xmp_prid() + 1) \
xmp_spin(); }
#define XMP_SIMPLE_SPINLOCK_OWNER(atomic_int_ptr) (xmp_atomic_int_value(atomic_int_ptr) - 1)
/* -------------------------------------------------------------------------
xmp_mutex_t - An even higher-level data structure to enforce
mutual exclusion between cores. A core which waits on a mutex might
sleep with a waiti and be interrupted by an interrupt.
Mutexes can be normal or recursive. For a normal mutex, a core
attempting to acquire a mutex it already holds will result in
deadlock. For a recursive mutex, a core will succeed in acquiring a
mutex it already holds, and must release it as many times as it
acquired it.
Mutexes are not sharable between interrupt levels--because
ownership is tracked by core, not thread.
Like all xmp data structures, an object of type xmp_mutex_t
should be treated by the programmer as opaque. They are only
public in this header file to allow them to be declared statically.
For configurations with 16-byte cache lines, this has the most
frequently used and changed data in the first line.
*/
#if XCHAL_DCACHE_IS_COHERENT
typedef struct xmp_mutex_t {
xmp_atomic_int_t qlock;
unsigned int qhead;
unsigned int qtail;
unsigned char queue[XMP_MAX_CORES];
unsigned short held;
unsigned char owner;
unsigned char recursive : 1;
unsigned char trace : 1;
unsigned char system : 1;
unsigned char unused : 5;
const char * name;
} xmp_mutex_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE)));
#define XMP_MUTEX_INITIALIZER(name) \
{ 0, 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \
0, XMP_NO_OWNER, XMP_MUTEX_FLAG_NORMAL, 0, 0, 0, name }
#define XMP_RECURSIVE_MUTEX_INITIALIZER(name) \
{ 0, 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \
0, XMP_NO_OWNER, XMP_MUTEX_FLAG_RECURSIVE, 0, 0, 0, name }
#define XMP_MUTEX_FLAG_NORMAL 0
#define XMP_MUTEX_FLAG_RECURSIVE 1
#define XMP_MUTEX_ACQUIRE_FAILED -1
#define XMP_MUTEX_ERROR_DESTROY_OWNED -2
#define XMP_MUTEX_ERROR_NOT_OWNED -3
#define XMP_MUTEX_ERROR_ALREADY_OWNED -4
/*
xmp_mutex_init
Nonsynchronizing
Nonblocking
Usage:
mutex - points to an uninitialized mutex
name - name if you want one, NULL if not.
recursive - use recursive semantices
Returns
zero on success (always succeeds)
*/
extern int xmp_mutex_init (xmp_mutex_t * mutex,
const char * name,
unsigned int recursive);
/*
int xmp_mutex_destroy (xmp_mutex_t * mutex);
Synchronizing - will fail if mutex is held by anyone -- including
current processor
Nonblocking
Usage:
mutex - points to a mutex
Returns
zero on success
non-zero if mutex is held
*/
extern int xmp_mutex_destroy (xmp_mutex_t * mutex);
/*
xmp_mutex_lock -- Synchronizing
xmp_mutex_trylock
Usage:
mutex - points to a mutex
Returns
zero on success
*/
extern int xmp_mutex_lock (xmp_mutex_t * mutex);
extern int xmp_mutex_trylock (xmp_mutex_t * mutex);
/*
xmp_mutex_unlock
Synchronizing
Nonblocking
Usage:
mutex - points to a mutex
Returns
zero on success - mutex is released
non-zero on failure - mutex is owned by another core
- prid of processor that does own it
note that by the time this function
returns, the owner of the core may
have changed.
*/
extern int xmp_mutex_unlock (xmp_mutex_t * mutex);
/*
xmp_mutex_name
Nonsynchronizing
Nonblocking
Usage:
mutex - points to a mutex
Returns the name of the given mutex, which may be NULL.
*/
const char * xmp_mutex_name (const xmp_mutex_t * mutex);
/*
xmp_mutex_trace_on
xmp_mutex_trace_off
Nonsynchronizing
Nonblocking
Turn off and on tracing for the mutex.
These functions are only present in the debug version of the library.
*/
extern void xmp_mutex_trace_on (xmp_mutex_t * mutex);
extern void xmp_mutex_trace_off (xmp_mutex_t * mutex);
/* -------------------------------------------------------------------------
xmp_condition_t
Condition Variables following Mesa semantics.
Condition variables are not sharable among interrupt levels.
*/
typedef struct xmp_condition_t {
unsigned int qhead;
unsigned int qtail;
unsigned char queue[XMP_MAX_CORES];
unsigned int waiting[XMP_MAX_CORES];
unsigned char trace : 1;
unsigned char unused : 7;
const char * name;
} xmp_condition_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE)));
#define XMP_CONDITION_INITIALIZER(name) \
{ 0, -1, {XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER, XMP_NO_OWNER}, \
{0, 0, 0, 0}, 0, 0, name}
/* xmp_condition_init - Initialize a condition variable
Nonsynchronizing, Nonblocking
Usage:
condition - pointer to an xmp_condition_t
On exit:
condition initialized
Errors: none
*/
extern int xmp_condition_init (xmp_condition_t * condition,
const char * name);
extern int xmp_condition_destroy (xmp_condition_t * condition);
/* xmp_condition_wait - Wait for a condition variable
Synchronizing, blocking
Usage:
condition - pointer to an xmp_condition_t
mutex - pointer to an xmp_mutex_t already acquired by the calling
process
Errors: if the mutex isn't held by this core
*/
extern int xmp_condition_wait (xmp_condition_t * condition,
xmp_mutex_t * mutex);
/* xmp_condition_signal
- Signal the first (if any) core waiting on a condition variable
You must hold the mutex you passed to xmp_condition_wait before
calling this function.
Synchronizing, nonblocking
Usage:
condition - pointer to an xmp_condition_t
Errors: none
*/
extern int xmp_condition_signal (xmp_condition_t * condition);
/* xmp_condition_broadcast
- Signal all cores waiting on a condition variable
Synchronizing, nonblocking
You must hold the mutex you passed to xmp_condition_wait before
calling this function.
Usage:
condition - pointer to an xmp_condition_t
Errors: none
*/
extern int xmp_condition_broadcast (xmp_condition_t * condition);
static inline const char * xmp_condition_name (const xmp_condition_t * condition)
{
return condition->name;
}
/*
xmp_condition_trace_on
xmp_condition_trace_off
Nonsynchronizing
Nonblocking
Turn off and on statistics and tracing for the condition. For
tracing you must also set a trace file for the core.
These functions are only present in the debug-version of the library.
*/
extern void xmp_condition_trace_on (xmp_condition_t * condition);
extern void xmp_condition_trace_off (xmp_condition_t * condition);
#endif /* XCHAL_DCACHE_IS_COHERENT */
/* -------------------------------------------------------------------------
xmp_barrier_t
Classic barriers that stop any core from continuing until a
specified number of cores reach that point. Once the barrier allows
cores through, the barrier is reset and will stop cores from
progressing again.
Barriers are not sharable among interrupt levels.
*/
typedef struct xmp_barrier_t
{
xmp_atomic_int_t count;
xmp_atomic_int_t state;
xmp_atomic_int_t sleeping;
unsigned short num_cores;
unsigned short trace : 1;
unsigned short system : 1;
const char * name;
} xmp_barrier_t __attribute__ ((aligned (XMP_MAX_DCACHE_LINESIZE)));
#define XMP_BARRIER_INITIALIZER(number, name) \
{ 0, 0, 0, number, 0, 0, name }
/* xmp_barrier_init - Initialize a barrier
Nonsynchronizing, Nonblocking
Usage:
barrier - pointer to an xmp_barrier_t
num_cores - number of cores needed to arrive at the
barrier before any are allowed through
On exit:
barrier initialized
Always returns zero.
Errors: none
*/
extern int xmp_barrier_init (xmp_barrier_t * barrier, int num_cores,
const char * name);
/* xmp_barrier_wait - Wait on a barrier
Nonsynchronizing, Nonblocking
Usage:
barrier - pointer to an xmp_barrier_t
On exit:
Enough cores (as determined at the barrier's initialization)
have reached the barrier.
Errors: none
*/
extern int xmp_barrier_wait (xmp_barrier_t * barrier);
static inline const char * xmp_barrier_name (const xmp_barrier_t * barrier)
{
return barrier->name;
}
/*
xmp_barrier_trace_on
xmp_barrier_trace_off
Nonsynchronizing
Nonblocking
Turn on and off tracing for the barrier. For
tracing you must also set a trace file for the core.
These functions are only present in the debug-version of the library.
*/
extern void xmp_barrier_trace_on (xmp_barrier_t * barrier);
extern void xmp_barrier_trace_off (xmp_barrier_t * barrier);
/* -------------------------------------------------------------------------
Portions of the library that are internal, but belong here for
convenience.
*/
extern xmp_atomic_int_t _ResetSync;
static inline void
xmp_initial_sync (int num_cores)
{
xmp_atomic_int_increment (&_ResetSync, 1);
while (xmp_coherent_l32ai (&_ResetSync) != num_cores)
xmp_spin ();
}
#ifdef __cplusplus
}
#endif
#endif /* _XMP_LIBRARY_H */

524
components/esp32/include/xtensa/xos.h
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@@ -1,524 +0,0 @@
/** @file */
// xos.h - XOS API interface and data structures visible to user code.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __XOS_H__
#define __XOS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "xos_types.h"
#include <xtensa/config/core.h>
#if XCHAL_HAVE_INTERRUPTS
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_interrupt.h>
#endif
#include "xos_common.h"
#include "xos_errors.h"
#include "xos_regaccess.h"
//-----------------------------------------------------------------------------
// Convert x into a literal string.
//-----------------------------------------------------------------------------
#define _XOS_STR(x) __XOS_STR(x)
#define __XOS_STR(x) #x
//-----------------------------------------------------------------------------
// XOS version.
//-----------------------------------------------------------------------------
#define XOS_VERSION_MAJOR 1
#define XOS_VERSION_MINOR 10
#define XOS_VERSION_STRING "1.10" ///< XOS version string.
//-----------------------------------------------------------------------------
// Runtime error handling.
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
///
/// Reports a fatal error and halts XOS operation, i.e. halts the system. This
/// function will call a user-registered error handler (if one has been set)
/// and then halt the system. The user handler may do system-specific things
/// such as record the error reason in nonvolatile memory etc.
///
/// \param errcode Error code. May be any user defined value < 0.
/// Values >=0 are reserved for use by the system.
///
/// \param errmsg Optional text string describing the error.
///
/// \return This function does not return.
///
//-----------------------------------------------------------------------------
void
xos_fatal_error(int32_t errcode, const char * errmsg);
#if XOS_DEBUG
// Do not call directly.
void
xos_assert(const char * file, int32_t line);
//-----------------------------------------------------------------------------
///
/// Check condition and fail if condition expression is false.
/// In debug builds, an assertion failure will cause a fatal error to be
/// reported. In non-debug builds, assertions are compiled out.
///
/// NOTE: Remember that any code in XOS_ASSERT() statements gets compiled out
/// for non-debug builds.
///
//-----------------------------------------------------------------------------
#define XOS_ASSERT(expr) if ((expr) == 0) xos_assert(__FILE__, __LINE__)
#else
#define XOS_ASSERT(expr)
#endif
//-----------------------------------------------------------------------------
///
/// Interrupt handler function pointer type.
///
//-----------------------------------------------------------------------------
typedef void (XosIntFunc)(void * arg);
//-----------------------------------------------------------------------------
///
/// Print handler function pointer type.
///
//-----------------------------------------------------------------------------
typedef int32_t (XosPrintFunc)(void * arg, const char * fmt, ...);
//-----------------------------------------------------------------------------
///
/// Fatal error handler function pointer type.
///
//-----------------------------------------------------------------------------
typedef void (XosFatalErrFunc)(int32_t errcode, const char * errmsg);
//-----------------------------------------------------------------------------
///
/// Exception handler function pointer type.
///
//-----------------------------------------------------------------------------
typedef void (XosExcHandlerFunc)(XosExcFrame * frame);
//-----------------------------------------------------------------------------
///
/// Install a user defined exception handler for the specified exception type.
/// This will override the default XOS exception handler. The handler is a C
/// function that is passed one parameter -- a pointer to the exception frame.
/// The exception frame is allocated on the stack of the thread that caused the
/// exception, and contains saved state and exception information. For details
/// of the exception frame see the structure XosExcFrame.
///
/// \param exc Exception type (number) to override. The exception
/// numbers are enumerated in <xtensa/corebits.h>.
///
/// \param handler Pointer to handler function to be installed.
/// To revert to the default handler, pass NULL.
///
/// \return Returns a pointer to previous handler installed, if any.
///
//-----------------------------------------------------------------------------
XosExcHandlerFunc *
xos_register_exception_handler(int32_t exc, XosExcHandlerFunc * handler);
//-----------------------------------------------------------------------------
///
/// Install a user defined fatal error handler. This function will be called if
/// a fatal error is reported either by user code or by XOS itself. It will be
/// passed the same arguments that are passed to xos_fatal_error().
///
/// The handler need not return. It should make minimal assumptions about the
/// state of the system. In particular, it should not assume that further XOS
/// system calls will succeed.
///
/// \param handler Pointer to handler function to be installed.
///
/// \return Returns a pointer to previous handler installed, if any.
///
//-----------------------------------------------------------------------------
XosFatalErrFunc *
xos_register_fatal_error_handler(XosFatalErrFunc * handler);
#ifdef _XOS_INCLUDE_INTERNAL_
# include "xos_internal.h"
#endif
#include "xos_thread.h"
#include "xos_timer.h"
#include "xos_cond.h"
#include "xos_event.h"
#include "xos_mutex.h"
#include "xos_msgq.h"
#include "xos_semaphore.h"
#include "xos_stopwatch.h"
//-----------------------------------------------------------------------------
///
/// Register a handler function to call when interrupt "num" occurs.
///
/// For level-triggered and timer interrupts, the handler function will have
/// to clear the source of the interrupt before returning, to avoid infinitely
/// retaking the interrupt. Edge-triggered and software interrupts are
/// automatically cleared by the OS interrupt dispatcher (see xos_handlers.S).
///
/// \param num Xtensa internal interrupt number (0..31). To
/// refer to a specific external interrupt number
/// (BInterrupt pin), use HAL macro XCHAL_EXTINTx_NUM
/// where 'x' is the external number.
///
/// \param handler Pointer to handler function.
///
/// \param arg Argument passed to handler.
///
/// \return Returns XOS_OK if successful, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_register_interrupt_handler(int32_t num, XosIntFunc * handler, void * arg);
//-----------------------------------------------------------------------------
///
/// Unregister a handler function for interrupt "num". If no handler was
/// installed, this function will have no effect.
///
/// \param num Xtensa internal interrupt number (0..31). To
/// refer to a specific external interrupt number
/// (BInterrupt pin), use HAL macro XCHAL_EXTINTx_NUM
/// where 'x' is the external number.
///
/// \return Returns XOS_OK if successful, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_unregister_interrupt_handler(int32_t num);
//-----------------------------------------------------------------------------
///
/// Register a high priority interrupt handler for interrupt level "level".
///
/// Unlike low and medium priority interrupt handlers, high priority handlers
/// are not installed for a specific interrupt number, but for an interrupt
/// level. The level must be above XCHAL_EXCM_LEVEL. The handler function must
/// be written in assembly since C handlers are not supported for levels above
/// XCHAL_EXCM_LEVEL. The handler function must preserve all registers except
/// a0, and must return to the dispatcher via a "ret" instruction, not "rfi".
///
/// NOTE: This method of dispatch takes a few cycles of overhead. If you wish
/// to save even these cycles, then you can define your own dispatch function
/// to override the built-in dispatcher. See xos_handlers.S for more details.
///
/// \param level The interrupt level to be handled.
///
/// \param handler Pointer to handler function.
///
/// \return Returns XOS_OK if successful, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_register_hp_interrupt_handler(int32_t level, void * handler);
//-----------------------------------------------------------------------------
///
/// Enable a specific interrupt, by interrupt number.
/// The state (enabled vs. disabled) of individual interrupts is global, i.e.
/// not associated with any specific thread. Depending on system options and
/// implementation, this state may be stored in one of two ways:
/// - directly in the INTENABLE register, or
/// - in a global variable (this is generally the case when INTENABLE is used
/// not just to control what interrupts are enabled globally, but also for
/// software interrupt prioritization within an interrupt level, effectively
/// providing finer grained levels; in this case XOS takes care to update
/// INTENABLE whenever either the global enabled-state variable or the
/// per-thread fine-grained-level variable change).
/// Thus it is best to never access the INTENABLE register directly.
///
/// To modify thread-specific interrupt priority level, use one of:
/// - xos_set_int_pri_level()
/// - xos_restore_int_pri_level()
/// - xos_disable_interrupts()
/// - xos_restore_interrupts()
///
/// NOTE: To refer to a specific external interrupt number (BInterrupt pin),
/// use HAL macro XCHAL_EXTINTx_NUM where 'x' is the external interrupt
/// number. For example, to enable external interrupt 3 (BInterrupt[3]),
/// you can use:
///
/// xos_interrupt_enable( XCHAL_EXTINT3_NUM );
///
/// \param intnum Interrupt number to enable. Must range between 0-31.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
void
xos_interrupt_enable(uint32_t intnum);
//-----------------------------------------------------------------------------
///
/// Disable a specific individual interrupt, by interrupt number.
///
/// This is the counterpart to xos_interrupt_enable(). See the description
/// of xos_interrupt_enable() for further comments and notes.
///
/// \param intnum Interrupt number to disable. Must range between 0-31.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
void
xos_interrupt_disable(uint32_t intnum);
//-----------------------------------------------------------------------------
///
/// Get the CPU's current interrupt priority level. Interrupts at or below this
/// priority level are blocked.
///
/// \return Returns the current IPL, ranging from 0 to XCHAL_NUM_INTLEVELS.
///
//-----------------------------------------------------------------------------
static inline uint32_t
xos_get_int_pri_level(void)
{
#if XCHAL_HAVE_INTERRUPTS
return XT_RSR_PS() & 0xF;
#else
return 0;
#endif
}
//-----------------------------------------------------------------------------
///
/// Set the CPU's interrupt priority level to the specified level, but only if
/// the current IPL is below the one requested. This function will never cause
/// the interrupt priority level to be lowered from the current level.
/// Call this function to block interrupts at or below the specified priority
/// level.
///
/// When setting the IPL temporarily (such as in a critical section), call
/// xos_set_int_pri_level(), execute the critical code section, and then call
/// xos_restore_int_pri_level().
///
/// The interrupt priority level is part of the thread context, so it is saved
/// and restored across context switches. To enable and disable individual
/// interrupts globally, use the functions xos_interrupt_enable() and
/// xos_interrupt_disable() instead.
///
/// NOTE: It is usually not required to disable interrupts at a level higher
/// than that of the highest priority interrupt that interacts with the OS
/// (i.e. calls into XOS such that threads may be woken / blocked /
/// reprioritized / switched, or otherwise access XOS data structures).
/// In XOS, that maximum level is XOS_MAX_OS_INTLEVEL, which defaults to
/// XCHAL_EXCM_LEVEL. This may be modified by editing xos_params.h and
/// rebuilding XOS.
///
/// \param level The new interrupt priority level (IPL).
///
/// \return Returns a value that can be used to restore the previous
/// priority level by calling xos_restore_int_pri_level(). This
/// value should be treated as opaque by application code, and
/// should be passed unchanged to the restore function.
///
//-----------------------------------------------------------------------------
__attribute__((always_inline))
static inline uint32_t
xos_set_int_pri_level(uint32_t level)
{
#if XCHAL_HAVE_INTERRUPTS
#pragma no_reorder
uint32_t ps = XT_RSR_PS();
if (level > (ps & 0xF)) {
level = (ps & ~0xF) | level;
XT_WSR_PS(level);
XT_RSYNC();
}
return ps;
#else
return 0;
#endif
}
//-----------------------------------------------------------------------------
///
/// Restores the CPU to a previously saved interrupt priority level. This level
/// must have been obtained by calling xos_set_int_pri_level().
///
/// \param oldval Return value from xos_set_int_pri_level().
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
__attribute__((always_inline))
static inline void
xos_restore_int_pri_level(const uint32_t oldval)
{
#if XCHAL_HAVE_INTERRUPTS
#pragma no_reorder
XT_WSR_PS(oldval);
XT_RSYNC();
#else
// Nothing
#endif
}
//-----------------------------------------------------------------------------
///
/// Disable all interrupts that can interact directly with the OS. This is a
/// convenience function, shorthand for setting the IPL to XOS_MAX_OS_INTLEVEL.
///
/// Returns: A value that can be used to restore the previous priority level
/// by calling xos_restore_interrupts(). This value should be treated as
/// opaque by application code, and should be passed unchanged to the restore
/// function.
///
//-----------------------------------------------------------------------------
static inline uint32_t
xos_disable_interrupts(void)
{
return xos_set_int_pri_level(XOS_MAX_OS_INTLEVEL);
}
//-----------------------------------------------------------------------------
///
/// Restore the CPU's previously saved interrupt status. This is a convenience
/// function, the counterpart to xos_disable_interrupts().
///
/// \return rval Return value from xos_disable_interrupts().
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
static inline void
xos_restore_interrupts(uint32_t rval)
{
xos_restore_int_pri_level(rval);
}
#ifdef _XOS_INCLUDE_INTERNAL_
//-----------------------------------------------------------------------------
// Enter an OS critical section, i.e. get exclusive access to OS critical
// state and data structures. Code that manipulates the state of OS objects
// or modifies internal OS state must call this function first, to ensure
// that it has exclusive access. On a single-core system, this is equivalent
// to blocking all interrupts that can interact directly with the OS, i.e.
// all interrupts at or below XOS_MAX_OS_INTLEVEL. In a multi-core system
// this is likely to be implemented differently to achieve the same effect.
//
// Returns: A value that is to be used to restore the state of the CPU when
// exiting the critical section. This must be treated as opaque and passed
// unmodified to xos_critical_exit().
//
// NOTE: This function is meant for use in OS code, not in applications.
//-----------------------------------------------------------------------------
__attribute__((always_inline))
static inline uint32_t
xos_critical_enter(void)
{
#if XCHAL_HAVE_INTERRUPTS
// This function cannot be called by high-level interrupt handlers,
// i.e. it can never be called with intlevel > XOS_MAX_OS_INTLEVEL.
// So, we do not need to check current intlevel because we will not
// ever be lowering it by setting it to XOS_MAX_OS_INTLEVEL.
// NOTE: sync after RSIL not needed.
return XT_RSIL(XOS_MAX_OS_INTLEVEL);
#else
return 0;
#endif
}
//-----------------------------------------------------------------------------
// Exit an OS critical section and restore CPU state. See the documentation
// for xos_critical_enter().
//
// cflags Return value from xos_critical_enter().
// Must be treated as an opaque value.
//
// Returns: Nothing.
//
// NOTE: This function is meant for use in OS code, not in applications.
//-----------------------------------------------------------------------------
__attribute__((always_inline))
static inline void
xos_critical_exit(uint32_t cflags)
{
xos_restore_int_pri_level(cflags);
}
#endif // _XOS_INCLUDE_INTERNAL_
// This file uses things defined above
#include "xos_syslog.h"
// Misc
//-----------------------------------------------------------------------------
// Helper function to list all threads in system. Useful for debug.
//-----------------------------------------------------------------------------
void
xos_display_threads(void * arg, XosPrintFunc * print_fn);
#ifdef __cplusplus
}
#endif
#endif // __XOS_H__

362
components/esp32/include/xtensa/xos_common.h
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@@ -1,362 +0,0 @@
// xos_common.h - Macros and definitions common to C and assembly code.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __XOS_COMMON_H__
#define __XOS_COMMON_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include <xtensa/config/tie.h>
#include "xos_params.h"
//-----------------------------------------------------------------------------
// Macros that help define structures for both C and assembler.
// These are somewhat different from the XTOS version in xtruntime-frames.h.
//-----------------------------------------------------------------------------
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define STRUCT_BEGIN .pushsection .text; .struct 0
#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size
#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
#define STRUCT_END(sname) sname##Size:; .popsection
#else
#define STRUCT_BEGIN typedef struct {
#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
#define STRUCT_END(sname) } sname;
#endif //_ASMLANGUAGE || __ASSEMBLER__
//-----------------------------------------------------------------------------
// Offsets relative to xos_globals.
//-----------------------------------------------------------------------------
#define XOS_INTLEVEL_MASK 0 // offset to the level mask
#define XOS_INTENABLE_MASK 4 // offset to the enable mask
#define XOS_CURR_THREADPTR 8 // offset to the current thread ptr
#define XOS_NEXT_THREADPTR 12 // offset to the next thread ptr
#define XOS_INTERRUPT_TABLE 16 // offset to the interrupt table
//-----------------------------------------------------------------------------
// Offsets for xos_interrupt_table[] entries.
//-----------------------------------------------------------------------------
#define XOS_INTTAB_HANDLER (XOS_INTERRUPT_TABLE+0) // ofs to interrupt handler
#define XOS_INTTAB_ARG (XOS_INTERRUPT_TABLE+4) // ofs to interrupt handler arg
#define XOS_INTTAB_PS (XOS_INTERRUPT_TABLE+8) // (hwpri) PS for interrupt level
#define XOS_INTTAB_LEVEL (XOS_INTERRUPT_TABLE+8) // (swpri) interrupt level (1..7)
#define XOS_INTTAB_PRI (XOS_INTERRUPT_TABLE+9) // (swpri) interrupt priority (0..255)
#define XOS_INTTAB_PRIMASK (XOS_INTERRUPT_TABLE+12) // (swpri) mask of higher pri. interrupts
//-----------------------------------------------------------------------------
// Exception/interrupt stack frame layout for a pre-empted thread
// tcb->resume_fn == &xos_resume_preempted_thread).
// Pointed to by thread->esf. Located just below thread's current stack ptr.
// Thread's a1 == thread->esf + XosExcFrameSize.
// NOTE: exception frame size is a multiple of 16.
//-----------------------------------------------------------------------------
STRUCT_BEGIN
STRUCT_AFIELD(long,4,FRAME_AREG,areg, 12) // a4-a15 (offsets 0 thru 44)
// (a1 is computed, a0,a2-a3 are in s32e range of a1)
//#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,FRAME_LBEG,lbeg)
STRUCT_FIELD (long,4,FRAME_LEND,lend)
STRUCT_FIELD (long,4,FRAME_LCOUNT,lcount)
//#endif
//#if XCHAL_HAVE_MAC16
STRUCT_FIELD (long,4,FRAME_ACCLO,acclo)
STRUCT_FIELD (char,1,FRAME_ACCHI,acchi)
//#endif
STRUCT_FIELD (char,1,FRAME_SAR,sar)
STRUCT_FIELD (short,2,FRAME_PAD0,pad0) // unused
STRUCT_FIELD (long,4,FRAME_EXCCAUSE,exccause)
STRUCT_FIELD (long,4,FRAME_EXCVADDR,excvaddr)
STRUCT_FIELD (long,4,FRAME_PAD1,pad1) // unused -- pad to make multiple of 16 bytes
STRUCT_FIELD (long,4,FRAME_PAD2,pad2)
STRUCT_FIELD (long,4,FRAME_PS,ps) // (XOS_FRAME_SIZE-44) in S32E range of end
STRUCT_FIELD (long,4,FRAME_PC,pc) // (XOS_FRAME_SIZE-40) in S32E range of end
STRUCT_FIELD (long,4,FRAME_A0,a0)
STRUCT_FIELD (long,4,FRAME_A2,a2) // (XOS_FRAME_SIZE-32) in S32E range of end
STRUCT_FIELD (long,4,FRAME_A3,a3) // (XOS_FRAME_SIZE-28) in S32E range of end
STRUCT_FIELD (long,4,FRAME_LEVELMASK,levelmask) //
STRUCT_FIELD (long,4,FRAME_NESTCHAIN,nestchain) // nested C function call chain ptr
// Caller's a0-a3 save area below SP. These fields MUST be the last ones in the
// struct so that they are guaranteed to be just under the original SP (before
// we allocate the exception frame).
STRUCT_AFIELD (long,4,FRAME_CWINSAVE,cwinsave, 4) // (XOS_FRAME_SIZE-16)
STRUCT_END(XosExcFrame) // NOTE: exception frame size is 128
#define FRAME_AR(x) (FRAME_AREG + x*4 - 16)
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define XOS_FRAME_SIZE XosExcFrameSize
#else
#define XOS_FRAME_SIZE sizeof(XosExcFrame)
#endif
//-----------------------------------------------------------------------------
// Stack frame layout for a cooperatively switched out thread
// (tcb->resume_fn == &xos_resume_cooperative_thread).
// Pointed to by thread->esf. This is a function frame.
// Thread's a1 == thread->esf.
//-----------------------------------------------------------------------------
STRUCT_BEGIN
STRUCT_FIELD (long,4,CFRAME_A0,a0) // return PC
STRUCT_FIELD (long,4,CFRAME_LEVELMASK,levelmask)
STRUCT_FIELD (long,4,CFRAME_PS,ps)
#ifdef __XTENSA_CALL0_ABI__
STRUCT_FIELD (long,4,CFRAME_PAD0,pad0)
STRUCT_AFIELD(long,4,CFRAME_AREG,areg,4) // callee-saved regs a12-a15
#endif
STRUCT_END(XosCoopFrame)
//-----------------------------------------------------------------------------
// Offsets into thread control block (must match xos_thread.h !!)
//-----------------------------------------------------------------------------
#define TCB_RESUME_FN 12 // ptr to thread resume asm sequence
#define TCB_STACK_ESF 16 // saved stack ptr (actually, ptr to ESF)
#define TCB_TIE_SAVE 20 // ptr to TIE save area
#define TCB_RETVALUE 24 // ptr to xos_block return value
#define TCB_STACK_END 36 // ptr to end of stack (thread's initial stack ptr)
#define TCB_STARTUP_ENTRY 40 // ptr to thread entry function
#define TCB_STARTUP_ARG 44 // ptr to thread entry function's arg
#define TCB_READY 48 // thread ready state (1 byte)
#define TCB_CLIB_PTR 108 // thread C lib context pointer
#define TCB_RESUME_CCOUNT 116 // cycle count at last resume
#define TCB_CYCLE_COUNT 120 // number of cycles consumed
#define TCB_NORMAL_RESUMES 128 // number of cooperative/restart thread resumes
#define TCB_PREEMPT_RESUMES 132 // number of pre-emptive thread resumes
//-----------------------------------------------------------------------------
// Coprocessor state handling:
// The coprocessor state save area is allocated on the thread stack. The stack
// must be sized appropriately. Threads that do not use coprocessors need not
// allocate the storage area.
//
// Along with the save area for each coprocessor, two bitmasks with flags per
// coprocessor (laid out as in the CPENABLE reg) help manage context switching
// coprocessors as efficiently as possible:
//
// XT_CPENABLE
// The contents of a non-running thread's CPENABLE register.
// It represents the coprocessors owned (and whose state is still needed)
// by the thread. When a thread is preempted, its CPENABLE is saved here.
// When a thread solicits a context switch, its CPENABLE is cleared - the
// compiler has saved the (caller-saved) coprocessor state if needed.
// When a non-running thread loses ownership of a CP, its bit is cleared.
// When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
// Avoids coprocessor exceptions when no change of ownership is needed.
//
// XT_CPSTORED
// A bitmask with the same layout as CPENABLE, a bit per coprocessor.
// Indicates whether the state of each coprocessor is saved in the state
// save area. When a thread enters the kernel, only the state of coprocs
// still enabled in CPENABLE is saved. When the coprocessor exception
// handler assigns ownership of a coprocessor to a thread, it restores
// the saved state only if this bit is set, and clears this bit.
//
// XT_CP_CS_ST
// A bitmask with the same layout as CPENABLE, a bit per co-processor.
// Indicates whether callee-saved state is saved in the state save area.
// Callee-saved state is saved by itself on a solicited context switch,
// and restored when needed by the coprocessor exception handler.
// Unsolicited switches will cause the entire coprocessor to be saved
// when necessary.
//
// XT_NCP_ASA
// Pointer to aligned save area for non-CP state. This is always filled
// in, even if there is no non-CP state to be saved. If there is no state
// to be saved then no space is actually allocated and this pointer is
// not used.
//
// XT_CP_ASA
// Pointer to aligned save area for coprocessor state. This is filled in
// only if coprocessor state is to be saved for the thread. Allows it to be
// aligned more than the overall save area (which might be stack-aligned
// or TCB-aligned). Especially relevant for Xtensa cores configured with a
// very large data path that requires alignment greater than 16 bytes (ABI
// stack alignment).
//-----------------------------------------------------------------------------
#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
// Offsets of each coprocessor save area within the 'aligned save area'.
// The non-CP TIE state save area is at offset 0, so that it does not
// move around if some or all coprocessors are not to be saved.
#define XT_NCP_SA 0
#define XT_CP0_SA ALIGNUP(XCHAL_CP0_SA_ALIGN, XT_NCP_SA + XCHAL_NCP_SA_SIZE)
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
#define XT_TOT_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
#define XT_NCP_SA_SIZE XCHAL_NCP_SA_SIZE
// Offsets within the overall save area
#define XT_CPENABLE 0 // (2 bytes) coprocessors active for this thread
#define XT_CPSTORED 2 // (2 bytes) coprocessors saved for this thread
#define XT_CP_CS_ST 4 // (2 bytes) coprocessor callee-saved regs for this thread
#define XT_NCP_ASA 8 // (4 bytes) ptr to aligned save area for nonCP state
#define XT_CP_ASA 12 // (4 bytes) ptr to aligned save area for CP state
// Overall size allows for dynamic alignment, make sure multiple of 4 bytes.
// XT_CP_SIZE - total space needed for all coprocessors + nonCP state + hdr
// XT_NCP_SIZE - total space needed for nonCP state + hdr
#define XT_CP_SIZE ALIGNUP(4, (16 + XT_TOT_SA_SIZE + XCHAL_TOTAL_SA_ALIGN))
#define XT_NCP_SIZE ALIGNUP(4, (16 + XT_NCP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN))
//-----------------------------------------------------------------------------
// Stack size computation.
//
// XOS_STACK_MIN_SIZE
// The minimum recommended stack size for any XOS thread. If you want to
// use a stack size smaller than this, you will have to verify that the
// smaller size will work under all operating conditions.
//
// XOS_STACK_MIN_SIZE_NO_CP
// The minimum recommended atack size for threads that will not use any
// coprocessor resources. No coprocessor state will be saved/restored
// for these threads. Non-CP TIE state will still be saved/restored.
// These threads must be created with the flag XOS_THREAD_NO_CP.
//
// XOS_STACK_EXTRA
// The amount of stack space used by the system to:
// - save coprocessor state
// - save non-coprocessor TIE state
// - allocate an interrupt/exception frame
//
// XOS_STACK_EXTRA_NO_CP
// The amount of stack space used by the system to:
// - save non-coprocessor TIE state
// - allocate an interrupt/exception frame
//-----------------------------------------------------------------------------
#define XOS_STACK_EXTRA (XOS_FRAME_SIZE + XT_CP_SIZE)
#define XOS_STACK_EXTRA_NO_CP (XOS_FRAME_SIZE + XT_NCP_SIZE)
#ifdef __XTENSA_CALL0_ABI__
#define XOS_STACK_MIN_SIZE (XOS_STACK_EXTRA + 0x180)
#define XOS_STACK_MIN_SIZE_NO_CP (XOS_STACK_EXTRA_NO_CP + 0x180)
#else
#define XOS_STACK_MIN_SIZE (XOS_STACK_EXTRA + 0x200)
#define XOS_STACK_MIN_SIZE_NO_CP (XOS_STACK_EXTRA_NO_CP + 0x200)
#endif
//-----------------------------------------------------------------------------
// Items related to C library thread safety.
//-----------------------------------------------------------------------------
#if XOS_OPT_THREAD_SAFE_CLIB
#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#include <sys/reent.h>
#endif
#define CLIB_THREAD_STRUCT struct _reent xclib_reent
#define GLOBAL_CLIB_PTR _reent_ptr
#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#include <sys/reent.h>
#endif
#define CLIB_THREAD_STRUCT struct _reent newlib_reent
#define GLOBAL_CLIB_PTR _impure_ptr
#else
#error The selected C runtime library is not thread safe.
#endif
#endif // XOS_OPT_THREAD_SAFE_CLIB
//-----------------------------------------------------------------------------
// Check (MAX_OS_INTLEVEL,EXCM_LEVEL)
//-----------------------------------------------------------------------------
#if XOS_MAX_OS_INTLEVEL >= XCHAL_EXCM_LEVEL
# define XOS_MAX_OSEXCM_LEVEL XOS_MAX_OS_INTLEVEL
#else
# warning "XOS_MAX_OS_INTLEVEL was set below XCHAL_EXCM_LEVEL: this was never tested"
# define XOS_MAX_OSEXCM_LEVEL XCHAL_EXCM_LEVEL
#endif
//-----------------------------------------------------------------------------
// Detect if in interrupt context.
//-----------------------------------------------------------------------------
#if XCHAL_HAVE_INTERRUPTS
#define INTERRUPT_CONTEXT ((XT_RSR_PS() & PS_UM) == 0)
#else
#define INTERRUPT_CONTEXT 0
#endif
//-----------------------------------------------------------------------------
// Xtensa tools version.
//-----------------------------------------------------------------------------
#if defined __XCC__
#define XTTOOLS_VERSION (__XCC__ + __XCC_MINOR__)
#else
#define XTTOOLS_VERSION (0)
#endif
//-----------------------------------------------------------------------------
// Erratum workarounds.
//-----------------------------------------------------------------------------
// Erratum 487 fix is available in version RF.3 onwards and RG.2 onwards.
#if ((__XCC__ == 11000) && (__XCC_MINOR__ >= 3)) || (XTTOOLS_VERSION >= 12002)
#define HWERR_487_FIX hw_erratum_487_fix
#else
#define HWERR_487_FIX
#endif
#ifdef __cplusplus
}
#endif
#endif // __XOS_COMMON_H__

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/** @file */
// xos_cond.h - XOS condition variables API interface and data structures.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_COND_H__
#define __XOS_COND_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
//
// Function pointer type for condition callbacks (defined in xos_thread.h)
//
// typedef int32_t (XosCondFunc)(void * arg, int32_t sig_value, XosThread * thread);
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
///
/// Condition object.
///
//-----------------------------------------------------------------------------
typedef struct XosCond {
XosThreadQueue queue; ///< Queue of waiters.
#if XOS_COND_DEBUG
uint32_t sig; // Signature indicates valid object.
#endif
} XosCond;
//-----------------------------------------------------------------------------
///
/// Initialize a condition object before first use. The object must be
/// allocated by the caller.
///
/// \param cond Pointer to condition object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
void
xos_cond_create(XosCond * cond);
//-----------------------------------------------------------------------------
///
/// Destroy a condition object. Must have been previously created by calling
/// xos_cond_create().
///
/// \param cond Pointer to condition object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
void
xos_cond_delete(XosCond * cond);
//-----------------------------------------------------------------------------
///
/// Wait on a condition: block until the condition is satisfied. The condition
/// is satisfied when xos_cond_signal() is called on this condition *and* the
/// condition callback function returns non-zero. If there is no callback
/// function, then the condition is automatically satisfied.
///
/// The condition structure must have been initialized before first use by
/// calling xos_cond_create().
///
/// \param cond Pointer to condition object.
///
/// \param cond_fn Pointer to a function, called by xos_cond_signal(),
/// that should return non-zero if this thread is to
/// be resumed. The function is invoked as:
/// `(*cond_fn)(cond_arg, sig_value)`.
///
/// \param cond_arg Argument passed to cond_fn.
///
/// \return Returns the value passed to xos_cond_signal().
///
//-----------------------------------------------------------------------------
int32_t
xos_cond_wait(XosCond * cond, XosCondFunc * cond_fn, void * cond_arg);
//-----------------------------------------------------------------------------
///
/// Trigger the condition: wake all threads waiting on the condition, if their
/// condition function evaluates to true (non-zero). If there is no condition
/// function for a thread then it is automatically awakened.
///
/// The condition structure must have been initialized before first use by
/// calling xos_cond_create().
///
/// \param cond Pointer to condition object.
///
/// \param sig_value Value passed to all waiters, returned by
/// xos_cond_wait().
///
/// \return Returns the number of waiting threads that were resumed.
///
/// NOTE: Signaling a condition that has no waiters has no effect on it, and
/// the signal is not remembered. Any thread that waits on it later must be
/// woken by another call to xos_cond_signal().
///
//-----------------------------------------------------------------------------
int32_t
xos_cond_signal(XosCond * cond, int32_t sig_value);
#ifdef __cplusplus
}
#endif
#endif // __XOS_COND_H__

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/** @file */
// xos_errors.h - XOS error codes.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_ERRORS_H__
#define __XOS_ERRORS_H__
#include "xos_types.h"
#define _XOS_ERR_FIRST (-65536)
#define _XOS_ERR_LAST (-1)
//-----------------------------------------------------------------------------
///
/// List of XOS error codes. All error codes are negative integers, except for
/// XOS_OK which is zero.
/// XOS error codes occupy the range from -65536 up to -1.
/// The function IS_XOS_ERRCODE() can be used to check if a value lies within
/// the error code range.
///
//-----------------------------------------------------------------------------
typedef enum xos_err_t {
XOS_OK = 0,
XOS_ERR_NOT_FOUND = _XOS_ERR_FIRST, ///< Object not found
XOS_ERR_INVALID_PARAMETER, ///< Function parameter is invalid
XOS_ERR_LIMIT, ///< Limit exceeded
XOS_ERR_NOT_OWNED, ///< Object not owned by caller
XOS_ERR_MUTEX_LOCKED, ///< Mutex is already locked
XOS_ERR_MUTEX_NOT_OWNED, ///< Mutex not owned by caller
XOS_ERR_MUTEX_ALREADY_OWNED, ///< Mutex already owned by caller
XOS_ERR_MUTEX_DELETE, ///< Mutex being waited on has been deleted
XOS_ERR_COND_DELETE, ///< Condition being waited on has been deleted
XOS_ERR_SEM_DELETE, ///< Semaphore being waited on has been deleted
XOS_ERR_SEM_BUSY, ///< Semaphore is not available
XOS_ERR_EVENT_DELETE, ///< Event being waited on has been deleted
XOS_ERR_MSGQ_FULL, ///< Message queue is full
XOS_ERR_MSGQ_EMPTY, ///< Message queue is empty
XOS_ERR_MSGQ_DELETE, ///< Message queue being waited on has been deleted
XOS_ERR_TIMER_DELETE, ///< Timer being waited on has been deleted
XOS_ERR_CONTAINER_NOT_RTC, ///< Containing thread not of RTC type
XOS_ERR_CONTAINER_NOT_SAME_PRI, ///< Containing thread not at same priority
XOS_ERR_STACK_TOO_SMALL, ///< Thread stack is too small
XOS_ERR_CONTAINER_ILLEGAL, ///< Illegal container thread
XOS_ERR_ILLEGAL_OPERATION, ///< This operation is not allowed
XOS_ERR_THREAD_EXITED, ///< The thread has already exited
XOS_ERR_NO_TIMER, ///< No suitable timer found
XOS_ERR_FEATURE_NOT_PRESENT, ///< This feature is disabled or not implemented
XOS_ERR_TIMEOUT, ///< Wait timed out
XOS_ERR_UNHANDLED_INTERRUPT, ///< No handler for interrupt
XOS_ERR_UNHANDLED_EXCEPTION, ///< No handler for exception
XOS_ERR_INTERRUPT_CONTEXT, ///< Operation is illegal in interrupt context
XOS_ERR_THREAD_BLOCKED, ///< Thread already blocked
XOS_ERR_ASSERT_FAILED, ///< Runtime assertion failure
XOS_ERR_CLIB_ERR, ///< Error in C library thread safety module
XOS_ERR_INTERNAL_ERROR, ///< XOS internal error
XOS_ERR_LAST = _XOS_ERR_LAST,
} xos_err_t;
//-----------------------------------------------------------------------------
///
/// Check if a value is a valid XOS error code.
///
/// \param val Value to check
///
/// \return Returns nonzero if 'val' is in the XOS error code range.
///
//-----------------------------------------------------------------------------
static inline int32_t
IS_XOS_ERRCODE(xos_err_t val)
{
return ((val >= _XOS_ERR_FIRST) && (val <= _XOS_ERR_LAST));
}
#endif // __XOS_ERRORS_H__

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/** @file */
// xos_event.h - XOS Event API interface and data structures.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_EVENT_H__
#define __XOS_EVENT_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// Defines.
//-----------------------------------------------------------------------------
#define XOS_EVENT_BITS_ALL 0xFFFFFFFF
#define XOS_EVENT_BITS_NONE 0
//-----------------------------------------------------------------------------
// Event flags.
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
///
/// Event object.
///
//-----------------------------------------------------------------------------
typedef struct XosEvent {
XosThreadQueue waitq; ///< Queue of waiters.
uint32_t bits; ///< Event bits
uint32_t mask; ///< Specifies which bits are valid
uint16_t flags; ///< Properties.
uint16_t pad; ///< Padding
#if XOS_EVENT_DEBUG
uint32_t sig; // Valid signature indicates inited.
#endif
} XosEvent;
//-----------------------------------------------------------------------------
///
/// Initialize an event object before first use.
///
/// \param event Pointer to event object.
///
/// \param mask Mask of active bits. Only these bits can be signaled.
///
/// \param flags Creation flags (currently ignored, should be zero).
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
void
xos_event_create(XosEvent * event, uint32_t mask, uint32_t flags);
//-----------------------------------------------------------------------------
///
/// Destroy an event object. Must have been previously created by calling
/// xos_event_create().
///
/// \param event Pointer to event object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
void
xos_event_delete(XosEvent * event);
//-----------------------------------------------------------------------------
///
/// Set the specified bits in the specified event. Propagates the bit states
/// to all waiting threads and wakes them if needed.
///
/// \param event Pointer to event object.
///
/// \param bits Mask of bits to set. Bits not set in the mask
/// will not be modified by this call. To set all
/// the bits in the event, use the constant
/// XOS_EVENT_BITS_ALL.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_set(XosEvent * event, uint32_t bits);
//-----------------------------------------------------------------------------
///
/// Clear the specified bits in the specified event. Propagates the bit states
/// to all waiting threads and wakes them if needed.
///
/// \param event Pointer to event object.
///
/// \param bits Mask of bits to clear. Every bit that is set in
/// the mask will be cleared from the event. Bits
/// not set in the mask will not be modified by this
/// call. To clear all the bits in an event use the
/// constant XOS_EVENT_BITS_ALL.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_clear(XosEvent * event, uint32_t bits);
//-----------------------------------------------------------------------------
///
/// Clear and set the specified bits in the specified event. The two steps are
/// combined into one update, so this is faster than calling xos_event_clear()
/// and xos_event_set() separately. Only one update is sent out to waiting
/// threads.
///
/// \param event Pointer to event object.
///
/// \param clr_bits Mask of bits to clear. The clear operation
/// happens before the set operation.
///
/// \param set_bits Mask of bits to set.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_clear_and_set(XosEvent * event, uint32_t clr_bits, uint32_t set_bits);
//-----------------------------------------------------------------------------
///
/// Get the current state of the event object. This is a snapshot of the state
/// of the event at this time.
///
/// \param event Pointer to event object.
///
/// \param pstate Pointer to a uint32_t variable where the state
/// will be returned.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_get(XosEvent * event, uint32_t * pstate);
//-----------------------------------------------------------------------------
///
/// Wait until all the specified bits in the wait mask become set in the given
/// event object.
///
/// \param event Pointer to event object.
///
/// \param bits Mask of bits to test.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_wait_all(XosEvent * event, uint32_t bits);
//-----------------------------------------------------------------------------
///
/// Wait until all the specified bits in the wait mask become set in the given
/// event object, or the timeout expires.
///
/// \param event Pointer to event object.
///
/// \param bits Mask of bits to test.
///
/// \param to_cycles Timeout in cycles. Convert from time to cycles
/// using the helper functions provided in xos_timer.
/// A value of zero indicates no timeout.
///
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else
/// error code.
///
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
/// ignored, and no timeout will occur.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_wait_all_timeout(XosEvent * event, uint32_t bits, uint64_t to_cycles);
//-----------------------------------------------------------------------------
///
/// Wait until any of the specified bits in the wait mask become set in the
/// given event object.
///
/// \param event Pointer to event object.
///
/// \param bits Mask of bits to test.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_wait_any(XosEvent * event, uint32_t bits);
//-----------------------------------------------------------------------------
///
/// Wait until any of the specified bits in the wait mask become set in the
/// event object, or the timeout expires.
///
/// \param event Pointer to event object.
///
/// \param bits Mask of bits to test.
///
/// \param to_cycles Timeout in cycles. Convert from time to cycles
/// using the helper functions provided in xos_timer.
/// A value of zero indicates no timeout.
///
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else
/// error code.
///
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
/// ignored, and no timeout will occur.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_wait_any_timeout(XosEvent * event, uint32_t bits, uint64_t to_cycles);
//-----------------------------------------------------------------------------
///
/// Atomically set a specified group of bits, then wait for another specified
/// group of bits to become set.
///
/// \param event Pointer to event object.
///
/// \param set_bits Group of bits to set.
///
/// \param wait_bits Group of bits to wait on. All the bits in the
/// group will have to get set before the wait is
/// satisfied.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_event_set_and_wait(XosEvent * event, uint32_t set_bits, uint32_t wait_bits);
#ifdef __cplusplus
}
#endif
#endif // __XOS_EVENT_H__

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// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __XOS_INTERNAL_H__
#define __XOS_INTERNAL_H__
#if !defined(__XOS_H__) || !defined(_XOS_INCLUDE_INTERNAL_)
#error "xos_internal.h must be included by defining _XOS_INCLUDE_INTERNAL_ before including xos.h"
#endif
#include <xtensa/config/core.h>
#include "xos_common.h"
#ifdef __cplusplus
extern "C" {
#endif
// Use this macro to suppress compiler warnings for unused variables.
#define UNUSED(x) (void)(x)
#if XOS_DEBUG
#include <stdio.h>
#include <xtensa/xtutil.h>
# define DPRINTF printf
#else
# define DPRINTF(x...) do {} while(0)
#endif
//-----------------------------------------------------------------------------
// Internal flags for thread creation.
//-----------------------------------------------------------------------------
#define XOS_THREAD_FAKE 0x8000 // Don't allocate stack (init and idle threads).
//-----------------------------------------------------------------------------
// Interrupt handler table entry. This structure defines one entry in the XOS
// interrupt handler table.
//-----------------------------------------------------------------------------
typedef struct XosIntEntry {
XosIntFunc * handler; // Pointer to handler function.
void * arg; // Argument passed to handler function.
#if XOS_OPT_INTERRUPT_SWPRI
unsigned char level; // Interrupt level.
unsigned char priority; // Interrupt priority.
short reserved; // Reserved.
unsigned int primask; // Mask of interrupts at higher priority.
#else
unsigned int ps; // Value of PS when running the handler.
#endif
} XosIntEntry;
//-----------------------------------------------------------------------------
// Extern variables.
//-----------------------------------------------------------------------------
extern unsigned xos_intlevel_mask;
extern unsigned xos_intenable_mask;
extern XosIntEntry xos_interrupt_table[XCHAL_NUM_INTERRUPTS];
extern uint32_t xos_clock_freq;
extern uint32_t xos_tick_period;
extern uint64_t xos_system_ticks;
extern uint64_t xos_system_cycles;
extern uint32_t xos_num_ctx_switches;
/*
One thing I noticed is different between my initial idea of stack
assignments to RTC threads, when comparing to interrupts, is that I
expected each RTC thread priority to have its own stack, whereas
interrupts of different priorities share an interrupt stack.
It's not really a difference in memory usage, because when assigning
multiple priorities to a stack, you have to add-up worst-case for
all priorities. One possible functional difference is that with
separate stacks per priority, it's possible to dynamically change
the priority of an RTC thread (while it's running). Not sure how
valuable that might be -- changing priority is useful with priority
inheritance, to avoid priority inversion, but I don't know how often
an RTC thread might acquire a lock (it couldn't block on acquiring a
lock in the usual sense -- it could get queued waiting and be restarted
when it becomes available, or use try_lock instead of lock).
*/
#ifdef __cplusplus
}
#endif
#endif /* __XOS_INTERNAL_H__ */

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/** @file */
// xos_msgq.h - XOS Message Queue API and data structures.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_MSGQ_H__
#define __XOS_MSGQ_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// XosMsgQueue is a multi-writer multi-reader message queue implementation.
// It is completely thread-safe and can be used by interrupt handlers.
// Interrupt handlers are guaranteed not to block when trying to send or
// receive a message. Messages are copied into the queue. The queue contains
// storage for a fixed number of messages defined at queue creation time.
// Messages must be a multiple of 4 bytes long (padded if necessary) and the
// message buffers must be 4-byte aligned.
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Message Queue flags.
//-----------------------------------------------------------------------------
#define XOS_MSGQ_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default)
#define XOS_MSGQ_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order
#define XOS_MSGQ_FULL 0x0002 // Queue is full
#define XOS_MSGQ_DELETED 0x8000 // Queue is deleted
//-----------------------------------------------------------------------------
///
/// XosMsgQueue object.
///
//-----------------------------------------------------------------------------
typedef struct XosMsgQueue {
uint16_t flags; ///< queue flags
uint16_t count; ///< # of messages queue can hold
uint32_t msize; ///< message size in bytes
uint16_t head; ///< write pointer
uint16_t tail; ///< read pointer
XosThreadQueue readq; ///< reader wait queue
XosThreadQueue writeq; ///< writer wait queue
#if XOS_MSGQ_DEBUG
uint32_t sig; // debug signature
#endif
#if XOS_OPT_MSGQ_STATS
uint32_t num_send; ///< # of messages put to queue
uint32_t num_recv; ///< # of messages taken from queue
uint32_t num_send_blks; ///< # of times thread blocked on send
uint32_t num_recv_blks; ///< # of times thread blocked on recv
#endif
uint32_t msg[1]; ///< first word of message buffer
} XosMsgQueue;
//-----------------------------------------------------------------------------
///
/// Use these macros to statically or dynamically allocate a message queue.
/// XOS_MSGQ_ALLOC allocates a static queue, while XOS_MSGQ_SIZE can be used
/// to allocate memory via malloc() etc.
///
/// Static: this allocates a queue named "testq", containing 10 messages,
/// each 16 bytes long.
///
/// XOS_MSGQ_ALLOC(testq, 10, 16);
///
/// Dynamic: this allocates a queue named "testq", containing 10 messages,
/// each 16 bytes long.
///
/// XosMsgQueue * testq = malloc( XOS_MSGQ_SIZE(10, 16) );
///
/// \param name The queue name, i.e. the name of the pointer
/// to the queue. Used as the queue handle in
/// queue API calls.
///
/// \param num Number of messages to allocate in queue. Must be > 0.
///
/// \param size Message size in bytes. Must be > 0 and multiple of 4.
///
//-----------------------------------------------------------------------------
#define XOS_MSGQ_ALLOC(name, num, size) \
static uint8_t name ## _buf[ sizeof(XosMsgQueue) + ((num) * (size)) ]; \
XosMsgQueue * name = (XosMsgQueue *) name ## _buf;
#define XOS_MSGQ_SIZE(num, size) \
(sizeof(XosMsgQueue) + ((num) * (size)))
//-----------------------------------------------------------------------------
///
/// Create the message queue object. Memory for the queue must be allocated by
/// the caller, either statically or via dynamic allocation. See the macros
/// XOS_MSGQ_ALLOC and XOS_MSGQ_SIZE for examples.
///
/// \param msgq Handle (pointer) to message queue.
///
/// \param num Number of messages allocated in queue. Must be > 0.
///
/// \param size Message size in bytes. Must be > 0 and multiple of 4.
///
/// \param flags Queue flags:
/// - XOS_MSGQ_WAIT_FIFO - blocked threads will be
/// woken in FIFO order.
/// - XOS_MSGQ_WAIT_PRIORITY - blocked threads will
/// be woken in priority order (default).
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_create(XosMsgQueue * msgq, uint16_t num, uint32_t size, uint16_t flags);
//-----------------------------------------------------------------------------
///
/// Destroys the specified queue. Any waiting threads are unblocked with an
/// error return. Any messages in the queue will be lost.
///
/// \param msgq Pointer to message queue.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_delete(XosMsgQueue * msgq);
//-----------------------------------------------------------------------------
///
/// Put a message into the queue. The message contents are copied into the next
/// available message slot. If no space is available, this function will block
/// if called from a thread, but will return immediately if called from an
/// interrupt handler.
///
/// \param msgq Pointer to message queue.
///
/// \param msg Pointer to message buffer.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_put(XosMsgQueue * msgq, const uint32_t * msg);
//-----------------------------------------------------------------------------
///
/// Put a message into the queue. The message contents are copied into the next
/// available message slot. If no space is available, this function will block
/// if called from a thread, but will return immediately if called from an
/// interrupt handler. The thread will be unblocked when space frees up in the
/// queue or the timeout expires.
///
/// \param msgq Pointer to message queue.
///
/// \param msg Pointer to message buffer.
///
/// \param to_cycles Timeout in cycles. Convert from time to cycles
/// using the helper functions provided in xos_timer.
/// A value of zero indicates no timeout.
///
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
///
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
/// ignored, and no timeout will occur.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_put_timeout(XosMsgQueue * msgq, const uint32_t * msg, uint64_t to_cycles);
//-----------------------------------------------------------------------------
///
/// Get a message from the queue. The message contents are copied into the
/// buffer that must be provided. If no message is available, this function
/// will block if called from a thread, but will return immediately if called
/// from an interrupt handler.
///
/// \param msgq Pointer to message queue.
///
/// \param msg Pointer to message buffer.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_get(XosMsgQueue * msgq, uint32_t * msg);
//-----------------------------------------------------------------------------
///
/// Get a message from the queue. The message contents are copied into the
/// buffer that must be provided. If no message is available, this function
/// will block if called from a thread, but will return immediately if called
/// from an interrupt handler. The thread will be unblocked when a message
/// arrives in the queue or the timeout expires.
///
/// \param msgq Pointer to message queue.
///
/// \param msg Pointer to message buffer.
///
/// \param to_cycles Timeout in cycles. Convert from time to cycles
/// using the helper functions provided in xos_timer.
/// A value of zero indicates no timeout.
///
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
///
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
/// ignored, and no timeout will occur.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_get_timeout(XosMsgQueue * msgq, uint32_t * msg, uint64_t to_cycles);
//-----------------------------------------------------------------------------
///
/// Check if the queue is empty.
///
/// \param msgq Pointer to message queue.
///
/// \return Returns nonzero if queue is empty, zero if queue is not empty.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_empty(XosMsgQueue * msgq);
//-----------------------------------------------------------------------------
///
/// Check if the queue is full.
///
/// \param msgq Pointer to message queue.
///
/// \return Returns nonzero if queue is full, zero if queue is not full.
///
//-----------------------------------------------------------------------------
int32_t
xos_msgq_full(XosMsgQueue * msgq);
#ifdef __cplusplus
}
#endif
#endif // __XOS_MSGQ_H__

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/** @file */
// xos_mutex.h - XOS Mutex API interface and data structures.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_MUTEX_H__
#define __XOS_MUTEX_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// Mutex flags.
//-----------------------------------------------------------------------------
#define XOS_MUTEX_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default)
#define XOS_MUTEX_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order
#define XOS_MUTEX_PRIORITY_CLG 0x0004 // Use priority ceiling
#define XOS_MUTEX_PRIORITY_INV 0x0008 // Protect against priority inversion
//-----------------------------------------------------------------------------
///
/// XosMutex object.
///
//-----------------------------------------------------------------------------
typedef struct XosMutex {
XosThread * owner; ///< Owning thread (null if unlocked).
XosThreadQueue waitq; ///< Queue of waiters.
uint32_t flags; ///< Properties.
uint32_t priority;
int32_t lock_count; ///< For recursive locking.
#if XOS_MUTEX_DEBUG
uint32_t sig; // Valid signature indicates inited.
#endif
} XosMutex;
//-----------------------------------------------------------------------------
///
/// Initialize a mutex object before first use.
///
/// \param mutex Pointer to mutex object.
///
/// \param flags Creation flags:
/// - XOS_MUTEX_WAIT_FIFO -- Queue waiting threads
/// in fifo order.
/// - XOS_MUTEX_WAIT_PRIORITY -- Queue waiting threads
/// by priority. This is the default.
/// - XOS_MUTEX_PRIORITY_CLG -- Use specified priority
/// value as the mutex's priority ceiling. If the
/// owning thread has a priority lower than the mutex's
/// priority, then the thread will have its priority
/// raised to the higher value as long as it owns the
/// mutex.
/// - XOS_MUTEX_PRIORITY_INV -- Protect against priority
/// inversion. If there is a waiting thread with a
/// higher priority than the current owner thread,
/// then the owner thread's priority is raised to the
/// higher value for as long as it owns the mutex.
///
/// \param priority Mutex's priority ceiling. This is used only if the
/// XOS_MUTEX_PRIORITY_CLG flag is set.
///
/// \return Returns XOS_OK on success, else error code.
///
/// NOTE: XOS_MUTEX_PRIORITY_CLG and XOS_MUTEX_PRIORITY_INV are NOT supported
/// in the current release. They will be supported in a future release.
///
//-----------------------------------------------------------------------------
int32_t
xos_mutex_create(XosMutex * mutex, uint32_t flags, uint8_t priority);
//-----------------------------------------------------------------------------
///
/// Destroy a mutex object. Must have been previously initialized by calling
/// xos_mutex_create().
///
/// \param mutex Pointer to mutex object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_mutex_delete(XosMutex * mutex);
//-----------------------------------------------------------------------------
///
/// Take ownership of the mutex: block until the mutex is owned.
/// The mutex must have been initialized.
///
/// \param mutex Pointer to mutex object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_mutex_lock(XosMutex * mutex);
//-----------------------------------------------------------------------------
///
/// Take ownership of the mutex: block until the mutex is owned or the timeout
/// expires. The mutex must have been initialized.
///
/// \param mutex Pointer to mutex object.
///
/// \param to_cycles Timeout in cycles. Convert from time to cycles
/// using the helper functions provided in xos_timer.
/// A value of zero indicates no timeout.
///
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
///
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
/// ignored, and no timeout will occur.
///
//-----------------------------------------------------------------------------
int32_t
xos_mutex_lock_timeout(XosMutex * mutex, uint64_t to_cycles);
//-----------------------------------------------------------------------------
///
/// Release ownership of the mutex. The mutex must have been initialized and
/// must be owned by the calling thread.
///
/// \param mutex Pointer to mutex object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_mutex_unlock(XosMutex * mutex);
//-----------------------------------------------------------------------------
///
/// Try to take ownership of the mutex, but do not block if the mutex is taken.
/// Return immediately. The mutex must have been initialized.
///
/// \param mutex Pointer to mutex object.
///
/// \return Returns XOS_OK on success (mutex owned), else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_mutex_trylock(XosMutex * mutex);
//-----------------------------------------------------------------------------
///
/// Return the state of the mutex (locked or unlocked) but do not attempt to
/// take ownership. The mutex must have been initialized.
///
/// \param mutex Pointer to mutex object.
///
/// \return Returns 0 if the mutex is unlocked, 1 if it is locked, -1 on error.
///
//-----------------------------------------------------------------------------
static inline int32_t
xos_mutex_test(XosMutex * mutex)
{
XOS_ASSERT(mutex);
if (mutex != XOS_NULL) {
return (mutex->owner != XOS_NULL) ? 1 : 0;
}
return -1;
}
#ifdef __cplusplus
}
#endif
#endif // __XOS_MUTEX_H__

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/** @file */
// xos_params.h - user-settable compile time parameters for XOS.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __XOS_PARAMS_H__
#define __XOS_PARAMS_H__
#include <xtensa/config/core.h>
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
///
/// Number of thread priority levels. At this time XOS supports a maximum of
/// 32 priority levels (0 - 31).
///
//-----------------------------------------------------------------------------
#ifndef XOS_NUM_PRIORITY
#define XOS_NUM_PRIORITY 16 // Default is 16
#endif
//-----------------------------------------------------------------------------
///
/// Debug flags - Set to 1 to enable debug mode (and more verbose operation).
/// Can be set individually, or define XOS_DEBUG_ALL to enable all of them.
///
/// - XOS_DEBUG -- Generic OS debug
/// - XOS_COND_DEBUG -- Condition objects debug
/// - XOS_EVENT_DEBUG -- Event objects debug
/// - XOS_MSGQ_DEBUG -- Message queue debug
/// - XOS_MUTEX_DEBUG -- Mutex objects debug
/// - XOS_SEM_DEBUG -- Semaphore objects debug
/// - XOS_THREAD_DEBUG -- Thread module debug
/// - XOS_TIMER_DEBUG -- Timer module debug
///
/// WARNING: Enabling one or more of these flags will affect system performance
/// and timing.
///
/// NOTE: Not all of these have been fully implemented.
///
//-----------------------------------------------------------------------------
#if defined XOS_DEBUG_ALL
#define XOS_DEBUG 1
#define XOS_THREAD_DEBUG 1
#define XOS_TIMER_DEBUG 1
#define XOS_COND_DEBUG 1
#define XOS_MUTEX_DEBUG 1
#define XOS_SEM_DEBUG 1
#define XOS_EVENT_DEBUG 1
#define XOS_MSGQ_DEBUG 1
#else
#ifndef XOS_DEBUG
#define XOS_DEBUG 0
#endif
#ifndef XOS_THREAD_DEBUG
#define XOS_THREAD_DEBUG 0
#endif
#ifndef XOS_TIMER_DEBUG
#define XOS_TIMER_DEBUG 0
#endif
#ifndef XOS_COND_DEBUG
#define XOS_COND_DEBUG 0
#endif
#ifndef XOS_MUTEX_DEBUG
#define XOS_MUTEX_DEBUG 0
#endif
#ifndef XOS_SEM_DEBUG
#define XOS_SEM_DEBUG 0
#endif
#ifndef XOS_EVENT_DEBUG
#define XOS_EVENT_DEBUG 0
#endif
#ifndef XOS_MSGQ_DEBUG
#define XOS_MSGQ_DEBUG 0
#endif
#endif
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to enable runtime statistics collection for XOS.
/// NOTE: Enabling this option does have some impact on runtime performance
/// and OS footprint.
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_STATS
#define XOS_OPT_STATS 1
#endif
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to enable statistics tracking for message queues.
/// enabling this will cause message queue objects to increase in size, and add
/// some overhead to message queue processing.
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_MSGQ_STATS
#define XOS_OPT_MSGQ_STATS 0
#endif
//-----------------------------------------------------------------------------
///
/// Size of interrupt stack in bytes. Shared by all interrupt handlers. Must be
/// sized to handle worst case nested interrupts. This is also used by the idle
/// thread so must exist even if interrupts are not configured.
///
//-----------------------------------------------------------------------------
#ifndef XOS_INT_STACK_SIZE
#if XCHAL_HAVE_INTERRUPTS
#define XOS_INT_STACK_SIZE 8192
#else
#define XOS_INT_STACK_SIZE 32
#endif
#endif
//-----------------------------------------------------------------------------
///
/// Default maximum interrupt level at which XOS primitives may be called.
/// It is the level at which interrupts are disabled by default.
/// See also description of xos_set_int_pri_level().
///
//-----------------------------------------------------------------------------
#ifndef XOS_MAX_OS_INTLEVEL
#define XOS_MAX_OS_INTLEVEL XCHAL_EXCM_LEVEL
#endif
//-----------------------------------------------------------------------------
///
/// Set this to 1 to enable stack checking. The stack is filled with a pattern
/// on thread creation, and the stack is checked at certain times during system
/// operation.
/// WARNING: Enabling this option can have some impact on runtime performance.
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_STACK_CHECK
#if XOS_DEBUG
#define XOS_OPT_STACK_CHECK 1
#else
#define XOS_OPT_STACK_CHECK 0
#endif
#endif
//-----------------------------------------------------------------------------
///
/// Set XOS_CLOCK_FREQ to the system clock frequency if this is known ahead of
/// time. Otherwise, call xos_set_clock_freq() to set it at run time.
///
//-----------------------------------------------------------------------------
#ifndef XOS_CLOCK_FREQ
#define XOS_CLOCK_FREQ 1000000
#endif
#define XOS_DEFAULT_CLOCK_FREQ XOS_CLOCK_FREQ
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to enable software prioritization of interrupts. The
/// priority scheme applied is that a higher interrupt number at the same level
/// will have higher priority.
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_INTERRUPT_SWPRI
#define XOS_OPT_INTERRUPT_SWPRI 1
#endif
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to use the thread-safe version of the C runtime library.
/// You may need to enable this if you call C library functions from multiple
/// threads -- see the documentation for the relevant C library to determine if
/// this is necessary. This option increases the size of the TCB.
/// NOTE: At this time only the newlib and xclib libraries are supported for
/// thread safety.
///
//-----------------------------------------------------------------------------
#include <xtensa/config/system.h>
#ifndef XOS_OPT_THREAD_SAFE_CLIB
#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
#define XOS_OPT_THREAD_SAFE_CLIB 1
#elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
#define XOS_OPT_THREAD_SAFE_CLIB 1
#else
#define XOS_OPT_THREAD_SAFE_CLIB 0
#endif
#endif
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to enable the wait timeout feature. This allows waits
/// on waitable objects to expire after a specified timeout.
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_WAIT_TIMEOUT
#define XOS_OPT_WAIT_TIMEOUT 1
#endif
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to enable threads waiting on timer objects. If this
/// feature is not used, turning it off will make timer objects smaller, and
/// reduce the time taken by timer expiry processing (by a small amount).
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_TIMER_WAIT
#define XOS_OPT_TIMER_WAIT 1
#endif
//-----------------------------------------------------------------------------
///
/// Set this option to 1 to enable time-slicing between multiple threads at the
/// same priority. If this option is enabled then on every timer tick the timer
/// handler will switch out the current thread if there is another ready thread
/// at the same priority, and allow the latter thread to run. Execution will be
/// round robin switched among all the threads at the same priority.
///
/// Currently the time slice interval is fixed to be one timer tick.
///
/// This feature is most useful if fixed duration timer ticks are used.
/// If dynamic ticking is enabled, then time slicing will work unpredictably
/// because the interval between ticks will vary. In some cases it may be
/// better to turn time slicing off.
///
//-----------------------------------------------------------------------------
#ifndef XOS_OPT_TIME_SLICE
#define XOS_OPT_TIME_SLICE 1
#endif
#ifdef __cplusplus
}
#endif
#endif // __XOS_PARAMS_H__

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// xos_regaccess.h - Access routines for various processor special registers.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __REGACCESS_H__
#define __REGACCESS_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "xos_types.h"
#include <xtensa/config/core.h>
#if defined (__XCC__)
#if XCHAL_HAVE_CCOUNT
#include <xtensa/tie/xt_timer.h>
#endif
#endif
//-----------------------------------------------------------------------------
// Read CCOUNT register.
//-----------------------------------------------------------------------------
static __inline__ uint32_t xos_get_ccount(void)
{
#if XCHAL_HAVE_CCOUNT
#if defined (__XCC__)
return XT_RSR_CCOUNT();
#else
uint32_t ccount;
__asm__ __volatile__ ( "rsr %0, ccount" : "=a" (ccount) );
return ccount;
#endif
#else
return 0;
#endif
}
//-----------------------------------------------------------------------------
// Read CCOMPARE0
//-----------------------------------------------------------------------------
static __inline__ uint32_t xos_get_ccompare0(void)
{
#if XCHAL_HAVE_CCOUNT
#if defined (__XCC__)
return XT_RSR_CCOMPARE0();
#else
uint32_t ccompare0;
__asm__ __volatile__ ( "rsr %0, ccompare0" : "=a" (ccompare0));
return ccompare0;
#endif
#else
return 0;
#endif
}
//-----------------------------------------------------------------------------
// Read CCOMPARE1
//-----------------------------------------------------------------------------
#if (XCHAL_NUM_TIMERS > 1)
static __inline__ uint32_t xos_get_ccompare1(void)
{
#if defined (__XCC__)
return XT_RSR_CCOMPARE1();
#else
uint32_t ccompare1;
__asm__ __volatile__ ( "rsr %0, ccompare1" : "=a" (ccompare1));
return ccompare1;
#endif
}
#endif
//-----------------------------------------------------------------------------
// Read CCOMPARE2
//-----------------------------------------------------------------------------
#if (XCHAL_NUM_TIMERS > 2)
static __inline__ uint32_t xos_get_ccompare2(void)
{
#if defined (__XCC__)
return XT_RSR_CCOMPARE2();
#else
uint32_t ccompare2;
__asm__ __volatile__ ( "rsr %0, ccompare2" : "=a" (ccompare2));
return ccompare2;
#endif
}
#endif
//-----------------------------------------------------------------------------
// Write CCOMPARE0
//-----------------------------------------------------------------------------
static __inline__ void xos_set_ccompare0(uint32_t val)
{
#if XCHAL_HAVE_CCOUNT
#if defined (__XCC__)
XT_WSR_CCOMPARE0(val);
XT_ISYNC();
#else
__asm__ __volatile__ (
"wsr %0, ccompare0\n"
"isync"
:
: "a" (val)
);
#endif
#else
// Empty
#endif
}
//-----------------------------------------------------------------------------
// Write CCOMPARE1
//-----------------------------------------------------------------------------
#if (XCHAL_NUM_TIMERS > 1)
static __inline__ void xos_set_ccompare1(uint32_t val)
{
#if defined (__XCC__)
XT_WSR_CCOMPARE1(val);
XT_ISYNC();
#else
__asm__ __volatile__ (
"wsr %0, ccompare1\n"
"isync"
:
: "a" (val)
);
#endif
}
#endif
//-----------------------------------------------------------------------------
// Write CCOMPARE2
//-----------------------------------------------------------------------------
#if (XCHAL_NUM_TIMERS > 2)
static __inline__ void xos_set_ccompare2(uint32_t val)
{
#if defined (__XCC__)
XT_WSR_CCOMPARE2(val);
XT_ISYNC();
#else
__asm__ __volatile__ (
"wsr %0, ccompare2\n"
"isync"
:
: "a" (val)
);
#endif
}
#endif
#ifdef __cplusplus
}
#endif
#endif // __REGACCESS_H__

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components/esp32/include/xtensa/xos_semaphore.h
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@@ -1,190 +0,0 @@
/** @file */
// xos_semaphore.h - XOS Semaphore API interface and data structures.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_SEMAPHORE_H__
#define __XOS_SEMAPHORE_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// Semaphore flags.
//-----------------------------------------------------------------------------
#define XOS_SEM_WAIT_PRIORITY 0x0000 ///< Wake waiters in priority order (default)
#define XOS_SEM_WAIT_FIFO 0x0001 ///< Wake waiters in FIFO order
#define XOS_SEM_PRIORITY_INV 0x0004 // Protect against priority inversion
//-----------------------------------------------------------------------------
///
/// XosSem object.
///
//-----------------------------------------------------------------------------
typedef struct XosSem {
uint32_t count; ///< Current count
XosThreadQueue waitq; ///< Queue of waiters.
uint32_t flags; ///< Properties.
#if XOS_SEM_DEBUG
uint32_t sig; // Valid signature indicates inited.
#endif
} XosSem;
//-----------------------------------------------------------------------------
///
/// Initialize a semaphore object before first use.
///
/// \param sem Pointer to semaphore object.
///
/// \param flags Creation flags:
/// - XOS_SEM_WAIT_FIFO -- queue waiting threads in
/// fifo order.
/// - XOS_SEM_WAIT_PRIORITY -- queue waiting threads
/// by priority. This is the default.
/// - XOS_SEM_PRIORITY_INV -- protect against priority
/// inversion.
///
/// \param initial_count Initial count for semaphore on creation.
///
/// \return Returns XOS_OK on success, else error code.
///
/// NOTE: XOS_SEM_PRIORITY_INV is NOT supported in the current release. It will
/// be supported in a future release.
///
//-----------------------------------------------------------------------------
int32_t
xos_sem_create(XosSem * sem, uint32_t flags, uint32_t initial_count);
//-----------------------------------------------------------------------------
///
/// Destroy a semaphore object. Must have been previously created by calling
/// xos_sem_create().
///
/// \param sem Pointer to semaphore object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_sem_delete(XosSem * sem);
//-----------------------------------------------------------------------------
///
/// Decrement the semaphore count: block until the decrement is possible.
/// The semaphore must have been initialized.
///
/// \param sem Pointer to semaphore object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_sem_get(XosSem * sem);
//-----------------------------------------------------------------------------
///
/// Decrement the semaphore count: block until the decrement is possible or
/// the timeout expires. The semaphore must have been initialized.
///
/// \param sem Pointer to semaphore object.
///
/// \param to_cycles Timeout in cycles. Convert from time to cycles
/// using the helper functions provided in xos_timer.
/// A value of zero indicates no timeout.
///
/// \return Returns XOS_OK on success, XOS_ERR_TIMEOUT on timeout, else error code.
///
/// NOTE: If XOS_OPT_WAIT_TIMEOUT is not enabled, then the timeout value is
/// ignored, and no timeout will occur.
///
//-----------------------------------------------------------------------------
int32_t
xos_sem_get_timeout(XosSem * sem, uint64_t to_cycles);
//-----------------------------------------------------------------------------
///
/// Increment the semaphore count. The semaphore must have been initialized.
/// Remember that this action may wake up a waiting thread, and if that thread
/// is higher priority then there will be an immediate context switch.
///
/// \param sem Pointer to semaphore object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_sem_put(XosSem * sem);
//-----------------------------------------------------------------------------
///
/// Try to decrement the semaphore, but do not block if the semaphore count is
/// zero. Return immediately. The semaphore must have been initialized.
///
/// \param sem Pointer to semaphore object.
///
/// \return Returns XOS_OK on success (semaphore decremented), else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_sem_tryget(XosSem * sem);
//-----------------------------------------------------------------------------
///
/// Return the count of the semaphore but do not attempt to decrement it.
/// The semaphore must have been initialized.
///
/// \param sem Pointer to semaphore object.
///
/// \return Returns semaphore count, -1 on error.
///
//-----------------------------------------------------------------------------
static inline int32_t
xos_sem_test(XosSem * sem)
{
XOS_ASSERT(sem);
return sem ? sem->count : -1;
}
#ifdef __cplusplus
}
#endif
#endif // __XOS_SEMAPHORE_H__

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components/esp32/include/xtensa/xos_stopwatch.h
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/** @file */
// xos_stopwatch.h - XOS Stopwatch objects and related API.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_STOPWATCH_H__
#define __XOS_STOPWATCH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "xos_types.h"
#include "xos_params.h"
//-----------------------------------------------------------------------------
// A stopwatch object can be used to track elapsed time and accumulate total
// elapsed time over multiple execution periods. The stopwatch records the
// time whenever its start function is called, and stops recording the time
// when the stop function is called and updates its cumulative time counter.
// The stopwatch keeps time in cycles. This can be converted to seconds etc.
// by using the XOS conversion calls such as xos_cycles_to_secs().
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
///
/// XosStopwatch object.
///
//-----------------------------------------------------------------------------
typedef struct XosStopwatch {
uint64_t total; ///< Total accumulated cycle count
uint64_t start; ///< Starting system cycle count
uint16_t active; ///< Active flag (nonzero when active)
} XosStopwatch;
//-----------------------------------------------------------------------------
///
/// Initialize a stopwatch object.
///
/// \param sw Pointer to a stopwatch object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
static inline void
xos_stopwatch_init(XosStopwatch * sw)
{
sw->total = 0;
sw->start = 0;
sw->active = 0;
}
//-----------------------------------------------------------------------------
///
/// Start a stopwatch. Starts cycle counting.
/// Note that this does not necessarily start counting from zero. The current
/// run (start-to-stop interval) will just get added to the accumulated count
/// in the stopwatch if any.
/// To reset the accumulated count, use xos_stopwatch_clear().
///
/// \param sw Pointer to a stopwatch object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
static inline void
xos_stopwatch_start(XosStopwatch * sw)
{
XOS_ASSERT(!sw->active);
sw->active = 1;
sw->start = xos_get_system_cycles();
}
//-----------------------------------------------------------------------------
///
/// Stop a stopwatch. Stops cycle counting and updates total.
///
/// \param sw Pointer to a stopwatch object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
static inline void
xos_stopwatch_stop(XosStopwatch * sw)
{
XOS_ASSERT(sw->active);
sw->active = 0;
sw->total += xos_get_system_cycles() - sw->start;
}
//-----------------------------------------------------------------------------
///
/// Get stopwatch accumulated count.
///
/// \param sw Pointer to a stopwatch object.
///
/// \return Returns the accumulated count.
///
//-----------------------------------------------------------------------------
static inline uint64_t
xos_stopwatch_count(XosStopwatch * sw)
{
return sw->total;
}
//-----------------------------------------------------------------------------
///
/// Get elapsed time since stopwatch was started. If not started, returns zero.
///
/// \param sw Pointer to a stopwatch object.
///
/// \return Returns elapsed time in cycles.
///
//-----------------------------------------------------------------------------
static inline uint64_t
xos_stopwatch_elapsed(XosStopwatch * sw)
{
return sw->active ? xos_get_system_cycles() - sw->start : 0;
}
//-----------------------------------------------------------------------------
///
/// Clears a stopwatch. Resets the accumulated count to zero, and deactivates
/// it if active.
///
/// \param sw Pointer to a stopwatch object.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
static inline void
xos_stopwatch_clear(XosStopwatch * sw)
{
xos_stopwatch_init(sw);
}
#ifdef __cplusplus
}
#endif
#endif // __XOS_STOPWATCH_H__

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components/esp32/include/xtensa/xos_syslog.h
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/** @file */
// xos_syslog.h - XOS Event logging module.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_SYSLOG_H__
#define __XOS_SYSLOG_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
// The XOS system log is an array of fixed size entries. The size of the log
// is determined by the application, and memory for the log must be provided
// at init time. Every time the log function is called, an entry is made in
// the log and the next pointer advanced. When the log is full, it will wrap
// around and start overwriting the oldest entries.
// Logging can be done from C/C++ code as well as assembly code, and at any
// interrupt level, even from high level interrupt handlers.
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Defines.
//-----------------------------------------------------------------------------
#define XOS_SYSLOG_ENABLED 0x0001
///----------------------------------------------------------------------------
///
/// Use this macro to compute how much memory to allocate for the syslog.
///
///----------------------------------------------------------------------------
#define XOS_SYSLOG_SIZE(num_entries) \
( sizeof(XosSysLog) + ((num_entries - 1) * sizeof(XosSysLogEntry)) )
///----------------------------------------------------------------------------
///
/// System log entry structure.
///
///----------------------------------------------------------------------------
typedef struct XosSysLogEntry {
uint32_t timestamp; ///< Timestamp in clock cycles
uint32_t param1; ///< User defined value
uint32_t param2; ///< User defined value
struct XosSysLogEntry * next; ///< Link to next entry
} XosSysLogEntry;
///----------------------------------------------------------------------------
///
/// System log structure.
///
///----------------------------------------------------------------------------
typedef struct XosSysLog {
uint16_t flags; ///< Flags
uint16_t size; ///< Number of entries
XosSysLogEntry * next; ///< Next write position
XosSysLogEntry entries[1]; ///< First entry
} XosSysLog;
//-----------------------------------------------------------------------------
// Pointer to syslog area.
//-----------------------------------------------------------------------------
extern XosSysLog * xos_syslog;
//----------------------------------------------------------------------------
///
/// Initialize the syslog. Initializing the log also enables it. The system
/// log always wraps around when full and overwrites the oldest entries.
///
/// \param log_mem Pointer to allocated memory for the log.
///
/// \param num_entries The number of entries that the log can contain.
///
/// \return Returns nothing.
///
//----------------------------------------------------------------------------
static inline void
xos_syslog_init(void * log_mem, uint16_t num_entries)
{
uint16_t i;
xos_syslog = (XosSysLog *) log_mem;
xos_syslog->size = num_entries;
xos_syslog->next = xos_syslog->entries;
for (i = 0; i < num_entries - 1; i++) {
xos_syslog->entries[i].next = &(xos_syslog->entries[i+1]);
xos_syslog->entries[i].timestamp = 0;
}
xos_syslog->entries[i].next = xos_syslog->entries;
xos_syslog->entries[i].timestamp = 0;
xos_syslog->flags = XOS_SYSLOG_ENABLED;
}
///----------------------------------------------------------------------------
///
/// Reset the syslog. All entries made up to now are abandoned and the write
/// pointer is set to the first entry location.
///
/// No parameters.
///
/// \return Returns nothing.
///
///----------------------------------------------------------------------------
static inline void
xos_syslog_clear()
{
#if XCHAL_HAVE_INTERRUPTS
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
#endif
xos_syslog_init(xos_syslog, xos_syslog->size);
#if XCHAL_HAVE_INTERRUPTS
xos_restore_int_pri_level(ps);
#endif
}
///----------------------------------------------------------------------------
///
/// Enable logging to the syslog. This function needs to be called only if
/// logging had been previously disabled via xos_syslog_disable(), since
/// initializing the syslog automatically enables it.
///
/// No parameters.
///
/// \return Returns nothing.
///
///----------------------------------------------------------------------------
static inline void
xos_syslog_enable()
{
#if XCHAL_HAVE_INTERRUPTS
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
#endif
xos_syslog->flags |= XOS_SYSLOG_ENABLED;
#if XCHAL_HAVE_INTERRUPTS
xos_restore_int_pri_level(ps);
#endif
}
///----------------------------------------------------------------------------
///
/// Disable logging to the syslog. It is sometimes useful to disable logging
/// while the log is being examined or dumped.
///
/// No parameters.
///
/// \return Returns nothing.
///
///----------------------------------------------------------------------------
static inline void
xos_syslog_disable()
{
#if XCHAL_HAVE_INTERRUPTS
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
#endif
xos_syslog->flags &= ~XOS_SYSLOG_ENABLED;
#if XCHAL_HAVE_INTERRUPTS
xos_restore_int_pri_level(ps);
#endif
}
///----------------------------------------------------------------------------
///
/// Write an entry into the syslog. This function does disable all interrupts
/// since logging can be done from interrupt handlers as well. It will write
/// into the log only if the log exists and is enabled.
///
/// \param param1 User defined value.
///
/// \param param2 User defined value.
///
/// \return Returns nothing.
///
///----------------------------------------------------------------------------
static inline void
xos_syslog_write(uint32_t param1, uint32_t param2)
{
if (xos_syslog != XOS_NULL) {
#if XCHAL_HAVE_INTERRUPTS
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
#endif
if ((xos_syslog->flags & XOS_SYSLOG_ENABLED) != 0) {
XosSysLogEntry * next = xos_syslog->next;
next->timestamp = xos_get_ccount();
next->param1 = param1;
next->param2 = param2;
xos_syslog->next = next->next;
}
#if XCHAL_HAVE_INTERRUPTS
xos_restore_int_pri_level(ps);
#endif
}
}
///----------------------------------------------------------------------------
///
/// Read the first (oldest) entry in the syslog. Will return an error if the
/// log has not been created or is empty. Storage to copy the entry must be
/// provided by the caller.
///
/// \param entry Pointer to storage where the entry data will be
/// copied. This pointer must be passed to
/// xos_syslog_get_next().
///
/// \return Returns XOS_OK on success, else error code.
///
///----------------------------------------------------------------------------
static inline int32_t
xos_syslog_get_first(XosSysLogEntry * entry)
{
if (xos_syslog == XOS_NULL) {
return XOS_ERR_NOT_FOUND;
}
if (entry != XOS_NULL) {
#if XCHAL_HAVE_INTERRUPTS
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
#endif
XosSysLogEntry * next = xos_syslog->next;
// 'next' should be pointing to the next entry to be overwritten, if we
// have wrapped. This means it is the oldest entry. However if this entry
// has a zero timestamp then we have not wrapped, in which case we must
// look at the first entry in the list.
if (next->timestamp == 0) {
next = xos_syslog->entries;
}
*entry = *next;
#if XCHAL_HAVE_INTERRUPTS
xos_restore_int_pri_level(ps);
#endif
return entry->timestamp ? XOS_OK : XOS_ERR_NOT_FOUND;
}
return XOS_ERR_INVALID_PARAMETER;
}
///----------------------------------------------------------------------------
///
/// Get the next sequential entry from the syslog. This function must be called
/// only after xos_syslog_get_first() has been called.
///
/// \param entry Pointer to storage where entry data will be copied.
/// Must be the same pointer that was passed in the call
/// to xos_syslog_get_first(), as it is used to keep track
/// of the current position.
///
/// \return Returns XOS_OK on success, else error code.
///
///----------------------------------------------------------------------------
static inline int32_t
xos_syslog_get_next(XosSysLogEntry * entry)
{
if (entry != XOS_NULL) {
#if XCHAL_HAVE_INTERRUPTS
uint32_t ps = XT_RSIL(XCHAL_NUM_INTLEVELS);
#endif
XosSysLogEntry * next = entry->next;
int32_t ret = XOS_OK;
// Make sure we're not pointing past the last entry.
if ((next != XOS_NULL) && (next != xos_syslog->next) && (next->timestamp != 0)) {
*entry = *next;
}
else {
ret = XOS_ERR_NOT_FOUND;
}
#if XCHAL_HAVE_INTERRUPTS
xos_restore_int_pri_level(ps);
#endif
return ret;
}
return XOS_ERR_INVALID_PARAMETER;
}
#ifdef __cplusplus
}
#endif
#endif // __XOS_SYSLOG_H__

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components/esp32/include/xtensa/xos_thread.h
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components/esp32/include/xtensa/xos_timer.h
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/** @file */
// xos_timer.h - XOS Timer API interface and data structures.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_TIMER_H__
#define __XOS_TIMER_H__
#include "xos_types.h"
#ifdef __cplusplus
extern "C" {
#endif
//-----------------------------------------------------------------------------
///
/// Function pointer type for timer callbacks.
///
//-----------------------------------------------------------------------------
typedef void (XosTimerFunc)(void * arg);
//-----------------------------------------------------------------------------
///
/// Timer event structure. Used to track pending timer events.
///
//-----------------------------------------------------------------------------
typedef struct XosTimer {
struct XosTimer * next; ///< Pointer to next event in list.
uint64_t when; ///< Time (clock cycles) at which to trigger.
uint64_t delta; ///< Delta for next re-trigger, 0 if none.
XosTimerFunc * fn; ///< Function to call when timer expires.
void * arg; ///< Argument to pass to called function.
bool active; ///< Set if active (in some list of events).
#if XOS_OPT_TIMER_WAIT
XosThreadQueue waitq; ///< Queue of threads waiting on this timer.
#endif
#if XOS_TIMER_DEBUG
uint32_t signature;
#endif
} XosTimer;
//-----------------------------------------------------------------------------
// Extern declarations.
//-----------------------------------------------------------------------------
// System clock frequency in cycles per second.
extern uint32_t xos_clock_freq;
///@{
//-----------------------------------------------------------------------------
// Functions to convert from clock cycles to time units and vice versa.
//
// Note that these are integer conversions so for example a cycle count of less
// than one second will convert to zero seconds.
//-----------------------------------------------------------------------------
/// Converts CPU cycles to time in seconds.
///
/// \param cycles Number of CPU cycles.
///
/// \return Equivalent number of seconds (truncated to integer).
static inline uint64_t
xos_cycles_to_secs(uint64_t cycles)
{
return cycles / xos_clock_freq;
}
/// Converts CPU cycles to time in milliseconds.
///
/// \param cycles Number of CPU cycles.
///
/// \return Equivalent number of milliseconds (truncated to integer).
static inline uint64_t
xos_cycles_to_msecs(uint64_t cycles)
{
return (cycles * 1000) / xos_clock_freq;
}
/// Converts CPU cycles to time in microseconds.
///
/// \param cycles Number of CPU cycles.
///
/// \return Equivalent number of microseconds (truncated to integer).
static inline uint64_t
xos_cycles_to_usecs(uint64_t cycles)
{
return (cycles * 1000000) / xos_clock_freq;
}
/// Converts time in seconds to CPU cycle count.
///
/// \param secs Number of seconds.
///
/// \return Equivalent number of CPU cycles.
static inline uint64_t
xos_secs_to_cycles(uint64_t secs)
{
return secs * xos_clock_freq;
}
/// Converts time in milliseconds to CPU cycle count.
///
/// \param msecs Number of milliseconds.
///
/// \return Equivalent number of CPU cycles.
static inline uint64_t
xos_msecs_to_cycles(uint64_t msecs)
{
return (msecs * xos_clock_freq) / 1000;
}
/// Converts time in microseconds to CPU cycle count.
///
/// \param usecs Number of microseconds.
///
/// \return Equivalent number of CPU cycles.
static inline uint64_t
xos_usecs_to_cycles(uint64_t usecs)
{
return (usecs * xos_clock_freq) / 1000000;
}
///@}
//-----------------------------------------------------------------------------
///
/// Set system clock frequency. This is expected to be set only once, and only
/// if the clock frequency is not known at compile time.
///
/// \param freq Frequency in cycles per second.
///
/// \return Returns nothing.
///
//-----------------------------------------------------------------------------
static inline void
xos_set_clock_freq(uint32_t freq)
{
xos_clock_freq = freq;
}
//-----------------------------------------------------------------------------
///
/// Get current system clock frequency.
///
/// \return Returns current system clock frequency in cycles per second.
///
//-----------------------------------------------------------------------------
static inline uint32_t
xos_get_clock_freq()
{
return xos_clock_freq;
}
//-----------------------------------------------------------------------------
///
/// Initialize timer support and start the system timer.
/// This function must be called before calling any other timer function.
///
/// NOTE: The smaller the tick period, the more precisely delays can be
/// specified using timers. However, we also need to make the tick period
/// large enough to allow time both to execute the tick timer interrupt handler
/// and for the application to make reasonable forward progress. If tick_period
/// is too small, the timer interrupt may re-trigger before the timer interrupt
/// handler has returned to the application, thus keeping the processor busy in
/// constantly executing the timer interrupt handler without leaving any cycles
/// for the application. Or, the application might get some cycles but only a
/// fraction of what is spent in the timer interrupt handler, thus severely
/// impacting application performance.
///
/// The exact number of cycles needed to execute the timer interrupt handler
/// is not specified here. It depends on many factors (e.g. use of caches,
/// various processor configuration options, etc) and can vary by orders of
/// magnitude. Also note that the time to execute this handler is variable:
/// when timers expire upon a given tick timer interrupt, their respective
/// timer handler functions are called from within the interrupt handler.
///
/// \param timer_num Which Xtensa timer to use (0..2). This timer
/// must exist and be configured at level 1 or at a
/// medium-priority interrupt level (<=EXCM_LEVEL).
/// If 'timer_num' is -1, then this function will
/// automatically choose the highest priority timer
/// that is suitable for use. This value will be
/// passed to xos_system_timer_select().
///
/// \param tick_period Number of clock (CCOUNT) cycles between ticks.
/// Must range between 0 and UINT32_MAX.
/// Zero is used to specify dynamic tick (tickless)
/// mode.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_start_system_timer(int32_t timer_num, uint32_t tick_period);
//-----------------------------------------------------------------------------
///
/// Get the timer number of the system timer. Useful mainly when XOS has been
/// allowed to choose its own timer via xos_start_system_timer(). Not valid if
/// called before the system timer has been started.
///
/// \return Returns one of XOS_SYS_TIMER_0, XOS_SYS_TIMER_1, XOS_SYS_TIMER_2
/// or XOS_SYS_TIMER_EXTERNAL, or XOS_SYS_TIMER_NONE.
///
//-----------------------------------------------------------------------------
int32_t
xos_get_system_timer_num(void);
//-----------------------------------------------------------------------------
///
/// Initialize timer object.
///
/// \param timer Pointer to timer event structure.
///
/// \return Returns nothing.
///
/// NOTE: This function should not be called on a timer object once it has
/// been activated.
///
//-----------------------------------------------------------------------------
void xos_timer_init(XosTimer * timer);
//-----------------------------------------------------------------------------
// Flags for xos_timer_start().
//-----------------------------------------------------------------------------
#define XOS_TIMER_DELTA 0x0000
#define XOS_TIMER_PERIODIC 0x0001
#define XOS_TIMER_ABSOLUTE 0x0002
#define XOS_TIMER_FROM_NOW 0x0000
#define XOS_TIMER_FROM_LAST 0x0010
//-----------------------------------------------------------------------------
///
/// Start the timer, and when the timer expires, call the specified function
/// (invoke (*fn)(arg)). If the timer is periodic, it will be automatically
/// restarted when it expires.
///
/// The specified timer event structure must have been initialized before
/// first use by calling xos_timer_init().
///
/// The callback function will be called in an interrupt context. Hence it is
/// NOT safe to use any coprocessors in the function, including the FPU. If a
/// coprocessor must be used, then its state must be saved and restored across
/// its use.
///
/// NOTE: If you are using the timer only to wait on (via xos_timer_wait())
/// then it is not necessary to specify a callback function. You should pass
/// NULL for the callback function and zero for the callback argument.
///
/// \param timer Pointer to timer event structure. Must have been
/// initialized. May be active or not.
///
/// \param when When to call the function (see flags).
///
/// \param flags Set of option flags XOS_TIMER_* \n
/// The following flags are mutually exclusive:
/// - XOS_TIMER_DELTA -- when is number of cycles from
/// [see below] (default)
/// - XOS_TIMER_PERIODIC -- when is number of cycles
/// from [see below], and timer continually
/// re-triggers at that interval
/// - XOS_TIMER_ABSOLUTE -- when is absolute value of
/// cycle count \n
/// \n
/// The following flags are mutually exclusive:
/// - XOS_TIMER_FROM_NOW -- *DELTA and *PERIODIC are
/// relative to now (default)
/// - XOS_TIMER_FROM_LAST -- *DELTA and *PERIODIC are
/// relative to the timer event's last specified expiry
/// time (usually in the future if active, in the past
/// if not, absolute 0 if was never activated).
///
/// \param func Function to call (called in timer interrupt context).
/// This argument is optional. Specify NULL if no function
/// is to be called.
///
/// \param arg Argument passed to callback function. Only relevant if
/// 'func' is not NULL.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_timer_start(XosTimer * timer,
uint64_t when,
uint32_t flags,
XosTimerFunc * func,
void * arg);
//-----------------------------------------------------------------------------
///
/// Stop the timer and remove it from the list of active timers. Has no effect
/// if the timer is not active. Any waiting threads are woken up.
///
/// The timer structure must have been initialized at least once, else its
/// contents are undefined and can lead to unpredictable results.
///
/// \param timer Pointer to timer object.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_timer_stop(XosTimer * timer);
//-----------------------------------------------------------------------------
///
/// Reset and restart the timer.
///
/// The timer is reset to go off at time "when" from now. If the timer was not
/// active, it will be activated. If the timer was active, it will be restarted.
/// If the timer is periodic, the period will be set to "when".
/// The timer object must have been initialized at some point before this call.
///
/// \param timer Pointer to timer object.
///
/// \param when Number of cycles from now that the timer will expire.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_timer_restart(XosTimer * timer, uint64_t when);
//-----------------------------------------------------------------------------
///
/// Check if the timer is active. The timer is active if it has been started
/// and not yet expired or canceled.
///
/// \param timer Pointer to timer object.
///
/// \return Returns non-zero if the timer is active, else zero.
///
//-----------------------------------------------------------------------------
static inline int32_t
xos_timer_is_active(XosTimer * timer)
{
return timer ? timer->active : 0;
}
//-----------------------------------------------------------------------------
///
/// Get the repeat period for a periodic timer. For a one-shot timer this will
/// return zero. The period is reported in system clock cycles.
///
/// \param timer Pointer to timer object.
///
/// \return Returns period in cycles, or zero for non-periodic timers.
///
//-----------------------------------------------------------------------------
static inline uint64_t
xos_timer_get_period(XosTimer * timer)
{
return timer ? timer->delta : 0;
}
//-----------------------------------------------------------------------------
///
/// Set the repeat period for a periodic timer. The period must be specified
/// in system clock cycles.
///
/// If the timer is active, the change in period does not take effect until
/// the timer expires at least once after this call.
/// Note that setting a period of zero will effectively turn a periodic timer
/// into a one-shot timer. Similarly, a one-shot timer can be turned into a
/// periodic timer.
///
/// \param timer Pointer to timer object.
///
/// \param period Repeat period in system clock cycles.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_timer_set_period(XosTimer * timer, uint64_t period);
//-----------------------------------------------------------------------------
///
/// Get the current system cycle count. This accounts for the periodic rollover
/// of the 32-bit CCOUNT cycle counter and returns a 64-bit value.
///
/// \return Returns the current system cycle count.
///
//-----------------------------------------------------------------------------
static inline uint64_t
xos_get_system_cycles(void)
{
extern uint64_t xos_system_cycles;
extern uint32_t xos_last_ccount;
// xos_last_ccount was updated when xos_system_cycles was last updated.
// We need to add in the number of cycles elapsed since then.
return xos_system_cycles + (xos_get_ccount() - xos_last_ccount);
}
//-----------------------------------------------------------------------------
///
/// Put calling thread to sleep for at least the specified number of cycles.
/// The actual number of cycles spent sleeping may be larger depending upon
/// the granularity of the system timer. Once the specified time has elapsed
/// the thread will be woken and made ready.
///
/// \param cycles Number of system clock cycles to sleep.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_thread_sleep(uint64_t cycles);
//-----------------------------------------------------------------------------
///
/// Put calling thread to sleep for at least the specified number of msec.
/// The actual amount of time spent sleeping may be larger depending upon
/// the granularity of the system timer. Once the specified time has elapsed
/// the thread will be woken and made ready.
///
/// \return msecs The number of milliseconds to sleep.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
static inline int32_t
xos_thread_sleep_msec(uint64_t msecs)
{
return xos_thread_sleep(xos_msecs_to_cycles(msecs));
}
//-----------------------------------------------------------------------------
///
/// Put calling thread to sleep for at least the specified number of usec.
/// The actual amount of time spent sleeping may be larger depending upon
/// the granularity of the system timer. Once the specified time has elapsed
/// the thread will be woken and made ready.
///
/// \return usecs The number of microseconds to sleep.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
static inline int32_t
xos_thread_sleep_usec(uint64_t usecs)
{
return xos_thread_sleep(xos_usecs_to_cycles(usecs));
}
//-----------------------------------------------------------------------------
///
/// Wait on a timer until it expires or is cancelled. The calling thread will
/// be blocked. The timer must be active.
/// NOTE: This operation is only available if XOS_OPT_TIMER_WAIT is set
/// to 1 in the configuration options.
///
/// \param timer Pointer to timer object.
///
/// \return Returns XOS_OK on normal timeout, else an error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_timer_wait(XosTimer * timer);
//-----------------------------------------------------------------------------
// System timer control interface.
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Defines for system timer ID.
//-----------------------------------------------------------------------------
#define XOS_SYS_TIMER_0 0 ///< Internal timer 0
#define XOS_SYS_TIMER_1 1 ///< Internal timer 1
#define XOS_SYS_TIMER_2 2 ///< Internal timer 2
#define XOS_SYS_TIMER_EXTERNAL -2 ///< External timer
#define XOS_SYS_TIMER_NONE -1 ///< No system timer selected
//-----------------------------------------------------------------------------
///
/// This function handles XOS timer tick processing. It must be called by the
/// timer interrupt handler on every timer interrupt. This function computes
/// the time to the next tick and sets it up by calling xos_system_timer_set().
///
//-----------------------------------------------------------------------------
void
xos_tick_handler(void);
//-----------------------------------------------------------------------------
///
/// Selects the timer to use. The selection may be one of the internal timers
/// or an external timer. The default implementation selects an internal timer.
/// This function can be overridden to provide custom timer processing or to
/// support an external timer.
///
/// \param timer_num The internal timer number to select (0-2) or
/// -1 to auto-select a timer. This parameter can
/// be ignored by custom implementations that use
/// an external timer.
///
/// \param psel Pointer to a location where the selected timer
/// ID must be returned. The timer ID must be one
/// of XOS_SYS_TIMER_0, XOS_SYS_TIMER_1, XOS_SYS_TIMER_2
/// or XOS_SYS_TIMER_EXTERNAL.
///
/// \return Returns XOS_OK on success, else error code.
///
//-----------------------------------------------------------------------------
int32_t
xos_system_timer_select(int32_t timer_num, int32_t *psel);
//-----------------------------------------------------------------------------
///
/// Starts the system timer and sets up the first interrupt. This function can
/// be overridden to provide custom timer processing or to support an external
/// timer.
///
/// \param cycles The number of CPU cycles from now when the
/// first interrupt must occur.
///
//-----------------------------------------------------------------------------
void
xos_system_timer_init(uint32_t cycles);
//-----------------------------------------------------------------------------
///
/// Sets the next trigger value of the system timer. The parameter 'cycles' is
/// the number of CPU cycles from now when the interrupt must occur.
/// This function can be overridden to provide custom timer processing or to
/// support an external timer.
///
/// \param cycles The number of CPU cycles from now when the
/// next interrupt must occur.
///
//-----------------------------------------------------------------------------
void
xos_system_timer_set(uint32_t cycles);
#ifdef __cplusplus
}
#endif
#endif // __XOS_TIMER_H__

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components/esp32/include/xtensa/xos_types.h
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/** @file */
// xos_types.h - XOS type definitions.
// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// NOTE: Do not include this file directly in your application. Including
// xos.h will automatically include this file.
#ifndef __XOS_TYPES_H__
#define __XOS_TYPES_H__
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
//-----------------------------------------------------------------------------
// The following are defined here because of the variations in the C libraries
// that we need to work with.
// - Not all of them have stdbool.h
// - Not all of them define NULL as (void *)0
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
///
/// XOS define for NULL value. This makes the NULL value independent of the
/// C library (not all of them define NULL the same way).
///
//-----------------------------------------------------------------------------
#define XOS_NULL ((void *)0)
//-----------------------------------------------------------------------------
///
/// XOS definition of 'bool' type. Some C libraries do not support stdbool.h.
///
//-----------------------------------------------------------------------------
#ifndef bool
#define bool int8_t
#define false 0 ///< XOS definition of 'false'
#define true 1 ///< XOS definition of 'true'
#endif
#ifdef __cplusplus
}
#endif
#endif // !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#endif // __XOS_TYPES_H__

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components/esp32/include/xtensa/xt_perfmon.h
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/*
* Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef __XT_PERFMON_H__
#define __XT_PERFMON_H__
#include <xtensa/config/core.h>
#include <xtensa/xt_perf_consts.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef int counter_id_t;
/* xt_perf_init
Initialize the performance monitor library. Ordinarily, this
function is called automatically via the .init section. If your
environment does not support the .init section, you will need to
call this function from your code.
*/
extern void xt_perf_init(void);
/* xt_perf_enable
Turn on the performance monitor. Ordinarily, counting is off by
default. If you turn off performance monitor using xt_perf_disable or
by call to a function that disables performance monitor, you can turn
it on again via this function.
*/
extern void xt_perf_enable(void);
/* xt_perf_disable
Turn off the performance monitor. If you want to suspend counting
events for a portion of your code, use this function and then call
xt_perf_enable when you want to start again.
*/
extern void xt_perf_disable(void);
/* xt_perf_clear
Disable performance monitor and clear all initialized hardware counters.
All counter ids are invalid after call to this function and all hardware
counters available for initialization.
*/
extern void xt_perf_clear (void);
/* xt_perf_counters_num
Returns number of free hardware performance counters. After call to xt_perf_clear
all counters are free and available for initialization. With each successful
xt_perf_init_counter/xt_perf_init_event call this number is decreasing until
no free counters available.
*/
extern int xt_perf_counters_num (void);
/* xt_perf_init_counter32
Setup 32 bit performance counter. This function disables performance monitor
if it was enabled.
Returns zero based counter id on success or negative value if failed.
This function may fail if there is insufficient number of free hardware
counters or function arguments are invalid.
The counter id returned on success can be used with xt_perf_reset_counter
and xt_perf_counter32 functions.
<selector> - events group, one of XTPERF_CNT constants defined in
xt_perf_consts.h;
<mask> - events mask for selected group. Mask bit fields for each
selector defined with XTPERF_MASK prefix in xt_perf_consts.h;
<trace_level> - specifies interrupt levels at which to count events;
if trace_level is greater or equal to zero events are
counted only at interrupt levels below or equal to
trace_level; if trace_level is negative events are
counted only at (-trace_level) interrupt level or higher.
*/
extern counter_id_t xt_perf_init_counter32 ( unsigned int selector,
unsigned int mask,
int trace_level);
/* xt_perf_init_counter64
Setup 64 bit performance counter. Library emulates 64 bit counters by handling
profiling interrupt and recording overflows of 32 bit hardware counters.
This function disables performance monitor if it was enabled.
Returns zero based counter id on success or negative value if failed.
This function may fail if there is insufficient number of free hardware
counters or function arguments are invalid.
The counter id returned on success can be used with xt_perf_reset_counter
and xt_perf_counter64 functions.
<selector> - events group, one of XTPERF_CNT constants defined in
xt_perf_consts.h;
<mask> - events mask for selected group. Mask bit fields for each
selector defined with XTPERF_MASK prefix in xt_perf_consts.h;
<trace_level> - specifies interrupt levels at which to count events;
if trace_level is greater or equal to zero events are
counted only at interrupt levels below or equal to
trace_level; if trace_level is negative events are
counted only at (-trace_level) interrupt level or higher.
*/
extern counter_id_t xt_perf_init_counter64 ( unsigned int selector,
unsigned int mask,
int trace_level);
/* xt_perf_reset_counter
Reset counter value to 0.
Returns zero on success or non zero if failed.
*/
extern int xt_perf_reset_counter (counter_id_t counter_id);
/* xt_perf_counter32
Read 32 bit counter value.
Returns zero if counter id is not valid.
*/
extern unsigned int xt_perf_counter32 (counter_id_t counter_id);
/* xt_perf_counter64
Read 64 bit counter value.
Counter must be initialized using xt_perf_init_counter64 function.
Returns zero if counter id is not valid.
*/
extern unsigned long long xt_perf_counter64 (counter_id_t counter_id);
/* xt_perf_overflow32
Read overflow flag of 32 bit counter. This flag is dropped when
counter initialized or reset. Once counter overflows and wraps
around the flag is set and stays set until counter reset.
Returns negative value if counter id is invalid, zero if counter
not overflowed, positive if in overflowed state.
*/
extern int xt_perf_overflow32 (counter_id_t counter_id);
#ifdef __cplusplus
}
#endif
#endif /* __XT_PERFMON_H__ */

233
components/esp32/include/xtensa/xt_profiling.h
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@@ -1,233 +0,0 @@
/*
* Customer ID=11656; Build=0x5f626; Copyright (c) 2005-2012 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#ifndef __XT_PROFILER_H__
#define __XT_PROFILER_H__
#include <xtensa/config/core.h>
#if XCHAL_NUM_PERF_COUNTERS
/* Performance monitor counters constants */
#include <xtensa/xt_perf_consts.h>
#endif /* XCHAL_NUM_PERF_COUNTERS */
#ifdef __cplusplus
extern "C" {
#endif
/* This file defines an interface that allows a program being profiled
to control when and how it is profiled, whether it is running under
the instruction set simulator or under the hardware profiler.
Both ISS and HWP implement this interface, although in different
ways. Both also do the right thing if you don't call any of these
functions.
*/
/*
xt_profile_init
ISS: a no op.
HWP: Initialize the profiler. Ordinarily, this function is called
automatically via the .init section. If your environment does not
support the .init section, you will need to call this function
by hand.
*/
extern void xt_profile_init(void);
/*
xt_profile_add_memory
ISS: a no op.
HWP:
Makes "buf_size" bytes at "buf" available to the hardware profiler.
This buffer should be initialized to zeros prior to this call.
The hardware profiler has already estimated the amount of memory it needs,
but under certain circumstances may still run out of memory. If so, you can
provide more memory with this routine.
*/
extern void xt_profile_add_memory(void * buf, unsigned int buf_size);
/* xt_profile_enable
Turn on the profiler. Ordinarily, profiling is on by default.
If you turn off profiling using xt_profile_disable, You can turn
it on again via this function.
*/
extern void xt_profile_enable(void);
/* xt_profile_disable
Turn off the profiler. If you don't want to profile a portion of your code,
use this function and then xt_profile_enable when you want to start again.
*/
extern void xt_profile_disable(void);
/* xt_profile_save_and_reset
Save and reset the profiler's data.
If there were errors, either during profiling or while attempting to
write the data, no data will be written and this function will
return non-zero.
*/
extern int xt_profile_save_and_reset(void);
/* xt_profile_get_frequency
ISS: always returns 1.
HWP:
Returns the number of cycles between samples for timer based profiler.
In performance counters based profiler always returns 1.
*/
extern unsigned int xt_profile_get_frequency(void);
/* xt_profile_set_frequency
ISS: a no op.
HWP:
Set the number of cycles between samples for timer based profiler.
Ignored in performance counters based profiler.
sample frequency is the number of cycles to wait between samples. It should
be a multiple of 1024.
If you set the sample frequency to a different value than was passed in xt_profile_init,
then the labels in the output will reflect the later frequency, even though some samples may
have been taken at the earlier frequency. Typically this does not make a significant difference
in the results if this function is called early enough.
*/
extern void xt_profile_set_frequency(unsigned int sample_frequency);
/* xt_profile_num_errors
ISS: always returns 0
HWP:
Returns the number of errors that occured while taking samples. Typically these
are out of memory errors and you need to pass a bigger buffer to
xt_profile_add_memory
*/
extern int xt_profile_num_errors(void);
#if XCHAL_NUM_PERF_COUNTERS
/* xt_profile_randomize
ISS: not available
HWP: Available in performance monitor based profiler.
Turns on or off sampling period randomization mode. Period randomization
helps to avoid aliasing problems when code being profiled is highly periodic.
Profiler maintains same average sampling period but individual sampling
steps may vary.
Period randomization is turned off by default.
<value> - non zero turns randomization on,
zero turns randomization off.
*/
extern void xt_profile_randomization(int value);
/* xt_profile_config_clear
ISS: not available
HWP: Available in performance monitor based profiler.
Stops profiling if it was enabled and clears performance counters
parameters. Accumulated profile data stays in memory and will be
saved when xt_profile_save_and_reset is called or at program exit.
Number of configured performance counters is zero after this
function call.
*/
extern void xt_profile_config_clear(void);
/* xt_profile_config_num
ISS: not available
HWP: Available in performance monitor based profiler.
Returns number of free performance counters.
*/
extern int xt_profile_config_num(void);
/* xt_profile_config_counter error codes
*/
#define XTPROF_ERR_OUT_OF_MEM -1
#define XTPROF_ERR_INVALID_ARGS -2
#define XTPROF_ERR_NOT_ENOUGH_COUNTERS -3
#define XTPROF_ERR_DEFUNCT -4
/* xt_profile_config_counter
ISS: not available
HWP: Available in performance monitor based profiler.
Allocating and initializing one or more performance counter for sampling.
Even though event may require multiple performance counters allocated the
profile data for event is merged and dumped into single gmon file.
This function disables profiling if it was enabled.
Returns 0 on success, non zero if failed:
XTPROF_ERR_OUT_OF_MEM - memory allocation failed;
XTPROF_ERR_INVALID_ARGS - invalid function parameters;
XTPROF_ERR_NOT_ENOUGH_COUNTERS - not enough free performance counters available;
XTPROF_ERR_DEFUNCT - profiling is disabled because of previous errors
(xt_profile_num_errors() is non zero)
<selector> - events group, one of XTPERF_CNT constants defined in xt_perf_consts.h
<mask> - events mask for selected group. Mask bit fields for each
selector defined with XTPERF_MASK prefix in xt_perf_consts.h
<trace_level> - specifies interrupt levels at which to take samples;
if trace_level is greater or equal to zero samples are
taken only at interrupt levels below or equal to
trace_level; if trace_level is negative samples are taken
only at (-trace_level) interrupt level or higher.
<period> - sampling period; 1 - record every event, 2 - record every
other event and so on;
Please note - there is overhead associated with events recording,
high frequency events may produce incorrect profile when period
is too small.
*/
extern int xt_profile_config_counter ( unsigned int selector,
unsigned int mask,
int trace_level,
unsigned int period);
#endif /* XCHAL_NUM_PERF_COUNTERS */
#ifdef __cplusplus
}
#endif
#endif /* __XT_PROFILER_H__ */

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/*
* Customer ID=11656; Build=0x5f626; Copyright (c) 2009-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of
* Tensilica Inc. They may be adapted and modified by bona fide
* purchasers for internal use, but neither the original nor any
* adapted or modified version may be disclosed or distributed to
* third parties in any manner, medium, or form, in whole or in part,
* without the prior written consent of Tensilica Inc.
*
* This software and its derivatives are to be executed solely on
* products incorporating a Tensilica processor.
*/
// Utility routines for returning pass/fail status in HW simulations
#ifndef XT_REF_TESTBENCH_H
#define XT_REF_TESTBENCH_H 1
#ifdef __cplusplus
extern "C" {
#endif
// Exit routines for HW simulation
extern int diag_pass();
extern int diag_fail();
// Set exit status for HW simulation
int set_diag_status(int stat);
// Setup for user power toggling
extern int setup_power_toggle();
// Return exit status location
extern unsigned int* testbench_exit_location();
// Return power toggle location
extern unsigned int* testbench_power_toggle_location();
// Change exit status location
// You must also change the plusarg "+DVMagicExit" sent to the HW simulator
// or change the argument "--exit_location" sent to the ISS
extern unsigned int* set_testbench_exit_location(unsigned int*);
// Change power toggle location
// You must also change the plusarg "+DVPowerLoc" sent to the HW simulator
extern unsigned int* set_testbench_power_toggle_location(unsigned int*);
// Exit routines with status message
//
static inline
int pass(const char *msg)
{
return diag_pass();
}
static inline
int fail(const char *msg)
{
return diag_fail();
}
#define POWER_TOGGLE_ON 1
#define POWER_TOGGLE_OFF 0
// Routine to turn on and off power toggle
// Does a magic write that Monitors.v intercepts and appropriately turns
// SAIF dumping on and offf
//
extern volatile unsigned int *_reftb_power_toggle;
__attribute__ ((always_inline))
static inline
int set_power_toggle(int val)
{
#ifdef __XTENSA__
*_reftb_power_toggle = val;
#endif
return val;
}
#ifdef __cplusplus
}
#endif
#endif // XT_REF_TESTBENCH_H

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components/esp32/include/xtensa/xtav110.h
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/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* xtav110.h - Xtensa Avnet LX110 (XT-AV110) board specific definitions */
#ifndef _INC_XTAV110_H_
#define _INC_XTAV110_H_
#include <xtensa/config/core.h>
#include <xtensa/config/system.h>
#define XTBOARD_NAME "XT-AV110"
/*
* Default assignment of XTAV110 devices to external interrupts.
*/
/* Ethernet interrupt: */
#ifdef XCHAL_EXTINT1_NUM
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
#else
#define ETHERNET_INTMASK 0
#endif
/* UART interrupt: */
#ifdef XCHAL_EXTINT0_NUM
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
#else
#define UART16550_INTMASK 0
#endif
/* Audio output interrupt (I2S transmitter FIFO): */
#ifdef XCHAL_EXTINT2_NUM
#define AUDIO_I2S_OUT_INTNUM XCHAL_EXTINT2_NUM
#define AUDIO_I2S_OUT_INTLEVEL XCHAL_EXTINT2_LEVEL
#define AUDIO_I2S_OUT_INTMASK XCHAL_EXTINT2_MASK
#else
#define AUDIO_I2S_OUT_INTMASK 0
#endif
/* Audio input interrupt (I2S receiver FIFO): */
#ifdef XCHAL_EXTINT3_NUM
#define AUDIO_I2S_IN_INTNUM XCHAL_EXTINT3_NUM
#define AUDIO_I2S_IN_INTLEVEL XCHAL_EXTINT3_LEVEL
#define AUDIO_I2S_IN_INTMASK XCHAL_EXTINT3_MASK
#else
#define AUDIO_I2S_IN_INTMASK 0
#endif
/* I2C interrupt */
#ifdef XCHAL_EXTINT4_NUM
#define I2C_INTNUM XCHAL_EXTINT4_NUM
#define I2C_INTLEVEL XCHAL_EXTINT4_LEVEL
#define I2C_INTMASK XCHAL_EXTINT4_MASK
#else
#define I2C_INTMASK 0
#endif
/* USB interrupt */
#ifdef XCHAL_EXTINT5_NUM
#define USB_INTNUM XCHAL_EXTINT5_NUM
#define USB_INTLEVEL XCHAL_EXTINT5_LEVEL
#define USB_INTMASK XCHAL_EXTINT5_MASK
#else
#define USB_INTMASK 0
#endif
/*
* Device addresses.
*
* Note: for endianness-independence, use 32-bit loads and stores for all
* register accesses to Ethernet, UART and LED devices. Undefined bits
* may need to be masked out if needed when reading if the actual register
* size is smaller than 32 bits.
*
* Note: XTAV110 bus byte lanes are defined in terms of msbyte and lsbyte
* relative to the processor. So 32-bit registers are accessed consistently
* from both big and little endian processors. However, this means byte
* sequences are not consistent between big and little endian processors.
* This is fine for RAM, and for ROM if ROM is created for a specific
* processor (and thus has correct byte sequences). However this may be
* unexpected for Flash, which might contain a file-system that one wants
* to use for multiple processor configurations (eg. the Flash might contain
* the Ethernet card's address, endianness-independent application data, etc).
* That is, byte sequences written in Flash by a core of a given endianness
* will be byte-swapped when seen by a core of the other endianness.
* Someone implementing an endianness-independent Flash file system will
* likely handle this byte-swapping issue in the Flash driver software.
*/
#define XTBOARD_FLASH_MAXSIZE 0x1000000 /* 16 MB */
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
/* Flash Memory: */
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
/* UART National-Semi PC16550D: */
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
/* I2S transmitter */
# define AUDIO_I2S_OUT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D080000)
/* I2S receiver */
# define AUDIO_I2S_IN_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D088000)
/* I2C master */
# define I2C_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D090000)
/* SPI controller */
# define SPI_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0A0000)
/* Display controller Sunplus SPLC780D, 4bit mode,
* LCD Display MYTech MOC-16216B-B: */
# define SPLC780D_4BIT_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0C0000)
/* USB Controller */
# define USB_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D0D0000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
/*** Same thing over again, this time with virtual addresses: ***/
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
/* Flash Memory: */
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
/* UART National-Semi PC16550D: */
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
/* I2S transmitter */
# define AUDIO_I2S_OUT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D080000)
/* I2S receiver */
# define AUDIO_I2S_IN_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D088000)
/* I2C master */
# define I2C_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D090000)
/* SPI controller */
# define SPI_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0A0000)
/* Display controller Sunplus SPLC780D, 4bit mode,
* LCD Display MYTech MOC-16216B-B: */
# define SPLC780D_4BIT_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0C0000)
/* USB Controller */
# define USB_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D0D0000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
/* System ROM: */
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
#ifdef XSHAL_ROM_VADDR
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
#endif
#ifdef XSHAL_ROM_PADDR
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
#endif
/* System RAM: */
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
#ifdef XSHAL_RAM_VADDR
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
#endif
#ifdef XSHAL_RAM_PADDR
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
#endif
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
/*
* Things that depend on device addresses.
*/
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
/*
* FPGA registers.
* All these registers are normally accessed using 32-bit loads/stores.
*/
/* Register offsets: */
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
/* Physical register addresses: */
#ifdef XTBOARD_FPGAREGS_PADDR
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS)
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
#endif
/* Virtual register addresses: */
#ifdef XTBOARD_FPGAREGS_VADDR
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS)
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
/* Register access (for C code): */
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR)
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
#endif
/* DATECD (date code; when core was built) bit fields: */
/* BCD-coded month (01..12): */
#define XTBOARD_DATECD_MONTH_SHIFT 24
#define XTBOARD_DATECD_MONTH_BITS 8
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
/* BCD-coded day (01..31): */
#define XTBOARD_DATECD_DAY_SHIFT 16
#define XTBOARD_DATECD_DAY_BITS 8
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
/* BCD-coded year (2001..9999): */
#define XTBOARD_DATECD_YEAR_SHIFT 0
#define XTBOARD_DATECD_YEAR_BITS 16
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
/* SYSLED (system LED) bit fields: */
/* LED control bits (off=0, on=1): */
#define XTBOARD_SYSLED_USER_SHIFT 0
#define XTBOARD_SYSLED_USER_BITS 2
#define XTBOARD_SYSLED_USER_MASK 0x00000003
/* DIP Switch SW5 (left=sw1=lsb=bit0, right=sw4=msb=bit3; off=0, on=1): */
/* DIP switch bit fields (bit2/sw3 is reserved and presently unused): */
#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-2 (1=lsb) */
#define XTBOARD_DIPSW_USER_BITS 2
#define XTBOARD_DIPSW_USER_MASK 0x00000003
#define XTBOARD_DIPSW_BOOT_SHIFT 3 /* labeled 8 (msb) */
#define XTBOARD_DIPSW_BOOT_BITS 1
#define XTBOARD_DIPSW_BOOT_MASK 0x00000008
/* Boot settings: bit3/sw4, off=0, on=1 (this switch controls hardware): */
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
/* Software reset bits: */
#define XTBOARD_SWRST_SWR_SHIFT 0
#define XTBOARD_SWRST_SWR_BITS 16
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
/* Software reset value -- writing this value resets the board: */
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
#endif /*_INC_XTAV110_H_*/

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components/esp32/include/xtensa/xtav110/xtensa/board.h
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/*
* board.h - Include board-specific definitions
*
* Copyright (c) 2010 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#include <xtensa/xtav110.h>

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components/esp32/include/xtensa/xtav200.h
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/* Copyright (c) 2007-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* xtav200.h - Xtensa Avnet LX200 (XT-AV200) board specific definitions */
#ifndef _INC_XTAV200_H_
#define _INC_XTAV200_H_
#include <xtensa/config/core.h>
#include <xtensa/config/system.h>
#define XTBOARD_NAME "XT-AV200"
/*
* Default assignment of XTAV200 devices to external interrupts.
*/
/* Ethernet interrupt: */
#ifdef XCHAL_EXTINT1_NUM
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
#else
#define ETHERNET_INTMASK 0
#endif
/* UART interrupt: */
#ifdef XCHAL_EXTINT0_NUM
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
#else
#define UART16550_INTMASK 0
#endif
/* Audio output interrupt (I2S FIFO underrun): */
#ifdef XCHAL_EXTINT2_NUM
#define AUDIO_INTNUM XCHAL_EXTINT2_NUM
#define AUDIO_INTLEVEL XCHAL_EXTINT2_LEVEL
#define AUDIO_INTMASK XCHAL_EXTINT2_MASK
#else
#define AUDIO_INTMASK 0
#endif
/* Audio output (I2S FIFO level) interrupt: */
#ifdef XCHAL_EXTINT3_NUM
#define AUDIO_I2SLVL_INTNUM XCHAL_EXTINT3_NUM
#define AUDIO_I2SLVL_INTLEVEL XCHAL_EXTINT3_LEVEL
#define AUDIO_I2SLVL_INTMASK XCHAL_EXTINT3_MASK
#else
#define AUDIO_I2SLVL_INTMASK 0
#endif
/* Audio input (ADC FIFO level) interrupt: */
#ifdef XCHAL_EXTINT4_NUM
#define AUDIO_ADCLVL_INTNUM XCHAL_EXTINT4_NUM
#define AUDIO_ADCLVL_INTLEVEL XCHAL_EXTINT4_LEVEL
#define AUDIO_ADCLVL_INTMASK XCHAL_EXTINT4_MASK
#else
#define AUDIO_ADCLVL_INTMASK 0
#endif
/*
* Device addresses.
*
* Note: for endianness-independence, use 32-bit loads and stores for all
* register accesses to Ethernet, UART and LED devices. Undefined bits
* may need to be masked out if needed when reading if the actual register
* size is smaller than 32 bits.
*
* Note: XTAV200 bus byte lanes are defined in terms of msbyte and lsbyte
* relative to the processor. So 32-bit registers are accessed consistently
* from both big and little endian processors. However, this means byte
* sequences are not consistent between big and little endian processors.
* This is fine for RAM, and for ROM if ROM is created for a specific
* processor (and thus has correct byte sequences). However this may be
* unexpected for Flash, which might contain a file-system that one wants
* to use for multiple processor configurations (eg. the Flash might contain
* the Ethernet card's address, endianness-independent application data, etc).
* That is, byte sequences written in Flash by a core of a given endianness
* will be byte-swapped when seen by a core of the other endianness.
* Someone implementing an endianness-independent Flash file system will
* likely handle this byte-swapping issue in the Flash driver software.
*/
#define XTBOARD_FLASH_MAXSIZE 0x1000000 /* 16 MB */
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
/* Flash Memory: */
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
/* UART National-Semi PC16550D: */
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
/* TI 320AIC23/28-TSSOP Stereo Audio Codec: */
# define AUDIO_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D070000)
/* Boot 128K Sram address: */
# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000)
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
/*** Same thing over again, this time with virtual addresses: ***/
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
/* Flash Memory: */
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
/* UART National-Semi PC16550D: */
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
/* TI 320AIC23/28-TSSOP Stereo Audio Codec: */
# define AUDIO_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D070000)
/* 128K Sram address: */
# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
# define AUDIO_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D070000)
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000)
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
/* System ROM: */
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
#ifdef XSHAL_ROM_VADDR
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
#endif
#ifdef XSHAL_ROM_PADDR
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
#endif
/* System RAM: */
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
#ifdef XSHAL_RAM_VADDR
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
#endif
#ifdef XSHAL_RAM_PADDR
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
#endif
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
/*
* Things that depend on device addresses.
*/
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
/*
* FPGA registers.
* All these registers are normally accessed using 32-bit loads/stores.
*/
/* Register offsets: */
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
#define XTBOARD_SYSLED_OFS 0x08 /* LEDs */
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
/* Physical register addresses: */
#ifdef XTBOARD_FPGAREGS_PADDR
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_SYSLED_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SYSLED_OFS)
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
#endif
/* Virtual register addresses: */
#ifdef XTBOARD_FPGAREGS_VADDR
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_SYSLED_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SYSLED_OFS)
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
/* Register access (for C code): */
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
#define XTBOARD_SYSLED_REG (*(volatile unsigned*) XTBOARD_SYSLED_VADDR)
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
#endif
/* DATECD (date code; when core was built) bit fields: */
/* BCD-coded month (01..12): */
#define XTBOARD_DATECD_MONTH_SHIFT 24
#define XTBOARD_DATECD_MONTH_BITS 8
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
/* BCD-coded day (01..31): */
#define XTBOARD_DATECD_DAY_SHIFT 16
#define XTBOARD_DATECD_DAY_BITS 8
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
/* BCD-coded year (2001..9999): */
#define XTBOARD_DATECD_YEAR_SHIFT 0
#define XTBOARD_DATECD_YEAR_BITS 16
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
/* SYSLED (system LED) bit fields: */
/* LED control bits (off=0, on=1): */
#define XTBOARD_SYSLED_USER_SHIFT 0
#define XTBOARD_SYSLED_USER_BITS 4
#define XTBOARD_SYSLED_USER_MASK 0x0000000F
/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */
/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */
#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */
#define XTBOARD_DIPSW_USER_BITS 6
#define XTBOARD_DIPSW_USER_MASK 0x0000003F
#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */
#define XTBOARD_DIPSW_BOOT_BITS 1
#define XTBOARD_DIPSW_BOOT_MASK 0x00000080
/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
/* Software reset bits: */
#define XTBOARD_SWRST_SWR_SHIFT 0
#define XTBOARD_SWRST_SWR_BITS 16
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
/* Software reset value -- writing this value resets the board: */
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
#endif /*_INC_XTAV200_H_*/

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components/esp32/include/xtensa/xtav200/xtensa/board.h
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/*
* board.h - Include board-specific definitions
*
* Copyright (c) 2008 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#include <xtensa/xtav200.h>

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components/esp32/include/xtensa/xtav60.h
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/* Copyright (c) 2002-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* xtav60.h - Xtensa Avnet LX60 (XT-AV60) board specific definitions */
#ifndef _INC_XTAV60_H_
#define _INC_XTAV60_H_
#include <xtensa/config/core.h>
#include <xtensa/config/system.h>
#define XTBOARD_NAME "XT-AV60"
/*
* Default assignment of XTAV60 devices to external interrupts.
*/
/* Ethernet interrupt: */
#ifdef XCHAL_EXTINT1_NUM
#define ETHERNET_INTNUM XCHAL_EXTINT1_NUM
#define ETHERNET_INTLEVEL XCHAL_EXTINT1_LEVEL
#define ETHERNET_INTMASK XCHAL_EXTINT1_MASK
#else
#define ETHERNET_INTMASK 0
#endif
/* UART interrupt: */
#ifdef XCHAL_EXTINT0_NUM
#define UART16550_INTNUM XCHAL_EXTINT0_NUM
#define UART16550_INTLEVEL XCHAL_EXTINT0_LEVEL
#define UART16550_INTMASK XCHAL_EXTINT0_MASK
#else
#define UART16550_INTMASK 0
#endif
/*
* Device addresses.
*
* Note: for endianness-independence, use 32-bit loads and stores for all
* register accesses to Ethernet, UART and LED devices. Undefined bits
* may need to be masked out if needed when reading if the actual register
* size is smaller than 32 bits.
*
* Note: XTAV60 bus byte lanes are defined in terms of msbyte and lsbyte
* relative to the processor. So 32-bit registers are accessed consistently
* from both big and little endian processors. However, this means byte
* sequences are not consistent between big and little endian processors.
* This is fine for RAM, and for ROM if ROM is created for a specific
* processor (and thus has correct byte sequences). However this may be
* unexpected for Flash, which might contain a file-system that one wants
* to use for multiple processor configurations (eg. the Flash might contain
* the Ethernet card's address, endianness-independent application data, etc).
* That is, byte sequences written in Flash by a core of a given endianness
* will be byte-swapped when seen by a core of the other endianness.
* Someone implementing an endianness-independent Flash file system will
* likely handle this byte-swapping issue in the Flash driver software.
*/
#define XTBOARD_FLASH_MAXSIZE 0x400000 /* 4 MB */
#ifdef XSHAL_IOBLOCK_BYPASS_PADDR
/* Flash Memory: */
# define XTBOARD_FLASH_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x08000000)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D030000)
# define ETHERNET_CONTROLLER_PADDR ETHERNET_PADDR /* legacy macro */
/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */
# define SPLC780D_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D040000)
/* UART National-Semi PC16550D: */
# define UART16550_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D050000)
/* Boot 128K Sram address: */
# define BOOT_SRAM_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D400000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_PADDR (XSHAL_IOBLOCK_BYPASS_PADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_PADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_PADDR
# define XTBOARD_FLASH_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x08000000)
# define ETHERNET_BUFFER_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D800000)
# define BOOT_SRAM_CACHED_PADDR (XSHAL_IOBLOCK_CACHED_PADDR+0x0D400000)
#endif /* XSHAL_IOBLOCK_CACHED_PADDR */
/*** Same thing over again, this time with virtual addresses: ***/
#ifdef XSHAL_IOBLOCK_BYPASS_VADDR
/* Flash Memory: */
# define XTBOARD_FLASH_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x08000000)
/* FPGA registers: */
# define XTBOARD_FPGAREGS_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D020000)
/* Ethernet controller/transceiver SONIC SN83934: */
# define ETHERNET_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D030000)
/* Display controller Sunplus SPLC780D, LCD Display MYTech MOC-16216B-B: */
# define SPLC780D_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D040000)
/* UART National-Semi PC16550D: */
# define UART16550_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D050000)
/* 128K Sram address: */
# define BOOT_SRAM_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D400000)
/* Ethernet buffer: */
# define ETHERNET_BUFFER_VADDR (XSHAL_IOBLOCK_BYPASS_VADDR+0x0D800000)
#endif /* XSHAL_IOBLOCK_BYPASS_VADDR */
/* These devices might be accessed cached: */
#ifdef XSHAL_IOBLOCK_CACHED_VADDR
# define XTBOARD_FLASH_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x08000000)
# define ETHERNET_BUFFER_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D800000)
# define BOOT_SRAM_CACHED_VADDR (XSHAL_IOBLOCK_CACHED_VADDR+0x0D400000)
#endif /* XSHAL_IOBLOCK_CACHED_VADDR */
/* System ROM: */
#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
#ifdef XSHAL_ROM_VADDR
#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
#endif
#ifdef XSHAL_ROM_PADDR
#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
#endif
/* System RAM: */
#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
#ifdef XSHAL_RAM_VADDR
#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
#endif
#ifdef XSHAL_RAM_PADDR
#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
#endif
#define XTBOARD_RAM_BYPASS_VADDR XSHAL_RAM_BYPASS_VADDR
#define XTBOARD_RAM_BYPASS_PADDR XSHAL_RAM_BYPASS_PADDR
/*
* Things that depend on device addresses.
*/
#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_XT2000_CACHEATTR_WRITEBACK
#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_XT2000_CACHEATTR_WRITEALLOC
#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_XT2000_CACHEATTR_WRITETHRU
#define XTBOARD_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS
#define XTBOARD_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT
#define XTBOARD_BUSINT_PIPE_REGIONS XSHAL_XT2000_PIPE_REGIONS
#define XTBOARD_BUSINT_SDRAM_REGIONS XSHAL_XT2000_SDRAM_REGIONS
/*
* FPGA registers.
* All these registers are normally accessed using 32-bit loads/stores.
*/
/* Register offsets: */
#define XTBOARD_DATECD_OFS 0x00 /* date code (read-only) */
#define XTBOARD_CLKFRQ_OFS 0x04 /* clock frequency Hz (read-only) */
#define XTBOARD_DIPSW_OFS 0x0C /* DIP switch bits (read-only) */
#define XTBOARD_SWRST_OFS 0x10 /* software reset */
/* Physical register addresses: */
#ifdef XTBOARD_FPGAREGS_PADDR
#define XTBOARD_DATECD_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_DIPSW_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_PADDR (XTBOARD_FPGAREGS_PADDR+XTBOARD_SWRST_OFS)
#endif
/* Virtual register addresses: */
#ifdef XTBOARD_FPGAREGS_VADDR
#define XTBOARD_DATECD_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DATECD_OFS)
#define XTBOARD_CLKFRQ_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_CLKFRQ_OFS)
#define XTBOARD_DIPSW_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_DIPSW_OFS)
#define XTBOARD_SWRST_VADDR (XTBOARD_FPGAREGS_VADDR+XTBOARD_SWRST_OFS)
/* Register access (for C code): */
#define XTBOARD_DATECD_REG (*(volatile unsigned*) XTBOARD_DATECD_VADDR)
#define XTBOARD_CLKFRQ_REG (*(volatile unsigned*) XTBOARD_CLKFRQ_VADDR)
#define XTBOARD_DIPSW_REG (*(volatile unsigned*) XTBOARD_DIPSW_VADDR)
#define XTBOARD_SWRST_REG (*(volatile unsigned*) XTBOARD_SWRST_VADDR)
#endif
/* DATECD (date code; when core was built) bit fields: */
/* BCD-coded month (01..12): */
#define XTBOARD_DATECD_MONTH_SHIFT 24
#define XTBOARD_DATECD_MONTH_BITS 8
#define XTBOARD_DATECD_MONTH_MASK 0xFF000000
/* BCD-coded day (01..31): */
#define XTBOARD_DATECD_DAY_SHIFT 16
#define XTBOARD_DATECD_DAY_BITS 8
#define XTBOARD_DATECD_DAY_MASK 0x00FF0000
/* BCD-coded year (2001..9999): */
#define XTBOARD_DATECD_YEAR_SHIFT 0
#define XTBOARD_DATECD_YEAR_BITS 16
#define XTBOARD_DATECD_YEAR_MASK 0x0000FFFF
/* DIP Switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): */
/* DIP switch bit fields (bit6/sw7 is reserved and presently unused): */
#define XTBOARD_DIPSW_USER_SHIFT 0 /* labeled 1-6 (1=lsb) */
#define XTBOARD_DIPSW_USER_BITS 6
#define XTBOARD_DIPSW_USER_MASK 0x0000003F
#define XTBOARD_DIPSW_BOOT_SHIFT 7 /* labeled 8 (msb) */
#define XTBOARD_DIPSW_BOOT_BITS 1
#define XTBOARD_DIPSW_BOOT_MASK 0x00000080
/* Boot settings: bit7/sw8, off=0, on=1 (this switch controls hardware): */
#define XTBOARD_DIPSW_BOOT_RAM (0<<XTBOARD_DIPSW_BOOT_SHIFT) /* off */
#define XTBOARD_DIPSW_BOOT_FLASH (1<<XTBOARD_DIPSW_BOOT_SHIFT) /* on */
/* SWRST (software reset; allows s/w to generate power-on equivalent reset): */
/* Software reset bits: */
#define XTBOARD_SWRST_SWR_SHIFT 0
#define XTBOARD_SWRST_SWR_BITS 16
#define XTBOARD_SWRST_SWR_MASK 0x0000FFFF
/* Software reset value -- writing this value resets the board: */
#define XTBOARD_SWRST_RESETVALUE 0x0000DEAD
#endif /*_INC_XTAV60_H_*/

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components/esp32/include/xtensa/xtav60/xtensa/board.h
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/*
* board.h - Include board-specific definitions
*
* Copyright (c) 2008 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
* They may not be modified, copied, reproduced, distributed, or disclosed to
* third parties in any manner, medium, or form, in whole or in part, without
* the prior written consent of Tensilica Inc.
*/
#include <xtensa/xtav60.h>

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components/esp32/include/xtensa/xtav60/xtensa/lcd-splc780d-board.h
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/*******************************************************************************
Copyright (c) 2006-2007 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
lcd-splc780d-board.h Board-specific LCD info on Avnet AV60 (XT-AV60) board.
Interface between board-independent driver and board-specific header.
This is used by a board-independent SPLC780D LCD controller driver to obtain
board-specific information about LCD displays on the board, such as the
controller register base address and spacing (a function of how the address
lines are connected on the board) and length of the visible window of the
display (a function of the LCD panel the controller drives). The driver does
not refer directly to the board-specific header, which therefore is not
constrained to use macro names consistent with other boards.
!! Must not contain any board-specific macro names (only controller specific) !!
Included at compile-time via an include path specific to the board.
The XT-AV60 board contains a single MYTech MOC-16216B-B display driven by
a Sunplus SPLC870D controller.
*******************************************************************************/
#ifndef _LCD_SPLC780D_BOARD_H
#define _LCD_SPLC780D_BOARD_H
#include <xtensa/xtav60.h> /* Board info */
/* Base address of the controller's registers. */
#ifdef SPLC780D_VADDR
#define SPLC780D_REGBASE SPLC780D_VADDR
#endif
/*
The controller's registers are connected at word addresses on the XT-AV60.
Each byte-wide register appears as the least-significant-byte (LSB) of the
word regardless of the endianness of the processor (so if using word accesses
then endianness doesn't matter).
*/
#define SPLC780D_REGSPACING 4
typedef unsigned splc780d_reg_t;
/* Include generic information shared by all boards that use this device. */
#include <xtensa/lcd-splc780d.h>
/* Display limits of the LCD panel. */
#define DISPLAY_VISIBLE_LEN 16 /* length (chars) of visible window */
#endif /* _LCD_SPLC780D_BOARD_H */

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components/esp32/include/xtensa/xtbsp.h
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/*******************************************************************************
Copyright (c) 2006-2009 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
--------------------------------------------------------------------------------
xtbsp.h Xtensa Board Support Package API
This API defines a minimal set of board-support functions that every supported
Xtensa board is expected to provide in the board-support-package (BSP) library
associated with the board-specific LSP. Only basic board functions are provided
in this board-independent API. API functions not applicable to a board must be
stubbed in its BSP library. More complex operations must use a board-specific
interface. Functions are grouped by type of peripheral device.
*******************************************************************************/
#ifndef _XTBSP_H_
#define _XTBSP_H_
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
BOARD INITIALIZATION.
The board with all its devices is initialized by xtbsp_board_init().
Individual devices represented by this API can be reinitialized at any
time by calling their inidividual device init functions (grouped with
other device functions). This might be useful to (say) change the baud
rate of the UART.
*/
/*
Initialize the board. Must call before any other API function.
Iniitializes BSP, board in general, and all devices on the board.
*/
extern void xtbsp_board_init(void);
/*******************************************************************************
BOARD CHARACTERISTICS and CONVENIENCE FUNCTIONS.
Board support functions not associated with a particular peripheral device.
*/
/*
Return a short string representing the type of board.
If the board has a display, the string must fit on a single line.
*/
extern const char * xtbsp_board_name(void);
/*
Hardware reset the entire board (if possible). Does not return if successful.
If this function returns, it is stubbed out or not possible with this board.
*/
extern void xtbsp_board_reset(void);
/*
Return the clock frequency in Hertz. May be constant or computed.
*/
extern unsigned xtbsp_clock_freq_hz(void);
/*
Return the clock period in picoseconds. May be constant or computed.
*/
extern unsigned xtbsp_clock_period_ps(void);
/*
Spin (at least) a number of cycles per the processor's CCOUNT register.
Unlike a s/w delay loop, the duration is not affected by compiler
optimization or interrupts completed within the delay period.
If the processor doesn't have CCOUNT, a s/w delay loop is used to obtain
a rough approximation of the cycle count.
*/
extern void xtbsp_delay_cycles(unsigned cycles);
/*
Spin at least a number of nanoseconds (approximate and err in the high side).
BSP implementation should do this efficiently, avoiding integer overflow or
excessive loss of precision, run-time division or floating point.
Function implementation (vs. macro) allows BSP to optimize for the clock
frequency by pre-computing (or using constant) scale factors.
*/
extern void xtbsp_delay_ns(unsigned ns);
/*******************************************************************************
C LIBRARY SUPPORT.
These functions are called by the C library libgloss interface.
Their names are predetermined apart from this BSP API.
*/
/*
Initialize the board. Called by C library initialization code.
Usually simply calls xtbsp_board_init().
*/
extern void board_init(void);
/*
(Wait for and) Input a single byte from the default character I/O
device. Return -1 if there is no input device.
This device is usually a UART and this function calls xtbsp_uart_getchar().
On some boards (eg.) it might be a directly connected keyboard.
*/
extern int inbyte(void);
/*
Output a single char to the default character I/O device (and wait
until it's been taken).
This device is usually a UART and this function calls xtbsp_uart_putchar().
On some boards (eg.) it might be a directly connected bit-mapped screen.
*/
extern void outbyte(int c);
/*******************************************************************************
UART (SERIAL I/O).
Supports a single UART in a simple polling mode and provides control of
receiver and transmitter data interrupts (client must provide handler).
Provides a mapping to processor interrupt number which can be used with
the HAL to control processor interrupt enable (INTENABLE) etc.
*/
/* Bitmasks to identify UART interrupts. */
typedef enum xtbsp_uart_int {
xtbsp_uart_int_rx = 1<<0,
xtbsp_uart_int_tx = 1<<1,
/* mask of all valid interrupt bits */
xtbsp_uart_int_all = (1<<2)-1
} xtbsp_uart_int;
/*
Return non-zero if the board has a UART.
*/
extern int xtbsp_uart_exists(void);
/*
Initialize the UART:
parity = 0 (none), 1 (odd), or 2 (even).
nstop = 1 or 2 (stop bits).
ndata = 7 or 8 (data bits).
Disables all UART interrupts.
Returns non-zero if failed (perhaps due to unsupported parameter values).
Must call before any of the following functions.
*/
extern int xtbsp_uart_init(unsigned baud, unsigned ndata,
unsigned parity, unsigned nstop);
#define xtbsp_uart_init_default() xtbsp_uart_init(38400, 8, 0, 1)
/*
(Wait for and) Input a single char from the UART.
Any pending xtbsp_uart_int_rx interrupt is cleared.
*/
extern char xtbsp_uart_getchar(void);
/*
(Wait for transmitter ready and) Output a single char to the UART.
Any pending xtbsp_uart_int_tx interrupt is cleared.
*/
extern void xtbsp_uart_putchar(const char c);
/*
Return true (non-zero) if a character has been received and is ready
to be input by xtbsp_uart_getchar() without waiting, else return 0.
*/
extern int xtbsp_uart_get_isready(void);
/*
Return non-zero if a character may be output by xtbsp_uart_putchar()
without waiting, else return 0.
Any pending xtbsp_uart_int_tx interrupt is cleared.
*/
extern int xtbsp_uart_put_isready(void);
/*
Return the enable status of all UART interrupts represented by this API,
that is those with bits defined in type xtbsp_uart_int (1 bit = enabled).
This is the enable status at the device, not the processor's INTENABLE.
*/
extern xtbsp_uart_int xtbsp_uart_int_enable_status(void);
/*
Enable selected UART interrupts at the device.
*/
extern void xtbsp_uart_int_enable(const xtbsp_uart_int mask);
/*
Disable selected UART interrupts at the device.
*/
extern void xtbsp_uart_int_disable(const xtbsp_uart_int mask);
/*
Return the interrupt number (0..31) to which the selected UART interrupt
is connected. May be used with the link-time HAL to obtain more information,
eg. Xthal_intlevel_mask[xtbsp_uart_int_number(xtbsp_uart_int_rx)]
This information can be used to control the processor's INTENABLE, etc.
Result is -1 if not connected, undefined if mask has more than 1 bit set.
*/
extern int xtbsp_uart_int_number(const xtbsp_uart_int mask);
/*******************************************************************************
DISPLAY.
Supports a single display that can render a series of ASCII characters.
Functions are provided to perform generic display tasks such as display
a string, display character by character, or blank the display.
Chars are 7-bit printable ASCII. Strings are C style NUL \0 terminated.
These functions busy-wait for any required timing delays so the caller does
not have to deal with timing. Some displays require long delays which in
some client applications warrant a board and RTOS specific approach to
driving the display, however that is beyond the scope of this API.
*/
/*
Return non-zero if board has a display.
*/
extern int xtbsp_display_exists(void);
/*
Initialize the display. Must call before any of the following functions.
*/
extern void xtbsp_display_init(void);
/*
Display a single char at position pos (0 is leftmost). Other positions are
left untouched. Positions beyond the width of the display are ignored.
*/
extern void xtbsp_display_char(unsigned pos, const char c);
/*
Display a string. Blank-pad to or truncate at the end of the display
(overwrites any previous string so don't need to blank display first).
*/
extern void xtbsp_display_string(const char *s);
/*
Blank (clear) the entire display.
*/
extern void xtbsp_display_blank(void);
#ifdef __cplusplus
}
#endif
#endif /* _XTBSP_H_ */

14
components/esp32/include/xtensa/xtkc705.h
View File

@@ -1,14 +0,0 @@
/* Copyright (c) 2006-2013 by Tensilica Inc. ALL RIGHTS RESERVED.
/ These coded instructions, statements, and computer programs are the
/ copyrighted works and confidential proprietary information of Tensilica Inc.
/ They may not be modified, copied, reproduced, distributed, or disclosed to
/ third parties in any manner, medium, or form, in whole or in part, without
/ the prior written consent of Tensilica Inc.
*/
/* xtkc705.h - Xtensa Xilinx KC705 (XT-KC705) board specific definitions */
/* 99.9% same as ML605, just indicate we're KC705 and include ML605 header: */
#define XTBOARD_IS_KC705 1
#include <xtensa/xtml605.h>

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