soc: prefer assertions, disabling functions for cpu abstractions

Prefer assertions, making available functions only when caps support it
for cpu-related abstractions.

Changes cpu hal functions to stall, unstall, reset to not accept -1;
instead prefering macros that provide the same functionality.

components/soc/include/hal/cpu_hal.h

@@ -21,6 +21,7 @@
 
 #include "hal/cpu_types.h"
 #include "hal/cpu_ll.h"
+#include "soc/cpu_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -66,56 +67,60 @@ extern "C" {
  */
 #define cpu_hal_break()                 cpu_ll_break()
 
+#if SOC_CPU_BREAKPOINTS_NUM > 0
+
 /**
  * Set and enable breakpoint at an instruction address.
  *
  * @note Overwrites previously set breakpoint with same breakpoint ID.
  *
- * @param id breakpoint to set [0..SOC_CPU_BREAKPOINT_NUM - 1]
+ * @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1]
  * @param addr address to set a breakpoint on
  * 
- * @return ESP_ERR_INVALID_ARG invalid breakpoint id or addr
- * @return ESP_ERR_NOT_SUPPORTED processor does not support breakpoints
  * @return ESP_OK success
+ * @return others fail
  */
 esp_err_t cpu_hal_set_breakpoint(int id, const void* addr);
 
 /**
  * Clear and disable breakpoint.
  *
- * @param id breakpoint to clear [0..SOC_CPU_BREAKPOINT_NUM - 1]
+ * @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1]
  *
- * @return ESP_ERR_INVALID_ARG invalid breakpoint id
- * @return ESP_ERR_NOT_SUPPORTED processor does not support breakpoints
  * @return ESP_OK success
+ * @return others fail
  */
 esp_err_t cpu_hal_clear_breakpoint(int id);
 
+#endif // SOC_CPU_BREAKPOINTS_NUM > 0
+
+#if SOC_CPU_WATCHPOINTS_NUM > 0
+
 /**
  * Set and enable a watchpoint, specifying the memory range and trigger operation.
  *
- * @param id watchpoint to set [0..SOC_CPU_WATCHPOINT_NUM - 1]
+ * @param id watchpoint to set [0..SOC_CPU_WATCHPOINTS_NUM - 1]
  * @param addr starting address
  * @param size number of bytes from starting address to watch
  * @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write)
  * 
- * @return ESP_ERR_INVALID_ARG invalid watchpoint id
- * @return ESP_ERR_NOT_SUPPORTED processor does not support watchpoints
  * @return ESP_OK success
+ * @return others fail
  */
 esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
 
 /**
  * Clear and disable watchpoint.
  *
- * @param id watchpoint to clear [0..SOC_CPU_WATCHPOINT_NUM - 1]
+ * @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1]
  * 
- * @return ESP_ERR_INVALID_ARG invalid watchpoint id
- * @return ESP_ERR_NOT_SUPPORTED processor does not support watchpoints
  * @return ESP_OK success
+ * @return others fail
  */
 esp_err_t cpu_hal_clear_watchpoint(int id);
 
+#endif // SOC_CPU_WATCHPOINTS_NUM > 0
+
 #ifdef __cplusplus
 }
 #endif

components/soc/include/hal/mpu_hal.h

@@ -17,7 +17,10 @@
 #include "esp_err.h"
 
 #include "hal/mpu_types.h"
-#include "soc/mpu_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /**
  * Specify the type of access allowed on a memory region.
@@ -26,7 +29,11 @@
  * the region divisions is predefined in hardware which is likely reflected in LL implementation.
  * @param access type of access allowed
  * 
- * @return ESP_ERR_INVALID_ARG invalid id or access
  * @return ESP_OK success
+ * @return others fail
  */
 esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access);
+
+#ifdef __cplusplus
+}
+#endif

components/soc/include/hal/soc_hal.h

@@ -17,15 +17,37 @@
 #include <stdint.h>
 #include <stdbool.h>
 
+#include "hal/cpu_hal.h"
+#include "soc/soc_caps.h"
+
 #include "esp_err.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_CPU_CORES_NUM > 1
+
+// Utility functions for multicore targets
+#define __SOC_HAL_PERFORM_ON_OTHER_CORES(action)    { \
+                                                        for (int i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
+                                                            if (i != cur) { \
+                                                                action(i); \
+                                                            } \
+                                                        } \
+                                                    }
+
+#define SOC_HAL_STALL_OTHER_CORES()                 __SOC_HAL_PERFORM_ON_OTHER_CORES(soc_hal_stall_core);
+#define SOC_HAL_UNSTALL_OTHER_CORES()               __SOC_HAL_PERFORM_ON_OTHER_CORES(soc_hal_unstall_core);
+#define SOC_HAL_RESET_OTHER_CORES()                 __SOC_HAL_PERFORM_ON_OTHER_CORES(soc_hal_reset_core);
+
 /**
  * Stall the specified CPU core.
  *
  * @note Has no effect if the core is already stalled - does not return an
  * ESP_ERR_INVALID_STATE.
  *
- * @param core core to stall [0..SOC_CPU_CORES_NUM - 1]; if core < 0 is specified, all other cores are stalled
+ * @param core core to stall [0..SOC_CPU_CORES_NUM - 1]
  *
  * @return ESP_ERR_INVALID_ARG core argument invalid
  * @return ESP_OK success
@@ -38,19 +60,25 @@ esp_err_t soc_hal_stall_core(int core);
  * @note Has no effect if the core is already unstalled - does not return an
  * ESP_ERR_INVALID_STATE.
  *
- * @param core core to unstall [0..SOC_CPU_CORES_NUM - 1]; if core < 0 is specified, all other cores are unstalled
+ * @param core core to unstall [0..SOC_CPU_CORES_NUM - 1]
  *
  * @return ESP_ERR_INVALID_ARG core argument invalid
  * @return ESP_OK success
  */
 esp_err_t soc_hal_unstall_core(int core);
 
+#endif // SOC_CPU_CORES_NUM > 1
+
 /**
  * Reset the specified core.
  *
- * @param core core to reset [0..SOC_CPU_CORES_NUM - 1]; if core < 0 is specified, all other cores are reset
+ * @param core core to reset [0..SOC_CPU_CORES_NUM - 1]
  *
  * @return ESP_ERR_INVALID_ARG core argument invalid
  * @return ESP_OK success
  */
 esp_err_t soc_hal_reset_core(int core);
+
+#ifdef __cplusplus
+}
+#endif

components/soc/src/cpu_util.c

@@ -23,17 +23,22 @@
 #include "hal/cpu_types.h"
 
 #include "hal/soc_hal.h"
+#include "soc/soc_caps.h"
 
 #include "sdkconfig.h"
 
 void IRAM_ATTR esp_cpu_stall(int cpu_id)
 {
+#if SOC_CPU_CORES_NUM > 1
     soc_hal_stall_core(cpu_id);
+#endif
 }
 
 void IRAM_ATTR esp_cpu_unstall(int cpu_id)
 {
+#if SOC_CPU_CORES_NUM > 1
     soc_hal_unstall_core(cpu_id);
+#endif
 }
 
 void IRAM_ATTR esp_cpu_reset(int cpu_id)

components/soc/src/esp32/include/hal/mpu_ll.h

@@ -14,6 +14,8 @@
 
 #include <stdint.h>
 
+#include "soc/mpu_caps.h"
+
 #include "xt_instr_macros.h"
 
 #ifdef __cplusplus

components/soc/src/esp32s2/include/hal/mpu_ll.h

@@ -14,6 +14,8 @@
 
 #include <stdint.h>
 
+#include "soc/mpu_caps.h"
+
 #include "xt_instr_macros.h"
 
 #ifdef __cplusplus

components/soc/src/esp32s2/include/hal/soc_ll.h

@@ -21,20 +21,6 @@
 extern "C" {
 #endif
 
-static inline void soc_ll_stall_core(int core)
-{
-    CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
-    SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21 << RTC_CNTL_SW_STALL_PROCPU_C1_S);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
-    SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2 << RTC_CNTL_SW_STALL_PROCPU_C0_S);
-}
-
-static inline void soc_ll_unstall_core(int core)
-{
-    CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
-}
-
 static inline void soc_ll_reset_core(int core)
 {
     SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST_M);

components/soc/src/hal/cpu_hal.c

@@ -21,46 +21,30 @@
 
 #include "soc/cpu_caps.h"
 
+#if SOC_CPU_BREAKPOINTS_NUM > 0
 esp_err_t cpu_hal_set_breakpoint(int id, const void* addr)
 {
-#if SOC_CPU_BREAKPOINTS_NUM != 0
+    assert(id < SOC_CPU_BREAKPOINTS_NUM && id >= 0);
-    if (id >= SOC_CPU_BREAKPOINTS_NUM || id < 0) {
-        return ESP_ERR_INVALID_ARG;
-    }
-
     cpu_ll_set_breakpoint(id, cpu_ll_ptr_to_pc(addr));
-
     return ESP_OK;
-#else
-    return ESP_ERR_NOT_SUPPORTED;
-#endif
 }
 
 esp_err_t cpu_hal_clear_breakpoint(int id)
 {
-#if SOC_CPU_BREAKPOINTS_NUM > 0
+    assert(id < SOC_CPU_BREAKPOINTS_NUM && id >= 0);
-    if (id >= SOC_CPU_BREAKPOINTS_NUM || id < 0) {
-        return ESP_ERR_INVALID_ARG;
-    }
-
     cpu_ll_clear_breakpoint(id);
-
     return ESP_OK;
-#else
-    return ESP_ERR_NOT_SUPPORTED;
-#endif
 }
+#endif // SOC_CPU_BREAKPOINTS_NUM > 0
 
+#if SOC_CPU_WATCHPOINTS_NUM > 0
 esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger)
 {
-#if SOC_CPU_WATCHPOINTS_NUM > 0
+    assert(id < SOC_CPU_WATCHPOINTS_NUM && id >= 0);
-    if (id >= SOC_CPU_WATCHPOINTS_NUM || id < 0) {
+    assert(size <= SOC_CPU_WATCHPOINT_SIZE);
-        return ESP_ERR_INVALID_ARG;
+    assert(trigger == WATCHPOINT_TRIGGER_ON_RO || 
-    }
+           trigger == WATCHPOINT_TRIGGER_ON_WO ||
-
+           trigger == WATCHPOINT_TRIGGER_ON_RW);
-    if (size > SOC_CPU_WATCHPOINT_SIZE) {
-        return ESP_ERR_INVALID_ARG;
-    }
 
     bool on_read = false, on_write = false;
 
@@ -75,22 +59,12 @@ esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoi
     cpu_ll_set_watchpoint(id, addr, size, on_read, on_write);
 
     return ESP_OK;
-#else
-    return ESP_ERR_NOT_SUPPORTED;
-#endif
 }
 
 esp_err_t cpu_hal_clear_watchpoint(int id)
 {
-#if SOC_CPU_WATCHPOINTS_NUM > 0
+    assert(id < SOC_CPU_WATCHPOINTS_NUM && id >= 0);
-    if (id >= SOC_CPU_WATCHPOINTS_NUM || id < 0) {
-        return ESP_ERR_INVALID_ARG;
-    }
-
     cpu_ll_clear_watchpoint(id);
-
     return ESP_OK;
-#else
-    return ESP_ERR_NOT_SUPPORTED;
-#endif
 }
+#endif // SOC_CPU_WATCHPOINTS_NUM > 0

components/soc/src/hal/mpu_hal.c

@@ -21,11 +21,22 @@
 #include "hal/mpu_ll.h"
 #include "hal/mpu_types.h"
 
+#include "soc/mpu_caps.h"
+
 esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access)
 {
-    if (id > SOC_MPU_REGIONS_MAX_NUM || id < 0) {
+    assert(id < SOC_MPU_REGIONS_MAX_NUM && id >= 0);
-        return ESP_ERR_INVALID_ARG;
+    assert(
-    }
+#if SOC_MPU_REGION_RO_SUPPORTED
+           access == MPU_REGION_RO ||
+#endif
+#if SOC_MPU_REGION_WO_SUPPORTED
+           access == MPU_REGION_WO ||
+#endif
+           access == MPU_REGION_RW ||
+           access == MPU_REGION_X  ||
+           access == MPU_REGION_RWX ||
+           access == MPU_REGION_ILLEGAL);
 
     uint32_t addr = cpu_ll_id_to_addr(id);
 
@@ -51,7 +62,6 @@ esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access)
             mpu_ll_set_region_rwx(addr);
             break;
         default:
-            return ESP_ERR_INVALID_ARG;
             break;
     }
 

components/soc/src/hal/soc_hal.c

@@ -16,55 +16,31 @@
 
 #include "esp_err.h"
 
-#include "hal/cpu_hal.h"
 #include "hal/soc_hal.h"
 #include "hal/soc_ll.h"
 #include "soc/soc_caps.h"
 
-#define CHECK_CORE(core)                            { if ((core) > SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG; }
+#if SOC_CPU_CORES_NUM > 1
-#define PERFORM_ON_OTHER_CORES(action)              { \
-                                                        for (int i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
-                                                            if (i != cur) { \
-                                                                action(i); \
-                                                            } \
-                                                        } \
-                                                    }
 
 esp_err_t soc_hal_stall_core(int core)
 {
-    CHECK_CORE(core);
+    assert(core < SOC_CPU_CORES_NUM && core >= 0);
-
-    if (core < 0) {
-        PERFORM_ON_OTHER_CORES(soc_hal_stall_core);
-    } else {
     soc_ll_stall_core(core);
-    }
-
     return ESP_OK;
 }
 
 esp_err_t soc_hal_unstall_core(int core)
 {
-    CHECK_CORE(core);
+    assert(core < SOC_CPU_CORES_NUM && core >= 0);
-
-    if (core < 0) {
-        PERFORM_ON_OTHER_CORES(soc_hal_unstall_core);
-    } else {
     soc_ll_unstall_core(core);
-    }
-
     return ESP_OK;
 }
 
+#endif // SOC_CPU_CORES_NUM > 1
+
 esp_err_t soc_hal_reset_core(int core)
 {
-    CHECK_CORE(core);
+    assert(core < SOC_CPU_CORES_NUM && core >= 0);
-
-    if (core < 0) {
-        PERFORM_ON_OTHER_CORES(soc_hal_reset_core);
-    } else {
     soc_ll_reset_core(core);
-    }
-
     return ESP_OK;
 }