Merge branch 'feature/usb_host_collective_backport_v5.2' into 'release/v5.2'

USB Host: Collective backport to v5.2 See merge request espressif/esp-idf!28095
2026-05-19 23:45:28 +02:00 · 2024-02-20 18:51:26 +08:00
parent 98cbd1fd72 471fe41828
commit 7fafe4a9f4
58 changed files with 1659 additions and 1741 deletions
@@ -234,6 +234,12 @@ if(NOT BOOTLOADER_BUILD)
        list(APPEND srcs "huk_hal.c")
    endif()

+    if(CONFIG_SOC_USB_OTG_SUPPORTED)
+        list(APPEND srcs
+                    "usb_dwc_hal.c"
+                    "usb_fsls_phy_hal.c")
+    endif()
+
    if(${target} STREQUAL "esp32")
        list(APPEND srcs
            "touch_sensor_hal.c"
@@ -244,23 +250,17 @@ if(NOT BOOTLOADER_BUILD)
    if(${target} STREQUAL "esp32s2")
        list(APPEND srcs
                    "touch_sensor_hal.c"
-                    "usb_hal.c"
-                    "usb_phy_hal.c"
                    "xt_wdt_hal.c"
                    "esp32s2/cp_dma_hal.c"
-                    "esp32s2/touch_sensor_hal.c"
-                    "usb_dwc_hal.c")
+                    "esp32s2/touch_sensor_hal.c")
    endif()

    if(${target} STREQUAL "esp32s3")
        list(APPEND srcs
            "touch_sensor_hal.c"
-            "usb_hal.c"
-            "usb_phy_hal.c"
            "xt_wdt_hal.c"
            "esp32s3/touch_sensor_hal.c"
-            "esp32s3/rtc_cntl_hal.c"
-            "usb_dwc_hal.c")
+            "esp32s3/rtc_cntl_hal.c")
    endif()

    if(${target} STREQUAL "esp32c3")
@@ -17,7 +17,7 @@ extern "C" {
 *
 * @param hw Start address of the USB Serial_JTAG registers
 */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
    // USB_Serial_JTAG use internal PHY
    hw->conf0.phy_sel = 0;
@@ -17,7 +17,7 @@ extern "C" {
 *
 * @param hw Start address of the USB Serial_JTAG registers
 */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
    // USB_Serial_JTAG use internal PHY
    hw->conf0.phy_sel = 0;
@@ -17,7 +17,7 @@ extern "C" {
 *
 * @param hw Start address of the USB Serial_JTAG registers
 */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
    // USB_Serial_JTAG use internal PHY
    hw->conf0.phy_sel = 0;
@@ -21,7 +21,7 @@ extern "C" {
 *
 * @param hw Start address of the USB Wrap registers
 */
-static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
 {
    hw->otg_conf.phy_sel = 0;
 }
@@ -31,7 +31,7 @@ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
 *
 * @param hw Start address of the USB Wrap registers
 */
-static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
 {
    //Enable external PHY
    hw->otg_conf.phy_sel = 1;
@@ -46,7 +46,7 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
 * @param dm_pu D- pullup load
 * @param dm_pd D- pulldown load
 */
-static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
+static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
 {
    usb_wrap_otg_conf_reg_t conf;
    conf.val = hw->otg_conf.val;
@@ -63,7 +63,7 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
 * @param hw     Start address of the USB Wrap registers
 * @param pad_en Enable the PHY control to D+/D- pad
 */
-static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
+static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
 {
    hw->otg_conf.pad_enable = pad_en;
 }
@@ -74,7 +74,7 @@ static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_e
 * @param hw Start address of the USB Wrap registers
 * @param en Whether to enable the internal PHY's test mode
 */
-static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
+static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
 {
    if (en) {
        // Clear USB_WRAP_TEST_CONF_REG
@@ -92,25 +92,25 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
 * Enable the bus clock for USB Wrap module
 * @param clk_en True if enable the clock of USB Wrap module
 */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
 {
    REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en);
 }

 // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
-#define usb_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
+#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)

 /**
 * @brief Reset the USB Wrap module
 */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
 {
    REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1);
    REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0);
 }

 // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
-#define usb_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
+#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__)

 #ifdef __cplusplus
 }
@@ -1,43 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#include "soc/soc.h"
-#include "soc/system_reg.h"
-#include "soc/gpio_sig_map.h"
-#include "soc/usb_periph.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static inline void usb_ll_int_phy_enable(void)
-{
-    USB_WRAP.otg_conf.pad_enable = 1;
-    USB_WRAP.otg_conf.phy_sel = 0;
-}
-
-static inline void usb_ll_ext_phy_enable(void)
-{
-    USB_WRAP.otg_conf.pad_enable = 1;
-    USB_WRAP.otg_conf.phy_sel = 1;
-}
-
-static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
-{
-    usb_wrap_otg_conf_reg_t conf;
-    conf.val = USB_WRAP.otg_conf.val;
-    conf.pad_pull_override = 1;
-    conf.dp_pullup = dp_pu;
-    conf.dp_pulldown = dp_pd;
-    conf.dm_pullup = dm_pu;
-    conf.dm_pulldown = dm_pd;
-    USB_WRAP.otg_conf.val = conf.val;
-}
-
-#ifdef __cplusplus
-}
-#endif
@@ -23,7 +23,7 @@ extern "C" {
 *
 * @param hw Start address of the USB Wrap registers
 */
-static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
 {
    // USB_OTG use internal PHY
    hw->otg_conf.phy_sel = 0;
@@ -38,7 +38,7 @@ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
 *
 * @param hw Start address of the USB Wrap registers
 */
-static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
 {
    // USB_OTG use external PHY
    hw->otg_conf.phy_sel = 1;
@@ -53,7 +53,7 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
 *
 * @param hw Start address of the USB Serial_JTAG registers
 */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
    // USB_Serial_JTAG use internal PHY
    hw->conf0.phy_sel = 0;
@@ -74,7 +74,7 @@ static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 *
 * @param hw Start address of the USB Serial_JTAG registers
 */
-static inline void usb_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
    // USB_Serial_JTAG use external PHY
    hw->conf0.phy_sel = 1;
@@ -93,7 +93,7 @@ static inline void usb_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
 * @param dm_pu D- pullup load
 * @param dm_pd D- pulldown load
 */
-static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
+static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
 {
    usb_wrap_otg_conf_reg_t conf;
    conf.val = hw->otg_conf.val;
@@ -112,7 +112,7 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
 * @param hw     Start address of the USB Wrap registers
 * @param pad_en Enable the PHY control to D+/D- pad
 */
-static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
+static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
 {
    hw->otg_conf.pad_enable = pad_en;
 }
@@ -123,7 +123,7 @@ static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_e
 * @param hw Start address of the USB Wrap registers
 * @param en Whether to enable the internal PHY's test mode
 */
-static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
+static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
 {
    if (en) {
        // Clear USB_WRAP_TEST_CONF_REG
@@ -141,25 +141,25 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
 * Enable the bus clock for USB Wrap module
 * @param clk_en True if enable the clock of USB Wrap module
 */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
 {
    SYSTEM.perip_clk_en0.usb_clk_en = clk_en;
 }

 // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
-#define usb_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
+#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)

 /**
 * @brief Reset the USB Wrap module
 */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
 {
    SYSTEM.perip_rst_en0.usb_rst = 1;
    SYSTEM.perip_rst_en0.usb_rst = 0;
 }

 // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
-#define usb_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
+#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__)

 #ifdef __cplusplus
 }
@@ -1,55 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#include "soc/soc.h"
-#include "soc/system_reg.h"
-#include "soc/gpio_sig_map.h"
-#include "soc/usb_periph.h"
-#include "soc/rtc_cntl_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static inline void usb_ll_int_phy_enable(void)
-{
-    USB_WRAP.otg_conf.pad_enable = 1;
-    // USB_OTG use internal PHY
-    USB_WRAP.otg_conf.phy_sel = 0;
-    // phy_sel is controlled by the following register value
-    RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
-    // phy_sel=sw_usb_phy_sel=1, USB_OTG is connected with internal PHY
-    RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
-}
-
-static inline void usb_ll_ext_phy_enable(void)
-{
-    USB_WRAP.otg_conf.pad_enable = 1;
-    // USB_OTG use external PHY
-    USB_WRAP.otg_conf.phy_sel = 1;
-    // phy_sel is controlled by the following register value
-    RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
-    // phy_sel=sw_usb_phy_sel=0, USB_OTG is connected with external PHY through GPIO Matrix
-    RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
-}
-
-static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
-{
-    usb_wrap_otg_conf_reg_t conf;
-    conf.val = USB_WRAP.otg_conf.val;
-
-    conf.pad_pull_override = 1;
-    conf.dp_pullup = dp_pu;
-    conf.dp_pulldown = dp_pd;
-    conf.dm_pullup = dm_pu;
-    conf.dm_pulldown = dm_pd;
-    USB_WRAP.otg_conf.val = conf.val;
-}
-
-#ifdef __cplusplus
-}
-#endif
@@ -6,25 +6,23 @@

 #pragma once

+#include "soc/soc_caps.h"
+/*
+This header is shared across all targets. Resolve to an empty header for targets
+that don't support USB OTG.
+*/
+#if SOC_USB_OTG_SUPPORTED
+#include <stdint.h>
+#include <stdbool.h>
+#include "hal/usb_dwc_ll.h"
+#include "hal/usb_dwc_types.h"
+#include "hal/assert.h"
+#endif // SOC_USB_OTG_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif

-/*
-NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL
-      functions must be called from critical sections unless specified otherwise
-*/
-
-#include <stdlib.h>
-#include <stddef.h>
-#include "soc/soc_caps.h"
-#if SOC_USB_OTG_SUPPORTED
-#include "soc/usb_dwc_struct.h"
-#include "hal/usb_dwc_ll.h"
-#endif
-#include "hal/usb_dwc_types.h"
-#include "hal/assert.h"
-
 #if SOC_USB_OTG_SUPPORTED

 // ------------------------------------------------ Macros and Types ---------------------------------------------------
@@ -142,7 +140,7 @@ typedef struct {
        uint32_t val;
    };
    struct {
-        usb_hal_interval_t interval;        /**< The interval of the endpoint */
+        unsigned int interval;              /**< The interval of the endpoint in frames (FS) or microframes (HS) */
        uint32_t phase_offset_frames;       /**< Phase offset in number of frames */
    } periodic;     /**< Characteristic for periodic (interrupt/isochronous) endpoints only */
 } usb_dwc_hal_ep_char_t;
@@ -178,7 +176,7 @@ typedef struct {
    uint32_t *periodic_frame_list;                 /**< Pointer to scheduling frame list */
    usb_hal_frame_list_len_t frame_list_len;       /**< Length of the periodic scheduling frame list */
    //FIFO related
-    const usb_dwc_hal_fifo_config_t *fifo_config;  /**< FIFO sizes configuration */
+    usb_dwc_hal_fifo_config_t fifo_config;         /**< FIFO sizes configuration */
    union {
        struct {
            uint32_t dbnc_lock_enabled: 1;      /**< Debounce lock enabled */
@@ -193,7 +191,7 @@ typedef struct {
    struct {
        int num_allocd;                             /**< Number of channels currently allocated */
        uint32_t chan_pend_intrs_msk;               /**< Bit mask of channels with pending interrupts */
-        usb_dwc_hal_chan_t *hdls[USB_DWC_NUM_HOST_CHAN];    /**< Handles of each channel. Set to NULL if channel has not been allocated */
+        usb_dwc_hal_chan_t *hdls[OTG_NUM_HOST_CHAN];    /**< Handles of each channel. Set to NULL if channel has not been allocated */
    } channels;
 } usb_dwc_hal_context_t;

@@ -1,24 +1,30 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #pragma once

+#include "soc/soc_caps.h"
+/*
+This header is shared across all targets. Resolve to an empty header for targets
+that don't support USB OTG.
+*/
+#if SOC_USB_OTG_SUPPORTED
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/usb_dwc_struct.h"
+#include "soc/usb_dwc_cfg.h"
+#include "hal/usb_dwc_types.h"
+#include "hal/misc.h"
+#endif // SOC_USB_OTG_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif

-#include <stdint.h>
-#include <stdbool.h>
-#include "soc/soc_caps.h"
 #if SOC_USB_OTG_SUPPORTED
-#include "soc/usb_dwc_struct.h"
-#endif
-#include "hal/usb_dwc_types.h"
-#include "hal/misc.h"
-

 /* -----------------------------------------------------------------------------
 --------------------------------- DWC Constants --------------------------------
@@ -26,88 +32,6 @@ extern "C" {

 #define USB_DWC_QTD_LIST_MEM_ALIGN              512
 #define USB_DWC_FRAME_LIST_MEM_ALIGN            512     // The frame list needs to be 512 bytes aligned (contrary to the databook)
-/*
-Although we have a 256 lines, only 200 lines are useable due to EPINFO_CTL.
-Todo: Check sizes again and express this macro in terms of DWC config options (IDF-7384)
-*/
-#define USB_DWC_FIFO_TOTAL_USABLE_LINES         200
-
-/* -----------------------------------------------------------------------------
------------------------------ DWC Configuration -------------------------------
----------------------------------------------------------------------------- */
-
-/**
- * @brief Default FIFO sizes (see 2.1.2.4 for programming guide)
- *
- * RXFIFO
- * - Recommended: ((LPS/4) * 2) + 2
- * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104
- * - Worst case can accommodate two packets of 204 bytes, or one packet of 408
- * NPTXFIFO
- * - Recommended: (LPS/4) * 2
- * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48
- * - Worst case can accommodate three packets of 64 bytes or one packet of 192
- * PTXFIFO
- * - Recommended: (LPS/4) * 2
- * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 3 = 48
- * - Worst case can accommodate three packets of 64 bytes or one packet of 192
- */
-#define USB_DWC_FIFO_RX_LINES_DEFAULT    104
-#define USB_DWC_FIFO_NPTX_LINES_DEFAULT  48
-#define USB_DWC_FIFO_PTX_LINES_DEFAULT   48
-
-/**
- * @brief FIFO sizes that bias to giving RX FIFO more capacity
- *
- * RXFIFO
- * - Recommended: ((LPS/4) * 2) + 2
- * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152
- * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes
- * NPTXFIFO
- * - Recommended: (LPS/4) * 2
- * - Actual: Assume LPS is 64, and 1 packets: (64/4) * 1 = 16
- * - Worst case can accommodate one packet of 64 bytes
- * PTXFIFO
- * - Recommended: (LPS/4) * 2
- * - Actual: Assume LPS is 64, and 3 packets: (64/4) * 2 = 32
- * - Worst case can accommodate two packets of 64 bytes or one packet of 128
- */
-#define USB_DWC_FIFO_RX_LINES_BIASRX     152
-#define USB_DWC_FIFO_NPTX_LINES_BIASRX   16
-#define USB_DWC_FIFO_PTX_LINES_BIASRX    32
-
-/**
- * @brief FIFO sizes that bias to giving Periodic TX FIFO more capacity (i.e., ISOC OUT)
- *
- * RXFIFO
- * - Recommended: ((LPS/4) * 2) + 2
- * - Actual: Assume LPS is 64, and 2 packets: ((64/4) * 2) + 2 = 34
- * - Worst case can accommodate two packets of 64 bytes or one packet of 128
- * NPTXFIFO
- * - Recommended: (LPS/4) * 2
- * - Actual: Assume LPS is 64, and 1 packets: (64/4) * 1 = 16
- * - Worst case can accommodate one packet of 64 bytes
- * PTXFIFO
- * - Recommended: (LPS/4) * 2
- * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150
- * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes
- */
-#define USB_DWC_FIFO_RX_LINES_BIASTX     34
-#define USB_DWC_FIFO_NPTX_LINES_BIASTX   16
-#define USB_DWC_FIFO_PTX_LINES_BIASTX    150
-
-
-/*
- * List of relevant DWC configurations. See DWC OTG databook Chapter 3 for more
- * details.
- */
-#define USB_DWC_FSPHY_INTERFACE             1
-#define USB_DWC_NUM_EPS                     6
-#define USB_DWC_NUM_IN_EPS                  5       // Todo: Add check for when number of IN channels exceeds limit (IDF-8556)
-#define USB_DWC_NUM_HOST_CHAN               8
-#define USB_DWC_DFIFO_DEPTH                 256
-#define USB_DWC_RX_DFIFO_DEPTH              256
-#define USB_DWC_TX_DFIFO_DEPTH              256     // Same value applies to HNPERIO, NPERIO, HPERIO, and DINEP

 /* -----------------------------------------------------------------------------
 ------------------------------- Global Registers -------------------------------
@@ -187,7 +111,6 @@ Todo: Check sizes again and express this macro in terms of DWC config options (I
 #define USB_DWC_LL_INTR_CHAN_CHHLTD         (1 << 1)
 #define USB_DWC_LL_INTR_CHAN_XFERCOMPL      (1 << 0)

-#if SOC_USB_OTG_SUPPORTED
 /*
 * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
 * Each QTD describes one transfer. Scatter gather mode will automatically split
@@ -857,28 +780,48 @@ static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs

 static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, ntd, qtd_list_len - 1);    //Set the length of the descriptor list
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    //Set the length of the descriptor list. NTD occupies xfersize[15:8]
+    hctsiz.xfersize &= ~(0xFF << 8);
+    hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8;
+    chan->hctsiz_reg.val = hctsiz.val;
 }

 static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
 {
-    chan->hctsiz_reg.dopng = 0;         //Don't do ping
-    HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, sched_info, 0xFF); //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    hctsiz.dopng = 0;         //Don't do ping
+    /*
+    Set SCHED_INFO which occupies xfersize[7:0]
+    It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels
+    */
+    hctsiz.xfersize |= 0xFF;
+    chan->hctsiz_reg.val = hctsiz.val;
 }

 // ---------------------------- HCDMAi Register --------------------------------

 static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
 {
-    //Set HCDMAi
-    chan->hcdma_reg.val = 0;
-    chan->hcdma_reg.non_iso.dmaaddr = (((uint32_t)dmaaddr) >> 9) & 0x7FFFFF;  //MSB of 512 byte aligned address
-    chan->hcdma_reg.non_iso.ctd = qtd_idx;
+    usb_dwc_hcdma_reg_t hcdma;
+    /*
+    Set the base address portion of the field which is dmaaddr[31:9]. This is
+    the based address of the QTD list and must be 512 bytes aligned
+    */
+    hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00;
+    //Set the current QTD index in the QTD list which is dmaaddr[8:3]
+    hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3;
+    //dmaaddr[2:0] is reserved thus doesn't not need to be set
+
+    chan->hcdma_reg.val = hcdma.val;
 }

 static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan)
 {
-    return chan->hcdma_reg.non_iso.ctd;
+    //The current QTD index is dmaaddr[8:3]
+    return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F;
 }

 // ---------------------------- HCDMABi Register -------------------------------
@@ -998,7 +941,7 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem
    qtd->buffer_status_val = 0;
 }

-#endif
+#endif // SOC_USB_OTG_SUPPORTED

 #ifdef __cplusplus
 }
@@ -51,19 +51,6 @@ typedef enum {
    USB_HAL_FRAME_LIST_LEN_64 = 64,
 } usb_hal_frame_list_len_t;

-/**
- * @brief Support intervals in number of USB frames (i.e., 1ms)
- */
-typedef enum {
-    USB_HAL_INTERVAL_1 = 1,
-    USB_HAL_INTERVAL_2 = 2,
-    USB_HAL_INTERVAL_4 = 4,
-    USB_HAL_INTERVAL_8 = 8,
-    USB_HAL_INTERVAL_16 = 16,
-    USB_HAL_INTERVAL_32 = 32,
-    USB_HAL_INTERVAL_64 = 64,
-} usb_hal_interval_t;
-
 #ifdef __cplusplus
 }
 #endif
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -31,7 +31,7 @@ typedef struct {
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
    usb_serial_jtag_dev_t *jtag_dev;            /**< Pointer to base address of USB Serial JTAG registers */
 #endif
-} usb_phy_hal_context_t;
+} usb_fsls_phy_hal_context_t;


 /**
@@ -39,7 +39,7 @@ typedef struct {
 *
 * @param hal Context of the HAL layer
 */
-void usb_phy_hal_init(usb_phy_hal_context_t *hal);
+void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal);

 /**
 * @brief Configure internal/external PHY for USB_OTG
@@ -47,7 +47,7 @@ void usb_phy_hal_init(usb_phy_hal_context_t *hal);
 * @param hal Context of the HAL layer
 * @param phy_target USB PHY target
 */
-void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target);
+void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target);

 #if SOC_USB_SERIAL_JTAG_SUPPORTED
 /**
@@ -56,7 +56,7 @@ void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targe
 * @param hal Context of the HAL layer
 * @param phy_target USB PHY target
 */
-void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target);
+void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target);
 #endif

 /**
@@ -64,7 +64,7 @@ void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targ
 *
 * @param hal Context of the HAL layer
 */
-void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
+void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal);

 /**
 * @brief Configure pullup/pulldown loads for the D+/D- as a device
@@ -72,7 +72,7 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
 * @param hal Context of the HAL layer
 * @param speed USB speed
 */
-void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed);
+void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed);

 /**
 * @brief Enable/Disable test mode for internal PHY to mimick host-device disconnection
@@ -80,7 +80,7 @@ void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t s
 * @param hal Context of the HAL layer
 * @param disconn Whether to disconnect
 */
-void usb_phy_hal_int_mimick_disconn(usb_phy_hal_context_t *hal, bool disconn);
+void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn);

 #endif

@@ -1,25 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#pragma once
-
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    bool use_external_phy;
-} usb_hal_context_t;
-
-void usb_hal_init(usb_hal_context_t *usb);
-
-
-#ifdef __cplusplus
-}
-#endif
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -9,9 +9,9 @@
 #include <string.h>
 #include "sdkconfig.h"
 #include "soc/chip_revision.h"
-#include "hal/efuse_hal.h"
 #include "hal/usb_dwc_hal.h"
 #include "hal/usb_dwc_ll.h"
+#include "hal/efuse_hal.h"
 #include "hal/assert.h"

 // ------------------------------------------------ Macros and Types ---------------------------------------------------
@@ -21,40 +21,7 @@
 #define BENDPOINTADDRESS_NUM_MSK     0x0F   //Endpoint number mask of the bEndpointAddress field of an endpoint descriptor
 #define BENDPOINTADDRESS_DIR_MSK     0x80   //Endpoint direction mask of the bEndpointAddress field of an endpoint descriptor

-#define CORE_REG_GSNPSID    0x4F54400A
-#define CORE_REG_GHWCFG1    0x00000000
-#define CORE_REG_GHWCFG2    0x224DD930
-#define CORE_REG_GHWCFG3    0x00C804B5
-#define CORE_REG_GHWCFG4    0xD3F0A030
-
-// ----------------------- Configs -------------------------
-
-/**
- * @brief Default FIFO sizes (see 2.1.2.4 for programming guide)
- */
-const usb_dwc_hal_fifo_config_t fifo_config_default = {
-    .rx_fifo_lines =   USB_DWC_FIFO_RX_LINES_DEFAULT,
-    .nptx_fifo_lines = USB_DWC_FIFO_NPTX_LINES_DEFAULT,
-    .ptx_fifo_lines =  USB_DWC_FIFO_PTX_LINES_DEFAULT,
-};
-
-/**
- * @brief FIFO sizes that bias to giving RX FIFO more capacity
- */
-const usb_dwc_hal_fifo_config_t fifo_config_bias_rx = {
-    .rx_fifo_lines = USB_DWC_FIFO_RX_LINES_BIASRX,
-    .nptx_fifo_lines = USB_DWC_FIFO_NPTX_LINES_BIASRX,
-    .ptx_fifo_lines = USB_DWC_FIFO_PTX_LINES_BIASRX,
-};
-
-/**
- * @brief FIFO sizes that bias to giving Periodic TX FIFO more capacity (i.e., ISOC OUT)
- */
-const usb_dwc_hal_fifo_config_t fifo_config_bias_ptx = {
-    .rx_fifo_lines = USB_DWC_FIFO_RX_LINES_BIASTX,
-    .nptx_fifo_lines = USB_DWC_FIFO_NPTX_LINES_BIASTX,
-    .ptx_fifo_lines = USB_DWC_FIFO_PTX_LINES_BIASTX,
-};
+#define CORE_REG_GSNPSID    0x4F54400A      //Release number of USB_DWC used in Espressif's SoCs

 // -------------------- Configurable -----------------------

@@ -188,42 +155,69 @@ void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal)
    hal->flags.val = 0;
    hal->channels.num_allocd = 0;
    hal->channels.chan_pend_intrs_msk = 0;
-    memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_NUM_HOST_CHAN);
+    memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * OTG_NUM_HOST_CHAN);
 }

 void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bias_t fifo_bias)
 {
-    const usb_dwc_hal_fifo_config_t *fifo_config;
+    /*
+    * EPINFO_CTL is located at the end of FIFO, its size is fixed in HW.
+    * The reserved size is always the worst-case, which is device mode that requires 4 locations per EP direction (including EP0).
+    * Here we just read the FIFO size from HW register, to avoid any ambivalence
+    */
+    uint32_t ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4;
+    usb_dwc_ll_ghwcfg_get_hw_config(hal->dev, &ghwcfg1, &ghwcfg2, &ghwcfg3, &ghwcfg4);
+    const uint16_t fifo_size_lines = ((usb_dwc_ghwcfg3_reg_t)ghwcfg3).dfifodepth;
+
+    /*
+    * Recommended FIFO sizes (see 2.1.2.4 for programming guide)
+    *
+    * RXFIFO:   ((LPS/4) * 2) + 2
+    * NPTXFIFO: (LPS/4) * 2
+    * PTXFIFO:  (LPS/4) * 2
+    *
+    * Recommended sizes fit 2 packets of each type. For S2 and S3 we can't fit even one MPS ISOC packet (1023 FS and 1024 HS).
+    * So the calculations below are compromises between the available FIFO size and optimal performance.
+    */
+    usb_dwc_hal_fifo_config_t fifo_config;
    switch (fifo_bias) {
+        // Define minimum viable (fits at least 1 MPS) FIFO sizes for non-biased FIFO types
+        // Allocate the remaining size to the biased FIFO type
        case USB_HAL_FIFO_BIAS_DEFAULT:
-            fifo_config = &fifo_config_default;
+            fifo_config.nptx_fifo_lines = OTG_DFIFO_DEPTH / 4;
+            fifo_config.ptx_fifo_lines  = OTG_DFIFO_DEPTH / 8;
+            fifo_config.rx_fifo_lines   = fifo_size_lines - fifo_config.ptx_fifo_lines - fifo_config.nptx_fifo_lines;
            break;
        case USB_HAL_FIFO_BIAS_RX:
-            fifo_config = &fifo_config_bias_rx;
+            fifo_config.nptx_fifo_lines = OTG_DFIFO_DEPTH / 16;
+            fifo_config.ptx_fifo_lines  = OTG_DFIFO_DEPTH / 8;
+            fifo_config.rx_fifo_lines   = fifo_size_lines - fifo_config.ptx_fifo_lines - fifo_config.nptx_fifo_lines;
            break;
        case USB_HAL_FIFO_BIAS_PTX:
-            fifo_config = &fifo_config_bias_ptx;
+            fifo_config.rx_fifo_lines   = OTG_DFIFO_DEPTH / 8 + 2; // 2 extra lines are allocated for status information. See USB-OTG Programming Guide, chapter 2.1.2.1
+            fifo_config.nptx_fifo_lines = OTG_DFIFO_DEPTH / 16;
+            fifo_config.ptx_fifo_lines  = fifo_size_lines - fifo_config.nptx_fifo_lines - fifo_config.rx_fifo_lines;
            break;
        default:
            abort();
    }

-    HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_FIFO_TOTAL_USABLE_LINES);
+    HAL_ASSERT((fifo_config.rx_fifo_lines + fifo_config.nptx_fifo_lines + fifo_config.ptx_fifo_lines) <= fifo_size_lines);
    //Check that none of the channels are active
-    for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) {
+    for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) {
        if (hal->channels.hdls[i] != NULL) {
            HAL_ASSERT(!hal->channels.hdls[i]->flags.active);
        }
    }
    //Set the new FIFO lengths
-    usb_dwc_ll_grxfsiz_set_fifo_size(hal->dev, fifo_config->rx_fifo_lines);
-    usb_dwc_ll_gnptxfsiz_set_fifo_size(hal->dev, fifo_config->rx_fifo_lines, fifo_config->nptx_fifo_lines);
-    usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(hal->dev, fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines, fifo_config->ptx_fifo_lines);
+    usb_dwc_ll_grxfsiz_set_fifo_size(hal->dev, fifo_config.rx_fifo_lines);
+    usb_dwc_ll_gnptxfsiz_set_fifo_size(hal->dev, fifo_config.rx_fifo_lines, fifo_config.nptx_fifo_lines);
+    usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(hal->dev, fifo_config.rx_fifo_lines + fifo_config.nptx_fifo_lines, fifo_config.ptx_fifo_lines);
    //Flush the FIFOs
    usb_dwc_ll_grstctl_flush_nptx_fifo(hal->dev);
    usb_dwc_ll_grstctl_flush_ptx_fifo(hal->dev);
    usb_dwc_ll_grstctl_flush_rx_fifo(hal->dev);
-    hal->fifo_config = fifo_config;
+    hal->fifo_config = fifo_config; // Implicit struct copy
    hal->flags.fifo_sizes_set = 1;
 }

@@ -232,7 +226,7 @@ void usb_dwc_hal_get_mps_limits(usb_dwc_hal_context_t *hal, usb_hal_fifo_mps_lim
    HAL_ASSERT(hal && mps_limits);
    HAL_ASSERT(hal->flags.fifo_sizes_set);

-    const usb_dwc_hal_fifo_config_t *fifo_config = hal->fifo_config;
+    const usb_dwc_hal_fifo_config_t *fifo_config = &(hal->fifo_config);
    mps_limits->in_mps = (fifo_config->rx_fifo_lines - 2) * 4; // Two lines are reserved for status quadlets internally by USB_DWC
    mps_limits->non_periodic_out_mps = fifo_config->nptx_fifo_lines * 4;
    mps_limits->periodic_out_mps = fifo_config->ptx_fifo_lines * 4;
@@ -264,11 +258,11 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan
 {
    HAL_ASSERT(hal->flags.fifo_sizes_set);  //FIFO sizes should be set befor attempting to allocate a channel
    //Attempt to allocate channel
-    if (hal->channels.num_allocd == USB_DWC_NUM_HOST_CHAN) {
+    if (hal->channels.num_allocd == OTG_NUM_HOST_CHAN) {
        return false;    //Out of free channels
    }
    int chan_idx = -1;
-    for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) {
+    for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) {
        if (hal->channels.hdls[i] == NULL) {
            hal->channels.hdls[i] = chan_obj;
            chan_idx = i;
@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hal/usb_fsls_phy_ll.h"
+#include "hal/usb_fsls_phy_hal.h"
+
+void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal)
+{
+    hal->wrap_dev = &USB_WRAP;
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
+    hal->jtag_dev = &USB_SERIAL_JTAG;
+#endif
+}
+
+void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
+{
+    if (phy_target == USB_PHY_TARGET_EXT) {
+        usb_fsls_phy_ll_ext_otg_enable(hal->wrap_dev);
+    } else if (phy_target == USB_PHY_TARGET_INT) {
+        usb_fsls_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
+        usb_fsls_phy_ll_int_otg_enable(hal->wrap_dev);
+    }
+}
+
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
+void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
+{
+    if (phy_target == USB_PHY_TARGET_EXT) {
+        usb_fsls_phy_ll_ext_jtag_enable(hal->jtag_dev);
+    } else if (phy_target == USB_PHY_TARGET_INT) {
+        usb_fsls_phy_ll_int_jtag_enable(hal->jtag_dev);
+    }
+}
+#endif
+
+void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal)
+{
+    // HOST - upstream: dp_pd = 1, dm_pd = 1
+    usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
+}
+
+void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed)
+{
+    // DEVICE - downstream
+    if (speed == USB_PHY_SPEED_LOW) {
+        // LS: dm_pu = 1
+        usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
+    } else {
+        // FS: dp_pu = 1
+        usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
+    }
+}
+
+void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn)
+{
+    /*
+    We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will:
+    A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection.
+    */
+    usb_fsls_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
+}
@@ -1,18 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#include "hal/usb_ll.h"
-#include "hal/usb_hal.h"
-
-void usb_hal_init(usb_hal_context_t *usb)
-{
-    if (usb->use_external_phy) {
-        usb_ll_ext_phy_enable();
-    } else {
-        usb_ll_int_phy_enable();
-    }
-}
@@ -1,64 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "hal/usb_phy_ll.h"
-#include "hal/usb_phy_hal.h"
-
-void usb_phy_hal_init(usb_phy_hal_context_t *hal)
-{
-    hal->wrap_dev = &USB_WRAP;
-#if SOC_USB_SERIAL_JTAG_SUPPORTED
-    hal->jtag_dev = &USB_SERIAL_JTAG;
-#endif
-}
-
-void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target)
-{
-    if (phy_target == USB_PHY_TARGET_EXT) {
-        usb_phy_ll_ext_otg_enable(hal->wrap_dev);
-    } else if (phy_target == USB_PHY_TARGET_INT) {
-        usb_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
-        usb_phy_ll_int_otg_enable(hal->wrap_dev);
-    }
-}
-
-#if SOC_USB_SERIAL_JTAG_SUPPORTED
-void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target)
-{
-    if (phy_target == USB_PHY_TARGET_EXT) {
-        usb_phy_ll_ext_jtag_enable(hal->jtag_dev);
-    } else if (phy_target == USB_PHY_TARGET_INT) {
-        usb_phy_ll_int_jtag_enable(hal->jtag_dev);
-    }
-}
-#endif
-
-void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal)
-{
-    // HOST - upstream: dp_pd = 1, dm_pd = 1
-    usb_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
-}
-
-void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed)
-{
-    // DEVICE - downstream
-    if (speed == USB_PHY_SPEED_LOW) {
-        // LS: dm_pu = 1
-        usb_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
-    } else {
-        // FS: dp_pu = 1
-        usb_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
-    }
-}
-
-void usb_phy_hal_int_mimick_disconn(usb_phy_hal_context_t *hal, bool disconn)
-{
-    /*
-    We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will:
-    A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection.
-    */
-    usb_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
-}