diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
index e1eec5bcd8..1e2b4ce501 100644
--- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
+++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
@@ -103,33 +103,10 @@ static inline void bootloader_hardware_init(void)
 
 static inline void bootloader_ana_reset_config(void)
 {
-    // TODO: IDF-5990 copied from C3, need update
-    // Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
-    /*
-      For origin chip & ECO1: only support swt reset;
-      For ECO2: fix brownout reset bug, support swt & brownout reset;
-      For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
-    */
-    uint8_t chip_version = efuse_hal_get_minor_chip_version();
-    switch (chip_version) {
-        case 0:
-        case 1:
-            //Disable BOR and GLITCH reset
-            bootloader_ana_bod_reset_config(false);
-            bootloader_ana_clock_glitch_reset_config(false);
-            break;
-        case 2:
-            //Enable BOR reset. Disable GLITCH reset
-            bootloader_ana_bod_reset_config(true);
-            bootloader_ana_clock_glitch_reset_config(false);
-            break;
-        case 3:
-        default:
-            //Enable BOR, and GLITCH reset
-            bootloader_ana_bod_reset_config(true);
-            bootloader_ana_clock_glitch_reset_config(true);
-            break;
-    }
+    //Enable super WDT reset.
+    bootloader_ana_super_wdt_reset_config(true);
+    //Enable BOD reset
+    bootloader_ana_bod_reset_config(true);
 }
 
 esp_err_t bootloader_init(void)
diff --git a/components/bootloader_support/src/esp32c6/bootloader_soc.c b/components/bootloader_support/src/esp32c6/bootloader_soc.c
index 77a8d2176a..66358dd3fa 100644
--- a/components/bootloader_support/src/esp32c6/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c6/bootloader_soc.c
@@ -1,15 +1,24 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <stdbool.h>
+#include <assert.h>
 #include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
 
+void bootloader_ana_super_wdt_reset_config(bool enable)
+{
+    //C6 doesn't support bypass super WDT reset
+    assert(enable);
+    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
+}
+
 void bootloader_ana_bod_reset_config(bool enable)
 {
-    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
+    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
+
     if (enable) {
         REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
     } else {
@@ -17,12 +26,8 @@ void bootloader_ana_bod_reset_config(bool enable)
     }
 }
 
+//Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
-    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
-    if (enable) {
-        REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
-    } else {
-        REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
-    }
+    (void)enable;
 }
diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
index 5de830031f..6fcdfcc8c4 100644
--- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
@@ -93,33 +93,10 @@ static inline void bootloader_hardware_init(void)
 
 static inline void bootloader_ana_reset_config(void)
 {
-    // TODO: IDF-5990 copied from C6, need update
-    // Have removed bootloader_ana_super_wdt_reset_config for now; can be evaluated later to see whether needs to add it back
-    /*
-      For origin chip & ECO1: only support swt reset;
-      For ECO2: fix brownout reset bug, support swt & brownout reset;
-      For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
-    */
-    uint8_t chip_version = efuse_hal_get_minor_chip_version();
-    switch (chip_version) {
-        case 0:
-        case 1:
-            //Disable BOR and GLITCH reset
-            bootloader_ana_bod_reset_config(false);
-            bootloader_ana_clock_glitch_reset_config(false);
-            break;
-        case 2:
-            //Enable BOR reset. Disable GLITCH reset
-            bootloader_ana_bod_reset_config(true);
-            bootloader_ana_clock_glitch_reset_config(false);
-            break;
-        case 3:
-        default:
-            //Enable BOR, and GLITCH reset
-            bootloader_ana_bod_reset_config(true);
-            bootloader_ana_clock_glitch_reset_config(true);
-            break;
-    }
+    //Enable super WDT reset.
+    bootloader_ana_super_wdt_reset_config(true);
+    //Enable BOD reset
+    bootloader_ana_bod_reset_config(true);
 }
 
 esp_err_t bootloader_init(void)
diff --git a/components/bootloader_support/src/esp32h2/bootloader_soc.c b/components/bootloader_support/src/esp32h2/bootloader_soc.c
index 21334dd9ec..508e0b6a7b 100644
--- a/components/bootloader_support/src/esp32h2/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32h2/bootloader_soc.c
@@ -1,20 +1,22 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <stdbool.h>
-#include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
 
 void bootloader_ana_super_wdt_reset_config(bool enable)
 {
-    // ESP32H2 has removed the super wdt
+    //H2 doesn't support bypass super WDT reset
+    assert(enable);
+    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
 }
 
 void bootloader_ana_bod_reset_config(bool enable)
 {
-    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
+    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
+
     if (enable) {
         REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
     } else {
@@ -22,12 +24,8 @@ void bootloader_ana_bod_reset_config(bool enable)
     }
 }
 
+//Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
-    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
-    if (enable) {
-        REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
-    } else {
-        REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
-    }
+    (void)enable;
 }
diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
index 7b48fcc756..50653dbd8c 100644
--- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
+++ b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
@@ -85,7 +85,7 @@ static inline void bootloader_hardware_init(void)
 
 static inline void bootloader_ana_reset_config(void)
 {
-    //Enable WDT, BOR, and GLITCH reset
+    //Enable WDT, BOD, and GLITCH reset
     bootloader_ana_super_wdt_reset_config(true);
     bootloader_ana_bod_reset_config(true);
     bootloader_ana_clock_glitch_reset_config(true);
diff --git a/components/bootloader_support/src/esp32h4/bootloader_soc.c b/components/bootloader_support/src/esp32h4/bootloader_soc.c
index 7104528a58..a8e6f45d9d 100644
--- a/components/bootloader_support/src/esp32h4/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32h4/bootloader_soc.c
@@ -20,7 +20,7 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
 
 void bootloader_ana_bod_reset_config(bool enable)
 {
-    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
+    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
 
     if (enable) {
         REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
index 25848608d6..84f2f919e6 100644
--- a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
+++ b/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -109,7 +109,7 @@ extern "C" {
 #define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S  0
 
 #define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
-#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
+#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
 #define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
 
 /** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register
diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h b/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h
index d44ae667ae..85277c4d35 100644
--- a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h
+++ b/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -234,7 +234,7 @@ extern "C" {
 #define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S  0
 
 #define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
-#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
+#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
 #define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
 
 /** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register
diff --git a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h b/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h
index 34d6c7c5d4..f079d1240c 100644
--- a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h
@@ -2727,7 +2727,7 @@ extern "C" {
 #define RTC_CNTL_FIB_SEL_S  0
 
 #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
-#define RTC_CNTL_FIB_BOR_RST BIT(1)
+#define RTC_CNTL_FIB_BOD_RST BIT(1)
 #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
 
 #define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0x013C)
diff --git a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h b/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h
index 8226d49e4f..c2e6c19f9a 100644
--- a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h
@@ -3475,7 +3475,7 @@ extern "C" {
 #define RTC_CNTL_FIB_SEL_S  0
 
 #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
-#define RTC_CNTL_FIB_BOR_RST BIT(1)
+#define RTC_CNTL_FIB_BOD_RST BIT(1)
 #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
 
 /** RTC_CNTL_GPIO_WAKEUP_REG register