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fix(cache): add lock to protect cache sync operation

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This commit is contained in:
gaoxiaojie
2023-07-21 19:02:47 +08:00
parent 4a2f38930b
commit 805f3bc557
2 changed files with 25 additions and 0 deletions
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4
components/esp_system/port/cpu_start.c
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@ -375,6 +375,10 @@ void IRAM_ATTR call_start_cpu0(void)
extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size); extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE); rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
Cache_Resume_DCache(0); Cache_Resume_DCache(0);
/*add lock to protect cache operation*/
extern void esp_cache_op_lock_init(void);
esp_cache_op_lock_init();
#endif // CONFIG_IDF_TARGET_ESP32S3 #endif // CONFIG_IDF_TARGET_ESP32S3
if (esp_efuse_check_errors() != ESP_OK) { if (esp_efuse_check_errors() != ESP_OK) {

21
components/spi_flash/cache_utils.c
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@ -968,3 +968,24 @@ void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
spi_flash_restore_cache(0, 0); // TODO cache_value should be non-zero spi_flash_restore_cache(0, 0); // TODO cache_value should be non-zero
#endif #endif
} }
#if CONFIG_IDF_TARGET_ESP32S3
/*protect cache opreation*/
static spinlock_t cache_op_lock = SPINLOCK_INITIALIZER;
IRAM_ATTR void esp_cache_op_lock(void)
{
portENTER_CRITICAL_SAFE(&cache_op_lock);
}
IRAM_ATTR void esp_cache_op_unlock(void)
{
portEXIT_CRITICAL_SAFE(&cache_op_lock);
}
IRAM_ATTR void esp_cache_op_lock_init(void)
{
rom_cache_op_cb.start = esp_cache_op_lock;
rom_cache_op_cb.end = esp_cache_op_unlock;
}
#endif// CONFIG_IDF_TARGET_ESP32S3