mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-02 12:14:32 +02:00
fix(i2c): read write FIFO memory by volatile
This commit is contained in:
@@ -24,7 +24,6 @@
|
|||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief I2C hardware cmd register fields.
|
* @brief I2C hardware cmd register fields.
|
||||||
*/
|
*/
|
||||||
@@ -305,8 +304,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e
|
|||||||
__attribute__((always_inline))
|
__attribute__((always_inline))
|
||||||
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
||||||
{
|
{
|
||||||
switch (hw->sr.stretch_cause)
|
switch (hw->sr.stretch_cause) {
|
||||||
{
|
|
||||||
case 0:
|
case 0:
|
||||||
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
||||||
break;
|
break;
|
||||||
@@ -623,14 +621,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs to be writen
|
* @param len Amount of data needs to be writen
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr;
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
fifo_addr[i + ram_offset] = ptr[i];
|
hw->txfifo_mem[i + ram_offset] = ptr[i];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -641,15 +636,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs read
|
* @param len Amount of data needs read
|
||||||
*
|
|
||||||
* @return None
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr;
|
|
||||||
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
ptr[i] = fifo_addr[i + ram_offset];
|
ptr[i] = hw->rxfifo_mem[i + ram_offset];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -700,8 +691,6 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
|
|||||||
*filter_conf = hw->filter_cfg.scl_thres;
|
*filter_conf = hw->filter_cfg.scl_thres;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
|
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
|
||||||
*
|
*
|
||||||
@@ -1057,7 +1046,6 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
|
|||||||
hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT);
|
hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Configure I2C SCL timing
|
* @brief Configure I2C SCL timing
|
||||||
*
|
*
|
||||||
|
@@ -310,8 +310,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e
|
|||||||
__attribute__((always_inline))
|
__attribute__((always_inline))
|
||||||
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
||||||
{
|
{
|
||||||
switch (hw->sr.stretch_cause)
|
switch (hw->sr.stretch_cause) {
|
||||||
{
|
|
||||||
case 0:
|
case 0:
|
||||||
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
||||||
break;
|
break;
|
||||||
@@ -628,14 +627,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs to be writen
|
* @param len Amount of data needs to be writen
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr;
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
fifo_addr[i + ram_offset] = ptr[i];
|
hw->txfifo_mem[i + ram_offset] = ptr[i];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -646,15 +642,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs read
|
* @param len Amount of data needs read
|
||||||
*
|
|
||||||
* @return None
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr;
|
|
||||||
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
ptr[i] = fifo_addr[i + ram_offset];
|
ptr[i] = hw->rxfifo_mem[i + ram_offset];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -306,8 +306,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e
|
|||||||
__attribute__((always_inline))
|
__attribute__((always_inline))
|
||||||
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
||||||
{
|
{
|
||||||
switch (hw->sr.stretch_cause)
|
switch (hw->sr.stretch_cause) {
|
||||||
{
|
|
||||||
case 0:
|
case 0:
|
||||||
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
||||||
break;
|
break;
|
||||||
@@ -624,14 +623,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs to be writen
|
* @param len Amount of data needs to be writen
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr;
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
fifo_addr[i + ram_offset] = ptr[i];
|
hw->txfifo_mem[i + ram_offset] = ptr[i];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -642,15 +638,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs read
|
* @param len Amount of data needs read
|
||||||
*
|
|
||||||
* @return None
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr;
|
|
||||||
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
ptr[i] = fifo_addr[i + ram_offset];
|
ptr[i] = hw->rxfifo_mem[i + ram_offset];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -610,14 +610,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs to be writen
|
* @param len Amount of data needs to be writen
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr;
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
fifo_addr[i + ram_offset] = ptr[i];
|
hw->txfifo_mem[i + ram_offset] = ptr[i];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -628,15 +625,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs read
|
* @param len Amount of data needs read
|
||||||
*
|
|
||||||
* @return None
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr;
|
|
||||||
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
ptr[i] = fifo_addr[i + ram_offset];
|
ptr[i] = hw->rxfifo_mem[i + ram_offset];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -835,7 +828,6 @@ static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
|
|||||||
return &dev->int_status;
|
return &dev->int_status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Enable I2C slave clock stretch.
|
* @brief Enable I2C slave clock stretch.
|
||||||
*
|
*
|
||||||
|
@@ -304,8 +304,7 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e
|
|||||||
__attribute__((always_inline))
|
__attribute__((always_inline))
|
||||||
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
|
||||||
{
|
{
|
||||||
switch (hw->sr.stretch_cause)
|
switch (hw->sr.stretch_cause) {
|
||||||
{
|
|
||||||
case 0:
|
case 0:
|
||||||
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
*stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
|
||||||
break;
|
break;
|
||||||
@@ -622,14 +621,11 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs to be writen
|
* @param len Amount of data needs to be writen
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr;
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
fifo_addr[i + ram_offset] = ptr[i];
|
hw->txfifo_mem[i + ram_offset] = ptr[i];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -640,15 +636,11 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
|
|||||||
* @param ram_offset Offset value of I2C RAM.
|
* @param ram_offset Offset value of I2C RAM.
|
||||||
* @param ptr Pointer to data buffer
|
* @param ptr Pointer to data buffer
|
||||||
* @param len Amount of data needs read
|
* @param len Amount of data needs read
|
||||||
*
|
|
||||||
* @return None
|
|
||||||
*/
|
*/
|
||||||
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
||||||
{
|
{
|
||||||
uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr;
|
|
||||||
|
|
||||||
for (int i = 0; i < len; i++) {
|
for (int i = 0; i < len; i++) {
|
||||||
ptr[i] = fifo_addr[i + ram_offset];
|
ptr[i] = hw->rxfifo_mem[i + ram_offset];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -1,16 +1,8 @@
|
|||||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
/*
|
||||||
//
|
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
*
|
||||||
// you may not use this file except in compliance with the License.
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
// You may obtain a copy of the License at
|
*/
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
#ifndef _SOC_I2C_STRUCT_H_
|
#ifndef _SOC_I2C_STRUCT_H_
|
||||||
#define _SOC_I2C_STRUCT_H_
|
#define _SOC_I2C_STRUCT_H_
|
||||||
|
|
||||||
@@ -363,39 +355,8 @@ typedef volatile struct i2c_dev_s {
|
|||||||
uint32_t reserved_f4;
|
uint32_t reserved_f4;
|
||||||
uint32_t date;
|
uint32_t date;
|
||||||
uint32_t reserved_fc;
|
uint32_t reserved_fc;
|
||||||
uint32_t txfifo_start_addr;
|
uint32_t txfifo_mem[32];
|
||||||
uint32_t reserved_104;
|
uint32_t rxfifo_mem[32];
|
||||||
uint32_t reserved_108;
|
|
||||||
uint32_t reserved_10c;
|
|
||||||
uint32_t reserved_110;
|
|
||||||
uint32_t reserved_114;
|
|
||||||
uint32_t reserved_118;
|
|
||||||
uint32_t reserved_11c;
|
|
||||||
uint32_t reserved_120;
|
|
||||||
uint32_t reserved_124;
|
|
||||||
uint32_t reserved_128;
|
|
||||||
uint32_t reserved_12c;
|
|
||||||
uint32_t reserved_130;
|
|
||||||
uint32_t reserved_134;
|
|
||||||
uint32_t reserved_138;
|
|
||||||
uint32_t reserved_13c;
|
|
||||||
uint32_t reserved_140;
|
|
||||||
uint32_t reserved_144;
|
|
||||||
uint32_t reserved_148;
|
|
||||||
uint32_t reserved_14c;
|
|
||||||
uint32_t reserved_150;
|
|
||||||
uint32_t reserved_154;
|
|
||||||
uint32_t reserved_158;
|
|
||||||
uint32_t reserved_15c;
|
|
||||||
uint32_t reserved_160;
|
|
||||||
uint32_t reserved_164;
|
|
||||||
uint32_t reserved_168;
|
|
||||||
uint32_t reserved_16c;
|
|
||||||
uint32_t reserved_170;
|
|
||||||
uint32_t reserved_174;
|
|
||||||
uint32_t reserved_178;
|
|
||||||
uint32_t reserved_17c;
|
|
||||||
uint32_t rxfifo_start_addr;
|
|
||||||
} i2c_dev_t;
|
} i2c_dev_t;
|
||||||
extern i2c_dev_t I2C0;
|
extern i2c_dev_t I2C0;
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@@ -948,34 +948,6 @@ typedef union {
|
|||||||
} i2c_date_reg_t;
|
} i2c_date_reg_t;
|
||||||
|
|
||||||
|
|
||||||
/** Group: Address register */
|
|
||||||
/** Type of txfifo_start_addr register
|
|
||||||
* I2C TXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
|
|
||||||
* This is the I2C txfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t txfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_txfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
/** Type of rxfifo_start_addr register
|
|
||||||
* I2C RXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
|
|
||||||
* This is the I2C rxfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t rxfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_rxfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct i2c_dev_t {
|
typedef struct i2c_dev_t {
|
||||||
volatile i2c_scl_low_period_reg_t scl_low_period;
|
volatile i2c_scl_low_period_reg_t scl_low_period;
|
||||||
volatile i2c_ctr_reg_t ctr;
|
volatile i2c_ctr_reg_t ctr;
|
||||||
@@ -1007,16 +979,15 @@ typedef struct i2c_dev_t {
|
|||||||
uint32_t reserved_088[28];
|
uint32_t reserved_088[28];
|
||||||
volatile i2c_date_reg_t date;
|
volatile i2c_date_reg_t date;
|
||||||
uint32_t reserved_0fc;
|
uint32_t reserved_0fc;
|
||||||
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
|
volatile uint32_t txfifo_mem[32];
|
||||||
uint32_t reserved_104[31];
|
volatile uint32_t rxfifo_mem[32];
|
||||||
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
|
|
||||||
} i2c_dev_t;
|
} i2c_dev_t;
|
||||||
|
|
||||||
extern i2c_dev_t I2C0;
|
extern i2c_dev_t I2C0;
|
||||||
extern i2c_dev_t LP_I2C;
|
extern i2c_dev_t LP_I2C;
|
||||||
|
|
||||||
#ifndef __cplusplus
|
#ifndef __cplusplus
|
||||||
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
|
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@@ -948,34 +948,6 @@ typedef union {
|
|||||||
} i2c_date_reg_t;
|
} i2c_date_reg_t;
|
||||||
|
|
||||||
|
|
||||||
/** Group: Address register */
|
|
||||||
/** Type of txfifo_start_addr register
|
|
||||||
* I2C TXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
|
|
||||||
* This is the I2C txfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t txfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_txfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
/** Type of rxfifo_start_addr register
|
|
||||||
* I2C RXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
|
|
||||||
* This is the I2C rxfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t rxfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_rxfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct i2c_dev_t {
|
typedef struct i2c_dev_t {
|
||||||
volatile i2c_scl_low_period_reg_t scl_low_period;
|
volatile i2c_scl_low_period_reg_t scl_low_period;
|
||||||
volatile i2c_ctr_reg_t ctr;
|
volatile i2c_ctr_reg_t ctr;
|
||||||
@@ -1007,16 +979,15 @@ typedef struct i2c_dev_t {
|
|||||||
uint32_t reserved_088[28];
|
uint32_t reserved_088[28];
|
||||||
volatile i2c_date_reg_t date;
|
volatile i2c_date_reg_t date;
|
||||||
uint32_t reserved_0fc;
|
uint32_t reserved_0fc;
|
||||||
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
|
volatile uint32_t txfifo_mem[32];
|
||||||
uint32_t reserved_104[31];
|
volatile uint32_t rxfifo_mem[32];
|
||||||
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
|
|
||||||
} i2c_dev_t;
|
} i2c_dev_t;
|
||||||
|
|
||||||
extern i2c_dev_t I2C0;
|
extern i2c_dev_t I2C0;
|
||||||
extern i2c_dev_t I2C1;
|
extern i2c_dev_t I2C1;
|
||||||
|
|
||||||
#ifndef __cplusplus
|
#ifndef __cplusplus
|
||||||
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
|
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@@ -1047,34 +1047,6 @@ typedef union {
|
|||||||
} i2c_date_reg_t;
|
} i2c_date_reg_t;
|
||||||
|
|
||||||
|
|
||||||
/** Group: Address register */
|
|
||||||
/** Type of txfifo_start_addr register
|
|
||||||
* I2C TXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
|
|
||||||
* Represents the I2C txfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t txfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_txfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
/** Type of rxfifo_start_addr register
|
|
||||||
* I2C RXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
|
|
||||||
* Represents the I2C rxfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t rxfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_rxfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
volatile i2c_scl_low_period_reg_t scl_low_period;
|
volatile i2c_scl_low_period_reg_t scl_low_period;
|
||||||
volatile i2c_ctr_reg_t ctr;
|
volatile i2c_ctr_reg_t ctr;
|
||||||
@@ -1106,9 +1078,8 @@ typedef struct {
|
|||||||
uint32_t reserved_088[28];
|
uint32_t reserved_088[28];
|
||||||
volatile i2c_date_reg_t date;
|
volatile i2c_date_reg_t date;
|
||||||
uint32_t reserved_0fc;
|
uint32_t reserved_0fc;
|
||||||
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
|
volatile uint32_t txfifo_mem[32];
|
||||||
uint32_t reserved_104[31];
|
volatile uint32_t rxfifo_mem[32];
|
||||||
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
|
|
||||||
} i2c_dev_t;
|
} i2c_dev_t;
|
||||||
|
|
||||||
extern i2c_dev_t I2C0;
|
extern i2c_dev_t I2C0;
|
||||||
@@ -1116,7 +1087,7 @@ extern i2c_dev_t I2C1;
|
|||||||
extern i2c_dev_t LP_I2C;
|
extern i2c_dev_t LP_I2C;
|
||||||
|
|
||||||
#ifndef __cplusplus
|
#ifndef __cplusplus
|
||||||
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
|
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@@ -941,35 +941,6 @@ typedef union {
|
|||||||
uint32_t val;
|
uint32_t val;
|
||||||
} i2c_date_reg_t;
|
} i2c_date_reg_t;
|
||||||
|
|
||||||
|
|
||||||
/** Group: Address register */
|
|
||||||
/** Type of txfifo_start_addr register
|
|
||||||
* I2C TXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** txfifo_start_addr : RO; bitpos: [31:0]; default: 0;
|
|
||||||
* This is the I2C txfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t txfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_txfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
/** Type of rxfifo_start_addr register
|
|
||||||
* I2C RXFIFO base address register
|
|
||||||
*/
|
|
||||||
typedef union {
|
|
||||||
struct {
|
|
||||||
/** rxfifo_start_addr : RO; bitpos: [31:0]; default: 0;
|
|
||||||
* This is the I2C rxfifo first address.
|
|
||||||
*/
|
|
||||||
uint32_t rxfifo_start_addr:32;
|
|
||||||
};
|
|
||||||
uint32_t val;
|
|
||||||
} i2c_rxfifo_start_addr_reg_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
volatile i2c_scl_low_period_reg_t scl_low_period;
|
volatile i2c_scl_low_period_reg_t scl_low_period;
|
||||||
volatile i2c_ctr_reg_t ctr;
|
volatile i2c_ctr_reg_t ctr;
|
||||||
@@ -1001,16 +972,15 @@ typedef struct {
|
|||||||
uint32_t reserved_088[28];
|
uint32_t reserved_088[28];
|
||||||
volatile i2c_date_reg_t date;
|
volatile i2c_date_reg_t date;
|
||||||
uint32_t reserved_0fc;
|
uint32_t reserved_0fc;
|
||||||
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
|
volatile uint32_t txfifo_mem[32];
|
||||||
uint32_t reserved_104[31];
|
volatile uint32_t rxfifo_mem[32];
|
||||||
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
|
|
||||||
} i2c_dev_t;
|
} i2c_dev_t;
|
||||||
|
|
||||||
extern i2c_dev_t I2C0;
|
extern i2c_dev_t I2C0;
|
||||||
extern i2c_dev_t I2C1;
|
extern i2c_dev_t I2C1;
|
||||||
|
|
||||||
#ifndef __cplusplus
|
#ifndef __cplusplus
|
||||||
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
|
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@@ -667,7 +667,6 @@ components/soc/esp32c3/include/soc/fe_reg.h
|
|||||||
components/soc/esp32c3/include/soc/gpio_reg.h
|
components/soc/esp32c3/include/soc/gpio_reg.h
|
||||||
components/soc/esp32c3/include/soc/gpio_struct.h
|
components/soc/esp32c3/include/soc/gpio_struct.h
|
||||||
components/soc/esp32c3/include/soc/i2c_reg.h
|
components/soc/esp32c3/include/soc/i2c_reg.h
|
||||||
components/soc/esp32c3/include/soc/i2c_struct.h
|
|
||||||
components/soc/esp32c3/include/soc/interrupt_core0_reg.h
|
components/soc/esp32c3/include/soc/interrupt_core0_reg.h
|
||||||
components/soc/esp32c3/include/soc/ledc_reg.h
|
components/soc/esp32c3/include/soc/ledc_reg.h
|
||||||
components/soc/esp32c3/include/soc/nrx_reg.h
|
components/soc/esp32c3/include/soc/nrx_reg.h
|
||||||
|
Reference in New Issue
Block a user