From 7585e86a05d31b4a9f880800e2cae84a8e644b2c Mon Sep 17 00:00:00 2001
From: jiangguangming <jiangguangming@espressif.com>
Date: Thu, 5 Jan 2023 15:52:49 +0800
Subject: [PATCH 1/3] esp_rom: update H2 and C2 rom rtc.h

---
 components/esp_rom/include/esp32c2/rom/rtc.h | 38 +-------------
 components/esp_rom/include/esp32h2/rom/rtc.h | 55 ++++++++------------
 2 files changed, 22 insertions(+), 71 deletions(-)

diff --git a/components/esp_rom/include/esp32c2/rom/rtc.h b/components/esp_rom/include/esp32c2/rom/rtc.h
index 910792a29a..f5b2a35478 100644
--- a/components/esp_rom/include/esp32c2/rom/rtc.h
+++ b/components/esp_rom/include/esp32c2/rom/rtc.h
@@ -4,16 +4,13 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ROM_RTC_H_
-#define _ROM_RTC_H_
+#pragma once
 
 #include "ets_sys.h"
 
 #include <stdbool.h>
 #include <stdint.h>
 #include "esp_assert.h"
-
-#include "soc/soc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/reset_reasons.h"
 
@@ -161,17 +158,6 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
-/**
-  * @brief Get CRC for Fast RTC Memory.
-  *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
-  *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
-  *
-  * @return uint32_t : CRC32 result
-  */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
-
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
   * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
@@ -190,26 +176,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *
@@ -241,5 +207,3 @@ void software_reset_cpu(int cpu_no);
 #ifdef __cplusplus
 }
 #endif
-
-#endif /* _ROM_RTC_H_ */
diff --git a/components/esp_rom/include/esp32h2/rom/rtc.h b/components/esp_rom/include/esp32h2/rom/rtc.h
index 2629fd9a6d..8499f1b052 100644
--- a/components/esp_rom/include/esp32h2/rom/rtc.h
+++ b/components/esp_rom/include/esp32h2/rom/rtc.h
@@ -4,16 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ROM_RTC_H_
-#define _ROM_RTC_H_
-
-#include "ets_sys.h"
+#pragma once
 
 #include <stdbool.h>
 #include <stdint.h>
 #include "esp_assert.h"
-
-#include "soc/soc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/reset_reasons.h"
 
@@ -67,7 +62,6 @@ extern "C" {
 
 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 
-
 typedef enum {
     AWAKE = 0,             //<CPU ON
     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
@@ -175,16 +169,31 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
   */
 WAKEUP_REASON rtc_get_wakeup_cause(void);
 
+typedef void (* esp_rom_wake_func_t)(void);
+
 /**
-  * @brief Get CRC for Fast RTC Memory.
+  * @brief Read stored RTC wake function address
   *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
   *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  * @param  None
   *
-  * @return uint32_t : CRC32 result
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
   */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
+/**
+  * @brief Store new RTC wake function address
+  *
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
+  *
+  * @param entry_addr Address of function. If NULL, length is ignored and all registers are cleared to 0.
+  * @param length of function in RTC fast memory. cannot be larger than RTC Fast memory size.
+  *
+  * @return None
+  */
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
 
 /**
   * @brief Suppress ROM log by setting specific RTC control register.
@@ -204,26 +213,6 @@ static inline void rtc_suppress_rom_log(void)
     REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }
 
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
   * @brief Software Reset digital core.
   *
@@ -255,5 +244,3 @@ void software_reset_cpu(int cpu_no);
 #ifdef __cplusplus
 }
 #endif
-
-#endif /* _ROM_RTC_H_ */

From 8e6dfb8af4a5fd1864dd86fbd675079c3a927a21 Mon Sep 17 00:00:00 2001
From: jiangguangming <jiangguangming@espressif.com>
Date: Thu, 5 Jan 2023 15:56:20 +0800
Subject: [PATCH 2/3] soc: H2(beta) support
 SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY

---
 components/soc/esp32h2/include/soc/Kconfig.soc_caps.in | 4 ++++
 components/soc/esp32h2/include/soc/soc_caps.h          | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 7622e5a604..3fa83982df 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -739,6 +739,10 @@ config SOC_PM_SUPPORT_BT_PD
     bool
     default y
 
+config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index bb88bf0243..dc9cd43fbc 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -361,6 +361,8 @@
 
 #define SOC_PM_SUPPORT_BT_PD            (1)
 
+#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)

From d9efa662c821d99e6d711d751f22c207b7f08202 Mon Sep 17 00:00:00 2001
From: jiangguangming <jiangguangming@espressif.com>
Date: Thu, 5 Jan 2023 15:58:37 +0800
Subject: [PATCH 3/3] esp_hw_support: support riscv call

---
 components/esp_hw_support/sleep_modes.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 138aa8ec98..aae1342c18 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -229,9 +229,15 @@ static void __attribute__((section(".rtc.entry.text"))) esp_wake_stub_entry(void
 {
 #define _SYM2STR(s) # s
 #define SYM2STR(s)  _SYM2STR(s)
+
+#ifdef __riscv
+    __asm__ __volatile__ ("call " SYM2STR(esp_wake_stub_start) "\n");
+#else
     // call4 has a larger effective addressing range (-524284 to 524288 bytes),
     // which is sufficient for instruction addressing in RTC fast memory.
     __asm__ __volatile__ ("call4 " SYM2STR(esp_wake_stub_start) "\n");
+#endif
+
 }
 #endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY