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spi_master:support octal mode for esp32s2 and esp32s3
Add support for 8-line spi for lcd on esp32s2 and esp32s3 Closes https://github.com/espressif/esp-idf/issues/6371
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bizhuangyang
morris
@@ -47,12 +47,16 @@ Term Definition
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**Host** The SPI controller peripheral inside {IDF_TARGET_NAME} that initiates SPI transmissions over the bus, and acts as an SPI Master.
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**Device** SPI slave device. An SPI bus may be connected to one or more Devices. Each Device shares the MOSI, MISO and SCLK signals but is only active on the bus when the Host asserts the Device's individual CS line.
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**Bus** A signal bus, common to all Devices connected to one Host. In general, a bus includes the following lines: MISO, MOSI, SCLK, one or more CS lines, and, optionally, QUADWP and QUADHD. So Devices are connected to the same lines, with the exception that each Device has its own CS line. Several Devices can also share one CS line if connected in the daisy-chain manner.
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**MISO** Master In, Slave Out, a.k.a. Q. Data transmission from a Device to Host.
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**MOSI** Master Out, Slave In, a.k.a. D. Data transmission from a Host to Device.
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**MISO** Master In, Slave Out, a.k.a. Q. Data transmission from a Device to Host. Also data1 signal in octal mode.
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**MOSI** Master Out, Slave In, a.k.a. D. Data transmission from a Host to Device. Also data0 signal in octal mode.
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**SCLK** Serial Clock. Oscillating signal generated by a Host that keeps the transmission of data bits in sync.
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**CS** Chip Select. Allows a Host to select individual Device(s) connected to the bus in order to send or receive data.
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**QUADWP** Write Protect signal. Only used for 4-bit (qio/qout) transactions.
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**QUADHD** Hold signal. Only used for 4-bit (qio/qout) transactions.
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**QUADWP** Write Protect signal. Used for 4-bit (qio/qout) transactions. Also for data2 signal in octal mode.
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**QUADHD** Hold signal. Used for 4-bit (qio/qout) transactions. Also for data3 signal in octal mode.
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**DATA4** Data4 signal in octal mode.
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**DATA5** Data5 signal in octal mode.
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**DATA6** Data6 signal in octal mode.
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**DATA7** Data7 signal in octal mode.
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**Assertion** The action of activating a line.
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**De-assertion** The action of returning the line back to inactive (back to idle) status.
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**Transaction** One instance of a Host asserting a CS line, transferring data to and from a Device, and de-asserting the CS line. Transactions are atomic, which means they can never be interrupted by another transaction.
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@@ -144,6 +148,41 @@ All the tasks that use interrupt transactions can be blocked by the queue. At th
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The :cpp:func:`spi_device_polling_end` routine needs an overhead of at least 1 us to unblock other tasks when the transaction is finished. It is strongly recommended to wrap a series of polling transactions using the functions :cpp:func:`spi_device_acquire_bus` and :cpp:func:`spi_device_release_bus` to avoid the overhead. For more information, see :ref:`bus_acquiring`.
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Transaction Line Mode
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^^^^^^^^^^^^^^^^^^^^^
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Supported line modes are as follows:
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====================== ====================== ====================== ==================
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Mode name Command Line Width Address Line Width Data Line Width
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====================== ====================== ====================== ==================
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**Dual Output** 1 1 2
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**Dual I/O** 1 2 2
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**Quad Output** 1 1 4
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**Quad I/O** 1 4 4
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**Octal Output** 1 1 8
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**OPI** 8 8 8
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====================== ====================== ====================== ==================
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To make use of these modes, `data0_io_num` to `data7_io_num` I/O pins in the struct :cpp:type:`spi_bus_config_t` and the member `flags` in the struct :cpp:type:`spi_bus_config_t` should be set as shown below:
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+-------------------+--------------------------+
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| Mode name | Flags |
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+===================+==========================+
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| Dual Output | |
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+-------------------+ SPICOMMON_BUSFLAG_DUAL |
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| Dual I/O | |
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+-------------------+--------------------------+
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| Quad Output | |
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+-------------------+ SPICOMMON_BUSFLAG_QUAD |
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| Quad I/O | |
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+-------------------+--------------------------+
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| Octal Output | |
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+-------------------+ SPICOMMON_BUSFLAG_OCTAL |
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| OPI | |
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+-------------------+--------------------------+
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Command and Address Phases
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -152,6 +191,8 @@ During the command and address phases, the members :cpp:member:`cmd` and :cpp:me
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If the lengths of the command and address phases need to be variable, declare the struct :cpp:type:`spi_transaction_ext_t`, set the flags :cpp:type:`SPI_TRANS_VARIABLE_CMD` and/or :cpp:type:`SPI_TRANS_VARIABLE_ADDR` in the member :cpp:member:`spi_transaction_ext_t::base` and configure the rest of base as usual. Then the length of each phase will be equal to :cpp:member:`command_bits` and :cpp:member:`address_bits` set in the struct :cpp:type:`spi_transaction_ext_t`.
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If using more than one data lines to transmit, please set flags at the member `flags` in the struct :cpp:type:`spi_transaction_t`. If the number of lines transmitting command is the same as that transmitting data, please set `MULTILINE_CMD`. If the number of lines transmitting address is the same as that transmitting data, please set `MULTILINE_ADDR`.
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Write and Read Phases
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^^^^^^^^^^^^^^^^^^^^^
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@@ -163,6 +204,24 @@ Normally, the data that needs to be transferred to or from a Device will be read
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If these requirements are not satisfied, the transaction efficiency will be affected due to the allocation and copying of temporary buffers.
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If using more than one data lines to transmit, please set `SPI_DEVICE_HALFDUPLEX` flag at the member `flags` in the struct :cpp:type:`spi_device_interface_config_t`. And the member `flags` in the struct :cpp:type:`spi_transaction_t` should be set as below:
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+-------------------+--------------------+
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| Mode name | Flags |
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+===================+====================+
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| Dual Output | |
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+-------------------+ SPI_TRANS_MODE_DIO |
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| Dual I/O | |
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+-------------------+--------------------+
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| Quad Output | |
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+-------------------+ SPI_TRANS_MODE_QIO |
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| Quad I/O | |
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+-------------------+--------------------+
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| Octal Output | |
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+-------------------+ SPI_TRANS_MODE_OCT |
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| OPI | |
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+-------------------+--------------------+
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.. only:: esp32
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.. note::
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@@ -31,7 +31,7 @@ Introduction
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------------
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In the half duplex mode, the master has to use the protocol defined by the slave to communicate
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with the slave. Each transaction may consists of the following phases (list by the order they
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with the slave. Each transaction may consist of the following phases (list by the order they
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should exist):
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- Command: 8-bit, master to slave
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