From 217e36bec09ad7ca485aafdc108582c5f52d55f7 Mon Sep 17 00:00:00 2001 From: wanlei Date: Mon, 13 Feb 2023 20:33:44 +0800 Subject: [PATCH] spi: fix spi support on h4 after diver/cmakelist refactored --- .../driver/test_apps/spi/master/main/test_spi_master.c | 9 +++++++++ components/hal/esp32h4/include/hal/spi_ll.h | 10 +++++++++- components/soc/esp32h4/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32h4/include/soc/clk_tree_defs.h | 7 ++++--- components/soc/esp32h4/include/soc/soc_caps.h | 2 ++ 5 files changed, 32 insertions(+), 4 deletions(-) diff --git a/components/driver/test_apps/spi/master/main/test_spi_master.c b/components/driver/test_apps/spi/master/main/test_spi_master.c index ddfb431851..1a929ae373 100644 --- a/components/driver/test_apps/spi/master/main/test_spi_master.c +++ b/components/driver/test_apps/spi/master/main/test_spi_master.c @@ -117,6 +117,15 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") } #endif +#if SOC_SPI_SUPPORT_CLK_AHB + clk_tree_src_get_freq_hz(SPI_CLK_SRC_AHB, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz); + printf("\nTest clock source AHB = %ld\n", clock_source_hz); + TEST_ASSERT((48 * 1000 * 1000) == clock_source_hz); + for (int i = 0; i < TEST_CLK_TIMES; i++) { + check_spi_pre_n_for(SPI_CLK_SRC_AHB, test_clk_param.clk_param_48m[i][0], test_clk_param.clk_param_48m[i][1], test_clk_param.clk_param_48m[i][2]); + } +#endif + #if SOC_SPI_SUPPORT_CLK_PLL_F40M clk_tree_src_get_freq_hz(SPI_CLK_SRC_PLL_F40M, CLK_TREE_SRC_FREQ_PRECISION_APPROX, &clock_source_hz); printf("\nTest clock source PLL_40M = %ld\n", clock_source_hz); diff --git a/components/hal/esp32h4/include/hal/spi_ll.h b/components/hal/esp32h4/include/hal/spi_ll.h index 4ab56b97a4..b4df8b61fd 100644 --- a/components/hal/esp32h4/include/hal/spi_ll.h +++ b/components/hal/esp32h4/include/hal/spi_ll.h @@ -99,7 +99,15 @@ typedef enum { */ static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) { - //empty, keep this for compatibility + switch (clk_source) + { + case SPI_CLK_SRC_XTAL: + hw->clk_gate.mst_clk_sel = 0; + break; + default: + hw->clk_gate.mst_clk_sel = 1; + break; + } } /** diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 913156a2d6..356fc7aa54 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -75,6 +75,10 @@ config SOC_SDM_SUPPORTED bool default y +config SOC_GPSPI_SUPPORTED + bool + default y + config SOC_LEDC_SUPPORTED bool default y @@ -583,6 +587,10 @@ config SOC_SPI_SUPPORT_CLK_AHB bool default y +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT bool default y diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h index e301c08b50..0c0fc8eab4 100644 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h @@ -254,14 +254,15 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of SPI */ -#define SOC_SPI_CLKS {SOC_MOD_CLK_AHB} +#define SOC_SPI_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL} /** * @brief Type of SPI clock source. */ typedef enum { - SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as SPI source clock */ - SPI_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB as SPI source clock */ + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB 48M as SPI source clock */ + SPI_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB 48M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL 32M as SPI source clock */ } soc_periph_spi_clk_src_t; //////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index a4499dc921..d8332be15f 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -51,6 +51,7 @@ #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 +#define SOC_GPSPI_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 @@ -288,6 +289,7 @@ #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 #define SOC_SPI_SUPPORT_CLK_AHB 1 +#define SOC_SPI_SUPPORT_CLK_XTAL 1 // Peripheral supports DIO, DOUT, QIO, or QOUT // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,