From 8227ca97bd4b27d2aabcd93971590713a36effd5 Mon Sep 17 00:00:00 2001
From: Xiao Xufeng <xiaoxufeng@espressif.com>
Date: Wed, 8 Mar 2023 14:12:34 +0800
Subject: [PATCH] bootloader: enable super WDT and BOD reset on C2

---
 .../src/esp32c2/bootloader_esp32c2.c          | 10 +++++++++
 .../src/esp32c2/bootloader_soc.c              | 21 ++++++++++++++++---
 .../soc/esp32c2/include/soc/rtc_cntl_reg.h    |  4 ++++
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
index 0b6b67f781..8908c515c1 100644
--- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
+++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
@@ -34,6 +34,7 @@
 #include "bootloader_mem.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
+#include "bootloader_soc.h"
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
@@ -240,10 +241,19 @@ static void bootloader_super_wdt_auto_feed(void)
     REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
 }
 
+static inline void bootloader_ana_reset_config(void)
+{
+    //Enable super WDT reset.
+    bootloader_ana_super_wdt_reset_config(true);
+    //Enable BOD reset
+    bootloader_ana_bod_reset_config(true);
+}
+
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
 
+    bootloader_ana_reset_config();
     bootloader_super_wdt_auto_feed();
     // protect memory region
     bootloader_init_mem();
diff --git a/components/bootloader_support/src/esp32c2/bootloader_soc.c b/components/bootloader_support/src/esp32c2/bootloader_soc.c
index 2b20b0415a..2233be7529 100644
--- a/components/bootloader_support/src/esp32c2/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c2/bootloader_soc.c
@@ -3,19 +3,34 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
 #include <stdbool.h>
+#include "soc/rtc_cntl_reg.h"
 
 void bootloader_ana_super_wdt_reset_config(bool enable)
 {
-    (void)enable; // ESP32-C2 has none of these features.
+    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
+
+    if (enable) {
+        REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
+    } else {
+        REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
+    }
 }
 
 void bootloader_ana_bod_reset_config(bool enable)
 {
-    (void)enable; // ESP32-C2 has none of these features.
+    REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
+
+    if (enable) {
+        REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
+    } else {
+        REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
+    }
 }
 
+//Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
-    (void)enable; // ESP32-C2 has none of these features.
+    (void)enable;
 }
diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
index 2ae5143b01..e70fb47603 100644
--- a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
@@ -1678,6 +1678,10 @@ RO CPU.*/
 #define RTC_CNTL_FIB_SEL_V  0x7
 #define RTC_CNTL_FIB_SEL_S  0
 
+#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
+#define RTC_CNTL_FIB_BOD_RST BIT(1)
+#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
+
 #define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
 /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE :  ;bitpos:[31] ;default: 1'b0 ; */
 /*description: Need add desc.*/