mirror of
https://github.com/espressif/esp-idf.git
synced 2025-12-03 15:49:51 +01:00
driver(touch): fix bug and add more features
1. add sens_struct.h 2. add definition of RTCCNTL and RTCIO 3. modify touch pad examples 4. update example code. 5. add comments add option in menuconfig 6. fix issue that pad index 8 and 9 are mismatched 7. add touch_pad_read_filtered() api to get value filtered by iir filter 8. modify touch pad isr func 9. Make the items in perihperal.ld in the sequence of address 10. delete Kconfig for touch pad 11. add touchpad filter APIs to adjust the filter 12. add touch_pad into index.rst 13. add touch_pad in Doxyfile 14. add touch_pad.rst
This commit is contained in:
Wangjialin
@@ -550,4 +550,5 @@ typedef volatile struct {
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uint32_t val;
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} date;
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} rtc_cntl_dev_t;
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extern rtc_cntl_dev_t RTCCNTL;
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#endif /* _SOC_RTC_CNTL_STRUCT_H_ */
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@@ -277,4 +277,5 @@ typedef volatile struct {
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uint32_t val;
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} date;
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} rtc_io_dev_t;
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extern rtc_io_dev_t RTCIO;
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#endif /* _SOC_RTC_IO_STRUCT_H_ */
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316
components/soc/esp32/include/soc/sens_struct.h
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316
components/soc/esp32/include/soc/sens_struct.h
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@@ -0,0 +1,316 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SENS_STRUCT_H_
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#define _SOC_SENS_STRUCT_H_
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typedef volatile struct {
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union {
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struct {
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uint32_t sar1_clk_div: 8;
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uint32_t sar1_sample_cycle: 8;
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uint32_t sar1_sample_bit: 2;
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uint32_t sar1_clk_gated: 1;
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uint32_t sar1_sample_num: 8;
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uint32_t sar1_dig_force: 1;
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uint32_t sar1_data_inv: 1;
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uint32_t reserved29: 3;
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};
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uint32_t val;
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} sar_read_ctrl;
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uint32_t sar_read_status1; /**/
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union {
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struct {
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uint32_t sar_amp_wait1:16;
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uint32_t sar_amp_wait2:16;
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};
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uint32_t val;
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} sar_meas_wait1;
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union {
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struct {
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uint32_t sar_amp_wait3: 16;
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uint32_t force_xpd_amp: 2;
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uint32_t force_xpd_sar: 2;
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uint32_t sar2_rstb_wait: 8;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} sar_meas_wait2;
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union {
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struct {
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uint32_t xpd_sar_amp_fsm: 4;
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uint32_t amp_rst_fb_fsm: 4;
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uint32_t amp_short_ref_fsm: 4;
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uint32_t amp_short_ref_gnd_fsm: 4;
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uint32_t xpd_sar_fsm: 4;
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uint32_t sar_rstb_fsm: 4;
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uint32_t sar2_xpd_wait: 8;
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};
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uint32_t val;
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} sar_meas_ctrl;
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uint32_t sar_read_status2; /**/
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uint32_t ulp_cp_sleep_cyc0; /**/
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uint32_t ulp_cp_sleep_cyc1; /**/
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uint32_t ulp_cp_sleep_cyc2; /**/
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uint32_t ulp_cp_sleep_cyc3; /**/
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uint32_t ulp_cp_sleep_cyc4; /**/
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union {
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struct {
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uint32_t sar1_bit_width: 2;
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uint32_t sar2_bit_width: 2;
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uint32_t sar2_en_test: 1;
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uint32_t sar2_pwdet_cct: 3;
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uint32_t ulp_cp_force_start_top: 1;
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uint32_t ulp_cp_start_top: 1;
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uint32_t sarclk_en: 1;
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uint32_t pc_init: 11;
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uint32_t sar2_stop: 1;
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uint32_t sar1_stop: 1;
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uint32_t sar2_pwdet_en: 1;
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uint32_t reserved25: 7;
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};
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uint32_t val;
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} sar_start_force;
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union {
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struct {
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uint32_t mem_wr_addr_init: 11;
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uint32_t mem_wr_addr_size: 11;
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uint32_t rtc_mem_wr_offst_clr: 1;
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uint32_t reserved23: 9;
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};
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uint32_t val;
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} sar_mem_wr_ctrl;
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uint32_t sar_atten1; /**/
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uint32_t sar_atten2; /**/
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union {
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struct {
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uint32_t i2c_slave_addr1: 11;
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uint32_t i2c_slave_addr0: 11;
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uint32_t meas_status: 8;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} sar_slave_addr1;
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union {
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struct {
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uint32_t i2c_slave_addr3:11;
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uint32_t i2c_slave_addr2:11;
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uint32_t reserved22: 10;
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};
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uint32_t val;
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} sar_slave_addr2;
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union {
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struct {
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uint32_t i2c_slave_addr5:11;
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uint32_t i2c_slave_addr4:11;
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uint32_t tsens_out: 8;
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uint32_t tsens_rdy_out: 1;
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} sar_slave_addr3;
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union {
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struct {
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uint32_t i2c_slave_addr7:11;
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uint32_t i2c_slave_addr6:11;
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uint32_t i2c_rdata: 8;
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uint32_t i2c_done: 1;
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} sar_slave_addr4;
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union {
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struct {
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uint32_t tsens_xpd_wait: 12;
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uint32_t tsens_xpd_force: 1;
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uint32_t tsens_clk_inv: 1;
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uint32_t tsens_clk_gated: 1;
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uint32_t tsens_in_inv: 1;
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uint32_t tsens_clk_div: 8;
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uint32_t tsens_power_up: 1;
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uint32_t tsens_power_up_force: 1;
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uint32_t tsens_dump_out: 1;
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uint32_t reserved27: 5;
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};
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uint32_t val;
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} sar_tctrl;
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union {
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struct {
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uint32_t sar_i2c_ctrl: 28;
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uint32_t sar_i2c_start: 1;
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uint32_t sar_i2c_start_force: 1;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} sar_i2c_ctrl;
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union {
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struct {
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uint32_t meas1_data_sar: 16;
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uint32_t meas1_done_sar: 1;
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uint32_t meas1_start_sar: 1;
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uint32_t meas1_start_force: 1;
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uint32_t sar1_en_pad: 12;
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uint32_t sar1_en_pad_force: 1;
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};
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uint32_t val;
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} sar_meas_start1;
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union {
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struct {
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uint32_t touch_meas_delay:16;
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uint32_t touch_xpd_wait: 8;
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uint32_t touch_out_sel: 1;
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uint32_t touch_out_1en: 1;
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uint32_t xpd_hall_force: 1;
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uint32_t hall_phase_force: 1;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} sar_touch_ctrl1;
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union {
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struct {
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uint32_t l_thresh: 16;
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uint32_t h_thresh: 16;
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};
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uint32_t val;
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} touch_thresh[5];
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union {
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struct {
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uint32_t l_val: 16;
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uint32_t h_val: 16;
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};
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uint32_t val;
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} touch_meas[5];
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union {
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struct {
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uint32_t touch_meas_en: 10;
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uint32_t touch_meas_done: 1;
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uint32_t touch_start_fsm_en: 1;
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uint32_t touch_start_en: 1;
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uint32_t touch_start_force: 1;
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uint32_t touch_sleep_cycles:16;
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uint32_t touch_meas_en_clr: 1;
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} sar_touch_ctrl2;
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uint32_t reserved_88;
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union {
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struct {
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uint32_t touch_pad_worken:10;
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uint32_t touch_pad_outen2:10;
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uint32_t touch_pad_outen1:10;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} sar_touch_enable;
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union {
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struct {
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uint32_t sar2_clk_div: 8;
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uint32_t sar2_sample_cycle: 8;
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uint32_t sar2_sample_bit: 2;
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uint32_t sar2_clk_gated: 1;
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uint32_t sar2_sample_num: 8;
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uint32_t sar2_pwdet_force: 1;
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uint32_t sar2_dig_force: 1;
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uint32_t sar2_data_inv: 1;
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uint32_t reserved30: 2;
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};
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uint32_t val;
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} sar_read_ctrl2;
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union {
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struct {
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uint32_t meas2_data_sar: 16;
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uint32_t meas2_done_sar: 1;
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uint32_t meas2_start_sar: 1;
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uint32_t meas2_start_force: 1;
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uint32_t sar2_en_pad: 12;
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uint32_t sar2_en_pad_force: 1;
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};
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uint32_t val;
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} sar_meas_start2;
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union {
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struct {
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uint32_t sw_fstep: 16;
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uint32_t sw_tone_en: 1;
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uint32_t debug_bit_sel: 5;
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uint32_t dac_dig_force: 1;
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uint32_t dac_clk_force_low: 1;
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uint32_t dac_clk_force_high: 1;
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uint32_t dac_clk_inv: 1;
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uint32_t reserved26: 6;
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};
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uint32_t val;
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} sar_dac_ctrl1;
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union {
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struct {
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uint32_t dac_dc1: 8;
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uint32_t dac_dc2: 8;
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uint32_t dac_scale1: 2;
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uint32_t dac_scale2: 2;
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uint32_t dac_inv1: 2;
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uint32_t dac_inv2: 2;
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uint32_t dac_cw_en1: 1;
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uint32_t dac_cw_en2: 1;
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uint32_t reserved26: 6;
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};
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uint32_t val;
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} sar_dac_ctrl2;
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union {
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struct {
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uint32_t sar1_dac_xpd_fsm: 4;
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uint32_t sar1_dac_xpd_fsm_idle: 1;
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uint32_t xpd_sar_amp_fsm_idle: 1;
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uint32_t amp_rst_fb_fsm_idle: 1;
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uint32_t amp_short_ref_fsm_idle: 1;
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uint32_t amp_short_ref_gnd_fsm_idle: 1;
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uint32_t xpd_sar_fsm_idle: 1;
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uint32_t sar_rstb_fsm_idle: 1;
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uint32_t sar2_rstb_force: 2;
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uint32_t amp_rst_fb_force: 2;
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uint32_t amp_short_ref_force: 2;
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uint32_t amp_short_ref_gnd_force: 2;
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uint32_t reserved19: 13;
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};
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uint32_t val;
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} sar_meas_ctrl2;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t sar_nouse; /**/
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union {
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struct {
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uint32_t sar_date: 28;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} sardate;
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} sens_dev_t;
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extern sens_dev_t SENS;
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#endif /* _SOC_SENS_STRUCT_H_ */
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