diff --git a/components/soc/esp32c5/mp/include/soc/sha_reg.h b/components/soc/esp32c5/mp/include/soc/sha_reg.h index d49c15e267..ab9f346e77 100644 --- a/components/soc/esp32c5/mp/include/soc/sha_reg.h +++ b/components/soc/esp32c5/mp/include/soc/sha_reg.h @@ -172,150 +172,6 @@ extern "C" { #define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) #define SHA_M_MEM_SIZE_BYTES 64 -/** SHA_3_MODE_REG register - * Initial configuration register 0. - */ -#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800) -/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0; - * Sha3 mode - */ -#define SHA_3_MODE 0x00000007U -#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S) -#define SHA_3_MODE_V 0x00000007U -#define SHA_3_MODE_S 0 - -/** SHA_3_CLEAN_M_REG register - * Initial configuration register 1. - */ -#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804) -/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0; - * Clean Message. - */ -#define SHA_3_CLEAN_M (BIT(0)) -#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S) -#define SHA_3_CLEAN_M_V 0x00000001U -#define SHA_3_CLEAN_M_S 0 - -/** SHA_3_DMA_BLOCK_NUM_REG register - * DMA configuration register 0. - */ -#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c) -/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; - * DMA-SHA3 block number. - */ -#define SHA_3_DMA_BLOCK_NUM 0x0000003FU -#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S) -#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU -#define SHA_3_DMA_BLOCK_NUM_S 0 - -/** SHA_3_START_REG register - * Typical SHA3 configuration register 0. - */ -#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810) -/** SHA_3_START : WO; bitpos: [0]; default: 0; - * Start typical sha3. - */ -#define SHA_3_START (BIT(0)) -#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S) -#define SHA_3_START_V 0x00000001U -#define SHA_3_START_S 0 - -/** SHA_3_CONTINUE_REG register - * Typical SHA3 configuration register 1. - */ -#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814) -/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0; - * Continue typical sha3. - */ -#define SHA_3_CONTINUE (BIT(0)) -#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S) -#define SHA_3_CONTINUE_V 0x00000001U -#define SHA_3_CONTINUE_S 0 - -/** SHA_3_BUSY_REG register - * Busy register. - */ -#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818) -/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0; - * Sha3 busy state. 1'b0: idle. 1'b1: busy. - */ -#define SHA_3_BUSY_REG (BIT(0)) -#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S) -#define SHA_3_BUSY_REG_V 0x00000001U -#define SHA_3_BUSY_REG_S 0 - -/** SHA_3_DMA_START_REG register - * DMA configuration register 1. - */ -#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c) -/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0; - * Start dma-sha3. - */ -#define SHA_3_DMA_START (BIT(0)) -#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S) -#define SHA_3_DMA_START_V 0x00000001U -#define SHA_3_DMA_START_S 0 - -/** SHA_3_DMA_CONTINUE_REG register - * DMA configuration register 2. - */ -#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820) -/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0; - * Continue dma-sha3. - */ -#define SHA_3_DMA_CONTINUE (BIT(0)) -#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S) -#define SHA_3_DMA_CONTINUE_V 0x00000001U -#define SHA_3_DMA_CONTINUE_S 0 - -/** SHA_3_CLEAR_INT_REG register - * Interrupt clear register. - */ -#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824) -/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0; - * Clear sha3 interrupt. - */ -#define SHA_3_CLEAR_INT (BIT(0)) -#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S) -#define SHA_3_CLEAR_INT_V 0x00000001U -#define SHA_3_CLEAR_INT_S 0 - -/** SHA_3_INT_ENA_REG register - * Interrupt enable register. - */ -#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828) -/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0; - * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable - */ -#define SHA_3_INT_ENA (BIT(0)) -#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S) -#define SHA_3_INT_ENA_V 0x00000001U -#define SHA_3_INT_ENA_S 0 - -/** SHA_3_SHAKE_LENGTH_REG register - * DMA configuration register 3. - */ -#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c) -/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50; - * SHAKE output hash word length - */ -#define SHA_3_SHAKE_LENGTH 0x000007FFU -#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S) -#define SHA_3_SHAKE_LENGTH_V 0x000007FFU -#define SHA_3_SHAKE_LENGTH_S 0 - -/** SHA_3_M_OUT_MEM register - * Sha3 hash reg which contains intermediate hash or finial hash. - */ -#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900) -#define SHA_3_M_OUT_MEM_SIZE_BYTES 200 - -/** SHA_3_M_MEM register - * Sha3 message reg which contains message. - */ -#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00) -#define SHA_3_M_MEM_SIZE_BYTES 200 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c5/mp/include/soc/sha_struct.h b/components/soc/esp32c5/mp/include/soc/sha_struct.h index db2cb97f44..bc2cd2cef2 100644 --- a/components/soc/esp32c5/mp/include/soc/sha_struct.h +++ b/components/soc/esp32c5/mp/include/soc/sha_struct.h @@ -127,118 +127,6 @@ typedef union { uint32_t val; } sha_t_length_reg_t; -/** Type of mode register - * Initial configuration register 0. - */ -typedef union { - struct { - /** mode : R/W; bitpos: [2:0]; default: 0; - * Sha3 mode - */ - uint32_t mode:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} sha_3_mode_reg_t; - -/** Type of clean_m register - * Initial configuration register 1. - */ -typedef union { - struct { - /** clean_m : WO; bitpos: [0]; default: 0; - * Clean Message. - */ - uint32_t clean_m:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_clean_m_reg_t; - -/** Type of dma_block_num register - * DMA configuration register 0. - */ -typedef union { - struct { - /** dma_block_num : R/W; bitpos: [5:0]; default: 0; - * DMA-SHA3 block number. - */ - uint32_t dma_block_num:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} sha_3_dma_block_num_reg_t; - -/** Type of start register - * Typical SHA3 configuration register 0. - */ -typedef union { - struct { - /** start : WO; bitpos: [0]; default: 0; - * Start typical sha3. - */ - uint32_t start:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_start_reg_t; - -/** Type of continue register - * Typical SHA3 configuration register 1. - */ -typedef union { - struct { - /** conti : WO; bitpos: [0]; default: 0; - * Continue typical sha3. - */ - uint32_t conti:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_continue_reg_t; - -/** Type of dma_start register - * DMA configuration register 1. - */ -typedef union { - struct { - /** dma_start : WO; bitpos: [0]; default: 0; - * Start dma-sha3. - */ - uint32_t dma_start:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_dma_start_reg_t; - -/** Type of dma_continue register - * DMA configuration register 2. - */ -typedef union { - struct { - /** dma_continue : WO; bitpos: [0]; default: 0; - * Continue dma-sha3. - */ - uint32_t dma_continue:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_dma_continue_reg_t; - -/** Type of shake_length register - * DMA configuration register 3. - */ -typedef union { - struct { - /** shake_length : WO; bitpos: [10:0]; default: 50; - * SHAKE output hash word length - */ - uint32_t shake_length:11; - uint32_t reserved_11:21; - }; - uint32_t val; -} sha_3_shake_length_reg_t; - /** Group: Status Registers */ /** Type of busy register @@ -306,52 +194,6 @@ typedef union { /** Group: memory type */ -/** Group: Status Register */ -/** Type of busy register - * Busy register. - */ -typedef union { - struct { - /** busy_reg : RO; bitpos: [0]; default: 0; - * Sha3 busy state. 1'b0: idle. 1'b1: busy. - */ - uint32_t busy_reg:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_busy_reg_t; - - -/** Group: Interrupt Register */ -/** Type of clear_int register - * Interrupt clear register. - */ -typedef union { - struct { - /** clear_int : WO; bitpos: [0]; default: 0; - * Clear sha3 interrupt. - */ - uint32_t clear_int:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_clear_int_reg_t; - -/** Type of int_ena register - * Interrupt enable register. - */ -typedef union { - struct { - /** int_ena : R/W; bitpos: [0]; default: 0; - * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable - */ - uint32_t int_ena:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_int_ena_reg_t; - - typedef struct { volatile sha_mode_reg_t mode; volatile sha_t_string_reg_t t_string; @@ -368,29 +210,12 @@ typedef struct { uint32_t reserved_030[4]; volatile uint32_t h[16]; volatile uint32_t m[16]; - uint32_t reserved_0c0[464]; - volatile sha_3_mode_reg_t mode_3; - volatile sha_3_clean_m_reg_t clean_m_3; - uint32_t reserved_808; - volatile sha_3_dma_block_num_reg_t dma_block_num_3; - volatile sha_3_start_reg_t start_3; - volatile sha_3_continue_reg_t continue_3; - volatile sha_3_busy_reg_t busy_3; - volatile sha_3_dma_start_reg_t dma_start_3; - volatile sha_3_dma_continue_reg_t dma_continue_3; - volatile sha_3_clear_int_reg_t clear_int_3; - volatile sha_3_int_ena_reg_t int_ena_3; - volatile sha_3_shake_length_reg_t shake_length_3; - uint32_t reserved_830[52]; - volatile uint32_t m_out_3[50]; - uint32_t reserved_9c8[14]; - volatile uint32_t m_3[50]; } sha_dev_t; extern sha_dev_t SHA; #ifndef __cplusplus -_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure"); +_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/soc/sha_reg.h b/components/soc/esp32c61/include/soc/sha_reg.h index d49c15e267..ab9f346e77 100644 --- a/components/soc/esp32c61/include/soc/sha_reg.h +++ b/components/soc/esp32c61/include/soc/sha_reg.h @@ -172,150 +172,6 @@ extern "C" { #define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) #define SHA_M_MEM_SIZE_BYTES 64 -/** SHA_3_MODE_REG register - * Initial configuration register 0. - */ -#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800) -/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0; - * Sha3 mode - */ -#define SHA_3_MODE 0x00000007U -#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S) -#define SHA_3_MODE_V 0x00000007U -#define SHA_3_MODE_S 0 - -/** SHA_3_CLEAN_M_REG register - * Initial configuration register 1. - */ -#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804) -/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0; - * Clean Message. - */ -#define SHA_3_CLEAN_M (BIT(0)) -#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S) -#define SHA_3_CLEAN_M_V 0x00000001U -#define SHA_3_CLEAN_M_S 0 - -/** SHA_3_DMA_BLOCK_NUM_REG register - * DMA configuration register 0. - */ -#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c) -/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; - * DMA-SHA3 block number. - */ -#define SHA_3_DMA_BLOCK_NUM 0x0000003FU -#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S) -#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU -#define SHA_3_DMA_BLOCK_NUM_S 0 - -/** SHA_3_START_REG register - * Typical SHA3 configuration register 0. - */ -#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810) -/** SHA_3_START : WO; bitpos: [0]; default: 0; - * Start typical sha3. - */ -#define SHA_3_START (BIT(0)) -#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S) -#define SHA_3_START_V 0x00000001U -#define SHA_3_START_S 0 - -/** SHA_3_CONTINUE_REG register - * Typical SHA3 configuration register 1. - */ -#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814) -/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0; - * Continue typical sha3. - */ -#define SHA_3_CONTINUE (BIT(0)) -#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S) -#define SHA_3_CONTINUE_V 0x00000001U -#define SHA_3_CONTINUE_S 0 - -/** SHA_3_BUSY_REG register - * Busy register. - */ -#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818) -/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0; - * Sha3 busy state. 1'b0: idle. 1'b1: busy. - */ -#define SHA_3_BUSY_REG (BIT(0)) -#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S) -#define SHA_3_BUSY_REG_V 0x00000001U -#define SHA_3_BUSY_REG_S 0 - -/** SHA_3_DMA_START_REG register - * DMA configuration register 1. - */ -#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c) -/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0; - * Start dma-sha3. - */ -#define SHA_3_DMA_START (BIT(0)) -#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S) -#define SHA_3_DMA_START_V 0x00000001U -#define SHA_3_DMA_START_S 0 - -/** SHA_3_DMA_CONTINUE_REG register - * DMA configuration register 2. - */ -#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820) -/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0; - * Continue dma-sha3. - */ -#define SHA_3_DMA_CONTINUE (BIT(0)) -#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S) -#define SHA_3_DMA_CONTINUE_V 0x00000001U -#define SHA_3_DMA_CONTINUE_S 0 - -/** SHA_3_CLEAR_INT_REG register - * Interrupt clear register. - */ -#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824) -/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0; - * Clear sha3 interrupt. - */ -#define SHA_3_CLEAR_INT (BIT(0)) -#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S) -#define SHA_3_CLEAR_INT_V 0x00000001U -#define SHA_3_CLEAR_INT_S 0 - -/** SHA_3_INT_ENA_REG register - * Interrupt enable register. - */ -#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828) -/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0; - * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable - */ -#define SHA_3_INT_ENA (BIT(0)) -#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S) -#define SHA_3_INT_ENA_V 0x00000001U -#define SHA_3_INT_ENA_S 0 - -/** SHA_3_SHAKE_LENGTH_REG register - * DMA configuration register 3. - */ -#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c) -/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50; - * SHAKE output hash word length - */ -#define SHA_3_SHAKE_LENGTH 0x000007FFU -#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S) -#define SHA_3_SHAKE_LENGTH_V 0x000007FFU -#define SHA_3_SHAKE_LENGTH_S 0 - -/** SHA_3_M_OUT_MEM register - * Sha3 hash reg which contains intermediate hash or finial hash. - */ -#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900) -#define SHA_3_M_OUT_MEM_SIZE_BYTES 200 - -/** SHA_3_M_MEM register - * Sha3 message reg which contains message. - */ -#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00) -#define SHA_3_M_MEM_SIZE_BYTES 200 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c61/include/soc/sha_struct.h b/components/soc/esp32c61/include/soc/sha_struct.h index a297423e8f..058b8a88f6 100644 --- a/components/soc/esp32c61/include/soc/sha_struct.h +++ b/components/soc/esp32c61/include/soc/sha_struct.h @@ -127,118 +127,6 @@ typedef union { uint32_t val; } sha_t_length_reg_t; -/** Type of mode_3 register - * Initial configuration register 0. - */ -typedef union { - struct { - /** mode_3 : R/W; bitpos: [2:0]; default: 0; - * Sha3 mode - */ - uint32_t mode_3:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} sha_3_mode_reg_t; - -/** Type of clean_m_3 register - * Initial configuration register 1. - */ -typedef union { - struct { - /** clean_m_3 : WO; bitpos: [0]; default: 0; - * Clean Message. - */ - uint32_t clean_m_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_clean_m_reg_t; - -/** Type of dma_block_num_3 register - * DMA configuration register 0. - */ -typedef union { - struct { - /** dma_block_num_3 : R/W; bitpos: [5:0]; default: 0; - * DMA-SHA3 block number. - */ - uint32_t dma_block_num_3:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} sha_3_dma_block_num_reg_t; - -/** Type of start_3 register - * Typical SHA3 configuration register 0. - */ -typedef union { - struct { - /** start_3 : WO; bitpos: [0]; default: 0; - * Start typical sha3. - */ - uint32_t start_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_start_reg_t; - -/** Type of continue_3 register - * Typical SHA3 configuration register 1. - */ -typedef union { - struct { - /** continue_3 : WO; bitpos: [0]; default: 0; - * Continue typical sha3. - */ - uint32_t continue_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_continue_reg_t; - -/** Type of dma_start_3 register - * DMA configuration register 1. - */ -typedef union { - struct { - /** dma_start_3 : WO; bitpos: [0]; default: 0; - * Start dma-sha3. - */ - uint32_t dma_start_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_dma_start_reg_t; - -/** Type of dma_continue_3 register - * DMA configuration register 2. - */ -typedef union { - struct { - /** dma_continue_3 : WO; bitpos: [0]; default: 0; - * Continue dma-sha3. - */ - uint32_t dma_continue_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_dma_continue_reg_t; - -/** Type of shake_length_3 register - * DMA configuration register 3. - */ -typedef union { - struct { - /** shake_length_3 : WO; bitpos: [10:0]; default: 50; - * SHAKE output hash word length - */ - uint32_t shake_length_3:11; - uint32_t reserved_11:21; - }; - uint32_t val; -} sha_3_shake_length_reg_t; - /** Group: Status Registers */ /** Type of busy register @@ -306,52 +194,6 @@ typedef union { /** Group: memory type */ -/** Group: Status Register */ -/** Type of busy_3 register - * Busy register. - */ -typedef union { - struct { - /** busy_reg_3 : RO; bitpos: [0]; default: 0; - * Sha3 busy state. 1'b0: idle. 1'b1: busy. - */ - uint32_t busy_reg_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_busy_reg_t; - - -/** Group: Interrupt Register */ -/** Type of clear_int_3 register - * Interrupt clear register. - */ -typedef union { - struct { - /** clear_int_3 : WO; bitpos: [0]; default: 0; - * Clear sha3 interrupt. - */ - uint32_t clear_int_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_clear_int_reg_t; - -/** Type of int_ena_3 register - * Interrupt enable register. - */ -typedef union { - struct { - /** int_ena_3 : R/W; bitpos: [0]; default: 0; - * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable - */ - uint32_t int_ena_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sha_3_int_ena_reg_t; - - typedef struct { volatile sha_mode_reg_t mode; volatile sha_t_string_reg_t t_string; @@ -368,29 +210,12 @@ typedef struct { uint32_t reserved_030[4]; volatile uint32_t h[16]; volatile uint32_t m[16]; - uint32_t reserved_0c0[464]; - volatile sha_3_mode_reg_t mode_3; - volatile sha_3_clean_m_reg_t clean_m_3; - uint32_t reserved_808; - volatile sha_3_dma_block_num_reg_t dma_block_num_3; - volatile sha_3_start_reg_t start_3; - volatile sha_3_continue_reg_t continue_3; - volatile sha_3_busy_reg_t busy_3; - volatile sha_3_dma_start_reg_t dma_start_3; - volatile sha_3_dma_continue_reg_t dma_continue_3; - volatile sha_3_clear_int_reg_t clear_int_3; - volatile sha_3_int_ena_reg_t int_ena_3; - volatile sha_3_shake_length_reg_t shake_length_3; - uint32_t reserved_830[52]; - volatile uint32_t m_out_3[50]; - uint32_t reserved_9c8[14]; - volatile uint32_t m_3[50]; } sha_dev_t; extern sha_dev_t SHA; #ifndef __cplusplus -_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure"); +_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure"); #endif #ifdef __cplusplus