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build and link hello-world for esp32s2beta

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This commit is contained in:
suda-morris
2019-06-06 10:57:29 +08:00
parent 61ce868396
commit 84b2f9f14d
108 changed files with 3377 additions and 645 deletions
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4
components/driver/can.c
View File

@@ -11,7 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#include "freertos/task.h"
@@ -25,6 +25,7 @@
#include "driver/gpio.h"
#include "driver/periph_ctrl.h"
#include "driver/can.h"
#if CONFIG_IDF_TARGET_ESP32
/* ---------------------------- Definitions --------------------------------- */
//Internal Macros
@@ -1004,3 +1005,4 @@ esp_err_t can_clear_receive_queue()
return ESP_OK;
}
#endif

12
components/driver/gpio.c
View File

@@ -212,7 +212,11 @@ esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
{
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
#if CONFIG_IDF_TARGET_ESP32
if (gpio_num >= 34 && (mode & GPIO_MODE_DEF_OUTPUT)) {
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if (gpio_num >= 46 && (mode & GPIO_MODE_DEF_OUTPUT)) {
#endif
ESP_LOGE(GPIO_TAG, "io_num=%d can only be input", gpio_num);
return ESP_ERR_INVALID_ARG;
}
@@ -516,7 +520,11 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num)
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
r = rtc_gpio_hold_en(gpio_num);
} else if (GPIO_HOLD_MASK[gpio_num]) {
#if CONFIG_IDF_TARGET_ESP32
SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
#endif
} else {
r = ESP_ERR_NOT_SUPPORTED;
}
@@ -530,7 +538,11 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
if (RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
r = rtc_gpio_hold_dis(gpio_num);
} else if (GPIO_HOLD_MASK[gpio_num]) {
#if CONFIG_IDF_TARGET_ESP32
CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
#endif
} else {
r = ESP_ERR_NOT_SUPPORTED;
}

12
components/driver/i2s.c
View File

@@ -34,6 +34,9 @@
#include "esp_err.h"
#include "esp_log.h"
#include "esp_pm.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
static const char* I2S_TAG = "I2S";
@@ -453,12 +456,20 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
I2S[i2s_num]->clkm_conf.clkm_div_a = 1;
I2S[i2s_num]->sample_rate_conf.tx_bck_div_num = m_scale;
I2S[i2s_num]->sample_rate_conf.rx_bck_div_num = m_scale;
#if CONFIG_IDF_TARGET_ESP32
I2S[i2s_num]->clkm_conf.clka_en = 1;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
I2S[i2s_num]->clkm_conf.clk_sel = 1;
#endif
double fi2s_rate = i2s_apll_get_fi2s(bits, sdm0, sdm1, sdm2, odir);
ESP_LOGI(I2S_TAG, "APLL: Req RATE: %d, real rate: %0.3f, BITS: %u, CLKM: %u, BCK_M: %u, MCLK: %0.3f, SCLK: %f, diva: %d, divb: %d",
rate, fi2s_rate/bits/channel/m_scale, bits, 1, m_scale, fi2s_rate, fi2s_rate/8, 1, 0);
} else {
#if CONFIG_IDF_TARGET_ESP32
I2S[i2s_num]->clkm_conf.clka_en = 0;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
I2S[i2s_num]->clkm_conf.clk_sel = 2;
#endif
I2S[i2s_num]->clkm_conf.clkm_div_a = 63;
I2S[i2s_num]->clkm_conf.clkm_div_b = clkmDecimals;
I2S[i2s_num]->clkm_conf.clkm_div_num = clkmInteger;
@@ -1378,3 +1389,4 @@ int i2s_pop_sample(i2s_port_t i2s_num, void *sample, TickType_t ticks_to_wait)
return bytes_pop;
}
}
#endif

67
components/driver/include/driver/gpio.h
View File

@@ -76,6 +76,7 @@ extern "C" {
#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */
#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */
#if CONFIG_IDF_TARGET_ESP32
#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG
#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG
@@ -111,6 +112,56 @@ extern "C" {
#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG
#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG
#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG
#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG
#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG
#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG
#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG
#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG
#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG
#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG
#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG
#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG
#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG
#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG
#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG
#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG
#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG
#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG
#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG
#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG
#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG
#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG
#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG
#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG
#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG
#define GPIO_PIN_REG_24 IO_MUX_GPIO24_REG
#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG
#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG
#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG
#define GPIO_PIN_REG_28 IO_MUX_GPIO28_REG
#define GPIO_PIN_REG_29 IO_MUX_GPIO29_REG
#define GPIO_PIN_REG_30 IO_MUX_GPIO30_REG
#define GPIO_PIN_REG_31 IO_MUX_GPIO31_REG
#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG
#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG
#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG
#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG
#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG
#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG
#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG
#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG
#define GPIO_PIN_REG_40 IO_MUX_GPIO40_REG
#define GPIO_PIN_REG_41 IO_MUX_GPIO41_REG
#define GPIO_PIN_REG_42 IO_MUX_GPIO42_REG
#define GPIO_PIN_REG_43 IO_MUX_GPIO43_REG
#define GPIO_PIN_REG_44 IO_MUX_GPIO44_REG
#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG
#endif
#define GPIO_APP_CPU_INTR_ENA (BIT(0))
#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1))
@@ -127,7 +178,11 @@ extern "C" {
/** @endcond */
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
#if CONFIG_IDF_TARGET_ESP32
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) /*!< Check whether it can be a valid GPIO number of output mode */
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */
#endif
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
@@ -173,7 +228,19 @@ typedef enum {
GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */
GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */
GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */
#if CONFIG_IDF_TARGET_ESP32
GPIO_NUM_MAX = 40,
#elif CONFIG_IDF_TARGET_ESP32S2BETA
GPIO_NUM_40 = 40, /*!< GPIO40, input mode only */
GPIO_NUM_41 = 41, /*!< GPIO41, input mode only */
GPIO_NUM_42 = 42, /*!< GPIO42, input mode only */
GPIO_NUM_43 = 43, /*!< GPIO43, input mode only */
GPIO_NUM_44 = 44, /*!< GPIO44, input mode only */
GPIO_NUM_45 = 45, /*!< GPIO45, input mode only */
GPIO_NUM_46 = 46, /*!< GPIO46, input mode only */
GPIO_NUM_47 = 47, /*!< GPIO47, input mode only */
GPIO_NUM_MAX = 48,
#endif
/** @endcond */
} gpio_num_t;

42
components/driver/include/driver/spi_common.h
View File

@@ -61,15 +61,52 @@ extern "C"
*/
#define SPI_SWAP_DATA_RX(data, len) (__builtin_bswap32(data)>>(32-len))
/**
* Transform unsigned integer of length <= 32 bits to the format which can be
* sent by the SPI driver directly.
*
* E.g. to send 9 bits of data, you can:
*
* uint16_t data = SPI_SWAP_DATA_TX(0x145, 9);
*
* Then points tx_buffer to ``&data``.
*
* @param data Data to be sent, can be uint8_t, uint16_t or uint32_t. @param
* len Length of data to be sent, since the SPI peripheral sends from the MSB,
* this helps to shift the data to the MSB.
*/
#define SPI_SWAP_DATA_TX(data, len) __builtin_bswap32((uint32_t)data<<(32-len))
/**
* Transform received data of length <= 32 bits to the format of an unsigned integer.
*
* E.g. to transform the data of 15 bits placed in a 4-byte array to integer:
*
* uint16_t data = SPI_SWAP_DATA_RX(*(uint32_t*)t->rx_data, 15);
*
* @param data Data to be rearranged, can be uint8_t, uint16_t or uint32_t.
* @param len Length of data received, since the SPI peripheral writes from
* the MSB, this helps to shift the data to the LSB.
*/
#define SPI_SWAP_DATA_RX(data, len) (__builtin_bswap32(data)>>(32-len))
/**
* @brief Enum with the three SPI peripherals that are software-accessible in it
*/
#if CONFIG_IDF_TARGET_ESP32
typedef enum {
SPI_HOST=0, ///< SPI1, SPI
HSPI_HOST=1, ///< SPI2, HSPI
VSPI_HOST=2 ///< SPI3, VSPI
} spi_host_device_t;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
typedef enum {
SPI_HOST=0, ///< SPI1, SPI
FSPI_HOST=1, ///< SPI2, FSPI
HSPI_HOST=2, ///< SPI3, HSPI
VSPI_HOST=3 ///< SPI4, VSPI
} spi_host_device_t;
#endif
/**
* @brief This is a configuration structure for a SPI bus.
*
@@ -85,6 +122,9 @@ typedef struct {
int sclk_io_num; ///< GPIO pin for Spi CLocK signal, or -1 if not used.
int quadwp_io_num; ///< GPIO pin for WP (Write Protect) signal which is used as D2 in 4-bit communication modes, or -1 if not used.
int quadhd_io_num; ///< GPIO pin for HD (HolD) signal which is used as D3 in 4-bit communication modes, or -1 if not used.
#if CONFIG_IDF_TARGET_ESP32S2BETA
int spicd_io_num; ///< CD GPIO pin for this device, or -1 if not used
#endif
int max_transfer_sz; ///< Maximum transfer size, in bytes. Defaults to 4094 if 0.
uint32_t flags; ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags.
int intr_flags; /**< Interrupt flag for the bus to set the priority, and IRAM attribute, see

16
components/driver/include/driver/spi_master.h
View File

@@ -25,6 +25,7 @@
/** SPI master clock is divided by 80MHz apb clock. Below defines are example frequencies, and are accurate. Be free to specify a random frequency, it will be rounded to closest frequency (to macros below if above 8MHz).
* 8MHz
*/
#if APB_CLK_FREQ==80*1000*1000
#define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10)
#define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) ///< 8.89MHz
#define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) ///< 10MHz
@@ -35,7 +36,14 @@
#define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) ///< 26.67MHz
#define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) ///< 40MHz
#define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) ///< 80MHz
#elif APB_CLK_FREQ==40*1000*1000
#define SPI_MASTER_FREQ_7M (APB_CLK_FREQ/6) ///< 13.33MHz
#define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/5) ///< 16MHz
#define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/4) ///< 20MHz
#define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/3) ///< 26.67MHz
#define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/2) ///< 40MHz
#define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/1) ///< 80MHz
#endif
#ifdef __cplusplus
extern "C"
{
@@ -54,6 +62,7 @@ extern "C"
* Set this flag to confirm that you're going to work with output only, or read without dummy bits at your own risk.
*/
#define SPI_DEVICE_NO_DUMMY (1<<6)
#define SPI_DEVICE_DDRCLK (1<<7)
typedef struct spi_transaction_t spi_transaction_t;
@@ -67,8 +76,8 @@ typedef struct {
uint8_t address_bits; ///< Default amount of bits in address phase (0-64), used when ``SPI_TRANS_VARIABLE_ADDR`` is not used, otherwise ignored.
uint8_t dummy_bits; ///< Amount of dummy bits to insert between address and data phase
uint8_t mode; ///< SPI mode (0-3)
uint8_t duty_cycle_pos; ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128.
uint8_t cs_ena_pretrans; ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions.
uint16_t duty_cycle_pos; ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128.
uint16_t cs_ena_pretrans; ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions.
uint8_t cs_ena_posttrans; ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)
int clock_speed_hz; ///< Clock speed, divisors of 80MHz, in Hz. See ``SPI_MASTER_FREQ_*``.
int input_delay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO
@@ -110,6 +119,7 @@ typedef struct {
#define SPI_TRANS_VARIABLE_CMD (1<<5) ///< Use the ``command_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
#define SPI_TRANS_VARIABLE_ADDR (1<<6) ///< Use the ``address_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
#define SPI_TRANS_VARIABLE_DUMMY (1<<7) ///< Use the ``dummy_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
#define SPI_TRANS_SET_CD (1<<7) ///< Set the CD pin
/**
* This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes.

4
components/driver/ledc.c
View File

@@ -278,7 +278,9 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
if (speed_mode == LEDC_HIGH_SPEED_MODE) {
#if CONFIG_IDF_TARGET_ESP32
gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0);
#endif
} else {
gpio_matrix_out(gpio_num, LEDC_LS_SIG_OUT0_IDX + ledc_channel, 0, 0);
}
@@ -318,7 +320,9 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf)
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
if (speed_mode == LEDC_HIGH_SPEED_MODE) {
#if CONFIG_IDF_TARGET_ESP32
gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0);
#endif
} else {
gpio_matrix_out(gpio_num, LEDC_LS_SIG_OUT0_IDX + ledc_channel, 0, 0);
}

6
components/driver/mcpwm.c
View File

@@ -23,6 +23,9 @@
#include "soc/gpio_periph.h"
#include "driver/mcpwm.h"
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
static mcpwm_dev_t *MCPWM[2] = {&MCPWM0, &MCPWM1};
static const char *MCPWM_TAG = "MCPWM";
@@ -41,7 +44,7 @@ static portMUX_TYPE mcpwm_spinlock = portMUX_INITIALIZER_UNLOCKED;
#define MCPWM_DB_ERROR "MCPWM DEADTIME TYPE ERROR"
#define MCPWM_BASE_CLK (2 * APB_CLK_FREQ) //2*APB_CLK_FREQ 160Mhz
#define MCPWM_CLK_PRESCL 15 //MCPWM clock prescale
#define MCPWM_CLK_PRESCL 15 //MCPWM clock prescale
#define TIMER_CLK_PRESCALE 9 //MCPWM timer prescales
#define MCPWM_CLK (MCPWM_BASE_CLK/(MCPWM_CLK_PRESCL +1))
#define MCPWM_PIN_IGNORE (-1)
@@ -727,3 +730,4 @@ esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *a
ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
return ret;
}
#endif

10
components/driver/pcnt.c
View File

@@ -101,11 +101,11 @@ esp_err_t pcnt_set_pin(pcnt_unit_t unit, pcnt_channel_t channel, int pulse_io, i
PCNT_CHECK(channel < PCNT_CHANNEL_MAX, PCNT_CHANNEL_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_CHECK(GPIO_IS_VALID_GPIO(pulse_io) || pulse_io < 0, PCNT_GPIO_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_CHECK(GPIO_IS_VALID_GPIO(ctrl_io) || ctrl_io < 0, PCNT_GPIO_ERR_STR, ESP_ERR_INVALID_ARG);
int sig_base = (channel == 0) ? PCNT_SIG_CH0_IN0_IDX : PCNT_SIG_CH1_IN0_IDX;
int ctrl_base = (channel == 0) ? PCNT_CTRL_CH0_IN0_IDX : PCNT_CTRL_CH1_IN0_IDX;
if (unit > 4) {
sig_base += 12; // GPIO matrix assignments have a gap between units 4 & 5
if (unit > 4) {
sig_base += 12; // GPIO matrix assignments have a gap between units 4 & 5
ctrl_base += 12;
}
int input_sig_index = sig_base + (4 * unit);
@@ -156,7 +156,11 @@ esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit)
{
PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_ENTER_CRITICAL(&pcnt_spinlock);
#if CONFIG_IDF_TARGET_ESP32
uint32_t reset_bit = BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2));
#elif CONFIG_IDF_TARGET_ESP32S2BETA
uint32_t reset_bit = BIT(PCNT_PULSE_CNT_RST_U0_S + (pcnt_unit * 2));
#endif
PCNT.ctrl.val |= reset_bit;
PCNT.ctrl.val &= ~reset_bit;
PCNT_EXIT_CRITICAL(&pcnt_spinlock);

64
components/driver/periph_ctrl.c
View File

@@ -16,7 +16,9 @@
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "soc/dport_reg.h"
#include "soc/syscon_reg.h"
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
@@ -61,8 +63,13 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
return DPORT_UART_CLK_EN;
case PERIPH_UART1_MODULE:
return DPORT_UART1_CLK_EN;
#if CONFIG_IDF_TARGET_ESP32
case PERIPH_UART2_MODULE:
return DPORT_UART2_CLK_EN;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
case PERIPH_USB_MODULE:
return DPORT_USB_CLK_EN;
#endif
case PERIPH_I2C0_MODULE:
return DPORT_I2C_EXT0_CLK_EN;
case PERIPH_I2C1_MODULE:
@@ -91,12 +98,27 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
return DPORT_PCNT_CLK_EN;
case PERIPH_SPI_MODULE:
return DPORT_SPI01_CLK_EN;
#if CONFIG_IDF_TARGET_ESP32
case PERIPH_HSPI_MODULE:
return DPORT_SPI2_CLK_EN;
case PERIPH_VSPI_MODULE:
return DPORT_SPI3_CLK_EN;
case PERIPH_SPI_DMA_MODULE:
return DPORT_SPI_DMA_CLK_EN;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
case PERIPH_FSPI_MODULE:
return DPORT_SPI2_CLK_EN;
case PERIPH_HSPI_MODULE:
return DPORT_SPI3_CLK_EN;
case PERIPH_VSPI_MODULE:
return DPORT_SPI4_CLK_EN;
case PERIPH_SPI2_DMA_MODULE:
return DPORT_SPI2_DMA_CLK_EN;
case PERIPH_SPI3_DMA_MODULE:
return DPORT_SPI3_DMA_CLK_EN;
case PERIPH_SPI_SHARED_DMA_MODULE:
return DPORT_SPI_SHARED_DMA_CLK_EN;
#endif
case PERIPH_SDMMC_MODULE:
return DPORT_WIFI_CLK_SDIO_HOST_EN;
case PERIPH_SDIO_SLAVE_MODULE:
@@ -117,12 +139,14 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
return DPORT_BT_BASEBAND_EN;
case PERIPH_BT_LC_MODULE:
return DPORT_BT_LC_EN;
#if CONFIG_IDF_TARGET_ESP32
case PERIPH_AES_MODULE:
return DPORT_PERI_EN_AES;
case PERIPH_SHA_MODULE:
return DPORT_PERI_EN_SHA;
case PERIPH_RSA_MODULE:
return DPORT_PERI_EN_RSA;
#endif
default:
return 0;
}
@@ -139,8 +163,13 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
return DPORT_UART_RST;
case PERIPH_UART1_MODULE:
return DPORT_UART1_RST;
#if CONFIG_IDF_TARGET_ESP32
case PERIPH_UART2_MODULE:
return DPORT_UART2_RST;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
case PERIPH_USB_MODULE:
return DPORT_USB_RST;
#endif
case PERIPH_I2C0_MODULE:
return DPORT_I2C_EXT0_RST;
case PERIPH_I2C1_MODULE:
@@ -169,12 +198,27 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
return DPORT_PCNT_RST;
case PERIPH_SPI_MODULE:
return DPORT_SPI01_RST;
#if CONFIG_IDF_TARGET_ESP32
case PERIPH_HSPI_MODULE:
return DPORT_SPI2_RST;
case PERIPH_VSPI_MODULE:
return DPORT_SPI3_RST;
case PERIPH_SPI_DMA_MODULE:
return DPORT_SPI_DMA_RST;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
case PERIPH_FSPI_MODULE:
return DPORT_SPI2_RST;
case PERIPH_HSPI_MODULE:
return DPORT_SPI3_RST;
case PERIPH_VSPI_MODULE:
return DPORT_SPI4_RST;
case PERIPH_SPI2_DMA_MODULE:
return DPORT_SPI2_DMA_RST;
case PERIPH_SPI3_DMA_MODULE:
return DPORT_SPI3_DMA_RST;
case PERIPH_SPI_SHARED_DMA_MODULE:
return DPORT_SPI_SHARED_DMA_RST;
#endif
case PERIPH_SDMMC_MODULE:
return DPORT_SDIO_HOST_RST;
case PERIPH_SDIO_SLAVE_MODULE:
@@ -183,6 +227,7 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
return DPORT_CAN_RST;
case PERIPH_EMAC_MODULE:
return DPORT_EMAC_RST;
#if CONFIG_IDF_TARGET_ESP32
case PERIPH_AES_MODULE:
if (enable == true) {
// Clear reset on digital signature & secure boot units, otherwise AES unit is held in reset also.
@@ -207,6 +252,7 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
// Don't reset digital signature unit, as this resets AES also
return DPORT_PERI_EN_RSA;
}
#endif
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
case PERIPH_WIFI_BT_COMMON_MODULE:
@@ -240,18 +286,32 @@ static bool is_wifi_clk_peripheral(periph_module_t periph)
static uint32_t get_clk_en_reg(periph_module_t periph)
{
#if CONFIG_IDF_TARGET_ESP32
if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
return DPORT_PERI_CLK_EN_REG;
} else {
}
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if(periph == PERIPH_SPI_SHARED_DMA_MODULE) {
return DPORT_PERIP_CLK_EN1_REG;
}
#endif
else {
return is_wifi_clk_peripheral(periph) ? DPORT_WIFI_CLK_EN_REG : DPORT_PERIP_CLK_EN_REG;
}
}
static uint32_t get_rst_en_reg(periph_module_t periph)
{
#if CONFIG_IDF_TARGET_ESP32
if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
return DPORT_PERI_RST_EN_REG;
} else {
}
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if(periph == PERIPH_SPI_SHARED_DMA_MODULE){
return DPORT_PERIP_CLK_EN1_REG;
}
#endif
else {
return is_wifi_clk_peripheral(periph) ? DPORT_CORE_RST_EN_REG : DPORT_PERIP_RST_EN_REG;
}
}

4
components/driver/rmt.c
View File

@@ -317,7 +317,11 @@ esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool* idle_out_en, rmt_idle_
esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t* status)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
#if CONFIG_IDF_TARGET_ESP32
*status = RMT.status_ch[channel];
#elif CONFIG_IDF_TARGET_ESP32S2BETA
*status = RMT.status_ch[channel].val;
#endif
return ESP_OK;
}

76
components/driver/rtc_module.c
View File

@@ -15,12 +15,12 @@
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "esp32/rom/ets_sys.h"
#include "esp_log.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/syscon_periph.h"
#include "soc/rtc.h"
#include "soc/periph_defs.h"
#include "rtc_io.h"
#include "touch_pad.h"
#include "adc.h"
@@ -34,6 +34,12 @@
#include "driver/rtc_cntl.h"
#include "driver/gpio.h"
#include "adc1_i2s_private.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds
@@ -83,14 +89,14 @@ portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;
static SemaphoreHandle_t rtc_touch_mux = NULL;
/*
In ADC2, there're two locks used for different cases:
1. lock shared with app and WIFI:
when wifi using the ADC2, we assume it will never stop,
1. lock shared with app and WIFI:
when wifi using the ADC2, we assume it will never stop,
so app checks the lock and returns immediately if failed.
2. lock shared between tasks:
when several tasks sharing the ADC2, we want to guarantee
2. lock shared between tasks:
when several tasks sharing the ADC2, we want to guarantee
all the requests will be handled.
Since conversions are short (about 31us), app returns the lock very soon,
Since conversions are short (about 31us), app returns the lock very soon,
we use a spinlock to stand there waiting to do conversions one by one.
adc2_spinlock should be acquired first, then adc2_wifi_lock or rtc_spinlock.
@@ -373,7 +379,9 @@ void rtc_gpio_force_hold_dis_all()
for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio];
if (desc->hold_force != 0) {
#if CONFIG_IDF_TARGET_ESP32
REG_CLR_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold_force);
#endif
}
}
}
@@ -432,13 +440,21 @@ inline static touch_pad_t touch_pad_num_wrap(touch_pad_t touch_num)
esp_err_t touch_pad_isr_handler_register(void (*fn)(void *), void *arg, int no_use, intr_handle_t *handle_no_use)
{
RTC_MODULE_CHECK(fn, "Touch_Pad ISR null", ESP_ERR_INVALID_ARG);
#if CONFIG_IDF_TARGET_ESP32
return rtc_isr_register(fn, arg, RTC_CNTL_TOUCH_INT_ST_M);
#else
return ESP_FAIL;
#endif
}
esp_err_t touch_pad_isr_register(intr_handler_t fn, void* arg)
{
RTC_MODULE_CHECK(fn, "Touch_Pad ISR null", ESP_ERR_INVALID_ARG);
#if CONFIG_IDF_TARGET_ESP32
return rtc_isr_register(fn, arg, RTC_CNTL_TOUCH_INT_ST_M);
#else
return ESP_FAIL;
#endif
}
esp_err_t touch_pad_isr_deregister(intr_handler_t fn, void *arg)
@@ -566,7 +582,7 @@ esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, t
ESP_ERR_INVALID_ARG);
RTC_MODULE_CHECK(((atten < TOUCH_HVOLT_ATTEN_MAX) && (refh >= (int )TOUCH_HVOLT_ATTEN_KEEP)), "touch atten error",
ESP_ERR_INVALID_ARG);
#if CONFIG_IDF_TARGET_ESP32
portENTER_CRITICAL(&rtc_spinlock);
if (refh > TOUCH_HVOLT_KEEP) {
RTCIO.touch_cfg.drefh = refh;
@@ -578,11 +594,13 @@ esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, t
RTCIO.touch_cfg.drange = atten;
}
portEXIT_CRITICAL(&rtc_spinlock);
#endif
return ESP_OK;
}
esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl, touch_volt_atten_t *atten)
{
#if CONFIG_IDF_TARGET_ESP32
portENTER_CRITICAL(&rtc_spinlock);
if (refh) {
*refh = RTCIO.touch_cfg.drefh;
@@ -594,6 +612,7 @@ esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl,
*atten = RTCIO.touch_cfg.drange;
}
portEXIT_CRITICAL(&rtc_spinlock);
#endif
return ESP_OK;
}
@@ -601,7 +620,7 @@ esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope,
{
RTC_MODULE_CHECK((slope < TOUCH_PAD_SLOPE_MAX), "touch slope error", ESP_ERR_INVALID_ARG);
RTC_MODULE_CHECK((opt < TOUCH_PAD_TIE_OPT_MAX), "touch opt error", ESP_ERR_INVALID_ARG);
touch_pad_t touch_pad_wrap = touch_pad_num_wrap(touch_num);
portENTER_CRITICAL(&rtc_spinlock);
RTCIO.touch_pad[touch_pad_wrap].tie_opt = opt;
@@ -613,7 +632,7 @@ esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope,
esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope, touch_tie_opt_t *opt)
{
RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG);
touch_pad_t touch_pad_wrap = touch_pad_num_wrap(touch_num);
portENTER_CRITICAL(&rtc_spinlock);
if(opt) {
@@ -1152,7 +1171,7 @@ void adc_power_on()
#ifndef CONFIG_ADC_FORCE_XPD_FSM
//Set the power always on to increase precision.
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
#else
#else
//Use the FSM to turn off the power while not used to save power.
if (SENS.sar_meas_wait2.force_xpd_sar & SENS_FORCE_XPD_SAR_SW_M) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
@@ -1266,12 +1285,12 @@ static void adc_set_controller(adc_unit_t unit, adc_controller_t ctrl )
break;
default:
ESP_LOGE(TAG, "adc1 selects invalid controller");
break;
break;
}
} else if ( unit == ADC_UNIT_2) {
switch( ctrl ) {
case ADC_CTRL_RTC:
SENS.sar_meas_start2.meas2_start_force = true; //RTC controller controls the ADC,not ulp coprocessor
SENS.sar_meas_start2.meas2_start_force = true; //RTC controller controls the ADC,not ulp coprocessor
SENS.sar_meas_start2.sar2_en_pad_force = true; //RTC controller controls the data port, not ulp coprocessor
SENS.sar_read_ctrl2.sar2_dig_force = false; //RTC controller controls the ADC, not digital controller
SENS.sar_read_ctrl2.sar2_pwdet_force = false; //RTC controller controls the ADC, not PWDET
@@ -1301,7 +1320,7 @@ static void adc_set_controller(adc_unit_t unit, adc_controller_t ctrl )
break;
default:
ESP_LOGE(TAG, "adc2 selects invalid controller");
break;
break;
}
} else {
ESP_LOGE(TAG, "invalid adc unit");
@@ -1321,12 +1340,12 @@ static int adc_convert( adc_unit_t unit, int channel)
while (SENS.sar_meas_start1.meas1_done_sar == 0);
adc_value = SENS.sar_meas_start1.meas1_data_sar;
} else if ( unit == ADC_UNIT_2 ) {
SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected.
SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected.
SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0
SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1
while (SENS.sar_meas_start2.meas2_done_sar == 0) {}; //read done
adc_value = SENS.sar_meas_start2.meas2_data_sar;
adc_value = SENS.sar_meas_start2.meas2_data_sar;
} else {
ESP_LOGE(TAG, "invalid adc unit");
return ESP_ERR_INVALID_ARG;
@@ -1479,7 +1498,7 @@ static inline void adc1_fsm_disable()
SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
SENS.sar_meas_wait1.sar_amp_wait1 = 1;
SENS.sar_meas_wait1.sar_amp_wait2 = 1;
SENS.sar_meas_wait2.sar_amp_wait3 = 1;
SENS.sar_meas_wait2.sar_amp_wait3 = 1;
}
esp_err_t adc1_i2s_mode_acquire()
@@ -1530,7 +1549,7 @@ int adc1_get_raw(adc1_channel_t channel)
adc1_adc_mode_acquire();
adc_power_on();
portENTER_CRITICAL(&rtc_spinlock);
portENTER_CRITICAL(&rtc_spinlock);
//disable other peripherals
adc1_hall_enable(false);
adc1_fsm_disable(); //currently the LNA is not open, close it by default
@@ -1652,7 +1671,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
}
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(3<<(channel*2)) ) | ((atten&3) << (channel*2));
_lock_release( &adc2_wifi_lock );
portEXIT_CRITICAL( &adc2_spinlock );
return ESP_OK;
}
@@ -1682,7 +1701,7 @@ static inline void adc2_dac_disable( adc2_channel_t channel)
}
//registers in critical section with adc1:
//SENS_SAR_START_FORCE_REG,
//SENS_SAR_START_FORCE_REG,
esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int* raw_out)
{
uint16_t adc_value = 0;
@@ -1692,7 +1711,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int*
adc_power_on();
//avoid collision with other tasks
portENTER_CRITICAL(&adc2_spinlock);
portENTER_CRITICAL(&adc2_spinlock);
//lazy initialization
//try the lock, return if failed (wifi using).
if ( _lock_try_acquire( &adc2_wifi_lock ) == -1 ) {
@@ -1895,7 +1914,9 @@ esp_err_t dac_i2s_disable()
static inline void adc1_hall_enable(bool enable)
{
RTCIO.hall_sens.xpd_hall = enable;
#if CONFIG_IDF_TARGET_ESP32
RTCIO.hall_sens.xpd_hall = enable;
#endif
}
static int hall_sensor_get_value() //hall sensor without LNA
@@ -1904,14 +1925,15 @@ static int hall_sensor_get_value() //hall sensor without LNA
int Sens_Vn0;
int Sens_Vp1;
int Sens_Vn1;
int hall_value;
int hall_value = 0;
adc_power_on();
#if CONFIG_IDF_TARGET_ESP32
portENTER_CRITICAL(&rtc_spinlock);
//disable other peripherals
adc1_fsm_disable();//currently the LNA is not open, close it by default
adc1_hall_enable(true);
adc1_fsm_disable();//currently the LNA is not open, close it by default
adc1_hall_enable(true);
// set controller
adc_set_controller( ADC_UNIT_1, ADC_CTRL_RTC );
// convert for 4 times with different phase and outputs
@@ -1923,7 +1945,7 @@ static int hall_sensor_get_value() //hall sensor without LNA
Sens_Vn1 = adc_convert( ADC_UNIT_1, ADC1_CHANNEL_3 );
portEXIT_CRITICAL(&rtc_spinlock);
hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
#endif
return hall_value;
}

3
components/driver/sdmmc_host.c
View File

@@ -25,7 +25,7 @@
#include "sdmmc_private.h"
#include "freertos/semphr.h"
#include "soc/sdmmc_periph.h"
#if CONFIG_IDF_TARGET_ESP32
#define SDMMC_EVENT_QUEUE_LENGTH 32
@@ -635,3 +635,4 @@ esp_err_t sdmmc_host_pullup_en(int slot, int width)
}
return ESP_OK;
}
#endif

90
components/driver/spi_common.c
View File

@@ -14,6 +14,8 @@
#include <string.h>
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "driver/spi_master.h"
#include "soc/spi_periph.h"
#include "esp32/rom/ets_sys.h"
@@ -30,6 +32,9 @@
#include "driver/spi_common.h"
#include "stdatomic.h"
#include "hal/spi_hal.h"
#if CONFIG_IDF_TARGET_ESP32S2BETA
#include "cas.h"
#endif
static const char *SPI_TAG = "spi";
@@ -112,7 +117,17 @@ bool spicommon_dma_chan_claim (int dma_chan)
spi_dma_chan_enabled |= DMA_CHANNEL_ENABLED(dma_chan);
ret = true;
}
#if CONFIG_IDF_TARGET_ESP32
periph_module_enable( PERIPH_SPI_DMA_MODULE );
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if (dma_chan==1) {
periph_module_enable(PERIPH_SPI2_DMA_MODULE);
} else if (dma_chan==2) {
periph_module_enable(PERIPH_SPI3_DMA_MODULE);
} else if (dma_chan==3) {
periph_module_enable(PERIPH_SPI_SHARED_DMA_MODULE);
}
#endif
portEXIT_CRITICAL(&spi_dma_spinlock);
return ret;
@@ -131,10 +146,20 @@ bool spicommon_dma_chan_free(int dma_chan)
portENTER_CRITICAL(&spi_dma_spinlock);
spi_dma_chan_enabled &= ~DMA_CHANNEL_ENABLED(dma_chan);
#if CONFIG_IDF_TARGET_ESP32
if ( spi_dma_chan_enabled == 0 ) {
//disable the DMA only when all the channels are freed.
periph_module_disable( PERIPH_SPI_DMA_MODULE );
}
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if (dma_chan==1) {
periph_module_disable(PERIPH_SPI2_DMA_MODULE);
} else if (dma_chan==2) {
periph_module_disable(PERIPH_SPI3_DMA_MODULE);
} else if (dma_chan==3) {
periph_module_disable(PERIPH_SPI_SHARED_DMA_MODULE);
}
#endif
portEXIT_CRITICAL(&spi_dma_spinlock);
return true;
@@ -234,23 +259,43 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
ESP_LOGD(SPI_TAG, "SPI%d use iomux pins.", host+1);
if (bus_config->mosi_io_num >= 0) {
gpio_iomux_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in);
#if CONFIG_IDF_TARGET_ESP32
gpio_iomux_out(bus_config->mosi_io_num, FUNC_SPI, false);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
gpio_iomux_out(bus_config->mosi_io_num, spi_periph_signal[host].func, false);
#endif
}
if (bus_config->miso_io_num >= 0) {
gpio_iomux_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in);
#if CONFIG_IDF_TARGET_ESP32
gpio_iomux_out(bus_config->miso_io_num, FUNC_SPI, false);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
gpio_iomux_out(bus_config->miso_io_num, spi_periph_signal[host].func, false);
#endif
}
if (bus_config->quadwp_io_num >= 0) {
gpio_iomux_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in);
#if CONFIG_IDF_TARGET_ESP32
gpio_iomux_out(bus_config->quadwp_io_num, FUNC_SPI, false);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
gpio_iomux_out(bus_config->quadwp_io_num, spi_periph_signal[host].func, false);
#endif
}
if (bus_config->quadhd_io_num >= 0) {
gpio_iomux_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in);
#if CONFIG_IDF_TARGET_ESP32
gpio_iomux_out(bus_config->quadhd_io_num, FUNC_SPI, false);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
gpio_iomux_out(bus_config->quadhd_io_num, spi_periph_signal[host].func, false);
#endif
}
if (bus_config->sclk_io_num >= 0) {
gpio_iomux_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in);
#if CONFIG_IDF_TARGET_ESP32
gpio_iomux_out(bus_config->sclk_io_num, FUNC_SPI, false);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
gpio_iomux_out(bus_config->sclk_io_num, spi_periph_signal[host].func, false);
#endif
}
temp_flag |= SPICOMMON_BUSFLAG_NATIVE_PINS;
} else {
@@ -264,6 +309,9 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT);
}
gpio_matrix_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in, false);
#if CONFIG_IDF_TARGET_ESP32S2BETA
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]);
#endif
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], FUNC_GPIO);
}
if (bus_config->miso_io_num >= 0) {
@@ -274,18 +322,27 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT);
}
gpio_matrix_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in, false);
#if CONFIG_IDF_TARGET_ESP32S2BETA
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]);
#endif
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], FUNC_GPIO);
}
if (bus_config->quadwp_io_num >= 0) {
gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_out, false, false);
gpio_matrix_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in, false);
#if CONFIG_IDF_TARGET_ESP32S2BETA
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]);
#endif
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], FUNC_GPIO);
}
if (bus_config->quadhd_io_num >= 0) {
gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_out, false, false);
gpio_matrix_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in, false);
#if CONFIG_IDF_TARGET_ESP32S2BETA
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]);
#endif
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], FUNC_GPIO);
}
if (bus_config->sclk_io_num >= 0) {
@@ -296,12 +353,30 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT);
}
gpio_matrix_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in, false);
#if CONFIG_IDF_TARGET_ESP32S2BETA
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]);
#endif
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], FUNC_GPIO);
}
#if CONFIG_IDF_TARGET_ESP32S2BETA
if (bus_config->spicd_io_num >= 0) {
gpio_set_direction(bus_config->spicd_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->spicd_io_num, spi_periph_signal[host].spicd_out, false, false);
gpio_matrix_in(bus_config->spicd_io_num, spi_periph_signal[host].spicd_in, false);
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->spicd_io_num]);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->spicd_io_num], FUNC_GPIO);
}
#endif
}
//Select DMA channel.
#if CONFIG_IDF_TARGET_ESP32
DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if (dma_chan==VSPI_HOST) {
DPORT_SET_PERI_REG_MASK(DPORT_SPI_DMA_CHAN_SEL_REG, DPORT_SPI_SHARED_DMA_SEL_M);
}
#endif
if (flags_o) *flags_o = temp_flag;
return ESP_OK;
@@ -354,7 +429,11 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
if (!force_gpio_matrix && cs_io_num == spi_periph_signal[host].spics0_iomux_pin && cs_num == 0) {
//The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
gpio_iomux_in(cs_io_num, spi_periph_signal[host].spics_in);
#if CONFIG_IDF_TARGET_ESP32
gpio_iomux_out(cs_io_num, FUNC_SPI, false);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
gpio_iomux_out(cs_io_num, spi_periph_signal[host].func, false);
#endif
} else {
//Use GPIO matrix
if (GPIO_IS_VALID_OUTPUT_GPIO(cs_io_num)) {
@@ -364,6 +443,9 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
gpio_set_direction(cs_io_num, GPIO_MODE_INPUT);
}
if (cs_num == 0) gpio_matrix_in(cs_io_num, spi_periph_signal[host].spics_in, false);
#if CONFIG_IDF_TARGET_ESP32S2BETA
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]);
#endif
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO);
}
}
@@ -402,6 +484,7 @@ static int dmaworkaround_waiting_for_chan = 0;
bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg)
{
#if CONFIG_IDF_TARGET_ESP32
int otherchan = (dmachan == 1) ? 2 : 1;
bool ret;
portENTER_CRITICAL_ISR(&dmaworkaround_mux);
@@ -418,6 +501,9 @@ bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t
}
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
return ret;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
return true;
#endif
}
bool IRAM_ATTR spicommon_dmaworkaround_reset_in_progress()
@@ -427,6 +513,7 @@ bool IRAM_ATTR spicommon_dmaworkaround_reset_in_progress()
void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
{
#if CONFIG_IDF_TARGET_ESP32
portENTER_CRITICAL_ISR(&dmaworkaround_mux);
dmaworkaround_channels_busy[dmachan-1] = 0;
if (dmaworkaround_waiting_for_chan == dmachan) {
@@ -438,6 +525,7 @@ void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
}
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
#endif
}
void IRAM_ATTR spicommon_dmaworkaround_transfer_active(int dmachan)
@@ -447,4 +535,4 @@ void IRAM_ATTR spicommon_dmaworkaround_transfer_active(int dmachan)
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
}
#endif

26
components/driver/spi_master.c
View File

@@ -122,7 +122,6 @@ We have two bits to control the interrupt:
#include "driver/spi_common.h"
#include "driver/spi_master.h"
#include "soc/spi_periph.h"
#include "esp32/rom/ets_sys.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
@@ -139,8 +138,12 @@ We have two bits to control the interrupt:
#include "esp_heap_caps.h"
#include "stdatomic.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "hal/spi_hal.h"
#if CONFIG_IDF_TARGET_ESP32S2BETA
#include "cas.h"
#endif
typedef struct spi_device_t spi_device_t;
@@ -183,6 +186,9 @@ typedef struct {
int dma_chan;
int max_transfer_sz;
spi_bus_config_t bus_cfg;
#if CONFIG_IDF_TARGET_ESP32S2BETA
int id;
#endif
#ifdef CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock;
#endif
@@ -199,7 +205,7 @@ struct spi_device_t {
bool waiting; //the device is waiting for the exclusive control of the bus
};
static spi_host_t *spihost[3];
static spi_host_t *spihost[SPI_PERIPH_NUM];
static const char *SPI_TAG = "spi_master";
@@ -245,6 +251,10 @@ esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus
}
memset(spihost[host], 0, sizeof(spi_host_t));
memcpy( &spihost[host]->bus_cfg, bus_config, sizeof(spi_bus_config_t));
#if CONFIG_IDF_TARGET_ESP32S2BETA
spihost[host]->id = host;
#endif
#ifdef CONFIG_PM_ENABLE
err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_master",
&spihost[host]->pm_lock);
@@ -259,7 +269,13 @@ esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus
ret = err;
goto cleanup;
}
#if CONFIG_IDF_TARGET_ESP32
DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
#elif CONFIG_IDF_TARGET_ESP32S2BETA
if (host==VSPI_HOST) {
DPORT_SET_PERI_REG_BITS(DPORT_SPI_SHARED_DMA_SEL_REG, DPORT_SPI_SHARED_DMA_SEL_M, 1, DPORT_SPI_SHARED_DMA_SEL_S);
}
#endif
int dma_desc_ct=0;
spihost[host]->dma_chan=dma_chan;
if (dma_chan == 0) {
@@ -1084,4 +1100,4 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_transmit(spi_device_handle_t ha
return ESP_OK;
}
#endif

7
components/driver/spi_slave.c
View File

@@ -13,13 +13,14 @@
// limitations under the License.
#include <string.h>
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include <hal/spi_ll.h>
#include <hal/spi_slave_hal.h>
#include <soc/lldesc.h>
#include "driver/spi_common.h"
#include "driver/spi_slave.h"
#include "soc/spi_periph.h"
#include "esp32/rom/ets_sys.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
@@ -34,7 +35,7 @@
#include "esp32/rom/lldesc.h"
#include "driver/gpio.h"
#include "esp_heap_caps.h"
#include "esp32/rom/ets_sys.h"
static const char *SPI_TAG = "spi_slave";
#define SPI_CHECK(a, str, ret_val) \
if (!(a)) { \
@@ -392,4 +393,4 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
if (do_yield) portYIELD_FROM_ISR();
}
#endif

11
components/driver/timer.c
View File

@@ -19,6 +19,7 @@
#include "freertos/xtensa_api.h"
#include "driver/timer.h"
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
static const char* TIMER_TAG = "timer_group";
#define TIMER_CHECK(a, str, ret_val) \
@@ -47,7 +48,11 @@ esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL_SAFE(&timer_spinlock[group_num]);
#if CONFIG_IDF_TARGET_ESP32
TG[group_num]->hw_timer[timer_num].update = 1;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
TG[group_num]->hw_timer[timer_num].update.update = 1;
#endif
*timer_val = ((uint64_t) TG[group_num]->hw_timer[timer_num].cnt_high << 32)
| (TG[group_num]->hw_timer[timer_num].cnt_low);
portEXIT_CRITICAL_SAFE(&timer_spinlock[group_num]);
@@ -171,7 +176,7 @@ esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_
return ESP_OK;
}
esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
void (*fn)(void*), void * arg, int intr_alloc_flags, timer_isr_handle_t *handle)
{
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
@@ -222,7 +227,11 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
//but software reset does not clear interrupt status. This is not safe for application when enable the interrupt of timer_group.
//we need to disable the interrupt and clear the interrupt status here.
TG[group_num]->int_ena.val &= (~BIT(timer_num));
#if CONFIG_IDF_TARGET_ESP32
TG[group_num]->int_clr_timers.val = BIT(timer_num);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
TG[group_num]->int_clr.val = BIT(timer_num);
#endif
TG[group_num]->hw_timer[timer_num].config.autoreload = config->auto_reload;
TG[group_num]->hw_timer[timer_num].config.divider = (uint16_t) config->divider;
TG[group_num]->hw_timer[timer_num].config.enable = config->counter_en;

49
components/driver/uart.c
View File

@@ -17,7 +17,6 @@
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp32/clk.h"
#include "malloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
@@ -28,6 +27,12 @@
#include "driver/uart.h"
#include "driver/gpio.h"
#include "driver/uart_select.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/clk.h"
#endif
#define XOFF (char)0x13
#define XON (char)0x11
@@ -79,7 +84,7 @@ typedef struct {
intr_handle_t intr_handle; /*!< UART interrupt handle*/
uart_mode_t uart_mode; /*!< UART controller actual mode set by uart_set_mode() */
bool coll_det_flg; /*!< UART collision detection flag */
//rx parameters
int rx_buffered_len; /*!< UART cached data length */
SemaphoreHandle_t rx_mux; /*!< UART RX data mutex*/
@@ -298,9 +303,15 @@ static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num)
//See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
// we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
#if CONFIG_IDF_TARGET_ESP32
while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) {
READ_PERI_REG(UART_FIFO_REG(uart_num));
}
#elif CONFIG_IDF_TARGET_ESP32S2BETA
while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.rx_waddr != UART[uart_num]->mem_rx_status.apb_rx_raddr)) {
READ_PERI_REG(UART_FIFO_AHB_REG(uart_num));
}
#endif
return ESP_OK;
}
@@ -577,12 +588,14 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
rts_sig = U1RTS_OUT_IDX;
cts_sig = U1CTS_IN_IDX;
break;
#if CONFIG_IDF_TARGET_ESP32
case UART_NUM_2:
tx_sig = U2TXD_OUT_IDX;
rx_sig = U2RXD_IN_IDX;
rts_sig = U2RTS_OUT_IDX;
cts_sig = U2CTS_IN_IDX;
break;
#endif
case UART_NUM_MAX:
default:
tx_sig = U0TXD_OUT_IDX;
@@ -657,7 +670,11 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
} else if(uart_num == UART_NUM_1) {
periph_module_enable(PERIPH_UART1_MODULE);
} else if(uart_num == UART_NUM_2) {
#if CONFIG_IDF_TARGET_ESP32
periph_module_enable(PERIPH_UART2_MODULE);
#else
return ESP_FAIL;
#endif
}
r = uart_set_hw_flow_ctrl(uart_num, uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
if (r != ESP_OK) return r;
@@ -861,7 +878,11 @@ static void uart_rx_intr_handler_default(void *param)
if (p_uart->rx_buffer_full_flg == false) {
//We have to read out all data in RX FIFO to clear the interrupt signal
while (buf_idx < rx_fifo_len) {
#if CONFIG_IDF_TARGET_ESP32
p_uart->rx_data_buf[buf_idx++] = uart_reg->fifo.rw_byte;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
p_uart->rx_data_buf[buf_idx++] = READ_PERI_REG(UART_FIFO_AHB_REG(uart_num));
#endif
}
uint8_t pat_chr = uart_reg->at_cmd_char.data;
int pat_num = uart_reg->at_cmd_char.char_num;
@@ -997,13 +1018,13 @@ static void uart_rx_intr_handler_default(void *param)
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_reset_rx_fifo(uart_num);
// Set collision detection flag
p_uart_obj[uart_num]->coll_det_flg = true;
p_uart_obj[uart_num]->coll_det_flg = true;
UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
uart_event.type = UART_EVENT_MAX;
} else if(uart_intr_status & UART_TX_DONE_INT_ST_M) {
uart_disable_intr_mask_from_isr(uart_num, UART_TX_DONE_INT_ENA_M);
uart_clear_intr_status(uart_num, UART_TX_DONE_INT_CLR_M);
// If RS485 half duplex mode is enable then reset FIFO and
// If RS485 half duplex mode is enable then reset FIFO and
// reset RTS pin to start receiver driver
if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
@@ -1461,7 +1482,11 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
} else if(uart_num == UART_NUM_1) {
periph_module_disable(PERIPH_UART1_MODULE);
} else if(uart_num == UART_NUM_2) {
periph_module_disable(PERIPH_UART2_MODULE);
#if CONFIG_IDF_TARGET_ESP32
periph_module_disable(PERIPH_UART2_MODULE);
#else
return ESP_FAIL;
#endif
}
}
return ESP_OK;
@@ -1479,11 +1504,11 @@ portMUX_TYPE *uart_get_selectlock()
return &uart_selectlock;
}
// Set UART mode
esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
{
UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
if ((mode == UART_MODE_RS485_COLLISION_DETECT) || (mode == UART_MODE_RS485_APP_CTRL)
if ((mode == UART_MODE_RS485_COLLISION_DETECT) || (mode == UART_MODE_RS485_APP_CTRL)
|| (mode == UART_MODE_RS485_HALF_DUPLEX)) {
UART_CHECK((UART[uart_num]->conf1.rx_flow_en != 1),
"disable hw flowctrl before using RS485 mode", ESP_ERR_INVALID_ARG);
@@ -1538,13 +1563,13 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
return ESP_OK;
}
esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh)
esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
UART_CHECK((tout_thresh < 127), "tout_thresh max value is 126", ESP_ERR_INVALID_ARG);
UART_ENTER_CRITICAL(&uart_spinlock[uart_num]);
// The tout_thresh = 1, defines TOUT interrupt timeout equal to
// transmission time of one symbol (~11 bit) on current baudrate
// The tout_thresh = 1, defines TOUT interrupt timeout equal to
// transmission time of one symbol (~11 bit) on current baudrate
if (tout_thresh > 0) {
UART[uart_num]->conf1.rx_tout_thrhd = (tout_thresh & UART_RX_TOUT_THRHD_V);
UART[uart_num]->conf1.rx_tout_en = 1;
@@ -1559,8 +1584,8 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag)
{
UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
UART_CHECK((collision_flag != NULL), "wrong parameter pointer", ESP_ERR_INVALID_ARG);
UART_CHECK((UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)
|| UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)),
UART_CHECK((UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)
|| UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)),
"wrong mode", ESP_ERR_INVALID_ARG);
*collision_flag = p_uart_obj[uart_num]->coll_det_flg;
return ESP_OK;