diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml index 058bb62f9e..fc40192d54 100644 --- a/.gitlab/ci/build.yml +++ b/.gitlab/ci/build.yml @@ -215,14 +215,6 @@ build_pytest_examples_esp32c2: IDF_TARGET: esp32c2 TEST_DIR: examples -build_pytest_examples_esp32h4: - extends: - - .build_pytest_no_jtag_template - - .rules:build:example_test-esp32h4 - variables: - IDF_TARGET: esp32h4 - TEST_DIR: examples - build_pytest_examples_jtag: # for all targets extends: - .build_pytest_jtag_template @@ -649,14 +641,6 @@ build_examples_cmake_esp32c3: IDF_TARGET: esp32c3 TEST_DIR: examples -build_examples_cmake_esp32h4: - extends: - - .build_cmake_template - - .rules:build:example_test-esp32h4 - variables: - IDF_TARGET: esp32h4 - TEST_DIR: examples - build_examples_cmake_esp32c6: extends: - .build_cmake_template @@ -729,13 +713,6 @@ build_clang_test_apps_esp32c6: variables: IDF_TARGET: esp32c6 -build_clang_test_apps_esp32h4: - extends: - - .build_clang_test_apps_riscv - - .rules:build:custom_test-esp32h4 - variables: - IDF_TARGET: esp32h4 - .test_build_system_template: stage: host_test extends: diff --git a/.gitlab/ci/dependencies/dependencies.yml b/.gitlab/ci/dependencies/dependencies.yml index 0ba5e12ec7..70b3ee9c01 100644 --- a/.gitlab/ci/dependencies/dependencies.yml +++ b/.gitlab/ci/dependencies/dependencies.yml @@ -3,7 +3,6 @@ - esp32s2 - esp32s3 - esp32c3 - - esp32h4 - esp32c2 - esp32c6 - esp32h2 diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml index 27f5d07e47..1aa8eea585 100644 --- a/.gitlab/ci/host-test.yml +++ b/.gitlab/ci/host-test.yml @@ -185,11 +185,6 @@ test_efuse_table_on_host_esp32c6: variables: IDF_TARGET: esp32c6 -test_efuse_table_on_host_esp32h4: - extends: .test_efuse_table_on_host_template - variables: - IDF_TARGET: esp32h4 - test_espcoredump: extends: .host_test_template artifacts: diff --git a/.gitlab/ci/rules.yml b/.gitlab/ci/rules.yml index 09f2e8b446..43b21d3569 100644 --- a/.gitlab/ci/rules.yml +++ b/.gitlab/ci/rules.yml @@ -447,9 +447,6 @@ .if-label-component_ut_esp32h2: &if-label-component_ut_esp32h2 if: '$BOT_LABEL_COMPONENT_UT_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h2(?:,[^,\n\r]+)*$/i' -.if-label-component_ut_esp32h4: &if-label-component_ut_esp32h4 - if: '$BOT_LABEL_COMPONENT_UT_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32h4(?:,[^,\n\r]+)*$/i' - .if-label-component_ut_esp32s2: &if-label-component_ut_esp32s2 if: '$BOT_LABEL_COMPONENT_UT_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*component_ut_esp32s2(?:,[^,\n\r]+)*$/i' @@ -474,9 +471,6 @@ .if-label-custom_test_esp32h2: &if-label-custom_test_esp32h2 if: '$BOT_LABEL_CUSTOM_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h2(?:,[^,\n\r]+)*$/i' -.if-label-custom_test_esp32h4: &if-label-custom_test_esp32h4 - if: '$BOT_LABEL_CUSTOM_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32h4(?:,[^,\n\r]+)*$/i' - .if-label-custom_test_esp32s2: &if-label-custom_test_esp32s2 if: '$BOT_LABEL_CUSTOM_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*custom_test_esp32s2(?:,[^,\n\r]+)*$/i' @@ -504,9 +498,6 @@ .if-label-example_test_esp32h2: &if-label-example_test_esp32h2 if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h2(?:,[^,\n\r]+)*$/i' -.if-label-example_test_esp32h4: &if-label-example_test_esp32h4 - if: '$BOT_LABEL_EXAMPLE_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32h4(?:,[^,\n\r]+)*$/i' - .if-label-example_test_esp32s2: &if-label-example_test_esp32s2 if: '$BOT_LABEL_EXAMPLE_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*example_test_esp32s2(?:,[^,\n\r]+)*$/i' @@ -567,9 +558,6 @@ .if-label-unit_test_esp32h2: &if-label-unit_test_esp32h2 if: '$BOT_LABEL_UNIT_TEST_ESP32H2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h2(?:,[^,\n\r]+)*$/i' -.if-label-unit_test_esp32h4: &if-label-unit_test_esp32h4 - if: '$BOT_LABEL_UNIT_TEST_ESP32H4 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32h4(?:,[^,\n\r]+)*$/i' - .if-label-unit_test_esp32s2: &if-label-unit_test_esp32s2 if: '$BOT_LABEL_UNIT_TEST_ESP32S2 || $CI_MERGE_REQUEST_LABELS =~ /^(?:[^,\n\r]+,)*unit_test_esp32s2(?:,[^,\n\r]+)*$/i' @@ -607,7 +595,6 @@ - <<: *if-label-component_ut_esp32c3 - <<: *if-label-component_ut_esp32c6 - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-component_ut_esp32h4 - <<: *if-label-component_ut_esp32s2 - <<: *if-label-component_ut_esp32s3 - <<: *if-label-lan8720 @@ -618,7 +605,6 @@ - <<: *if-label-unit_test_esp32c3 - <<: *if-label-unit_test_esp32c6 - <<: *if-label-unit_test_esp32h2 - - <<: *if-label-unit_test_esp32h4 - <<: *if-label-unit_test_esp32s2 - <<: *if-label-unit_test_esp32s3 - <<: *if-dev-push @@ -879,7 +865,6 @@ - <<: *if-label-custom_test_esp32c3 - <<: *if-label-custom_test_esp32c6 - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-custom_test_esp32h4 - <<: *if-label-custom_test_esp32s2 - <<: *if-label-custom_test_esp32s3 - <<: *if-label-target_test @@ -1020,30 +1005,6 @@ - <<: *if-dev-push changes: *patterns-target_test-wifi -.rules:build:custom_test-esp32h4: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build - - <<: *if-label-custom_test - - <<: *if-label-custom_test_esp32h4 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-build_components - - <<: *if-dev-push - changes: *patterns-build_system - - <<: *if-dev-push - changes: *patterns-custom_test - - <<: *if-dev-push - changes: *patterns-downloadable-tools - - <<: *if-dev-push - changes: *patterns-target_test-adc - - <<: *if-dev-push - changes: *patterns-target_test-i154 - - <<: *if-dev-push - changes: *patterns-target_test-wifi - .rules:build:custom_test-esp32s2: rules: - <<: *if-revert-branch @@ -1121,7 +1082,6 @@ - <<: *if-label-example_test_esp32c3 - <<: *if-label-example_test_esp32c6 - <<: *if-label-example_test_esp32h2 - - <<: *if-label-example_test_esp32h4 - <<: *if-label-example_test_esp32s2 - <<: *if-label-example_test_esp32s3 - <<: *if-label-iperf_stress_test @@ -1348,44 +1308,6 @@ - <<: *if-dev-push changes: *patterns-target_test-wifi -.rules:build:example_test-esp32h4: - rules: - - <<: *if-revert-branch - when: never - - <<: *if-protected - - <<: *if-label-build - - <<: *if-label-example_test - - <<: *if-label-example_test_esp32h4 - - <<: *if-label-target_test - - <<: *if-dev-push - changes: *patterns-build-example_test - - <<: *if-dev-push - changes: *patterns-build_components - - <<: *if-dev-push - changes: *patterns-build_system - - <<: *if-dev-push - changes: *patterns-downloadable-tools - - <<: *if-dev-push - changes: *patterns-example_test - - <<: *if-dev-push - changes: *patterns-example_test-bt - - <<: *if-dev-push - changes: *patterns-example_test-ethernet - - <<: *if-dev-push - changes: *patterns-example_test-i154 - - <<: *if-dev-push - changes: *patterns-example_test-sdio - - <<: *if-dev-push - changes: *patterns-example_test-usb - - <<: *if-dev-push - changes: *patterns-example_test-wifi - - <<: *if-dev-push - changes: *patterns-target_test-adc - - <<: *if-dev-push - changes: *patterns-target_test-i154 - - <<: *if-dev-push - changes: *patterns-target_test-wifi - .rules:build:example_test-esp32s2: rules: - <<: *if-revert-branch @@ -1509,7 +1431,6 @@ - <<: *if-label-component_ut_esp32c3 - <<: *if-label-component_ut_esp32c6 - <<: *if-label-component_ut_esp32h2 - - <<: *if-label-component_ut_esp32h4 - <<: *if-label-component_ut_esp32s2 - <<: *if-label-component_ut_esp32s3 - <<: *if-label-custom_test @@ -1518,7 +1439,6 @@ - <<: *if-label-custom_test_esp32c3 - <<: *if-label-custom_test_esp32c6 - <<: *if-label-custom_test_esp32h2 - - <<: *if-label-custom_test_esp32h4 - <<: *if-label-custom_test_esp32s2 - <<: *if-label-custom_test_esp32s3 - <<: *if-label-example_test @@ -1527,7 +1447,6 @@ - <<: *if-label-example_test_esp32c3 - <<: *if-label-example_test_esp32c6 - <<: *if-label-example_test_esp32h2 - - <<: *if-label-example_test_esp32h4 - <<: *if-label-example_test_esp32s2 - <<: *if-label-example_test_esp32s3 - <<: *if-label-integration_test @@ -1542,7 +1461,6 @@ - <<: *if-label-unit_test_esp32c3 - <<: *if-label-unit_test_esp32c6 - <<: *if-label-unit_test_esp32h2 - - <<: *if-label-unit_test_esp32h4 - <<: *if-label-unit_test_esp32s2 - <<: *if-label-unit_test_esp32s3 - <<: *if-label-weekend_test @@ -1609,7 +1527,6 @@ - <<: *if-label-unit_test_esp32c3 - <<: *if-label-unit_test_esp32c6 - <<: *if-label-unit_test_esp32h2 - - <<: *if-label-unit_test_esp32h4 - <<: *if-label-unit_test_esp32s2 - <<: *if-label-unit_test_esp32s3 - <<: *if-dev-push diff --git a/Kconfig b/Kconfig index 7fdc422815..8cf51af062 100644 --- a/Kconfig +++ b/Kconfig @@ -66,28 +66,6 @@ mainmenu "Espressif IoT Development Framework Configuration" select FREERTOS_UNICORE select IDF_TARGET_ARCH_RISCV - config IDF_TARGET_ESP32H4 - bool - default "y" if IDF_TARGET="esp32h4" - select FREERTOS_UNICORE - select IDF_TARGET_ARCH_RISCV - - choice IDF_TARGET_ESP32H4_BETA_VERSION - prompt "ESP32-H4 beta version" - depends on IDF_TARGET_ESP32H4 - default IDF_TARGET_ESP32H4_BETA_VERSION_2 - help - Currently ESP32-H4 has several beta versions for internal use only. - Select the one that matches your chip model. - - config IDF_TARGET_ESP32H4_BETA_VERSION_1 - bool - prompt "ESP32-H4 beta1" - config IDF_TARGET_ESP32H4_BETA_VERSION_2 - bool - prompt "ESP32-H4 beta2" - endchoice - config IDF_TARGET_ESP32C2 bool default "y" if IDF_TARGET="esp32c2" @@ -116,10 +94,8 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x0002 if IDF_TARGET_ESP32S2 default 0x0005 if IDF_TARGET_ESP32C3 default 0x0009 if IDF_TARGET_ESP32S3 - default 0x000A if IDF_TARGET_ESP32H4_BETA_VERSION_1 default 0x000C if IDF_TARGET_ESP32C2 default 0x000D if IDF_TARGET_ESP32C6 - default 0x000E if IDF_TARGET_ESP32H4_BETA_VERSION_2 # ESP32-TODO: IDF-3475 default 0x0010 if IDF_TARGET_ESP32H2 default 0xFFFF diff --git a/components/app_update/esp_ota_ops.c b/components/app_update/esp_ota_ops.c index 80a07af5fa..6b80abab30 100644 --- a/components/app_update/esp_ota_ops.c +++ b/components/app_update/esp_ota_ops.c @@ -37,8 +37,6 @@ #include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/app_update/include/esp_ota_ops.h b/components/app_update/include/esp_ota_ops.h index 7809f2dc52..1364b543a8 100644 --- a/components/app_update/include/esp_ota_ops.h +++ b/components/app_update/include/esp_ota_ops.h @@ -334,7 +334,7 @@ typedef enum { /** * @brief Revokes the old signature digest. To be called in the application after the rollback logic. * - * Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-H4 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1). + * Relevant for Secure boot v2 on ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6, ESP32-H2 where upto 3 key digests can be stored (Key \#N-1, Key \#N, Key \#N+1). * When key \#N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key \#N-1 & Key \#N. * After successfully booting the OTA app should call this function to revoke Key \#N-1. * diff --git a/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld deleted file mode 100644 index 75c7d6a8fa..0000000000 --- a/components/bootloader/subproject/main/ld/esp32h4/bootloader.ld +++ /dev/null @@ -1,240 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/** Simplified memory map for the bootloader. - * Make sure the bootloader can load into main memory without overwriting itself. - * - * ESP32-H4 ROM static data usage is as follows: - * - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only - * - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup - * - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) - * - * The 2nd stage bootloader can take space up to the end of ROM shared - * buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700). - */ - -/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ -iram_dram_offset = 0x700000; - -/* We consider 0x3fce9700 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, - * and work out iram_seg and iram_loader_seg addresses from there, backwards. - */ - -/* These lengths can be adjusted, if necessary: */ -bootloader_usable_dram_end = 0x3fcdd120; -bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */ -bootloader_dram_seg_len = 0x5000; -bootloader_iram_loader_seg_len = 0x7000; -bootloader_iram_seg_len = 0x2000; - -/* Start of the lower region is determined by region size and the end of the higher region */ -bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; -bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; -bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; -bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; - -MEMORY -{ - iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len - iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len - dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len -} - -/* Default entry point: */ -ENTRY(call_start_cpu0); - -SECTIONS -{ - - .iram_loader.text : - { - . = ALIGN (16); - _loader_text_start = ABSOLUTE(.); - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ - *liblog.a:(.literal .text .literal.* .text.*) - *libgcc.a:(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) - *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) - *libspi_flash.a:*.*(.literal .text .literal.* .text.*) - *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) - *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*) - *libhal.a:cache_hal.*(.literal .text .literal.* .text.*) - *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) - *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) - *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) - *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) - *libefuse.a:*.*(.literal .text .literal.* .text.*) - *(.fini.literal) - *(.fini) - *(.gnu.version) - _loader_text_end = ABSOLUTE(.); - } > iram_loader_seg - - .iram.text : - { - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - } > iram_seg - - - /* Shared RAM */ - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _dram_start = ABSOLUTE(.); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } > dram_seg - - .dram0.data : - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - _data_end = ABSOLUTE(.); - } > dram_seg - - .dram0.rodata : - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - *(.sdata2 .sdata2.* .srodata .srodata.*) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - *(.eh_frame) - . = (. + 3) & ~ 3; - /* C++ constructor and destructor tables, properly ordered: */ - __init_array_start = ABSOLUTE(.); - KEEP (*crtbegin.*(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __init_array_end = ABSOLUTE(.); - KEEP (*crtbegin.*(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _rodata_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - _dram_end = ABSOLUTE(.); - } > dram_seg - - .iram.text : - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.iram .iram.*) /* catch stray IRAM_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /** CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - } > iram_seg - -} - -/** - * Appendix: Memory Usage of ROM bootloader - * - * 0x3fccb81c ------------------> _dram0_0_start - * | | - * | | - * | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h - * | | - * | | - * 0x3fcdd120 ------------------> __stack_sentry - * | | - * | | 2. Startup pro cpu stack (freed when IDF app is running) - * | | - * 0x3fcdf120 ------------------> __stack (pro cpu) - * | | - * | | - * | | 3. Shared memory only used in startup code or nonos/early boot* - * | | (can be freed when IDF runs) - * | | - * | | - * 0x3fcdfa6c ------------------> _dram0_rtos_reserved_start - * | | - * | | - * | | 4. Shared memory used in startup code and when IDF runs - * | | - * | | - * 0x3fcdfe40 ------------------> _dram0_rtos_reserved_end - * | | - * 0x3fcdfe4c ------------------> _data_start_interface - * | | - * | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible) - * | | - * 0x3fce0000 ------------------> _data_end_interface - */ diff --git a/components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld deleted file mode 100644 index 34156bcc91..0000000000 --- a/components/bootloader/subproject/main/ld/esp32h4/bootloader.rom.ld +++ /dev/null @@ -1,6 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* No definition for ESP32-H4 target */ diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c deleted file mode 100644 index 8281f42682..0000000000 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include "string.h" -#include "sdkconfig.h" -#include "esp_err.h" -#include "esp_log.h" -#include "esp_rom_gpio.h" -#include "esp_rom_efuse.h" -#include "esp32h4/rom/gpio.h" -#include "esp32h4/rom/spi_flash.h" -#include "esp32h4/rom/efuse.h" -#include "soc/gpio_periph.h" -#include "soc/efuse_reg.h" -#include "soc/spi_reg.h" -#include "soc/spi_mem_reg.h" -#include "soc/soc_caps.h" -#include "flash_qio_mode.h" -#include "bootloader_flash_config.h" -#include "bootloader_common.h" -#include "bootloader_flash_priv.h" -#include "bootloader_init.h" -#include "hal/mmu_hal.h" -#include "hal/cache_hal.h" -#include "hal/mmu_ll.h" - -#define FLASH_IO_MATRIX_DUMMY_40M 0 -#define FLASH_IO_MATRIX_DUMMY_80M 0 - -void bootloader_flash_update_id() -{ - esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip; - chip->device_id = bootloader_read_flash_id(); -} - -void IRAM_ATTR bootloader_flash_cs_timing_config() -{ - SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); - SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); -} - -void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) -{ - uint32_t spi_clk_div = 0; - switch (pfhdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_1: - spi_clk_div = 1; - break; - case ESP_IMAGE_SPI_SPEED_DIV_2: - spi_clk_div = 2; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - spi_clk_div = 3; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - spi_clk_div = 4; - break; - default: - break; - } - esp_rom_spiflash_config_clk(spi_clk_div, 0); -} - -void IRAM_ATTR bootloader_flash_set_dummy_out(void) -{ - REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); - REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); -} - -void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) -{ - bootloader_configure_spi_pins(1); - bootloader_flash_set_dummy_out(); -} - -static const char *TAG = "boot.esp32h4"; - -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - if (spiconfig == 0) { - - } else { - clk_gpio_num = spiconfig & 0x3f; - q_gpio_num = (spiconfig >> 6) & 0x3f; - d_gpio_num = (spiconfig >> 12) & 0x3f; - cs0_gpio_num = (spiconfig >> 18) & 0x3f; - hd_gpio_num = (spiconfig >> 24) & 0x3f; - wp_gpio_num = wp_pin; - } - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - } - if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); - } -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "24MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "16MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "12MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "48MHz"; - break; - default: - str = "12MHz"; - break; - } - ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static void bootloader_spi_flash_resume(void) -{ - bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); - esp_rom_spiflash_wait_idle(&g_rom_flashchip); -} - -esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); -#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { - ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); - return ESP_FAIL; - } -#endif - - bootloader_spi_flash_resume(); - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 611269f73b..14c3917181 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -18,11 +18,6 @@ typedef enum { ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */ ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */ ESP_CHIP_ID_ESP32C2 = 0x000C, /*!< chip ID: ESP32-C2 */ -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - ESP_CHIP_ID_ESP32H4 = 0x000E, /*!< chip ID: ESP32-H4 Beta2*/ // ESP32H4-TODO: IDF-3475 -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 - ESP_CHIP_ID_ESP32H4 = 0x000A, /*!< chip ID: ESP32-H4 Beta1 */ -#endif ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/bootloader_support/private_include/bootloader_signature.h b/components/bootloader_support/private_include/bootloader_signature.h index 9af5c7a51e..ac4c713f86 100644 --- a/components/bootloader_support/private_include/bootloader_signature.h +++ b/components/bootloader_support/private_include/bootloader_signature.h @@ -17,8 +17,6 @@ #include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c index 7c811768cb..605a20deb9 100644 --- a/components/bootloader_support/src/bootloader_efuse.c +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -27,9 +27,6 @@ int bootloader_clock_get_rated_freq_mhz(void) #elif CONFIG_IDF_TARGET_ESP32C3 return 160; -#elif CONFIG_IDF_TARGET_ESP32H4 - return 96; - #elif CONFIG_IDF_TARGET_ESP32C6 return 160; diff --git a/components/bootloader_support/src/bootloader_random_esp32h4.c b/components/bootloader_support/src/bootloader_random_esp32h4.c deleted file mode 100644 index 2d3d086871..0000000000 --- a/components/bootloader_support/src/bootloader_random_esp32h4.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "sdkconfig.h" -#include "bootloader_random.h" -#include "esp_log.h" -#include "soc/syscon_reg.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/apb_saradc_reg.h" -#include "soc/system_reg.h" -#include "esp_private/regi2c_ctrl.h" - -// ESP32H4-TODO: IDF-3381 -void bootloader_random_enable(void) -{ - -} - -void bootloader_random_disable(void) -{ - -} diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 29c7f32c9c..715ef610a3 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -28,12 +28,6 @@ #include "esp32c3/rom/uart.h" #include "esp32c3/rom/gpio.h" #include "esp32c3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/efuse.h" -#include "esp32h4/rom/crc.h" -#include "esp32h4/rom/uart.h" -#include "esp32h4/rom/gpio.h" -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/efuse.h" #include "esp32c2/rom/crc.h" diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c deleted file mode 100644 index 50653dbd8c..0000000000 --- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include "sdkconfig.h" -#include "esp_attr.h" -#include "esp_log.h" -#include "esp_image_format.h" -#include "flash_qio_mode.h" -#include "esp_rom_gpio.h" -#include "esp_rom_efuse.h" -#include "esp_rom_uart.h" -#include "esp_rom_sys.h" -#include "esp_rom_spiflash.h" -#include "soc/efuse_reg.h" -#include "soc/gpio_sig_map.h" -#include "soc/io_mux_reg.h" -#include "soc/assist_debug_reg.h" -#include "esp_cpu.h" -#include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/spi_periph.h" -#include "soc/extmem_reg.h" -#include "soc/io_mux_reg.h" -#include "soc/system_reg.h" -#include "esp32h4/rom/efuse.h" -#include "esp32h4/rom/ets_sys.h" -#include "bootloader_common.h" -#include "bootloader_init.h" -#include "bootloader_clock.h" -#include "bootloader_flash_config.h" -#include "bootloader_mem.h" -#include "bootloader_console.h" -#include "bootloader_flash_priv.h" -#include "bootloader_soc.h" -#include "esp_private/bootloader_flash_internal.h" -#include "hal/mmu_hal.h" -#include "hal/cache_hal.h" - -static const char *TAG = "boot.esp32h4"; - -static void wdt_reset_cpu0_info_enable(void) -{ - REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG); - REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); - REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN); -} - -static void wdt_reset_info_dump(int cpu) -{ - (void) cpu; - // saved PC was already printed by the ROM bootloader. - // nothing to do here. -} - -static void bootloader_check_wdt_reset(void) -{ - int wdt_rst = 0; - soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 || - rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) { - ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); - wdt_rst = 1; - } - if (wdt_rst) { - // if reset by WDT dump info from trace port - wdt_reset_info_dump(0); - } - wdt_reset_cpu0_info_enable(); -} - -static void bootloader_super_wdt_auto_feed(void) -{ - REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE); - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); - REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0); -} - -static inline void bootloader_hardware_init(void) -{ - -} - -static inline void bootloader_ana_reset_config(void) -{ - //Enable WDT, BOD, and GLITCH reset - bootloader_ana_super_wdt_reset_config(true); - bootloader_ana_bod_reset_config(true); - bootloader_ana_clock_glitch_reset_config(true); -} - -esp_err_t bootloader_init(void) -{ - esp_err_t ret = ESP_OK; - - bootloader_hardware_init(); - bootloader_ana_reset_config(); - bootloader_super_wdt_auto_feed(); - -// In RAM_APP, memory will be initialized in `call_start_cpu0` -#if !CONFIG_APP_BUILD_TYPE_RAM - // protect memory region - bootloader_init_mem(); - /* check that static RAM is after the stack */ - assert(&_bss_start <= &_bss_end); - assert(&_data_start <= &_data_end); - // clear bss section - bootloader_clear_bss_section(); -#endif // !CONFIG_APP_BUILD_TYPE_RAM - - // config clock - bootloader_clock_configure(); - // initialize console, from now on, we can use esp_log - bootloader_console_init(); - /* print 2nd bootloader banner */ - bootloader_print_banner(); - -#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - //init cache hal - cache_hal_init(); //TODO IDF-4649 - //init mmu - mmu_hal_init(); - // update flash ID - bootloader_flash_update_id(); - // Check and run XMC startup flow - if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) { - ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!"); - return ret; - } -#if !CONFIG_APP_BUILD_TYPE_RAM - // read bootloader header - if ((ret = bootloader_read_bootloader_header()) != ESP_OK) { - return ret; - } - // read chip revision and check if it's compatible to bootloader - if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) { - return ret; - } -#endif // !CONFIG_APP_BUILD_TYPE_RAM - // initialize spi flash - if ((ret = bootloader_init_spi_flash()) != ESP_OK) { - return ret; - } -#endif // #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP - - // check whether a WDT reset happend - bootloader_check_wdt_reset(); - // config WDT - bootloader_config_wdt(); - // enable RNG early entropy source - bootloader_enable_random(); - return ret; -} diff --git a/components/bootloader_support/src/esp32h4/bootloader_sha.c b/components/bootloader_support/src/esp32h4/bootloader_sha.c deleted file mode 100644 index 1ae0d74459..0000000000 --- a/components/bootloader_support/src/esp32h4/bootloader_sha.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "bootloader_sha.h" -#include -#include -#include -#include - -#include "esp32h4/rom/sha.h" - -static SHA_CTX ctx; - -bootloader_sha256_handle_t bootloader_sha256_start() -{ - // Enable SHA hardware - ets_sha_enable(); - ets_sha_init(&ctx, SHA2_256); - return &ctx; // Meaningless non-NULL value -} - -void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len) -{ - assert(handle != NULL); - assert(data_len % 4 == 0); - ets_sha_update(&ctx, data, data_len, false); -} - -void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest) -{ - assert(handle != NULL); - - if (digest == NULL) { - bzero(&ctx, sizeof(ctx)); - return; - } - ets_sha_finish(&ctx, digest); -} diff --git a/components/bootloader_support/src/esp32h4/bootloader_soc.c b/components/bootloader_support/src/esp32h4/bootloader_soc.c deleted file mode 100644 index f808b72fd5..0000000000 --- a/components/bootloader_support/src/esp32h4/bootloader_soc.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include "soc/soc.h" -#include "soc/rtc_cntl_reg.h" - -void bootloader_ana_super_wdt_reset_config(bool enable) -{ - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); - - if (enable) { - REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } else { - REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); - } -} - -void bootloader_ana_bod_reset_config(bool enable) -{ - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); - - if (enable) { - REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); - } else { - REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); - } -} - -void bootloader_ana_clock_glitch_reset_config(bool enable) -{ - REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); - - if (enable) { - REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); - } else { - REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); - } -} diff --git a/components/bootloader_support/src/esp32h4/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32h4/flash_encryption_secure_features.c deleted file mode 100644 index 163cc7ac86..0000000000 --- a/components/bootloader_support/src/esp32h4/flash_encryption_secure_features.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "esp_flash_encrypt.h" -#include "esp_secure_boot.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" -#include "esp_log.h" -#include "sdkconfig.h" - -static __attribute__((unused)) const char *TAG = "flash_encrypt"; - -esp_err_t esp_flash_encryption_enable_secure_features(void) -{ -#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC - ESP_LOGI(TAG, "Disable UART bootloader encryption..."); - esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT); -#else - ESP_LOGW(TAG, "Not disabling UART bootloader encryption"); -#endif - -#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE - ESP_LOGI(TAG, "Disable UART bootloader cache..."); - esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE); -#else - ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED"); -#endif - -#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG - ESP_LOGI(TAG, "Disable JTAG..."); - esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG); - esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG); -#else - ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED"); -#endif - - esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT); - -#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS) - // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot - // otherwise the Flash Encryption key cannot be read protected - esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS); -#endif - -#ifndef CONFIG_SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE - // Set write-protection for DIS_ICACHE to prevent bricking chip in case it will be set accidentally. - // esp32h4 has DIS_ICACHE. Write-protection bit = 2. - // List of eFuses with the same write protection bit: - // DIS_ICACHE, DIS_USB_JTAG, POWERGLITCH_EN, DIS_FORCE_DOWNLOAD, SPI_DOWNLOAD_MSPI_DIS, - // DIS_TWAI, JTAG_SEL_ENABLE, DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT - esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_ICACHE); -#endif - - return ESP_OK; -} diff --git a/components/bootloader_support/src/esp32h4/secure_boot_secure_features.c b/components/bootloader_support/src/esp32h4/secure_boot_secure_features.c deleted file mode 100644 index a460dbce5e..0000000000 --- a/components/bootloader_support/src/esp32h4/secure_boot_secure_features.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "esp_flash_encrypt.h" -#include "esp_secure_boot.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" -#include "esp_log.h" -#include "sdkconfig.h" - -static __attribute__((unused)) const char *TAG = "secure_boot"; - -esp_err_t esp_secure_boot_enable_secure_features(void) -{ - esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT); - -#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE - ESP_LOGI(TAG, "Enabling Security download mode..."); - esp_err_t err = esp_efuse_enable_rom_secure_download_mode(); - if (err != ESP_OK) { - ESP_LOGE(TAG, "Could not enable Security download mode..."); - return err; - } -#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE - ESP_LOGI(TAG, "Disable ROM Download mode..."); - esp_err_t err = esp_efuse_disable_rom_download_mode(); - if (err != ESP_OK) { - ESP_LOGE(TAG, "Could not disable ROM Download mode..."); - return err; - } -#else - ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED"); -#endif - -#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG - ESP_LOGI(TAG, "Disable hardware & software JTAG..."); - esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG); - esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG); - esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count); -#else - ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED"); -#endif - -#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE - esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE); -#endif - - esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN); - -#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS - bool rd_dis_now = true; -#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED - /* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot - when Flash Encryption is being enabled */ - rd_dis_now = esp_flash_encryption_enabled(); -#endif - if (rd_dis_now) { - ESP_LOGI(TAG, "Prevent read disabling of additional efuses..."); - esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS); - } -#else - ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED"); -#endif - - return ESP_OK; -} diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index ef96101db0..af40d2ab23 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -29,8 +29,6 @@ #include "esp32s3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rom/secure_boot.h" diff --git a/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h b/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h index 540b18aebf..8e8bd43a09 100644 --- a/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h +++ b/components/bootloader_support/src/secure_boot_v2/secure_boot_signature_priv.h @@ -13,8 +13,6 @@ #include "esp32c3/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/secure_boot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt index 15a8052f9a..f04ef4191d 100644 --- a/components/bt/CMakeLists.txt +++ b/components/bt/CMakeLists.txt @@ -17,10 +17,6 @@ if(CONFIG_BT_ENABLED) list(APPEND srcs "controller/esp32c3/bt.c") list(APPEND include_dirs include/esp32c3/include) - elseif(CONFIG_IDF_TARGET_ESP32H4) - list(APPEND srcs "controller/esp32h4/bt.c") - list(APPEND include_dirs include/esp32h4/include) - elseif(CONFIG_IDF_TARGET_ESP32C2) list(APPEND srcs "controller/esp32c2/bt.c") list(APPEND include_dirs include/esp32c2/include) @@ -716,15 +712,6 @@ if(CONFIG_BT_ENABLED) target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3") target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app) - elseif(CONFIG_IDF_TARGET_ESP32H4) - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - # TODO: rename esp32h2 to esp32h4 [BT-2875] - add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta1/libble_app.a") - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - # TODO: rename esp32h2 to esp32h4 [BT-2875] - add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/beta2/libble_app.a") - endif() - target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app) elseif(CONFIG_IDF_TARGET_ESP32C2) add_prebuilt_library(libble_app "controller/lib_esp32c2/esp32c2-bt-lib/libble_app.a") target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app) diff --git a/components/bt/controller/esp32h4/Kconfig.in b/components/bt/controller/esp32h4/Kconfig.in deleted file mode 100644 index 9f5c226a0f..0000000000 --- a/components/bt/controller/esp32h4/Kconfig.in +++ /dev/null @@ -1,392 +0,0 @@ - -menu "HCI Config" - - choice BT_LE_HCI_INTERFACE - prompt "Select HCI interface" - default BT_LE_HCI_INTERFACE_USE_RAM - - config BT_LE_HCI_INTERFACE_USE_RAM - bool "ram" - help - Use RAM as HCI interface - config BT_LE_HCI_INTERFACE_USE_UART - bool "uart" - help - Use UART as HCI interface - endchoice - - config BT_LE_HCI_UART_PORT - int "HCI UART port" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 1 - help - Set the port number of HCI UART - - config BT_LE_HCI_UART_FLOWCTRL - bool "HCI uart Hardware Flow ctrl" - depends on BT_LE_HCI_INTERFACE_USE_UART - default n - - config BT_LE_HCI_UART_TX_PIN - int "HCI uart Tx gpio" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 19 - - config BT_LE_HCI_UART_RX_PIN - int "HCI uart Rx gpio" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 10 - - config BT_LE_HCI_UART_RTS_PIN - int "HCI uart RTS gpio" - depends on BT_LE_HCI_UART_FLOWCTRL - default 4 - - config BT_LE_HCI_UART_CTS_PIN - int "HCI uart CTS gpio" - depends on BT_LE_HCI_UART_FLOWCTRL - default 5 - - config BT_LE_HCI_UART_BAUD - int "HCI uart baudrate" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 921600 - help - HCI uart baud rate 115200 ~ 1000000 - - choice BT_LE_HCI_UART_PARITY - prompt "select uart parity" - depends on BT_LE_HCI_INTERFACE_USE_UART - default BT_LE_HCI_UART_UART_PARITY_DISABLE - - config BT_LE_HCI_UART_UART_PARITY_DISABLE - bool "PARITY_DISABLE" - help - UART_PARITY_DISABLE - config BT_LE_HCI_UART_UART_PARITY_EVEN - bool "PARITY_EVEN" - help - UART_PARITY_EVEN - config BT_LE_HCI_UART_UART_PARITY_ODD - bool "PARITY_ODD" - help - UART_PARITY_ODD - endchoice - - config BT_LE_HCI_UART_TASK_STACK_SIZE - int "HCI uart task stack size" - depends on BT_LE_HCI_INTERFACE_USE_UART - default 1000 - help - Set the size of uart task stack -endmenu - -config BT_LE_CONTROLLER_NPL_OS_PORTING_SUPPORT - bool - default y - help - Enable NPL porting for controller. - - -menuconfig BT_LE_50_FEATURE_SUPPORT - bool "Enable BLE 5 feature" - depends on !BT_NIMBLE_ENABLED - default y - help - Enable BLE 5 feature - -config BT_LE_LL_CFG_FEAT_LE_2M_PHY - bool "Enable 2M Phy" - depends on BT_LE_50_FEATURE_SUPPORT - default y - help - Enable 2M-PHY - -config BT_LE_LL_CFG_FEAT_LE_CODED_PHY - bool "Enable coded Phy" - depends on BT_LE_50_FEATURE_SUPPORT - default y - help - Enable coded-PHY - -config BT_LE_EXT_ADV - bool "Enable extended advertising" - depends on BT_LE_50_FEATURE_SUPPORT - default y - help - Enable this option to do extended advertising. Extended advertising - will be supported from BLE 5.0 onwards. - -if BT_LE_EXT_ADV - config BT_LE_MAX_EXT_ADV_INSTANCES - int "Maximum number of extended advertising instances." - range 0 4 - default 1 - depends on BT_LE_EXT_ADV - help - Change this option to set maximum number of extended advertising - instances. Minimum there is always one instance of - advertising. Enter how many more advertising instances you - want. - Each extended advertising instance will take about 0.5k DRAM. - - config BT_LE_EXT_ADV_MAX_SIZE - int "Maximum length of the advertising data." - range 0 1650 - default 1650 - depends on BT_LE_EXT_ADV - help - Defines the length of the extended adv data. The value should not - exceed 1650. - - config BT_LE_ENABLE_PERIODIC_ADV - bool "Enable periodic advertisement." - default y - depends on BT_LE_EXT_ADV - help - Enable this option to start periodic advertisement. - - config BT_LE_PERIODIC_ADV_SYNC_TRANSFER - bool "Enable Transer Sync Events" - depends on BT_LE_ENABLE_PERIODIC_ADV - default y - help - This enables controller transfer periodic sync events to host - -endif - -config BT_LE_MAX_PERIODIC_SYNCS - int "Maximum number of periodic advertising syncs" - depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED - - range 0 8 - default 1 if BT_LE_ENABLE_PERIODIC_ADV - default 0 - help - Set this option to set the upper limit for number of periodic sync - connections. This should be less than maximum connections allowed by - controller. - -config BT_LE_MAX_PERIODIC_ADVERTISER_LIST - int "Maximum number of periodic advertiser list" - depends on BT_LE_50_FEATURE_SUPPORT && !BT_NIMBLE_ENABLED - range 1 5 - default 5 - help - Set this option to set the upper limit for number of periodic advertiser list. - -menu "Memory Settings" - depends on !BT_NIMBLE_ENABLED - - config BT_LE_MSYS_1_BLOCK_COUNT - int "MSYS_1 Block Count" - default 12 - help - MSYS is a system level mbuf registry. For prepare write & prepare - responses MBUFs are allocated out of msys_1 pool. For NIMBLE_MESH - enabled cases, this block count is increased by 8 than user defined - count. - - config BT_LE_MSYS_1_BLOCK_SIZE - int "MSYS_1 Block Size" - default 256 - help - Dynamic memory size of block 1 - - config BT_LE_MSYS_2_BLOCK_COUNT - int "MSYS_2 Block Count" - default 24 - help - Dynamic memory count - - config BT_LE_MSYS_2_BLOCK_SIZE - int "MSYS_2 Block Size" - default 320 - help - Dynamic memory size of block 2 - - config BT_LE_ACL_BUF_COUNT - int "ACL Buffer count" - default 10 - help - The number of ACL data buffers. - - config BT_LE_ACL_BUF_SIZE - int "ACL Buffer size" - default 517 - help - This is the maximum size of the data portion of HCI ACL data packets. - It does not include the HCI data header (of 4 bytes) - - config BT_LE_HCI_EVT_BUF_SIZE - int "HCI Event Buffer size" - default 257 if BT_LE_EXT_ADV - default 70 - help - This is the size of each HCI event buffer in bytes. In case of - extended advertising, packets can be fragmented. 257 bytes is the - maximum size of a packet. - - config BT_LE_HCI_EVT_HI_BUF_COUNT - int "High Priority HCI Event Buffer count" - default 30 - help - This is the high priority HCI events' buffer size. High-priority - event buffers are for everything except advertising reports. If there - are no free high-priority event buffers then host will try to allocate a - low-priority buffer instead - - config BT_LE_HCI_EVT_LO_BUF_COUNT - int "Low Priority HCI Event Buffer count" - default 8 - help - This is the low priority HCI events' buffer size. Low-priority event - buffers are only used for advertising reports. If there are no free - low-priority event buffers, then an incoming advertising report will - get dropped -endmenu - -config BT_LE_CONTROLLER_TASK_STACK_SIZE - int "Controller task stack size" - default 5120 if BLE_MESH - default 4096 - help - This configures stack size of NimBLE controller task - -config BT_LE_LL_RESOLV_LIST_SIZE - int "BLE LL Resolving list size" - range 1 5 - default 4 - help - Configure the size of resolving list used in link layer. - -menuconfig BT_LE_SECURITY_ENABLE - bool "Enable BLE SM feature" - depends on !BT_NIMBLE_ENABLED - default y - help - Enable BLE sm feature - -config BT_LE_SM_LEGACY - bool "Security manager legacy pairing" - depends on BT_LE_SECURITY_ENABLE - default y - help - Enable security manager legacy pairing - -config BT_LE_SM_SC - bool "Security manager secure connections (4.2)" - depends on BT_LE_SECURITY_ENABLE - default y - help - Enable security manager secure connections - -config BT_LE_SM_SC_DEBUG_KEYS - bool "Use predefined public-private key pair" - default n - depends on BT_LE_SECURITY_ENABLE && BT_LE_SM_SC - help - If this option is enabled, SM uses predefined DH key pair as described - in Core Specification, Vol. 3, Part H, 2.3.5.6.1. This allows to - decrypt air traffic easily and thus should only be used for debugging. - -config BT_LE_LL_CFG_FEAT_LE_ENCRYPTION - bool "Enable LE encryption" - depends on BT_LE_SECURITY_ENABLE - default y - help - Enable encryption connection - -config BT_LE_CRYPTO_STACK_MBEDTLS - bool "Override TinyCrypt with mbedTLS for crypto computations" - default y - depends on !BT_NIMBLE_ENABLED - select MBEDTLS_ECP_RESTARTABLE - select MBEDTLS_CMAC_C - help - Enable this option to choose mbedTLS instead of TinyCrypt for crypto - computations. - -config BT_LE_WHITELIST_SIZE - int "BLE white list size" - range 1 15 - default 12 - depends on !BT_NIMBLE_ENABLED - - help - BLE list size - -config BT_LE_LL_DUP_SCAN_LIST_COUNT - int "BLE duplicate scan list count" - range 1 100 - default 20 - help - config the max count of duplicate scan list - -config BT_LE_LL_SCA - int "BLE Sleep clock accuracy" - range 0 500 - default 60 - help - Sleep clock accuracy of our device (in ppm) - -config BT_LE_MAX_CONNECTIONS - int "Maximum number of concurrent connections" - depends on !BT_NIMBLE_ENABLED - range 1 9 - default 3 - help - Defines maximum number of concurrent BLE connections. For ESP32, user - is expected to configure BTDM_CTRL_BLE_MAX_CONN from controller menu - along with this option. Similarly for ESP32-C3 or ESP32-S3, user is expected to - configure BT_CTRL_BLE_MAX_ACT from controller menu. - Each connection will take about 1k DRAM. - -choice BT_LE_COEX_PHY_CODED_TX_RX_TLIM - prompt "Coexistence: limit on MAX Tx/Rx time for coded-PHY connection" - default BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS - depends on !BT_NIMBLE_ENABLED - help - When using PHY-Coded in BLE connection, limitation on max tx/rx time can be applied to - better avoid dramatic performance deterioration of Wi-Fi. - - config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN - bool "Force Enable" - help - Always enable the limitation on max tx/rx time for Coded-PHY connection - - config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS - bool "Force Disable" - help - Disable the limitation on max tx/rx time for Coded-PHY connection -endchoice - -config BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF - int - depends on !BT_NIMBLE_ENABLED - default 1 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EN - default 0 if BT_LE_COEX_PHY_CODED_TX_RX_TLIM_DIS - -config BT_LE_SLEEP_ENABLE - bool "Enable BLE sleep" - default n - help - Enable BLE sleep - -choice BT_LE_WAKEUP_SOURCE - prompt "BLE light sleep wakeup source" - depends on BT_LE_SLEEP_ENABLE - default BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - config BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - bool "Use ESP timer to wakeup CPU" - help - Use esp timer to wakeup CPU -endchoice - -config BT_LE_USE_ESP_TIMER - bool "Use Esp Timer for callout" - depends on !BT_NIMBLE_ENABLED - default y - help - Set this option to use Esp Timer which has higher priority timer - instead of FreeRTOS timer diff --git a/components/bt/controller/esp32h4/bt.c b/components/bt/controller/esp32h4/bt.c deleted file mode 100644 index 67a66f0c97..0000000000 --- a/components/bt/controller/esp32h4/bt.c +++ /dev/null @@ -1,1169 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include "esp_random.h" -#include - -#include "sdkconfig.h" - -#include "nimble/nimble_port.h" -#include "nimble/nimble_port_freertos.h" - -#ifdef ESP_PLATFORM -#include "esp_log.h" -#endif - -#if CONFIG_SW_COEXIST_ENABLE -#include "esp_coexist_internal.h" -#endif - -#include "nimble/nimble_npl_os.h" -#include "nimble/ble_hci_trans.h" -#include "os/endian.h" - -#include "esp_bt.h" -#include "esp_intr_alloc.h" -#include "esp_sleep.h" -#include "esp_pm.h" -#include "esp_phy_init.h" -#include "soc/system_reg.h" -#include "soc/clkrst_reg.h" - -#include "hci_uart.h" -#include "bt_osi_mem.h" - -#ifdef CONFIG_BT_BLUEDROID_ENABLED -#include "hci/hci_hal.h" -#endif - -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" - -#include "esp_private/periph_ctrl.h" -#include "esp_sleep.h" - -#include "soc/syscon_reg.h" -#include "soc/dport_access.h" - -/* Macro definition - ************************************************************************ - */ - -#define NIMBLE_PORT_LOG_TAG "BLE_INIT" -#define OSI_COEX_VERSION 0x00010006 -#define OSI_COEX_MAGIC_VALUE 0xFADEBEAD - -#define EXT_FUNC_VERSION 0x20221122 -#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5 - -#define BT_ASSERT_PRINT ets_printf - -#ifdef CONFIG_BT_BLUEDROID_ENABLED -/* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */ -#define ACL_DATA_MBUF_LEADINGSPCAE 4 -#endif - -/* Types definition - ************************************************************************ - */ - -struct osi_coex_funcs_t { - uint32_t _magic; - uint32_t _version; - void (* _coex_wifi_sleep_set)(bool sleep); - int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high); - void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); - void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); -}; - -struct ext_funcs_t { - uint32_t ext_version; - int (*_esp_intr_alloc)(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle); - int (*_esp_intr_free)(void **ret_handle); - void *(* _malloc)(size_t size); - void (*_free)(void *p); - void (*_hal_uart_start_tx)(int); - int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *); - int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t); - int (*_hal_uart_close)(int); - void (*_hal_uart_blocking_tx)(int, uint8_t); - int (*_hal_uart_init)(int, void *); - int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id); - void (* _task_delete)(void *task_handle); - void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2); - uint32_t (* _os_random)(void); - int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv); - int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y, const uint8_t *local_priv_key, uint8_t *dhkey); - void (* _esp_reset_rpa_moudle)(void); - uint32_t magic; -}; - - -/* External functions or variables - ************************************************************************ - */ - -extern int ble_plf_set_log_level(int level); -extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs); -extern int ble_controller_init(esp_bt_controller_config_t *cfg); -extern int ble_controller_deinit(void); -extern int ble_controller_enable(uint8_t mode); -extern int ble_controller_disable(void); -extern int esp_register_ext_funcs (struct ext_funcs_t *); -extern void esp_unregister_ext_funcs (void); -extern int esp_ble_ll_set_public_addr(const uint8_t *addr); -extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func); -extern void esp_unregister_npl_funcs (void); -extern void npl_freertos_mempool_deinit(void); -extern int os_msys_buf_alloc(void); -extern uint32_t r_os_cputime_get32(void); -extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks); -extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled); -extern void r_ble_rtc_wake_up_state_clr(void); -extern int os_msys_init(void); -extern void os_msys_buf_free(void); -extern void bt_bb_set_le_tx_on_delay(uint32_t delay_us); -extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, - const uint8_t *peer_pub_key_y, - const uint8_t *our_priv_key, uint8_t *out_dhkey); -extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv); -extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level); -extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle); -extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info); -extern uint32_t _bt_bss_start; -extern uint32_t _bt_bss_end; -extern uint32_t _nimble_bss_start; -extern uint32_t _nimble_bss_end; -extern uint32_t _nimble_data_start; -extern uint32_t _nimble_data_end; -extern uint32_t _bt_data_start; -extern uint32_t _bt_data_end; - -/* Local Function Declaration - ********************************************************************* - */ -static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status); -static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status); -static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id); -static void task_delete_wrapper(void *task_handle); -#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART -static void hci_uart_start_tx_wrapper(int uart_no); -static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func, - hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg); -static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits, - uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl); -static int hci_uart_close_wrapper(int uart_no); -static void hci_uart_blocking_tx_wrapper(int port, uint8_t data); -static int hci_uart_init_wrapper(int uart_no, void *cfg); -#endif -static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in); -static int esp_intr_free_wrapper(void **ret_handle); -static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2); -static uint32_t osi_random_wrapper(void); - -static void esp_reset_rpa_moudle(void); - - -/* Local variable definition - *************************************************************************** - */ - -/* Static variable declare */ -static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; - -/* This variable tells if BLE is running */ -static bool s_ble_active = false; -#ifdef CONFIG_PM_ENABLE -static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL; - -#define BTDM_MIN_TIMER_UNCERTAINTY_US (200) -#endif /* #ifdef CONFIG_PM_ENABLE */ - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER -#define BLE_RTC_DELAY_US (1100) -#endif - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -#define BLE_RTC_DELAY_US (0) -static void ble_sleep_timer_callback(void *arg); -static DRAM_ATTR esp_timer_handle_t s_ble_sleep_timer = NULL; -#endif - - -static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = { - ._magic = OSI_COEX_MAGIC_VALUE, - ._version = OSI_COEX_VERSION, - ._coex_wifi_sleep_set = NULL, - ._coex_core_ble_conn_dyn_prio_get = NULL, - ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, - ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, -}; - -struct ext_funcs_t ext_funcs_ro = { - .ext_version = EXT_FUNC_VERSION, - ._esp_intr_alloc = esp_intr_alloc_wrapper, - ._esp_intr_free = esp_intr_free_wrapper, - ._malloc = bt_osi_mem_malloc_internal, - ._free = bt_osi_mem_free, -#if CONFIG_BT_LE_HCI_INTERFACE_USE_UART - ._hal_uart_start_tx = hci_uart_start_tx_wrapper, - ._hal_uart_init_cbs = hci_uart_init_cbs_wrapper, - ._hal_uart_config = hci_uart_config_wrapper, - ._hal_uart_close = hci_uart_close_wrapper, - ._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper, - ._hal_uart_init = hci_uart_init_wrapper, -#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART - ._task_create = task_create_wrapper, - ._task_delete = task_delete_wrapper, - ._osi_assert = osi_assert_wrapper, - ._os_random = osi_random_wrapper, - ._ecc_gen_key_pair = ble_sm_alg_gen_key_pair, - ._ecc_gen_dh_key = ble_sm_alg_gen_dhkey, - ._esp_reset_rpa_moudle = esp_reset_rpa_moudle, - .magic = EXT_FUNC_MAGIC_VALUE, -}; - -static void IRAM_ATTR esp_reset_rpa_moudle(void) -{ - DPORT_SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_BAH_RST); - DPORT_CLEAR_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, SYSTEM_BLE_SEC_BAH_RST); - -} - -static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2) -{ - BT_ASSERT_PRINT("BLE assert: line %d in function %s, param: 0x%x, 0x%x", ln, fn, param1, param2); - assert(0); -} - -static uint32_t IRAM_ATTR osi_random_wrapper(void) -{ - return esp_random(); -} - -static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) -{ -#if CONFIG_SW_COEXIST_ENABLE - coex_schm_status_bit_set(type, status); -#endif -} - -static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status) -{ -#if CONFIG_SW_COEXIST_ENABLE - coex_schm_status_bit_clear(type, status); -#endif -} -#ifdef CONFIG_BT_BLUEDROID_ENABLED - -bool esp_vhci_host_check_send_available(void) -{ - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - return false; - } - return true; -} - -/** - * Allocates an mbuf for use by the nimble host. - */ -static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space) -{ - struct os_mbuf *om; - int rc; - - om = os_msys_get_pkthdr(0, 0); - if (om == NULL) { - return NULL; - } - - if (om->om_omp->omp_databuf_len < leading_space) { - rc = os_mbuf_free_chain(om); - assert(rc == 0); - return NULL; - } - - om->om_data += leading_space; - - return om; -} - -/** - * Allocates an mbuf suitable for an HCI ACL data packet. - * - * @return An empty mbuf on success; null on memory - * exhaustion. - */ -struct os_mbuf *ble_hs_mbuf_acl_pkt(void) -{ - return ble_hs_mbuf_gen_pkt(4 + 1); -} - -void esp_vhci_host_send_packet(uint8_t *data, uint16_t len) -{ - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - return; - } - - if (*(data) == DATA_TYPE_COMMAND) { - struct ble_hci_cmd *cmd = NULL; - cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD); - memcpy((uint8_t *)cmd, data + 1, len - 1); - ble_hci_trans_hs_cmd_tx((uint8_t *)cmd); - } - - if (*(data) == DATA_TYPE_ACL) { - struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE); - assert(om); - assert(os_mbuf_append(om, &data[1], len - 1) == 0); - ble_hci_trans_hs_acl_tx(om); - } - -} - -esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback) -{ - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - return ESP_FAIL; - } - - ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL); - - return ESP_OK; -} - -#endif -static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id) -{ - return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle, (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY)); -} - -static void task_delete_wrapper(void *task_handle) -{ - vTaskDelete(task_handle); -} - -#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART -static void hci_uart_start_tx_wrapper(int uart_no) -{ - hci_uart_start_tx(uart_no); -} - -static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func, - hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg) -{ - int rc = -1; - rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg); - return rc; -} - - -static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits, uint8_t stop_bits, - uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl) -{ - int rc = -1; - rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl); - return rc; -} - -static int hci_uart_close_wrapper(int uart_no) -{ - int rc = -1; - rc = hci_uart_close(uart_no); - return rc; -} - -static void hci_uart_blocking_tx_wrapper(int port, uint8_t data) -{ - //This function is nowhere to use. -} - -static int hci_uart_init_wrapper(int uart_no, void *cfg) -{ - //This function is nowhere to use. - return 0; -} - -#endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART - -static int ble_hci_unregistered_hook(void*, void*) -{ - ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__); - return 0; -} - -static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in) -{ - int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, arg, (intr_handle_t *)ret_handle_in); - return rc; -} - -static int esp_intr_free_wrapper(void **ret_handle) -{ - int rc = 0; - rc = esp_intr_free((intr_handle_t) * ret_handle); - *ret_handle = NULL; - return rc; -} - -IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg) -{ - if (!s_ble_active) { - return; - } -#ifdef CONFIG_PM_ENABLE -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - uint32_t delta_tick; - uint32_t us_to_sleep; - uint32_t sleep_tick; - uint32_t tick_invalid = *(uint32_t*)(arg); - assert(arg != NULL); - if (!tick_invalid) { - sleep_tick = r_os_cputime_get32(); - // start a timer to wake up and acquire the pm_lock before modem_sleep awakes - delta_tick = enable_tick - sleep_tick; - if (delta_tick & 0x80000000) { - return; - } - us_to_sleep = r_os_cputime_ticks_to_usecs(delta_tick); - if (us_to_sleep <= BTDM_MIN_TIMER_UNCERTAINTY_US) { - return; - } - esp_err_t err = esp_timer_start_once(s_ble_sleep_timer, us_to_sleep - BTDM_MIN_TIMER_UNCERTAINTY_US); - if (err != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ESP timer start failed\n"); - return; - } - } -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - r_ble_rtc_wake_up_state_clr(); -#endif - esp_pm_lock_release(s_pm_lock); -#endif // CONFIG_PM_ENABLE - esp_phy_disable(); - s_ble_active = false; -} - -IRAM_ATTR void controller_wakeup_cb(void *arg) -{ - if (s_ble_active) { - return; - } - esp_phy_enable(); - // need to check if need to call pm lock here -#ifdef CONFIG_PM_ENABLE - esp_pm_lock_acquire(s_pm_lock); -#endif //CONFIG_PM_ENABLE - s_ble_active = true; -} - -#ifdef CONFIG_PM_ENABLE -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -static void ble_sleep_timer_callback(void * arg) -{ - -} - -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -#endif // CONFIG_PM_ENABLE - -esp_err_t controller_sleep_init(void) -{ - esp_err_t rc = 0; -#ifdef CONFIG_BT_LE_SLEEP_ENABLE - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled\n"); - r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US); - -#ifdef CONFIG_PM_ENABLE - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); -#endif // CONFIG_PM_ENABLE - -#endif // CONFIG_BT_LE_SLEEP_ENABLE - - // enable light sleep -#ifdef CONFIG_PM_ENABLE - rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock); - if (rc != ESP_OK) { - goto error; - } - esp_pm_lock_acquire(s_pm_lock); -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - esp_timer_create_args_t create_args = { - .callback = ble_sleep_timer_callback, - .arg = NULL, - .name = "btSlp" - }; - rc = esp_timer_create(&create_args, &s_ble_sleep_timer); - if (rc != ESP_OK) { - goto error; - } - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is ESP timer"); -#endif //CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - esp_sleep_enable_bt_wakeup(); - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer"); -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - - return rc; - -error: - /*lock should release first and then delete*/ - if (s_pm_lock != NULL) { - esp_pm_lock_release(s_pm_lock); - esp_pm_lock_delete(s_pm_lock); - s_pm_lock = NULL; - } -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - if (s_ble_sleep_timer != NULL) { - esp_timer_stop(s_ble_sleep_timer); - esp_timer_delete(s_ble_sleep_timer); - s_ble_sleep_timer = NULL; - } -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - esp_sleep_disable_bt_wakeup(); -#endif // CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - -#endif //CONFIG_PM_ENABLE - return rc; -} - -void controller_sleep_deinit(void) -{ -#ifdef CONFIG_PM_ENABLE -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - r_ble_rtc_wake_up_state_clr(); - esp_sleep_disable_bt_wakeup(); -#endif //CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO); - - /*lock should release first and then delete*/ - if (s_ble_active) { - esp_pm_lock_release(s_pm_lock); - } - - esp_pm_lock_delete(s_pm_lock); - s_pm_lock = NULL; -#ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER - if (s_ble_sleep_timer != NULL) { - esp_timer_stop(s_ble_sleep_timer); - esp_timer_delete(s_ble_sleep_timer); - s_ble_sleep_timer = NULL; - } -#endif //CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER -#endif //CONFIG_PM_ENABLE -} - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -void periph_module_etm_active(void) -{ - /*This part for esp32h4 beta2*/ - REG_SET_BIT(SYSTEM_MODCLK_CONF_REG, SYSTEM_ETM_CLK_SEL | SYSTEM_ETM_CLK_ACTIVE ); //Active ETM clock -} -#endif - -esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) -{ - esp_err_t ret = ESP_OK; - ble_npl_count_info_t npl_info; - memset(&npl_info, 0, sizeof(ble_npl_count_info_t)); - - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_ERR_INVALID_STATE; - } - - if (!cfg) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "cfg is NULL"); - return ESP_ERR_INVALID_ARG; - } - - ret = esp_register_ext_funcs(&ext_funcs_ro); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "register extend functions failed"); - return ret; - } - - /* Initialize the function pointers for OS porting */ - npl_freertos_funcs_init(); - struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get(); - if (!p_npl_funcs) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions get failed"); - return ESP_ERR_INVALID_ARG; - } - - ret = esp_register_npl_funcs(p_npl_funcs); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions register failed"); - goto free_mem; - } - - ble_get_npl_element_info(cfg, &npl_info); - npl_freertos_set_controller_npl_info(&npl_info); - if (npl_freertos_mempool_init() != 0) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed"); - ret = ESP_ERR_INVALID_ARG; - goto free_mem; - } - - /* Initialize the global memory pool */ - ret = os_msys_buf_alloc(); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "os msys alloc failed"); - goto free_mem; - } - - os_msys_init(); -#if CONFIG_BT_NIMBLE_ENABLED - // ble_npl_eventq_init() need to use npl function in rom and must be called after esp_bt_controller_init() - /* Initialize default event queue */ - ble_npl_eventq_init(nimble_port_get_dflt_eventq()); -#endif - - periph_module_enable(PERIPH_BT_MODULE); -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - // only use for esp32h4 beta2 - periph_module_etm_active(); -#endif - - // init phy - esp_phy_enable(); - esp_btbb_enable(); - s_ble_active = true; - // set bb delay - bt_bb_set_le_tx_on_delay(50); - - if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed"); - ret = ESP_ERR_INVALID_ARG; - goto free_controller; - } - -#if CONFIG_SW_COEXIST_ENABLE - coex_init(); -#endif - ret = ble_controller_init(cfg); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret); - goto free_controller; - } - - ret = controller_sleep_init(); - if (ret != ESP_OK) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret); - goto free_controller; - } - - uint8_t mac[6]; - ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT)); - - swap_in_place(mac, 6); - - esp_ble_ll_set_public_addr(mac); - - ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - - ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL, - (ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL); - return ESP_OK; -free_controller: - controller_sleep_deinit(); - ble_controller_deinit(); - esp_btbb_disable(); - esp_phy_disable(); -#if CONFIG_BT_NIMBLE_ENABLED - ble_npl_eventq_deinit(nimble_port_get_dflt_eventq()); -#endif // CONFIG_BT_NIMBLE_ENABLED -free_mem: - os_msys_buf_free(); - npl_freertos_mempool_deinit(); - esp_unregister_npl_funcs(); - npl_freertos_funcs_deinit(); - esp_unregister_ext_funcs(); - return ret; -} - -esp_err_t esp_bt_controller_deinit(void) -{ - if ((ble_controller_status < ESP_BT_CONTROLLER_STATUS_INITED) || (ble_controller_status >= ESP_BT_CONTROLLER_STATUS_ENABLED)) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_FAIL; - } - - controller_sleep_deinit(); - - esp_btbb_disable(); - - if (s_ble_active) { - esp_phy_disable(); - s_ble_active = false; - } - - ble_controller_deinit(); - -#if CONFIG_BT_NIMBLE_ENABLED - /* De-initialize default event queue */ - ble_npl_eventq_deinit(nimble_port_get_dflt_eventq()); -#endif - os_msys_buf_free(); - - esp_unregister_npl_funcs(); - - esp_unregister_ext_funcs(); - - /* De-initialize npl functions */ - npl_freertos_funcs_deinit(); - - npl_freertos_mempool_deinit(); - - ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; - - return ESP_OK; -} - -esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode) -{ - if (mode != ESP_BT_MODE_BLE) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller mode"); - return ESP_FAIL; - } - if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_FAIL; - } -#if CONFIG_SW_COEXIST_ENABLE - coex_enable(); -#endif - if (ble_controller_enable(mode) != 0) { - return ESP_FAIL; - } - ble_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; - return ESP_OK; -} - -esp_err_t esp_bt_controller_disable(void) -{ - if (ble_controller_status < ESP_BT_CONTROLLER_STATUS_ENABLED) { - ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state"); - return ESP_FAIL; - } - if (ble_controller_disable() != 0) { - return ESP_FAIL; - } - ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - return ESP_OK; -} - -esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode) -{ - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__); - return ESP_OK; -} - -static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end) -{ - /* TODO */ - int ret = ESP_ERR_INVALID_SIZE; - /* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is - * is too small to fit a heap. This cannot be termed as a fatal error and hence - * we replace it by ESP_OK - */ - if (ret == ESP_ERR_INVALID_SIZE) { - return ESP_OK; - } - return ret; -} - -esp_err_t esp_bt_mem_release(esp_bt_mode_t mode) -{ - intptr_t mem_start, mem_end; - - if (mode == ESP_BT_MODE_BLE) { - mem_start = (intptr_t)&_bt_bss_start; - mem_end = (intptr_t)&_bt_bss_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - - mem_start = (intptr_t)&_bt_data_start; - mem_end = (intptr_t)&_bt_data_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - - mem_start = (intptr_t)&_nimble_bss_start; - mem_end = (intptr_t)&_nimble_bss_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - - mem_start = (intptr_t)&_nimble_data_start; - mem_end = (intptr_t)&_nimble_data_end; - if (mem_start != mem_end) { - ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end); - ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end)); - } - } - - return ESP_OK; -} - - -esp_bt_controller_status_t esp_bt_controller_get_status(void) -{ - return ble_controller_status; -} - -/* extra functions */ -esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level) -{ - esp_err_t stat = ESP_FAIL; - - switch (power_type) { - case ESP_BLE_PWR_TYPE_DEFAULT: - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { - stat = ESP_OK; - } - break; - case ESP_BLE_PWR_TYPE_CONN_HDL0: - case ESP_BLE_PWR_TYPE_CONN_HDL1: - case ESP_BLE_PWR_TYPE_CONN_HDL2: - case ESP_BLE_PWR_TYPE_CONN_HDL3: - case ESP_BLE_PWR_TYPE_CONN_HDL4: - case ESP_BLE_PWR_TYPE_CONN_HDL5: - case ESP_BLE_PWR_TYPE_CONN_HDL6: - case ESP_BLE_PWR_TYPE_CONN_HDL7: - case ESP_BLE_PWR_TYPE_CONN_HDL8: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) { - stat = ESP_OK; - } - break; - default: - stat = ESP_ERR_NOT_SUPPORTED; - break; - } - - return stat; -} - -esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle, esp_power_level_t power_level) -{ - esp_err_t stat = ESP_FAIL; - switch (power_type) { - case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: - case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: - case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) { - stat = ESP_OK; - } - break; - case ESP_BLE_ENHANCED_PWR_TYPE_ADV: - case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - if (ble_txpwr_set(power_type, handle, power_level) == 0) { - stat = ESP_OK; - } - break; - default: - stat = ESP_ERR_NOT_SUPPORTED; - break; - } - - return stat; -} - -esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type) -{ - int tx_level = 0; - - switch (power_type) { - case ESP_BLE_PWR_TYPE_ADV: - case ESP_BLE_PWR_TYPE_SCAN: - case ESP_BLE_PWR_TYPE_DEFAULT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); - break; - case ESP_BLE_PWR_TYPE_CONN_HDL0: - case ESP_BLE_PWR_TYPE_CONN_HDL1: - case ESP_BLE_PWR_TYPE_CONN_HDL2: - case ESP_BLE_PWR_TYPE_CONN_HDL3: - case ESP_BLE_PWR_TYPE_CONN_HDL4: - case ESP_BLE_PWR_TYPE_CONN_HDL5: - case ESP_BLE_PWR_TYPE_CONN_HDL6: - case ESP_BLE_PWR_TYPE_CONN_HDL7: - case ESP_BLE_PWR_TYPE_CONN_HDL8: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type); - break; - default: - return ESP_PWR_LVL_INVALID; - } - - if (tx_level < 0) { - return ESP_PWR_LVL_INVALID; - } - - return (esp_power_level_t)tx_level; -} - -esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle) -{ - int tx_level = 0; - - switch (power_type) { - case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT: - case ESP_BLE_ENHANCED_PWR_TYPE_SCAN: - case ESP_BLE_ENHANCED_PWR_TYPE_INIT: - tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0); - break; - case ESP_BLE_ENHANCED_PWR_TYPE_ADV: - case ESP_BLE_ENHANCED_PWR_TYPE_CONN: - tx_level = ble_txpwr_get(power_type, handle); - break; - default: - return ESP_PWR_LVL_INVALID; - } - - if (tx_level < 0) { - return ESP_PWR_LVL_INVALID; - } - - return (esp_power_level_t)tx_level; -} - - -#if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED == true) - -#define BLE_SM_KEY_ERR 0x17 - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS -#include "mbedtls/aes.h" - -#if CONFIG_BT_LE_SM_SC -#include "mbedtls/cipher.h" -#include "mbedtls/entropy.h" -#include "mbedtls/ctr_drbg.h" -#include "mbedtls/cmac.h" -#include "mbedtls/ecdh.h" -#include "mbedtls/ecp.h" -#endif - -#else -#include "tinycrypt/aes.h" -#include "tinycrypt/constants.h" -#include "tinycrypt/utils.h" - -#if CONFIG_BT_LE_SM_SC -#include "tinycrypt/cmac_mode.h" -#include "tinycrypt/ecc_dh.h" -#endif - -#endif - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS -#if CONFIG_BT_LE_SM_SC -static mbedtls_ecp_keypair keypair; -#endif -#endif - -int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y, - const uint8_t *our_priv_key, uint8_t *out_dhkey) -{ - uint8_t dh[32]; - uint8_t pk[64]; - uint8_t priv[32]; - int rc = BLE_SM_KEY_ERR; - - swap_buf(pk, peer_pub_key_x, 32); - swap_buf(&pk[32], peer_pub_key_y, 32); - swap_buf(priv, our_priv_key, 32); - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS - struct mbedtls_ecp_point pt = {0}, Q = {0}; - mbedtls_mpi z = {0}, d = {0}; - mbedtls_ctr_drbg_context ctr_drbg = {0}; - mbedtls_entropy_context entropy = {0}; - - uint8_t pub[65] = {0}; - /* Hardcoded first byte of pub key for MBEDTLS_ECP_PF_UNCOMPRESSED */ - pub[0] = 0x04; - memcpy(&pub[1], pk, 64); - - /* Initialize the required structures here */ - mbedtls_ecp_point_init(&pt); - mbedtls_ecp_point_init(&Q); - mbedtls_ctr_drbg_init(&ctr_drbg); - mbedtls_entropy_init(&entropy); - mbedtls_mpi_init(&d); - mbedtls_mpi_init(&z); - - /* Below 3 steps are to validate public key on curve secp256r1 */ - if (mbedtls_ecp_group_load(&keypair.MBEDTLS_PRIVATE(grp), MBEDTLS_ECP_DP_SECP256R1) != 0) { - goto exit; - } - - if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &pt, pub, 65) != 0) { - goto exit; - } - - if (mbedtls_ecp_check_pubkey(&keypair.MBEDTLS_PRIVATE(grp), &pt) != 0) { - goto exit; - } - - /* Set PRNG */ - if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, - NULL, 0)) != 0) { - goto exit; - } - - /* Prepare point Q from pub key */ - if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &Q, pub, 65) != 0) { - goto exit; - } - - if (mbedtls_mpi_read_binary(&d, priv, 32) != 0) { - goto exit; - } - - rc = mbedtls_ecdh_compute_shared(&keypair.MBEDTLS_PRIVATE(grp), &z, &Q, &d, - mbedtls_ctr_drbg_random, &ctr_drbg); - if (rc != 0) { - goto exit; - } - - rc = mbedtls_mpi_write_binary(&z, dh, 32); - if (rc != 0) { - goto exit; - } - -exit: - mbedtls_ecp_point_free(&pt); - mbedtls_mpi_free(&z); - mbedtls_mpi_free(&d); - mbedtls_ecp_point_free(&Q); - mbedtls_entropy_free(&entropy); - mbedtls_ctr_drbg_free(&ctr_drbg); - if (rc != 0) { - return BLE_SM_KEY_ERR; - } - -#else - if (uECC_valid_public_key(pk, &curve_secp256r1) < 0) { - return BLE_SM_KEY_ERR; - } - - rc = uECC_shared_secret(pk, priv, dh, &curve_secp256r1); - if (rc == TC_CRYPTO_FAIL) { - return BLE_SM_KEY_ERR; - } -#endif - - swap_buf(out_dhkey, dh, 32); - return 0; -} - -/* based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */ -static const uint8_t ble_sm_alg_dbg_priv_key[32] = { - 0x3f, 0x49, 0xf6, 0xd4, 0xa3, 0xc5, 0x5f, 0x38, 0x74, 0xc9, 0xb3, 0xe3, - 0xd2, 0x10, 0x3f, 0x50, 0x4a, 0xff, 0x60, 0x7b, 0xeb, 0x40, 0xb7, 0x99, - 0x58, 0x99, 0xb8, 0xa6, 0xcd, 0x3c, 0x1a, 0xbd -}; - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS -static int mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key) -{ - int rc = BLE_SM_KEY_ERR; - mbedtls_entropy_context entropy = {0}; - mbedtls_ctr_drbg_context ctr_drbg = {0}; - - mbedtls_entropy_init(&entropy); - mbedtls_ctr_drbg_init(&ctr_drbg); - mbedtls_ecp_keypair_init(&keypair); - - if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, - NULL, 0)) != 0) { - goto exit; - } - - if ((rc = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, &keypair, - mbedtls_ctr_drbg_random, &ctr_drbg)) != 0) { - goto exit; - } - - if ((rc = mbedtls_mpi_write_binary(&keypair.MBEDTLS_PRIVATE(d), private_key, 32)) != 0) { - goto exit; - } - - size_t olen = 0; - uint8_t pub[65] = {0}; - - if ((rc = mbedtls_ecp_point_write_binary(&keypair.MBEDTLS_PRIVATE(grp), &keypair.MBEDTLS_PRIVATE(Q), MBEDTLS_ECP_PF_UNCOMPRESSED, - &olen, pub, 65)) != 0) { - goto exit; - } - - memcpy(public_key, &pub[1], 64); - -exit: - mbedtls_ctr_drbg_free(&ctr_drbg); - mbedtls_entropy_free(&entropy); - if (rc != 0) { - mbedtls_ecp_keypair_free(&keypair); - return BLE_SM_KEY_ERR; - } - - return 0; -} -#endif - -/** - * pub: 64 bytes - * priv: 32 bytes - */ -int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv) -{ -#if CONFIG_BT_LE_SM_SC_DEBUG_KEYS - swap_buf(pub, ble_sm_alg_dbg_pub_key, 32); - swap_buf(&pub[32], &ble_sm_alg_dbg_pub_key[32], 32); - swap_buf(priv, ble_sm_alg_dbg_priv_key, 32); -#else - uint8_t pk[64]; - - do { - -#if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS - if (mbedtls_gen_keypair(pk, priv) != 0) { - return BLE_SM_KEY_ERR; - } -#else - if (uECC_make_key(pk, priv, &curve_secp256r1) != TC_CRYPTO_SUCCESS) { - return BLE_SM_KEY_ERR; - } -#endif - - /* Make sure generated key isn't debug key. */ - } while (memcmp(priv, ble_sm_alg_dbg_priv_key, 32) == 0); - - swap_buf(pub, pk, 32); - swap_buf(&pub[32], &pk[32], 32); - swap_in_place(priv, 32); -#endif - - return 0; -} - -#endif diff --git a/components/driver/deprecated/driver/adc_types_legacy.h b/components/driver/deprecated/driver/adc_types_legacy.h index c075812323..1f36f22594 100644 --- a/components/driver/deprecated/driver/adc_types_legacy.h +++ b/components/driver/deprecated/driver/adc_types_legacy.h @@ -61,7 +61,7 @@ typedef enum { ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */ ADC1_CHANNEL_MAX, } adc1_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 typedef enum { ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */ @@ -97,7 +97,7 @@ typedef enum { ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */ ADC2_CHANNEL_MAX, } adc2_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 // ESP32C6 has no ADC2 typedef enum { ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */ diff --git a/components/driver/test/test_i2c.c b/components/driver/test/test_i2c.c index 4154233c7b..f675f24da6 100644 --- a/components/driver/test/test_i2c.c +++ b/components/driver/test/test_i2c.c @@ -32,7 +32,7 @@ #define RW_TEST_LENGTH 129 /*!bit_count); - return pkg_ver; -} - - -esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) -{ - int cur_log_scheme = 0; - esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2); - if (!cur_log_scheme) { // not burned yet - return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2); - } else { - return ESP_ERR_INVALID_STATE; - } -} - -esp_err_t esp_efuse_disable_rom_download_mode(void) -{ - return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE); -} - -esp_err_t esp_efuse_enable_rom_secure_download_mode(void) -{ - if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { - return ESP_ERR_INVALID_STATE; - } - return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); -} diff --git a/components/efuse/esp32h4/esp_efuse_rtc_calib.c b/components/efuse/esp32h4/esp_efuse_rtc_calib.c deleted file mode 100644 index 5bfd20b019..0000000000 --- a/components/efuse/esp32h4/esp_efuse_rtc_calib.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "esp_efuse.h" -#include "esp_efuse_table.h" - -int esp_efuse_rtc_calib_get_ver(void) -{ - uint32_t result = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3); - return result; -} - -uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten) -{ - assert(version == 1); - const esp_efuse_desc_t** init_code_efuse; - assert(atten < 4); - if (atten == 0) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; - } else if (atten == 1) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; - } else if (atten == 2) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; - } else { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; - } - - int init_code_size = esp_efuse_get_field_size(init_code_efuse); - assert(init_code_size == 10); - - uint32_t init_code = 0; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size)); - return init_code + 1000; // version 1 logic -} - -esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) -{ - const esp_efuse_desc_t** cal_vol_efuse; - uint32_t calib_vol_expected_mv; - if (version != 1) { - return ESP_ERR_INVALID_ARG; - } - if (atten >= 4) { - return ESP_ERR_INVALID_ARG; - } - if (atten == 0) { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0; - calib_vol_expected_mv = 400; - } else if (atten == 1) { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1; - calib_vol_expected_mv = 550; - } else if (atten == 2) { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2; - calib_vol_expected_mv = 750; - } else { - cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3; - calib_vol_expected_mv = 1370; - } - - assert(cal_vol_efuse[0]->bit_count == 10); - - uint32_t cal_vol = 0; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count)); - - *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol); - *out_vol_mv = calib_vol_expected_mv; - return ESP_OK; -} - -esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) -{ - uint32_t version = esp_efuse_rtc_calib_get_ver(); - if (version != 1) { - *tsens_cal = 0.0; - return ESP_ERR_NOT_SUPPORTED; - } - const esp_efuse_desc_t** cal_temp_efuse; - cal_temp_efuse = ESP_EFUSE_TEMP_CALIB; - int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse); - assert(cal_temp_size == 9); - - uint32_t cal_temp = 0; - esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size); - assert(err == ESP_OK); - (void)err; - // BIT(8) stands for sign: 1: negtive, 0: positive - *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp; - return ESP_OK; -} diff --git a/components/efuse/esp32h4/esp_efuse_table.c b/components/efuse/esp32h4/esp_efuse_table.c deleted file mode 100644 index dd5f5a9f20..0000000000 --- a/components/efuse/esp32h4/esp_efuse_table.c +++ /dev/null @@ -1,1049 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sdkconfig.h" -#include "esp_efuse.h" -#include -#include "esp_efuse_table.h" - -// md5_digest_table 4561606695cfe94477d259619fd723ef -// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. -// If you want to change some fields, you need to change esp_efuse_table.csv file -// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. -// To show efuse_table run the command 'show_efuse_table'. - -static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 32}, // Write protection, -}; - -static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, -}; - -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, -}; - -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL, -}; - -static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, -}; - -static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { - {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, -}; - -static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, -}; - -static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { - {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, -}; - -static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { - {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, -}; - -static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { - {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, -}; - -static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { - {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, -}; - -static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, -}; - -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, -}; - -static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, -}; - -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, -}; - -static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { - {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, -}; - -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, -}; - -static const esp_efuse_desc_t WR_DIS_KEY1[] = { - {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, -}; - -static const esp_efuse_desc_t WR_DIS_KEY2[] = { - {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, -}; - -static const esp_efuse_desc_t WR_DIS_KEY3[] = { - {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, -}; - -static const esp_efuse_desc_t WR_DIS_KEY4[] = { - {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, -}; - -static const esp_efuse_desc_t WR_DIS_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, -}; - -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // Read protection, -}; - -static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, -}; - -static const esp_efuse_desc_t RD_DIS_KEY1[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, -}; - -static const esp_efuse_desc_t RD_DIS_KEY2[] = { - {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, -}; - -static const esp_efuse_desc_t RD_DIS_KEY3[] = { - {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, -}; - -static const esp_efuse_desc_t RD_DIS_KEY4[] = { - {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, -}; - -static const esp_efuse_desc_t RD_DIS_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, -}; - -static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, -}; - -static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // Disable Icache, -}; - -static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // Disable USB JTAG, -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode, -}; - -static const esp_efuse_desc_t DIS_USB_DEVICE[] = { - {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE, -}; - -static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, -}; - -static const esp_efuse_desc_t DIS_TWAI[] = { - {EFUSE_BLK0, 46, 1}, // Disable TWAI function, -}; - -static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., -}; - -static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., -}; - -static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., -}; - -static const esp_efuse_desc_t USB_DREFH[] = { - {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., -}; - -static const esp_efuse_desc_t USB_DREFL[] = { - {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., -}; - -static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, -}; - -static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio, -}; - -static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { - {EFUSE_BLK0, 59, 2}, // Enable btlc gpio, -}; - -static const esp_efuse_desc_t POWERGLITCH_EN[] = { - {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function, -}; - -static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = { - {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch, -}; - -static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, -}; - -static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, -}; - -static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // Key0 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // Key1 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // Key2 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // Key3 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // Key4 purpose, -}; - -static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // Key5 purpose, -}; - -static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // Secure boot enable, -}; - -static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, -}; - -static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, -}; - -static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // Disable usb serial jtag print during rom boot, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Disable download through USB-Serial-JTAG, -}; - -static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, -}; - -static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print., -}; - -static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, -}; - -static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, -}; - -static const esp_efuse_desc_t BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 158, 1}, // Fast verify on wake option in ROM for Secure Boot, -}; - -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], -}; - -static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 123, 8}, // Extend MAC addr [0], - {EFUSE_BLK1, 131, 8}, // Extend MAC addr [1], -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, -}; - -static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, -}; - -static const esp_efuse_desc_t WAFER_VERSION[] = { - {EFUSE_BLK1, 114, 3}, // WAFER version, -}; - -static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32H4, -}; - -static const esp_efuse_desc_t BLOCK1_VERSION[] = { - {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version, -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t BLOCK2_VERSION[] = { - {EFUSE_BLK2, 128, 3}, // Version of BLOCK2, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 131, 9}, // Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 140, 8}, // ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK3, 0, 256}, // User data, -}; - -static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // Custom MAC, -}; - -static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK4, 0, 256}, // Key0 or user data, -}; - -static const esp_efuse_desc_t KEY1[] = { - {EFUSE_BLK5, 0, 256}, // Key1 or user data, -}; - -static const esp_efuse_desc_t KEY2[] = { - {EFUSE_BLK6, 0, 256}, // Key2 or user data, -}; - -static const esp_efuse_desc_t KEY3[] = { - {EFUSE_BLK7, 0, 256}, // Key3 or user data, -}; - -static const esp_efuse_desc_t KEY4[] = { - {EFUSE_BLK8, 0, 256}, // Key4 or user data, -}; - -static const esp_efuse_desc_t KEY5[] = { - {EFUSE_BLK9, 0, 256}, // Key5 or user data, -}; - -static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK10, 0, 256}, // System configuration, -}; - - - - - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { - &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { - &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { - &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { - &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { - &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { - &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { - &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { - &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { - &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { - &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { - &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { - &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { - &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { - &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { - &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { - &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { - &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { - &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { - &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { - &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { - &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // Disable Icache - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // Disable USB JTAG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = { - &DIS_USB_DEVICE[0], // Disable USB_DEVICE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { - &DIS_TWAI[0], // Disable TWAI function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { - &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { - &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // Exchange D+ D- pins - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { - &BTLC_GPIO_ENABLE[0], // Enable btlc gpio - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { - &POWERGLITCH_EN[0], // Set this bit to enable power glitch function - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = { - &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { - &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { - &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { - &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // Key0 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // Key1 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // Key2 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // Key3 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // Key4 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // Key5 purpose - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Secure boot enable - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // Disable direct boot mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Disable usb serial jtag print during rom boot - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Disable download through USB-Serial-JTAG - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[] = { - &BOOT_DISABLE_FAST_WAKE[0], // Fast verify on wake option in ROM for Secure Boot - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // Extend MAC addr [0] - &MAC_EXT[1], // Extend MAC addr [1] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { - &WAFER_VERSION[0], // WAFER version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version 0:ESP32H4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { - &BLOCK1_VERSION[0], // BLOCK1 efuse version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { - &BLOCK2_VERSION[0], // Version of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // Key0 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { - &KEY1[0], // Key1 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { - &KEY2[0], // Key2 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { - &KEY3[0], // Key3 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { - &KEY4[0], // Key4 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { - &KEY5[0], // Key5 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // System configuration - NULL -}; diff --git a/components/efuse/esp32h4/esp_efuse_table.csv b/components/efuse/esp32h4/esp_efuse_table.csv deleted file mode 100644 index cd94d46d37..0000000000 --- a/components/efuse/esp32h4/esp_efuse_table.csv +++ /dev/null @@ -1,156 +0,0 @@ -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1..-) | # -# | EFUSE_BLK1 | |MAX_BLK_LEN*| # -# | ... | | | # -# | EFUSE_BLK10)| | | # -########################################################################## -# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. -# !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# ESP32H4-TODO: IDF-3390 -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 32, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE - WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT - WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 - WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 - WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 - WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 - WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 - WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 - WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 - WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 - WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 - WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN - WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_TINY_BASIC DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 - WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA - WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 - WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 - WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 - WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 - WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 - WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 - WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 - - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 7, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 - RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 - RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 - RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 - RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 - RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 - RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache - DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode - DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE - DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function - DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function - JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. - SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. - DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. - USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. - USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. - USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins - VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio - BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio - POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function - POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch - - # EFUSE_RD_REPEAT_DATA1_REG # - WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key - SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key - SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key - KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose - KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose - - # EFUSE_RD_REPEAT_DATA2_REG # - KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose - KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose - KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose - KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable - SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke - FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - - # EFUSE_RD_REPEAT_DATA3_REG # - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode - DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Disable download through USB-Serial-JTAG - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode - UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. - FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot - SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback - BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Fast verify on wake option in ROM for Secure Boot - - # EFUSE_RD_REPEAT_DATA4_REG # - - -# MAC_SPI_SYS BLOCK# -####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - MAC_EXT, EFUSE_BLK1, 123, 8, Extend MAC addr [0] - , EFUSE_BLK1, 131, 8, Extend MAC addr [1] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version - PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H4 - BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2 - TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data - OCODE, EFUSE_BLK2, 140, 8, ADC OCode - ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 - ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 - ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 - ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 - ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 - ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 - ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 - ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 - -################ -USER_DATA, EFUSE_BLK3, 0, 256, User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC - -################ -KEY0, EFUSE_BLK4, 0, 256, Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration diff --git a/components/efuse/esp32h4/esp_efuse_utility.c b/components/efuse/esp32h4/esp_efuse_utility.c deleted file mode 100644 index 7ce412a8da..0000000000 --- a/components/efuse/esp32h4/esp_efuse_utility.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdkconfig.h" -#include "esp_log.h" -#include "assert.h" -#include "esp_efuse_utility.h" -#include "soc/efuse_periph.h" -#include "hal/efuse_hal.h" - -static const char *TAG = "efuse"; - -#ifdef CONFIG_EFUSE_VIRTUAL -extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; -#endif // CONFIG_EFUSE_VIRTUAL - -/*Range addresses to read blocks*/ -const esp_efuse_range_addr_t range_read_addr_blocks[] = { - {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT - {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M - {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA - {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA - {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 - {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 - {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 - {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 - {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 - {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 - {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 -}; - -static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; - -/*Range addresses to write blocks (it is not real regs, it is buffer) */ -const esp_efuse_range_addr_t range_write_addr_blocks[] = { - {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, - {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, -}; - -#ifndef CONFIG_EFUSE_VIRTUAL -// Update Efuse timing configuration -static esp_err_t esp_efuse_set_timing(void) -{ - // efuse clock is fixed. - // An argument (0) is for compatibility and will be ignored. - efuse_hal_set_timing(0); - return ESP_OK; -} -#endif // ifndef CONFIG_EFUSE_VIRTUAL - -// Efuse read operation: copies data from physical efuses to efuse read registers. -void esp_efuse_utility_clear_program_registers(void) -{ - efuse_hal_read(); - efuse_hal_clear_program_registers(); -} - -esp_err_t esp_efuse_utility_check_errors(void) -{ - return ESP_OK; -} - -// Burn values written to the efuse write registers -esp_err_t esp_efuse_utility_burn_chip(void) -{ - esp_err_t error = ESP_OK; -#ifdef CONFIG_EFUSE_VIRTUAL - ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); - for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { - int subblock = 0; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); - } - } -#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH - esp_efuse_utility_write_efuses_to_flash(); -#endif -#else // CONFIG_EFUSE_VIRTUAL - if (esp_efuse_set_timing() != ESP_OK) { - ESP_LOGE(TAG, "Efuse fields are not burnt"); - } else { - // Permanently update values written to the efuse write registers - // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. - for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { - bool need_burn_block = false; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - if (REG_READ(addr_wr_block) != 0) { - need_burn_block = true; - break; - } - } - if (!need_burn_block) { - continue; - } - if (error) { - // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) - // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. - ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); - continue; - } - efuse_hal_clear_program_registers(); - if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { - uint8_t block_rs[12]; - efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); - hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); - } - unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); - unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); - memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); - - uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data - hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); - int repeat_burn_op = 1; - bool correct_written_data; - bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block); - if (coding_error_before) { - ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); - } - bool coding_error_occurred; - - do { - ESP_LOGI(TAG, "BURN BLOCK%d", num_block); - efuse_hal_program(num_block); // BURN a block - - bool coding_error_after; - for (unsigned i = 0; i < 5; i++) { - efuse_hal_read(); - coding_error_after = efuse_hal_is_coding_error_in_block(num_block); - if (coding_error_after == true) { - break; - } - } - coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false; - if (coding_error_occurred) { - ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); - } - - correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len); - if (!correct_written_data || coding_error_occurred) { - ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); - hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); - } - - } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); - - if (coding_error_occurred) { - ESP_LOGW(TAG, "Coding error was not fixed"); - if (num_block == 0) { - ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); - error = ESP_FAIL; - } - } - if (!correct_written_data) { - ESP_LOGE(TAG, "Written data are incorrect"); - error = ESP_FAIL; - } - } - } -#endif // CONFIG_EFUSE_VIRTUAL - esp_efuse_utility_reset(); - return error; -} - -// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. -// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. -// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. -// They will be filled during the burn operation. -esp_err_t esp_efuse_utility_apply_new_coding_scheme() -{ - // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. - for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { - if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - if (REG_READ(addr_wr_block)) { - int num_reg = 0; - for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { - if (esp_efuse_utility_read_reg(num_block, num_reg)) { - ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); - return ESP_ERR_CODING; - } - } - break; - } - } - } - } - return ESP_OK; -} diff --git a/components/efuse/esp32h4/include/esp_efuse_chip.h b/components/efuse/esp32h4/include/esp_efuse_chip.h deleted file mode 100644 index c5a67663c1..0000000000 --- a/components/efuse/esp32h4/include/esp_efuse_chip.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Type of eFuse blocks ESP32H4 - */ -typedef enum { - EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ - - EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ - - EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ - EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ - - EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ - EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ - - EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ - EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ - - EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ - EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ - - EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ - EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ - - EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ - EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ - - EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ - EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ - - EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ - EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ - EFUSE_BLK_KEY_MAX = 10, - - EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ - EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ - - EFUSE_BLK_MAX -} esp_efuse_block_t; - -/** - * @brief Type of coding scheme - */ -typedef enum { - EFUSE_CODING_SCHEME_NONE = 0, /**< None */ - EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ -} esp_efuse_coding_scheme_t; - -/** - * @brief Type of key purpose - */ -typedef enum { - ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ - ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ - ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ - ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ - ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ -} esp_efuse_purpose_t; - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/include/esp_efuse_rtc_calib.h b/components/efuse/esp32h4/include/esp_efuse_rtc_calib.h deleted file mode 100644 index e495669710..0000000000 --- a/components/efuse/esp32h4/include/esp_efuse_rtc_calib.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get the RTC calibration efuse version - * - * @return Version of the stored efuse - */ -int esp_efuse_rtc_calib_get_ver(void); - -/** - * @brief Get the init code in the efuse, for the corresponding attenuation. - * - * @param version Version of the stored efuse - * @param atten Attenuation of the init code - * @return The init code stored in efuse - */ -uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten); - -/** - * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. - * - * @param version Version of the stored efuse - * @param atten Attenuation to use - * @param out_digi Output buffer of the digits - * @param out_vol_mv Output of the voltage, in mV - * @return - * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid - * - ESP_OK: if success - */ -esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); - -/** - * @brief Get the temperature sensor calibration number delta_T stored in the efuse. - * - * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse. - * - * @return ESP_OK if get the calibration value successfully. - * ESP_ERR_INVALID_ARG if can't get the calibration value. - */ -esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal); - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/include/esp_efuse_table.h b/components/efuse/esp32h4/include/esp_efuse_table.h deleted file mode 100644 index 402f995278..0000000000 --- a/components/efuse/esp32h4/include/esp_efuse_table.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "esp_efuse.h" - -// md5_digest_table 4561606695cfe94477d259619fd723ef -// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. -// If you want to change some fields, you need to change esp_efuse_table.csv file -// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. -// To show efuse_table run the command 'show_efuse_table'. - - -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; -extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/private_include/esp_efuse_utility.h b/components/efuse/esp32h4/private_include/esp_efuse_utility.h deleted file mode 100644 index 37573eea8f..0000000000 --- a/components/efuse/esp32h4/private_include/esp_efuse_utility.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ - -#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 - -#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) - -#ifdef __cplusplus -} -#endif diff --git a/components/efuse/esp32h4/sources.cmake b/components/efuse/esp32h4/sources.cmake deleted file mode 100644 index 9dffd72008..0000000000 --- a/components/efuse/esp32h4/sources.cmake +++ /dev/null @@ -1,4 +0,0 @@ -set(EFUSE_SOC_SRCS "esp_efuse_table.c" - "esp_efuse_fields.c" - "esp_efuse_rtc_calib.c" - "esp_efuse_utility.c") diff --git a/components/esp_adc/esp32h4/include/adc_cali_schemes.h b/components/esp_adc/esp32h4/include/adc_cali_schemes.h deleted file mode 100644 index 2505fb46f6..0000000000 --- a/components/esp_adc/esp32h4/include/adc_cali_schemes.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file adc_cali_schemes.h - * - * @brief Supported calibration schemes - */ - -//Now no scheme supported diff --git a/components/esp_coex/CMakeLists.txt b/components/esp_coex/CMakeLists.txt index 9ea06f892f..55c482ced6 100644 --- a/components/esp_coex/CMakeLists.txt +++ b/components/esp_coex/CMakeLists.txt @@ -8,17 +8,8 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE) set(link_binary_libs 1) set(ldfragments "linker.lf") endif() - - # TODO: need to remove these logic when unsupport esp32h4. - if(IDF_TARGET STREQUAL "esp32h4") - set(srcs - "src/coexist.c" - "esp32h2/esp_coex_adapter.c") - else() - set(srcs - "src/coexist.c" - "${idf_target}/esp_coex_adapter.c") - endif() + set(srcs "src/coexist.c" + "${idf_target}/esp_coex_adapter.c") endif() if(CONFIG_ESP_WIFI_ENABLED) @@ -38,14 +29,8 @@ if(CONFIG_ESP_COEX_SW_COEXIST_ENABLE OR CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE) if(link_binary_libs) set(blob coexist) - # TODO: need to remove these logic when unsupport esp32h4. - if(IDF_TARGET STREQUAL "esp32h4") - add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h2/lib${blob}.a" + add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/lib${blob}.a" REQUIRES ${COMPONENT_NAME}) - else() - add_prebuilt_library(${blob} "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}/lib${blob}.a" - REQUIRES ${COMPONENT_NAME}) - endif() target_link_libraries(${COMPONENT_LIB} PUBLIC ${blob}) endif() diff --git a/components/esp_hw_support/esp_clk.c b/components/esp_hw_support/esp_clk.c index 511b73eb4a..29057fe1b8 100644 --- a/components/esp_hw_support/esp_clk.c +++ b/components/esp_hw_support/esp_clk.c @@ -29,9 +29,6 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rtc.h" diff --git a/components/esp_hw_support/esp_ds.c b/components/esp_hw_support/esp_ds.c index c567508c0a..3be5836549 100644 --- a/components/esp_hw_support/esp_ds.c +++ b/components/esp_hw_support/esp_ds.c @@ -44,10 +44,6 @@ #include "esp32c6/rom/digital_signature.h" #endif -#if CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/digital_signature.h" -#endif - #if CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/digital_signature.h" #endif diff --git a/components/esp_hw_support/include/esp_chip_info.h b/components/esp_hw_support/include/esp_chip_info.h index 49dc9e714d..c9003cde7c 100644 --- a/components/esp_hw_support/include/esp_chip_info.h +++ b/components/esp_hw_support/include/esp_chip_info.h @@ -24,7 +24,6 @@ typedef enum { CHIP_ESP32S2 = 2, //!< ESP32-S2 CHIP_ESP32S3 = 9, //!< ESP32-S3 CHIP_ESP32C3 = 5, //!< ESP32-C3 - CHIP_ESP32H4 = 6, //!< ESP32-H4 CHIP_ESP32C2 = 12, //!< ESP32-C2 CHIP_ESP32C6 = 13, //!< ESP32-C6 CHIP_ESP32H2 = 16, //!< ESP32-H2 diff --git a/components/esp_hw_support/include/esp_mac.h b/components/esp_hw_support/include/esp_mac.h index 6b00695d85..7b1bf37c83 100644 --- a/components/esp_hw_support/include/esp_mac.h +++ b/components/esp_hw_support/include/esp_mac.h @@ -40,8 +40,6 @@ typedef enum { #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES #elif CONFIG_IDF_TARGET_ESP32C3 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES -#elif CONFIG_IDF_TARGET_ESP32H4 -#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H4_UNIVERSAL_MAC_ADDRESSES #elif CONFIG_IDF_TARGET_ESP32C2 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_hw_support/include/soc/esp32h4/esp_crypto_lock.h b/components/esp_hw_support/include/soc/esp32h4/esp_crypto_lock.h deleted file mode 100644 index 67a08741b5..0000000000 --- a/components/esp_hw_support/include/soc/esp32h4/esp_crypto_lock.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Acquire lock for HMAC cryptography peripheral - * - * Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral - */ -void esp_crypto_hmac_lock_acquire(void); - -/** - * @brief Release lock for HMAC cryptography peripheral - * - * Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral - */ -void esp_crypto_hmac_lock_release(void); - -/** - * @brief Acquire lock for DS cryptography peripheral - * - * Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals - */ -void esp_crypto_ds_lock_acquire(void); - -/** - * @brief Release lock for DS cryptography peripheral - * - * Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals - */ -void esp_crypto_ds_lock_release(void); - -/** - * @brief Acquire lock for the SHA and AES cryptography peripheral. - * - */ -void esp_crypto_sha_aes_lock_acquire(void); - -/** - * @brief Release lock for the SHA and AES cryptography peripheral. - * - */ -void esp_crypto_sha_aes_lock_release(void); - - -/** - * @brief Acquire lock for the mpi cryptography peripheral. - * - */ -void esp_crypto_mpi_lock_acquire(void); - -/** - * @brief Release lock for the mpi/rsa cryptography peripheral. - * - */ -void esp_crypto_mpi_lock_release(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_hw_support/include/soc/esp32h4/rtc.h b/components/esp_hw_support/include/soc/esp32h4/rtc.h deleted file mode 100644 index 7586359f4e..0000000000 --- a/components/esp_hw_support/include/soc/esp32h4/rtc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @file esp32h4/rtc.h - * - * This file contains declarations of rtc related functions. - */ - -/** - * @brief Get current value of RTC counter in microseconds - * - * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute - * - * @return current value of RTC counter in microseconds - */ -uint64_t esp_rtc_get_time_us(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_hw_support/include/soc/esp32h4/soc_memprot_types.h b/components/esp_hw_support/include/soc/esp32h4/soc_memprot_types.h deleted file mode 100644 index 0359804ca4..0000000000 --- a/components/esp_hw_support/include/soc/esp32h4/soc_memprot_types.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -////////////////////////////////////////////////////////// -// ESP32-H4 PMS memory protection types -// - -#pragma once - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Memory types recognized by PMS - */ -typedef enum { - MEMPROT_TYPE_NONE = 0x00000000, - MEMPROT_TYPE_ALL = 0x7FFFFFFF, - MEMPROT_TYPE_INVALID = 0x80000000 -} esp_mprot_mem_t; - -/** - * @brief Splitting address (line) type - */ -typedef enum { - MEMPROT_SPLIT_ADDR_NONE = 0x00000000, - MEMPROT_SPLIT_ADDR_ALL = 0x7FFFFFFF, - MEMPROT_SPLIT_ADDR_INVALID = 0x80000000 -} esp_mprot_split_addr_t; - -/** - * @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address) - */ -typedef enum { - MEMPROT_PMS_AREA_NONE = 0x00000000, - MEMPROT_PMS_AREA_ALL = 0x7FFFFFFF, - MEMPROT_PMS_AREA_INVALID = 0x80000000 -} esp_mprot_pms_area_t; - -/** -* @brief Memory protection configuration -*/ -typedef struct { - bool invoke_panic_handler; /*!< Register PMS violation interrupt for panic-handling */ - bool lock_feature; /*!< Lock all PMS settings */ - void *split_addr; /*!< Main I/D splitting address */ - uint32_t mem_type_mask; /*!< Memory types required to protect. See esp_mprot_mem_t enum */ -} esp_memp_config_t; - -#define ESP_MEMPROT_DEFAULT_CONFIG() { \ - .invoke_panic_handler = true, \ - .lock_feature = true, \ - .split_addr = NULL, \ - .mem_type_mask = MEMPROT_TYPE_ALL \ -} - -/** - * @brief Converts Memory protection type to string - * - * @param mem_type Memory protection type - */ -static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type) -{ - switch (mem_type) { - case MEMPROT_TYPE_NONE: - return "MEMPROT_TYPE_NONE"; - case MEMPROT_TYPE_ALL: - return "MEMPROT_TYPE_ALL"; - default: - return "MEMPROT_TYPE_INVALID"; - } -} - -/** - * @brief Converts Splitting address type to string - * - * @param line_type Split line type - */ -static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type) -{ - switch (line_type) { - case MEMPROT_SPLIT_ADDR_NONE: - return "MEMPROT_SPLIT_ADDR_NONE"; - case MEMPROT_SPLIT_ADDR_ALL: - return "MEMPROT_SPLIT_ADDR_ALL"; - default: - return "MEMPROT_SPLIT_ADDR_INVALID"; - } -} - -/** - * @brief Converts PMS Area type to string - * - * @param area_type PMS Area type - */ -static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type) -{ - switch (area_type) { - case MEMPROT_PMS_AREA_NONE: - return "MEMPROT_PMS_AREA_NONE"; - case MEMPROT_PMS_AREA_ALL: - return "MEMPROT_PMS_AREA_ALL"; - default: - return "MEMPROT_PMS_AREA_INVALID"; - } -} - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_hw_support/port/esp32h4/CMakeLists.txt b/components/esp_hw_support/port/esp32h4/CMakeLists.txt deleted file mode 100644 index af789acfd6..0000000000 --- a/components/esp_hw_support/port/esp32h4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -set(srcs "rtc_clk_init.c" - "rtc_clk.c" - "rtc_init.c" - "rtc_sleep.c" - "rtc_time.c" - "chip_info.c" - ) - -if(NOT BOOTLOADER_BUILD) - list(APPEND srcs "esp_crypto_lock.c" - "sar_periph_ctrl.c") - - if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE) - list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c") - endif() - -endif() - -add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") - -target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") -target_include_directories(${COMPONENT_LIB} PUBLIC . private_include) -target_include_directories(${COMPONENT_LIB} PRIVATE ../hal) diff --git a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support deleted file mode 100644 index 2a3d71c4c5..0000000000 --- a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support +++ /dev/null @@ -1,41 +0,0 @@ -choice ESP32H4_REV_MIN - prompt "Minimum Supported ESP32-H4 Revision" - default ESP32H4_REV_MIN_0 - help - Required minimum chip revision. ESP-IDF will check for it and - reject to boot if the chip revision fails the check. - This ensures the chip used will have some modifications (features, or bugfixes). - - The complied binary will only support chips above this revision, - this will also help to reduce binary size. - - config ESP32H4_REV_MIN_0 - bool "Rev v0.0 (ECO0)" -endchoice - -config ESP32H4_REV_MIN_FULL - int - default 0 if ESP32H4_REV_MIN_0 - -config ESP_REV_MIN_FULL - int - default ESP32H4_REV_MIN_FULL - - # - # MAX Revision - # - - comment "Maximum Supported ESP32-H4 Revision (Rev v1.99)" - # Maximum revision that IDF supports. - # It can not be changed by user. - # Only Espressif can change it when a new version will be supported in IDF. - # Supports all chips starting from ESP32H4_REV_MIN_FULL to ESP32H4_REV_MAX_FULL - -config ESP32H4_REV_MAX_FULL - int - default 199 - # keep in sync the "Maximum Supported Revision" description with this value - -config ESP_REV_MAX_FULL - int - default ESP32H4_REV_MAX_FULL diff --git a/components/esp_hw_support/port/esp32h4/Kconfig.mac b/components/esp_hw_support/port/esp32h4/Kconfig.mac deleted file mode 100644 index 3f32df4c49..0000000000 --- a/components/esp_hw_support/port/esp32h4/Kconfig.mac +++ /dev/null @@ -1,19 +0,0 @@ -# ESP32H4-TODO: IDF-3390 -choice ESP32H4_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or derived from a - single base MAC address. - - config ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO - select ESP_MAC_ADDR_UNIVERSE_IEEE802154 - select ESP_MAC_ADDR_UNIVERSE_BT -endchoice - -config ESP32H4_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32H4_UNIVERSAL_MAC_ADDRESSES_TWO diff --git a/components/esp_hw_support/port/esp32h4/Kconfig.rtc b/components/esp_hw_support/port/esp32h4/Kconfig.rtc deleted file mode 100644 index 55068bf315..0000000000 --- a/components/esp_hw_support/port/esp32h4/Kconfig.rtc +++ /dev/null @@ -1,38 +0,0 @@ -choice RTC_CLK_SRC - prompt "RTC clock source" - default RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" - config RTC_CLK_SRC_EXT_CRYS - bool "External 32.768kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - config RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config RTC_CLK_SRC_INT_RC32K - bool "Internal 32kHz RC oscillator" -endchoice - -config RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_RC32K - default 576 if RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. diff --git a/components/esp_hw_support/port/esp32h4/chip_info.c b/components/esp_hw_support/port/esp32h4/chip_info.c deleted file mode 100644 index b234821060..0000000000 --- a/components/esp_hw_support/port/esp32h4/chip_info.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "esp_chip_info.h" -#include "hal/efuse_hal.h" - -void esp_chip_info(esp_chip_info_t *out_info) -{ - memset(out_info, 0, sizeof(*out_info)); - out_info->model = CHIP_ESP32H4; - out_info->revision = efuse_hal_chip_revision(); - out_info->cores = 1; - out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE; -} diff --git a/components/esp_hw_support/port/esp32h4/clk_tree.c b/components/esp_hw_support/port/esp32h4/clk_tree.c deleted file mode 100644 index e4e193a136..0000000000 --- a/components/esp_hw_support/port/esp32h4/clk_tree.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "clk_tree.h" -#include "esp_err.h" -#include "esp_check.h" -#include "soc/rtc.h" -#include "hal/clk_tree_hal.h" -#include "hal/clk_tree_ll.h" -#include "esp_private/clk_tree_common.h" - -static const char *TAG = "clk_tree"; - -esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision, -uint32_t *freq_value) -{ - ESP_RETURN_ON_FALSE(clk_src > 0 && clk_src < SOC_MOD_CLK_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown clk src"); - ESP_RETURN_ON_FALSE(precision < CLK_TREE_SRC_FREQ_PRECISION_INVALID, ESP_ERR_INVALID_ARG, TAG, "unknown precision"); - ESP_RETURN_ON_FALSE(freq_value, ESP_ERR_INVALID_ARG, TAG, "null pointer"); - - uint32_t clk_src_freq = 0; - switch (clk_src) { - case SOC_MOD_CLK_CPU: - clk_src_freq = clk_hal_cpu_get_freq_hz(); - break; - case SOC_MOD_CLK_AHB: - clk_src_freq = clk_hal_ahb_get_freq_hz(); - break; - case SOC_MOD_CLK_APB: - clk_src_freq = clk_hal_apb_get_freq_hz(); - break; - case SOC_MOD_CLK_XTAL: - clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ; - break; - case SOC_MOD_CLK_PLL: - clk_src_freq = clk_ll_bbpll_get_freq_mhz() * MHZ; - break; - case SOC_MOD_CLK_RTC_SLOW: - clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision); - break; - case SOC_MOD_CLK_RTC_FAST: - clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision); - break; - case SOC_MOD_CLK_RC_FAST: - clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision); - break; - case SOC_MOD_CLK_XTAL32K: - clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision); - break; - default: - break; - } - - ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG, - "freq shouldn't be 0, calibration failed"); - *freq_value = clk_src_freq; - return ESP_OK; -} diff --git a/components/esp_hw_support/port/esp32h4/cpu_region_protect.c b/components/esp_hw_support/port/esp32h4/cpu_region_protect.c deleted file mode 100644 index 8590b95ecf..0000000000 --- a/components/esp_hw_support/port/esp32h4/cpu_region_protect.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdkconfig.h" -#include "soc/soc.h" -#include "riscv/csr.h" - -void esp_cpu_configure_region_protection(void) -{ - /* Notes on implementation: - * - * 1) Note: ESP32-H4 CPU doesn't support overlapping PMP regions - * - * 2) Therefore, we use TOR (top of range) entries to map the whole address - * space, bottom to top. - * - * 3) There are not enough entries to describe all the memory regions 100% accurately. - * - * 4) This means some gaps (invalid memory) are accessible. Priority for extending regions - * to cover gaps is to extend read-only or read-execute regions or read-only regions only - * (executing unmapped addresses should always fault with invalid instruction, read-only means - * stores will correctly fault even if reads may return some invalid value.) - * - * 5) Entries are grouped in order with some static asserts to try and verify everything is - * correct. - */ - const unsigned NONE = PMP_L | PMP_TOR; - const unsigned R = PMP_L | PMP_TOR | PMP_R; - const unsigned RW = PMP_L | PMP_TOR | PMP_R | PMP_W; - const unsigned RX = PMP_L | PMP_TOR | PMP_R | PMP_X; - const unsigned RWX = PMP_L | PMP_TOR | PMP_R | PMP_W | PMP_X; - - // 1. Gap at bottom of address space - PMP_ENTRY_SET(0, SOC_DEBUG_LOW, NONE); - - // 2. Debug region - PMP_ENTRY_SET(1, SOC_DEBUG_HIGH, RWX); - _Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region"); - - // 3. Gap between debug region & DROM (flash cache) - PMP_ENTRY_SET(2, SOC_DROM_LOW, NONE); - _Static_assert(SOC_DEBUG_HIGH < SOC_DROM_LOW, "Invalid PMP entry order"); - - // 4. DROM (flash cache) - // 5. Gap between DROM & DRAM - // (Note: To save PMP entries these two are merged into one read-only region) - PMP_ENTRY_SET(3, SOC_DRAM_LOW, R); - _Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid DROM region"); - _Static_assert(SOC_DROM_HIGH < SOC_DRAM_LOW, "Invalid PMP entry order"); - - // 6. DRAM - PMP_ENTRY_SET(4, SOC_DRAM_HIGH, RW); - _Static_assert(SOC_DRAM_LOW < SOC_DRAM_HIGH, "Invalid DRAM region"); - - // 7. Gap between DRAM and Mask DROM - // 8. Mask DROM - // (Note: to save PMP entries these two are merged into one read-only region) - PMP_ENTRY_SET(5, SOC_DROM_MASK_HIGH, R); - _Static_assert(SOC_DRAM_HIGH < SOC_DROM_MASK_LOW, "Invalid PMP entry order"); - _Static_assert(SOC_DROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid mask DROM region"); - - // 9. Gap between mask DROM and mask IROM - // 10. Mask IROM - // (Note: to save PMP entries these two are merged into one RX region) - PMP_ENTRY_SET(6, SOC_IROM_MASK_HIGH, RX); - _Static_assert(SOC_DROM_MASK_HIGH < SOC_IROM_MASK_LOW, "Invalid PMP entry order"); - _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid mask IROM region"); - - // 11. Gap between mask IROM & IRAM - PMP_ENTRY_SET(7, SOC_IRAM_LOW, NONE); - _Static_assert(SOC_IROM_MASK_HIGH < SOC_IRAM_LOW, "Invalid PMP entry order"); - - // 12. IRAM - PMP_ENTRY_SET(8, SOC_IRAM_HIGH, RWX); - _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid IRAM region"); - - // 13. Gap between IRAM and IROM - // 14. IROM (flash cache) - // (Note: to save PMP entries these two are merged into one RX region) - PMP_ENTRY_SET(9, SOC_IROM_HIGH, RX); - _Static_assert(SOC_IRAM_HIGH < SOC_IROM_LOW, "Invalid PMP entry order"); - _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid IROM region"); - - // 15. Gap between IROM & RTC slow memory - PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE); - _Static_assert(SOC_IROM_HIGH < SOC_RTC_IRAM_LOW, "Invalid PMP entry order"); - - // 16. RTC fast memory - PMP_ENTRY_SET(11, SOC_RTC_IRAM_HIGH, RWX); - _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region"); - - // 17. Gap between RTC fast memory & peripheral addresses - PMP_ENTRY_SET(12, SOC_PERIPHERAL_LOW, NONE); - _Static_assert(SOC_RTC_IRAM_HIGH < SOC_PERIPHERAL_LOW, "Invalid PMP entry order"); - - // 18. Peripheral addresses - PMP_ENTRY_SET(13, SOC_PERIPHERAL_HIGH, RW); - _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region"); - - // 19. End of address space - PMP_ENTRY_SET(14, UINT32_MAX, NONE); // all but last 4 bytes - PMP_ENTRY_SET(15, UINT32_MAX, PMP_L | PMP_NA4); // last 4 bytes -} diff --git a/components/esp_hw_support/port/esp32h4/esp_crypto_lock.c b/components/esp_hw_support/port/esp32h4/esp_crypto_lock.c deleted file mode 100644 index 51b02be94d..0000000000 --- a/components/esp_hw_support/port/esp32h4/esp_crypto_lock.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include "esp_crypto_lock.h" - -/* Lock overview: -SHA: peripheral independent, but DMA is shared with AES -AES: peripheral independent, but DMA is shared with SHA -MPI/RSA: independent -HMAC: needs SHA -DS: needs HMAC (which needs SHA), AES and MPI -*/ - -/* Lock for DS peripheral */ -static _lock_t s_crypto_ds_lock; - -/* Lock for HMAC peripheral */ -static _lock_t s_crypto_hmac_lock; - -/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */ -static _lock_t s_crypto_mpi_lock; - -/* Single lock for SHA and AES, sharing a reserved GDMA channel */ -static _lock_t s_crypto_sha_aes_lock; - -void esp_crypto_hmac_lock_acquire(void) -{ - _lock_acquire(&s_crypto_hmac_lock); - esp_crypto_sha_aes_lock_acquire(); -} - -void esp_crypto_hmac_lock_release(void) -{ - esp_crypto_sha_aes_lock_release(); - _lock_release(&s_crypto_hmac_lock); -} - -void esp_crypto_ds_lock_acquire(void) -{ - _lock_acquire(&s_crypto_ds_lock); - esp_crypto_hmac_lock_acquire(); - esp_crypto_mpi_lock_acquire(); -} - -void esp_crypto_ds_lock_release(void) -{ - esp_crypto_mpi_lock_release(); - esp_crypto_hmac_lock_release(); - _lock_release(&s_crypto_ds_lock); -} - -void esp_crypto_sha_aes_lock_acquire(void) -{ - _lock_acquire(&s_crypto_sha_aes_lock); -} - -void esp_crypto_sha_aes_lock_release(void) -{ - _lock_release(&s_crypto_sha_aes_lock); -} - -void esp_crypto_mpi_lock_acquire(void) -{ - _lock_acquire(&s_crypto_mpi_lock); -} - -void esp_crypto_mpi_lock_release(void) -{ - _lock_release(&s_crypto_mpi_lock); -} diff --git a/components/esp_hw_support/port/esp32h4/esp_memprot.c b/components/esp_hw_support/port/esp32h4/esp_memprot.c deleted file mode 100644 index ae6e93e622..0000000000 --- a/components/esp_hw_support/port/esp32h4/esp_memprot.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sdkconfig.h" -#include "soc/periph_defs.h" -#include "esp_intr_alloc.h" -#include "esp_fault.h" -#include "esp_attr.h" -#include "esp_memprot_err.h" -#include "hal/memprot_types.h" -#include "esp_private/esp_memprot_internal.h" -#include "esp_memprot.h" - -esp_err_t esp_mprot_set_split_addr(const esp_mprot_mem_t mem_type, const esp_mprot_split_addr_t line_type, const void *line_addr) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_split_addr(const esp_mprot_mem_t mem_type, const esp_mprot_split_addr_t line_type, void **line_addr) -{ - if (line_addr == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *line_addr = NULL; - - return ESP_OK; -} - -esp_err_t esp_mprot_get_default_main_split_addr(const esp_mprot_mem_t mem_type, void **def_split_addr) -{ - if (def_split_addr == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *def_split_addr = NULL; - - return ESP_OK; -} - -esp_err_t esp_mprot_set_split_addr_lock(const esp_mprot_mem_t mem_type) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_split_addr_lock(const esp_mprot_mem_t mem_type, bool *locked) -{ - if (locked == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *locked = false; - - return ESP_OK; -} - -esp_err_t esp_mprot_set_pms_lock(const esp_mprot_mem_t mem_type) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_pms_lock(const esp_mprot_mem_t mem_type, bool *locked) -{ - if (locked == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *locked = false; - - return ESP_OK; -} - -esp_err_t esp_mprot_set_pms_area(const esp_mprot_pms_area_t area_type, const uint32_t flags) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_pms_area(const esp_mprot_pms_area_t area_type, uint32_t *flags) -{ - if (flags == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *flags = MEMPROT_OP_NONE; - - return ESP_OK; -} - -esp_err_t esp_mprot_set_monitor_lock(const esp_mprot_mem_t mem_type) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_monitor_lock(const esp_mprot_mem_t mem_type, bool *locked) -{ - if (locked == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *locked = false; - - return ESP_OK; -} - -esp_err_t esp_mprot_set_monitor_en(const esp_mprot_mem_t mem_type, const bool enable) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_monitor_en(const esp_mprot_mem_t mem_type, bool *enabled) -{ - if (enabled == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *enabled = false; - - return ESP_OK; -} - -esp_err_t esp_mprot_monitor_clear_intr(const esp_mprot_mem_t mem_type, const int core __attribute__((unused))) -{ - return ESP_OK; -} - -esp_err_t esp_mprot_get_active_intr(esp_memp_intr_source_t *active_memp_intr) -{ - if (active_memp_intr == NULL) { - return ESP_ERR_INVALID_ARG; - } - - active_memp_intr->mem_type = MEMPROT_TYPE_NONE; - active_memp_intr->core = -1; - - return ESP_OK; -} - -esp_err_t esp_mprot_is_conf_locked_any(bool *locked) -{ - if (locked == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *locked = false; - - return ESP_OK; -} - -esp_err_t esp_mprot_is_intr_ena_any(bool *enabled) -{ - if (enabled == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *enabled = false; - - return ESP_OK; -} - -esp_err_t esp_mprot_get_violate_addr(const esp_mprot_mem_t mem_type, void **fault_addr, const int core __attribute__((unused))) -{ - if (fault_addr == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *fault_addr = NULL; - - return ESP_OK; -} - -esp_err_t esp_mprot_get_violate_world(const esp_mprot_mem_t mem_type, esp_mprot_pms_world_t *world, const int core __attribute__((unused))) -{ - if (world == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *world = MEMPROT_PMS_WORLD_NONE; - - return ESP_OK; -} - -esp_err_t esp_mprot_get_violate_operation(const esp_mprot_mem_t mem_type, uint32_t *oper, const int core __attribute__((unused))) -{ - if (oper == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *oper = MEMPROT_OP_NONE; - - return ESP_OK; -} - -bool esp_mprot_has_byte_enables(const esp_mprot_mem_t mem_type) -{ - return false; -} - -esp_err_t esp_mprot_get_violate_byte_enables(const esp_mprot_mem_t mem_type, uint32_t *byte_en, const int core __attribute__((unused))) -{ - if (byte_en == NULL) { - return ESP_ERR_INVALID_ARG; - } - - *byte_en = 0; - - return ESP_OK; -} - -esp_err_t esp_mprot_set_prot(const esp_memp_config_t *memp_config) -{ - return ESP_OK; -} diff --git a/components/esp_hw_support/port/esp32h4/i2c_brownout.h b/components/esp_hw_support/port/esp32h4/i2c_brownout.h deleted file mode 100644 index 1d2ab34411..0000000000 --- a/components/esp_hw_support/port/esp32h4/i2c_brownout.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file i2c_brownout.h - * @brief Register definitions for brownout detector - * - * This file lists register fields of the brownout detector, located on an internal configuration - * bus. These definitions are used via macros defined in i2c_rtc_clk.h. - */ - -#define I2C_BOD 0x61 -#define I2C_BOD_HOSTID 1 - -#define I2C_BOD_THRESHOLD 0x5 -#define I2C_BOD_THRESHOLD_MSB 2 -#define I2C_BOD_THRESHOLD_LSB 0 diff --git a/components/esp_hw_support/port/esp32h4/io_mux.c b/components/esp_hw_support/port/esp32h4/io_mux.c deleted file mode 100644 index d17a300030..0000000000 --- a/components/esp_hw_support/port/esp32h4/io_mux.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_private/io_mux.h" - -esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) -{ - // IO MUX clock source is not selectable - return ESP_OK; -} diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk.c b/components/esp_hw_support/port/esp32h4/rtc_clk.c deleted file mode 100644 index 417d5be1a8..0000000000 --- a/components/esp_hw_support/port/esp32h4/rtc_clk.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include "sdkconfig.h" -#include "esp32h4/rom/ets_sys.h" -#include "esp32h4/rom/rtc.h" -#include "esp32h4/rom/uart.h" -#include "esp32h4/rom/gpio.h" -#include "soc/rtc.h" -#include "esp_private/rtc_clk.h" -#include "soc/io_mux_reg.h" -#include "hal/clk_tree_ll.h" -#include "hal/regi2c_ctrl_ll.h" -#include "hal/gpio_ll.h" -#include "esp_hw_log.h" -#include "esp_rom_sys.h" - -static const char *TAG = "rtc_clk"; - -#define RTC_OSC_FREQ_RC8M 8 - -// Current PLL frequency, in 96MHZ. Zero if PLL is not enabled. -static int s_cur_pll_freq; - -static uint32_t rtc_clk_ahb_freq_get(void); -static void rtc_clk_cpu_freq_to_xtal(int freq, int div); -void rtc_clk_cpu_freq_to_8m(void); - -// Unused as unsupported yet -static uint32_t __attribute((unused)) s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG - -void rtc_clk_bbpll_add_consumer(void) -{ - s_bbpll_digi_consumers_ref_count += 1; -} - -void rtc_clk_bbpll_remove_consumer(void) -{ - s_bbpll_digi_consumers_ref_count -= 1; -} - -static void rtc_gpio_hangup(uint32_t gpio_no) -{ - gpio_ll_pulldown_dis(&GPIO, gpio_no); - gpio_ll_pullup_dis(&GPIO, gpio_no); - gpio_ll_output_disable(&GPIO, gpio_no); - gpio_ll_input_disable(&GPIO, gpio_no); - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_no], PIN_FUNC_GPIO); -} - -void rtc_clk_32k_enable(bool enable) -{ - if (enable) { - /* need to hangup 32K_P and 32K_N pins before enable xtal_32k */ - rtc_gpio_hangup(XTAL32K_P_GPIO_NUM); - rtc_gpio_hangup(XTAL32K_N_GPIO_NUM); - clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL); - } else { - clk_ll_xtal32k_disable(); - } -} - -void rtc_clk_32k_enable_external(void) -{ - clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL); -} - -void rtc_clk_32k_bootstrap(uint32_t cycle) -{ - /* No special bootstrapping needed for ESP32-H4, 'cycle' argument is to keep the signature - * same as for the ESP32. Just enable the XTAL here. - */ - (void)cycle; - rtc_clk_32k_enable(true); -} - -bool rtc_clk_32k_enabled(void) -{ - return clk_ll_xtal32k_is_enabled(); -} - -void rtc_clk_rc32k_enable(bool enable) -{ - if (enable) { - clk_ll_rc32k_enable(); - } else { - clk_ll_rc32k_disable(); - } -} - -void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) -{ - clk_ll_rtc_slow_set_src(clk_src); - rtc_clk_32k_enable((clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? 1 : 0); - rtc_clk_rc32k_enable((clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? 1 : 0); - esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH); -} - -soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void) -{ - return clk_ll_rtc_slow_get_src(); -} - -uint32_t rtc_clk_slow_freq_get_hz(void) -{ - switch (rtc_clk_slow_src_get()) { - case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX; - default: return 0; - } -} - -void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src) -{ - clk_ll_rtc_fast_set_src(clk_src); - esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH); -} - -soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void) -{ - return clk_ll_rtc_fast_get_src(); -} - -static void rtc_clk_bbpll_disable(void) -{ - clk_ll_bbpll_disable(); - s_cur_pll_freq = 0; -} - -static void rtc_clk_bbpll_enable(void) -{ - clk_ll_bbpll_enable(); -} - -static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) -{ - if (!((pll_freq == CLK_LL_PLL_96M_FREQ_MHZ) && (xtal_freq == RTC_XTAL_FREQ_32M))) { - ESP_HW_LOGE(TAG, "invalid pll or xtal frequency"); - } - - // No digital part needs to be set, pll_freq can only be 96MHz - - // Configure analog part - regi2c_ctrl_ll_bbpll_calibration_start(); - clk_ll_bbpll_set_config(pll_freq, xtal_freq); - // Wait until calibration finishes - while (!regi2c_ctrl_ll_bbpll_calibration_is_done()); - // Prevent BBPLL clock jitter - regi2c_ctrl_ll_bbpll_calibration_stop(); - s_cur_pll_freq = pll_freq; -} - -uint32_t rtc_clk_select_root_clk(soc_cpu_clk_src_t cpu_clk_src) -{ - uint32_t root_clk_freq_mhz; - switch (cpu_clk_src) { - case SOC_CPU_CLK_SRC_XTAL: - root_clk_freq_mhz = RTC_XTAL_FREQ_32M; - rtc_clk_bbpll_disable(); - break; - case SOC_CPU_CLK_SRC_PLL: - // SPLL_ENABLE - root_clk_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ; - rtc_clk_bbpll_enable(); - rtc_clk_bbpll_configure(RTC_XTAL_FREQ_32M, root_clk_freq_mhz); - break; - case SOC_CPU_CLK_SRC_RC_FAST: - root_clk_freq_mhz = RTC_OSC_FREQ_RC8M; - rtc_dig_clk8m_enable(); // TODO: Do we need to enable digital gating here? - rtc_clk_8m_divider_set(1); - rtc_clk_bbpll_disable(); - break; - case SOC_CPU_CLK_SRC_XTAL_D2: - root_clk_freq_mhz = RTC_XTAL_FREQ_32M / 2; - rtc_clk_bbpll_disable(); - break; - default: - ESP_HW_LOGE(TAG, "unsupported source clk configuration"); - // fallback to XTAL as root clock source - root_clk_freq_mhz = RTC_XTAL_FREQ_32M; - rtc_clk_bbpll_disable(); - cpu_clk_src = SOC_CPU_CLK_SRC_XTAL; - break; - } - clk_ll_cpu_set_src(cpu_clk_src); - return root_clk_freq_mhz; -} - -/** - * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL. - * PLL must already be enabled. - * @param cpu_freq new CPU frequency - */ -static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) -{ - int div = 1; - if (CLK_LL_PLL_96M_FREQ_MHZ % cpu_freq_mhz == 0) { - div = CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz; - } else { - ESP_HW_LOGE(TAG, "invalid frequency"); - abort(); - } - rtc_clk_cpu_freq_set(SOC_CPU_CLK_SRC_PLL, div); - if (cpu_freq_mhz > RTC_XTAL_FREQ_32M) { - clk_ll_ahb_set_divider(2); - } else { - clk_ll_ahb_set_divider(1); - } - - ets_update_cpu_frequency(cpu_freq_mhz); - rtc_clk_apb_freq_update(rtc_clk_apb_freq_get()); -} - -bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) -{ - // TODO: This function supposes to only fill a cpu config, but it is writing to registers, needs to check - uint32_t source_freq_mhz; - soc_cpu_clk_src_t source; - uint32_t divider; - uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get(); - if (freq_mhz > xtal_freq) { - source = SOC_CPU_CLK_SRC_PLL; - source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ; - divider = CLK_LL_PLL_96M_FREQ_MHZ / freq_mhz; - clk_ll_ahb_set_divider(2); - } else if (freq_mhz != 0) { - source = clk_ll_cpu_get_src(); - source_freq_mhz = rtc_clk_select_root_clk(source); - divider = source_freq_mhz / freq_mhz; - clk_ll_ahb_set_divider(1); - } else { - // unsupported frequency - return false; - } - *out_config = (rtc_cpu_freq_config_t) { - .source = source, - .div = divider, - .source_freq_mhz = source_freq_mhz, - .freq_mhz = freq_mhz - }; - return true; -} - -void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) -{ - uint32_t src_freq_mhz = rtc_clk_select_root_clk(config->source); - uint32_t div = src_freq_mhz / (config->freq_mhz); - rtc_clk_cpu_freq_set(config->source, div); - ets_update_cpu_frequency(config->freq_mhz); -} - -void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) -{ - soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); - uint32_t source_freq_mhz; - uint32_t div; - uint32_t freq_mhz; - switch (source) { - case SOC_CPU_CLK_SRC_XTAL: { - div = clk_ll_cpu_get_divider(); - source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; - break; - } - case SOC_CPU_CLK_SRC_PLL: { - div = clk_ll_cpu_get_divider(); - source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ; - freq_mhz = source_freq_mhz / div; - break; - } - case SOC_CPU_CLK_SRC_RC_FAST: { - source_freq_mhz = RTC_OSC_FREQ_RC8M; - div = clk_ll_cpu_get_divider(); - freq_mhz = source_freq_mhz / div; - break; - } - case SOC_CPU_CLK_SRC_XTAL_D2: { - div = clk_ll_cpu_get_divider(); - source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div / 2; - break; - } - default: { - ESP_HW_LOGE(TAG, "unsupported frequency configuration"); - abort(); - } - } - *out_config = (rtc_cpu_freq_config_t) { - .source = source, - .source_freq_mhz = source_freq_mhz, - .div = div, - .freq_mhz = freq_mhz - }; -} - -void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) -{ - if (config->source == SOC_CPU_CLK_SRC_XTAL) { - rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - } else if (config->source == SOC_CPU_CLK_SRC_PLL && - s_cur_pll_freq == config->source_freq_mhz) { - rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } else { - /* fallback */ - rtc_clk_cpu_freq_set_config(config); - } -} - -void rtc_clk_cpu_freq_set_xtal(void) -{ - rtc_clk_cpu_set_to_default_config(); - rtc_clk_bbpll_disable(); -} - -void rtc_clk_cpu_set_to_default_config(void) -{ - int freq_mhz = (int)rtc_clk_xtal_freq_get(); - - rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); -} - -/** - * Switch to use XTAL as the CPU clock source. - * Must satisfy: cpu_freq = XTAL_FREQ / div. - * Does not disable the PLL. - */ -static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div) -{ - ets_update_cpu_frequency(cpu_freq); - /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */ - rtc_clk_cpu_freq_set(SOC_CPU_CLK_SRC_XTAL, div); - /* no need to adjust the REF_TICK */ - /* switch clock source */ - rtc_clk_apb_freq_update(rtc_clk_apb_freq_get()); -} - -void rtc_clk_cpu_freq_to_8m(void) -{ - ets_update_cpu_frequency(RTC_OSC_FREQ_RC8M); - rtc_clk_select_root_clk(SOC_CPU_CLK_SRC_RC_FAST); - rtc_clk_apb_freq_update(rtc_clk_apb_freq_get()); -} - -rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) -{ - uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); - if (xtal_freq_mhz == 0) { - ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz"); - return RTC_XTAL_FREQ_32M; - } - return (rtc_xtal_freq_t)xtal_freq_mhz; -} - -void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq) -{ - clk_ll_xtal_store_freq_mhz(xtal_freq); -} - -void rtc_clk_apb_freq_update(uint32_t apb_freq) -{ - clk_ll_apb_store_freq_hz(apb_freq); -} - -uint32_t rtc_clk_apb_freq_get(void) -{ - return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider(); -} - -static uint32_t rtc_clk_ahb_freq_get(void) -{ - rtc_cpu_freq_config_t cpu_config; - rtc_clk_cpu_freq_get_config(&cpu_config); - return cpu_config.freq_mhz * MHZ / clk_ll_ahb_get_divider(); -} - -void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div) -{ - if ((uint32_t)clk_ll_cpu_get_src() != source) { - rtc_clk_select_root_clk(source); - } - clk_ll_cpu_set_divider(div); -} - -void rtc_clk_divider_set(uint32_t div) -{ - clk_ll_rc_slow_set_divider(div); -} - -void rtc_clk_8m_divider_set(uint32_t div) -{ - clk_ll_rc_fast_set_divider(div); -} - -void rtc_dig_clk8m_enable(void) -{ - clk_ll_rc_fast_digi_enable(); - esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH); -} - -void rtc_dig_clk8m_disable(void) -{ - clk_ll_rc_fast_digi_disable(); - esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH); -} - -bool rtc_dig_8m_enabled(void) -{ - return clk_ll_rc_fast_digi_is_enabled(); -} - -/* Name used in libphy.a:phy_chip_v7.o - * TODO: update the library to use rtc_clk_xtal_freq_get - */ -rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get"))); diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk_init.c b/components/esp_hw_support/port/esp32h4/rtc_clk_init.c deleted file mode 100644 index f46cfe7e8e..0000000000 --- a/components/esp_hw_support/port/esp32h4/rtc_clk_init.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include "sdkconfig.h" -#include "esp32h4/rom/ets_sys.h" -#include "esp32h4/rom/rtc.h" -#include "esp32h4/rom/uart.h" -#include "esp32h4/rom/gpio.h" -#include "soc/rtc.h" -#include "soc/rtc_periph.h" -#include "soc/rtc_cntl_reg.h" -#include "esp_hw_log.h" -#include "esp_cpu.h" -#include "sdkconfig.h" -#include "esp_rom_uart.h" -#include "soc/system_reg.h" -#include "esp_rom_sys.h" - -static const char *TAG = "rtc_clk_init"; - -void rtc_clk_init(rtc_clk_config_t cfg) -{ - rtc_cpu_freq_config_t old_config, new_config; - - /* Set tuning parameters for 8M and 150k clocks. - * Note: this doesn't attempt to set the clocks to precise frequencies. - * Instead, we calibrate these clocks against XTAL frequency later, when necessary. - * - SCK_DCAP value controls tuning of 150k clock. - * The higher the value of DCAP is, the lower is the frequency. - * - CK8M_DFREQ value controls tuning of 8M clock. - * CLK_8M_DFREQ constant gives the best temperature characteristics. - */ -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); -#endif - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); - - /* enable modem clk */ - REG_WRITE(SYSTEM_MODEM_CLK_EN_REG, UINT32_MAX); - - /* Configure 150k clock division */ - rtc_clk_divider_set(cfg.clk_rtc_clk_div); - - /* Configure 8M clock division */ - rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); - - rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; - esp_rom_uart_tx_wait_idle(0); - rtc_clk_xtal_freq_update(xtal_freq); - rtc_clk_apb_freq_update(rtc_clk_apb_freq_get()); - - /* Set CPU frequency */ - rtc_clk_cpu_freq_get_config(&old_config); - uint32_t freq_before = old_config.freq_mhz; - - rtc_clk_select_root_clk(cfg.root_clk_slt); - bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); - if (!res) { - ESP_HW_LOGE(TAG, "invalid CPU frequency value"); - abort(); - } - rtc_clk_cpu_freq_set_config(&new_config); - - /* Re-calculate the ccount to make time calculation correct. */ - esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); - - /* Slow & fast clocks setup */ - if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - rtc_clk_32k_enable(true); - } - if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) { - rtc_dig_clk8m_enable(); - } - rtc_clk_fast_src_set(cfg.fast_clk_src); - rtc_clk_slow_src_set(cfg.slow_clk_src); -} diff --git a/components/esp_hw_support/port/esp32h4/rtc_init.c b/components/esp_hw_support/port/esp32h4/rtc_init.c deleted file mode 100644 index 40174e3682..0000000000 --- a/components/esp_hw_support/port/esp32h4/rtc_init.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdkconfig.h" -#include "soc/soc.h" -#include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/gpio_reg.h" -#include "soc/spi_mem_reg.h" -#include "soc/extmem_reg.h" -#include "soc/system_reg.h" -#include "soc/syscon_reg.h" -#include "regi2c_ctrl.h" -#include "i2c_pmu.h" -#include "soc/clkrst_reg.h" -#ifndef BOOTLOADER_BUILD -#include "esp_private/sar_periph_ctrl.h" -#endif - -void pmu_ctl(void); -void dcdc_ctl(uint32_t mode); -void regulator_slt(regulator_config_t regula_cfg); - -void rtc_init(rtc_config_t cfg) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN); - - // set default powerup & wait time - rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT(); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles); - - if (cfg.clkctl_init) { - //clear CMMU clock force on - CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON); - //clear tag clock force on - CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON); - //clear register clock force on - CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN); - CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN); - } - - if (cfg.pwrctl_init) { - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - //cancel xtal force pu if no need to force power up - //cannot cancel xtal force pu if pll is force power on - if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) { - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU); - } else { - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU); - } - // force pd APLL - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); - - if (!cfg.bbpll_fpu) { - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); - } else { - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); - } - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU); -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); -#endif - - // clear i2c_reset_protect pd force, need tested in low temperature. - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD); - - /* If this mask is enabled, all soc memories cannot enter power down mode */ - /* We should control soc memory power down mode from RTC, so we will not touch this register any more */ - CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK); - - /* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */ - /* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */ - rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0); - rtc_sleep_pu(pu_cfg); - - //cancel digital PADS force pu - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU); // - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_MEM_FORCE_PU); // - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); // - - //cancel digital PADS force no iso - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); // - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_MEM_FORCE_NOISO); // - - if (cfg.cpu_waiti_clk_gate) { - CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON); - } else { - SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON); - } - /*if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); - } - - REG_WRITE(RTC_CNTL_INT_ENA_REG, 0); - REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX); - if (cfg.pmu_ctl) { - /* pmu init*/ - pmu_ctl(); - } - /* config dcdc frequency */ - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL0_REG, RTC_CNTL_FSW_DCDC, RTC_CNTL_DCDC_FREQ_DEFAULT); - -#ifndef BOOTLOADER_BUILD - //initialise SAR related peripheral register settings - sar_periph_ctrl_init(); -#endif -} - -void pmu_ctl(void) -{ - pmu_config_t pmu_cfg = PMU_CONFIG_DEFAULT(); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_EN_CONT_CAL, pmu_cfg.or_en_cont_cal); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_ENX_RTC_DREG, pmu_cfg.enx_rtc_dreg); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_ENX_DIG_DREG, pmu_cfg.enx_dig_dreg); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, pmu_cfg.en_i2c_rtc_dreg); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, pmu_cfg.en_i2c_dig_dreg); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, pmu_cfg.en_i2c_rtc_dreg_slp); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, pmu_cfg.en_i2c_dig_dreg_slp); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_SLAVE_3P3, pmu_cfg.or_xpd_rtc_slave_3p3); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, pmu_cfg.or_xpd_rtc_reg); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, pmu_cfg.or_xpd_dig_reg); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_PD_RTC_REG_SLP, pmu_cfg.or_pd_rtc_reg_slp); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_PD_DIG_REG_SLP, pmu_cfg.or_pd_dig_reg_slp); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DCDC, pmu_cfg.or_xpd_dcdc); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC, pmu_cfg.or_disalbe_deep_sleep_dcdc); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC, pmu_cfg.or_disalbe_light_sleep_dcdc); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENALBE_TRX_MODE_DCDC, pmu_cfg.or_enalbe_trx_mode_dcdc); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENX_REG_DCDC, pmu_cfg.or_enx_reg_dcdc); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_UNLOCK_DCDC, pmu_cfg.or_unlock_dcdc); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_FORCE_LOCK_DCDC, pmu_cfg.or_force_lock_dcdc); - // REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_ENB_SLOW_CLK, pmu_cfg.or_enb_slow_clk); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, pmu_cfg.or_xpd_trx); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_EN_RESET_CHIP, pmu_cfg.or_en_reset_chip); - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_FORCE_XPD_REG_SLAVE, pmu_cfg.or_force_xpd_reg_slave); -} - -void dslp_osc_pd(void){ - REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG,RTC_CNTL_RC32K_XPD, 0); - REG_SET_FIELD(RTC_CNTL_PLL8M_REG, RTC_CNTL_XPD_PLL8M, 0); -} diff --git a/components/esp_hw_support/port/esp32h4/rtc_sleep.c b/components/esp_hw_support/port/esp32h4/rtc_sleep.c deleted file mode 100644 index d1ffa8f2a9..0000000000 --- a/components/esp_hw_support/port/esp32h4/rtc_sleep.c +++ /dev/null @@ -1,397 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "soc/soc.h" -#include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/syscon_reg.h" -#include "soc/i2s_reg.h" -#include "soc/bb_reg.h" -#include "soc/nrx_reg.h" -#include "soc/fe_reg.h" -#include "soc/timer_group_reg.h" -#include "soc/system_reg.h" -#include "esp32h4/rom/ets_sys.h" -#include "esp32h4/rom/rtc.h" -#include "regi2c_ctrl.h" -#include "soc/regi2c_bias.h" -#include "soc/regi2c_ulp.h" -#include "i2c_pmu.h" -#include "esp_hw_log.h" -#include "esp_rom_uart.h" - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG -#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG -#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG RTC_CNTL_DIGULATOR0_DBIAS_REG -#define RTC_CNTL_REGULATOR1_DBIAS_REG RTC_CNTL_RTCULATOR1_DBIAS_REG -#define RTC_CNTL_REGULATOR0_DBIAS_REG RTC_CNTL_RTCULATOR0_DBIAS_REG -#endif - -/** - * Configure whether certain peripherals are powered down in deep sleep - * @param cfg power down flags as rtc_sleep_pu_config_t structure - */ -static const char *TAG = "rtc_sleep"; - -void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) -{ - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); - REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); - if (cfg.sram_fpu) { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP); - } else { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0); - } - if (cfg.rom_ram_fpu) { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP); - } else { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0); - } -} - -void dcdc_ctl(uint32_t mode) -{ - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_IDLE, RTC_CNTL_DCDC_TRX_MODE); - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_MONITOR, RTC_CNTL_DCDC_TRX_MODE); - if ((mode & 0x10) == 0x10) { - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, mode); - } else if (mode == 0) { - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_TRX_MODE); - } else if (mode == 1) { - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_LSLP_MODE); - } else if (mode == 2) { - REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_DSLP_MODE); - } else { - ESP_HW_LOGE(TAG, "invalid dcdc mode!\n"); - } -} - -void regulator_set(regulator_cfg_t cfg) -{ - // DIG REGULATOR0 - if (cfg.dig_regul0_en) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0); - } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1); - } - // DIG REGULATOR1 - if (cfg.dig_regul1_en) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0); - } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1); - } - // RTC REGULATOR0 - if (cfg.rtc_regul0_en) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 0); - } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 1); - } -} - -void regulator_slt(regulator_config_t regula_cfg) -{ - // dig regulator - if (regula_cfg.dig_source == 1) { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); - } else { - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias); - } - // rtc regulator - if (regula_cfg.rtc_source == 1) { - REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias); - REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); - } else { - REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias); - REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias); - } -} - -void dbias_switch_set(dbias_swt_cfg_t cfg) -{ - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp); -} - -void left_up_trx_fpu(bool fpu) -{ - if (fpu) { - REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP, 0); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_BIAS_BUF, 0); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 0); - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU); - } -} - -void rtc_sleep_pmu_init(void) -{ - dcdc_ctl(DCDC_SLP_DSLP_MODE); - dbias_swt_cfg_t swt_cfg = DBIAS_SWITCH_CONFIG_DEFAULT(); - dbias_switch_set(swt_cfg); - regulator_config_t regula0_cfg = REGULATOR0_CONFIG_DEFAULT(); - regulator_slt(regula0_cfg); - regulator_config_t regula1_cfg = REGULATOR1_CONFIG_DEFAULT(); - regulator_slt(regula1_cfg); - regulator_cfg_t rg_set = REGULATOR_SET_DEFAULT(); - regulator_set(rg_set); - left_up_trx_fpu(0); -} - -void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) -{ - *out_config = (rtc_sleep_config_t) { - .lslp_mem_inf_fpu = 0, - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, - .dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, - .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, - .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, - .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, - .wdt_flashboot_mod_en = 0, - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, - .deep_slp_reject = 1, - .light_slp_reject = 1 - }; - - if ((sleep_flags) & RTC_SLEEP_PD_DIG) { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; - - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; - } else { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; - } -} - -void rtc_sleep_init(rtc_sleep_config_t cfg) -{ - if (cfg.lslp_mem_inf_fpu) { - rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1); - rtc_sleep_pu(pu_cfg); - } - if (cfg.bt_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); - } - if (cfg.cpu_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN); - } - if (cfg.dig_peri_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); - } - if (cfg.dig_ret_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN); - } - - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); - - // ESP32-H4 TO-DO: IDF-3693 - if (cfg.deep_slp) { - // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); - // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, - RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | - RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); - } else { - SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP_EN); - REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - // SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - } - - if (!cfg.int_8m_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); - } - - /* enable VDDSDIO control by state machine */ - REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); - REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); - - /* gating XTAL clock */ - REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING); - esp_rom_uart_tx_wait_idle(0); - -} - -void rtc_sleep_low_init(uint32_t slowclk_period) -{ - // set 5 PWC state machine times to fit in main state machine time - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); -} - -static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu); - -uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu) -{ - REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt); - - /* Start entry into sleep mode */ - SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); - while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, - RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) { - ; - } - - return rtc_sleep_finish(lslp_mem_inf_fpu); -} - -#define STR2(X) #X -#define STR(X) STR2(X) - -uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt) -{ - REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); - WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt); - - /* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep - - Because we may be running from RTC memory as stack, we can't easily call any - functions to do this (as registers will spill to stack, corrupting the CRC). - - Instead, load all the values we need into registers then use register ops only to calculate - the CRC value, write it to the RTC CRC value register, and immediately go into deep sleep. - */ - - /* Values used to set the SYSTEM_RTC_FASTMEM_CONFIG_REG value */ - const unsigned CRC_START_ADDR = 0; - const unsigned CRC_LEN = 0x7ff; - - asm volatile( - /* Start CRC calculation */ - "sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN - "or t0, %1, %2\n" - "sw t0, 0(%0)\n" // set RTC_MEM_CRC_START - - /* Wait for the CRC calculation to finish */ - ".Lwaitcrc:\n" - "fence\n" - "lw t0, 0(%0)\n" - "li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n" - "and t0, t0, t1\n" - "beqz t0, .Lwaitcrc\n" - "not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START - "and t0, t0, %2\n" - "sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START - "fence\n" - "not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged - - /* Store the calculated value in RTC_MEM_CRC_REG */ - "lw t0, 0(%3)\n" - "sw t0, 0(%4)\n" - "fence\n" - - /* Set register bit to go into deep sleep */ - "lw t0, 0(%5)\n" - "or t0, t0, %6\n" - "sw t0, 0(%5)\n" - "fence\n" - - /* Wait for sleep reject interrupt (never finishes if successful) */ - ".Lwaitsleep:" - "fence\n" - "lw t0, 0(%7)\n" - "and t0, t0, %8\n" - "beqz t0, .Lwaitsleep\n" - - : - : - "r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0 - "r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S) - | (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1 - "r" (SYSTEM_RTC_MEM_CRC_START), // %2 - "r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3 - "r" (RTC_MEMORY_CRC_REG), // %4 - "r" (RTC_CNTL_STATE0_REG), // %5 - "r" (RTC_CNTL_SLEEP_EN), // %6 - "r" (RTC_CNTL_INT_RAW_REG), // %7 - "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8 - : "t0", "t1" // working registers - ); - - return rtc_sleep_finish(0); -} - -static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu) -{ - /* In deep sleep mode, we never get here */ - uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW); - SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, - RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); - - /* restore config if it is a light sleep */ - if (lslp_mem_inf_fpu) { - rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1); - rtc_sleep_pu(pu_cfg); - } - return reject; -} diff --git a/components/esp_hw_support/port/esp32h4/rtc_time.c b/components/esp_hw_support/port/esp32h4/rtc_time.c deleted file mode 100644 index 21b23649f8..0000000000 --- a/components/esp_hw_support/port/esp32h4/rtc_time.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "esp32h4/rom/ets_sys.h" -#include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" -#include "hal/clk_tree_ll.h" -#include "hal/rtc_cntl_ll.h" -#include "soc/timer_group_reg.h" -#include "esp_rom_sys.h" - -/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. - * This feature counts the number of XTAL clock cycles within a given number of - * RTC_SLOW_CLK cycles. - * - * Slow clock calibration feature has two modes of operation: one-off and cycling. - * In cycling mode (which is enabled by default on SoC reset), counting of XTAL - * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled - * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed - * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is - * enabled using TIMG_RTC_CALI_START bit. - */ - -/** - * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio - * @param cal_clk which clock to calibrate - * @param slowclk_cycles number of slow clock cycles to count - * @return number of XTAL clock cycles within the given number of slow clock cycles - */ -uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) -{ - /* On ESP32H4, choosing RTC_CAL_RTC_MUX results in calibration of - * the 150k RTC clock regardless of the currenlty selected SLOW_CLK. - * On the ESP32, it used the currently selected SLOW_CLK. - * The following code emulates ESP32 behavior: - */ - if (cal_clk == RTC_CAL_RTC_MUX) { - soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); - if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - cal_clk = RTC_CAL_RC32K; - } - } - - /* Enable requested clock (150k clock is always on) */ - bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { - clk_ll_xtal32k_digi_enable(); - } - bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled(); - if (cal_clk == RTC_CAL_RC32K && !dig_rc32k_enabled) { - clk_ll_rc32k_digi_enable(); - } - /* There may be another calibration process already running during we call this function, - * so we should wait the last process is done. - */ - if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { - /** - * Set a small timeout threshold to accelerate the generation of timeout. - * The internal circuit will be reset when the timeout occurs and will not affect the next calibration. - */ - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1); - while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) - && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); - } - - /* Prepare calibration */ - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); - CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); - /* Figure out how long to wait for calibration to finish */ - - /* Set timeout reg and expect time delay*/ - uint32_t expected_freq; - if (cal_clk == RTC_CAL_32K_XTAL) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; - } else if (cal_clk == RTC_CAL_RC32K) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = SOC_CLK_RC32K_FREQ_APPROX; - } else { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); - expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; - } - uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); - /* Start calibration */ - CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - - /* Wait for calibration to finish up to another us_time_estimate */ - esp_rom_delay_us(us_time_estimate * 3); - uint32_t cal_val; - while (true) { - if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { - cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); - break; - } - if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { - cal_val = 0; - break; - } - } - CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - - /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ - if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { - clk_ll_xtal32k_digi_disable(); - } - /* if dig_rc32k was originally off and enabled due to calibration, then set back to off state */ - if (cal_clk == RTC_CAL_RC32K && !dig_rc32k_enabled) { - clk_ll_rc32k_digi_disable(); - } - - return cal_val; -} - -uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) -{ - uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); - uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles; - uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX); - return ratio; -} - -static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles) -{ - uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768 - uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 - return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta)); -} - -uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) -{ - rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); - uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles); - - if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) { - return 0; - } - - uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; - uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; - uint32_t period = (uint32_t)(period_64 & UINT32_MAX); - return period; -} - -uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) -{ - /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. - * TODO: fix overflow. - */ - return (time_in_us << RTC_CLK_CAL_FRACT) / period; -} - -uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) -{ - return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; -} - -uint64_t rtc_time_get(void) -{ - return rtc_cntl_ll_get_rtc_time(); -} - -void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more -{ - SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE); - while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { - esp_rom_delay_us(1); - } -} - -uint32_t rtc_clk_freq_cal(uint32_t cal_val) -{ - if (cal_val == 0) { - return 0; // cal_val will be denominator, return 0 as the symbol of failure. - } - return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val; -} diff --git a/components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c deleted file mode 100644 index 2b154503c7..0000000000 --- a/components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * SAR related peripherals are interdependent. This file - * provides a united control to these registers, as multiple - * components require these controls. - * - * Related peripherals are: - * - ADC - * - PWDET - */ - -#include "sdkconfig.h" -#include "esp_log.h" -#include "freertos/FreeRTOS.h" -#include "esp_private/sar_periph_ctrl.h" -#include "hal/sar_ctrl_ll.h" - -static const char *TAG = "sar_periph_ctrl"; -extern portMUX_TYPE rtc_spinlock; - - -void sar_periph_ctrl_init(void) -{ - //TODO: IDF-6123 -} - -void sar_periph_ctrl_power_enable(void) -{ - //TODO: IDF-6123 -} - -void sar_periph_ctrl_power_disable(void) -{ - //TODO: IDF-6123 -} - -/** - * This gets incremented when s_sar_power_acquire() is called, - * and decremented when s_sar_power_release() is called. - * PWDET is powered down when the value reaches zero. - * Should be modified within critical section. - */ -static int s_pwdet_power_on_cnt; - -static void s_sar_power_acquire(void) -{ - portENTER_CRITICAL_SAFE(&rtc_spinlock); - s_pwdet_power_on_cnt++; - if (s_pwdet_power_on_cnt == 1) { - sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); - } - portEXIT_CRITICAL_SAFE(&rtc_spinlock); -} - -static void s_sar_power_release(void) -{ - portENTER_CRITICAL_SAFE(&rtc_spinlock); - s_pwdet_power_on_cnt--; - if (s_pwdet_power_on_cnt < 0) { - portEXIT_CRITICAL(&rtc_spinlock); - ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); - abort(); - } else if (s_pwdet_power_on_cnt == 0) { - sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); - } - portEXIT_CRITICAL_SAFE(&rtc_spinlock); -} - - -/*------------------------------------------------------------------------------ -* PWDET Power -*----------------------------------------------------------------------------*/ -void sar_periph_ctrl_pwdet_power_acquire(void) -{ - s_sar_power_acquire(); -} - -void sar_periph_ctrl_pwdet_power_release(void) -{ - s_sar_power_release(); -} - - -/*------------------------------------------------------------------------------ -* ADC Power -*----------------------------------------------------------------------------*/ -void sar_periph_ctrl_adc_oneshot_power_acquire(void) -{ - s_sar_power_acquire(); -} - -void sar_periph_ctrl_adc_oneshot_power_release(void) -{ - s_sar_power_release(); -} - -void sar_periph_ctrl_adc_continuous_power_acquire(void) -{ - s_sar_power_acquire(); -} - -void sar_periph_ctrl_adc_continuous_power_release(void) -{ - s_sar_power_release(); -} diff --git a/components/esp_hw_support/port/esp32h4/systimer.c b/components/esp_hw_support/port/esp32h4/systimer.c deleted file mode 100644 index 88e5fb5b8c..0000000000 --- a/components/esp_hw_support/port/esp32h4/systimer.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_private/systimer.h" - -/** - * @brief systimer's clock source is fixed to XTAL (32MHz), and has a fixed fractional divider (2.0). - * So the resolution of the systimer is 32MHz/2.0 = 16MHz. - */ - -uint64_t systimer_ticks_to_us(uint64_t ticks) -{ - return ticks / 16; -} - -uint64_t systimer_us_to_ticks(uint64_t us) -{ - return us * 16; -} diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 9538e80fbd..d5c545fef4 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -76,8 +76,6 @@ #include "esp_private/mspi_timing_tuning.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 @@ -115,9 +113,6 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (105) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37) -#elif CONFIG_IDF_TARGET_ESP32H4 -#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105) -#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37) #elif CONFIG_IDF_TARGET_ESP32C2 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9) diff --git a/components/esp_hw_support/sleep_wake_stub.c b/components/esp_hw_support/sleep_wake_stub.c index ec8153fe8c..c511b70340 100644 --- a/components/esp_hw_support/sleep_wake_stub.c +++ b/components/esp_hw_support/sleep_wake_stub.c @@ -41,8 +41,6 @@ #include "esp32s3/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32H2 diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c index 46f0edbe1b..3425455c1e 100644 --- a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c +++ b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c @@ -40,9 +40,6 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" #include "esp32c3/rom/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" -#include "esp32h4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #include "esp32c2/rom/rtc.h" diff --git a/components/esp_mm/port/esp32h4/ext_mem_layout.c b/components/esp_mm/port/esp32h4/ext_mem_layout.c deleted file mode 100644 index d81ec0cc82..0000000000 --- a/components/esp_mm/port/esp32h4/ext_mem_layout.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include "sdkconfig.h" -#include "soc/ext_mem_defs.h" -#include "../ext_mem_layout.h" - -/** - * The start addresses in this list should always be sorted from low to high, as MMU driver will need to - * coalesce adjacent regions - */ -const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = { - [0] = { - .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW, - .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH, - .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR), - .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0, - .targets = MMU_TARGET_FLASH0, - .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT, - }, -}; diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index 77bdc3d238..6b68cc9596 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -47,16 +47,7 @@ idf_component_register(SRCS "${srcs}" ) set(target_name "${idf_target}") -if(IDF_TARGET STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h4/rev2") - endif() - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/esp32h4/rev1") - endif() -else() - target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}") -endif() +target_link_directories(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}") # Override functions in PHY lib with the functions in 'phy_override.c' target_link_libraries(${COMPONENT_LIB} INTERFACE "-u include_esp_phy_override") diff --git a/components/esp_phy/src/phy_init_esp32hxx.c b/components/esp_phy/src/phy_init_esp32hxx.c index d1ac1f454f..faaf3bc6cb 100644 --- a/components/esp_phy/src/phy_init_esp32hxx.c +++ b/components/esp_phy/src/phy_init_esp32hxx.c @@ -54,10 +54,10 @@ void esp_phy_enable(void) s_phy_access_ref++; _lock_release(&s_phy_access_lock); - // ESP32H4-TODO: enable common clk. + // ESP32H2-TODO: enable common clk. } void esp_phy_disable(void) { - // ESP32H4-TODO: close rf and disable clk for modem sleep and light sleep + // ESP32H2-TODO: close rf and disable clk for modem sleep and light sleep } diff --git a/components/esp_pm/include/esp32h4/pm.h b/components/esp_pm/include/esp32h4/pm.h deleted file mode 100644 index 1078f77812..0000000000 --- a/components/esp_pm/include/esp32h4/pm.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -#warning "esp_pm_config_esp32h4_t is deprecated, please include esp_pm.h and use esp_pm_config_t instead" - -/* backward compatibility */ -#include "esp_pm.h" diff --git a/components/esp_pm/include/esp_pm.h b/components/esp_pm/include/esp_pm.h index f64bdd93cf..7e34b21380 100644 --- a/components/esp_pm/include/esp_pm.h +++ b/components/esp_pm/include/esp_pm.h @@ -33,7 +33,6 @@ typedef esp_pm_config_t esp_pm_config_esp32_t __attribute__((deprecated("pleas typedef esp_pm_config_t esp_pm_config_esp32s2_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32s3_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32c3_t __attribute__((deprecated("please use esp_pm_config_t instead"))); -typedef esp_pm_config_t esp_pm_config_esp32h4_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32c2_t __attribute__((deprecated("please use esp_pm_config_t instead"))); typedef esp_pm_config_t esp_pm_config_esp32c6_t __attribute__((deprecated("please use esp_pm_config_t instead"))); diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index d4ff1804a8..13343f48f4 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -73,8 +73,6 @@ #define REF_CLK_DIV_MIN 2 // TODO: IDF-5660 #elif CONFIG_IDF_TARGET_ESP32C3 #define REF_CLK_DIV_MIN 2 -#elif CONFIG_IDF_TARGET_ESP32H4 -#define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32C2 #define REF_CLK_DIV_MIN 2 #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_pm/pm_trace.c b/components/esp_pm/pm_trace.c index c77e77ffb3..c23d10e099 100644 --- a/components/esp_pm/pm_trace.c +++ b/components/esp_pm/pm_trace.c @@ -15,7 +15,7 @@ * Feel free to change when debugging. */ static const int DRAM_ATTR s_trace_io[] = { -#if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32H4) && !defined(CONFIG_IDF_TARGET_ESP32C2) +#if !defined(CONFIG_IDF_TARGET_ESP32C3) && !defined(CONFIG_IDF_TARGET_ESP32C2) BIT(4), BIT(5), // ESP_PM_TRACE_IDLE BIT(16), BIT(17), // ESP_PM_TRACE_TICK BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH diff --git a/components/esp_pm/test_apps/esp_pm/main/test_pm.c b/components/esp_pm/test_apps/esp_pm/main/test_pm.c index af98d2c54a..e341dc1f57 100644 --- a/components/esp_pm/test_apps/esp_pm/main/test_pm.c +++ b/components/esp_pm/test_apps/esp_pm/main/test_pm.c @@ -67,8 +67,6 @@ static const int test_freqs[] = {40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, 40, 80 #elif CONFIG_IDF_TARGET_ESP32C2 static const int test_freqs[] = {CONFIG_XTAL_FREQ, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, CONFIG_XTAL_FREQ, 80, CONFIG_XTAL_FREQ / 2, CONFIG_XTAL_FREQ}; // C2 xtal has 40/26MHz option -#elif CONFIG_IDF_TARGET_ESP32H4 -static const int test_freqs[] = {32, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 32} // TODO: IDF-3786 #else static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40}; #endif diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index f2fdb079d4..c74be6db21 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -51,15 +51,7 @@ idf_component_register(SRCS ${sources} PRIV_REQUIRES ${private_required_comp} LDFRAGMENTS linker.lf) -if(target STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - set(ld_folder "ld/rev1") - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - set(ld_folder "ld/rev2") - endif() -else() - set(ld_folder "ld") -endif() +set(ld_folder "ld") # Append a target linker script at the target-specific path, # only the 'name' part is different for each script @@ -108,9 +100,6 @@ if(BOOTLOADER_BUILD) elseif(target STREQUAL "esp32c3") rom_linker_script("newlib") - elseif(target STREQUAL "esp32h4") - rom_linker_script("newlib") - elseif(target STREQUAL "esp32c2") rom_linker_script("newlib") rom_linker_script("mbedtls") @@ -215,16 +204,6 @@ else() # Regular app build rom_linker_script("eco3") endif() - elseif(target STREQUAL "esp32h4") - rom_linker_script("newlib") - rom_linker_script("version") - - if(CONFIG_NEWLIB_NANO_FORMAT AND time_t_size EQUAL 4) - # nano formatting functions in ROM are built for 32-bit time_t, - # only link them if the toolchain is also using 32-bit time_t and nano formatting was requested. - rom_linker_script("newlib-nano") - endif() - elseif(target STREQUAL "esp32c2") rom_linker_script("newlib") rom_linker_script("version") diff --git a/components/esp_rom/README.md b/components/esp_rom/README.md index 3cef0e4c82..e1f7f4385e 100644 --- a/components/esp_rom/README.md +++ b/components/esp_rom/README.md @@ -17,8 +17,6 @@ When using ROM functions in esp-idf, the including convention is `/rom/< #include "esp32c3/rom/uart.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/uart.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/uart.h" ... ``` diff --git a/components/esp_rom/esp32h4/Kconfig.soc_caps.in b/components/esp_rom/esp32h4/Kconfig.soc_caps.in deleted file mode 100644 index b8f83cc125..0000000000 --- a/components/esp_rom/esp32h4/Kconfig.soc_caps.in +++ /dev/null @@ -1,60 +0,0 @@ -##################################################### -# This file is auto-generated from SoC caps -# using gen_soc_caps_kconfig.py, do not edit manually -##################################################### - -config ESP_ROM_HAS_CRC_LE - bool - default y - -config ESP_ROM_HAS_CRC_BE - bool - default y - -config ESP_ROM_HAS_MZ_CRC32 - bool - default y - -config ESP_ROM_HAS_JPEG_DECODE - bool - default y - -config ESP_ROM_UART_CLK_IS_XTAL - bool - default y - -config ESP_ROM_USB_SERIAL_DEVICE_NUM - int - default 3 - -config ESP_ROM_HAS_RETARGETABLE_LOCKING - bool - default y - -config ESP_ROM_HAS_ERASE_0_REGION_BUG - bool - default y - -config ESP_ROM_GET_CLK_FREQ - bool - default y - -config ESP_ROM_HAS_LAYOUT_TABLE - bool - default y - -config ESP_ROM_HAS_ETS_PRINTF_BUG - bool - default y - -config ESP_ROM_HAS_NEWLIB_NANO_FORMAT - bool - default y - -config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE - bool - default y - -config ESP_ROM_RAM_APP_NEEDS_MMU_INIT - bool - default y diff --git a/components/esp_rom/esp32h4/esp_rom_caps.h b/components/esp_rom/esp32h4/esp_rom_caps.h deleted file mode 100644 index 30336691dc..0000000000 --- a/components/esp_rom/esp32h4/esp_rom_caps.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian -#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian -#define ESP_ROM_HAS_MZ_CRC32 (1) // ROM has mz_crc32 function -#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM -#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. -#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking -#define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug -#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` -#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table -#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register -#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions -#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap -#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld deleted file mode 100644 index 8a1eb5afe0..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld +++ /dev/null @@ -1,62 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** ROM APIs - */ -PROVIDE ( esp_rom_crc32_le = crc32_le ); -PROVIDE ( esp_rom_crc16_le = crc16_le ); -PROVIDE ( esp_rom_crc8_le = crc8_le ); -PROVIDE ( esp_rom_crc32_be = crc32_be ); -PROVIDE ( esp_rom_crc16_be = crc16_be ); -PROVIDE ( esp_rom_crc8_be = crc8_be ); - -PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); -PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); -PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); -PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); -PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); -PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); - -PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); -PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); -PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); -PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); - -PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); -PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); -PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); -PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); -PROVIDE ( esp_rom_uart_rx_string = UartRxString ); -PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); -PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - -PROVIDE ( esp_rom_md5_init = MD5Init ); -PROVIDE ( esp_rom_md5_update = MD5Update ); -PROVIDE ( esp_rom_md5_final = MD5Final ); - -PROVIDE ( esp_rom_software_reset_system = software_reset ); -PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); - -PROVIDE ( esp_rom_printf = ets_printf ); -PROVIDE ( esp_rom_delay_us = ets_delay_us ); -PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); -PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); -PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); - -PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); -PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); -PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable); -PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); - -PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); -PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); -PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); -PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld deleted file mode 100644 index ffad80955c..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.ld +++ /dev/null @@ -1,723 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group common - ***************************************/ - -/* Functions */ -rtc_get_reset_reason = 0x40000018; -analog_super_wdt_reset_happened = 0x4000001c; -jtag_cpu_reset_happened = 0x40000020; -rtc_get_wakeup_cause = 0x40000024; -rtc_select_apb_bridge = 0x40000028; -rtc_unhold_all_pads = 0x4000002c; -ets_is_print_boot = 0x40000030; -ets_printf = 0x40000034; -ets_install_putc1 = 0x40000038; -ets_install_uart_printf = 0x4000003c; -ets_install_putc2 = 0x40000040; -PROVIDE( ets_delay_us = 0x40000044 ); -ets_get_stack_info = 0x40000048; -ets_install_lock = 0x4000004c; -ets_backup_dma_copy = 0x40000050; -ets_apb_backup_init_lock_func = 0x40000054; -UartRxString = 0x40000058; -uart_tx_one_char = 0x4000005c; -uart_tx_one_char2 = 0x40000060; -uart_rx_one_char = 0x40000064; -uart_rx_one_char_block = 0x40000068; -uart_rx_readbuff = 0x4000006c; -uartAttach = 0x40000070; -uart_tx_flush = 0x40000074; -uart_tx_wait_idle = 0x40000078; -uart_div_modify = 0x4000007c; -multofup = 0x40000080; -software_reset = 0x40000084; -software_reset_cpu = 0x40000088; -assist_debug_clock_enable = 0x4000008c; -assist_debug_record_enable = 0x40000090; -clear_super_wdt_reset_flag = 0x40000094; -disable_default_watchdog = 0x40000098; -esp_rom_set_rtc_wake_addr = 0x4000009c; -esp_rom_get_rtc_wake_addr = 0x400000a0; -send_packet = 0x400000a4; -recv_packet = 0x400000a8; -GetUartDevice = 0x400000ac; -UartDwnLdProc = 0x400000b0; -Uart_Init = 0x400000b4; -ets_set_user_start = 0x400000b8; -/* Data (.data, .bss, .rodata) */ -ets_rom_layout_p = 0x3ff1fffc; -ets_ops_table_ptr = 0x3fcdfffc; - - -/*************************************** - Group miniz - ***************************************/ - -/* Functions */ -mz_adler32 = 0x400000bc; -mz_crc32 = 0x400000c0; -mz_free = 0x400000c4; -tdefl_compress = 0x400000c8; -tdefl_compress_buffer = 0x400000cc; -tdefl_compress_mem_to_heap = 0x400000d0; -tdefl_compress_mem_to_mem = 0x400000d4; -tdefl_compress_mem_to_output = 0x400000d8; -tdefl_get_adler32 = 0x400000dc; -tdefl_get_prev_return_status = 0x400000e0; -tdefl_init = 0x400000e4; -tdefl_write_image_to_png_file_in_memory = 0x400000e8; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000ec; -tinfl_decompress = 0x400000f0; -tinfl_decompress_mem_to_callback = 0x400000f4; -tinfl_decompress_mem_to_heap = 0x400000f8; -tinfl_decompress_mem_to_mem = 0x400000fc; - - -/*************************************** - Group tjpgd - ***************************************/ - -/* Functions */ -PROVIDE( jd_prepare = 0x40000100 ); -PROVIDE( jd_decomp = 0x40000104 ); - - -/*************************************** - Group esp-dsp - ***************************************/ - -/* Data (.data, .bss, .rodata) */ -dsps_fft2r_w_table_fc32_1024 = 0x3fcdfff8; - - -/*************************************** - Group spiflash_legacy - ***************************************/ - -/* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x40000108 ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000010c ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000110 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000114 ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000118 ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x4000011c ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000120 ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x40000124 ); -PROVIDE( esp_rom_spiflash_write = 0x40000128 ); -PROVIDE( esp_rom_spiflash_read = 0x4000012c ); -PROVIDE( esp_rom_spiflash_config_param = 0x40000130 ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000134 ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000138 ); -PROVIDE( esp_rom_spiflash_unlock = 0x4000013c ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000140 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x40000144 ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000148 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x4000014c ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000150 ); -PROVIDE( esp_rom_spiflash_read_status = 0x40000154 ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000158 ); -PROVIDE( esp_rom_spiflash_write_status = 0x4000015c ); -PROVIDE( spi_flash_attach = 0x40000160 ); -PROVIDE( spi_flash_get_chip_size = 0x40000164 ); -PROVIDE( spi_flash_guard_set = 0x40000168 ); -PROVIDE( spi_flash_guard_get = 0x4000016c ); -PROVIDE( spi_flash_write_config_set = 0x40000170 ); -PROVIDE( spi_flash_write_config_get = 0x40000174 ); -PROVIDE( spi_flash_safe_write_address_func_set = 0x40000178 ); -PROVIDE( spi_flash_unlock = 0x4000017c ); -PROVIDE( spi_flash_erase_range = 0x40000180 ); -PROVIDE( spi_flash_erase_sector = 0x40000184 ); -PROVIDE( spi_flash_write = 0x40000188 ); -PROVIDE( spi_flash_read = 0x4000018c ); -PROVIDE( spi_flash_write_encrypted = 0x40000190 ); -PROVIDE( spi_flash_read_encrypted = 0x40000194 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x40000198 ); -PROVIDE( spi_flash_mmap_page_num_init = 0x4000019c ); -PROVIDE( spi_flash_mmap = 0x400001a0 ); -PROVIDE( spi_flash_mmap_pages = 0x400001a4 ); -PROVIDE( spi_flash_munmap = 0x400001a8 ); -PROVIDE( spi_flash_mmap_dump = 0x400001ac ); -PROVIDE( spi_flash_check_and_flush_cache = 0x400001b0 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b4 ); -PROVIDE( spi_flash_cache2phys = 0x400001b8 ); -PROVIDE( spi_flash_phys2cache = 0x400001bc ); -PROVIDE( spi_flash_disable_cache = 0x400001c0 ); -PROVIDE( spi_flash_restore_cache = 0x400001c4 ); -PROVIDE( spi_flash_cache_enabled = 0x400001c8 ); -PROVIDE( spi_flash_enable_cache = 0x400001cc ); -PROVIDE( spi_cache_mode_switch = 0x400001d0 ); -PROVIDE( spi_common_set_dummy_output = 0x400001d4 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001d8 ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001dc ); -PROVIDE( SPIEraseArea = 0x400001e0 ); -PROVIDE( SPILock = 0x400001e4 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001e8 ); -PROVIDE( SPI_Common_Command = 0x400001ec ); -PROVIDE( SPI_WakeUp = 0x400001f0 ); -PROVIDE( SPI_block_erase = 0x400001f4 ); -PROVIDE( SPI_chip_erase = 0x400001f8 ); -PROVIDE( SPI_init = 0x400001fc ); -PROVIDE( SPI_page_program = 0x40000200 ); -PROVIDE( SPI_read_data = 0x40000204 ); -PROVIDE( SPI_sector_erase = 0x40000208 ); -PROVIDE( SPI_write_enable = 0x4000020c ); -PROVIDE( SelectSpiFunction = 0x40000210 ); -PROVIDE( SetSpiDrvs = 0x40000214 ); -PROVIDE( Wait_SPI_Idle = 0x40000218 ); -PROVIDE( spi_dummy_len_fix = 0x4000021c ); -PROVIDE( Disable_QMode = 0x40000220 ); -PROVIDE( Enable_QMode = 0x40000224 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec ); -PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); - - -/*************************************** - Group hal_soc - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 ); -PROVIDE( spi_flash_hal_device_config = 0x4000022c ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 ); -PROVIDE( spi_flash_hal_common_command = 0x40000234 ); -PROVIDE( spi_flash_hal_read = 0x40000238 ); -PROVIDE( spi_flash_hal_erase_chip = 0x4000023c ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000240 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000244 ); -PROVIDE( spi_flash_hal_program_page = 0x40000248 ); -PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c ); -PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); - - -/*************************************** - Group spi_flash_chips - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000254 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000258 ); -PROVIDE( spi_flash_chip_generic_write = 0x4000025c ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000260 ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000264 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000268 ); -PROVIDE( spi_flash_chip_generic_reset = 0x4000026c ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000270 ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000274 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x40000278 ); -PROVIDE( spi_flash_chip_generic_page_program = 0x4000027c ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000280 ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000284 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x40000288 ); -PROVIDE( spi_flash_chip_generic_yield = 0x4000028c ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x40000290 ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000294 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000298 ); -PROVIDE( spi_flash_chip_generic_read = 0x4000029c ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400002a0 ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400002a4 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400002a8 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400002ac ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400002b0 ); -PROVIDE( spi_flash_common_set_io_mode = 0x400002b4 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400002b8 ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400002bc ); -PROVIDE( spi_flash_chip_gd_probe = 0x400002c0 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400002c4 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 ); - - -/*************************************** - Group memspi_host - ***************************************/ - -/* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x400002c8 ); -PROVIDE( memspi_host_read_status_hs = 0x400002cc ); -PROVIDE( memspi_host_flush_cache = 0x400002d0 ); -PROVIDE( memspi_host_erase_chip = 0x400002d4 ); -PROVIDE( memspi_host_erase_sector = 0x400002d8 ); -PROVIDE( memspi_host_erase_block = 0x400002dc ); -PROVIDE( memspi_host_program_page = 0x400002e0 ); -PROVIDE( memspi_host_read = 0x400002e4 ); -PROVIDE( memspi_host_set_write_protect = 0x400002e8 ); -PROVIDE( memspi_host_set_max_read_len = 0x400002ec ); -PROVIDE( memspi_host_read_data_slicer = 0x400002f0 ); -PROVIDE( memspi_host_write_data_slicer = 0x400002f4 ); - - -/*************************************** - Group esp_flash - ***************************************/ - -/* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x400002f8 ); -PROVIDE( esp_flash_read_id = 0x400002fc ); -PROVIDE( esp_flash_get_size = 0x40000300 ); -PROVIDE( esp_flash_erase_chip = 0x40000304 ); -PROVIDE( rom_esp_flash_erase_region = 0x40000308 ); -PROVIDE( esp_flash_get_chip_write_protect = 0x4000030c ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000310 ); -PROVIDE( esp_flash_get_protectable_regions = 0x40000314 ); -PROVIDE( esp_flash_get_protected_region = 0x40000318 ); -PROVIDE( esp_flash_set_protected_region = 0x4000031c ); -PROVIDE( esp_flash_read = 0x40000320 ); -PROVIDE( esp_flash_write = 0x40000324 ); -PROVIDE( esp_flash_write_encrypted = 0x40000328 ); -PROVIDE( esp_flash_read_encrypted = 0x4000032c ); -PROVIDE( esp_flash_get_io_mode = 0x40000330 ); -PROVIDE( esp_flash_set_io_mode = 0x40000334 ); -PROVIDE( spi_flash_boot_attach = 0x40000338 ); -PROVIDE( spi_flash_dump_counters = 0x4000033c ); -PROVIDE( spi_flash_get_counters = 0x40000340 ); -PROVIDE( spi_flash_op_counters_config = 0x40000344 ); -PROVIDE( spi_flash_reset_counters = 0x40000348 ); -PROVIDE( esp_flash_read_chip_id = 0x4000034c ); -PROVIDE( detect_spi_flash_chip = 0x40000350 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x40000354 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fcdffe4 ); -PROVIDE( esp_flash_api_funcs = 0x3fcdffe0 ); - - -/*************************************** - Group cache - ***************************************/ - -/* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x400004b8 ); -PROVIDE( Cache_Get_Mode = 0x400004bc ); -PROVIDE( Cache_Address_Through_IBus = 0x400004c0 ); -PROVIDE( Cache_Address_Through_DBus = 0x400004c4 ); -PROVIDE( Cache_Set_Default_Mode = 0x400004c8 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400004cc ); -PROVIDE( ROM_Boot_Cache_Init = 0x400004d0 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x400004d4 ); -PROVIDE( Cache_Op_Addr = 0x400004d8 ); -PROVIDE( Cache_Invalidate_Addr = 0x400004dc ); -PROVIDE( Cache_Invalidate_ICache_All = 0x400004e0 ); -PROVIDE( Cache_Mask_All = 0x400004e4 ); -PROVIDE( Cache_UnMask_Dram0 = 0x400004e8 ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x400004ec ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x400004f0 ); -PROVIDE( Cache_Start_ICache_Preload = 0x400004f4 ); -PROVIDE( Cache_ICache_Preload_Done = 0x400004f8 ); -PROVIDE( Cache_End_ICache_Preload = 0x400004fc ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40000500 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x40000504 ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40000508 ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x4000050c ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40000510 ); -PROVIDE( Cache_Lock_ICache_Items = 0x40000514 ); -PROVIDE( Cache_Unlock_ICache_Items = 0x40000518 ); -PROVIDE( Cache_Lock_Addr = 0x4000051c ); -PROVIDE( Cache_Unlock_Addr = 0x40000520 ); -PROVIDE( Cache_Disable_ICache = 0x40000524 ); -PROVIDE( Cache_Enable_ICache = 0x40000528 ); -PROVIDE( Cache_Suspend_ICache = 0x4000052c ); -PROVIDE( Cache_Resume_ICache = 0x40000530 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x40000534 ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40000538 ); -PROVIDE( Cache_Pms_Lock = 0x4000053c ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000540 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x40000544 ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000548 ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x4000054c ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000550 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x40000554 ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x40000558 ); -PROVIDE( Cache_Owner_Init = 0x4000055c ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000560 ); -PROVIDE( Cache_MMU_Init = 0x40000564 ); -PROVIDE( Cache_Ibus_MMU_Set = 0x40000568 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x4000056c ); -PROVIDE( Cache_Count_Flash_Pages = 0x40000570 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x40000574 ); -PROVIDE( Cache_Get_Virtual_Addr = 0x40000578 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x4000057c ); -PROVIDE( Cache_Get_Memory_Addr = 0x40000580 ); -PROVIDE( Cache_Get_Memory_value = 0x40000584 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fcdffd4 ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffd0 ); - - -/*************************************** - Group clock - ***************************************/ - -/* Functions */ -ets_get_apb_freq = 0x40000588; -ets_get_cpu_frequency = 0x4000058c; -ets_update_cpu_frequency = 0x40000590; -ets_get_printf_channel = 0x40000594; -ets_get_xtal_div = 0x40000598; -ets_set_xtal_div = 0x4000059c; -ets_get_xtal_freq = 0x400005a0; - - -/*************************************** - Group gpio - ***************************************/ - -/* Functions */ -gpio_input_get = 0x400005a4; -gpio_matrix_in = 0x400005a8; -gpio_matrix_out = 0x400005ac; -gpio_output_disable = 0x400005b0; -gpio_output_enable = 0x400005b4; -gpio_output_set = 0x400005b8; -gpio_pad_hold = 0x400005bc; -gpio_pad_input_disable = 0x400005c0; -gpio_pad_input_enable = 0x400005c4; -gpio_pad_pulldown = 0x400005c8; -gpio_pad_pullup = 0x400005cc; -gpio_pad_select_gpio = 0x400005d0; -gpio_pad_set_drv = 0x400005d4; -gpio_pad_unhold = 0x400005d8; -gpio_pin_wakeup_disable = 0x400005dc; -gpio_pin_wakeup_enable = 0x400005e0; -gpio_bypass_matrix_in = 0x400005e4; - - -/*************************************** - Group interrupts - ***************************************/ - -/* Functions */ -esprv_intc_int_set_priority = 0x400005e8; -esprv_intc_int_set_threshold = 0x400005ec; -esprv_intc_int_enable = 0x400005f0; -esprv_intc_int_disable = 0x400005f4; -esprv_intc_int_set_type = 0x400005f8; -intr_matrix_set = 0x400005fc; -ets_intr_lock = 0x40000600; -ets_intr_unlock = 0x40000604; -PROVIDE( intr_handler_set = 0x40000608 ); -ets_isr_attach = 0x4000060c; -ets_isr_mask = 0x40000610; -ets_isr_unmask = 0x40000614; - - -/*************************************** - Group crypto - ***************************************/ - -/* Functions */ -md5_vector = 0x40000618; -MD5Init = 0x4000061c; -MD5Update = 0x40000620; -MD5Final = 0x40000624; -hmac_md5_vector = 0x40000628; -hmac_md5 = 0x4000062c; -crc32_le = 0x40000630; -crc32_be = 0x40000634; -crc16_le = 0x40000638; -crc16_be = 0x4000063c; -crc8_le = 0x40000640; -crc8_be = 0x40000644; -esp_crc8 = 0x40000648; -ets_sha_enable = 0x4000064c; -ets_sha_disable = 0x40000650; -ets_sha_get_state = 0x40000654; -ets_sha_init = 0x40000658; -ets_sha_process = 0x4000065c; -ets_sha_starts = 0x40000660; -ets_sha_update = 0x40000664; -ets_sha_finish = 0x40000668; -ets_sha_clone = 0x4000066c; -ets_hmac_enable = 0x40000670; -ets_hmac_disable = 0x40000674; -ets_hmac_calculate_message = 0x40000678; -ets_hmac_calculate_downstream = 0x4000067c; -ets_hmac_invalidate_downstream = 0x40000680; -ets_jtag_enable_temporarily = 0x40000684; -ets_aes_enable = 0x40000688; -ets_aes_disable = 0x4000068c; -ets_aes_setkey = 0x40000690; -ets_aes_block = 0x40000694; -ets_bigint_enable = 0x40000698; -ets_bigint_disable = 0x4000069c; -ets_bigint_multiply = 0x400006a0; -ets_bigint_modmult = 0x400006a4; -ets_bigint_modexp = 0x400006a8; -ets_bigint_wait_finish = 0x400006ac; -ets_bigint_getz = 0x400006b0; -ets_ds_enable = 0x400006b4; -ets_ds_disable = 0x400006b8; -ets_ds_start_sign = 0x400006bc; -ets_ds_is_busy = 0x400006c0; -ets_ds_finish_sign = 0x400006c4; -ets_ds_encrypt_params = 0x400006c8; -ets_aes_setkey_dec = 0x400006cc; -ets_aes_setkey_enc = 0x400006d0; -ets_mgf1_sha256 = 0x400006d4; - - -/*************************************** - Group efuse - ***************************************/ - -/* Functions */ -ets_efuse_read = 0x400006d8; -ets_efuse_program = 0x400006dc; -ets_efuse_clear_program_registers = 0x400006e0; -ets_efuse_write_key = 0x400006e4; -ets_efuse_get_read_register_address = 0x400006e8; -ets_efuse_get_key_purpose = 0x400006ec; -ets_efuse_key_block_unused = 0x400006f0; -ets_efuse_find_unused_key_block = 0x400006f4; -ets_efuse_rs_calculate = 0x400006f8; -ets_efuse_count_unused_key_blocks = 0x400006fc; -ets_efuse_secure_boot_enabled = 0x40000700; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000704; -ets_efuse_cache_encryption_enabled = 0x40000708; -ets_efuse_download_modes_disabled = 0x4000070c; -ets_efuse_find_purpose = 0x40000710; -ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40000714; -ets_efuse_force_send_resume = 0x40000718; -ets_efuse_get_flash_delay_us = 0x4000071c; -ets_efuse_get_mac = 0x40000720; -ets_efuse_get_spiconfig = 0x40000724; -ets_efuse_usb_print_is_disabled = 0x40000728; -/*ets_efuse_get_uart_print_channel = 0x4000072c;*/ -ets_efuse_usb_serial_jtag_print_is_disabled = 0x4000072c; -ets_efuse_get_uart_print_control = 0x40000730; -ets_efuse_get_wp_pad = 0x40000734; -ets_efuse_direct_boot_mode_disabled = 0x40000738; -ets_efuse_security_download_modes_enabled = 0x4000073c; -ets_efuse_set_timing = 0x40000740; -ets_efuse_jtag_disabled = 0x40000744; -ets_efuse_usb_download_mode_disabled = 0x40000748; -ets_efuse_usb_module_disabled = 0x4000074c; -ets_efuse_usb_device_disabled = 0x40000750; -ets_efuse_secure_boot_fast_wake_enabled = 0x40000754; - - -/*************************************** - Group secureboot - ***************************************/ - -/* Functions */ -ets_emsa_pss_verify = 0x40000758; -ets_rsa_pss_verify = 0x4000075c; -ets_secure_boot_verify_bootloader_with_keys = 0x40000760; -ets_secure_boot_verify_signature = 0x40000764; -ets_secure_boot_read_key_digests = 0x40000768; -ets_secure_boot_revoke_public_key_digest = 0x4000076c; - - -/*************************************** - Group usb_uart - ***************************************/ - -/* Functions */ -PROVIDE( usb_uart_device_rx_one_char = 0x400008d8 ); -PROVIDE( usb_uart_device_rx_one_char_block = 0x400008dc ); -PROVIDE( usb_uart_device_tx_flush = 0x400008e0 ); -PROVIDE( usb_uart_device_tx_one_char = 0x400008e4 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( g_uart_print = 0x3fcdffcd ); -PROVIDE( g_usb_print = 0x3fcdffcc ); - - -/*************************************** - Group rom_phy - ***************************************/ - -/* Functions */ -phy_get_romfuncs = 0x400008e8; -rom_abs_temp = 0x400008ec; -rom_bb_bss_cbw40_dig = 0x400008f0; -rom_bb_wdg_test_en = 0x400008f4; -rom_bb_wdt_get_status = 0x400008f8; -rom_bb_wdt_int_enable = 0x400008fc; -rom_bb_wdt_rst_enable = 0x40000900; -rom_bb_wdt_timeout_clear = 0x40000904; -rom_cbw2040_cfg = 0x40000908; -rom_check_noise_floor = 0x4000090c; -rom_chip_i2c_readReg = 0x40000910; -rom_chip_i2c_writeReg = 0x40000914; -rom_correct_rf_ana_gain = 0x40000918; -rom_dc_iq_est = 0x4000091c; -rom_disable_agc = 0x40000920; -rom_en_pwdet = 0x40000924; -rom_enable_agc = 0x40000928; -rom_get_bbgain_db = 0x4000092c; -rom_get_data_sat = 0x40000930; -rom_get_i2c_read_mask = 0x40000934; -rom_get_pwctrl_correct = 0x40000938; -rom_get_rf_gain_qdb = 0x4000093c; -rom_i2c_readReg = 0x40000940; -rom_i2c_readReg_Mask = 0x40000944; -rom_i2c_writeReg = 0x40000948; -rom_i2c_writeReg_Mask = 0x4000094c; -rom_index_to_txbbgain = 0x40000950; -rom_iq_est_disable = 0x40000954; -rom_iq_est_enable = 0x40000958; -rom_linear_to_db = 0x4000095c; -rom_loopback_mode_en = 0x40000960; -rom_mhz2ieee = 0x40000964; -rom_noise_floor_auto_set = 0x40000968; -rom_pbus_debugmode = 0x4000096c; -rom_pbus_force_mode = 0x40000970; -rom_pbus_force_test = 0x40000974; -rom_pbus_rd = 0x40000978; -rom_pbus_rd_addr = 0x4000097c; -rom_pbus_rd_shift = 0x40000980; -rom_pbus_set_dco = 0x40000984; -rom_pbus_set_rxgain = 0x40000988; -rom_pbus_workmode = 0x4000098c; -rom_pbus_xpd_rx_off = 0x40000990; -rom_pbus_xpd_rx_on = 0x40000994; -rom_pbus_xpd_tx_off = 0x40000998; -rom_pbus_xpd_tx_on = 0x4000099c; -rom_phy_byte_to_word = 0x400009a0; -rom_phy_disable_cca = 0x400009a4; -rom_phy_enable_cca = 0x400009a8; -rom_phy_get_noisefloor = 0x400009ac; -rom_phy_get_rx_freq = 0x400009b0; -rom_phy_set_bbfreq_init = 0x400009b4; -rom_pow_usr = 0x400009b8; -rom_pwdet_sar2_init = 0x400009bc; -rom_read_hw_noisefloor = 0x400009c0; -rom_read_sar_dout = 0x400009c4; -rom_set_cal_rxdc = 0x400009c8; -rom_set_chan_cal_interp = 0x400009cc; -rom_set_loopback_gain = 0x400009d0; -rom_set_noise_floor = 0x400009d4; -rom_set_rxclk_en = 0x400009d8; -rom_set_tx_dig_gain = 0x400009dc; -rom_set_txcap_reg = 0x400009e0; -rom_set_txclk_en = 0x400009e4; -rom_spur_cal = 0x400009e8; -rom_spur_reg_write_one_tone = 0x400009ec; -rom_target_power_add_backoff = 0x400009f0; -rom_tx_pwctrl_bg_init = 0x400009f4; -rom_txbbgain_to_index = 0x400009f8; -rom_wifi_11g_rate_chg = 0x400009fc; -rom_write_gain_mem = 0x40000a00; -chip726_phyrom_version = 0x40000a04; -rom_disable_wifi_agc = 0x40000a08; -rom_enable_wifi_agc = 0x40000a0c; -rom_set_tx_gain_table = 0x40000a10; -rom_bt_index_to_bb = 0x40000a14; -rom_bt_bb_to_index = 0x40000a18; -rom_wr_bt_tx_atten = 0x40000a1c; -rom_wr_bt_tx_gain_mem = 0x40000a20; -rom_spur_coef_cfg = 0x40000a24; -rom_bb_bss_cbw40 = 0x40000a28; -rom_set_cca = 0x40000a2c; -rom_tx_paon_set = 0x40000a30; -rom_i2cmst_reg_init = 0x40000a34; -rom_iq_corr_enable = 0x40000a38; -rom_fe_reg_init = 0x40000a3c; -rom_agc_reg_init = 0x40000a40; -rom_bb_reg_init = 0x40000a44; -rom_mac_enable_bb = 0x40000a48; -rom_bb_wdg_cfg = 0x40000a4c; -rom_force_txon = 0x40000a50; -rom_fe_txrx_reset = 0x40000a54; -rom_set_rx_comp = 0x40000a58; -rom_set_pbus_reg = 0x40000a5c; -rom_write_chan_freq = 0x40000a60; -rom_phy_xpd_rf = 0x40000a64; -rom_set_xpd_sar = 0x40000a68; -rom_write_dac_gain2 = 0x40000a6c; -rom_rtc_sar2_init = 0x40000a70; -rom_get_target_power_offset = 0x40000a74; -rom_write_txrate_power_offset = 0x40000a78; -rom_get_rate_fcc_index = 0x40000a7c; -rom_get_rate_target_power = 0x40000a80; -rom_write_wifi_dig_gain = 0x40000a84; -rom_bt_correct_rf_ana_gain = 0x40000a88; -rom_pkdet_vol_start = 0x40000a8c; -rom_read_sar2_code = 0x40000a90; -rom_get_sar2_vol = 0x40000a94; -rom_get_pll_vol = 0x40000a98; -rom_get_phy_target_power = 0x40000a9c; -rom_temp_to_power = 0x40000aa0; -rom_phy_track_pll_cap = 0x40000aa4; -rom_phy_pwdet_always_en = 0x40000aa8; -rom_phy_pwdet_onetime_en = 0x40000aac; -rom_get_i2c_mst0_mask = 0x40000ab0; -rom_get_i2c_hostid = 0x40000ab4; -rom_enter_critical_phy = 0x40000ab8; -rom_exit_critical_phy = 0x40000abc; -rom_chip_i2c_readReg_org = 0x40000ac0; -rom_i2c_paral_set_mst0 = 0x40000ac4; -rom_i2c_paral_set_read = 0x40000ac8; -rom_i2c_paral_read = 0x40000acc; -rom_i2c_paral_write = 0x40000ad0; -rom_i2c_paral_write_num = 0x40000ad4; -rom_i2c_paral_write_mask = 0x40000ad8; -rom_bb_bss_cbw40_ana = 0x40000adc; -rom_chan_to_freq = 0x40000ae0; -rom_open_i2c_xpd = 0x40000ae4; -rom_dac_rate_set = 0x40000ae8; -rom_tsens_read_init = 0x40000aec; -rom_tsens_code_read = 0x40000af0; -rom_tsens_index_to_dac = 0x40000af4; -rom_tsens_index_to_offset = 0x40000af8; -rom_tsens_dac_cal = 0x40000afc; -rom_code_to_temp = 0x40000b00; -rom_write_pll_cap_mem = 0x40000b04; -rom_pll_correct_dcap = 0x40000b08; -rom_phy_en_hw_set_freq = 0x40000b0c; -rom_phy_dis_hw_set_freq = 0x40000b10; -rom_pll_vol_cal = 0x40000b14; -rom_wrtie_pll_cap = 0x40000b18; -rom_set_tx_gain_mem = 0x40000b1c; -rom_bt_tx_dig_gain = 0x40000b20; -rom_bt_get_tx_gain = 0x40000b24; -rom_get_chan_target_power = 0x40000b28; -rom_get_tx_gain_value = 0x40000b2c; -rom_wifi_tx_dig_gain = 0x40000b30; -rom_wifi_get_tx_gain = 0x40000b34; -rom_fe_i2c_reg_renew = 0x40000b38; -rom_wifi_agc_sat_gain = 0x40000b3c; -rom_i2c_master_reset = 0x40000b40; -rom_bt_filter_reg = 0x40000b44; -rom_phy_bbpll_cal = 0x40000b48; -rom_i2c_sar2_init_code = 0x40000b4c; -rom_phy_param_addr = 0x40000b50; -rom_phy_reg_init = 0x40000b54; -rom_set_chan_reg = 0x40000b58; -rom_phy_wakeup_init = 0x40000b5c; -rom_phy_i2c_init1 = 0x40000b60; -rom_tsens_temp_read = 0x40000b64; -rom_bt_track_pll_cap = 0x40000b68; -rom_wifi_track_pll_cap = 0x40000b6c; -rom_wifi_set_tx_gain = 0x40000b70; -rom_txpwr_cal_track = 0x40000b74; -rom_tx_pwctrl_background = 0x40000b78; -rom_bt_set_tx_gain = 0x40000b7c; -rom_noise_check_loop = 0x40000b80; -rom_phy_close_rf = 0x40000b84; -rom_phy_xpd_tsens = 0x40000b88; -rom_phy_freq_mem_backup = 0x40000b8c; -rom_phy_ant_init = 0x40000b90; -rom_bt_track_tx_power = 0x40000b94; -rom_wifi_track_tx_power = 0x40000b98; -rom_phy_dig_reg_backup = 0x40000b9c; -chip726_phyrom_version_num = 0x40000ba0; -/* Data (.data, .bss, .rodata) */ -phy_param_rom = 0x3fcdffc8; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld deleted file mode 100644 index 49c7131938..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.libgcc.ld +++ /dev/null @@ -1,111 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group libgcc - ***************************************/ - -/* Functions */ -__absvdi2 = 0x40000770; -__absvsi2 = 0x40000774; -__adddf3 = 0x40000778; -__addsf3 = 0x4000077c; -__addvdi3 = 0x40000780; -__addvsi3 = 0x40000784; -__ashldi3 = 0x40000788; -__ashrdi3 = 0x4000078c; -__bswapdi2 = 0x40000790; -__bswapsi2 = 0x40000794; -__clear_cache = 0x40000798; -__clrsbdi2 = 0x4000079c; -__clrsbsi2 = 0x400007a0; -__clzdi2 = 0x400007a4; -__clzsi2 = 0x400007a8; -__cmpdi2 = 0x400007ac; -__ctzdi2 = 0x400007b0; -__ctzsi2 = 0x400007b4; -__divdc3 = 0x400007b8; -__divdf3 = 0x400007bc; -__divdi3 = 0x400007c0; -__divsc3 = 0x400007c4; -__divsf3 = 0x400007c8; -__divsi3 = 0x400007cc; -__eqdf2 = 0x400007d0; -__eqsf2 = 0x400007d4; -__extendsfdf2 = 0x400007d8; -__ffsdi2 = 0x400007dc; -__ffssi2 = 0x400007e0; -__fixdfdi = 0x400007e4; -__fixdfsi = 0x400007e8; -__fixsfdi = 0x400007ec; -__fixsfsi = 0x400007f0; -__fixunsdfsi = 0x400007f4; -__fixunssfdi = 0x400007f8; -__fixunssfsi = 0x400007fc; -__floatdidf = 0x40000800; -__floatdisf = 0x40000804; -__floatsidf = 0x40000808; -__floatsisf = 0x4000080c; -__floatundidf = 0x40000810; -__floatundisf = 0x40000814; -__floatunsidf = 0x40000818; -__floatunsisf = 0x4000081c; -__gcc_bcmp = 0x40000820; -__gedf2 = 0x40000824; -__gesf2 = 0x40000828; -__gtdf2 = 0x4000082c; -__gtsf2 = 0x40000830; -__ledf2 = 0x40000834; -__lesf2 = 0x40000838; -__lshrdi3 = 0x4000083c; -__ltdf2 = 0x40000840; -__ltsf2 = 0x40000844; -__moddi3 = 0x40000848; -__modsi3 = 0x4000084c; -__muldc3 = 0x40000850; -__muldf3 = 0x40000854; -__muldi3 = 0x40000858; -__mulsc3 = 0x4000085c; -__mulsf3 = 0x40000860; -__mulsi3 = 0x40000864; -__mulvdi3 = 0x40000868; -__mulvsi3 = 0x4000086c; -__nedf2 = 0x40000870; -__negdf2 = 0x40000874; -__negdi2 = 0x40000878; -__negsf2 = 0x4000087c; -__negvdi2 = 0x40000880; -__negvsi2 = 0x40000884; -__nesf2 = 0x40000888; -__paritysi2 = 0x4000088c; -__popcountdi2 = 0x40000890; -__popcountsi2 = 0x40000894; -__powidf2 = 0x40000898; -__powisf2 = 0x4000089c; -__subdf3 = 0x400008a0; -__subsf3 = 0x400008a4; -__subvdi3 = 0x400008a8; -__subvsi3 = 0x400008ac; -__truncdfsf2 = 0x400008b0; -__ucmpdi2 = 0x400008b4; -__udivdi3 = 0x400008b8; -__udivmoddi4 = 0x400008bc; -__udivsi3 = 0x400008c0; -__udiv_w_sdiv = 0x400008c4; -__umoddi3 = 0x400008c8; -__umodsi3 = 0x400008cc; -__unorddf2 = 0x400008d0; -__unordsf2 = 0x400008d4; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld deleted file mode 100644 index 953c20e02e..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib-nano.ld +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib_nano_format - ***************************************/ - -/* Functions */ -__sprint_r = 0x40000488; -_fiprintf_r = 0x4000048c; -_fprintf_r = 0x40000490; -_printf_common = 0x40000494; -_printf_i = 0x40000498; -_vfiprintf_r = 0x4000049c; -_vfprintf_r = 0x400004a0; -fiprintf = 0x400004a4; -fprintf = 0x400004a8; -printf = 0x400004ac; -vfiprintf = 0x400004b0; -vfprintf = 0x400004b4; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld deleted file mode 100644 index fc9ee8c9de..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.newlib.ld +++ /dev/null @@ -1,96 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z - * - * - * Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib - ***************************************/ - -/* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40000358; -memset = 0x4000035c; -memcpy = 0x40000360; -memmove = 0x40000364; -memcmp = 0x40000368; -strcpy = 0x4000036c; -strncpy = 0x40000370; -strcmp = 0x40000374; -strncmp = 0x40000378; -strlen = 0x4000037c; -strstr = 0x40000380; -bzero = 0x40000384; -sbrk = 0x4000038c; -isalnum = 0x40000390; -isalpha = 0x40000394; -isascii = 0x40000398; -isblank = 0x4000039c; -iscntrl = 0x400003a0; -isdigit = 0x400003a4; -islower = 0x400003a8; -isgraph = 0x400003ac; -isprint = 0x400003b0; -ispunct = 0x400003b4; -isspace = 0x400003b8; -isupper = 0x400003bc; -toupper = 0x400003c0; -tolower = 0x400003c4; -toascii = 0x400003c8; -memccpy = 0x400003cc; -memchr = 0x400003d0; -memrchr = 0x400003d4; -strcasecmp = 0x400003d8; -strcasestr = 0x400003dc; -strcat = 0x400003e0; -strdup = 0x400003e4; -strchr = 0x400003e8; -strcspn = 0x400003ec; -strcoll = 0x400003f0; -strlcat = 0x400003f4; -strlcpy = 0x400003f8; -strlwr = 0x400003fc; -strncasecmp = 0x40000400; -strncat = 0x40000404; -strndup = 0x40000408; -strnlen = 0x4000040c; -strrchr = 0x40000410; -strsep = 0x40000414; -strspn = 0x40000418; -strtok_r = 0x4000041c; -strupr = 0x40000420; -longjmp = 0x40000424; -setjmp = 0x40000428; -abs = 0x4000042c; -div = 0x40000430; -labs = 0x40000434; -ldiv = 0x40000438; -qsort = 0x4000043c; -rand_r = 0x40000440; -rand = 0x40000444; -srand = 0x40000448; -utoa = 0x4000044c; -itoa = 0x40000450; -atoi = 0x40000454; -atol = 0x40000458; -strtol = 0x4000045c; -strtoul = 0x40000460; -PROVIDE( fflush = 0x40000464 ); -PROVIDE( _fflush_r = 0x40000468 ); -PROVIDE( _fwalk = 0x4000046c ); -PROVIDE( _fwalk_reent = 0x40000470 ); -PROVIDE( __swbuf_r = 0x4000047c ); -__swbuf = 0x40000480; -/* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fcdffdc; -_global_impure_ptr = 0x3fcdffd8; diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld deleted file mode 100644 index 46dd7a4b49..0000000000 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.version.ld +++ /dev/null @@ -1,14 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM version variables for esp32b1z - * - * These addresses should be compatible with any ROM version for this chip. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ -_rom_chip_id = 0x40000010; -_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld deleted file mode 100644 index 7c821b46b1..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld +++ /dev/null @@ -1,61 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** ROM APIs - */ -PROVIDE ( esp_rom_crc32_le = crc32_le ); -PROVIDE ( esp_rom_crc16_le = crc16_le ); -PROVIDE ( esp_rom_crc8_le = crc8_le ); -PROVIDE ( esp_rom_crc32_be = crc32_be ); -PROVIDE ( esp_rom_crc16_be = crc16_be ); -PROVIDE ( esp_rom_crc8_be = crc8_be ); - -PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); -PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); -PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); -PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); -PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); -PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); - -PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); -PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); -PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); -PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); - -PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); -PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); -PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); -PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); -PROVIDE ( esp_rom_uart_rx_string = UartRxString ); -PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); -PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - -PROVIDE ( esp_rom_md5_init = MD5Init ); -PROVIDE ( esp_rom_md5_update = MD5Update ); -PROVIDE ( esp_rom_md5_final = MD5Final ); - -PROVIDE ( esp_rom_software_reset_system = software_reset ); -PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); - -PROVIDE ( esp_rom_printf = ets_printf ); -PROVIDE ( esp_rom_delay_us = ets_delay_us ); -PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); -PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); -PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); - -PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); -PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable); -PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); - -PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); -PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); -PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); -PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); - -PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg ); -PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask ); -PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg ); -PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask ); diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld deleted file mode 100644 index a6dbff60a7..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.ld +++ /dev/null @@ -1,1707 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group common - ***************************************/ - -/* Functions */ -rtc_get_reset_reason = 0x40000018; -analog_super_wdt_reset_happened = 0x4000001c; -rtc_get_wakeup_cause = 0x40000020; -rtc_select_apb_bridge = 0x40000024; -rtc_unhold_all_pads = 0x40000028; -ets_is_print_boot = 0x4000002c; -ets_printf = 0x40000030; -ets_install_putc1 = 0x40000034; -ets_install_uart_printf = 0x40000038; -ets_install_putc2 = 0x4000003c; -PROVIDE( ets_delay_us = 0x40000040 ); -ets_install_lock = 0x40000044; -ets_backup_dma_copy = 0x40000048; -ets_apb_backup_init_lock_func = 0x4000004c; -UartRxString = 0x40000050; -UartGetCmdLn = 0x40000054; -uart_tx_one_char = 0x40000058; -uart_tx_one_char2 = 0x4000005c; -uart_rx_one_char = 0x40000060; -uart_rx_one_char_block = 0x40000064; -uart_rx_readbuff = 0x40000068; -uartAttach = 0x4000006c; -uart_tx_flush = 0x40000070; -uart_tx_wait_idle = 0x40000074; -uart_div_modify = 0x40000078; -ets_write_char_uart = 0x4000007c; -uart_tx_switch = 0x40000080; -multofup = 0x40000084; -software_reset = 0x40000088; -software_reset_cpu = 0x4000008c; -assist_debug_clock_enable = 0x40000090; -assist_debug_record_enable = 0x40000094; -clear_super_wdt_reset_flag = 0x40000098; -disable_default_watchdog = 0x4000009c; -esp_rom_set_rtc_wake_addr = 0x400000a0; -esp_rom_get_rtc_wake_addr = 0x400000a4; -send_packet = 0x400000a8; -recv_packet = 0x400000ac; -GetUartDevice = 0x400000b0; -UartDwnLdProc = 0x400000b4; -GetSecurityInfoProc = 0x400000b8; -Uart_Init = 0x400000bc; -ets_set_user_start = 0x400000c0; -/* Data (.data, .bss, .rodata) */ -ets_rom_layout_p = 0x3ff1fffc; -ets_ops_table_ptr = 0x3fcdfff8; -g_uart_print = 0x3fcdfffd; -g_usb_print = 0x3fcdfffc; - - -/*************************************** - Group miniz - ***************************************/ - -/* Functions */ -mz_adler32 = 0x400000c4; -mz_free = 0x400000c8; -tdefl_compress = 0x400000cc; -tdefl_compress_buffer = 0x400000d0; -tdefl_compress_mem_to_heap = 0x400000d4; -tdefl_compress_mem_to_mem = 0x400000d8; -tdefl_compress_mem_to_output = 0x400000dc; -tdefl_get_adler32 = 0x400000e0; -tdefl_get_prev_return_status = 0x400000e4; -tdefl_init = 0x400000e8; -tdefl_write_image_to_png_file_in_memory = 0x400000ec; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000f0; -tinfl_decompress = 0x400000f4; -tinfl_decompress_mem_to_callback = 0x400000f8; -tinfl_decompress_mem_to_heap = 0x400000fc; -tinfl_decompress_mem_to_mem = 0x40000100; - - -/*************************************** - Group tjpgd - ***************************************/ - -/* Functions */ -jd_prepare = 0x40000104; -jd_decomp = 0x40000108; - - -/*************************************** - Group spiflash_legacy - ***************************************/ - -/* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000118 ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000011c ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x40000120 ); -PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000124 ); -PROVIDE( _esp_rom_spiflash_erase_block = 0x40000128 ); -PROVIDE( _esp_rom_spiflash_write = 0x4000012c ); -PROVIDE( _esp_rom_spiflash_read = 0x40000130 ); -PROVIDE( _esp_rom_spiflash_unlock = 0x40000134 ); -PROVIDE( _SPIEraseArea = 0x40000138 ); -PROVIDE( _SPI_write_enable = 0x4000013c ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x40000140 ); -PROVIDE( esp_rom_spiflash_erase_block = 0x40000144 ); -PROVIDE( esp_rom_spiflash_write = 0x40000148 ); -PROVIDE( esp_rom_spiflash_read = 0x4000014c ); -PROVIDE( esp_rom_spiflash_unlock = 0x40000150 ); -PROVIDE( SPIEraseArea = 0x40000154 ); -PROVIDE( SPI_write_enable = 0x40000158 ); -PROVIDE( esp_rom_spiflash_config_param = 0x4000015c ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000160 ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000164 ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000168 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x4000016c ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000170 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x40000174 ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000178 ); -PROVIDE( esp_rom_spiflash_read_status = 0x4000017c ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000180 ); -PROVIDE( esp_rom_spiflash_write_status = 0x40000184 ); -PROVIDE( spi_flash_attach = 0x40000188 ); -PROVIDE( spi_flash_get_chip_size = 0x4000018c ); -PROVIDE( spi_flash_guard_set = 0x40000190 ); -PROVIDE( spi_flash_guard_get = 0x40000194 ); -PROVIDE( spi_flash_read_encrypted = 0x40000198 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x4000019c ); -PROVIDE( spi_flash_mmap_page_num_init = 0x400001a0 ); -PROVIDE( spi_flash_mmap = 0x400001a4 ); -PROVIDE( spi_flash_mmap_pages = 0x400001a8 ); -PROVIDE( spi_flash_munmap = 0x400001ac ); -PROVIDE( spi_flash_mmap_dump = 0x400001b0 ); -PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 ); -PROVIDE( spi_flash_cache2phys = 0x400001bc ); -PROVIDE( spi_flash_phys2cache = 0x400001c0 ); -PROVIDE( spi_flash_disable_cache = 0x400001c4 ); -PROVIDE( spi_flash_restore_cache = 0x400001c8 ); -PROVIDE( spi_flash_cache_enabled = 0x400001cc ); -PROVIDE( spi_flash_enable_cache = 0x400001d0 ); -PROVIDE( spi_cache_mode_switch = 0x400001d4 ); -PROVIDE( spi_common_set_dummy_output = 0x400001d8 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x400001dc ); -PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001e0 ); -PROVIDE( esp_enable_cache_flash_wrap = 0x400001e4 ); -PROVIDE( SPILock = 0x400001e8 ); -PROVIDE( SPIMasterReadModeCnfig = 0x400001ec ); -PROVIDE( SPI_Common_Command = 0x400001f0 ); -PROVIDE( SPI_WakeUp = 0x400001f4 ); -PROVIDE( SPI_block_erase = 0x400001f8 ); -PROVIDE( SPI_chip_erase = 0x400001fc ); -PROVIDE( SPI_init = 0x40000200 ); -PROVIDE( SPI_page_program = 0x40000204 ); -PROVIDE( SPI_read_data = 0x40000208 ); -PROVIDE( SPI_sector_erase = 0x4000020c ); -PROVIDE( SelectSpiFunction = 0x40000210 ); -PROVIDE( SetSpiDrvs = 0x40000214 ); -PROVIDE( Wait_SPI_Idle = 0x40000218 ); -PROVIDE( spi_dummy_len_fix = 0x4000021c ); -PROVIDE( Disable_QMode = 0x40000220 ); -PROVIDE( Enable_QMode = 0x40000224 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff0 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcdffec ); -PROVIDE( g_flash_guard_ops = 0x3fcdfff4 ); - - -/*************************************** - Group hal_soc - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000228 ); -PROVIDE( spi_flash_hal_device_config = 0x4000022c ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000230 ); -PROVIDE( spi_flash_hal_common_command = 0x40000234 ); -PROVIDE( spi_flash_hal_read = 0x40000238 ); -PROVIDE( spi_flash_hal_erase_chip = 0x4000023c ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000240 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000244 ); -PROVIDE( spi_flash_hal_program_page = 0x40000248 ); -PROVIDE( spi_flash_hal_set_write_protect = 0x4000024c ); -PROVIDE( spi_flash_hal_host_idle = 0x40000250 ); -PROVIDE( spi_flash_hal_check_status = 0x40000254 ); -PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000258 ); -PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000025c ); -PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000260 ); -PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000264 ); -PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000268 ); -PROVIDE( spi_flash_hal_resume = 0x4000026c ); -PROVIDE( spi_flash_hal_suspend = 0x40000270 ); -PROVIDE( spi_flash_encryption_hal_enable = 0x40000274 ); -PROVIDE( spi_flash_encryption_hal_disable = 0x40000278 ); -PROVIDE( spi_flash_encryption_hal_prepare = 0x4000027c ); -PROVIDE( spi_flash_encryption_hal_done = 0x40000280 ); -PROVIDE( spi_flash_encryption_hal_destroy = 0x40000284 ); -PROVIDE( spi_flash_encryption_hal_check = 0x40000288 ); -PROVIDE( wdt_hal_init = 0x4000028c ); -PROVIDE( wdt_hal_deinit = 0x40000290 ); -PROVIDE( wdt_hal_config_stage = 0x40000294 ); -PROVIDE( wdt_hal_write_protect_disable = 0x40000298 ); -PROVIDE( wdt_hal_write_protect_enable = 0x4000029c ); -PROVIDE( wdt_hal_enable = 0x400002a0 ); -PROVIDE( wdt_hal_disable = 0x400002a4 ); -PROVIDE( wdt_hal_handle_intr = 0x400002a8 ); -PROVIDE( wdt_hal_feed = 0x400002ac ); -PROVIDE( wdt_hal_set_flashboot_en = 0x400002b0 ); -PROVIDE( wdt_hal_is_enabled = 0x400002b4 ); -PROVIDE( systimer_hal_init = 0x400002b8 ); -PROVIDE( systimer_hal_get_counter_value = 0x400002bc ); -PROVIDE( systimer_hal_get_time = 0x400002c0 ); -PROVIDE( systimer_hal_set_alarm_target = 0x400002c4 ); -PROVIDE( systimer_hal_set_alarm_period = 0x400002c8 ); -PROVIDE( systimer_hal_get_alarm_value = 0x400002cc ); -PROVIDE( systimer_hal_enable_alarm_int = 0x400002d0 ); -PROVIDE( systimer_hal_on_apb_freq_update = 0x400002d4 ); -PROVIDE( systimer_hal_counter_value_advance = 0x400002d8 ); -PROVIDE( systimer_hal_enable_counter = 0x400002dc ); -PROVIDE( systimer_hal_select_alarm_mode = 0x400002e0 ); -PROVIDE( systimer_hal_connect_alarm_counter = 0x400002e4 ); -PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002e8 ); - - -/*************************************** - Group heap - ***************************************/ - -/* Functions */ -PROVIDE( tlsf_create = 0x400002ec ); -PROVIDE( tlsf_create_with_pool = 0x400002f0 ); -PROVIDE( tlsf_get_pool = 0x400002f4 ); -PROVIDE( tlsf_add_pool = 0x400002f8 ); -PROVIDE( tlsf_remove_pool = 0x400002fc ); -PROVIDE( tlsf_malloc = 0x40000300 ); -PROVIDE( tlsf_memalign = 0x40000304 ); -PROVIDE( tlsf_memalign_offs = 0x40000308 ); -PROVIDE( tlsf_realloc = 0x4000030c ); -PROVIDE( tlsf_free = 0x40000310 ); -PROVIDE( tlsf_block_size = 0x40000314 ); -PROVIDE( tlsf_size = 0x40000318 ); -PROVIDE( tlsf_align_size = 0x4000031c ); -PROVIDE( tlsf_block_size_min = 0x40000320 ); -PROVIDE( tlsf_block_size_max = 0x40000324 ); -PROVIDE( tlsf_pool_overhead = 0x40000328 ); -PROVIDE( tlsf_alloc_overhead = 0x4000032c ); -PROVIDE( tlsf_walk_pool = 0x40000330 ); -PROVIDE( tlsf_check = 0x40000334 ); -PROVIDE( tlsf_check_pool = 0x40000338 ); -PROVIDE( tlsf_poison_fill_pfunc_set = 0x4000033c ); -PROVIDE( multi_heap_get_block_address_impl = 0x40000340 ); -PROVIDE( multi_heap_get_allocated_size_impl = 0x40000344 ); -PROVIDE( multi_heap_register_impl = 0x40000348 ); -PROVIDE( multi_heap_set_lock = 0x4000034c ); -PROVIDE( multi_heap_mutex_init = 0x40000350 ); -PROVIDE( multi_heap_internal_lock = 0x40000354 ); -PROVIDE( multi_heap_internal_unlock = 0x40000358 ); -PROVIDE( multi_heap_get_first_block = 0x4000035c ); -PROVIDE( multi_heap_get_next_block = 0x40000360 ); -PROVIDE( multi_heap_is_free = 0x40000364 ); -PROVIDE( multi_heap_malloc_impl = 0x40000368 ); -PROVIDE( multi_heap_free_impl = 0x4000036c ); -PROVIDE( multi_heap_realloc_impl = 0x40000370 ); -PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000374 ); -PROVIDE( multi_heap_aligned_alloc_impl = 0x40000378 ); -PROVIDE( multi_heap_check = 0x4000037c ); -PROVIDE( multi_heap_dump = 0x40000380 ); -PROVIDE( multi_heap_free_size_impl = 0x40000384 ); -PROVIDE( multi_heap_minimum_free_size_impl = 0x40000388 ); -PROVIDE( multi_heap_get_info_impl = 0x4000038c ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( heap_tlsf_table_ptr = 0x3fcdffe8 ); - - -/*************************************** - Group spi_flash_chips - ***************************************/ - -/* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000390 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000394 ); -PROVIDE( spi_flash_chip_generic_write = 0x40000398 ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000039c ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x400003a0 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x400003a4 ); -PROVIDE( spi_flash_chip_generic_reset = 0x400003a8 ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x400003ac ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x400003b0 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x400003b4 ); -PROVIDE( spi_flash_chip_generic_page_program = 0x400003b8 ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003bc ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003c0 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x400003c4 ); -PROVIDE( spi_flash_chip_generic_yield = 0x400003c8 ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x400003cc ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003d0 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003d4 ); -PROVIDE( spi_flash_chip_generic_read = 0x400003d8 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003dc ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003e0 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003e4 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003e8 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003ec ); -PROVIDE( spi_flash_common_set_io_mode = 0x400003f0 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003f4 ); -PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003f8 ); -PROVIDE( spi_flash_chip_generic_get_caps = 0x400003fc ); -PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x40000400 ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40000404 ); -PROVIDE( spi_flash_chip_gd_probe = 0x40000408 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x4000040c ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe4 ); -PROVIDE( spi_flash_encryption = 0x3fcdffe0 ); - - -/*************************************** - Group memspi_host - ***************************************/ - -/* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x40000410 ); -PROVIDE( memspi_host_read_status_hs = 0x40000414 ); -PROVIDE( memspi_host_flush_cache = 0x40000418 ); -PROVIDE( memspi_host_erase_chip = 0x4000041c ); -PROVIDE( memspi_host_erase_sector = 0x40000420 ); -PROVIDE( memspi_host_erase_block = 0x40000424 ); -PROVIDE( memspi_host_program_page = 0x40000428 ); -PROVIDE( memspi_host_read = 0x4000042c ); -PROVIDE( memspi_host_set_write_protect = 0x40000430 ); -PROVIDE( memspi_host_set_max_read_len = 0x40000434 ); -PROVIDE( memspi_host_read_data_slicer = 0x40000438 ); -PROVIDE( memspi_host_write_data_slicer = 0x4000043c ); - - -/*************************************** - Group esp_flash - ***************************************/ - -/* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x40000440 ); -PROVIDE( esp_flash_read_id = 0x40000444 ); -PROVIDE( esp_flash_get_size = 0x40000448 ); -PROVIDE( esp_flash_erase_chip = 0x4000044c ); -PROVIDE( esp_flash_erase_region = 0x40000450 ); -PROVIDE( esp_flash_get_chip_write_protect = 0x40000454 ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000458 ); -PROVIDE( esp_flash_get_protectable_regions = 0x4000045c ); -PROVIDE( esp_flash_get_protected_region = 0x40000460 ); -PROVIDE( esp_flash_set_protected_region = 0x40000464 ); -PROVIDE( esp_flash_read = 0x40000468 ); -PROVIDE( esp_flash_write = 0x4000046c ); -PROVIDE( esp_flash_write_encrypted = 0x40000470 ); -PROVIDE( esp_flash_read_encrypted = 0x40000474 ); -PROVIDE( esp_flash_get_io_mode = 0x40000478 ); -PROVIDE( esp_flash_set_io_mode = 0x4000047c ); -PROVIDE( spi_flash_boot_attach = 0x40000480 ); -PROVIDE( esp_flash_read_chip_id = 0x40000484 ); -PROVIDE( detect_spi_flash_chip = 0x40000488 ); -PROVIDE( esp_rom_spiflash_write_disable = 0x4000048c ); -PROVIDE( esp_flash_suspend_cmd_init = 0x40000490 ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fcdffdc ); -PROVIDE( esp_flash_api_funcs = 0x3fcdffd8 ); - - -/*************************************** - Group cache - ***************************************/ - -/* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x400006f0 ); -PROVIDE( Cache_Get_Mode = 0x400006f4 ); -PROVIDE( Cache_Address_Through_IBus = 0x400006f8 ); -PROVIDE( Cache_Address_Through_DBus = 0x400006fc ); -PROVIDE( Cache_Set_Default_Mode = 0x40000700 ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x40000704 ); -PROVIDE( ROM_Boot_Cache_Init = 0x40000708 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x4000070c ); -PROVIDE( Cache_Op_Addr = 0x40000710 ); -PROVIDE( Cache_Invalidate_Addr = 0x40000714 ); -PROVIDE( Cache_Invalidate_ICache_All = 0x40000718 ); -PROVIDE( Cache_Mask_All = 0x4000071c ); -PROVIDE( Cache_UnMask_Dram0 = 0x40000720 ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x40000724 ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x40000728 ); -PROVIDE( Cache_Start_ICache_Preload = 0x4000072c ); -PROVIDE( Cache_ICache_Preload_Done = 0x40000730 ); -PROVIDE( Cache_End_ICache_Preload = 0x40000734 ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40000738 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x4000073c ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40000740 ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x40000744 ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40000748 ); -PROVIDE( Cache_Lock_ICache_Items = 0x4000074c ); -PROVIDE( Cache_Unlock_ICache_Items = 0x40000750 ); -PROVIDE( Cache_Lock_Addr = 0x40000754 ); -PROVIDE( Cache_Unlock_Addr = 0x40000758 ); -PROVIDE( Cache_Disable_ICache = 0x4000075c ); -PROVIDE( Cache_Enable_ICache = 0x40000760 ); -PROVIDE( Cache_Suspend_ICache = 0x40000764 ); -PROVIDE( Cache_Resume_ICache = 0x40000768 ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x4000076c ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40000770 ); -PROVIDE( Cache_Pms_Lock = 0x40000774 ); -PROVIDE( Cache_Ibus_Pms_Set_Addr = 0x40000778 ); -PROVIDE( Cache_Ibus_Pms_Set_Attr = 0x4000077c ); -PROVIDE( Cache_Dbus_Pms_Set_Addr = 0x40000780 ); -PROVIDE( Cache_Dbus_Pms_Set_Attr = 0x40000784 ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000788 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x4000078c ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x40000790 ); -PROVIDE( Cache_Owner_Init = 0x40000794 ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000798 ); -PROVIDE( Cache_MMU_Init = 0x4000079c ); -PROVIDE( Cache_Ibus_MMU_Set = 0x400007a0 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x400007a4 ); -PROVIDE( Cache_Count_Flash_Pages = 0x400007a8 ); -PROVIDE( Cache_Travel_Tag_Memory = 0x400007ac ); -PROVIDE( Cache_Get_Virtual_Addr = 0x400007b0 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x400007b4 ); -PROVIDE( Cache_Get_Memory_Addr = 0x400007b8 ); -PROVIDE( Cache_Get_Memory_value = 0x400007bc ); -/* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fcdffcc ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffc8 ); - - -/*************************************** - Group clock - ***************************************/ - -/* Functions */ -ets_get_apb_freq = 0x400007c0; -ets_get_cpu_frequency = 0x400007c4; -ets_update_cpu_frequency = 0x400007c8; -ets_get_printf_channel = 0x400007cc; -ets_get_xtal_div = 0x400007d0; -ets_set_xtal_div = 0x400007d4; -ets_get_xtal_freq = 0x400007d8; - - -/*************************************** - Group gpio - ***************************************/ - -/* Functions */ -gpio_input_get = 0x400007dc; -gpio_matrix_in = 0x400007e0; -gpio_matrix_out = 0x400007e4; -gpio_output_disable = 0x400007e8; -gpio_output_enable = 0x400007ec; -gpio_output_set = 0x400007f0; -gpio_pad_hold = 0x400007f4; -gpio_pad_input_disable = 0x400007f8; -gpio_pad_input_enable = 0x400007fc; -gpio_pad_pulldown = 0x40000800; -gpio_pad_pullup = 0x40000804; -gpio_pad_select_gpio = 0x40000808; -gpio_pad_set_drv = 0x4000080c; -gpio_pad_unhold = 0x40000810; -gpio_pin_wakeup_disable = 0x40000814; -gpio_pin_wakeup_enable = 0x40000818; -gpio_bypass_matrix_in = 0x4000081c; - - -/*************************************** - Group interrupts - ***************************************/ - -/* Functions */ -esprv_intc_int_set_priority = 0x40000820; -esprv_intc_int_set_threshold = 0x40000824; -esprv_intc_int_enable = 0x40000828; -esprv_intc_int_disable = 0x4000082c; -esprv_intc_int_set_type = 0x40000830; -PROVIDE( intr_handler_set = 0x40000834 ); -intr_matrix_set = 0x40000838; -ets_intr_lock = 0x4000083c; -ets_intr_unlock = 0x40000840; -ets_isr_attach = 0x40000844; -ets_isr_mask = 0x40000848; -ets_isr_unmask = 0x4000084c; - - -/*************************************** - Group crypto - ***************************************/ - -/* Functions */ -md5_vector = 0x40000850; -MD5Init = 0x40000854; -MD5Update = 0x40000858; -MD5Final = 0x4000085c; -crc32_le = 0x40000860; -crc16_le = 0x40000864; -crc8_le = 0x40000868; -crc32_be = 0x4000086c; -crc16_be = 0x40000870; -crc8_be = 0x40000874; -esp_crc8 = 0x40000878; -ets_sha_enable = 0x4000087c; -ets_sha_disable = 0x40000880; -ets_sha_get_state = 0x40000884; -ets_sha_init = 0x40000888; -ets_sha_process = 0x4000088c; -ets_sha_starts = 0x40000890; -ets_sha_update = 0x40000894; -ets_sha_finish = 0x40000898; -ets_sha_clone = 0x4000089c; -ets_hmac_enable = 0x400008a0; -ets_hmac_disable = 0x400008a4; -ets_hmac_calculate_message = 0x400008a8; -ets_hmac_calculate_downstream = 0x400008ac; -ets_hmac_invalidate_downstream = 0x400008b0; -ets_jtag_enable_temporarily = 0x400008b4; -ets_aes_enable = 0x400008b8; -ets_aes_disable = 0x400008bc; -ets_aes_setkey = 0x400008c0; -ets_aes_block = 0x400008c4; -ets_aes_setkey_dec = 0x400008c8; -ets_aes_setkey_enc = 0x400008cc; -ets_bigint_enable = 0x400008d0; -ets_bigint_disable = 0x400008d4; -ets_bigint_multiply = 0x400008d8; -ets_bigint_modmult = 0x400008dc; -ets_bigint_modexp = 0x400008e0; -ets_bigint_wait_finish = 0x400008e4; -ets_bigint_getz = 0x400008e8; -ets_ds_enable = 0x400008ec; -ets_ds_disable = 0x400008f0; -ets_ds_start_sign = 0x400008f4; -ets_ds_is_busy = 0x400008f8; -ets_ds_finish_sign = 0x400008fc; -ets_ds_encrypt_params = 0x40000900; -ets_mgf1_sha256 = 0x40000904; -/* Data (.data, .bss, .rodata) */ -crc32_le_table_ptr = 0x3ff1fff8; -crc16_le_table_ptr = 0x3ff1fff4; -crc8_le_table_ptr = 0x3ff1fff0; -crc32_be_table_ptr = 0x3ff1ffec; -crc16_be_table_ptr = 0x3ff1ffe8; -crc8_be_table_ptr = 0x3ff1ffe4; - - -/*************************************** - Group efuse - ***************************************/ - -/* Functions */ -ets_efuse_read = 0x40000908; -ets_efuse_program = 0x4000090c; -ets_efuse_clear_program_registers = 0x40000910; -ets_efuse_write_key = 0x40000914; -ets_efuse_get_read_register_address = 0x40000918; -ets_efuse_get_key_purpose = 0x4000091c; -ets_efuse_key_block_unused = 0x40000920; -ets_efuse_find_unused_key_block = 0x40000924; -ets_efuse_rs_calculate = 0x40000928; -ets_efuse_count_unused_key_blocks = 0x4000092c; -ets_efuse_secure_boot_enabled = 0x40000930; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000934; -ets_efuse_cache_encryption_enabled = 0x40000938; -ets_efuse_download_modes_disabled = 0x4000093c; -ets_efuse_find_purpose = 0x40000940; -ets_efuse_force_send_resume = 0x40000944; -ets_efuse_get_flash_delay_us = 0x40000948; -ets_efuse_get_mac = 0x4000094c; -ets_efuse_get_uart_print_control = 0x40000950; -ets_efuse_direct_boot_mode_disabled = 0x40000954; -ets_efuse_security_download_modes_enabled = 0x40000958; -ets_efuse_set_timing = 0x4000095c; -ets_efuse_jtag_disabled = 0x40000960; -ets_efuse_get_spiconfig = 0x40000964; -ets_efuse_get_wp_pad = 0x40000968; -ets_efuse_usb_print_is_disabled = 0x4000096c; -ets_efuse_usb_download_mode_disabled = 0x40000970; -ets_efuse_usb_module_disabled = 0x40000974; -ets_efuse_usb_device_disabled = 0x40000978; -ets_efuse_secure_boot_fast_wake_enabled = 0x4000097c; - - -/*************************************** - Group secureboot - ***************************************/ - -/* Functions */ -ets_emsa_pss_verify = 0x40000980; -ets_rsa_pss_verify = 0x40000984; -ets_secure_boot_verify_bootloader_with_keys = 0x40000988; -ets_secure_boot_verify_signature = 0x4000098c; -ets_secure_boot_read_key_digests = 0x40000990; -ets_secure_boot_revoke_public_key_digest = 0x40000994; - - -/*************************************** - Group btdm - ***************************************/ - -/* Functions */ -/* -ble_controller_rom_data_init = 0x40000b08; -ble_osi_coex_funcs_register = 0x40000b0c; -bt_rf_coex_cfg_get_default = 0x40000b10; -bt_rf_coex_dft_pti_get_default = 0x40000b14; -bt_rf_coex_hooks_p_set = 0x40000b18; -r__os_mbuf_copypkthdr = 0x40000b1c; -r__os_msys_find_pool = 0x40000b20; -r_ble_controller_get_rom_compile_version = 0x40000b24; -r_ble_hci_ram_hs_acl_tx = 0x40000b28; -r_ble_hci_ram_hs_cmd_tx = 0x40000b2c; -r_ble_hci_ram_ll_acl_tx = 0x40000b30; -r_ble_hci_ram_ll_evt_tx = 0x40000b34; -r_ble_hci_ram_reset = 0x40000b38; -r_ble_hci_ram_set_acl_free_cb = 0x40000b3c; -r_ble_hci_trans_acl_buf_alloc = 0x40000b40; -r_ble_hci_trans_buf_alloc = 0x40000b44; -r_ble_hci_trans_buf_free = 0x40000b48; -r_ble_hci_trans_cfg_hs = 0x40000b4c; -r_ble_hci_trans_cfg_ll = 0x40000b50; -r_ble_hci_trans_deinit = 0x40000b54; -r_ble_hci_trans_env_init = 0x40000b58; -r_ble_hci_trans_init = 0x40000b5c; -r_ble_hci_uart_acl_tx = 0x40000b60; -r_ble_hci_uart_cmdevt_tx = 0x40000b64; -r_ble_hci_uart_config = 0x40000b68; -r_ble_hci_uart_free_pkt = 0x40000b6c; -r_ble_hci_uart_hs_acl_tx = 0x40000b70; -r_ble_hci_uart_hs_cmd_tx = 0x40000b74; -r_ble_hci_uart_ll_acl_tx = 0x40000b78; -r_ble_hci_uart_ll_evt_tx = 0x40000b7c; -r_ble_hci_uart_rx_acl = 0x40000b80; -r_ble_hci_uart_rx_char = 0x40000b84; -r_ble_hci_uart_rx_cmd = 0x40000b88; -r_ble_hci_uart_rx_evt = 0x40000b8c; -r_ble_hci_uart_rx_evt_cb = 0x40000b90; -r_ble_hci_uart_rx_le_evt = 0x40000b94; -r_ble_hci_uart_rx_pkt_type = 0x40000b98; -r_ble_hci_uart_rx_skip_acl = 0x40000b9c; -r_ble_hci_uart_rx_skip_cmd = 0x40000ba0; -r_ble_hci_uart_rx_skip_evt = 0x40000ba4; -r_ble_hci_uart_rx_sync_loss = 0x40000ba8; -r_ble_hci_uart_set_acl_free_cb = 0x40000bac; -r_ble_hci_uart_sync_lost = 0x40000bb0; -r_ble_hci_uart_trans_reset = 0x40000bb4; -r_ble_hci_uart_tx_char = 0x40000bb8; -r_ble_hci_uart_tx_pkt_type = 0x40000bbc; -r_ble_hw_driver_deinit = 0x40000bc0; -r_ble_hw_driver_env_init = 0x40000bc4; -r_ble_hw_encrypt_block = 0x40000bc8; -r_ble_hw_get_public_addr = 0x40000bcc; -r_ble_hw_get_static_addr = 0x40000bd0; -r_ble_hw_periodiclist_add = 0x40000bd4; -r_ble_hw_periodiclist_clear = 0x40000bd8; -r_ble_hw_periodiclist_rmv = 0x40000bdc; -r_ble_hw_resolv_list_cur_entry = 0x40000be0; -r_ble_hw_resolv_list_match = 0x40000be4; -r_ble_hw_resolv_list_set = 0x40000be8; -r_ble_hw_rng_init = 0x40000bec; -r_ble_hw_rng_start = 0x40000bf0; -r_ble_hw_rng_stop = 0x40000bf4; -r_ble_hw_rx_local_is_rpa = 0x40000bf8; -r_ble_hw_whitelist_add = 0x40000bfc; -r_ble_hw_whitelist_clear = 0x40000c00; -r_ble_hw_whitelist_dev_num = 0x40000c04; -r_ble_hw_whitelist_get_base = 0x40000c08; -r_ble_hw_whitelist_rmv = 0x40000c0c; -r_ble_hw_whitelist_search = 0x40000c10; -r_ble_hw_whitelist_sort = 0x40000c14; -r_ble_ll_acl_data_in = 0x40000c18; -r_ble_ll_addr_is_id = 0x40000c1c; -r_ble_ll_addr_subtype = 0x40000c20; -r_ble_ll_adv_active_chanset_clear = 0x40000c24; -r_ble_ll_adv_active_chanset_is_pri = 0x40000c28; -r_ble_ll_adv_active_chanset_is_sec = 0x40000c2c; -r_ble_ll_adv_active_chanset_set_pri = 0x40000c30; -r_ble_ll_adv_active_chanset_set_sec = 0x40000c34; -r_ble_ll_adv_aux_calculate = 0x40000c38; -r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000c3c; -r_ble_ll_adv_aux_pdu_make = 0x40000c40; -r_ble_ll_adv_aux_scannable_pdu_make = 0x40000c44; -r_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000c48; -r_ble_ll_adv_aux_schedule = 0x40000c4c; -r_ble_ll_adv_aux_schedule_first = 0x40000c50; -r_ble_ll_adv_aux_schedule_next = 0x40000c54; -r_ble_ll_adv_aux_scheduled = 0x40000c58; -r_ble_ll_adv_aux_set_start_time = 0x40000c5c; -r_ble_ll_adv_aux_txed = 0x40000c60; -r_ble_ll_adv_can_chg_whitelist = 0x40000c64; -r_ble_ll_adv_chk_rpa_timeout = 0x40000c68; -r_ble_ll_adv_clear_all = 0x40000c6c; -r_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000c70; -r_ble_ll_adv_coex_dpc_process_pri = 0x40000c74; -r_ble_ll_adv_coex_dpc_process_sec = 0x40000c78; -r_ble_ll_adv_coex_dpc_pti_get = 0x40000c7c; -r_ble_ll_adv_coex_dpc_update = 0x40000c80; -r_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000c84; -r_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000c88; -r_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000c8c; -r_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000c90; -r_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000c94; -r_ble_ll_adv_conn_req_rxd = 0x40000c98; -r_ble_ll_adv_deinit = 0x40000c9c; -r_ble_ll_adv_done = 0x40000ca0; -r_ble_ll_adv_drop_event = 0x40000ca4; -r_ble_ll_adv_enabled = 0x40000ca8; -r_ble_ll_adv_env_init = 0x40000cac; -r_ble_ll_adv_event_done = 0x40000cb0; -r_ble_ll_adv_event_rmvd_from_sched = 0x40000cb4; -r_ble_ll_adv_ext_estimate_data_itvl = 0x40000cb8; -r_ble_ll_adv_ext_set_adv_data = 0x40000cbc; -r_ble_ll_adv_ext_set_enable = 0x40000cc0; -r_ble_ll_adv_ext_set_param = 0x40000cc4; -r_ble_ll_adv_ext_set_scan_rsp = 0x40000cc8; -r_ble_ll_adv_final_chan = 0x40000ccc; -r_ble_ll_adv_first_chan = 0x40000cd0; -r_ble_ll_adv_flags_clear = 0x40000cd4; -r_ble_ll_adv_flags_set = 0x40000cd8; -r_ble_ll_adv_get_local_rpa = 0x40000cdc; -r_ble_ll_adv_get_peer_rpa = 0x40000ce0; -r_ble_ll_adv_get_sec_pdu_len = 0x40000ce4; -r_ble_ll_adv_halt = 0x40000ce8; -r_ble_ll_adv_hci_set_random_addr = 0x40000cec; -r_ble_ll_adv_init = 0x40000cf0; -r_ble_ll_adv_legacy_pdu_make = 0x40000cf4; -r_ble_ll_adv_make_done = 0x40000cf8; -r_ble_ll_adv_pdu_make = 0x40000cfc; -r_ble_ll_adv_periodic_check_data_itvl = 0x40000d00; -r_ble_ll_adv_periodic_done = 0x40000d04; -r_ble_ll_adv_periodic_enable = 0x40000d08; -r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000d0c; -r_ble_ll_adv_periodic_event_done = 0x40000d10; -r_ble_ll_adv_periodic_rmvd_from_sched = 0x40000d14; -r_ble_ll_adv_periodic_schedule_first = 0x40000d18; -r_ble_ll_adv_periodic_schedule_next = 0x40000d1c; -r_ble_ll_adv_periodic_send_sync_ind = 0x40000d20; -r_ble_ll_adv_periodic_set_data = 0x40000d24; -r_ble_ll_adv_periodic_set_info_transfer = 0x40000d28; -r_ble_ll_adv_periodic_set_param = 0x40000d2c; -r_ble_ll_adv_put_aux_ptr = 0x40000d30; -r_ble_ll_adv_put_syncinfo = 0x40000d34; -r_ble_ll_adv_rd_max_adv_data_len = 0x40000d38; -r_ble_ll_adv_rd_sup_adv_sets = 0x40000d3c; -r_ble_ll_adv_read_txpwr = 0x40000d40; -r_ble_ll_adv_remove = 0x40000d44; -r_ble_ll_adv_reschedule_event = 0x40000d48; -r_ble_ll_adv_reschedule_periodic_event = 0x40000d4c; -r_ble_ll_adv_reset = 0x40000d50; -r_ble_ll_adv_rpa_timeout = 0x40000d54; -r_ble_ll_adv_rpa_update = 0x40000d58; -r_ble_ll_adv_rx_isr_end = 0x40000d5c; -r_ble_ll_adv_rx_isr_start = 0x40000d60; -r_ble_ll_adv_rx_pkt_in = 0x40000d64; -r_ble_ll_adv_rx_req = 0x40000d68; -r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000d6c; -r_ble_ll_adv_scan_rsp_pdu_make = 0x40000d70; -r_ble_ll_adv_scheduled = 0x40000d74; -r_ble_ll_adv_sec_done = 0x40000d78; -r_ble_ll_adv_sec_event_done = 0x40000d7c; -r_ble_ll_adv_secondary_tx_start_cb = 0x40000d80; -r_ble_ll_adv_send_conn_comp_ev = 0x40000d84; -r_ble_ll_adv_set_adv_data = 0x40000d88; -r_ble_ll_adv_set_adv_params = 0x40000d8c; -r_ble_ll_adv_set_enable = 0x40000d90; -r_ble_ll_adv_set_random_addr = 0x40000d94; -r_ble_ll_adv_set_scan_rsp_data = 0x40000d98; -r_ble_ll_adv_set_sched = 0x40000d9c; -r_ble_ll_adv_sm_deinit = 0x40000da0; -r_ble_ll_adv_sm_event_init = 0x40000da4; -r_ble_ll_adv_sm_event_restore = 0x40000da8; -r_ble_ll_adv_sm_event_store = 0x40000dac; -r_ble_ll_adv_sm_find_configured = 0x40000db0; -r_ble_ll_adv_sm_get = 0x40000db4; -r_ble_ll_adv_sm_init = 0x40000db8; -r_ble_ll_adv_sm_reset = 0x40000dbc; -r_ble_ll_adv_sm_start = 0x40000dc0; -r_ble_ll_adv_sm_start_periodic = 0x40000dc4; -r_ble_ll_adv_sm_stop = 0x40000dc8; -r_ble_ll_adv_sm_stop_limit_reached = 0x40000dcc; -r_ble_ll_adv_sm_stop_periodic = 0x40000dd0; -r_ble_ll_adv_sm_stop_timeout = 0x40000dd4; -r_ble_ll_adv_sync_calculate = 0x40000dd8; -r_ble_ll_adv_sync_get_pdu_len = 0x40000ddc; -r_ble_ll_adv_sync_next_scheduled = 0x40000de0; -r_ble_ll_adv_sync_pdu_make = 0x40000de4; -r_ble_ll_adv_sync_schedule = 0x40000de8; -r_ble_ll_adv_sync_tx_done = 0x40000dec; -r_ble_ll_adv_sync_tx_end = 0x40000df0; -r_ble_ll_adv_sync_tx_start_cb = 0x40000df4; -r_ble_ll_adv_tx_done = 0x40000df8; -r_ble_ll_adv_tx_start_cb = 0x40000dfc; -r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000e00; -r_ble_ll_adv_update_data_mbuf = 0x40000e04; -r_ble_ll_adv_update_did = 0x40000e08; -r_ble_ll_adv_update_periodic_data = 0x40000e0c; -r_ble_ll_adv_update_rsp_offset = 0x40000e10; -r_ble_ll_adv_wfr_timer_exp = 0x40000e14; -r_ble_ll_arr_pool_init = 0x40000e18; -r_ble_ll_auth_pyld_tmo_event_send = 0x40000e1c; -r_ble_ll_aux_scan_cb = 0x40000e20; -r_ble_ll_aux_scan_drop = 0x40000e24; -r_ble_ll_aux_scan_drop_event_cb = 0x40000e28; -r_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000e2c; -r_ble_ll_calc_session_key = 0x40000e30; -r_ble_ll_calc_ticks_per_slot = 0x40000e34; -r_ble_ll_calc_us_convert_tick_unit = 0x40000e38; -r_ble_ll_check_scan_params = 0x40000e3c; -r_ble_ll_chk_txrx_octets = 0x40000e40; -r_ble_ll_chk_txrx_time = 0x40000e44; -r_ble_ll_conn_adjust_pyld_len = 0x40000e48; -r_ble_ll_conn_auth_pyld_timer_cb = 0x40000e4c; -r_ble_ll_conn_auth_pyld_timer_start = 0x40000e50; -r_ble_ll_conn_calc_dci = 0x40000e54; -r_ble_ll_conn_calc_dci_csa1 = 0x40000e58; -r_ble_ll_conn_calc_itvl_ticks = 0x40000e5c; -r_ble_ll_conn_can_send_next_pdu = 0x40000e60; -r_ble_ll_conn_chk_csm_flags = 0x40000e64; -r_ble_ll_conn_chk_phy_upd_start = 0x40000e68; -r_ble_ll_conn_coex_dpc_process = 0x40000e6c; -r_ble_ll_conn_coex_dpc_pti_get = 0x40000e70; -r_ble_ll_conn_coex_dpc_update = 0x40000e74; -r_ble_ll_conn_coex_dpc_update_on_event_scheduled = 0x40000e78; -r_ble_ll_conn_comp_event_send = 0x40000e7c; -r_ble_ll_conn_connect_ind_pdu_make = 0x40000e80; -r_ble_ll_conn_create = 0x40000e84; -r_ble_ll_conn_create_cancel = 0x40000e88; -r_ble_ll_conn_created = 0x40000e8c; -r_ble_ll_conn_cth_flow_alloc_credit = 0x40000e90; -r_ble_ll_conn_cth_flow_enable = 0x40000e94; -r_ble_ll_conn_cth_flow_error_fn = 0x40000e98; -r_ble_ll_conn_cth_flow_free_credit = 0x40000e9c; -r_ble_ll_conn_cth_flow_have_credit = 0x40000ea0; -r_ble_ll_conn_cth_flow_is_enabled = 0x40000ea4; -r_ble_ll_conn_cth_flow_process_cmd = 0x40000ea8; -r_ble_ll_conn_cth_flow_set_buffers = 0x40000eac; -r_ble_ll_conn_cur_pducb = 0x40000eb0; -r_ble_ll_conn_current_sm_over = 0x40000eb4; -r_ble_ll_conn_end = 0x40000eb8; -r_ble_ll_conn_enqueue_pkt = 0x40000ebc; -r_ble_ll_conn_env_init = 0x40000ec0; -r_ble_ll_conn_event_end = 0x40000ec4; -r_ble_ll_conn_event_end_timer_cb = 0x40000ec8; -r_ble_ll_conn_event_halt = 0x40000ecc; -r_ble_ll_conn_event_is_over = 0x40000ed0; -r_ble_ll_conn_event_start_cb = 0x40000ed4; -r_ble_ll_conn_ext_master_init = 0x40000ed8; -r_ble_ll_conn_ext_set_params = 0x40000edc; -r_ble_ll_conn_find_active_conn = 0x40000ee0; -r_ble_ll_conn_get_anchor = 0x40000ee4; -r_ble_ll_conn_get_ce_end_time = 0x40000ee8; -r_ble_ll_conn_get_new_pdu = 0x40000eec; -r_ble_ll_conn_get_next_sched_time = 0x40000ef0; -r_ble_ll_conn_halt = 0x40000ef4; -r_ble_ll_conn_hcc_params_set_fallback = 0x40000ef8; -r_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000efc; -r_ble_ll_conn_hci_chk_conn_params = 0x40000f00; -r_ble_ll_conn_hci_chk_scan_params = 0x40000f04; -r_ble_ll_conn_hci_disconnect_cmd = 0x40000f08; -r_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000f0c; -r_ble_ll_conn_hci_le_ltk_reply = 0x40000f10; -r_ble_ll_conn_hci_le_rd_phy = 0x40000f14; -r_ble_ll_conn_hci_le_set_phy = 0x40000f18; -r_ble_ll_conn_hci_le_start_encrypt = 0x40000f1c; -r_ble_ll_conn_hci_param_nrr = 0x40000f20; -r_ble_ll_conn_hci_param_rr = 0x40000f24; -r_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000f28; -r_ble_ll_conn_hci_rd_chan_map = 0x40000f2c; -r_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000f30; -r_ble_ll_conn_hci_rd_rssi = 0x40000f34; -r_ble_ll_conn_hci_read_rem_features = 0x40000f38; -r_ble_ll_conn_hci_set_chan_class = 0x40000f3c; -r_ble_ll_conn_hci_set_data_len = 0x40000f40; -r_ble_ll_conn_hci_update = 0x40000f44; -r_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000f48; -r_ble_ll_conn_init_pending_aux_conn_rsp = 0x40000f4c; -r_ble_ll_conn_init_phy = 0x40000f50; -r_ble_ll_conn_init_wfr_timer_exp = 0x40000f54; -r_ble_ll_conn_is_empty_pdu = 0x40000f58; -r_ble_ll_conn_is_lru = 0x40000f5c; -r_ble_ll_conn_master_common_init = 0x40000f60; -r_ble_ll_conn_master_init = 0x40000f64; -r_ble_ll_conn_module_deinit = 0x40000f68; -r_ble_ll_conn_module_init = 0x40000f6c; -r_ble_ll_conn_module_reset = 0x40000f70; -r_ble_ll_conn_new_pducb = 0x40000f74; -r_ble_ll_conn_next_event = 0x40000f78; -r_ble_ll_conn_num_comp_pkts_event_send = 0x40000f7c; -r_ble_ll_conn_process_conn_params = 0x40000f80; -r_ble_ll_conn_recv_ack = 0x40000f84; -r_ble_ll_conn_reset_pending_aux_conn_rsp = 0x40000f88; -r_ble_ll_conn_rx_data_pdu = 0x40000f8c; -r_ble_ll_conn_rx_isr_end = 0x40000f90; -r_ble_ll_conn_rx_isr_start = 0x40000f94; -r_ble_ll_conn_rxend_unencrypt = 0x40000f98; -r_ble_ll_conn_set_csa = 0x40000f9c; -r_ble_ll_conn_set_global_chanmap = 0x40000fa0; -r_ble_ll_conn_set_md_flag = 0x40000fa4; -r_ble_ll_conn_set_phy = 0x40000fa8; -r_ble_ll_conn_set_slave_flow_control = 0x40000fac; -r_ble_ll_conn_set_txpwr_by_handle = 0x40000fb0; -r_ble_ll_conn_set_unknown_rx_octets = 0x40000fb4; -r_ble_ll_conn_slave_start = 0x40000fb8; -r_ble_ll_conn_sm_get = 0x40000fbc; -r_ble_ll_conn_sm_new = 0x40000fc0; -r_ble_ll_conn_sm_npl_deinit = 0x40000fc4; -r_ble_ll_conn_sm_npl_init = 0x40000fc8; -r_ble_ll_conn_start_rx_encrypt = 0x40000fcc; -r_ble_ll_conn_start_rx_unencrypt = 0x40000fd0; -r_ble_ll_conn_timeout = 0x40000fd4; -r_ble_ll_conn_tx_pdu = 0x40000fd8; -r_ble_ll_conn_tx_pkt_in = 0x40000fdc; -r_ble_ll_conn_txend_encrypt = 0x40000fe0; -r_ble_ll_conn_update_conn_params = 0x40000fe4; -r_ble_ll_conn_update_eff_data_len = 0x40000fe8; -r_ble_ll_conn_update_new_pdu_len = 0x40000fec; -r_ble_ll_conn_wait_txend = 0x40000ff0; -r_ble_ll_conn_wfr_timer_exp = 0x40000ff4; -r_ble_ll_copy_data = 0x40000ff8; -r_ble_ll_ctrl_chanmap_req_make = 0x40000ffc; -r_ble_ll_ctrl_chk_proc_start = 0x40001000; -r_ble_ll_ctrl_conn_param_pdu_make = 0x40001004; -r_ble_ll_ctrl_conn_param_pdu_proc = 0x40001008; -r_ble_ll_ctrl_conn_param_reply = 0x4000100c; -r_ble_ll_ctrl_conn_upd_make = 0x40001010; -r_ble_ll_ctrl_datalen_upd_make = 0x40001014; -r_ble_ll_ctrl_enc_allowed_pdu = 0x40001018; -r_ble_ll_ctrl_enc_allowed_pdu_rx = 0x4000101c; -r_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40001020; -r_ble_ll_ctrl_enc_req_make = 0x40001024; -r_ble_ll_ctrl_find_new_phy = 0x40001028; -r_ble_ll_ctrl_initiate_dle = 0x4000102c; -r_ble_ll_ctrl_is_start_enc_rsp = 0x40001030; -r_ble_ll_ctrl_is_terminate_ind = 0x40001034; -r_ble_ll_ctrl_len_proc = 0x40001038; -r_ble_ll_ctrl_phy_from_phy_mask = 0x4000103c; -r_ble_ll_ctrl_phy_req_rsp_make = 0x40001040; -r_ble_ll_ctrl_phy_tx_transition_get = 0x40001044; -r_ble_ll_ctrl_phy_update_cancel = 0x40001048; -r_ble_ll_ctrl_phy_update_ind_make = 0x4000104c; -r_ble_ll_ctrl_phy_update_proc_complete = 0x40001050; -r_ble_ll_ctrl_proc_init = 0x40001054; -r_ble_ll_ctrl_proc_rsp_timer_cb = 0x40001058; -r_ble_ll_ctrl_proc_start = 0x4000105c; -r_ble_ll_ctrl_proc_stop = 0x40001060; -r_ble_ll_ctrl_proc_unk_rsp = 0x40001064; -r_ble_ll_ctrl_proc_with_instant_initiated = 0x40001068; -r_ble_ll_ctrl_rej_ext_ind_make = 0x4000106c; -r_ble_ll_ctrl_reject_ind_send = 0x40001070; -r_ble_ll_ctrl_rx_chanmap_req = 0x40001074; -r_ble_ll_ctrl_rx_conn_param_req = 0x40001078; -r_ble_ll_ctrl_rx_conn_param_rsp = 0x4000107c; -r_ble_ll_ctrl_rx_conn_update = 0x40001080; -r_ble_ll_ctrl_rx_enc_req = 0x40001084; -r_ble_ll_ctrl_rx_enc_rsp = 0x40001088; -r_ble_ll_ctrl_rx_feature_req = 0x4000108c; -r_ble_ll_ctrl_rx_feature_rsp = 0x40001090; -r_ble_ll_ctrl_rx_pause_enc_req = 0x40001094; -r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40001098; -r_ble_ll_ctrl_rx_pdu = 0x4000109c; -r_ble_ll_ctrl_rx_periodic_sync_ind = 0x400010a0; -r_ble_ll_ctrl_rx_phy_req = 0x400010a4; -r_ble_ll_ctrl_rx_phy_rsp = 0x400010a8; -r_ble_ll_ctrl_rx_phy_update_ind = 0x400010ac; -r_ble_ll_ctrl_rx_ping_rsp = 0x400010b0; -r_ble_ll_ctrl_rx_reject_ind = 0x400010b4; -r_ble_ll_ctrl_rx_start_enc_req = 0x400010b8; -r_ble_ll_ctrl_rx_start_enc_rsp = 0x400010bc; -r_ble_ll_ctrl_rx_version_ind = 0x400010c0; -r_ble_ll_ctrl_start_enc_send = 0x400010c4; -r_ble_ll_ctrl_start_rsp_timer = 0x400010c8; -r_ble_ll_ctrl_terminate_start = 0x400010cc; -r_ble_ll_ctrl_tx_done = 0x400010d0; -r_ble_ll_ctrl_update_features = 0x400010d4; -r_ble_ll_ctrl_version_ind_make = 0x400010d8; -r_ble_ll_data_buffer_overflow = 0x400010dc; -r_ble_ll_deinit = 0x400010e0; -r_ble_ll_disconn_comp_event_send = 0x400010e4; -r_ble_ll_dtm_calculate_itvl = 0x400010e8; -r_ble_ll_dtm_ctx_free = 0x400010ec; -r_ble_ll_dtm_deinit = 0x400010f0; -r_ble_ll_dtm_end_test = 0x400010f4; -r_ble_ll_dtm_ev_rx_restart_cb = 0x400010f8; -r_ble_ll_dtm_ev_tx_resched_cb = 0x400010fc; -r_ble_ll_dtm_init = 0x40001100; -r_ble_ll_dtm_reset = 0x40001104; -r_ble_ll_dtm_rx_create_ctx = 0x40001108; -r_ble_ll_dtm_rx_isr_end = 0x4000110c; -r_ble_ll_dtm_rx_isr_start = 0x40001110; -r_ble_ll_dtm_rx_pkt_in = 0x40001114; -r_ble_ll_dtm_rx_sched_cb = 0x40001118; -r_ble_ll_dtm_rx_start = 0x4000111c; -r_ble_ll_dtm_rx_test = 0x40001120; -r_ble_ll_dtm_set_next = 0x40001124; -r_ble_ll_dtm_tx_create_ctx = 0x40001128; -r_ble_ll_dtm_tx_done = 0x4000112c; -r_ble_ll_dtm_tx_sched_cb = 0x40001130; -r_ble_ll_dtm_tx_test = 0x40001134; -r_ble_ll_dtm_wfr_timer_exp = 0x40001138; -r_ble_ll_env_init = 0x4000113c; -r_ble_ll_event_comp_pkts = 0x40001140; -r_ble_ll_event_dbuf_overflow = 0x40001144; -r_ble_ll_event_rx_pkt = 0x40001148; -r_ble_ll_event_send = 0x4000114c; -r_ble_ll_event_tx_pkt = 0x40001150; -r_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40001154; -r_ble_ll_ext_conn_create = 0x40001158; -r_ble_ll_ext_scan_coex_dpc_process = 0x4000115c; -r_ble_ll_ext_scan_coex_dpc_pti_get = 0x40001160; -r_ble_ll_ext_scan_coex_dpc_update = 0x40001164; -r_ble_ll_ext_scan_coex_dpc_update_on_start = 0x40001168; -r_ble_ll_ext_scan_parse_adv_info = 0x4000116c; -r_ble_ll_ext_scan_parse_aux_ptr = 0x40001170; -r_ble_ll_flush_pkt_queue = 0x40001174; -r_ble_ll_generic_data_init = 0x40001178; -r_ble_ll_get_addr_type = 0x4000117c; -r_ble_ll_get_chan_to_scan = 0x40001180; -r_ble_ll_get_our_devaddr = 0x40001184; -r_ble_ll_get_tx_pwr_compensation = 0x40001188; -r_ble_ll_hci_acl_rx = 0x4000118c; -r_ble_ll_hci_adv_mode_ext = 0x40001190; -r_ble_ll_hci_adv_set_enable = 0x40001194; -r_ble_ll_hci_cb_host_buf_size = 0x40001198; -r_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x4000119c; -r_ble_ll_hci_cb_set_event_mask = 0x400011a0; -r_ble_ll_hci_cb_set_event_mask2 = 0x400011a4; -r_ble_ll_hci_chk_phy_masks = 0x400011a8; -r_ble_ll_hci_cmd_proc = 0x400011ac; -r_ble_ll_hci_cmd_rx = 0x400011b0; -r_ble_ll_hci_ctlr_bb_cmd_proc = 0x400011b4; -r_ble_ll_hci_deinit = 0x400011b8; -r_ble_ll_hci_disconnect = 0x400011bc; -r_ble_ll_hci_dtm_rx_test = 0x400011c0; -r_ble_ll_hci_dtm_rx_test_v2 = 0x400011c4; -r_ble_ll_hci_dtm_tx_test = 0x400011c8; -r_ble_ll_hci_dtm_tx_test_ext = 0x400011cc; -r_ble_ll_hci_dtm_tx_test_v2 = 0x400011d0; -r_ble_ll_hci_dtm_tx_test_v2_ext = 0x400011d4; -r_ble_ll_hci_env_init = 0x400011d8; -r_ble_ll_hci_ev_conn_update = 0x400011dc; -r_ble_ll_hci_ev_databuf_overflow = 0x400011e0; -r_ble_ll_hci_ev_datalen_chg = 0x400011e4; -r_ble_ll_hci_ev_encrypt_chg = 0x400011e8; -r_ble_ll_hci_ev_hw_err = 0x400011ec; -r_ble_ll_hci_ev_le_csa = 0x400011f0; -r_ble_ll_hci_ev_ltk_req = 0x400011f4; -r_ble_ll_hci_ev_phy_update = 0x400011f8; -r_ble_ll_hci_ev_rd_rem_used_feat = 0x400011fc; -r_ble_ll_hci_ev_rd_rem_ver = 0x40001200; -r_ble_ll_hci_ev_rem_conn_parm_req = 0x40001204; -r_ble_ll_hci_ev_send_adv_set_terminated = 0x40001208; -r_ble_ll_hci_ev_send_scan_req_recv = 0x4000120c; -r_ble_ll_hci_ev_send_scan_timeout = 0x40001210; -r_ble_ll_hci_ev_send_vendor_err = 0x40001214; -r_ble_ll_hci_event_send = 0x40001218; -r_ble_ll_hci_ext_scan_set_enable = 0x4000121c; -r_ble_ll_hci_get_num_cmd_pkts = 0x40001220; -r_ble_ll_hci_info_params_cmd_proc = 0x40001224; -r_ble_ll_hci_init = 0x40001228; -r_ble_ll_hci_is_event_enabled = 0x4000122c; -r_ble_ll_hci_is_le_event_enabled = 0x40001230; -r_ble_ll_hci_le_cmd_proc = 0x40001234; -r_ble_ll_hci_le_cmd_send_cmd_status = 0x40001238; -r_ble_ll_hci_le_encrypt = 0x4000123c; -r_ble_ll_hci_le_rand = 0x40001240; -r_ble_ll_hci_le_rd_max_data_len = 0x40001244; -r_ble_ll_hci_le_rd_sugg_data_len = 0x40001248; -r_ble_ll_hci_le_read_bufsize = 0x4000124c; -r_ble_ll_hci_le_read_local_features = 0x40001250; -r_ble_ll_hci_le_read_supp_states = 0x40001254; -r_ble_ll_hci_le_set_def_phy = 0x40001258; -r_ble_ll_hci_le_wr_sugg_data_len = 0x4000125c; -r_ble_ll_hci_link_ctrl_cmd_proc = 0x40001260; -r_ble_ll_hci_npl_init = 0x40001264; -r_ble_ll_hci_rd_bd_addr = 0x40001268; -r_ble_ll_hci_rd_local_supp_cmd = 0x4000126c; -r_ble_ll_hci_rd_local_supp_feat = 0x40001270; -r_ble_ll_hci_rd_local_version = 0x40001274; -r_ble_ll_hci_scan_set_enable = 0x40001278; -r_ble_ll_hci_send_adv_report = 0x4000127c; -r_ble_ll_hci_send_dir_adv_report = 0x40001280; -r_ble_ll_hci_send_ext_adv_report = 0x40001284; -r_ble_ll_hci_send_legacy_ext_adv_report = 0x40001288; -r_ble_ll_hci_send_noop = 0x4000128c; -r_ble_ll_hci_set_adv_data = 0x40001290; -r_ble_ll_hci_set_le_event_mask = 0x40001294; -r_ble_ll_hci_set_scan_rsp_data = 0x40001298; -r_ble_ll_hci_status_params_cmd_proc = 0x4000129c; -r_ble_ll_hci_vs_cmd_proc = 0x400012a0; -r_ble_ll_hci_vs_rd_static_addr = 0x400012a4; -r_ble_ll_hw_err_timer_cb = 0x400012a8; -r_ble_ll_hw_error = 0x400012ac; -r_ble_ll_init = 0x400012b0; -r_ble_ll_init_alloc_conn_comp_ev = 0x400012b4; -r_ble_ll_init_get_conn_comp_ev = 0x400012b8; -r_ble_ll_init_rx_isr_end = 0x400012bc; -r_ble_ll_init_rx_isr_start = 0x400012c0; -r_ble_ll_init_rx_pkt_in = 0x400012c4; -r_ble_ll_is_addr_empty = 0x400012c8; -r_ble_ll_is_controller_busy = 0x400012cc; -r_ble_ll_is_on_resolv_list = 0x400012d0; -r_ble_ll_is_our_devaddr = 0x400012d4; -r_ble_ll_is_rpa = 0x400012d8; -r_ble_ll_is_valid_adv_mode = 0x400012dc; -r_ble_ll_is_valid_own_addr_type = 0x400012e0; -r_ble_ll_is_valid_public_addr = 0x400012e4; -r_ble_ll_is_valid_random_addr = 0x400012e8; -r_ble_ll_mbuf_init = 0x400012ec; -r_ble_ll_misc_options_set = 0x400012f0; -r_ble_ll_pdu_max_tx_octets_get = 0x400012f4; -r_ble_ll_pdu_tx_time_get = 0x400012f8; -r_ble_ll_per_adv_coex_dpc_calc_pti_update_itvl = 0x400012fc; -r_ble_ll_per_adv_coex_dpc_process = 0x40001300; -r_ble_ll_per_adv_coex_dpc_pti_get = 0x40001304; -r_ble_ll_per_adv_coex_dpc_update = 0x40001308; -r_ble_ll_per_adv_coex_dpc_update_on_data_updated = 0x4000130c; -r_ble_ll_per_adv_coex_dpc_update_on_scheduled = 0x40001310; -r_ble_ll_per_adv_coex_dpc_update_on_start = 0x40001314; -r_ble_ll_phy_to_phy_mode = 0x40001318; -r_ble_ll_process_rx_data = 0x4000131c; -r_ble_ll_qa_enable = 0x40001320; -r_ble_ll_rand = 0x40001324; -r_ble_ll_rand_data_get = 0x40001328; -r_ble_ll_rand_deinit = 0x4000132c; -r_ble_ll_rand_env_init = 0x40001330; -r_ble_ll_rand_init = 0x40001334; -r_ble_ll_rand_prand_get = 0x40001338; -r_ble_ll_rand_sample = 0x4000133c; -r_ble_ll_rand_start = 0x40001340; -r_ble_ll_read_rf_path_compensation = 0x40001344; -r_ble_ll_read_supp_features = 0x40001348; -r_ble_ll_read_supp_states = 0x4000134c; -r_ble_ll_read_tx_power = 0x40001350; -r_ble_ll_reset = 0x40001354; -r_ble_ll_resolv_clear_all_pl_bit = 0x40001358; -r_ble_ll_resolv_clear_all_wl_bit = 0x4000135c; -r_ble_ll_resolv_deinit = 0x40001360; -r_ble_ll_resolv_enable_cmd = 0x40001364; -r_ble_ll_resolv_enabled = 0x40001368; -r_ble_ll_resolv_env_init = 0x4000136c; -r_ble_ll_resolv_gen_priv_addr = 0x40001370; -r_ble_ll_resolv_gen_rpa = 0x40001374; -r_ble_ll_resolv_get_addr_pointer = 0x40001378; -r_ble_ll_resolv_get_entry = 0x4000137c; -r_ble_ll_resolv_get_index = 0x40001380; -r_ble_ll_resolv_get_irk_pointer = 0x40001384; -r_ble_ll_resolv_get_list = 0x40001388; -r_ble_ll_resolv_get_priv_addr = 0x4000138c; -r_ble_ll_resolv_get_rpa_tmo = 0x40001390; -r_ble_ll_resolv_init = 0x40001394; -r_ble_ll_resolv_irk_nonzero = 0x40001398; -r_ble_ll_resolv_list_add = 0x4000139c; -r_ble_ll_resolv_list_chg_allowed = 0x400013a0; -r_ble_ll_resolv_list_clr = 0x400013a4; -r_ble_ll_resolv_list_find = 0x400013a8; -r_ble_ll_resolv_list_read_size = 0x400013ac; -r_ble_ll_resolv_list_reset = 0x400013b0; -r_ble_ll_resolv_list_rmv = 0x400013b4; -r_ble_ll_resolv_local_addr_rd = 0x400013b8; -r_ble_ll_resolv_peer_addr_rd = 0x400013bc; -r_ble_ll_resolv_peer_rpa_any = 0x400013c0; -r_ble_ll_resolv_reset = 0x400013c4; -r_ble_ll_resolv_rpa = 0x400013c8; -r_ble_ll_resolv_rpa_timer_cb = 0x400013cc; -r_ble_ll_resolv_set_local_rpa = 0x400013d0; -r_ble_ll_resolv_set_peer_rpa = 0x400013d4; -r_ble_ll_resolv_set_rpa_tmo = 0x400013d8; -r_ble_ll_resolve_set_priv_mode = 0x400013dc; -r_ble_ll_rfmgmt_controller_sleep_en = 0x400013e0; -r_ble_ll_rfmgmt_deinit = 0x400013e4; -r_ble_ll_rfmgmt_disable = 0x400013e8; -r_ble_ll_rfmgmt_enable = 0x400013ec; -r_ble_ll_rfmgmt_enable_now = 0x400013f0; -r_ble_ll_rfmgmt_init = 0x400013f4; -r_ble_ll_rfmgmt_is_enabled = 0x400013f8; -r_ble_ll_rfmgmt_release = 0x400013fc; -r_ble_ll_rfmgmt_release_ev = 0x40001400; -r_ble_ll_rfmgmt_reset = 0x40001404; -r_ble_ll_rfmgmt_scan_changed = 0x40001408; -r_ble_ll_rfmgmt_sched_changed = 0x4000140c; -r_ble_ll_rfmgmt_set_sleep_cb = 0x40001410; -r_ble_ll_rfmgmt_ticks_to_enabled = 0x40001414; -r_ble_ll_rfmgmt_timer_exp = 0x40001418; -r_ble_ll_rfmgmt_timer_reschedule = 0x4000141c; -r_ble_ll_rx_end = 0x40001420; -r_ble_ll_rx_pdu_in = 0x40001424; -r_ble_ll_rx_pkt_in = 0x40001428; -r_ble_ll_rx_start = 0x4000142c; -r_ble_ll_rxpdu_alloc = 0x40001430; -r_ble_ll_scan_add_scan_rsp_adv = 0x40001434; -r_ble_ll_scan_adv_decode_addr = 0x40001438; -r_ble_ll_scan_aux_data_free = 0x4000143c; -r_ble_ll_scan_aux_data_ref = 0x40001440; -r_ble_ll_scan_aux_data_unref = 0x40001444; -r_ble_ll_scan_can_chg_whitelist = 0x40001448; -r_ble_ll_scan_check_periodic_sync = 0x4000144c; -r_ble_ll_scan_chk_resume = 0x40001450; -r_ble_ll_scan_clean_cur_aux_data = 0x40001454; -r_ble_ll_scan_common_init = 0x40001458; -r_ble_ll_scan_continue_en = 0x4000145c; -r_ble_ll_scan_deinit = 0x40001460; -r_ble_ll_scan_dup_check_ext = 0x40001464; -r_ble_ll_scan_dup_check_legacy = 0x40001468; -r_ble_ll_scan_dup_move_to_head = 0x4000146c; -r_ble_ll_scan_dup_new = 0x40001470; -r_ble_ll_scan_dup_update_ext = 0x40001474; -r_ble_ll_scan_dup_update_legacy = 0x40001478; -r_ble_ll_scan_duration_period_timers_restart = 0x4000147c; -r_ble_ll_scan_duration_timer_cb = 0x40001480; -r_ble_ll_scan_enabled = 0x40001484; -r_ble_ll_scan_end_adv_evt = 0x40001488; -r_ble_ll_scan_env_init = 0x4000148c; -r_ble_ll_scan_event_proc = 0x40001490; -r_ble_ll_scan_ext_adv_init = 0x40001494; -r_ble_ll_scan_ext_initiator_start = 0x40001498; -r_ble_ll_scan_get_addr_data_from_legacy = 0x4000149c; -r_ble_ll_scan_get_addr_from_ext_adv = 0x400014a0; -r_ble_ll_scan_get_cur_sm = 0x400014a4; -r_ble_ll_scan_get_ext_adv_report = 0x400014a8; -r_ble_ll_scan_get_local_rpa = 0x400014ac; -r_ble_ll_scan_get_next_adv_prim_chan = 0x400014b0; -r_ble_ll_scan_get_pdu_data = 0x400014b4; -r_ble_ll_scan_get_peer_rpa = 0x400014b8; -r_ble_ll_scan_halt = 0x400014bc; -r_ble_ll_scan_has_sent_scan_req = 0x400014c0; -r_ble_ll_scan_have_rxd_scan_rsp = 0x400014c4; -r_ble_ll_scan_init = 0x400014c8; -r_ble_ll_scan_initiator_start = 0x400014cc; -r_ble_ll_scan_interrupted = 0x400014d0; -r_ble_ll_scan_interrupted_event_cb = 0x400014d4; -r_ble_ll_scan_is_inside_window = 0x400014d8; -r_ble_ll_scan_move_window_to = 0x400014dc; -r_ble_ll_scan_npl_init = 0x400014e0; -r_ble_ll_scan_npl_reset = 0x400014e4; -r_ble_ll_scan_npl_restore = 0x400014e8; -r_ble_ll_scan_npl_store = 0x400014ec; -r_ble_ll_scan_parse_ext_hdr = 0x400014f0; -r_ble_ll_scan_period_timer_cb = 0x400014f4; -r_ble_ll_scan_record_new_adv = 0x400014f8; -r_ble_ll_scan_refresh_nrpa = 0x400014fc; -r_ble_ll_scan_req_backoff = 0x40001500; -r_ble_ll_scan_reset = 0x40001504; -r_ble_ll_scan_rx_filter = 0x40001508; -r_ble_ll_scan_rx_isr_end = 0x4000150c; -r_ble_ll_scan_rx_isr_on_aux = 0x40001510; -r_ble_ll_scan_rx_isr_on_legacy = 0x40001514; -r_ble_ll_scan_rx_isr_start = 0x40001518; -r_ble_ll_scan_rx_pkt_in = 0x4000151c; -r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001520; -r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001524; -r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001528; -r_ble_ll_scan_rxed = 0x4000152c; -r_ble_ll_scan_sched_remove = 0x40001530; -r_ble_ll_scan_send_adv_report = 0x40001534; -r_ble_ll_scan_send_truncated = 0x40001538; -r_ble_ll_scan_set_enable = 0x4000153c; -r_ble_ll_scan_set_peer_rpa = 0x40001540; -r_ble_ll_scan_set_scan_params = 0x40001544; -r_ble_ll_scan_sm_start = 0x40001548; -r_ble_ll_scan_sm_stop = 0x4000154c; -r_ble_ll_scan_start = 0x40001550; -r_ble_ll_scan_time_hci_to_ticks = 0x40001554; -r_ble_ll_scan_timer_cb = 0x40001558; -r_ble_ll_scan_update_aux_data = 0x4000155c; -r_ble_ll_scan_wfr_timer_exp = 0x40001560; -r_ble_ll_scan_whitelist_enabled = 0x40001564; -r_ble_ll_sched_adv_new = 0x40001568; -r_ble_ll_sched_adv_resched_pdu = 0x4000156c; -r_ble_ll_sched_adv_reschedule = 0x40001570; -r_ble_ll_sched_aux_scan = 0x40001574; -r_ble_ll_sched_conn_overlap = 0x40001578; -r_ble_ll_sched_conn_reschedule = 0x4000157c; -r_ble_ll_sched_deinit = 0x40001580; -r_ble_ll_sched_dtm = 0x40001584; -r_ble_ll_sched_env_init = 0x40001588; -r_ble_ll_sched_execute_item = 0x4000158c; -r_ble_ll_sched_init = 0x40001590; -r_ble_ll_sched_insert_if_empty = 0x40001594; -r_ble_ll_sched_is_overlap = 0x40001598; -r_ble_ll_sched_master_new = 0x4000159c; -r_ble_ll_sched_next_time = 0x400015a0; -r_ble_ll_sched_overlaps_current = 0x400015a4; -r_ble_ll_sched_periodic_adv = 0x400015a8; -r_ble_ll_sched_rmv_elem = 0x400015ac; -r_ble_ll_sched_rmv_elem_type = 0x400015b0; -r_ble_ll_sched_run = 0x400015b4; -r_ble_ll_sched_scan_req_over_aux_ptr = 0x400015b8; -r_ble_ll_sched_slave_new = 0x400015bc; -r_ble_ll_sched_stop = 0x400015c0; -r_ble_ll_sched_sync = 0x400015c4; -r_ble_ll_sched_sync_overlaps_current = 0x400015c8; -r_ble_ll_sched_sync_reschedule = 0x400015cc; -r_ble_ll_set_default_privacy_mode = 0x400015d0; -r_ble_ll_set_default_sync_transfer_params = 0x400015d4; -r_ble_ll_set_ext_scan_params = 0x400015d8; -r_ble_ll_set_host_feat = 0x400015dc; -r_ble_ll_set_public_addr = 0x400015e0; -r_ble_ll_set_random_addr = 0x400015e4; -r_ble_ll_set_sync_transfer_params = 0x400015e8; -r_ble_ll_slave_rx_isr_end = 0x400015ec; -r_ble_ll_state_get = 0x400015f0; -r_ble_ll_state_set = 0x400015f4; -r_ble_ll_sync_adjust_ext_hdr = 0x400015f8; -r_ble_ll_sync_cancel = 0x400015fc; -r_ble_ll_sync_cancel_complete_event = 0x40001600; -r_ble_ll_sync_chain_start_cb = 0x40001604; -r_ble_ll_sync_check_acad = 0x40001608; -r_ble_ll_sync_check_failed = 0x4000160c; -r_ble_ll_sync_coex_dpc_process = 0x40001610; -r_ble_ll_sync_coex_dpc_pti_get = 0x40001614; -r_ble_ll_sync_coex_dpc_update = 0x40001618; -r_ble_ll_sync_create = 0x4000161c; -r_ble_ll_sync_current_sm_over = 0x40001620; -r_ble_ll_sync_deinit = 0x40001624; -r_ble_ll_sync_enabled = 0x40001628; -r_ble_ll_sync_env_init = 0x4000162c; -r_ble_ll_sync_est_event_failed = 0x40001630; -r_ble_ll_sync_est_event_success = 0x40001634; -r_ble_ll_sync_established = 0x40001638; -r_ble_ll_sync_event_end = 0x4000163c; -r_ble_ll_sync_event_start_cb = 0x40001640; -r_ble_ll_sync_filter_enabled = 0x40001644; -r_ble_ll_sync_find = 0x40001648; -r_ble_ll_sync_get_cur_sm = 0x4000164c; -r_ble_ll_sync_get_event_end_time = 0x40001650; -r_ble_ll_sync_get_handle = 0x40001654; -r_ble_ll_sync_halt = 0x40001658; -r_ble_ll_sync_has_been_reported = 0x4000165c; -r_ble_ll_sync_info_event = 0x40001660; -r_ble_ll_sync_init = 0x40001664; -r_ble_ll_sync_list_add = 0x40001668; -r_ble_ll_sync_list_clear = 0x4000166c; -r_ble_ll_sync_list_empty = 0x40001670; -r_ble_ll_sync_list_get_free = 0x40001674; -r_ble_ll_sync_list_remove = 0x40001678; -r_ble_ll_sync_list_search = 0x4000167c; -r_ble_ll_sync_list_size = 0x40001680; -r_ble_ll_sync_lost_event = 0x40001684; -r_ble_ll_sync_next_event = 0x40001688; -r_ble_ll_sync_on_list = 0x4000168c; -r_ble_ll_sync_parse_aux_ptr = 0x40001690; -r_ble_ll_sync_parse_ext_hdr = 0x40001694; -r_ble_ll_sync_periodic_ind = 0x40001698; -r_ble_ll_sync_phy_mode_to_aux_phy = 0x4000169c; -r_ble_ll_sync_phy_mode_to_hci = 0x400016a0; -r_ble_ll_sync_put_syncinfo = 0x400016a4; -r_ble_ll_sync_reserve = 0x400016a8; -r_ble_ll_sync_reset = 0x400016ac; -r_ble_ll_sync_reset_sm = 0x400016b0; -r_ble_ll_sync_rmvd_from_sched = 0x400016b4; -r_ble_ll_sync_rx_isr_end = 0x400016b8; -r_ble_ll_sync_rx_isr_start = 0x400016bc; -r_ble_ll_sync_rx_pkt_in = 0x400016c0; -r_ble_ll_sync_schedule_chain = 0x400016c4; -r_ble_ll_sync_send_per_adv_rpt = 0x400016c8; -r_ble_ll_sync_send_sync_ind = 0x400016cc; -r_ble_ll_sync_send_truncated_per_adv_rpt = 0x400016d0; -r_ble_ll_sync_sm_clear = 0x400016d4; -r_ble_ll_sync_terminate = 0x400016d8; -r_ble_ll_sync_transfer = 0x400016dc; -r_ble_ll_sync_transfer_get = 0x400016e0; -r_ble_ll_sync_transfer_received = 0x400016e4; -r_ble_ll_sync_wfr_timer_exp = 0x400016e8; -r_ble_ll_task = 0x400016ec; -r_ble_ll_trace_set_func = 0x400016f0; -r_ble_ll_trace_u32 = 0x400016f4; -r_ble_ll_trace_u32x2 = 0x400016f8; -r_ble_ll_trace_u32x3 = 0x400016fc; -r_ble_ll_tx_flat_mbuf_pducb = 0x40001700; -r_ble_ll_tx_mbuf_pducb = 0x40001704; -r_ble_ll_tx_pkt_in = 0x40001708; -r_ble_ll_update_max_tx_octets_phy_mode = 0x4000170c; -r_ble_ll_usecs_to_ticks_round_up = 0x40001710; -r_ble_ll_utils_calc_access_addr = 0x40001714; -r_ble_ll_utils_calc_dci_csa2 = 0x40001718; -r_ble_ll_utils_calc_num_used_chans = 0x4000171c; -r_ble_ll_utils_calc_window_widening = 0x40001720; -r_ble_ll_utils_csa2_perm = 0x40001724; -r_ble_ll_utils_csa2_prng = 0x40001728; -r_ble_ll_utils_remapped_channel = 0x4000172c; -r_ble_ll_wfr_timer_exp = 0x40001730; -r_ble_ll_whitelist_add = 0x40001734; -r_ble_ll_whitelist_chg_allowed = 0x40001738; -r_ble_ll_whitelist_clear = 0x4000173c; -r_ble_ll_whitelist_read_size = 0x40001740; -r_ble_ll_whitelist_rmv = 0x40001744; -r_ble_ll_whitelist_search = 0x40001748; -r_ble_ll_write_rf_path_compensation = 0x4000174c; -r_ble_phy_access_addr_get = 0x40001750; -r_ble_phy_bb_bug_is_triggered = 0x40001754; -r_ble_phy_calculate_rxtx_ifs = 0x40001758; -r_ble_phy_calculate_rxwindow = 0x4000175c; -r_ble_phy_calculate_txrx_ifs = 0x40001760; -r_ble_phy_config_access_addr = 0x40001764; -r_ble_phy_data_make = 0x40001768; -r_ble_phy_disable = 0x4000176c; -r_ble_phy_disable_irq = 0x40001770; -r_ble_phy_disable_whitening = 0x40001774; -r_ble_phy_enable_scan_seq_immediately = 0x40001778; -r_ble_phy_enable_whitening = 0x4000177c; -r_ble_phy_encrypt_disable = 0x40001780; -r_ble_phy_env_init = 0x40001784; -r_ble_phy_get_current_phy = 0x40001788; -r_ble_phy_get_packet_counter = 0x4000178c; -r_ble_phy_get_packet_status = 0x40001790; -r_ble_phy_get_pyld_time_offset = 0x40001794; -r_ble_phy_get_rx_phy_mode = 0x40001798; -r_ble_phy_init = 0x4000179c; -r_ble_phy_isr = 0x400017a0; -r_ble_phy_max_data_pdu_pyld = 0x400017a4; -r_ble_phy_mode_config = 0x400017a8; -r_ble_phy_mode_convert = 0x400017ac; -r_ble_phy_mode_write = 0x400017b0; -r_ble_phy_module_deinit = 0x400017b4; -r_ble_phy_module_init = 0x400017b8; -r_ble_phy_monitor_bb_sync = 0x400017bc; -r_ble_phy_need_to_report = 0x400017c0; -r_ble_phy_pkt_received = 0x400017c4; -r_ble_phy_reset_bb_monitor = 0x400017c8; -r_ble_phy_resolv_list_disable = 0x400017cc; -r_ble_phy_resolv_list_enable = 0x400017d0; -r_ble_phy_restart_sequence = 0x400017d4; -r_ble_phy_rfclk_disable = 0x400017d8; -r_ble_phy_rfclk_enable = 0x400017dc; -r_ble_phy_rx_is_expected = 0x400017e0; -r_ble_phy_rxpdu_copy = 0x400017e4; -r_ble_phy_scan_set_start_time = 0x400017e8; -r_ble_phy_seq_encrypt_enable = 0x400017ec; -r_ble_phy_seq_encrypt_set_pkt_cntr = 0x400017f0; -r_ble_phy_sequence_adv_end = 0x400017f4; -r_ble_phy_sequence_copy_rx_flags = 0x400017f8; -r_ble_phy_sequence_end_isr = 0x400017fc; -r_ble_phy_sequence_get_mode = 0x40001800; -r_ble_phy_sequence_get_state = 0x40001804; -r_ble_phy_sequence_init_end = 0x40001808; -r_ble_phy_sequence_is_running = 0x4000180c; -r_ble_phy_sequence_is_waiting_rsp = 0x40001810; -r_ble_phy_sequence_isr_copy_data = 0x40001814; -r_ble_phy_sequence_master_end = 0x40001818; -r_ble_phy_sequence_rx_end_isr = 0x4000181c; -r_ble_phy_sequence_scan_end = 0x40001820; -r_ble_phy_sequence_single_end = 0x40001824; -r_ble_phy_sequence_slave_end = 0x40001828; -r_ble_phy_sequence_tx_end_invoke = 0x4000182c; -r_ble_phy_sequence_update_conn_params = 0x40001830; -r_ble_phy_set_adv_sequence = 0x40001834; -r_ble_phy_set_coex_pti = 0x40001838; -r_ble_phy_set_dev_address = 0x4000183c; -r_ble_phy_set_master_sequence = 0x40001840; -r_ble_phy_set_rx_pwr_compensation = 0x40001844; -r_ble_phy_set_rxhdr_flags = 0x40001848; -r_ble_phy_set_rxhdr_info = 0x4000184c; -r_ble_phy_set_scan_sequence = 0x40001850; -r_ble_phy_set_single_packet_rx_sequence = 0x40001854; -r_ble_phy_set_single_packet_tx_sequence = 0x40001858; -r_ble_phy_set_slave_sequence = 0x4000185c; -r_ble_phy_set_txend_cb = 0x40001860; -r_ble_phy_setchan = 0x40001864; -r_ble_phy_slave_set_start_time = 0x40001868; -r_ble_phy_state_get = 0x4000186c; -r_ble_phy_timer_config_start_time = 0x40001870; -r_ble_phy_timer_start_now = 0x40001874; -r_ble_phy_timer_stop = 0x40001878; -r_ble_phy_tx_set_start_time = 0x4000187c; -r_ble_phy_txpower_round = 0x40001880; -r_ble_phy_txpwr_set = 0x40001884; -r_ble_phy_wfr_enable = 0x40001888; -r_ble_phy_xcvr_state_get = 0x4000188c; -r_ble_plf_set_log_level = 0x40001890; -r_ble_vendor_hci_register = 0x40001894; -r_bleonly_os_tick_init = 0x40001898; -r_bt_rf_coex_cfg_set = 0x4000189c; -r_bt_rf_coex_coded_txrx_time_upper_lim = 0x400018a0; -r_bt_rf_coex_dft_pti_set = 0x400018a4; -r_bt_rf_coex_hook_deinit = 0x400018a8; -r_bt_rf_coex_hook_init = 0x400018ac; -r_bt_rf_coex_hook_st_set = 0x400018b0; -r_bt_rf_coex_hooks_p_set_default = 0x400018b4; -r_btdm_disable_adv_delay = 0x400018b8; -r_btdm_switch_phy_coded = 0x400018bc; -r_esp_wait_disabled = 0x400018c0; -r_get_be16 = 0x400018c4; -r_get_be24 = 0x400018c8; -r_get_be32 = 0x400018cc; -r_get_be64 = 0x400018d0; -r_get_le16 = 0x400018d4; -r_get_le24 = 0x400018d8; -r_get_le32 = 0x400018dc; -r_get_le64 = 0x400018e0; -r_get_local_irk_offset = 0x400018e4; -r_get_local_rpa_offset = 0x400018e8; -r_get_max_skip = 0x400018ec; -r_get_peer_id_offset = 0x400018f0; -r_get_peer_irk_offset = 0x400018f4; -r_get_peer_rpa_offset = 0x400018f8; -r_hal_os_tick_read_tick = 0x400018fc; -r_hal_os_tick_set_exp_tick = 0x40001900; -r_hal_rtc_intr_init = 0x40001904; -r_hal_rtc_irq_handler = 0x40001908; -r_hal_timer_deinit = 0x4000190c; -r_hal_timer_disable_irq = 0x40001910; -r_hal_timer_env_init = 0x40001914; -r_hal_timer_init = 0x40001918; -r_hal_timer_process = 0x4000191c; -r_hal_timer_read = 0x40001920; -r_hal_timer_read_tick = 0x40001924; -r_hal_timer_set_cb = 0x40001928; -r_hal_timer_set_exp_tick = 0x4000192c; -r_hal_timer_start = 0x40001930; -r_hal_timer_start_at = 0x40001934; -r_hal_timer_stop = 0x40001938; -r_hal_timer_task_start = 0x4000193c; -r_ll_assert = 0x40001940; -r_mem_init_mbuf_pool = 0x40001944; -r_mem_malloc_mbuf_pool = 0x40001948; -r_mem_malloc_mbufpkt_pool = 0x4000194c; -r_mem_malloc_mempool = 0x40001950; -r_mem_malloc_mempool_ext = 0x40001954; -r_mem_malloc_mempool_gen = 0x40001958; -r_mem_pullup_obj = 0x4000195c; -r_mem_split_frag = 0x40001960; -r_os_cputime_delay_ticks = 0x40001964; -r_os_cputime_delay_usecs = 0x40001968; -r_os_cputime_get32 = 0x4000196c; -r_os_cputime_ticks_to_usecs = 0x40001970; -r_os_cputime_timer_init = 0x40001974; -r_os_cputime_timer_relative = 0x40001978; -r_os_cputime_timer_start = 0x4000197c; -r_os_cputime_timer_stop = 0x40001980; -r_os_cputime_usecs_to_ticks = 0x40001984; -r_os_mbuf_adj = 0x40001988; -r_os_mbuf_append = 0x4000198c; -r_os_mbuf_appendfrom = 0x40001990; -r_os_mbuf_cmpf = 0x40001994; -r_os_mbuf_cmpm = 0x40001998; -r_os_mbuf_concat = 0x4000199c; -r_os_mbuf_copydata = 0x400019a0; -r_os_mbuf_copyinto = 0x400019a4; -r_os_mbuf_dup = 0x400019a8; -r_os_mbuf_extend = 0x400019ac; -r_os_mbuf_free = 0x400019b0; -r_os_mbuf_free_chain = 0x400019b4; -r_os_mbuf_get = 0x400019b8; -r_os_mbuf_get_pkthdr = 0x400019bc; -r_os_mbuf_len = 0x400019c0; -r_os_mbuf_off = 0x400019c4; -r_os_mbuf_pack_chains = 0x400019c8; -r_os_mbuf_pool_init = 0x400019cc; -r_os_mbuf_prepend = 0x400019d0; -r_os_mbuf_prepend_pullup = 0x400019d4; -r_os_mbuf_pullup = 0x400019d8; -r_os_mbuf_trim_front = 0x400019dc; -r_os_mbuf_widen = 0x400019e0; -r_os_memblock_from = 0x400019e4; -r_os_memblock_get = 0x400019e8; -r_os_memblock_put = 0x400019ec; -r_os_memblock_put_from_cb = 0x400019f0; -r_os_mempool_clear = 0x400019f4; -r_os_mempool_ext_clear = 0x400019f8; -r_os_mempool_ext_init = 0x400019fc; -r_os_mempool_info_get_next = 0x40001a00; -r_os_mempool_init = 0x40001a04; -r_os_mempool_init_internal = 0x40001a08; -r_os_mempool_is_sane = 0x40001a0c; -r_os_mempool_module_init = 0x40001a10; -r_os_mempool_unregister = 0x40001a14; -r_os_mqueue_get = 0x40001a18; -r_os_mqueue_init = 0x40001a1c; -r_os_mqueue_put = 0x40001a20; -r_os_msys_count = 0x40001a24; -r_os_msys_get = 0x40001a28; -r_os_msys_get_pkthdr = 0x40001a2c; -r_os_msys_num_free = 0x40001a30; -r_os_msys_register = 0x40001a34; -r_os_msys_reset = 0x40001a38; -r_os_tick_idle = 0x40001a3c; -r_pri_phy_valid = 0x40001a40; -r_put_be16 = 0x40001a44; -r_put_be24 = 0x40001a48; -r_put_be32 = 0x40001a4c; -r_put_be64 = 0x40001a50; -r_put_le16 = 0x40001a54; -r_put_le24 = 0x40001a58; -r_put_le32 = 0x40001a5c; -r_put_le64 = 0x40001a60; -r_rtc0_timer_handler = 0x40001a64; -r_rtc1_timer_handler = 0x40001a68; -r_sdkconfig_get_opts = 0x40001a6c; -r_sdkconfig_set_opts = 0x40001a70; -r_sec_phy_valid = 0x40001a74; -r_sub24 = 0x40001a78; -r_swap_buf = 0x40001a7c; -r_swap_in_place = 0x40001a80; -*/ -/* Data (.data, .bss, .rodata) */ -/* -ble_hci_uart_reset_cmd = 0x3ff1ffe0; -ble_hci_trans_env_p = 0x3fcdffc4; -ble_hci_trans_mode = 0x3fcdfebc; -ble_ll_adv_env_p = 0x3fcdffc0; -ble_ll_conn_env_p = 0x3fcdffbc; -g_ble_ll_conn_cth_flow = 0x3fcdffb4; -g_ble_ll_conn_cth_flow_error_ev = 0x3fcdffb0; -g_ble_ll_ctrl_pkt_lengths_ro = 0x3ff1ffbc; -ble_ll_dtm_module_env_p = 0x3fcdffac; -channel_rf_to_index = 0x3ff1ff94; -g_ble_ll_dtm_prbs15_data = 0x3ff1fe94; -g_ble_ll_dtm_prbs9_data = 0x3ff1fd94; -ble_ll_hci_env_p = 0x3fcdffa8; -ble_ll_rand_env_p = 0x3fcdffa4; -ble_ll_resolv_env_p = 0x3fcdffa0; -g_ble_ll_resolve_hdr = 0x3fcdff98; -g_device_mode_default = 0x3fcdfeba; -g_ble_ll_rfmgmt_data = 0x3fcdff50; -g_ble_sleep_enter_cb = 0x3fcdff4c; -g_ble_sleep_exit_cb = 0x3fcdff48; -g_rfclk_enabled = 0x3fcdff44; -ble_ll_scan_env_p = 0x3fcdff40; -ble_ll_sched_env_p = 0x3fcdff3c; -g_ble_ll_supp_cmds_ro = 0x3ff1fd64; -ble_ll_sync_env_p = 0x3fcdff38; -g_ble_sca_ppm_tbl_ro = 0x3ff1fd54; -ble_ll_env_p = 0x3fcdff34; -g_ble_ll_pdu_header_tx_time_ro = 0x3ff1fd4c; -priv_config_opts = 0x3fcdfea4; -ble_hci_trans_funcs_ptr = 0x3fcdff30; -r_ble_stub_funcs_ptr = 0x3fcdff2c; -r_ext_funcs_p = 0x3fcdff28; -r_npl_funcs = 0x3fcdff24; -ble_hw_env_p = 0x3fcdff20; -ble_phy_module_env_p = 0x3fcdff1c; -g_ble_phy_chan_freq_ro = 0x3ff1fd24; -g_ble_phy_mode_pkt_start_off_ro = 0x3ff1fd1c; -g_ble_phy_rxtx_ifs_compensation_ro = 0x3ff1fd0c; -g_ble_phy_t_rxaddrdelay_ro = 0x3ff1fd08; -g_ble_phy_t_rxenddelay_ro = 0x3ff1fd04; -g_ble_phy_t_txdelay_ro = 0x3ff1fd00; -g_ble_phy_t_txenddelay_ro = 0x3ff1fcfc; -g_ble_phy_txrx_ifs_compensation_ro = 0x3ff1fcec; -hal_timer_env_p = 0x3fcdff18; -g_hal_os_tick = 0x3fcdff0c; -r_osi_coex_funcs_p = 0x3fcdff08; -bt_rf_coex_hooks = 0x3fcdff00; -bt_rf_coex_hooks_p = 0x3fcdfefc; -coex_hook_st_group_tab = 0x3ff1fce0; -coex_hook_st_group_to_coex_schm_st_tab = 0x3ff1fcdc; -s_ble_act_count_by_group = 0x3fcdfef8; -s_ble_coex_st_map = 0x3fcdfee4; -bt_rf_coex_cfg_cb = 0x3fcdfec8; -bt_rf_coex_cfg_p = 0x3fcdfec4; -bt_rf_coex_cfg_rom = 0x3ff1fcc0; -bt_rf_coex_pti_dft_p = 0x3fcdfec0; -bt_rf_coex_pti_dft_rom = 0x3fcdfe64; -conn_dynamic_pti_param_rom = 0x3ff1fca8; -conn_phy_coded_max_data_time_param_rom = 0x3ff1fca4; -ext_adv_dynamic_pti_param_rom = 0x3ff1fc70; -ext_scan_dynamic_param_rom = 0x3ff1fc38; -legacy_adv_dynamic_pti_param_rom = 0x3ff1fc18; -per_adv_dynamic_pti_param_rom = 0x3ff1fbfc; -sync_dynamic_param_rom = 0x3ff1fbe4; -g_ble_plf_log_level = 0x3fcdfe60; -g_msys_pool_list = 0x3fcdfe58; -g_os_mempool_list = 0x3fcdfe50; -*/ - -/*************************************** - Group rom_phy - ***************************************/ - -/* Functions */ -phy_param_addr = 0x40001a84; -phy_get_romfuncs = 0x40001a88; -chip729_phyrom_version = 0x40001a8c; -chip729_phyrom_version_num = 0x40001a90; -rom_get_i2c_read_mask = 0x40001c6c; -rom_get_i2c_mst0_mask = 0x40001c70; -rom_get_i2c_hostid = 0x40001c74; -rom_chip_i2c_readReg_org = 0x40001c78; -rom_chip_i2c_readReg = 0x40001c7c; -rom_i2c_paral_set_mst0 = 0x40001c80; -rom_i2c_paral_set_read = 0x40001c84; -rom_i2c_paral_read = 0x40001c88; -rom_i2c_paral_write = 0x40001c8c; -rom_i2c_paral_write_num = 0x40001c90; -rom_i2c_paral_write_mask = 0x40001c94; -rom_i2c_readReg = 0x40001c98; -rom_chip_i2c_writeReg = 0x40001c9c; -rom_i2c_writeReg = 0x40001ca0; -rom_i2c_readReg_Mask = 0x40001ca4; -rom_i2c_writeReg_Mask = 0x40001ca8; -/* Data (.data, .bss, .rodata) */ -phy_param_rom = 0x3fcdfe4c; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld deleted file mode 100644 index d7374c7510..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.libgcc.ld +++ /dev/null @@ -1,112 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group libgcc - ***************************************/ - -/* Functions */ -__absvdi2 = 0x40000998; -__absvsi2 = 0x4000099c; -__adddf3 = 0x400009a0; -__addsf3 = 0x400009a4; -__addvdi3 = 0x400009a8; -__addvsi3 = 0x400009ac; -__ashldi3 = 0x400009b0; -__ashrdi3 = 0x400009b4; -__bswapdi2 = 0x400009b8; -__bswapsi2 = 0x400009bc; -__clear_cache = 0x400009c0; -__clrsbdi2 = 0x400009c4; -__clrsbsi2 = 0x400009c8; -__clzdi2 = 0x400009cc; -__clzsi2 = 0x400009d0; -__cmpdi2 = 0x400009d4; -__ctzdi2 = 0x400009d8; -__ctzsi2 = 0x400009dc; -__divdc3 = 0x400009e0; -__divdf3 = 0x400009e4; -__divdi3 = 0x400009e8; -__divsc3 = 0x400009ec; -__divsf3 = 0x400009f0; -__divsi3 = 0x400009f4; -__eqdf2 = 0x400009f8; -__eqsf2 = 0x400009fc; -__extendsfdf2 = 0x40000a00; -__ffsdi2 = 0x40000a04; -__ffssi2 = 0x40000a08; -__fixdfdi = 0x40000a0c; -__fixdfsi = 0x40000a10; -__fixsfdi = 0x40000a14; -__fixsfsi = 0x40000a18; -__fixunsdfsi = 0x40000a1c; -__fixunssfdi = 0x40000a20; -__fixunssfsi = 0x40000a24; -__floatdidf = 0x40000a28; -__floatdisf = 0x40000a2c; -__floatsidf = 0x40000a30; -__floatsisf = 0x40000a34; -__floatundidf = 0x40000a38; -__floatundisf = 0x40000a3c; -__floatunsidf = 0x40000a40; -__floatunsisf = 0x40000a44; -__gcc_bcmp = 0x40000a48; -__gedf2 = 0x40000a4c; -__gesf2 = 0x40000a50; -__gtdf2 = 0x40000a54; -__gtsf2 = 0x40000a58; -__ledf2 = 0x40000a5c; -__lesf2 = 0x40000a60; -__lshrdi3 = 0x40000a64; -__ltdf2 = 0x40000a68; -__ltsf2 = 0x40000a6c; -__moddi3 = 0x40000a70; -__modsi3 = 0x40000a74; -__muldc3 = 0x40000a78; -__muldf3 = 0x40000a7c; -__muldi3 = 0x40000a80; -__mulsc3 = 0x40000a84; -__mulsf3 = 0x40000a88; -__mulsi3 = 0x40000a8c; -__mulvdi3 = 0x40000a90; -__mulvsi3 = 0x40000a94; -__nedf2 = 0x40000a98; -__negdf2 = 0x40000a9c; -__negdi2 = 0x40000aa0; -__negsf2 = 0x40000aa4; -__negvdi2 = 0x40000aa8; -__negvsi2 = 0x40000aac; -__nesf2 = 0x40000ab0; -__paritysi2 = 0x40000ab4; -__popcountdi2 = 0x40000ab8; -__popcountsi2 = 0x40000abc; -__powidf2 = 0x40000ac0; -__powisf2 = 0x40000ac4; -__subdf3 = 0x40000ac8; -__subsf3 = 0x40000acc; -__subvdi3 = 0x40000ad0; -__subvsi3 = 0x40000ad4; -__truncdfsf2 = 0x40000ad8; -__ucmpdi2 = 0x40000adc; -__udivdi3 = 0x40000ae0; -__udivmoddi4 = 0x40000ae4; -__udivsi3 = 0x40000ae8; -__udiv_w_sdiv = 0x40000aec; -__umoddi3 = 0x40000af0; -__umodsi3 = 0x40000af4; -__unorddf2 = 0x40000af8; -__unordsf2 = 0x40000afc; -__extenddftf2 = 0x40000b00; -__trunctfdf2 = 0x40000b04; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld deleted file mode 100644 index ab7bbb3eab..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib-nano.ld +++ /dev/null @@ -1,47 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib_nano_format - ***************************************/ - -/* Functions */ -__sprint_r = 0x40000684; -_fiprintf_r = 0x40000688; -_fprintf_r = 0x4000068c; -_printf_common = 0x40000690; -_printf_i = 0x40000694; -_vfiprintf_r = 0x40000698; -_vfprintf_r = 0x4000069c; -fiprintf = 0x400006a0; -fprintf = 0x400006a4; -printf = 0x400006a8; -vfiprintf = 0x400006ac; -vfprintf = 0x400006b0; -asprintf = 0x400006b4; -sprintf = 0x400006b8; -snprintf = 0x400006bc; -siprintf = 0x400006c0; -sniprintf = 0x400006c4; -vprintf = 0x400006c8; -viprintf = 0x400006cc; -vsnprintf = 0x400006d0; -vsniprintf = 0x400006d4; -_printf_float = 0x400006d8; -_scanf_float = 0x400006dc; -_scanf_i = 0x400006e0; -_scanf_chars = 0x400006e4; -sscanf = 0x400006e8; -siscanf = 0x400006ec; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld deleted file mode 100644 index 141a85d09f..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.newlib.ld +++ /dev/null @@ -1,143 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.newlib.ld for esp32h4 - * - * - * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum da4c474a48c097d4ac9acad67f70fda6 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group newlib - ***************************************/ - -/* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40000494; -memset = 0x40000498; -memcpy = 0x4000049c; -memmove = 0x400004a0; -memcmp = 0x400004a4; -strcpy = 0x400004a8; -strncpy = 0x400004ac; -strcmp = 0x400004b0; -strncmp = 0x400004b4; -strlen = 0x400004b8; -strstr = 0x400004bc; -bzero = 0x400004c0; -sbrk = 0x400004c8; -isalnum = 0x400004cc; -isalpha = 0x400004d0; -isascii = 0x400004d4; -isblank = 0x400004d8; -iscntrl = 0x400004dc; -isdigit = 0x400004e0; -islower = 0x400004e4; -isgraph = 0x400004e8; -isprint = 0x400004ec; -ispunct = 0x400004f0; -isspace = 0x400004f4; -isupper = 0x400004f8; -toupper = 0x400004fc; -tolower = 0x40000500; -toascii = 0x40000504; -memccpy = 0x40000508; -memchr = 0x4000050c; -memrchr = 0x40000510; -strcasecmp = 0x40000514; -strcasestr = 0x40000518; -strcat = 0x4000051c; -strdup = 0x40000520; -strchr = 0x40000524; -strcspn = 0x40000528; -strcoll = 0x4000052c; -strlcat = 0x40000530; -strlcpy = 0x40000534; -strlwr = 0x40000538; -strncasecmp = 0x4000053c; -strncat = 0x40000540; -strndup = 0x40000544; -strnlen = 0x40000548; -strrchr = 0x4000054c; -strsep = 0x40000550; -strspn = 0x40000554; -strtok_r = 0x40000558; -strupr = 0x4000055c; -longjmp = 0x40000560; -setjmp = 0x40000564; -abs = 0x40000568; -div = 0x4000056c; -labs = 0x40000570; -ldiv = 0x40000574; -qsort = 0x40000578; -rand_r = 0x4000057c; -rand = 0x40000580; -srand = 0x40000584; -utoa = 0x40000588; -itoa = 0x4000058c; -atoi = 0x40000590; -atol = 0x40000594; -strtol = 0x40000598; -strtoul = 0x4000059c; -fflush = 0x400005a0; -_fflush_r = 0x400005a4; -_fwalk = 0x400005a8; -_fwalk_reent = 0x400005ac; -__swbuf_r = 0x400005b8; -__swbuf = 0x400005bc; -_strtod_l = 0x400005c4; -_strtod_r = 0x400005c8; -strtod_l = 0x400005cc; -strtod = 0x400005d0; -strtof_l = 0x400005d4; -strtof = 0x400005d8; -_strtol_r = 0x400005dc; -strtol_l = 0x400005e0; -_strtoul_r = 0x400005e4; -strtoul_l = 0x400005e8; -__match = 0x400005ec; -__hexnan = 0x400005f0; -__hexdig_fun = 0x400005f4; -__gethex = 0x400005f8; -_Balloc = 0x400005fc; -_Bfree = 0x40000600; -__multadd = 0x40000604; -__s2b = 0x40000608; -__hi0bits = 0x4000060c; -__lo0bits = 0x40000610; -__i2b = 0x40000614; -__multiply = 0x40000618; -__pow5mult = 0x4000061c; -__lshift = 0x40000620; -__mcmp = 0x40000624; -__mdiff = 0x40000628; -__ulp = 0x4000062c; -__b2d = 0x40000630; -__d2b = 0x40000634; -__ratio = 0x40000638; -_mprec_log10 = 0x4000063c; -__copybits = 0x40000640; -__any_on = 0x40000644; -asctime = 0x40000648; -asctime_r = 0x4000064c; -atof = 0x40000650; -atoff = 0x40000654; -_dtoa_r = 0x40000658; -_wctomb_r = 0x4000065c; -__ascii_wctomb = 0x40000660; -_mbtowc_r = 0x40000664; -__ascii_mbtowc = 0x40000668; -puts = 0x4000066c; -putc = 0x40000670; -putchar = 0x40000674; -nan = 0x40000678; -nanf = 0x4000067c; -__errno = 0x40000680; -/* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fcdffd4; -_global_impure_ptr = 0x3fcdffd0; diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld deleted file mode 100644 index fbe937c345..0000000000 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.version.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM version variables for esp32h4 - * - * These addresses should be compatible with any ROM version for this chip. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ -_rom_chip_id = 0x40000010; -_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/include/esp32h4/rom/aes.h b/components/esp_rom/include/esp32h4/rom/aes.h deleted file mode 100644 index e593c7b940..0000000000 --- a/components/esp_rom/include/esp32h4/rom/aes.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_AES_H_ -#define _ROM_AES_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define AES_BLOCK_SIZE 16 - -enum AES_TYPE { - AES_ENC, - AES_DEC, -}; - -enum AES_BITS { - AES128, - AES192, - AES256 -}; - -void ets_aes_enable(void); - -void ets_aes_disable(void); - -int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); - -int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); - -int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); - -void ets_aes_block(const void *input, void *output); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_AES_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/apb_backup_dma.h b/components/esp_rom/include/esp32h4/rom/apb_backup_dma.h deleted file mode 100644 index 14948bbde1..0000000000 --- a/components/esp_rom/include/esp32h4/rom/apb_backup_dma.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void)); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/bigint.h b/components/esp_rom/include/esp32h4/rom/bigint.h deleted file mode 100644 index a25f36a9fd..0000000000 --- a/components/esp_rom/include/esp32h4/rom/bigint.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_BIGINT_H_ -#define _ROM_BIGINT_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void ets_bigint_enable(void); - -void ets_bigint_disable(void); - -int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); - -int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); - -int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); - -void ets_bigint_wait_finish(void); - -int ets_bigint_getz(uint32_t *z, uint32_t len_words); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_BIGINT_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/cache.h b/components/esp_rom/include/esp32h4/rom/cache.h deleted file mode 100644 index 4bf5b854c5..0000000000 --- a/components/esp_rom/include/esp32h4/rom/cache.h +++ /dev/null @@ -1,750 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_CACHE_H_ -#define _ROM_CACHE_H_ - -#include -#include "esp_bit_defs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup cache_apis, cache operation related apis - * @brief cache apis - */ - -/** @addtogroup cache_apis - * @{ - */ -#define MIN_ICACHE_SIZE 16384 -#define MAX_ICACHE_SIZE 16384 -#define MIN_ICACHE_WAYS 8 -#define MAX_ICACHE_WAYS 8 -#define MAX_CACHE_WAYS 8 -#define MIN_CACHE_LINE_SIZE 32 -#define TAG_SIZE 4 -#define MIN_ICACHE_BANK_NUM 1 -#define MAX_ICACHE_BANK_NUM 1 -#define CACHE_MEMORY_BANK_NUM 1 -#define CACHE_MEMORY_IBANK_SIZE 0x4000 - -#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) -#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) -#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) -#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) - -typedef enum { - CACHE_DCACHE = 0, - CACHE_ICACHE0 = 1, - CACHE_ICACHE1 = 2, -} cache_t; - -typedef enum { - CACHE_MEMORY_INVALID = 0, - CACHE_MEMORY_IBANK0 = BIT(0), - CACHE_MEMORY_IBANK1 = BIT(1), - CACHE_MEMORY_IBANK2 = BIT(2), - CACHE_MEMORY_IBANK3 = BIT(3), - CACHE_MEMORY_DBANK0 = BIT(0), - CACHE_MEMORY_DBANK1 = BIT(1), - CACHE_MEMORY_DBANK2 = BIT(2), - CACHE_MEMORY_DBANK3 = BIT(3), -} cache_array_t; - -#define ICACHE_SIZE_16KB CACHE_SIZE_HALF -#define ICACHE_SIZE_32KB CACHE_SIZE_FULL -#define DCACHE_SIZE_32KB CACHE_SIZE_HALF -#define DCACHE_SIZE_64KB CACHE_SIZE_FULL - -typedef enum { - CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ - CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ -} cache_size_t; - -typedef enum { - CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ - CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ -} cache_ways_t; - -typedef enum { - CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ - CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ - CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ -} cache_line_size_t; - -typedef enum { - CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ - CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ -} cache_autoload_order_t; - -#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) - -typedef enum { - CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ - CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ - CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ -} cache_autoload_trigger_t; - -typedef enum { - CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ - CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ -} cache_freeze_mode_t; - -struct cache_mode { - uint32_t cache_size; /*!< cache size in byte */ - uint16_t cache_line_size; /*!< cache line size in byte */ - uint8_t cache_ways; /*!< cache ways, always 4 */ - uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ -}; - -struct icache_tag_item { - uint32_t valid:1; /*!< the tag item is valid or not */ - uint32_t lock:1; /*!< the cache line is locked or not */ - uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ - uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ - uint32_t reserved:14; -}; - -struct autoload_config { - uint8_t order; /*!< autoload step is positive or negative */ - uint8_t trigger; /*!< autoload trigger */ - uint8_t ena0; /*!< autoload region0 enable */ - uint8_t ena1; /*!< autoload region1 enable */ - uint32_t addr0; /*!< autoload region0 start address */ - uint32_t size0; /*!< autoload region0 size */ - uint32_t addr1; /*!< autoload region1 start address */ - uint32_t size1; /*!< autoload region1 size */ -}; - -struct tag_group_info { - struct cache_mode mode; /*!< cache and cache mode */ - uint32_t filter_addr; /*!< the address that used to generate the struct */ - uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ - uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ - uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ -}; - -struct lock_config { - uint32_t addr; /*!< manual lock address*/ - uint16_t size; /*!< manual lock size*/ - uint16_t group; /*!< manual lock group, 0 or 1*/ -}; - -struct cache_internal_stub_table { - uint32_t (* icache_line_size)(void); - uint32_t (* icache_addr)(uint32_t addr); - uint32_t (* dcache_addr)(uint32_t addr); - void (* invalidate_icache_items)(uint32_t addr, uint32_t items); - void (* lock_icache_items)(uint32_t addr, uint32_t items); - void (* unlock_icache_items)(uint32_t addr, uint32_t items); - uint32_t (* suspend_icache_autoload)(void); - void (* resume_icache_autoload)(uint32_t autoload); - void (* freeze_icache_enable)(cache_freeze_mode_t mode); - void (* freeze_icache_disable)(void); - int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); -}; - -/* Defined in the interface file, default value is rom_default_cache_internal_table */ -extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; - -typedef void (* cache_op_start)(void); -typedef void (* cache_op_end)(void); - -typedef struct { - cache_op_start start; - cache_op_end end; -} cache_op_cb_t; - -/* Defined in the interface file, default value is NULL */ -extern const cache_op_cb_t* rom_cache_op_cb; - -#define ESP_ROM_ERR_INVALID_ARG 1 -#define MMU_SET_ADDR_ALIGNED_ERROR 2 -#define MMU_SET_PASE_SIZE_ERROR 3 -#define MMU_SET_VADDR_OUT_RANGE 4 - -#define CACHE_OP_ICACHE_Y 1 -#define CACHE_OP_ICACHE_N 0 - -/** - * @brief Initialise cache mmu, mark all entries as invalid. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_MMU_Init(void); - -/** - * @brief Set ICache mmu mapping. - * Please do not call this function in your SDK application. - * - * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In - * esp32h4, external memory is always flash - * - * @param uint32_t vaddr : virtual address in CPU address space. - * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. - * Should be aligned by psize. - * - * @param uint32_t paddr : physical address in external memory. - * Should be aligned by psize. - * - * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. - * - * @param uint32_t num : pages to be set. - * - * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. - * - * @return uint32_t: error status - * 0 : mmu set success - * 2 : vaddr or paddr is not aligned - * 3 : psize error - * 4 : vaddr is out of range - */ -int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); - -/** - * @brief Set DCache mmu mapping. - * Please do not call this function in your SDK application. - * - * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In - * esp32h4, external memory is always flash - * - * @param uint32_t vaddr : virtual address in CPU address space. - * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. - * Should be aligned by psize. - * - * @param uint32_t paddr : physical address in external memory. - * Should be aligned by psize. - * - * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. - * - * @param uint32_t num : pages to be set. - - * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. - * - * @return uint32_t: error status - * 0 : mmu set success - * 2 : vaddr or paddr is not aligned - * 3 : psize error - * 4 : vaddr is out of range - */ -int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); - -/** - * @brief Count the pages in the bus room address which map to Flash. - * Please do not call this function in your SDK application. - * - * @param uint32_t bus : the bus to count with. - * - * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. - * - * return uint32_t : the number of pages which map to Flash. - */ -uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); - -/** - * @brief allocate memory to used by ICache. - * Please do not call this function in your SDK application. - * - * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0 - * - * return none - */ -void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); - -/** - * @brief Get cache mode of ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field - * - * return none - */ -void Cache_Get_Mode(struct cache_mode * mode); - -/** - * @brief Init Cache for ROM boot, including resetting the Icache, initializing Owner, MMU, setting ICache mode, Enabling ICache, unmasking bus. - * - * @param None - * - * @return None - */ -void ROM_Boot_Cache_Init(void); - -/** - * @brief Init mmu owner register to make i/d cache use half mmu entries. - * - * @param None - * - * @return None - */ -void Cache_Owner_Init(void); - -/** - * @brief Invalidate the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to invalidate - * - * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Invalidate the Cache items in the region from ICache or DCache. - * If the region is not in Cache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : invalidated region start address. - * - * @param uint32_t size : invalidated region size. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Invalidate all cache items in ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Invalidate_ICache_All(void); - -/** - * @brief Mask all buses through ICache and DCache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Mask_All(void); - -/** - * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : 0 for ICache not auto preload before suspend. - */ -uint32_t Cache_Suspend_ICache_Autoload(void); - -/** - * @brief Resume ICache auto preload operation after some ICache operations. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : 0 for ICache not auto preload before suspend. - * - * @return None. - */ -void Cache_Resume_ICache_Autoload(uint32_t autoload); - -/** - * @brief Start an ICache manual preload, will suspend auto preload of ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of the preload region. - * - * @param uint32_t size : size of the preload region, should not exceed the size of ICache. - * - * @param uint32_t order : the preload order, 0 for positive, other for negative - * - * @return uint32_t : 0 for ICache not auto preload before manual preload. - */ -uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); - -/** - * @brief Return if the ICache manual preload done. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : 0 for ICache manual preload not done. - */ -uint32_t Cache_ICache_Preload_Done(void); - -/** - * @brief End the ICache manual preload to resume auto preload of ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. - * - * @return None - */ -void Cache_End_ICache_Preload(uint32_t autoload); - -/** - * @brief Config autoload parameters of ICache. - * Please do not call this function in your SDK application. - * - * @param struct autoload_config * config : autoload parameters. - * - * @return None - */ -void Cache_Config_ICache_Autoload(const struct autoload_config * config); - -/** - * @brief Enable auto preload for ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Enable_ICache_Autoload(void); - -/** - * @brief Disable auto preload for ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Disable_ICache_Autoload(void); - -/** - * @brief Config a group of prelock parameters of ICache. - * Please do not call this function in your SDK application. - * - * @param struct lock_config * config : a group of lock parameters. - * - * @return None - */ - -void Cache_Enable_ICache_PreLock(const struct lock_config *config); - -/** - * @brief Disable a group of prelock parameters for ICache. - * However, the locked data will not be released. - * Please do not call this function in your SDK application. - * - * @param uint16_t group : 0 for group0, 1 for group1. - * - * @return None - */ -void Cache_Disable_ICache_PreLock(uint16_t group); - -/** - * @brief Lock the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to lock - * - * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Unlock the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to unlock - * - * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Lock the cache items in tag memory for ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of lock region. - * - * @param uint32_t size : size of lock region. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Lock_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Unlock the cache items in tag memory for ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of unlock region. - * - * @param uint32_t size : size of unlock region. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Unlock_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Disable ICache access for the cpu. - * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. - * Please do not call this function in your SDK application. - * - * @return uint32_t : auto preload enabled before - */ -uint32_t Cache_Disable_ICache(void); - -/** - * @brief Enable ICache access for the cpu. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : ICache will preload then. - * - * @return None - */ -void Cache_Enable_ICache(uint32_t autoload); - -/** - * @brief Suspend ICache access for the cpu. - * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. - * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : auto preload enabled before - */ -uint32_t Cache_Suspend_ICache(void); - -/** - * @brief Resume ICache access for the cpu. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : ICache will preload then. - * - * @return None - */ -void Cache_Resume_ICache(uint32_t autoload); - -/** - * @brief Get ICache cache line size - * - * @param None - * - * @return uint32_t: 16, 32, 64 Byte - */ -uint32_t Cache_Get_ICache_Line_Size(void); - -/** - * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. - * - * @param None - * - * @return None - */ -void Cache_Set_Default_Mode(void); - -/** - * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. - * - * @param None - * - * @return None - */ -void Cache_Enable_Defalut_ICache_Mode(void); - -/** - * @brief Enable freeze for ICache. - * Any miss request will be rejected, including cpu miss and preload/autoload miss. - * Please do not call this function in your SDK application. - * - * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit - * - * @return None - */ -void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); - -/** - * @brief Disable freeze for ICache. - * Please do not call this function in your SDK application. - * - * @return None - */ -void Cache_Freeze_ICache_Disable(void); - -/** - * @brief Travel tag memory to run a call back function. - * ICache and DCache are suspend when doing this. - * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the cache to check and the cache mode. - * - * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. - * 0 for do not filter, all cache lines will be returned. - * - * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. - * - * @return None - */ -void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); - -/** - * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. - * - * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. - * - * @param uint32_t addr_offset : the virtual address offset of the cache ways. - * - * @return uint32_t : the virtual address. - */ -uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); - -/** - * @brief Get cache memory block base address. - * Please do not call this function in your SDK application. - * - * @param uint32_t icache : 0 for dcache, other for icache. - * - * @param uint32_t bank_no : 0 ~ 3 bank. - * - * @return uint32_t : the cache memory block base address, 0 if the block not used. - */ -uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no); - -/** - * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. - * Please do not call this function in your SDK application. - * - * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. - * - * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. - * - * @param uint32_t addr_offset : the virtual address offset of the cache ways. - * - * @return uint32_t : the virtual address. - */ -uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); - -/** - * @brief Get the cache memory value by DRAM address. - * Please do not call this function in your SDK application. - * - * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. - * - * @return uint32_t : the word value of the address. - */ -uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); -/** - * @} - */ - -/** - * @brief Get the cache MMU IROM end address. - * Please do not call this function in your SDK application. - * - * @param void - * - * @return uint32_t : the word value of the address. - */ -uint32_t Cache_Get_IROM_MMU_End(void); - -/** - * @brief Get the cache MMU DROM end address. - * Please do not call this function in your SDK application. - * - * @param void - * - * @return uint32_t : the word value of the address. - */ -uint32_t Cache_Get_DROM_MMU_End(void); - -/** - * @brief Configure cache MMU page size according to instruction and rodata size - * - * @param irom_size The instruction cache MMU page size - * @param drom_size The rodata data cache MMU page size - */ -void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); - -/** - * @brief Lock the permission control section configuration. After lock, any - * configuration modification will be bypass. Digital reset will clear the lock! - * Please do not call this function in your SDK application. - * - * @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms - * - * @return None - */ -void Cache_Pms_Lock(int ibus); - -/** - * @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2. - * Please do not call this function in your SDK application. - * - * @param uint32_t ibus_boundary0_addr : vaddress for split line0 - * - * @param uint32_t ibus_boundary1_addr : vaddress for split line1 - * - * @param uint32_t ibus_boundary2_addr : vaddress for split line2 - * - * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success - */ -int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr); - -/** - * @brief Set three ibus pms attribute, which will determine pms in different section and world. - * Please do not call this function in your SDK application. - * - * @param uint32_t ibus_pms_sct2_attr : attr for section2 - * - * @param uint32_t ibus_pms_sct1_attr : attr for section1 - * - * @return None - */ -void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr); - -/** - * @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2. - * Please do not call this function in your SDK application. - * - * @param uint32_t dbus_boundary0_addr : vaddress for split line0 - * - * @param uint32_t dbus_boundary1_addr : vaddress for split line1 - * - * @param uint32_t dbus_boundary2_addr : vaddress for split line2 - * - * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success - */ -int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr); - -/** - * @brief Set three dbus pms attribute, which will determine pms in different section and world. - * Please do not call this function in your SDK application. - * - * @param uint32_t dbus_pms_sct2_attr : attr for section2 - * - * @param uint32_t dbus_pms_sct1_attr : attr for section1 - * - * @return None - */ -void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_CACHE_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/crc.h b/components/esp_rom/include/esp32h4/rom/crc.h deleted file mode 100644 index a651ce2db6..0000000000 --- a/components/esp_rom/include/esp32h4/rom/crc.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ROM_CRC_H -#define ROM_CRC_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup crc_apis, uart configuration and communication related apis - * @brief crc apis - */ - -/** @addtogroup crc_apis - * @{ - */ - - -/* Standard CRC8/16/32 algorithms. */ -// CRC-8 x8+x2+x1+1 0x07 -// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS -// CRC32: -//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 -//If your buf is not continuous, you can use the first result to be the second parameter. - -/** - * @brief Crc32 value that is in little endian. - * - * @param uint32_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc32 value that is in big endian. - * - * @param uint32_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc16 value that is in little endian. - * - * @param uint16_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc16 value that is in big endian. - * - * @param uint16_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc8 value that is in little endian. - * - * @param uint8_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); - -/** - * @brief Crc8 value that is in big endian. - * - * @param uint32_t crc : init crc value, use 0 at the first use. - * - * @param uint8_t const *buf : buffer to start calculate crc. - * - * @param uint32_t len : buffer length in byte. - * - * @return None - */ -uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/components/esp_rom/include/esp32h4/rom/digital_signature.h b/components/esp_rom/include/esp32h4/rom/digital_signature.h deleted file mode 100644 index 3b8ad1a376..0000000000 --- a/components/esp_rom/include/esp32h4/rom/digital_signature.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#define ETS_DS_MAX_BITS 3072 - -#define ETS_DS_IV_LEN 16 - -/* Length of parameter 'C' stored in flash (not including IV) - - Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8) - - Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware -*/ -#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8) - -/* Encrypted ETS data. Recommended to store in flash in this format. - */ -typedef struct { - /* RSA LENGTH register parameters - * (number of words in RSA key & operands, minus one). - * - * - * This value must match the length field encrypted and stored in 'c', - * or invalid results will be returned. (The DS peripheral will - * always use the value in 'c', not this value, so an attacker can't - * alter the DS peripheral results this way, it will just truncate or - * extend the message and the resulting signature in software.) - */ - unsigned rsa_length; - - /* IV value used to encrypt 'c' */ - uint8_t iv[ETS_DS_IV_LEN]; - - /* Encrypted Digital Signature parameters. Result of AES-CBC encryption - of plaintext values. Includes an encrypted message digest. - */ - uint8_t c[ETS_DS_C_LEN]; -} ets_ds_data_t; - -typedef enum { - ETS_DS_OK, - ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ - ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ - ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ - ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ -} ets_ds_result_t; - -void ets_ds_enable(void); - -void ets_ds_disable(void); - - -/* - * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral - * - * - @param message Pointer to message (or padded digest) containing the message to sign. Should be - * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data - * in flash. - * - * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling - * this function, and is responsible for calling ets_ds_finish_sign() and then - * ets_hmac_invalidate_downstream() afterwards. - * - * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, - * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. - */ -ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); - - -/* - * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() - * - * A result of false indicates that a call to ets_ds_finish_sign() will not block. - * - * Only valid if ets_ds_enable() has been called. - */ -bool ets_ds_is_busy(void); - - -/* @brief Finish signing a message using the Digital Signature peripheral - * - * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until - * peripheral is no longer busy. - * - * - @param signature Pointer to buffer to contain the signature. Should be - * (data->rsa_length + 1)*4 bytes long. - * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() - * - * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, - * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the - * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a - * digest is produced anyhow.) - */ -ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); - - -/* Plaintext parameters used by Digital Signature. - - Not used for signing with DS peripheral, but can be encrypted - in-device by calling ets_ds_encrypt_params() -*/ -typedef struct { - uint32_t Y[ETS_DS_MAX_BITS / 32]; - uint32_t M[ETS_DS_MAX_BITS / 32]; - uint32_t Rb[ETS_DS_MAX_BITS / 32]; - uint32_t M_prime; - uint32_t length; -} ets_ds_p_data_t; - -typedef enum { - ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ - ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ -} ets_ds_key_t; - -/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral - * - * @param data Output buffer to store encrypted data, suitable for later use generating signatures. - * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. - * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. - * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. - * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) - * - * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. - */ -ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); - - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/efuse.h b/components/esp_rom/include/esp32h4/rom/efuse.h deleted file mode 100644 index 5117ffadf3..0000000000 --- a/components/esp_rom/include/esp32h4/rom/efuse.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_EFUSE_H_ -#define _ROM_EFUSE_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** \defgroup efuse_APIs efuse APIs - * @brief ESP32 efuse read/write APIs - * @attention - * - */ - -/** @addtogroup efuse_APIs - * @{ - */ - -typedef enum { - ETS_EFUSE_KEY_PURPOSE_USER = 0, - ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, - ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, - ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, - ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, - ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, - ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, - ETS_EFUSE_KEY_PURPOSE_MAX, -} ets_efuse_purpose_t; - -typedef enum { - ETS_EFUSE_BLOCK0 = 0, - ETS_EFUSE_MAC_SPI_SYS_0 = 1, - ETS_EFUSE_BLOCK_SYS_DATA = 2, - ETS_EFUSE_BLOCK_USR_DATA = 3, - ETS_EFUSE_BLOCK_KEY0 = 4, - ETS_EFUSE_BLOCK_KEY1 = 5, - ETS_EFUSE_BLOCK_KEY2 = 6, - ETS_EFUSE_BLOCK_KEY3 = 7, - ETS_EFUSE_BLOCK_KEY4 = 8, - ETS_EFUSE_BLOCK_KEY5 = 9, - ETS_EFUSE_BLOCK_KEY6 = 10, - ETS_EFUSE_BLOCK_MAX, -} ets_efuse_block_t; - -/** - * @brief set timing accroding the apb clock, so no read error or write error happens. - * - * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. - * - * @return : 0 if success, others if clock not accepted - */ -int ets_efuse_set_timing(uint32_t clock); - -/** - * @brief Efuse read operation: copies data from physical efuses to efuse read registers. - * - * @param null - * - * @return : 0 if success, others if apb clock is not accepted - */ -int ets_efuse_read(void); - -/** - * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. - * - * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. - * - * @return : 0 if success, others if apb clock is not accepted - */ -int ets_efuse_program(ets_efuse_block_t block); - -/** - * @brief Set all Efuse program registers to zero. - * - * Call this before writing new data to the program registers. - */ -void ets_efuse_clear_program_registers(void); - -/** - * @brief Program a block of key data to an efuse block - * - * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). - * @param purpose Purpose to set for this key. Purpose must be already unset. - * @param data Pointer to data to write. - * @param data_len Length of data to write. - * - * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) - */ -int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); - - -/* @brief Return the address of a particular efuse block's first read register - * - * @param block Index of efuse block to look up - * - * @return 0 if block is invalid, otherwise a numeric read register address - * of the first word in the block. - */ -uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); - -/** - * @brief Return the current purpose set for an efuse key block - * - * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. - */ -ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); - -/** - * @brief Find a key block with the particular purpose set - * - * @param purpose Purpose to search for. - * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. - * @return true if found, false if not found. If false, value at key_block pointer is unchanged. - */ -bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); - -/** - * Return true if the key block is unused, false otherwise. - * - * An unused key block is all zero content, not read or write protected, - * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) - * - * @param key_block key block to check. - * - * @return true if key block is unused, false if key block or used - * or the specified block index is not a key block. - */ -bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); - - -/** - * @brief Search for an unused key block and return the first one found. - * - * See @ref ets_efuse_key_block_unused for a description of an unused key block. - * - * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. - */ -ets_efuse_block_t ets_efuse_find_unused_key_block(void); - -/** - * @brief Return the number of unused efuse key blocks (0-6) - */ -unsigned ets_efuse_count_unused_key_blocks(void); - -/** - * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. - * - * @param data Pointer to data buffer (length 32 bytes) - * @param rs_values Pointer to write encoded data to (length 12 bytes) - */ -void ets_efuse_rs_calculate(const void *data, void *rs_values); - -/** - * @brief Read spi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - 1 for default HSPI pins. - * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, - * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. - * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. - */ -uint32_t ets_efuse_get_spiconfig(void); - -/** - * @brief Read spi flash wp pad from Efuse - * - * @return - * - 0x3f for invalid. - * - 0~46 is valid. - */ -uint32_t ets_efuse_get_wp_pad(void); - -/** - * @brief Read if download mode disabled from Efuse - * - * @return - * - true for efuse disable download mode. - * - false for efuse doesn't disable download mode. - */ -bool ets_efuse_download_modes_disabled(void); - -/** - * @brief Read if uart print control value from Efuse - * - * @return - * - 0 for uart force print. - * - 1 for uart print when GPIO8 is low when digital reset. - * 2 for uart print when GPIO8 is high when digital reset. - * 3 for uart force slient - */ -uint32_t ets_efuse_get_uart_print_control(void); - -/** - * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse - * - * @return - * - 1 for efuse disable USB-Serial-JTAG print during rom boot. - * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. - */ -uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); - -/** - * @brief Read if usb download mode disabled from Efuse - * - * (Also returns true if security download mode is enabled, as this mode - * disables USB download.) - * - * @return - * - true for efuse disable usb download mode. - * - false for efuse doesn't disable usb download mode. - */ -bool ets_efuse_usb_download_mode_disabled(void); - - -/** - * @brief Read if usb module disabled from Efuse - * - * @return - * - true for efuse disable usb module. - * - false for efuse doesn't disable usb module. - */ -bool ets_efuse_usb_module_disabled(void); - -/** - * @brief Read if security download modes enabled from Efuse - * - * @return - * - true for efuse enable security download mode. - * - false for efuse doesn't enable security download mode. - */ -bool ets_efuse_security_download_modes_enabled(void); - -/** - * @brief Return true if secure boot is enabled in EFuse - */ -bool ets_efuse_secure_boot_enabled(void); - -/** - * @brief Return true if secure boot aggressive revoke is enabled in EFuse - */ -bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); - -/** - * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse - */ -bool ets_efuse_cache_encryption_enabled(void); - -/** - * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU - */ -bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); - -/** - * @brief Return true if EFuse indicates to send a flash resume command. - */ -bool ets_efuse_force_send_resume(void); - -/** - * @brief return the time in us ROM boot need wait flash to power on from Efuse - * - * @return - * - uint32_t the time in us. - */ -uint32_t ets_efuse_get_flash_delay_us(void); - -#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 -#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 - -#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 -#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) - -#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 -#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) - -#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 -#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) - -#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 -#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) - - -#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 -#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) - -/** - * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into - * the JTAG_CTRL registers. - * - * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. - * - * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. - * - * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. - * @param key_block Index of a key block containing the source for this key. - * - * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. - */ -int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); - -/** - * @brief A crc8 algorithm used for MAC addresses in efuse - * - * @param unsigned char const *p : Pointer to original data. - * - * @param unsigned int len : Data length in byte. - * - * @return unsigned char: Crc value. - */ -unsigned char esp_crc8(unsigned char const *p, unsigned int len); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_EFUSE_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/esp_flash.h b/components/esp_rom/include/esp32h4/rom/esp_flash.h deleted file mode 100644 index 85b4ae8755..0000000000 --- a/components/esp_rom/include/esp32h4/rom/esp_flash.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "esp_err.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function - just adds ROM-specific parts -*/ - -struct spi_flash_chip_t; -typedef struct esp_flash_t esp_flash_t; - -/* Structure to wrap "global" data used by esp_flash in ROM */ -typedef struct { - /* Default SPI flash chip, ie main chip attached to the MCU - This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL - */ - esp_flash_t *default_chip; - - /* Global API OS notification start/end/chip_check functions - - These are used by ROM if no other host functions are configured. - */ - struct { - esp_err_t (*start)(esp_flash_t *chip); - esp_err_t (*end)(esp_flash_t *chip, esp_err_t err); - esp_err_t (*chip_check)(esp_flash_t **inout_chip); - } api_funcs; -} esp_flash_rom_global_data_t; - -/** Access a pointer to the global data used by the ROM spi_flash driver - */ -esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/ets_sys.h b/components/esp_rom/include/esp32h4/rom/ets_sys.h deleted file mode 100644 index 91544de628..0000000000 --- a/components/esp_rom/include/esp32h4/rom/ets_sys.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_ETS_SYS_H_ -#define _ROM_ETS_SYS_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup ets_sys_apis, ets system related apis - * @brief ets system apis - */ - -/** @addtogroup ets_sys_apis - * @{ - */ - -/************************************************************************ - * NOTE - * Many functions in this header files can't be run in FreeRTOS. - * Please see the comment of the Functions. - * There are also some functions that doesn't work on FreeRTOS - * without listed in the header, such as: - * xtos functions start with "_xtos_" in ld file. - * - *********************************************************************** - */ - -/** \defgroup ets_apis, Espressif Task Scheduler related apis - * @brief ets apis - */ - -/** @addtogroup ets_apis - * @{ - */ - -typedef enum { - ETS_OK = 0, /**< return successful in ets*/ - ETS_FAILED = 1, /**< return failed in ets*/ - ETS_PENDING = 2, - ETS_BUSY = 3, - ETS_CANCEL = 4, -} ETS_STATUS; - -typedef ETS_STATUS ets_status_t; - -typedef uint32_t ETSSignal; -typedef uint32_t ETSParam; - -typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ - -struct ETSEventTag { - ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ - ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ -}; - -typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ -typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ - - - - - -/** - * @} - */ - -/** \defgroup ets_boot_apis, Boot routing related apis - * @brief ets boot apis - */ - -/** @addtogroup ets_apis - * @{ - */ - -extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ - -/** - * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. - * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the PRO Entry code address value in uint32_t - * - * @return None - */ -void ets_set_user_start(uint32_t start); - - -/** - * @} - */ - -/** \defgroup ets_printf_apis, ets_printf related apis used in ets - * @brief ets printf apis - */ - -/** @addtogroup ets_printf_apis - * @{ - */ - -/** - * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. - * Can not print float point data format, or longlong data format. - * So we maybe only use this in ROM. - * - * @param const char *fmt : See printf. - * - * @param ... : See printf. - * - * @return int : the length printed to the output device. - */ -int ets_printf(const char *fmt, ...); - -/** - * @brief Get the uart channel of ets_printf(uart_tx_one_char). - * - * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). - */ -uint8_t ets_get_printf_channel(void); - -/** - * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. - * Can not print float point data format, or longlong data format - * - * @param char c : char to output. - * - * @return None - */ -void ets_write_char_uart(char c); - -/** - * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. - * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. - * - * @param void (*)(char) p: Output function to install. - * - * @return None - */ -void ets_install_putc1(void (*p)(char c)); - -/** - * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. - * To install putc2, which is defaulted installed as NULL. - * - * @param void (*)(char) p: Output function to install. - * - * @return None - */ -void ets_install_putc2(void (*p)(char c)); - -/** - * @brief Install putc1 as ets_write_char_uart. - * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. - * - * @param None - * - * @return None - */ -void ets_install_uart_printf(void); - -#define ETS_PRINTF(...) ets_printf(...) - -#define ETS_ASSERT(v) do { \ - if (!(v)) { \ - ets_printf("%s %u \n", __FILE__, __LINE__); \ - while (1) {}; \ - } \ -} while (0); - -/** - * @} - */ - -/** \defgroup ets_timer_apis, ets_timer related apis used in ets - * @brief ets timer apis - */ - -/** @addtogroup ets_timer_apis - * @{ - */ -typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ - -typedef struct _ETSTIMER_ { - struct _ETSTIMER_ *timer_next; /**< timer linker*/ - uint32_t timer_expire; /**< abstruct time when timer expire*/ - uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ - ETSTimerFunc *timer_func; /**< timer handler*/ - void *timer_arg; /**< timer handler argument*/ -} ETSTimer; - -/** - * @brief Init ets timer, this timer range is 640 us to 429496 ms - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_timer_init(void); - -/** - * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_timer_deinit(void); - -/** - * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. - * - * @param bool repeat : Timer is periodic repeated. - * - * @return None - */ -void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); - -/** - * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. - * - * @param bool repeat : Timer is periodic repeated. - * - * @return None - */ -void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); - -/** - * @brief Disarm an ets timer. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @return None - */ -void ets_timer_disarm(ETSTimer *timer); - -/** - * @brief Set timer callback and argument. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @param ETSTimerFunc *pfunction : Timer callback. - * - * @param void *parg : Timer callback argument. - * - * @return None - */ -void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); - -/** - * @brief Unset timer callback and argument to NULL. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param ETSTimer *timer : Timer struct pointer. - * - * @return None - */ -void ets_timer_done(ETSTimer *ptimer); - -/** - * @brief CPU do while loop for some time. - * In FreeRTOS task, please call FreeRTOS apis. - * - * @param uint32_t us : Delay time in us. - * - * @return None - */ -void ets_delay_us(uint32_t us); - -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * Call this function when CPU frequency is changed. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency(uint32_t ticks_per_us); - - - -/** - * @brief Get the real CPU ticks per us to the ets. - * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. - * - * @param None - * - * @return uint32_t : CPU ticks per us record in ets. - */ -uint32_t ets_get_cpu_frequency(void); - -/** - * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if stored in efuse(not 0) - * clock = ets_efuse_get_xtal_freq() * 1000000; - * else if analog_8M in efuse - * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); - * else clock = 40M. - */ -uint32_t ets_get_xtal_freq(void); - -/** - * @brief Get the apb divior by xtal frequency. - * When any types of reset happen, the default value is 2. - * - * @param None - * - * @return uint32_t : 1 or 2. - */ -uint32_t ets_get_xtal_div(void); - -/** - * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. - * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; - * else store ets_get_detected_xtal_freq() in. - */ -uint32_t ets_get_apb_freq(void); - -/** - * @} - */ - -/** \defgroup ets_intr_apis, ets interrupt configure related apis - * @brief ets intr apis - */ - -/** @addtogroup ets_intr_apis - * @{ - */ - -typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ - -/** - * @brief Attach a interrupt handler to a CPU interrupt number. - * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param int i : CPU interrupt number. - * - * @param ets_isr_t func : Interrupt handler. - * - * @param void *arg : argument of the handler. - * - * @return None - */ -void ets_isr_attach(int i, ets_isr_t func, void *arg); - -/** - * @brief Mask the interrupts which show in mask bits. - * This function equals to _xtos_ints_off(mask). - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. - * - * @return None - */ -void ets_isr_mask(uint32_t mask); - -/** - * @brief Unmask the interrupts which show in mask bits. - * This function equals to _xtos_ints_on(mask). - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. - * - * @return None - */ -void ets_isr_unmask(uint32_t unmask); - -/** - * @brief Lock the interrupt to level 2. - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_intr_lock(void); - -/** - * @brief Unlock the interrupt to level 0. - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_intr_unlock(void); - -/** - * @brief Attach an CPU interrupt to a hardware source. - * We have 4 steps to use an interrupt: - * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); - * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); - * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); - * 4.Enable interrupt in the module. - * - * @param int cpu_no : The CPU which the interrupt number belongs. - * - * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. - * - * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. - * - * @return None - */ -void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); - -/** - * @} - */ - -#ifndef MAC2STR -#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] -#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" -#endif - -#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) - -#ifdef ESP_PLATFORM -// Remove in IDF v6.0 (IDF-7044) -typedef enum { - OK = 0, - FAIL, - PENDING, - BUSY, - CANCEL, -} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); -#endif - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_ETS_SYS_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/gpio.h b/components/esp_rom/include/esp32h4/rom/gpio.h deleted file mode 100644 index 3285d6caa7..0000000000 --- a/components/esp_rom/include/esp32h4/rom/gpio.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "soc/gpio_reg.h" -#include "sdkconfig.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup gpio_apis, uart configuration and communication related apis - * @brief gpio apis - */ - -/** @addtogroup gpio_apis - * @{ - */ - -#define GPIO_REG_READ(reg) READ_PERI_REG(reg) -#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) -#define GPIO_ID_PIN0 0 -#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) -#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -#define GPIO_FUNC_IN_HIGH 0x38 -#define GPIO_FUNC_IN_LOW 0x3C -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -#define GPIO_FUNC_IN_HIGH 0x1E -#define GPIO_FUNC_IN_LOW 0x1F -#endif - -#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ - ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) - -#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) - -typedef enum { - GPIO_PIN_INTR_DISABLE = 0, - GPIO_PIN_INTR_POSEDGE = 1, - GPIO_PIN_INTR_NEGEDGE = 2, - GPIO_PIN_INTR_ANYEDGE = 3, - GPIO_PIN_INTR_LOLEVEL = 4, - GPIO_PIN_INTR_HILEVEL = 5 -} GPIO_INT_TYPE; - - -/** - * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). - * There is no particular ordering guaranteed; so if the order of writes is significant, - * calling code should divide a single call into multiple calls. - * - * @param uint32_t set_mask : the gpios that need high level. - * - * @param uint32_t clear_mask : the gpios that need low level. - * - * @param uint32_t enable_mask : the gpios that need be changed. - * - * @param uint32_t disable_mask : the gpios that need diable output. - * - * @return None - */ -void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); - -/** - * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. - * - * @param None - * - * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. - */ -uint32_t gpio_input_get(void); - -/** - * @brief Set GPIO to wakeup the ESP32. - * Please do not call this function in SDK. - * - * @param uint32_t i: gpio number. - * - * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used - * - * @return None - */ -void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); - -/** - * @brief disable GPIOs to wakeup the ESP32. - * Please do not call this function in SDK. - * - * @param None - * - * @return None - */ -void gpio_pin_wakeup_disable(void); - -/** - * @brief set gpio input to a signal, one gpio can input to several signals. - * - * @param uint32_t gpio : gpio number, 0~0x2f - * gpio == 0x3C, input 0 to signal - * gpio == 0x3A, input nothing to signal - * gpio == 0x38, input 1 to signal - * - * @param uint32_t signal_idx : signal index. - * - * @param bool inv : the signal is inv or not - * - * @return None - */ -void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); - -/** - * @brief set signal output to gpio, one signal can output to several gpios. - * - * @param uint32_t gpio : gpio number, 0~0x2f - * - * @param uint32_t signal_idx : signal index. - * signal_idx == 0x100, cancel output put to the gpio - * - * @param bool out_inv : the signal output is invert or not - * - * @param bool oen_inv : the signal output enable is invert or not - * - * @return None - */ -void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); - -/** - * @brief Select pad as a gpio function from IOMUX. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_select_gpio(uint32_t gpio_num); - -/** - * @brief Set pad driver capability. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @param uint32_t drv : 0-3 - * - * @return None - */ -void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); - -/** - * @brief Pull up the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_pullup(uint32_t gpio_num); - -/** - * @brief Pull down the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_pulldown(uint32_t gpio_num); - -/** - * @brief Unhold the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_unhold(uint32_t gpio_num); - -/** - * @brief Hold the pad from gpio number. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_hold(uint32_t gpio_num); - -/** - * @brief enable gpio pad input. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_input_enable(uint32_t gpio_num); - -/** - * @brief disable gpio pad input. - * - * @param uint32_t gpio_num : gpio number, 0~0x2f - * - * @return None - */ -void gpio_pad_input_disable(uint32_t gpio_num); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/hmac.h b/components/esp_rom/include/esp32h4/rom/hmac.h deleted file mode 100644 index 8f110328e9..0000000000 --- a/components/esp_rom/include/esp32h4/rom/hmac.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_HMAC_H_ -#define _ROM_HMAC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "efuse.h" - -void ets_hmac_enable(void); - -void ets_hmac_disable(void); - -/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) - to digest a message. -*/ -int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); - -/* Calculate a downstream HMAC message to temporarily enable JTAG, or - to generate a Digital Signature data decryption key. - - - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE - or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG - - - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. - This efuse block must have the corresponding purpose set in "purpose", or - ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. - - The result of this HMAC calculation is only made available "downstream" to the - corresponding hardware module, and cannot be accessed by software. -*/ -int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); - -/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). - * - * - purpose must match a previous call to ets_hmac_calculate_downstream(). - * - * After this function is called, the corresponding internal operation (JTAG or DS) will no longer - * have access to the generated key. - */ -int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); - -#ifdef __cplusplus -} -#endif - -#endif // _ROM_HMAC_H_ diff --git a/components/esp_rom/include/esp32h4/rom/libc_stubs.h b/components/esp_rom/include/esp32h4/rom/libc_stubs.h deleted file mode 100644 index 0836f39cd9..0000000000 --- a/components/esp_rom/include/esp32h4/rom/libc_stubs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _ROM_LIBC_STUBS_H_ -#define _ROM_LIBC_STUBS_H_ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* -ESP32 ROM code contains implementations of some of C library functions. -Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall -implementation defined in the following struct. - -The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to -set the address - -So, before using any of the C library functions (except for pure functions and memcpy/memset functions), -application must allocate syscall table structure for each CPU being used, and populate it with pointers -to actual implementations of corresponding syscalls. -*/ - -struct syscall_stub_table -{ - struct _reent* (*__getreent)(void); - void* (*_malloc_r)(struct _reent *r, size_t); - void (*_free_r)(struct _reent *r, void*); - void* (*_realloc_r)(struct _reent *r, void*, size_t); - void* (*_calloc_r)(struct _reent *r, size_t, size_t); - void (*_abort)(void); - int (*_system_r)(struct _reent *r, const char*); - int (*_rename_r)(struct _reent *r, const char*, const char*); - clock_t (*_times_r)(struct _reent *r, struct tms *); - int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); - void (*_raise_r)(struct _reent *r); - int (*_unlink_r)(struct _reent *r, const char*); - int (*_link_r)(struct _reent *r, const char*, const char*); - int (*_stat_r)(struct _reent *r, const char*, struct stat *); - int (*_fstat_r)(struct _reent *r, int, struct stat *); - void* (*_sbrk_r)(struct _reent *r, ptrdiff_t); - int (*_getpid_r)(struct _reent *r); - int (*_kill_r)(struct _reent *r, int, int); - void (*_exit_r)(struct _reent *r, int); - int (*_close_r)(struct _reent *r, int); - int (*_open_r)(struct _reent *r, const char *, int, int); - int (*_write_r)(struct _reent *r, int, const void *, int); - int (*_lseek_r)(struct _reent *r, int, int, int); - int (*_read_r)(struct _reent *r, int, void *, int); -#ifdef _RETARGETABLE_LOCKING - void (*_retarget_lock_init)(_LOCK_T *lock); - void (*_retarget_lock_init_recursive)(_LOCK_T *lock); - void (*_retarget_lock_close)(_LOCK_T lock); - void (*_retarget_lock_close_recursive)(_LOCK_T lock); - void (*_retarget_lock_acquire)(_LOCK_T lock); - void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); - int (*_retarget_lock_try_acquire)(_LOCK_T lock); - int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); - void (*_retarget_lock_release)(_LOCK_T lock); - void (*_retarget_lock_release_recursive)(_LOCK_T lock); -#else - void (*_lock_init)(_lock_t *lock); - void (*_lock_init_recursive)(_lock_t *lock); - void (*_lock_close)(_lock_t *lock); - void (*_lock_close_recursive)(_lock_t *lock); - void (*_lock_acquire)(_lock_t *lock); - void (*_lock_acquire_recursive)(_lock_t *lock); - int (*_lock_try_acquire)(_lock_t *lock); - int (*_lock_try_acquire_recursive)(_lock_t *lock); - void (*_lock_release)(_lock_t *lock); - void (*_lock_release_recursive)(_lock_t *lock); -#endif - int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap); - int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); - void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn)); - void (*__sinit) (struct _reent *r); - void (*_cleanup_r) (struct _reent* r); -}; - -extern struct syscall_stub_table *syscall_table_ptr; - -#ifdef __cplusplus -} // extern "C" -#endif - -#endif /* _ROM_LIBC_STUBS_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/lldesc.h b/components/esp_rom/include/esp32h4/rom/lldesc.h deleted file mode 100644 index f2db37edfd..0000000000 --- a/components/esp_rom/include/esp32h4/rom/lldesc.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_LLDESC_H_ -#define _ROM_LLDESC_H_ - -#include - -#include "sys/queue.h" -#include "esp_rom_lldesc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define LLDESC_TX_MBLK_SIZE 268 /* */ -#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ -#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ -#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ -#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ -#ifdef ESP_MAC_5 -#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ -#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ -#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 -#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 -#else -#ifdef SBUF_RXTX -#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ -#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ -#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ -#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ -#endif -#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ - -#ifdef IEEE80211_RX_AMPDU -#define LLDESC_RX_MBLK_NUM 30 -#else -#define LLDESC_RX_MBLK_NUM 10 -#endif /*IEEE80211_RX_AMPDU*/ - -#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 -#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 -#endif /* !ESP_MAC_5 */ - -typedef struct tx_ampdu_entry_s { - uint32_t sub_len : 12, - dili_num : 7, - : 1, - null_byte: 2, - data : 1, - enc : 1, - seq : 8; -} tx_ampdu_entry_t; - -typedef struct lldesc_chain_s { - lldesc_t *head; - lldesc_t *tail; -} lldesc_chain_t; - -#ifdef SBUF_RXTX -enum sbuf_mask_s { - SBUF_MOVE_NO = 0, - SBUF_MOVE_TX2RX, - SBUF_MOVE_RX2TX, -} ; - -#define SBUF_MOVE_STEP 8 -#endif -#define LLDESC_SIZE sizeof(struct lldesc_s) - -/* SLC Descriptor */ -#define LLDESC_OWNER_MASK 0x80000000 -#define LLDESC_OWNER_SHIFT 31 -#define LLDESC_SW_OWNED 0 -#define LLDESC_HW_OWNED 1 - -#define LLDESC_EOF_MASK 0x40000000 -#define LLDESC_EOF_SHIFT 30 - -#define LLDESC_SOSF_MASK 0x20000000 -#define LLDESC_SOSF_SHIFT 29 - -#define LLDESC_LENGTH_MASK 0x00fff000 -#define LLDESC_LENGTH_SHIFT 12 - -#define LLDESC_SIZE_MASK 0x00000fff -#define LLDESC_SIZE_SHIFT 0 - -#define LLDESC_ADDR_MASK 0x000fffff - -static inline uint32_t lldesc_get_chain_length(lldesc_t *head) -{ - lldesc_t *ds = head; - uint32_t len = 0; - - while (ds) { - len += ds->length; - ds = STAILQ_NEXT(ds, qe); - } - - return len; -} - -static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) -{ - ds->owner = owner; - ds->eof = eof; - ds->sosf = sosf; - ds->length = len; -} - -#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \ - (_desc)->owner = (_owner); \ - (_desc)->eof = (_eof); \ - (_desc)->sosf = (_sosf); \ - (_desc)->length = (_len); \ -} while(0) - -#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) - -#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) - -#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_LLDESC_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/md5_hash.h b/components/esp_rom/include/esp32h4/rom/md5_hash.h deleted file mode 100644 index 3c5e10d1bf..0000000000 --- a/components/esp_rom/include/esp32h4/rom/md5_hash.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* - * MD5 internal definitions - * Copyright (c) 2003-2005, Jouni Malinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Alternatively, this software may be distributed under the terms of BSD - * license. - * - * See README and COPYING for more details. - */ - -#ifndef _ROM_MD5_HASH_H_ -#define _ROM_MD5_HASH_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct MD5Context { - uint32_t buf[4]; - uint32_t bits[2]; - uint8_t in[64]; -}; - -void MD5Init(struct MD5Context *context); -void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); -void MD5Final(unsigned char digest[16], struct MD5Context *context); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_MD5_HASH_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/miniz.h b/components/esp_rom/include/esp32h4/rom/miniz.h deleted file mode 100644 index f0baecabdc..0000000000 --- a/components/esp_rom/include/esp32h4/rom/miniz.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead" -#include "../../miniz.h" diff --git a/components/esp_rom/include/esp32h4/rom/rom_layout.h b/components/esp_rom/include/esp32h4/rom/rom_layout.h deleted file mode 100644 index 39d80438af..0000000000 --- a/components/esp_rom/include/esp32h4/rom/rom_layout.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Structure and functions for returning ROM global layout - * - * This is for address symbols defined in the linker script, which may change during ECOs. - */ -typedef struct { - void *dram0_stack_shared_mem_start; - void *dram0_rtos_reserved_start; - void *stack_sentry; - void *stack; - - /* BTDM data */ - void *data_start_btdm; - void *data_end_btdm; - void *bss_start_btdm; - void *bss_end_btdm; - void *data_start_btdm_rom; - void *data_end_btdm_rom; - void *data_start_interface_btdm; - void *data_end_interface_btdm; - void *bss_start_interface_btdm; - void *bss_end_interface_btdm; - - void *dram_start_phyrom; - void *dram_end_phyrom; - - void *dram_start_usbdev_rom; - void *dram_end_usbdev_rom; - void *dram_start_uart_rom; - void *dram_end_uart_rom; - -} ets_rom_layout_t; - -extern const ets_rom_layout_t * const ets_rom_layout_p; - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/rsa_pss.h b/components/esp_rom/include/esp32h4/rom/rsa_pss.h deleted file mode 100644 index 2ee06a8ef0..0000000000 --- a/components/esp_rom/include/esp32h4/rom/rsa_pss.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_RSA_PSS_H_ -#define _ROM_RSA_PSS_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define ETS_SIG_LEN 384 /* Bytes */ -#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ - -typedef struct { - uint8_t n[384]; /* Public key modulus */ - uint32_t e; /* Public key exponent */ - uint8_t rinv[384]; - uint32_t mdash; -} ets_rsa_pubkey_t; - -bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); - -void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); - -bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/components/esp_rom/include/esp32h4/rom/rtc.h b/components/esp_rom/include/esp32h4/rom/rtc.h deleted file mode 100644 index ed529a5e40..0000000000 --- a/components/esp_rom/include/esp32h4/rom/rtc.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "esp_assert.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/reset_reasons.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup rtc_apis, rtc registers and memory related apis - * @brief rtc apis - */ - -/** @addtogroup rtc_apis - * @{ - */ - -/************************************************************************************** - * Note: * - * Some Rtc memory and registers are used, in ROM or in internal library. * - * Please do not use reserved or used rtc memory or registers. * - * * - ************************************************************************************* - * RTC Memory & Store Register usage - ************************************************************************************* - * rtc memory addr type size usage - * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry - * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP - * - * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code - * - ************************************************************************************* - * RTC store registers usage - * RTC_CNTL_STORE0_REG Reserved - * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value - * RTC_CNTL_STORE2_REG Boot time, low word - * RTC_CNTL_STORE3_REG Boot time, high word - * RTC_CNTL_STORE4_REG External XTAL frequency - * RTC_CNTL_STORE5_REG APB bus frequency - * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY - * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC - ************************************************************************************* - */ - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG -#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG -#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG -#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG -#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG -#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG -#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG -#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG - -#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. - -typedef enum { - AWAKE = 0, // -#include -#include "ets_sys.h" -#include "rsa_pss.h" -#include "esp_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; -typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; -typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; - -/* Anti-FI measure: use full words for success/fail, instead of - 0/non-zero -*/ -typedef enum { - SB_SUCCESS = 0x3A5A5AA5, - SB_FAILED = 0x7533885E, -} ets_secure_boot_status_t; - -/* Verify bootloader image (reconfigures cache to map), - with key digests provided as parameters.) - - Can be used to verify secure boot status before enabling - secure boot permanently. - - If stage_load parameter is true, bootloader is copied into staging - buffer in RAM at the same time. - - If result is SB_SUCCESS, the "simple hash" of the bootloader is - copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); - -/* Read key digests from efuse. Any revoked/missing digests will be - marked as NULL -*/ -ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); - -/* Verify supplied signature against supplied digest, using - supplied trusted key digests. - - Doesn't reconfigure cache or any other hardware access except for RSA peripheral. - - If result is SB_SUCCESS, the image_digest value is copied into verified_digest. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); - -/* Revoke a public key digest in efuse. - @param index Digest to revoke. Must be 0, 1 or 2. - */ -void ets_secure_boot_revoke_public_key_digest(int index); - -#define CRC_SIGN_BLOCK_LEN 1196 -#define SIG_BLOCK_PADDING 4096 -#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 - -/* Secure Boot V2 signature block - - (Up to 3 in a signature sector are appended to the image) - */ -struct ets_secure_boot_sig_block { - uint8_t magic_byte; - uint8_t version; - uint8_t _reserved1; - uint8_t _reserved2; - uint8_t image_digest[32]; - ets_rsa_pubkey_t key; - uint8_t signature[384]; - uint32_t block_crc; - uint8_t _padding[16]; -}; - -ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); - -#define SECURE_BOOT_NUM_BLOCKS 3 - -/* V2 Secure boot signature sector (up to 3 blocks) */ -struct ets_secure_boot_signature { - ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; - uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; -}; - -ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); - -#define MAX_KEY_DIGESTS 3 - -struct ets_secure_boot_key_digests { - const void *key_digests[MAX_KEY_DIGESTS]; - bool allow_key_revoke; -}; - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/sha.h b/components/esp_rom/include/esp32h4/rom/sha.h deleted file mode 100644 index 80a8ac9335..0000000000 --- a/components/esp_rom/include/esp32h4/rom/sha.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _ROM_SHA_H_ -#define _ROM_SHA_H_ - -#include -#include -#include "ets_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - SHA1 = 0, - SHA2_224, - SHA2_256, - SHA_TYPE_MAX -} SHA_TYPE; - -typedef struct SHAContext { - bool start; - bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved - SHA_TYPE type; - uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 - unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 - uint32_t total_bits[4]; -} SHA_CTX; - -void ets_sha_enable(void); - -void ets_sha_disable(void); - -ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); - -ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); - -void ets_sha_get_state(SHA_CTX *ctx); - -void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); - -void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); - -ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_SHA_H_ */ diff --git a/components/esp_rom/include/esp32h4/rom/spi_flash.h b/components/esp_rom/include/esp32h4/rom/spi_flash.h deleted file mode 100644 index 6915de9671..0000000000 --- a/components/esp_rom/include/esp32h4/rom/spi_flash.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "esp_attr.h" -#include "esp_rom_spiflash.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) -#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) -#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) -#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) -#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) -#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) -#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) -#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) -#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) - -#define SPI0_R_QIO_DUMMY_CYCLELEN 5 -#define SPI0_R_QIO_ADDR_BITSLEN 23 -#define SPI0_R_FAST_DUMMY_CYCLELEN 7 -#define SPI0_R_DIO_DUMMY_CYCLELEN 3 -#define SPI0_R_FAST_ADDR_BITSLEN 23 -#define SPI0_R_SIO_ADDR_BITSLEN 23 - -#define SPI1_R_QIO_DUMMY_CYCLELEN 5 -#define SPI1_R_QIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_DUMMY_CYCLELEN 7 -#define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_ADDR_BITSLEN 23 -#define SPI1_R_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B - -//SPI address register -#define ESP_ROM_SPIFLASH_BYTES_LEN 24 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf - -typedef void (* spi_flash_func_t)(void); -typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); -typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); -typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); -typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); -typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); -typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); -typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); - -typedef struct { - uint8_t pp_addr_bit_len; - uint8_t se_addr_bit_len; - uint8_t be_addr_bit_len; - uint8_t rd_addr_bit_len; - uint32_t read_sub_len; - uint32_t write_sub_len; - spi_flash_op_t unlock; - spi_flash_erase_t erase_sector; - spi_flash_erase_t erase_block; - spi_flash_rd_t read; - spi_flash_wr_t write; - spi_flash_ewr_t encrypt_write; - spi_flash_func_t check_sus; - spi_flash_wren_t wren; - spi_flash_op_t wait_idle; - spi_flash_erase_area_t erase_area; -} spiflash_legacy_funcs_t; - -typedef struct { - uint8_t data_length; - uint8_t read_cmd0; - uint8_t read_cmd1; - uint8_t write_cmd; - uint16_t data_mask; - uint16_t data; -} esp_rom_spiflash_common_cmd_t; - -/** - * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t *status : The pointer to which to return the Flash status value. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); - -/** - * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t *status : The pointer to which to return the Flash status value. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); - -/** - * @brief Write status to Flash status register. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t status_value : Value to . - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); - -/** - * @brief Use a command to Read Flash status register. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t*status : The pointer to which to return the Flash status value. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); - -/** - * @brief Config SPI Flash read mode when init. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. - * - * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : config error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); - -/** - * @brief Config SPI Flash clock divisor. - * Please do not call this function in SDK. - * - * @param uint8_t freqdiv: clock divisor. - * - * @param uint8_t spi: 0 for SPI0, 1 for SPI1. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : config error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); - -/** - * @brief Clear all SR bits except QE bit. - * Please do not call this function in SDK. - * - * @param None. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); - -/** - * @brief Clear all SR bits except QE bit. - * Please do not call this function in SDK. - * - * @param None. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); - -/** - * @brief Update SPI Flash parameter. - * Please do not call this function in SDK. - * - * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. - * - * @param uint32_t chip_size : The Flash size. - * - * @param uint32_t block_size : The Flash block size. - * - * @param uint32_t sector_size : The Flash sector size. - * - * @param uint32_t page_size : The Flash page size. - * - * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, - uint32_t sector_size, uint32_t page_size, uint32_t status_mask); - -/** - * @brief Erase whole flash chip. - * Please do not call this function in SDK. - * - * @param None - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); - -/** - * @brief Erase a 64KB block of flash - * Uses SPI flash command D8H. - * Please do not call this function in SDK. - * - * @param uint32_t block_num : Which block to erase. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); - -/** - * @brief Erase a sector of flash. - * Uses SPI flash command 20H. - * Please do not call this function in SDK. - * - * @param uint32_t sector_num : Which sector to erase. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); - -/** - * @brief Erase some sectors. - * Please do not call this function in SDK. - * - * @param uint32_t start_addr : Start addr to erase, should be sector aligned. - * - * @param uint32_t area_len : Length to erase, should be sector aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); - -/** - * @brief Write Data to Flash, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. - * - * @param const uint32_t *src : The pointer to data which is to write. - * - * @param uint32_t len : Length to write, should be 4 bytes aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); - -/** - * @brief Read Data from Flash, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. - * - * @param uint32_t *dest : The buf to read the data. - * - * @param uint32_t len : Length to read, should be 4 bytes aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); - -/** - * @brief SPI1 go into encrypto mode. - * Please do not call this function in SDK. - * - * @param None - * - * @return None - */ -void esp_rom_spiflash_write_encrypted_enable(void); - -/** - * @brief SPI1 go out of encrypto mode. - * Please do not call this function in SDK. - * - * @param None - * - * @return None - */ -void esp_rom_spiflash_write_encrypted_disable(void); - -/** - * @brief Write data to flash with transparent encryption. - * @note Sectors to be written should already be erased. - * - * @note Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. - * - * @param uint32_t *data : The pointer to data to write. Note, this pointer must - * be 32 bit aligned and the content of the data will be - * modified by the encryption function. - * - * @param uint32_t len : Length to write, should be 32 bytes aligned. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. - * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); - - -/** @brief Wait until SPI flash write operation is complete - * - * @note Please do not call this function in SDK. - * - * Reads the Write In Progress bit of the SPI flash status register, - * repeats until this bit is zero (indicating write complete). - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete - * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); - - -/** @brief Enable Quad I/O pin functions - * - * @note Please do not call this function in SDK. - * - * Sets the HD & WP pin functions for Quad I/O modes, based on the - * efuse SPI pin configuration. - * - * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. - * - * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). - * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. - * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. - * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used - * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). - * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. - */ -void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); - -/** - * @brief Clear WEL bit unconditionally. - * - * @return always ESP_ROM_SPIFLASH_RESULT_OK - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); - -/** - * @brief Set WREN bit. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @return always ESP_ROM_SPIFLASH_RESULT_OK - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); - -/** - * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. - * Please do not call this function in SDK. - * - * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). - * - * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. - * - * @return None - */ -void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); - -/** - * @brief Set SPI Flash pad drivers. - * Please do not call this function in SDK. - * - * @param uint8_t wp_gpio_num: WP gpio number. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid - * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. - * Values usually read from falsh by rom code, function usually callde by rom code. - * if value with bit(3) set, the value is valid, bit[2:0] is the real value. - * - * @return None - */ -void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); - -/** - * @brief Select SPI Flash function for pads. - * Please do not call this function in SDK. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @return None - */ -void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); - -/** - * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. - * - * @return uint16_t 0 : do not send command any more. - * 1 : go to the next command. - * n > 1 : skip (n - 1) commands. - */ -uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); - -extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32h4/rom/tjpgd.h b/components/esp_rom/include/esp32h4/rom/tjpgd.h deleted file mode 100644 index 46527e1f11..0000000000 --- a/components/esp_rom/include/esp32h4/rom/tjpgd.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/*----------------------------------------------------------------------------/ -/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012 -/----------------------------------------------------------------------------*/ -#ifndef _TJPGDEC -#define _TJPGDEC -/*---------------------------------------------------------------------------*/ -/* System Configurations */ - -#define JD_SZBUF 512 /* Size of stream input buffer */ -#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ -#define JD_USE_SCALE 1 /* Use descaling feature for output */ -#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ - -/*---------------------------------------------------------------------------*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* These types must be 16-bit, 32-bit or larger integer */ -typedef int INT; -typedef unsigned int UINT; - -/* These types must be 8-bit integer */ -typedef char CHAR; -typedef unsigned char UCHAR; -typedef unsigned char BYTE; - -/* These types must be 16-bit integer */ -typedef short SHORT; -typedef unsigned short USHORT; -typedef unsigned short WORD; -typedef unsigned short WCHAR; - -/* These types must be 32-bit integer */ -typedef long LONG; -typedef unsigned long ULONG; -typedef unsigned long DWORD; - - -/* Error code */ -typedef enum { - JDR_OK = 0, /* 0: Succeeded */ - JDR_INTR, /* 1: Interrupted by output function */ - JDR_INP, /* 2: Device error or wrong termination of input stream */ - JDR_MEM1, /* 3: Insufficient memory pool for the image */ - JDR_MEM2, /* 4: Insufficient stream input buffer */ - JDR_PAR, /* 5: Parameter error */ - JDR_FMT1, /* 6: Data format error (may be damaged data) */ - JDR_FMT2, /* 7: Right format but not supported */ - JDR_FMT3 /* 8: Not supported JPEG standard */ -} JRESULT; - - - -/* Rectangular structure */ -typedef struct { - WORD left, right, top, bottom; -} JRECT; - - - -/* Decompressor object structure */ -typedef struct JDEC JDEC; -struct JDEC { - UINT dctr; /* Number of bytes available in the input buffer */ - BYTE *dptr; /* Current data read ptr */ - BYTE *inbuf; /* Bit stream input buffer */ - BYTE dmsk; /* Current bit in the current read byte */ - BYTE scale; /* Output scaling ratio */ - BYTE msx, msy; /* MCU size in unit of block (width, height) */ - BYTE qtid[3]; /* Quantization table ID of each component */ - SHORT dcv[3]; /* Previous DC element of each component */ - WORD nrst; /* Restart inverval */ - UINT width, height; /* Size of the input image (pixel) */ - BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ - WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */ - BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ - LONG *qttbl[4]; /* Dequaitizer tables [id] */ - void *workbuf; /* Working buffer for IDCT and RGB output */ - BYTE *mcubuf; /* Working buffer for the MCU */ - void *pool; /* Pointer to available memory pool */ - UINT sz_pool; /* Size of momory pool (bytes available) */ - UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */ - void *device; /* Pointer to I/O device identifiler for the session */ -}; - - - -/* TJpgDec API functions */ -JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *); -JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE); - - -#ifdef __cplusplus -} -#endif - -#endif /* _TJPGDEC */ diff --git a/components/esp_rom/include/esp32h4/rom/uart.h b/components/esp_rom/include/esp32h4/rom/uart.h deleted file mode 100644 index 28677ac409..0000000000 --- a/components/esp_rom/include/esp32h4/rom/uart.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_UART_H_ -#define _ROM_UART_H_ - -#include "esp_types.h" -#include "esp_attr.h" -#include "ets_sys.h" -#include "soc/soc.h" -#include "soc/uart_reg.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup uart_apis, uart configuration and communication related apis - * @brief uart apis - */ - -/** @addtogroup uart_apis - * @{ - */ - -#define RX_BUFF_SIZE 0x400 -#define TX_BUFF_SIZE 100 - -//uart int enalbe register ctrl bits -#define UART_RCV_INTEN BIT0 -#define UART_TRX_INTEN BIT1 -#define UART_LINE_STATUS_INTEN BIT2 - -//uart int identification ctrl bits -#define UART_INT_FLAG_MASK 0x0E - -//uart fifo ctrl bits -#define UART_CLR_RCV_FIFO BIT1 -#define UART_CLR_TRX_FIFO BIT2 -#define UART_RCVFIFO_TRG_LVL_BITS BIT6 - -//uart line control bits -#define UART_DIV_LATCH_ACCESS_BIT BIT7 - -//uart line status bits -#define UART_RCV_DATA_RDY_FLAG BIT0 -#define UART_RCV_OVER_FLOW_FLAG BIT1 -#define UART_RCV_PARITY_ERR_FLAG BIT2 -#define UART_RCV_FRAME_ERR_FLAG BIT3 -#define UART_BRK_INT_FLAG BIT4 -#define UART_TRX_FIFO_EMPTY_FLAG BIT5 -#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg -#define UART_RCV_ERR_FLAG BIT7 - -//send and receive message frame head -#define FRAME_FLAG 0x7E - -typedef enum { - UART_LINE_STATUS_INT_FLAG = 0x06, - UART_RCV_FIFO_INT_FLAG = 0x04, - UART_RCV_TMOUT_INT_FLAG = 0x0C, - UART_TXBUFF_EMPTY_INT_FLAG = 0x02 -} UartIntType; //consider bit0 for int_flag - -typedef enum { - RCV_ONE_BYTE = 0x0, - RCV_FOUR_BYTE = 0x1, - RCV_EIGHT_BYTE = 0x2, - RCV_FOURTEEN_BYTE = 0x3 -} UartRcvFifoTrgLvl; - -typedef enum { - FIVE_BITS = 0x0, - SIX_BITS = 0x1, - SEVEN_BITS = 0x2, - EIGHT_BITS = 0x3 -} UartBitsNum4Char; - -typedef enum { - ONE_STOP_BIT = 1, - ONE_HALF_STOP_BIT = 2, - TWO_STOP_BIT = 3 -} UartStopBitsNum; - -typedef enum { - NONE_BITS = 0, - ODD_BITS = 2, - EVEN_BITS = 3 - -} UartParityMode; - -typedef enum { - STICK_PARITY_DIS = 0, - STICK_PARITY_EN = 2 -} UartExistParity; - -typedef enum { - BIT_RATE_9600 = 9600, - BIT_RATE_19200 = 19200, - BIT_RATE_38400 = 38400, - BIT_RATE_57600 = 57600, - BIT_RATE_115200 = 115200, - BIT_RATE_230400 = 230400, - BIT_RATE_460800 = 460800, - BIT_RATE_921600 = 921600 -} UartBautRate; - -typedef enum { - NONE_CTRL, - HARDWARE_CTRL, - XON_XOFF_CTRL -} UartFlowCtrl; - -typedef enum { - EMPTY, - UNDER_WRITE, - WRITE_OVER -} RcvMsgBuffState; - -typedef struct { - uint8_t *pRcvMsgBuff; - uint8_t *pWritePos; - uint8_t *pReadPos; - uint8_t TrigLvl; - RcvMsgBuffState BuffState; -} RcvMsgBuff; - -typedef struct { - uint32_t TrxBuffSize; - uint8_t *pTrxBuff; -} TrxMsgBuff; - -typedef enum { - BAUD_RATE_DET, - WAIT_SYNC_FRM, - SRCH_MSG_HEAD, - RCV_MSG_BODY, - RCV_ESC_CHAR, -} RcvMsgState; - -typedef struct { - UartBautRate baut_rate; - UartBitsNum4Char data_bits; - UartExistParity exist_parity; - UartParityMode parity; // chip size in byte - UartStopBitsNum stop_bits; - UartFlowCtrl flow_ctrl; - uint8_t buff_uart_no; //indicate which uart use tx/rx buffer - RcvMsgBuff rcv_buff; -// TrxMsgBuff trx_buff; - RcvMsgState rcv_state; - int received; -} UartDevice; - -/** - * @brief Init uart device struct value and reset uart0/uart1 rx. - * Please do not call this function in SDK. - * - * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL - * - * @return None - */ -void uartAttach(void *rxBuffer); - -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, else for UART1. - * - * @param uint32_t clock : clock used by uart module, to adjust baudrate. - * - * @return None - */ -void Uart_Init(uint8_t uart_no, uint32_t clock); - -/** - * @brief Modify uart baudrate. - * This function will reset RX/TX fifo for uart. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint32_t DivLatchValue : (clock << 4)/baudrate. - * - * @return None - */ -void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); - -/** - * @brief Switch printf channel of uart_tx_one_char. - * Please do not call this function when printf. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_tx_switch(uint8_t uart_no); - -/** - * @brief Output a char to printf channel, wait until fifo not full. - * - * @param None - * - * @return OK. - */ -ETS_STATUS uart_tx_one_char(uint8_t TxChar); - -/** - * @brief Output a char to message exchange channel, wait until fifo not full. - * Please do not call this function in SDK. - * - * @param None - * - * @return OK. - */ -ETS_STATUS uart_tx_one_char2(uint8_t TxChar); - -/** - * @brief Wait until uart tx full empty. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None. - */ -void uart_tx_flush(uint8_t uart_no); - -/** - * @brief Wait until uart tx full empty and the last char send ok. - * - * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2 - * - * The function defined in ROM code has a bug, so we define the correct version - * here for compatibility. - */ -void uart_tx_wait_idle(uint8_t uart_no); - -/** - * @brief Get an input char from message channel. - * Please do not call this function in SDK. - * - * @param uint8_t *pRxChar : the pointer to store the char. - * - * @return OK for successful. - * FAIL for failed. - */ -ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); - -/** - * @brief Get an input char from message channel, wait until successful. - * Please do not call this function in SDK. - * - * @param None - * - * @return char : input char value. - */ -char uart_rx_one_char_block(void); - -/** - * @brief Get an input string line from message channel. - * Please do not call this function in SDK. - * - * @param uint8_t *pString : the pointer to store the string. - * - * @param uint8_t MaxStrlen : the max string length, incude '\0'. - * - * @return OK. - */ -ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); - -/** - * @brief Get an char from receive buffer. - * Please do not call this function in SDK. - * - * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. - * - * @param uint8_t *pRxByte : the pointer to store the char. - * - * @return OK for successful. - * FAIL for failed. - */ -ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); - -/** - * @brief Get all chars from receive buffer. - * Please do not call this function in SDK. - * - * @param uint8_t *pCmdLn : the pointer to store the string. - * - * @return OK for successful. - * FAIL for failed. - */ -ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); - -/** - * @brief Get uart configuration struct. - * Please do not call this function in SDK. - * - * @param None - * - * @return UartDevice * : uart configuration struct pointer. - */ -UartDevice *GetUartDevice(void); - -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *p : the pointer to output string. - * - * @param int len : the string length. - * - * @return None. - */ -void send_packet(uint8_t *p, int len); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *p : the pointer to input string. - * - * @param int len : If string length > len, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return int : the length of the string. - */ -int recv_packet(uint8_t *p, int len, uint8_t is_sync); - -extern UartDevice UartDev; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_UART_H_ */ diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index e8ed1f928c..3006f40b60 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -99,7 +99,6 @@ menu "ESP System Settings" default y if IDF_TARGET_ESP32S2 default y if IDF_TARGET_ESP32C3 default y if IDF_TARGET_ESP32S3 - default y if IDF_TARGET_ESP32H4 default y if IDF_TARGET_ESP32C6 default n if IDF_TARGET_ESP32H2 # IDF-5667 depends on SOC_RTC_FAST_MEM_SUPPORTED @@ -280,7 +279,7 @@ menu "ESP System Settings" config ESP_CONSOLE_MULTIPLE_UART bool - default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 + default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 choice ESP_CONSOLE_UART_NUM prompt "UART peripheral to use for console output (0-1)" diff --git a/components/esp_system/crosscore_int.c b/components/esp_system/crosscore_int.c index ceede38f66..03e0fa650f 100644 --- a/components/esp_system/crosscore_int.c +++ b/components/esp_system/crosscore_int.c @@ -29,7 +29,7 @@ #define REASON_FREQ_SWITCH BIT(1) #define REASON_GDB_CALL BIT(3) -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ARCH_XTENSA #define REASON_PRINT_BACKTRACE BIT(2) #define REASON_TWDT_ABORT BIT(4) #endif @@ -66,7 +66,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) { } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ARCH_RISCV WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); #endif @@ -147,7 +147,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) } else { WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1); } -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ARCH_RISCV WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); #endif } @@ -167,7 +167,7 @@ void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id) esp_crosscore_int_send(core_id, REASON_GDB_CALL); } -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 +#if CONFIG_IDF_TARGET_ARCH_XTENSA void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id) { esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE); diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c index 7439c7cfa3..9e52cab9a2 100644 --- a/components/esp_system/fpga_overrides.c +++ b/components/esp_system/fpga_overrides.c @@ -17,8 +17,6 @@ #include "esp32s3/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 @@ -49,8 +47,6 @@ void bootloader_clock_configure(void) uint32_t xtal_freq_mhz = 40; #ifdef CONFIG_IDF_TARGET_ESP32S2 uint32_t apb_freq_hz = 20000000; -#elif CONFIG_IDF_TARGET_ESP32H4 - uint32_t apb_freq_hz = 32000000; #else uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000; #endif // CONFIG_IDF_TARGET_ESP32S2 diff --git a/components/esp_system/include/esp_private/crosscore_int.h b/components/esp_system/include/esp_private/crosscore_int.h index 823794453a..652290eed2 100644 --- a/components/esp_system/include/esp_private/crosscore_int.h +++ b/components/esp_system/include/esp_private/crosscore_int.h @@ -50,7 +50,7 @@ void esp_crosscore_int_send_freq_switch(int core_id); void esp_crosscore_int_send_gdb_call(int core_id); -#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 +#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 /** * Send an interrupt to a CPU indicating it should print its current backtrace * @@ -75,7 +75,7 @@ void esp_crosscore_int_send_print_backtrace(int core_id); void esp_crosscore_int_send_twdt_abort(int core_id); #endif // CONFIG_ESP_TASK_WDT_EN -#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H4 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 +#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 #ifdef __cplusplus } diff --git a/components/esp_system/ld/esp32h4/memory.ld.in b/components/esp_system/ld/esp32h4/memory.ld.in deleted file mode 100644 index c51df7b808..0000000000 --- a/components/esp_system/ld/esp32h4/memory.ld.in +++ /dev/null @@ -1,121 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * ESP32-H4 Linker Script Memory Layout - * This file describes the memory layout (memory blocks) by virtual memory addresses. - * This linker script is passed through the C preprocessor to include configuration options. - * Please use preprocessor features sparingly! - * Restrict to simple macros with numeric values, and/or #if/#endif blocks. - */ - -#include "sdkconfig.h" -#include "ld.common" - -#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM -#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC -#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) -#else -#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) -#endif // not CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC -#else -#define ESP_BOOTLOADER_RESERVE_RTC 0 -#endif // not CONFIG_BOOTLOADER_RESERVE_RTC_MEM - -#define SRAM_IRAM_START 0x4037C000 -#define SRAM_DRAM_START 0x3FC7C000 -#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ - -#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) -#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) - -#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG - -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -MEMORY -{ - /** - * All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - * of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - * are connected to the data port of the CPU and eg allow byte-wise access. - */ - - /* IRAM for PRO CPU. */ - iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - /* Flash mapped instruction data */ - iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20 - - /** - * (0x20 offset above is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB).) - */ -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - - /** - * Shared data RAM, excluding memory reserved for ROM bss/data/stack. - * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. - */ - dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - /* Flash mapped constant data */ - drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20 - - /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - - /** - * RTC fast memory (executable). Persists over deep sleep. - */ - rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC -} - -/* Heap ends at top of dram0_0_seg */ -_heap_end = 0x40000000; - -_data_seg_org = ORIGIN(rtc_data_seg); - -/** - * The lines below define location alias for .rtc.data section - * As C3 only has RTC fast memory, this is not configurable like on other targets - */ -REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); -REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); -REGION_ALIAS("rtc_data_location", rtc_iram_seg ); - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - REGION_ALIAS("default_code_seg", iram0_2_seg); -#else - REGION_ALIAS("default_code_seg", iram0_0_seg); -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - REGION_ALIAS("default_rodata_seg", drom0_0_seg); -#else - REGION_ALIAS("default_rodata_seg", dram0_0_seg); -#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS - -/** - * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must - * also be first in the segment. - */ -#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS - ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), - ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") -#endif - -#if CONFIG_ESP_SYSTEM_USE_EH_FRAME - ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!"); - ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!"); -#endif diff --git a/components/esp_system/ld/esp32h4/sections.ld.in b/components/esp_system/ld/esp32h4/sections.ld.in deleted file mode 100644 index 43fbf0cb1f..0000000000 --- a/components/esp_system/ld/esp32h4/sections.ld.in +++ /dev/null @@ -1,422 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default entry point */ -ENTRY(call_start_cpu0); - -SECTIONS -{ - /** - * RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - _rtc_fast_start = ABSOLUTE(.); - - mapping[rtc_text] - - *rtc_wake_stub*.*(.literal .text .literal.* .text.*) - *(.rtc_text_end_test) - - /* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(4); - - _rtc_text_end = ABSOLUTE(.); - } > rtc_iram_seg - - /** - * This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : - { - . = ALIGN(4); - _rtc_force_fast_start = ABSOLUTE(.); - - mapping[rtc_force_fast] - - *(.rtc.force_fast .rtc.force_fast.*) - . = ALIGN(4) ; - _rtc_force_fast_end = ABSOLUTE(.); - } > rtc_data_seg - - /** - * RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. - * The memory location of the data is dependent on - * CONFIG_ESP32H4_RTCDATA_IN_FAST_MEM option. - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - - mapping[rtc_data] - - *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*) - _rtc_data_end = ABSOLUTE(.); - } > rtc_data_location - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*) - *rtc_wake_stub*.*(COMMON) - - mapping[rtc_bss] - - _rtc_bss_end = ABSOLUTE(.); - } > rtc_data_location - - /** - * This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - * The memory location of the data is dependent on CONFIG_ESP32H4_RTCDATA_IN_FAST_MEM option. - */ - .rtc_noinit (NOLOAD): - { - . = ALIGN(4); - _rtc_noinit_start = ABSOLUTE(.); - *(.rtc_noinit .rtc_noinit.*) - . = ALIGN(4) ; - _rtc_noinit_end = ABSOLUTE(.); - } > rtc_data_location - - /** - * This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg - - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) - ? (_rtc_force_slow_end - _rtc_data_start) - : (_rtc_force_slow_end - _rtc_force_slow_start); - - _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) - ? (_rtc_force_fast_end - _rtc_fast_start) - : (_rtc_noinit_end - _rtc_fast_start); - - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), - "RTC_SLOW segment data does not fit.") - - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), - "RTC_FAST segment data does not fit.") - - .iram0.text : - { - _iram_start = ABSOLUTE(.); - /* Vectors go to start of IRAM */ - ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned"); - KEEP(*(.exception_vectors.text)); - . = ALIGN(4); - - _invalid_pc_placeholder = ABSOLUTE(.); - - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - - mapping[iram0_text] - - } > iram0_0_seg - - /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - .dram0.dummy (NOLOAD): - { - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } > dram0_0_seg - - .dram0.data : - { - _data_start = ABSOLUTE(.); - *(.gnu.linkonce.d.*) - *(.data1) - __global_pointer$ = . + 0x800; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - - mapping[dram0_data] - - _data_end = ABSOLUTE(.); - . = ALIGN(4); - } > dram0_0_seg - - /** - * This section holds data that should not be initialized at power up. - * The section located in Internal SRAM memory region. The macro _NOINIT - * can be used as attribute to place data into this section. - * See the "esp_attr.h" file for more information. - */ - .noinit (NOLOAD): - { - . = ALIGN(4); - _noinit_start = ABSOLUTE(.); - *(.noinit .noinit.*) - . = ALIGN(4) ; - _noinit_end = ABSOLUTE(.); - } > dram0_0_seg - - /* Shared RAM */ - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - - mapping[dram0_bss] - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.share.mem) - *(.gnu.linkonce.b.*) - - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } > dram0_0_seg - - ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - - .flash.text : - { - _stext = .; - _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ - _text_start = ABSOLUTE(.); - - mapping[flash_text] - - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - - /** CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ - _etext = .; - - /** - * Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } > default_code_seg - - /** - * This dummy section represents the .flash.text section but in default_rodata_seg. - * Thus, it must have its alignment and (at least) its size. - */ - .flash_rodata_dummy (NOLOAD): - { - _flash_rodata_dummy_start = .; - /* Start at the same alignment constraint than .flash.text */ - . = ALIGN(ALIGNOF(.flash.text)); - /* Create an empty gap as big as .flash.text section */ - . = . + SIZEOF(.flash.text); - /* Prepare the alignment of the section above. Few bytes (0x20) must be - * added for the mapping header. */ - . = ALIGN(_esp_mmu_block_size) + 0x20; - } > default_rodata_seg - - .flash.appdesc : ALIGN(0x10) - { - _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - /* Create an empty gap within this section. Thanks to this, the end of this - * section will match .flash.rodata's begin address. Thus, both sections - * will be merged when creating the final bin image. */ - . = ALIGN(ALIGNOF(.flash.rodata)); - } >default_rodata_seg - - .flash.rodata : ALIGN(0x10) - { - _flash_rodata_start = ABSOLUTE(.); - - mapping[flash_rodata] - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 7) & ~ 3; - /* - * C++ constructor and destructor tables - * Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt. - * - * RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead. - * But the init_priority sections will be sorted for iteration in ascending order during startup. - * The rest of the init_array sections is sorted for iteration in descending order during startup, however. - * Hence a different section is generated for the init_priority functions which is iterated in - * ascending order during startup. The corresponding code can be found in startup.c. - */ - __init_priority_array_start = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) - __init_priority_array_end = ABSOLUTE(.); - __init_array_start = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) - __init_array_end = ABSOLUTE(.); - KEEP (*crtbegin.*(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ - soc_reserved_memory_region_start = ABSOLUTE(.); - KEEP (*(.reserved_memory_address)) - soc_reserved_memory_region_end = ABSOLUTE(.); - /* System init functions registered via ESP_SYSTEM_INIT_FN */ - _esp_system_init_fn_array_start = ABSOLUTE(.); - KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) - _esp_system_init_fn_array_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - _thread_local_start = ABSOLUTE(.); - *(.tdata) - *(.tdata.*) - *(.tbss) - *(.tbss.*) - _thread_local_end = ABSOLUTE(.); - . = ALIGN(ALIGNOF(.eh_frame)); - } > default_rodata_seg - - /* Keep this section shall be at least aligned on 4 */ - .eh_frame : ALIGN(4) - { - __eh_frame = ABSOLUTE(.); - KEEP (*(.eh_frame)) - __eh_frame_end = ABSOLUTE(.); - /* Guarantee that this section and the next one will be merged by making - * them adjacent. */ - . = ALIGN(ALIGNOF(.eh_frame_hdr)); - } > default_rodata_seg - - /* To avoid any exception in C++ exception frame unwinding code, this section - * shall be aligned on 8. */ - .eh_frame_hdr : ALIGN(8) - { - __eh_frame_hdr = ABSOLUTE(.); - KEEP (*(.eh_frame_hdr)) - __eh_frame_hdr_end = ABSOLUTE(.); - } > default_rodata_seg - - /* - This section is a place where we dump all the rodata which aren't used at runtime, - so as to avoid binary size increase - */ - .flash.rodata_noload (NOLOAD) : - { - /* - This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address - We don't need to include the noload rodata in this section - */ - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN (4); - } > default_rodata_seg - - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* iram_end_test section exists for use by memprot unit tests only */ - *(.iram_end_test) - - /* ESP32-H4 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */ - . += _esp_memprot_prefetch_pad_size; - . = ALIGN(_esp_memprot_align_size); - - _iram_text_end = ABSOLUTE(.); - } > iram0_0_seg - - .iram0.data : - { - . = ALIGN(16); - _iram_data_start = ABSOLUTE(.); - - mapping[iram0_data] - - _iram_data_end = ABSOLUTE(.); - } > iram0_0_seg - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - _iram_bss_start = ABSOLUTE(.); - - mapping[iram0_bss] - - _iram_bss_end = ABSOLUTE(.); - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } > iram0_0_seg - - /* Marks the end of data, bss and possibly rodata */ - .dram0.heap_start (NOLOAD) : - { - . = ALIGN (16); - _heap_start = ABSOLUTE(.); - } > dram0_0_seg -} - -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), - "DRAM segment data does not fit.") diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index a930c63db9..d3fdbc77d3 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -56,11 +56,6 @@ #include "esp32h2/rtc.h" #include "esp32h2/rom/cache.h" #include "esp_memprot.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" -#include "esp32h4/rom/cache.h" -#include "esp32h4/rom/secure_boot.h" -#include "esp_memprot.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #include "esp32c2/rom/cache.h" diff --git a/components/esp_system/port/soc/esp32h4/CMakeLists.txt b/components/esp_system/port/soc/esp32h4/CMakeLists.txt deleted file mode 100644 index a8034a3b9d..0000000000 --- a/components/esp_system/port/soc/esp32h4/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -set(srcs "clk.c" - "reset_reason.c" - "system_internal.c" - "cache_err_int.c" - "apb_backup_dma.c" - "../../arch/riscv/expression_with_stack.c" - "../../arch/riscv/expression_with_stack_asm.S" - "../../arch/riscv/panic_arch.c" - "../../arch/riscv/debug_stubs.c") - -add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs}) - -target_sources(${COMPONENT_LIB} PRIVATE ${srcs}) diff --git a/components/esp_system/port/soc/esp32h4/Kconfig.cpu b/components/esp_system/port/soc/esp32h4/Kconfig.cpu deleted file mode 100644 index 565e50ff57..0000000000 --- a/components/esp_system/port/soc/esp32h4/Kconfig.cpu +++ /dev/null @@ -1,27 +0,0 @@ -choice ESP_DEFAULT_CPU_FREQ_MHZ - prompt "CPU frequency" - default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA - default ESP_DEFAULT_CPU_FREQ_MHZ_96 if !IDF_ENV_FPGA - help - CPU frequency to be set on application startup. - - config ESP_DEFAULT_CPU_FREQ_MHZ_16 - bool "16 MHz" - depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786 - config ESP_DEFAULT_CPU_FREQ_MHZ_32 - bool "32 MHz" - depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786 - config ESP_DEFAULT_CPU_FREQ_MHZ_64 - bool "64 MHz" - depends on IDF_ENV_FPGA #ESP32H4-TODO: IDF-3786 - config ESP_DEFAULT_CPU_FREQ_MHZ_96 - bool "96 MHz" - depends on !IDF_ENV_FPGA -endchoice - -config ESP_DEFAULT_CPU_FREQ_MHZ - int - default 16 if ESP_DEFAULT_CPU_FREQ_MHZ_16 - default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32 - default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64 - default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96 diff --git a/components/esp_system/port/soc/esp32h4/Kconfig.system b/components/esp_system/port/soc/esp32h4/Kconfig.system deleted file mode 100644 index 95ec81ea7e..0000000000 --- a/components/esp_system/port/soc/esp32h4/Kconfig.system +++ /dev/null @@ -1,45 +0,0 @@ -menu "Brownout Detector" - - config ESP_BROWNOUT_DET - bool "Hardware brownout detect & reset" - default y - help - The ESP32-H4 has a built-in brownout detector which can detect if the voltage is lower than - a specific value. If this happens, it will reset the chip in order to prevent unintended - behaviour. - - choice ESP_BROWNOUT_DET_LVL_SEL - prompt "Brownout voltage level" - depends on ESP_BROWNOUT_DET - default ESP_BROWNOUT_DET_LVL_SEL_7 - help - The brownout detector will reset the chip when the supply voltage is approximately - below this level. Note that there may be some variation of brownout voltage level - between each chip. - - #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages - #of the brownout threshold levels. - config ESP_BROWNOUT_DET_LVL_SEL_7 - bool "2.51V" - config ESP_BROWNOUT_DET_LVL_SEL_6 - bool "2.64V" - config ESP_BROWNOUT_DET_LVL_SEL_5 - bool "2.76V" - config ESP_BROWNOUT_DET_LVL_SEL_4 - bool "2.92V" - config ESP_BROWNOUT_DET_LVL_SEL_3 - bool "3.10V" - config ESP_BROWNOUT_DET_LVL_SEL_2 - bool "3.27V" - endchoice - - config ESP_BROWNOUT_DET_LVL - int - default 2 if ESP_BROWNOUT_DET_LVL_SEL_2 - default 3 if ESP_BROWNOUT_DET_LVL_SEL_3 - default 4 if ESP_BROWNOUT_DET_LVL_SEL_4 - default 5 if ESP_BROWNOUT_DET_LVL_SEL_5 - default 6 if ESP_BROWNOUT_DET_LVL_SEL_6 - default 7 if ESP_BROWNOUT_DET_LVL_SEL_7 - -endmenu diff --git a/components/esp_system/port/soc/esp32h4/apb_backup_dma.c b/components/esp_system/port/soc/esp32h4/apb_backup_dma.c deleted file mode 100644 index 5f14c456d7..0000000000 --- a/components/esp_system/port/soc/esp32h4/apb_backup_dma.c +++ /dev/null @@ -1,40 +0,0 @@ - -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/soc_caps.h" - -#if SOC_APB_BACKUP_DMA -#include "esp_attr.h" -#include "freertos/FreeRTOS.h" -#include "freertos/portmacro.h" -#include "esp32h4/rom/apb_backup_dma.h" - -static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED; - -static void IRAM_ATTR apb_backup_dma_lock(void) -{ - if (xPortInIsrContext()) { - portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex); - } else { - portENTER_CRITICAL(&s_apb_backup_dma_mutex); - } -} - -static void IRAM_ATTR apb_backup_dma_unlock(void) -{ - if (xPortInIsrContext()) { - portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex); - } else { - portEXIT_CRITICAL(&s_apb_backup_dma_mutex); - } -} - -void esp_apb_backup_dma_lock_init(void) -{ - ets_apb_backup_init_lock_func(apb_backup_dma_lock, apb_backup_dma_unlock); -} -#endif diff --git a/components/esp_system/port/soc/esp32h4/cache_err_int.c b/components/esp_system/port/soc/esp32h4/cache_err_int.c deleted file mode 100644 index 5c24fed65b..0000000000 --- a/components/esp_system/port/soc/esp32h4/cache_err_int.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - The cache has an interrupt that can be raised as soon as an access to a cached - region (flash) is done without the cache being enabled. We use that here - to panic the CPU, which from a debugging perspective is better than grabbing bad - data from the bus. -*/ -#include "esp_rom_sys.h" -#include "esp_attr.h" -#include "esp_log.h" -#include "esp_intr_alloc.h" -#include "soc/periph_defs.h" -#include "riscv/interrupt.h" -#include "hal/cache_ll.h" - -static const char *TAG = "CACHE_ERR"; - -void esp_cache_err_int_init(void) -{ - const uint32_t core_id = 0; - - /* Disable cache interrupts if enabled. */ - ESP_INTR_DISABLE(ETS_CACHEERR_INUM); - - /** - * Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with - * them in handler by different types - * I) Cache access error - * 1. dbus trying to write to icache - * 2. dbus authentication fail - * 3. cpu access icache while dbus is disabled [1] - * 4. ibus authentication fail - * 5. ibus trying to write icache - * 6. cpu access icache while ibus is disabled - * II) Cache illegal error - * 1. dbus counter overflow - * 2. ibus counter overflow - * 3. mmu entry fault - * 4. icache preload configurations fault - * 5. icache sync configuration fault - * - * [1]: On ESP32H4 boards, the caches are shared but buses are still - * distinct. So, we have an ibus and a dbus sharing the same cache. - * This error can occur if the dbus performs a request but the icache - * (or simply cache) is disabled. - */ - esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM); - esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); - - /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); - esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); - - ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); - /* On the hardware side, start by clearing all the bits reponsible for cache access error */ - cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Then enable cache access error interrupts. */ - cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - - /* Same goes for cache illegal error: start by clearing the bits and then - * set them back. */ - ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); - - /* Enable the interrupts for cache error. */ - ESP_INTR_ENABLE(ETS_CACHEERR_INUM); -} - -int esp_cache_err_get_cpuid(void) -{ - return 0; -} diff --git a/components/esp_system/port/soc/esp32h4/clk.c b/components/esp_system/port/soc/esp32h4/clk.c deleted file mode 100644 index cb6c0a073a..0000000000 --- a/components/esp_system/port/soc/esp32h4/clk.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include "sdkconfig.h" -#include "esp_attr.h" -#include "esp_log.h" -#include "esp_cpu.h" -#include "esp_clk_internal.h" -#include "esp32h4/rom/ets_sys.h" -#include "esp32h4/rom/uart.h" -#include "esp32h4/rom/rtc.h" -#include "soc/system_reg.h" -#include "soc/soc.h" -#include "soc/rtc.h" -#include "soc/rtc_periph.h" -#include "soc/i2s_reg.h" -#include "hal/wdt_hal.h" -#include "esp_private/periph_ctrl.h" -#include "esp_private/esp_clk.h" -#include "bootloader_clock.h" -#include "soc/syscon_reg.h" -#include "esp_rom_uart.h" - -/* Number of cycles to wait from the 32k XTAL oscillator to consider it running. - * Larger values increase startup delay. Smaller values may cause false positive - * detection (i.e. oscillator runs for a few cycles and then stops). - */ -#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES - -#define MHZ (1000000) - -/* Indicates that this 32k oscillator gets input from external oscillator, rather - * than a crystal. - */ -#define EXT_OSC_FLAG BIT(3) - -/* This is almost the same as soc_rtc_slow_clk_src_t, except that we define - * an extra enum member for the external 32k oscillator. - * For convenience, lower 2 bits should correspond to soc_rtc_slow_clk_src_t values. - */ -typedef enum { - SLOW_CLK_RTC = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150 kHz RC oscillator - SLOW_CLK_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32 kHz XTAL - SLOW_CLK_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32 KHz RC oscillator - SLOW_CLK_32K_EXT_OSC = SOC_RTC_SLOW_CLK_SRC_XTAL32K | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin -} slow_clk_sel_t; - -static void select_rtc_slow_clk(slow_clk_sel_t slow_clk); - -static const char *TAG = "clk"; - - - __attribute__((weak)) void esp_clk_init(void) -{ - rtc_config_t cfg = RTC_CONFIG_DEFAULT(); - soc_reset_reason_t rst_reas; - rst_reas = esp_rom_get_reset_reason(0); - if (rst_reas == RESET_REASON_CHIP_POWER_ON) { - cfg.cali_ocode = 1; - } - rtc_init(cfg); - - assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M); - - rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST); - -#ifdef CONFIG_BOOTLOADER_WDT_ENABLE - // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed. - // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times. - // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec). - // This prevents excessive delay before resetting in case the supply voltage is drawdown. - // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec). - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_feed(&rtc_wdt_ctx); - //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#endif - -#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS) - select_rtc_slow_clk(SLOW_CLK_32K_XTAL); -#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC) - select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC); -#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K) - select_rtc_slow_clk(SLOW_CLK_RC32K); -#else - select_rtc_slow_clk(SLOW_CLK_RTC); -#endif - -#ifdef CONFIG_BOOTLOADER_WDT_ENABLE - // After changing a frequency WDT timeout needs to be set for new frequency. - stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_feed(&rtc_wdt_ctx); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#endif - - rtc_cpu_freq_config_t old_config, new_config; - rtc_clk_cpu_freq_get_config(&old_config); - const uint32_t old_freq_mhz = old_config.freq_mhz; - const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ; - - bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config); - assert(res); - - // Wait for UART TX to finish, otherwise some UART output will be lost - // when switching APB frequency - esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); - - if (res) { - rtc_clk_cpu_freq_set_config(&new_config); - } - - // Re calculate the ccount to make time calculation correct. - esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz ); -} - -static void select_rtc_slow_clk(slow_clk_sel_t slow_clk) -{ - soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; - uint32_t cal_val = 0; - /* number of times to repeat 32k XTAL calibration - * before giving up and switching to the internal RC - */ - int retry_32k_xtal = 3; - - do { - if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - /* 32k XTAL oscillator needs to be enabled and running before it can - * be used. Hardware doesn't have a direct way of checking if the - * oscillator is running. Here we use rtc_clk_cal function to count - * the number of main XTAL cycles in the given number of 32k XTAL - * oscillator cycles. If the 32k XTAL has not started up, calibration - * will time out, returning 0. - */ - ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); - if (slow_clk == SLOW_CLK_32K_XTAL) { - rtc_clk_32k_enable(true); - } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) { - rtc_clk_32k_enable_external(); - } - // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup. - if (SLOW_CLK_CAL_CYCLES > 0) { - cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if (cal_val == 0) { - if (retry_32k_xtal-- > 0) { - continue; - } - ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator"); - rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW; - } - } - } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { - rtc_clk_rc32k_enable(true); - } - rtc_clk_slow_src_set(rtc_slow_clk_src); - - if (SLOW_CLK_CAL_CYCLES > 0) { - /* TODO: 32k XTAL oscillator has some frequency drift at startup. - * Improve calibration routine to wait until the frequency is stable. - */ - cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES); - } else { - const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; - cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz()); - } - } while (cal_val == 0); - ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val); - esp_clk_slowclk_cal_set(cal_val); -} - -void rtc_clk_select_rtc_slow_clk(void) -{ - select_rtc_slow_clk(SLOW_CLK_32K_XTAL); -} - -/* This function is not exposed as an API at this point. - * All peripheral clocks are default enabled after chip is powered on. - * This function disables some peripheral clocks when cpu starts. - * These peripheral clocks are enabled when the peripherals are initialized - * and disabled when they are de-initialized. - */ -__attribute__((weak)) void esp_perip_clk_init(void) -{ - uint32_t common_perip_clk, hwcrypto_perip_clk = 0; - uint32_t common_perip_clk1 = 0; - - soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - - /* For reason that only reset CPU, do not disable the clocks - * that have been enabled before reset. - */ - if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || - rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1 || - rst_reason == RESET_REASON_CPU0_JTAG) { - common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); - } else { - common_perip_clk = SYSTEM_WDG_CLK_EN | - SYSTEM_I2S0_CLK_EN | -#if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | -#endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_LEDC_CLK_EN | - SYSTEM_TIMERGROUP1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_TWAI_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - - common_perip_clk1 = 0; - hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | - SYSTEM_CRYPTO_SHA_CLK_EN | - SYSTEM_CRYPTO_RSA_CLK_EN; - } - - //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. - common_perip_clk |= SYSTEM_I2S0_CLK_EN | -#if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | -#endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_UHCI1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - common_perip_clk1 = 0; - - /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, - * the current is not reduced when disable I2S clock. - */ - // TOCK(check replacement) - // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - - /* Disable some peripheral clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); - - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1); - - /* Disable hardware crypto clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk); - - /* Enable RNG clock. */ - periph_module_enable(PERIPH_RNG_MODULE); - - /* Enable TimerGroup 0 clock to ensure its reference counter will never - * be decremented to 0 during normal operation and preventing it from - * being disabled. - * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog - * registers (Flashboot protection included) will be reenabled, and some - * seconds later, will trigger an unintended reset. - */ - periph_module_enable(PERIPH_TIMG0_MODULE); -} diff --git a/components/esp_system/port/soc/esp32h4/reset_reason.c b/components/esp_system/port/soc/esp32h4/reset_reason.c deleted file mode 100644 index 83d0a2d5d8..0000000000 --- a/components/esp_system/port/soc/esp32h4/reset_reason.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "esp_system.h" -#include "esp_rom_sys.h" -#include "esp_private/system_internal.h" -#include "soc/rtc_periph.h" -#include "esp32h4/rom/rtc.h" - -static void esp_reset_reason_clear_hint(void); - -static esp_reset_reason_t s_reset_reason; - -static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint) -{ - switch (rtc_reset_reason) { - case RESET_REASON_CHIP_POWER_ON: - return ESP_RST_POWERON; - - case RESET_REASON_CPU0_SW: - case RESET_REASON_CORE_SW: - if (reset_reason_hint == ESP_RST_PANIC || - reset_reason_hint == ESP_RST_BROWNOUT || - reset_reason_hint == ESP_RST_TASK_WDT || - reset_reason_hint == ESP_RST_INT_WDT) { - return reset_reason_hint; - } - return ESP_RST_SW; - - case RESET_REASON_CORE_DEEP_SLEEP: - return ESP_RST_DEEPSLEEP; - - case RESET_REASON_CORE_MWDT0: - return ESP_RST_TASK_WDT; - - case RESET_REASON_CORE_MWDT1: - return ESP_RST_INT_WDT; - - case RESET_REASON_CORE_RTC_WDT: - case RESET_REASON_SYS_RTC_WDT: - case RESET_REASON_SYS_SUPER_WDT: - case RESET_REASON_CPU0_RTC_WDT: - case RESET_REASON_CPU0_MWDT0: - case RESET_REASON_CPU0_MWDT1: - return ESP_RST_WDT; - - case RESET_REASON_SYS_BROWN_OUT: - return ESP_RST_BROWNOUT; - - default: - return ESP_RST_UNKNOWN; - } -} - -static void __attribute__((constructor)) esp_reset_reason_init(void) -{ - esp_reset_reason_t hint = esp_reset_reason_get_hint(); - s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint); - if (hint != ESP_RST_UNKNOWN) { - esp_reset_reason_clear_hint(); - } -} - -esp_reset_reason_t esp_reset_reason(void) -{ - return s_reset_reason; -} - -/* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG, - * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the - * deep sleep wake stub entry address and for reset reason hint, since wake stub - * is only used for deep sleep reset, and in this case the reason provided by - * esp_rom_get_reset_reason is unambiguous. - * - * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG): - * the value is replicated in low and high half-words. In addition to that, - * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains - * deep sleep wake stub address. - */ - -#define RST_REASON_BIT 0x80000000 -#define RST_REASON_MASK 0x7FFF -#define RST_REASON_SHIFT 16 - -/* in IRAM, can be called from panic handler */ -void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint) -{ - assert((hint & (~RST_REASON_MASK)) == 0); - uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT; - REG_WRITE(RTC_RESET_CAUSE_REG, val); -} - -/* in IRAM, can be called from panic handler */ -esp_reset_reason_t esp_reset_reason_get_hint(void) -{ - uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG); - uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK; - uint32_t low = reset_reason_hint & RST_REASON_MASK; - if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) { - return ESP_RST_UNKNOWN; - } - return (esp_reset_reason_t) low; -} -static inline void esp_reset_reason_clear_hint(void) -{ - REG_WRITE(RTC_RESET_CAUSE_REG, 0); -} diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c deleted file mode 100644 index b6c3b72ca7..0000000000 --- a/components/esp_system/port/soc/esp32h4/system_internal.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "sdkconfig.h" -#include "esp_system.h" -#include "esp_private/system_internal.h" -#include "esp_attr.h" -#include "esp_efuse.h" -#include "esp_log.h" -#include "riscv/rv_utils.h" -#include "esp_rom_uart.h" -#include "soc/gpio_reg.h" -#include "soc/timer_group_reg.h" -#include "esp_cpu.h" -#include "soc/rtc.h" -#include "esp_private/rtc_clk.h" -#include "soc/rtc_periph.h" -#include "soc/syscon_reg.h" -#include "soc/system_reg.h" -#include "hal/wdt_hal.h" -#include "esp_private/cache_err_int.h" - -#include "esp32h4/rom/cache.h" -#include "esp32h4/rom/rtc.h" - -/* "inner" restart function for after RTOS, interrupts & anything else on this - * core are already stopped. Stalls other core, resets hardware, - * triggers restart. -*/ -void IRAM_ATTR esp_restart_noos(void) -{ - // Disable interrupts - rv_utils_intr_global_disable(); - // Enable RTC watchdog for 1 second - wdt_hal_context_t rtc_wdt_ctx; - wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); - uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT. - wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - - // Disable TG0/TG1 watchdogs - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - // Disable cache - Cache_Disable_ICache(); - - // 2nd stage bootloader reconfigures SPI flash signals. - // Reset them to the defaults expected by ROM. - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - // Reset timer/spi/uart - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, - SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST | - SYSTEM_BT_RST | SYSTEM_BTMAC_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | - SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST - ); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0); - - // Reset dma - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader. -#if !CONFIG_IDF_ENV_FPGA - rtc_clk_cpu_set_to_default_config(); -#endif - - // Reset CPU - esp_rom_software_reset_cpu(0); - while (true) { - ; - } -} diff --git a/components/esp_system/system_time.c b/components/esp_system/system_time.c index 8b130dce78..2ff7107978 100644 --- a/components/esp_system/system_time.c +++ b/components/esp_system/system_time.c @@ -21,8 +21,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c index 7d6bafbefb..f040254069 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c @@ -43,7 +43,7 @@ #define BROWNOUT "BROWN_OUT_RST" #define STORE_ERROR "StoreProhibited" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 #define DEEPSLEEP "DSLEEP" #define LOAD_STORE_ERROR "Store access fault" #define RESET "RTC_SW_CPU_RST" diff --git a/components/esp_timer/src/esp_timer.c b/components/esp_timer/src/esp_timer.c index 27dcf35c69..138bf18a08 100644 --- a/components/esp_timer/src/esp_timer.c +++ b/components/esp_timer/src/esp_timer.c @@ -31,8 +31,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_timer/src/ets_timer_legacy.c b/components/esp_timer/src/ets_timer_legacy.c index e21012f98d..5ba2868e1d 100644 --- a/components/esp_timer/src/ets_timer_legacy.c +++ b/components/esp_timer/src/ets_timer_legacy.c @@ -32,8 +32,6 @@ #include "esp32c3/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32H2 diff --git a/components/esp_timer/src/system_time.c b/components/esp_timer/src/system_time.c index 6f811d59de..e7844a2ccd 100644 --- a/components/esp_timer/src/system_time.c +++ b/components/esp_timer/src/system_time.c @@ -25,8 +25,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_timer/test_apps/main/test_ets_timer.c b/components/esp_timer/test_apps/main/test_ets_timer.c index 7585b4f2ef..6745e850b9 100644 --- a/components/esp_timer/test_apps/main/test_ets_timer.c +++ b/components/esp_timer/test_apps/main/test_ets_timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,8 +23,6 @@ #include "esp32s3/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/esp_wifi/Kconfig b/components/esp_wifi/Kconfig index 46e1f98be9..bc42da9f2d 100644 --- a/components/esp_wifi/Kconfig +++ b/components/esp_wifi/Kconfig @@ -1,6 +1,7 @@ menu "Wi-Fi" - visible if !IDF_TARGET_ESP32H4 + # TODO: Disable WIFI support on ESP32-H2 (WIFI-5796) + # visible if SOC_WIFI_SUPPORTED config ESP_WIFI_ENABLED bool diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index e59c2fbc04..abb0cf52df 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -91,7 +91,6 @@ menu "Serial flasher config" default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2 - default ESPTOOLPY_FLASHFREQ_48M if IDF_TARGET_ESP32H4 config ESPTOOLPY_FLASHFREQ_120M bool "120 MHz" select SPI_FLASH_HPM_ENABLE diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index a492887535..064a0825c0 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -6,14 +6,6 @@ idf_build_get_property(python PYTHON) idf_build_get_property(idf_path IDF_PATH) set(chip_model ${target}) -# TODO: remove this if block when esp32h4 beta1 is no longer supported and we have h4 target in esptool -if(target STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - set(chip_model esp32h2beta1) - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - set(chip_model esp32h2beta2) - endif() -endif() set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model}) set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py") diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig index 66f289e289..6c915d3d65 100644 --- a/components/freertos/Kconfig +++ b/components/freertos/Kconfig @@ -366,7 +366,7 @@ menu "FreeRTOS" config FREERTOS_TICK_SUPPORT_SYSTIMER bool default y if !FREERTOS_TICK_SUPPORT_CORETIMER - # ESP32-S3, ESP32-C3 and ESP32-H4 can use Systimer for FreeRTOS SysTick + # All targets except ESP32 and ESP32S2 can use Systimer for FreeRTOS SysTick # ESP32S2 also has SYSTIMER but it can not be used for the FreeRTOS SysTick because: # - It has only one counter, which already in use esp_timer. # A counter for SysTick should be stall in debug mode but work esp_timer. diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index c37b556c8e..43f0508f1e 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -25,14 +25,6 @@ if(NOT ${target} STREQUAL "esp32" AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) list(APPEND srcs "cache_hal.c") endif() -if(${target} STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - list(APPEND includes "${target}/include/rev1") - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - list(APPEND includes "${target}/include/rev2") - endif() -endif() - if(NOT BOOTLOADER_BUILD) list(APPEND srcs "rtc_io_hal.c" @@ -221,13 +213,6 @@ if(NOT BOOTLOADER_BUILD) "esp32c3/rtc_cntl_hal.c") endif() - if(${target} STREQUAL "esp32h4") - list(APPEND srcs - "spi_flash_hal_gpspi.c" - "aes_hal.c" - "esp32h4/rtc_cntl_hal.c") - endif() - if(${target} STREQUAL "esp32c2") list(APPEND srcs "spi_flash_hal_gpspi.c" diff --git a/components/hal/esp32h4/clk_tree_hal.c b/components/hal/esp32h4/clk_tree_hal.c deleted file mode 100644 index fbef1bb2b0..0000000000 --- a/components/hal/esp32h4/clk_tree_hal.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "hal/clk_tree_hal.h" -#include "hal/clk_tree_ll.h" -#include "soc/rtc.h" -#include "hal/assert.h" -#include "hal/log.h" - -static const char *CLK_HAL_TAG = "clk_hal"; - -uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src) -{ - switch (cpu_clk_src) { - case SOC_CPU_CLK_SRC_XTAL: - return clk_hal_xtal_get_freq_mhz(); - case SOC_CPU_CLK_SRC_PLL: - return clk_ll_bbpll_get_freq_mhz(); - case SOC_CPU_CLK_SRC_RC_FAST: - return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ; - case SOC_CPU_CLK_SRC_XTAL_D2: - return clk_hal_xtal_get_freq_mhz() >> 1; - default: - // Unknown CPU_CLK mux input - HAL_ASSERT(false); - return 0; - } -} - -uint32_t clk_hal_cpu_get_freq_hz(void) -{ - soc_cpu_clk_src_t source = clk_ll_cpu_get_src(); - return clk_hal_soc_root_get_freq_mhz(source) * MHZ / clk_ll_cpu_get_divider(); -} - -uint32_t clk_hal_ahb_get_freq_hz(void) -{ - return clk_hal_cpu_get_freq_hz() / clk_ll_ahb_get_divider(); -} - -uint32_t clk_hal_apb_get_freq_hz(void) -{ - return clk_hal_ahb_get_freq_hz() / clk_ll_apb_get_divider(); -} - -uint32_t clk_hal_lp_slow_get_freq_hz(void) -{ - switch (clk_ll_rtc_slow_get_src()) { - case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: - return SOC_CLK_RC_SLOW_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_XTAL32K: - return SOC_CLK_XTAL32K_FREQ_APPROX; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - return SOC_CLK_RC32K_FREQ_APPROX; - default: - // Unknown RTC_SLOW_CLK mux input - HAL_ASSERT(false); - return 0; - } -} - -uint32_t clk_hal_xtal_get_freq_mhz(void) -{ - uint32_t freq = clk_ll_xtal_load_freq_mhz(); - if (freq == 0) { - HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz"); - return (uint32_t)RTC_XTAL_FREQ_32M; - } - return freq; -} diff --git a/components/hal/esp32h4/efuse_hal.c b/components/hal/esp32h4/efuse_hal.c deleted file mode 100644 index 11aabfd4fb..0000000000 --- a/components/hal/esp32h4/efuse_hal.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "sdkconfig.h" -#include -#include "soc/soc_caps.h" -#include "hal/assert.h" -#include "hal/efuse_hal.h" -#include "hal/efuse_ll.h" -#include "esp_attr.h" - -#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block)))) - -IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void) -{ - return efuse_ll_get_chip_wafer_version_major(); -} - -IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void) -{ - return efuse_ll_get_chip_wafer_version_minor(); -} - -/******************* eFuse control functions *************************/ - -void efuse_hal_set_timing(uint32_t apb_freq_hz) -{ - (void) apb_freq_hz; - efuse_ll_set_pwr_off_num(0x190); -} - -void efuse_hal_read(void) -{ - efuse_hal_set_timing(0); - - efuse_ll_set_conf_read_op_code(); - efuse_ll_set_read_cmd(); - - while (efuse_ll_get_read_cmd() != 0) { } - /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ - while (efuse_ll_get_read_cmd() != 0) { } -} - -void efuse_hal_clear_program_registers(void) -{ - ets_efuse_clear_program_registers(); -} - -void efuse_hal_program(uint32_t block) -{ - efuse_hal_set_timing(0); - - efuse_ll_set_conf_write_op_code(); - efuse_ll_set_pgm_cmd(block); - - while (efuse_ll_get_pgm_cmd() != 0) { } - - efuse_hal_clear_program_registers(); - efuse_hal_read(); -} - -void efuse_hal_rs_calculate(const void *data, void *rs_values) -{ - ets_efuse_rs_calculate(data, rs_values); -} - -/******************* eFuse control functions *************************/ - -bool efuse_hal_is_coding_error_in_block(unsigned block) -{ - if (block == 0) { - for (unsigned i = 0; i < 5; i++) { - if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) { - return true; - } - } - } else if (block <= 10) { - // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) - // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 - block--; - uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); - return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; - } - return false; -} diff --git a/components/hal/esp32h4/include/hal/adc_ll.h b/components/hal/esp32h4/include/hal/adc_ll.h deleted file mode 100644 index d271c504cf..0000000000 --- a/components/hal/esp32h4/include/hal/adc_ll.h +++ /dev/null @@ -1,862 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include -#include "esp_attr.h" - -#include "soc/adc_periph.h" -#include "hal/adc_types.h" -#include "hal/adc_types_private.h" -#include "soc/apb_saradc_struct.h" -#include "soc/apb_saradc_reg.h" -#include "soc/rtc_cntl_struct.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/clk_tree_defs.h" -#include "hal/misc.h" -#include "hal/assert.h" -#include "hal/regi2c_ctrl.h" - -#include "soc/regi2c_saradc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31) -#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30) - -/*--------------------------------------------------------------- - Oneshot ----------------------------------------------------------------*/ -#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) -#define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1) - -/*--------------------------------------------------------------- - DMA ----------------------------------------------------------------*/ -#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) -#define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8) -#define ADC_LL_FSM_START_WAIT_DEFAULT (5) -#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100) -#define ADC_LL_SAMPLE_CYCLE_DEFAULT (2) -#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (1) - -#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 -#define ADC_LL_CLKM_DIV_B_DEFAULT 1 -#define ADC_LL_CLKM_DIV_A_DEFAULT 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_EN 0 -#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10 - -/*--------------------------------------------------------------- - PWDET (Power Detect) ----------------------------------------------------------------*/ -#define ADC_LL_PWDET_CCT_DEFAULT (4) - -typedef enum { - ADC_LL_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */ - ADC_LL_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */ - ADC_LL_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */ -} adc_ll_power_t; - -typedef enum { - ADC_LL_RTC_DATA_OK = 0, - ADC_LL_RTC_CTRL_UNSELECTED = 1, - ADC_LL_RTC_CTRL_BREAK = 2, - ADC_LL_RTC_DATA_FAIL = -1, -} adc_ll_rtc_raw_data_t; - -typedef enum { - ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller. - ADC_LL_CTRL_ARB = 1, ///< For ADC2. The controller is selected by the arbiter. -} adc_ll_controller_t; - -/** - * @brief ADC digital controller (DMA mode) work mode. - * - * @note The conversion mode affects the sampling frequency: - * ESP32H4 only support ONLY_ADC1 mode - * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once. - */ -typedef enum { - ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion -} adc_ll_digi_convert_mode_t; - -//These values should be set according to the HW -typedef enum { - ADC_LL_INTR_THRES1_LOW = BIT(26), - ADC_LL_INTR_THRES0_LOW = BIT(27), - ADC_LL_INTR_THRES1_HIGH = BIT(28), - ADC_LL_INTR_THRES0_HIGH = BIT(29), - ADC_LL_INTR_ADC2_DONE = BIT(30), - ADC_LL_INTR_ADC1_DONE = BIT(31), -} adc_ll_intr_t; -FLAG_ATTR(adc_ll_intr_t) - -typedef struct { - union { - struct { - uint8_t atten: 2; - uint8_t channel: 3; - uint8_t unit: 1; - uint8_t reserved: 2; - }; - uint8_t val; - }; -} __attribute__((packed)) adc_ll_digi_pattern_table_t; - -/*--------------------------------------------------------------- - Digital controller setting ----------------------------------------------------------------*/ - -/** - * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms. - * - * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor. - * @param start_wait Delay time after open xpd. - * @param standby_wait Delay time to close xpd. - */ -static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) -{ - // Internal FSM reset wait time - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); - // Internal FSM start wait time - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); - // Internal FSM standby wait time - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); -} - -/** - * Set adc sample cycle for digital controller. - * - * @note Normally, please use default value. - * @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor. - * Range: 2 ~ 0xFF. - */ -static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) -{ - /* Should be called before writing I2C registers. */ - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle); -} - -/** - * Set SAR ADC module clock division factor. - * SAR ADC clock divided from digital controller clock. - * - * @param div Division factor. - */ -static inline void adc_ll_digi_set_clk_div(uint32_t div) -{ - /* ADC clock divided from digital controller clock clk */ - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); -} - -/** - * Set adc max conversion number for digital controller. - * If the number of ADC conversion is equal to the maximum, the conversion is stopped. - * - * @param meas_num Max conversion number. Range: 0 ~ 255. - */ -static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); -} - -/** - * Enable max conversion number detection for digital controller. - * If the number of ADC conversion is equal to the maximum, the conversion is stopped. - * - * @param enable true: enable; false: disable - */ -static inline void adc_ll_digi_convert_limit_enable(bool enable) -{ - APB_SARADC.ctrl2.meas_num_limit = enable; -} - -/** - * Set adc conversion mode for digital controller. - * - * @note ESP32H4 only support ADC1 single mode. - * - * @param mode Conversion mode select. - */ -static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode) -{ - //ESP32H4 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode -} - -/** - * Set pattern table length for digital controller. - * The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection, - * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the - * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. - * - * @param adc_n ADC unit. - * @param patt_len Items range: 1 ~ 8. - */ -static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len) -{ - APB_SARADC.ctrl.sar_patt_len = patt_len - 1; -} - -/** - * Set pattern table for digital controller. - * The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection, - * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the - * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself. - * - * @param adc_n ADC unit. - * @param pattern_index Items index. Range: 0 ~ 7. - * @param pattern Stored conversion rules. - */ -static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table) -{ - uint32_t tab; - uint8_t index = pattern_index / 4; - uint8_t offset = (pattern_index % 4) * 6; - adc_ll_digi_pattern_table_t pattern = {0}; - - pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5); - tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value - tab &= (~(0xFC0000 >> offset)); // Clear old data - tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data - APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back -} - -/** - * Reset the pattern table pointer, then take the measurement rule from table header in next measurement. - * - * @param adc_n ADC unit. - */ -static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n) -{ - APB_SARADC.ctrl.sar_patt_p_clear = 1; - APB_SARADC.ctrl.sar_patt_p_clear = 0; -} - -/** - * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. - * - * @note Only ADC2 have arbiter function. - * @param cycle range: 0 ~ 4. - */ -static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle) -{ - APB_SARADC.ctrl.wait_arb_cycle = cycle; -} - -/** - * ADC Digital controller output data invert or not. - * - * @param adc_n ADC unit. - * @param inv_en data invert or not. - */ -static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en) -{ - if (adc_n == ADC_UNIT_1) { - APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert - } else { // adc_n == ADC_UNIT_2 - APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert - } -} - -/** - * Set the interval clock cycle for the digital controller to trigger the measurement. - * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. - * - * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. - * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. - */ -static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) -{ - APB_SARADC.ctrl2.timer_target = cycle; -} - -/** - * Enable digital controller timer to trigger the measurement. - */ -static inline void adc_ll_digi_trigger_enable(void) -{ - APB_SARADC.ctrl2.timer_en = 1; -} - -/** - * Disable digital controller timer to trigger the measurement. - */ -static inline void adc_ll_digi_trigger_disable(void) -{ - APB_SARADC.ctrl2.timer_en = 0; -} - -/** - * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. - * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1). - * - * @param div_num Division factor. Range: 0 ~ 255. - * @param div_b Division factor. Range: 1 ~ 63. - * @param div_a Division factor. Range: 0 ~ 63. - */ -static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); - APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b; - APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a; -} - -/** - * Enable clock and select clock source for ADC digital controller. - * - * @param clk_src clock source for ADC digital controller. - */ -static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) -{ - // TODO: temporary support - APB_SARADC.apb_adc_clkm_conf.clk_sel = 0; - APB_SARADC.ctrl.sar_clk_gated = 1; -} - -/** - * Disable clock for ADC digital controller. - */ -static inline void adc_ll_digi_controller_clk_disable(void) -{ - APB_SARADC.ctrl.sar_clk_gated = 0; -} - -/** - * Reset adc digital controller filter. - * - * @param idx Filter index - * @param adc_n ADC unit. - */ -static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n) -{ - (void)adc_n; - APB_SARADC.filter_ctrl0.filter_reset = 1; - APB_SARADC.filter_ctrl0.filter_reset = 0; -} - -/** - * Set adc digital controller filter coeff. - * - * @param idx filter index - * @param adc_n adc unit - * @param channel adc channel - * @param coeff filter coeff - */ -static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff) -{ - uint32_t factor_reg_val = 0; - switch (coeff) { - case ADC_DIGI_IIR_FILTER_COEFF_2: - factor_reg_val = 1; - break; - case ADC_DIGI_IIR_FILTER_COEFF_4: - factor_reg_val = 2; - break; - case ADC_DIGI_IIR_FILTER_COEFF_8: - factor_reg_val = 3; - break; - case ADC_DIGI_IIR_FILTER_COEFF_16: - factor_reg_val = 4; - break; - case ADC_DIGI_IIR_FILTER_COEFF_64: - factor_reg_val = 6; - break; - default: - HAL_ASSERT(false); - } - - if (idx == ADC_DIGI_IIR_FILTER_0) { - APB_SARADC.filter_ctrl0.filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7); - APB_SARADC.filter_ctrl1.filter_factor0 = factor_reg_val; - } else if (idx == ADC_DIGI_IIR_FILTER_1) { - APB_SARADC.filter_ctrl0.filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7); - APB_SARADC.filter_ctrl1.filter_factor1 = factor_reg_val; - } -} - -/** - * Enable adc digital controller filter. - * Filtering the ADC data to obtain smooth data at higher sampling rates. - * - * @param idx filter index - * @param adc_n ADC unit - * @param enable Enable / Disable - */ -static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable) -{ - (void)adc_n; - if (!enable) { - if (idx == ADC_DIGI_IIR_FILTER_0) { - APB_SARADC.filter_ctrl0.filter_channel0 = 0xF; - APB_SARADC.filter_ctrl1.filter_factor0 = 0; - } else if (idx == ADC_DIGI_IIR_FILTER_1) { - APB_SARADC.filter_ctrl0.filter_channel1 = 0xF; - APB_SARADC.filter_ctrl1.filter_factor1 = 0; - } - } - //nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled. -} - -/** - * Set monitor mode of adc digital controller. - * - * @note If the channel info is not supported, the monitor function will not be enabled. - * @param adc_n ADC unit. - * @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt. - * false: If ADC_OUT < threshold, Generates monitor interrupt. - */ -static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg) -{ - if (idx == ADC_DIGI_MONITOR_IDX0) { - APB_SARADC.thres0_ctrl.thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); - APB_SARADC.thres0_ctrl.thres0_high = cfg->h_threshold; - APB_SARADC.thres0_ctrl.thres0_low = cfg->l_threshold; - } else { // ADC_DIGI_MONITOR_IDX1 - APB_SARADC.thres1_ctrl.thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); - APB_SARADC.thres1_ctrl.thres1_high = cfg->h_threshold; - APB_SARADC.thres1_ctrl.thres1_low = cfg->l_threshold; - } -} - -/** - * Enable/disable monitor of adc digital controller. - * - * @note If the channel info is not supported, the monitor function will not be enabled. - * @param adc_n ADC unit. - */ -static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) -{ - if (idx == ADC_DIGI_MONITOR_IDX0) { - APB_SARADC.thres0_ctrl.thres0_channel = 0xF; - } else { // ADC_DIGI_MONITOR_IDX1 - APB_SARADC.thres1_ctrl.thres1_channel = 0xF; - } -} - -/** - * Set DMA eof num of adc digital controller. - * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated. - * - * @param num eof num of DMA. - */ -static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); -} - -/** - * Enable output data to DMA from adc digital controller. - */ -static inline void adc_ll_digi_dma_enable(void) -{ - APB_SARADC.dma_conf.apb_adc_trans = 1; -} - -/** - * Disable output data to DMA from adc digital controller. - */ -static inline void adc_ll_digi_dma_disable(void) -{ - APB_SARADC.dma_conf.apb_adc_trans = 0; -} - -/** - * Reset adc digital controller. - */ -static inline void adc_ll_digi_reset(void) -{ - APB_SARADC.dma_conf.apb_adc_reset_fsm = 1; - APB_SARADC.dma_conf.apb_adc_reset_fsm = 0; -} - -/*--------------------------------------------------------------- - PWDET(Power detect) controller setting ----------------------------------------------------------------*/ -/** - * Set adc cct for PWDET controller. - * - * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. - * @param cct Range: 0 ~ 7. - */ -static inline void adc_ll_pwdet_set_cct(uint32_t cct) -{ - /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - abort(); -} - -/** - * Get adc cct for PWDET controller. - * - * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY. - * @return cct Range: 0 ~ 7. - */ -static inline uint32_t adc_ll_pwdet_get_cct(void) -{ - /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ - abort(); -} - -/*--------------------------------------------------------------- - Common setting ----------------------------------------------------------------*/ -/** - * Set ADC module power management. - * - * @param manage Set ADC power status. - */ -static inline void adc_ll_set_power_manage(adc_ll_power_t manage) -{ - //HW bug, use `sar_ctrl_ll_set_power_mode_from_pwdet` instead, `APB_SARADC.ctrl.xpd_sar_force` doesn not effect - //Leave here for a record -} - -__attribute__((always_inline)) -static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl) -{ - //Not used on ESP32H4 -} - -/** - * Set ADC2 module arbiter work mode. - * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, - * the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data. - * - * @note Only ADC2 support arbiter. - * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. - * - * @param mode Refer to `adc_arbiter_mode_t`. - */ -__attribute__((always_inline)) -static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode) -{ - if (mode == ADC_ARB_MODE_FIX) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1; - } else if (mode == ADC_ARB_MODE_LOOP) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter. - } -} - -/** - * Set ADC2 module controller priority in arbiter. - * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, - * the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data. - * - * @note Only ADC2 support arbiter. - * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode. - * @note Default priority: Wi-Fi(2) > RTC(1) > Digital(0); - * - * @param pri_rtc RTC controller priority. Range: 0 ~ 2. - * @param pri_dig Digital controller priority. Range: 0 ~ 2. - * @param pri_pwdet Wi-Fi controller priority. Range: 0 ~ 2. - */ -__attribute__((always_inline)) -static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, uint8_t pri_pwdet) -{ - if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet; - } - /* Should select highest priority controller. */ - if (pri_rtc > pri_dig) { - if (pri_rtc > pri_pwdet) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 1; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; - } - } else { - if (pri_dig > pri_pwdet) { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 1; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0; - } else { - APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0; - APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1; - } - } -} - -/* ADC calibration code. */ -/** - * @brief Set common calibration configuration. Should be shared with other parts (PWDET). - */ -__attribute__((always_inline)) -static inline void adc_ll_calibration_init(adc_unit_t adc_n) -{ - if (adc_n == ADC_UNIT_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1); - } -} - -/** - * Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration. - * - * @note Different ADC units and different attenuation options use different calibration data (initial data). - * - * @param adc_n ADC index number. - * @param channel adc channel number. - * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. - * false: Use IO external voltage as calibration voltage. - */ -static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, adc_channel_t channel, bool internal_gnd) -{ - /* Enable/disable internal connect GND (for calibration). */ - if (adc_n == ADC_UNIT_1) { - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); - } - } else { - if (internal_gnd) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); - } - } -} - -/** - * Resume register status after calibration. - * - * @param adc_n ADC index number. - */ -static inline void adc_ll_calibration_finish(adc_unit_t adc_n) -{ - if (adc_n == ADC_UNIT_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); - } -} - -/** - * Set the calibration result to ADC. - * - * @note Different ADC units and different attenuation options use different calibration data (initial data). - * - * @param adc_n ADC index number. - */ -__attribute__((always_inline)) -static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param) -{ - uint8_t msb = param >> 8; - uint8_t lsb = param & 0xFF; - if (adc_n == ADC_UNIT_1) { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); - } else { - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); - REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); - } -} -/* Temp code end. */ - -/*--------------------------------------------------------------- - Single Read ----------------------------------------------------------------*/ -/** - * Set adc output data format for oneshot mode - * - * @note ESP32C3 Oneshot mode only supports 12bit. - * @param adc_n ADC unit. - * @param bits Output data bits width option. - */ -static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits) -{ - abort(); //TODO IDF-3908 - // //ESP32C3 only supports 12bit, leave here for compatibility - // HAL_ASSERT(bits == ADC_BITWIDTH_12); -} - -/** - * Enable adc channel to start convert. - * - * @note Only one channel can be selected for measurement. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel) -{ - abort(); //TODO IDF-3908 - // APB_SARADC.onetime_sample.onetime_channel = ((adc_n << 3) | channel); -} - -/** - * Disable adc channel to start convert. - * - * @note Only one channel can be selected in once measurement. - * - * @param adc_n ADC unit. - */ -static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n) -{ - abort(); //TODO IDF-3908 - // if (adc_n == ADC_UNIT_1) { - // APB_SARADC.onetime_sample.onetime_channel = ((adc_n << 3) | 0xF); - // } else { // adc_n == ADC_UNIT_2 - // APB_SARADC.onetime_sample.onetime_channel = ((adc_n << 3) | 0x1); - // } -} - -/** - * Start oneshot conversion by software - * - * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle, - * otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow. - * This hardware limitation will be removed in future versions. - */ -static inline void adc_oneshot_ll_start(bool val) -{ - abort(); //TODO IDF-3908 - // APB_SARADC.onetime_sample.onetime_start = val; -} - -/** - * Clear the event for each ADCn for Oneshot mode - * - * @param event ADC event - */ -static inline void adc_oneshot_ll_clear_event(uint32_t event_mask) -{ - abort(); //TODO IDF-3908 - // APB_SARADC.int_clr.val |= event_mask; -} - -/** - * Check the event for each ADCn for Oneshot mode - * - * @param event ADC event - * - * @return - * -true : The conversion process is finish. - * -false : The conversion process is not finish. - */ -static inline bool adc_oneshot_ll_get_event(uint32_t event_mask) -{ - abort(); //TODO IDF-3908 - // return (APB_SARADC.int_raw.val & event_mask); -} - -/** - * Get the converted value for each ADCn for RTC controller. - * - * @param adc_n ADC unit. - * @return - * - Converted value. - */ -static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n) -{ - abort(); //TODO IDF-3908 - // uint32_t ret_val = 0; - // if (adc_n == ADC_UNIT_1) { - // ret_val = APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff; - // } else { // adc_n == ADC_UNIT_2 - // ret_val = APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff; - // } - // return ret_val; -} - -/** - * Analyze whether the obtained raw data is correct. - * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. - * - * @param adc_n ADC unit. - * @param raw_data ADC raw data input (convert value). - * @return - * - 1: The data is correct to use. - * - 0: The data is invalid. - */ -static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data) -{ - abort(); //TODO IDF-3908 - // if (adc_n == ADC_UNIT_1) { - // return true; - // } - - // //The raw data API returns value without channel information. Read value directly from the register - // if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) { - // return false; - // } - - // return true; -} - -/** - * ADC module RTC output data invert or not. - * - * @param adc_n ADC unit. - * @param inv_en data invert or not. - */ -static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en) -{ - abort(); //TODO IDF-3908 - // (void)adc_n; - // (void)inv_en; - // //For compatibility -} - -/** - * Enable oneshot conversion trigger - * - * @param adc_n ADC unit - */ -static inline void adc_oneshot_ll_enable(adc_unit_t adc_n) -{ - abort(); //TODO IDF-3908 - // if (adc_n == ADC_UNIT_1) { - // APB_SARADC.onetime_sample.adc1_onetime_sample = 1; - // } else { - // APB_SARADC.onetime_sample.adc2_onetime_sample = 1; - // } -} - -/** - * Disable oneshot conversion trigger for all the ADC units - */ -static inline void adc_oneshot_ll_disable_all_unit(void) -{ - abort(); //TODO IDF-3908 - // APB_SARADC.onetime_sample.adc1_onetime_sample = 0; - // APB_SARADC.onetime_sample.adc2_onetime_sample = 0; -} - -/** - * Set attenuation - * - * @note Attenuation is for all channels - * - * @param adc_n ADC unit - * @param channel ADC channel - * @param atten ADC attenuation - */ -static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten) -{ - abort(); //TODO IDF-3908 - // (void)adc_n; - // (void)channel; - // // Attenuation is for all channels, unit and channel are for compatibility - // APB_SARADC.onetime_sample.onetime_atten = atten; -} -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/aes_ll.h b/components/hal/esp32h4/include/hal/aes_ll.h deleted file mode 100644 index efa7928377..0000000000 --- a/components/hal/esp32h4/include/hal/aes_ll.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "soc/hwcrypto_reg.h" -#include "hal/aes_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief State of AES accelerator, busy, idle or done - * - */ -typedef enum { - ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */ - ESP_AES_STATE_BUSY, /* Transform in progress */ - ESP_AES_STATE_DONE, /* Transform completed */ -} esp_aes_state_t; - - -/** - * @brief Write the encryption/decryption key to hardware - * - * @param key Key to be written to the AES hardware - * @param key_word_len Number of words in the key - * - * @return Number of bytes written to hardware, used for fault injection check - */ -static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len) -{ - /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ - volatile uint8_t key_in_hardware = 0; - /* Memcpy to avoid potential unaligned access */ - uint32_t key_word; - for (int i = 0; i < key_word_len; i++) { - memcpy(&key_word, key + 4 * i, 4); - REG_WRITE(AES_KEY_BASE + i * 4, key_word); - key_in_hardware += 4; - } - return key_in_hardware; -} - -/** - * @brief Sets the mode - * - * @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0 - * @param key_bytes Number of bytes in the key - */ -static inline void aes_ll_set_mode(int mode, uint8_t key_bytes) -{ - const uint32_t MODE_DECRYPT_BIT = 4; - unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; - - /* See TRM for the mapping between keylength and mode bit */ - REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2)); -} - -/** - * @brief Writes message block to AES hardware - * - * @param input Block to be written - */ -static inline void aes_ll_write_block(const void *input) -{ - uint32_t input_word; - - for (int i = 0; i < AES_BLOCK_WORDS; i++) { - memcpy(&input_word, (uint8_t*)input + 4 * i, 4); - REG_WRITE(AES_TEXT_IN_BASE + i * 4, input_word); - } -} - -/** - * @brief Read the AES block - * - * @param output the output of the transform, length = AES_BLOCK_BYTES - */ -static inline void aes_ll_read_block(void *output) -{ - uint32_t output_word; - const size_t REG_WIDTH = sizeof(uint32_t); - - for (size_t i = 0; i < AES_BLOCK_WORDS; i++) { - output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); - /* Memcpy to avoid potential unaligned access */ - memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word)); - } -} - -/** - * @brief Starts block transform - * - */ -static inline void aes_ll_start_transform(void) -{ - REG_WRITE(AES_TRIGGER_REG, 1); -} - - -/** - * @brief Read state of AES accelerator - * - * @return esp_aes_state_t - */ -static inline esp_aes_state_t aes_ll_get_state(void) -{ - return REG_READ(AES_STATE_REG); -} - - -/** - * @brief Set mode of operation - * - * @note Only used for DMA transforms - * - * @param mode - */ -static inline void aes_ll_set_block_mode(esp_aes_mode_t mode) -{ - REG_WRITE(AES_BLOCK_MODE_REG, mode); -} - -/** - * @brief Set AES-CTR counter to INC32 - * - * @note Only affects AES-CTR mode - * - */ -static inline void aes_ll_set_inc(void) -{ - REG_WRITE(AES_INC_SEL_REG, 0); -} - -/** - * @brief Release the DMA - * - */ -static inline void aes_ll_dma_exit(void) -{ - REG_WRITE(AES_DMA_EXIT_REG, 0); -} - -/** - * @brief Sets the number of blocks to be transformed - * - * @note Only used for DMA transforms - * - * @param num_blocks Number of blocks to transform - */ -static inline void aes_ll_set_num_blocks(size_t num_blocks) -{ - REG_WRITE(AES_BLOCK_NUM_REG, num_blocks); -} - -/* - * Write IV to hardware iv registers - */ -static inline void aes_ll_set_iv(const uint8_t *iv) -{ - uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE); - uint32_t iv_word; - - for (int i = 0; i < IV_WORDS; i++ ) { - /* Memcpy to avoid potential unaligned access */ - memcpy(&iv_word, iv + 4 * i, sizeof(iv_word)); - REG_WRITE(®_addr_buf[i], iv_word); - } -} - -/* - * Read IV from hardware iv registers - */ -static inline void aes_ll_read_iv(uint8_t *iv) -{ - uint32_t iv_word; - const size_t REG_WIDTH = sizeof(uint32_t); - - for (size_t i = 0; i < IV_WORDS; i++) { - iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); - /* Memcpy to avoid potential unaligned access */ - memcpy(iv + i * 4, &iv_word, sizeof(iv_word)); - } -} - -/** - * @brief Enable or disable DMA mode - * - * @param enable true to enable, false to disable. - */ -static inline void aes_ll_dma_enable(bool enable) -{ - REG_WRITE(AES_DMA_ENABLE_REG, enable); -} - -/** - * @brief Enable or disable transform completed interrupt - * - * @param enable true to enable, false to disable. - */ -static inline void aes_ll_interrupt_enable(bool enable) -{ - REG_WRITE(AES_INT_ENA_REG, enable); -} - -/** - * @brief Clears the interrupt - * - */ -static inline void aes_ll_interrupt_clear(void) -{ - REG_WRITE(AES_INT_CLEAR_REG, 1); -} - - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/brownout_ll.h b/components/hal/esp32h4/include/hal/brownout_ll.h deleted file mode 100644 index 0629229e6a..0000000000 --- a/components/hal/esp32h4/include/hal/brownout_ll.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The ll is not public api, don't use in application code. - * See readme.md in hal/readme.md - ******************************************************************************/ - -#pragma once -#include -#include "soc/rtc_cntl_struct.h" -#include "hal/regi2c_ctrl.h" -#include "soc/regi2c_brownout.h" -#include "i2c_pmu.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief power down the flash when a brown out happens. - * - * @param enable true: power down flash. false: not power down - */ -static inline void brownout_ll_enable_flash_power_down(bool enable) -{ - RTCCNTL.brown_out.close_flash_ena = enable; -} - -/** - * @brief power down the RF circuits when a brown out happens - * - * @param enable true: power down. false: not power done. - */ -static inline void brownout_ll_enable_rf_power_down(bool enable) -{ - RTCCNTL.brown_out.pd_rf_ena = enable; -} - -/** - * @brief Enable this to reset brown out - * - * @note: If brown out interrupt is used, this should be disabled. - * - * @param reset_ena true: enable reset. false: disable reset. - * @param reset_wait brown out reset wait cycles - * @param select 1: chip reset, 0: system reset - */ -static inline void brownout_ll_reset_config(bool reset_ena, uint32_t reset_wait, uint8_t select) -{ - RTCCNTL.brown_out.rst_wait = reset_wait; - RTCCNTL.brown_out.rst_ena = reset_ena; - RTCCNTL.brown_out.rst_sel = select; -} - -/** - * @brief Set brown out threshold - * - * @param threshold brownout threshold - */ -static inline void brownout_ll_set_threshold(uint8_t threshold) -{ - REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_DREF_LVDET, threshold); -} - -/** - * @brief Set this bit to enable the brown out detection - * - * @param bod_enable true: enable, false: disable - */ -static inline void brownout_ll_bod_enable(bool bod_enable) -{ - RTCCNTL.brown_out.ena = bod_enable; -} - -/** - * @brief configure the waiting cycles before sending an interrupt - * - * @param cycle waiting cycles. - */ -static inline void brownout_ll_set_intr_wait_cycles(uint8_t cycle) -{ - // Not supported on ESP32H4 -} - -/** - * @brief Enable brown out interrupt - * - * @param enable true: enable, false: disable - */ -static inline void brownout_ll_intr_enable(bool enable) -{ - RTCCNTL.int_ena.rtc_brown_out = enable; -} - -/** - * @brief Clear interrupt bits. - */ -__attribute__((always_inline)) -static inline void brownout_ll_intr_clear(void) -{ - RTCCNTL.int_clr.rtc_brown_out = 1; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/cache_ll.h b/components/hal/esp32h4/include/hal/cache_ll.h deleted file mode 100644 index 058fb9c895..0000000000 --- a/components/hal/esp32h4/include/hal/cache_ll.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for Cache register operations - -#pragma once - -#include "soc/extmem_reg.h" -#include "soc/ext_mem_defs.h" -#include "hal/cache_types.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0 -#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0 - -#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4) -#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1) -#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0) - -#define CACHE_LL_L1_ILG_EVENT_MASK (0x23) -#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5) -#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1) -#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0) - -/** - * @brief Get the buses of a particular cache that are mapped to a virtual address range - * - * External virtual address can only be accessed when the involved cache buses are enabled. - * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_end`) reside. - * - * @param cache_id cache ID (when l1 cache is per core) - * @param vaddr_start virtual address start - * @param len vaddr length - */ -#if !BOOTLOADER_BUILD -__attribute__((always_inline)) -#endif -static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) -{ - HAL_ASSERT(cache_id == 0); - cache_bus_mask_t mask = 0; - - uint32_t vaddr_end = vaddr_start + len - 1; - if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) { - mask |= CACHE_BUS_IBUS0; - } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) { - mask |= CACHE_BUS_DBUS0; - } else { - HAL_ASSERT(0); //Out of region - } - - return mask; -} - -/** - * Enable the Cache Buses - * - * @param cache_id cache ID (when l1 cache is per core) - * @param mask To know which buses should be enabled - */ -#if !BOOTLOADER_BUILD -__attribute__((always_inline)) -#endif -static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) -{ - HAL_ASSERT(cache_id == 0); - //On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); - - uint32_t ibus_mask = 0; - ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; - REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); - - uint32_t dbus_mask = 0; - dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; - REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); -} - -/** - * Disable the Cache Buses - * - * @param cache_id cache ID (when l1 cache is per core) - * @param mask To know which buses should be disabled - */ -__attribute__((always_inline)) -static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) -{ - HAL_ASSERT(cache_id == 0); - //On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first - HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); - - uint32_t ibus_mask = 0; - ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; - REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask); - - uint32_t dbus_mask = 0; - dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; - REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask); -} - - -/*------------------------------------------------------------------------------ - * Interrupt - *----------------------------------------------------------------------------*/ -/** - * @brief Enable Cache access error interrupt - * - * @param cache_id Cache ID, not used on H4. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) -{ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask); -} - -/** - * @brief Clear Cache access error interrupt status - * - * @param cache_id Cache ID, not used on H4. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) -{ - SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask); -} - -/** - * @brief Get Cache access error interrupt status - * - * @param cache_id Cache ID, not used on H4. For compabitlity - * @param mask Interrupt mask - * - * @return Status mask - */ -static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) -{ - return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); -} - -/** - * @brief Enable Cache illegal error interrupt - * - * @param cache_id Cache ID, not used on H4. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) -{ - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask); -} - -/** - * @brief Clear Cache illegal error interrupt status - * - * @param cache_id Cache ID, not used on H4. For compabitlity - * @param mask Interrupt mask - */ -static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) -{ - SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask); -} - -/** - * @brief Get Cache illegal error interrupt status - * - * @param cache_id Cache ID, not used on H4. For compabitlity - * @param mask Interrupt mask - * - * @return Status mask - */ -static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) -{ - return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/clk_gate_ll.h b/components/hal/esp32h4/include/hal/clk_gate_ll.h deleted file mode 100644 index 25e4674d84..0000000000 --- a/components/hal/esp32h4/include/hal/clk_gate_ll.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "soc/periph_defs.h" -#include "soc/system_reg.h" -#include "soc/syscon_reg.h" -#include "soc/dport_access.h" -#include "esp_attr.h" - -static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) -{ - switch (periph) { - case PERIPH_SARADC_MODULE: - return SYSTEM_APB_SARADC_CLK_EN; - case PERIPH_RMT_MODULE: - return SYSTEM_RMT_CLK_EN; - case PERIPH_LEDC_MODULE: - return SYSTEM_LEDC_CLK_EN; - case PERIPH_UART0_MODULE: - return SYSTEM_UART_CLK_EN; - case PERIPH_UART1_MODULE: - return SYSTEM_UART1_CLK_EN; - case PERIPH_I2C0_MODULE: - return SYSTEM_I2C_EXT0_CLK_EN; - case PERIPH_I2S1_MODULE: - return SYSTEM_I2S1_CLK_EN; - case PERIPH_TIMG0_MODULE: - return SYSTEM_TIMERGROUP_CLK_EN; - case PERIPH_TIMG1_MODULE: - return SYSTEM_TIMERGROUP1_CLK_EN; - case PERIPH_UHCI0_MODULE: - return SYSTEM_UHCI0_CLK_EN; - case PERIPH_SYSTIMER_MODULE: - return SYSTEM_SYSTIMER_CLK_EN; - case PERIPH_SPI_MODULE: - return SYSTEM_SPI01_CLK_EN; - case PERIPH_SPI2_MODULE: - return SYSTEM_SPI2_CLK_EN; - case PERIPH_TWAI_MODULE: - return SYSTEM_TWAI_CLK_EN; - case PERIPH_GDMA_MODULE: - return SYSTEM_DMA_CLK_EN; - case PERIPH_AES_MODULE: - return SYSTEM_CRYPTO_AES_CLK_EN; - case PERIPH_SHA_MODULE: - return SYSTEM_CRYPTO_SHA_CLK_EN; - case PERIPH_ECC_MODULE: - return SYSTEM_CRYPTO_ECC_CLK_EN; - case PERIPH_RSA_MODULE: - return SYSTEM_CRYPTO_RSA_CLK_EN; - case PERIPH_HMAC_MODULE: - return SYSTEM_CRYPTO_HMAC_CLK_EN; - case PERIPH_DS_MODULE: - return SYSTEM_CRYPTO_DS_CLK_EN; - case PERIPH_TEMPSENSOR_MODULE: - return SYSTEM_TSENS_CLK_EN; - case PERIPH_ETM_MODULE: - return SYSTEM_ETM_CLK_EN; - case PERIPH_MODEM_RPA_MODULE: - return SYSTEM_BLE_SEC_BAH_CLK_EN; - default: - return 0; - } -} - -static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable) -{ - - (void)enable; // unused - - switch (periph) { - case PERIPH_SARADC_MODULE: - return SYSTEM_APB_SARADC_RST; - case PERIPH_RMT_MODULE: - return SYSTEM_RMT_RST; - case PERIPH_LEDC_MODULE: - return SYSTEM_LEDC_RST; - case PERIPH_UART0_MODULE: - return SYSTEM_UART_RST; - case PERIPH_UART1_MODULE: - return SYSTEM_UART1_RST; - case PERIPH_I2C0_MODULE: - return SYSTEM_I2C_EXT0_RST; - case PERIPH_I2S1_MODULE: - return SYSTEM_I2S1_RST; - case PERIPH_TIMG0_MODULE: - return SYSTEM_TIMERGROUP_RST; - case PERIPH_TIMG1_MODULE: - return SYSTEM_TIMERGROUP1_RST; - case PERIPH_UHCI0_MODULE: - return SYSTEM_UHCI0_RST; - case PERIPH_SYSTIMER_MODULE: - return SYSTEM_SYSTIMER_RST; - case PERIPH_GDMA_MODULE: - return SYSTEM_DMA_RST; - case PERIPH_SPI_MODULE: - return SYSTEM_SPI01_RST; - case PERIPH_SPI2_MODULE: - return SYSTEM_SPI2_RST; - case PERIPH_TWAI_MODULE: - return SYSTEM_TWAI_RST; - case PERIPH_HMAC_MODULE: - return SYSTEM_CRYPTO_HMAC_RST; - case PERIPH_TEMPSENSOR_MODULE: - return SYSTEM_TSENS_RST; - case PERIPH_ECC_MODULE: - return SYSTEM_CRYPTO_ECC_RST; - case PERIPH_AES_MODULE: - if (enable == true) { - // Clear reset on digital signature, otherwise AES unit is held in reset also. - return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST); - } else { - //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. - return SYSTEM_CRYPTO_AES_RST; - } - case PERIPH_SHA_MODULE: - if (enable == true) { - // Clear reset on digital signature and HMAC, otherwise SHA is held in reset - return (SYSTEM_CRYPTO_SHA_RST | SYSTEM_CRYPTO_DS_RST | SYSTEM_CRYPTO_HMAC_RST); - } else { - // Don't assert reset on secure boot, otherwise AES is held in reset - return SYSTEM_CRYPTO_SHA_RST; - } - case PERIPH_RSA_MODULE: - if (enable == true) { - /* also clear reset on digital signature, otherwise RSA is held in reset */ - return (SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_DS_RST); - } else { - /* don't reset digital signature unit, as this resets AES also */ - return SYSTEM_CRYPTO_RSA_RST; - } - case PERIPH_DS_MODULE: - return SYSTEM_CRYPTO_DS_RST; - case PERIPH_ETM_MODULE: - return SYSTEM_ETM_RST; - case PERIPH_MODEM_RPA_MODULE: - return SYSTEM_BLE_SEC_BAH_RST; - default: - return 0; - } -} - -static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) -{ - switch (periph) { - case PERIPH_HMAC_MODULE: - case PERIPH_DS_MODULE: - case PERIPH_AES_MODULE: - case PERIPH_RSA_MODULE: - case PERIPH_SHA_MODULE: - case PERIPH_ECC_MODULE: - case PERIPH_GDMA_MODULE: - case PERIPH_TEMPSENSOR_MODULE: - case PERIPH_ETM_MODULE: - return SYSTEM_PERIP_CLK_EN1_REG; - case PERIPH_BT_MODULE: - return SYSTEM_MODEM_CLK_EN_REG; - case PERIPH_MODEM_RPA_MODULE: - return SYSTEM_MODEM_CLK_EN_REG; - default: - return SYSTEM_PERIP_CLK_EN0_REG; - } -} - -static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) -{ - switch (periph) { - case PERIPH_HMAC_MODULE: - case PERIPH_DS_MODULE: - case PERIPH_AES_MODULE: - case PERIPH_RSA_MODULE: - case PERIPH_SHA_MODULE: - case PERIPH_ECC_MODULE: - case PERIPH_GDMA_MODULE: - case PERIPH_TEMPSENSOR_MODULE: - case PERIPH_ETM_MODULE: - return SYSTEM_PERIP_RST_EN1_REG; - case PERIPH_BT_MODULE: - return SYSTEM_MODEM_RST_EN_REG; - case PERIPH_MODEM_RPA_MODULE: - return SYSTEM_MODEM_RST_EN_REG; - default: - return SYSTEM_PERIP_RST_EN0_REG; - } -} - -static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph) -{ - DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true)); -} - -static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) -{ - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)); - DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); -} - -static inline void periph_ll_reset(periph_module_t periph) -{ - DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); - DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); -} - -static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) -{ - return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && - DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/clk_tree_ll.h b/components/hal/esp32h4/include/hal/clk_tree_ll.h deleted file mode 100644 index 6afa9205a9..0000000000 --- a/components/hal/esp32h4/include/hal/clk_tree_ll.h +++ /dev/null @@ -1,580 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" -#include "soc/clk_tree_defs.h" -#include "soc/rtc.h" -#include "soc/system_reg.h" -#include "soc/clkrst_reg.h" -#include "soc/rtc_cntl_reg.h" -#include "hal/regi2c_ctrl.h" -#include "soc/regi2c_bbpll.h" -#include "hal/assert.h" -#include "hal/log.h" -#include "esp32h4/rom/rtc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define MHZ (1000000) - -#define CLK_LL_PLL_96M_FREQ_MHZ (96) - -#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \ - .dac = 3, \ - .dres = 3, \ - .dgm = 3, \ - .dbuf = 1, \ -} - -#define CLK_LL_RC32K_DFREQ_DEFAULT 707 - -/** - * @brief XTAL32K_CLK enable modes - */ -typedef enum { - CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK - CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL, //!< Enable the external clock signal for XTAL32K_CLK - CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */ -} clk_ll_xtal32k_enable_mode_t; - -/** - * @brief XTAL32K_CLK configuration structure - */ -typedef struct { - uint32_t dac : 6; - uint32_t dres : 3; - uint32_t dgm : 3; - uint32_t dbuf: 1; -} clk_ll_xtal32k_config_t; - -/** - * @brief Power up BBPLL circuit - */ -static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void) -{ - REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -} - -/** - * @brief Power down BBPLL circuit - */ -static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void) -{ - REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -} - -/** - * @brief Enable the 32kHz crystal oscillator - * - * @param mode Used to determine the xtal32k configuration parameters - */ -static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode) -{ - // Configure xtal32k (or only for mode == CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL?) - clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT(); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, cfg.dac); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, cfg.dres); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, cfg.dgm); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); - // Enable xtal32k xpd status - SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); - if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) { - // Not supported yet? - ; - } -} - -/** - * @brief Disable the 32kHz crystal oscillator - */ -static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void) -{ - // Set xtal32k xpd to be controlled by software - SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); - // Disable xtal32k xpd status - CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); -} - -/** - * @brief Get the state of the 32kHz crystal clock - * - * @return True if the 32kHz XTAL is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void) -{ - uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); - /* If xtal xpd is controlled by software */ - bool xtal_xpd_sw = (xtal_conf & RTC_CNTL_XTAL32K_XPD_FORCE) >> RTC_CNTL_XTAL32K_XPD_FORCE_S; - /* If xtal xpd software control is on */ - bool xtal_xpd_st = (xtal_conf & RTC_CNTL_XPD_XTAL_32K) >> RTC_CNTL_XPD_XTAL_32K_S; - // disabled = xtal_xpd_sw && !xtal_xpd_st; enabled = !disbaled - bool enabled = !xtal_xpd_sw || xtal_xpd_st; - return enabled; -} - -/** - * @brief Enable the internal oscillator output for RC32K_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_enable(void) -{ - // Configure rc32k - REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT); - // Enable rc32k xpd status - SET_PERI_REG_MASK(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_XPD); -} - -/** - * @brief Disable the internal oscillator output for RC32k_CLK - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_disable(void) -{ - // Configure rc32k - REG_SET_FIELD(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_DFREQ, CLK_LL_RC32K_DFREQ_DEFAULT); - // Disable rc32k xpd status - CLEAR_PERI_REG_MASK(RTC_CNTL_RC32K_CTRL_REG, RTC_CNTL_RC32K_XPD); -} - -/** - * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); -} - -/** - * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); -} - -/** - * @brief Get the state of the digital RC_FAST_CLK - * - * @return True if the digital RC_FAST_CLK is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void) -{ - return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); -} - -/** - * @brief Enable the digital RC32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_enable(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M); -} - -/** - * @brief Disable the digital RC32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_rc32k_digi_disable(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN_M); -} - -/** - * @brief Get the state of the digital RC32K_CLK - * - * @return True if the digital RC32K_CLK is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(void) -{ - return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN); -} - -/** - * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); -} - -/** - * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals. - */ -static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN_M); -} - -/** - * @brief Get the state of the digital XTAL32K_CLK - * - * @return True if the digital XTAL32K_CLK is enabled - */ -static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void) -{ - return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); -} - -/** - * @brief Get PLL_CLK frequency - * - * @return PLL clock frequency, in MHz - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void) -{ - uint32_t bbpll_freq = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SPLL_FREQ); - HAL_ASSERT(bbpll_freq == CLK_LL_PLL_96M_FREQ_MHZ); - return bbpll_freq; -} - -/** - * @brief Set BBPLL frequency from XTAL source (Digital part) - * - * @param pll_freq_mhz PLL frequency, in MHz - */ -static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz) -{ - (void)pll_freq_mhz; - // ESP32H4 bbpll frequency cannot be changed, fixed to 96MHz - // Do nothing -} - -/** - * @brief Set BBPLL frequency from XTAL source (Analog part) - * - * @param pll_freq_mhz PLL frequency, in MHz - * @param xtal_freq_mhz XTAL frequency, in MHz - */ -static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz) -{ - (void)xtal_freq_mhz; - switch (pll_freq_mhz) { - case CLK_LL_PLL_96M_FREQ_MHZ: // PLL_96M - /* set up PLL by analog control registers */ - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, 0); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DIV, 1); // I2C_BBPLL_OC_DIV_5_0 - break; - default: - break; - } - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 3); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); -} - -/** - * @brief Select the clock source for CPU_CLK - * - * @param in_sel One of the clock sources in soc_cpu_clk_src_t - */ -static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel) -{ - switch (in_sel) { - case SOC_CPU_CLK_SRC_XTAL: - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 0); - break; - case SOC_CPU_CLK_SRC_PLL: - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 1); - break; - case SOC_CPU_CLK_SRC_RC_FAST: - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 2); - break; - case SOC_CPU_CLK_SRC_XTAL_D2: - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 3); - break; - default: - // Unsupported CPU_CLK mux input sel - abort(); - } -} - -/** - * @brief Get the clock source for CPU_CLK - * - * @return Currently selected clock source (one of soc_cpu_clk_src_t values) - */ -static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void) -{ - uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - switch (clk_sel) { - case 0: - return SOC_CPU_CLK_SRC_XTAL; - case 1: - return SOC_CPU_CLK_SRC_PLL; - case 2: - return SOC_CPU_CLK_SRC_RC_FAST; - case 3: - return SOC_CPU_CLK_SRC_XTAL_D2; - default: - return SOC_CPU_CLK_SRC_INVALID; - } -} - -/** - * @brief Set CPU_CLK divider. freq of CPU_CLK = freq of CPU clock source / divider - * - * @param divider Divider. CPU_DIV_NUM = divider - 1. - */ -static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) -{ - HAL_ASSERT(divider > 0); - REG_SET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_CPU_DIV_NUM, divider - 1); -} - -/** - * @brief Get CPU_CLK divider - * - * @return Divider. Divider = (CPU_DIV_NUM + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void) -{ - return REG_GET_FIELD(SYSTEM_CPUCLK_CONF_REG, SYSTEM_CPU_DIV_NUM) + 1; -} - -/** - * @brief Set AHB_CLK divider. freq of AHB_CLK = freq of CPU_CLK / divider - * - * @param divider Divider. AHB_DIV_NUM = divider - 1. - */ -static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider) -{ - HAL_ASSERT(divider > 0); - REG_SET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_AHB_DIV_NUM, divider - 1); -} - -/** - * @brief Get AHB_CLK divider - * - * @return Divider. Divider = (AHB_DIV_NUM + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void) -{ - return REG_GET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_AHB_DIV_NUM) + 1; -} - -/** - * @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider - * - * @param divider Divider. APB_DIV_NUM = divider - 1. - */ -static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider) -{ - HAL_ASSERT(divider > 0); - REG_SET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_APB_DIV_NUM, divider - 1); -} - -/** - * @brief Get APB_CLK divider - * - * @return Divider. Divider = (APB_DIV_NUM + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void) -{ - return REG_GET_FIELD(SYSTEM_BUSCLK_CONF_REG, SYSTEM_APB_DIV_NUM) + 1; -} - -/** - * @brief Select the clock source for RTC_SLOW_CLK - * - * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t - */ -static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel) -{ - switch (in_sel) { - case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, 0); - break; - case SOC_RTC_SLOW_CLK_SRC_XTAL32K: - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, 1); - break; - case SOC_RTC_SLOW_CLK_SRC_RC32K: - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, 2); - break; - default: - // Unsupported RTC_SLOW_CLK mux input sel - abort(); - } -} - -/** - * @brief Get the clock source for RTC_SLOW_CLK - * - * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values) - */ -static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void) -{ - uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); - switch (clk_sel) { - case 0: - return SOC_RTC_SLOW_CLK_SRC_RC_SLOW; - case 1: - return SOC_RTC_SLOW_CLK_SRC_XTAL32K; - case 2: - return SOC_RTC_SLOW_CLK_SRC_RC32K; - default: - // Invalid ANA_CLK_RTC_SEL value - return SOC_RTC_SLOW_CLK_SRC_INVALID; - } -} - -/** - * @brief Select the clock source for RTC_FAST_CLK - * - * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t - */ -static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel) -{ - switch (in_sel) { - case SOC_RTC_FAST_CLK_SRC_XTAL_D2: - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, 0); - break; - case SOC_RTC_FAST_CLK_SRC_RC_FAST: - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, 1); - break; - default: - // Unsupported RTC_FAST_CLK mux input sel - abort(); - } -} - -/** - * @brief Get the clock source for RTC_FAST_CLK - * - * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values) - */ -static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void) -{ - uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); - switch (clk_sel) { - case 0: - return SOC_RTC_FAST_CLK_SRC_XTAL_D2; - case 1: - return SOC_RTC_FAST_CLK_SRC_RC_FAST; - default: - return SOC_RTC_FAST_CLK_SRC_INVALID; - } -} - -/** - * @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX. - * - * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. - */ -static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) -{ - HAL_ASSERT(divider > 0); - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD); -} - -/** - * @brief Get RC_FAST_CLK divider - * - * @return Divider. Divider = (CK8M_DIV_SEL + 1). - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void) -{ - return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; -} - -/** - * @brief Set RC_SLOW_CLK divider - * - * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage. - */ -static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) -{ - HAL_ASSERT(divider > 0); - CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); - REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); - SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD); -} - -/************************* RTC STORAGE REGISTER STORE/LOAD **************************/ -/** - * @brief Store XTAL_CLK frequency in RTC storage register - * - * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit - * halves. These are the routines to work with that representation. - * - * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even, - * otherwise there will be a conflict with the low bit, which is used to disable logs - * in the ROM code. - */ -static inline __attribute__((always_inline)) void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz) -{ - // Read the status of whether disabling logging from ROM code - uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG; - // If so, need to write back this setting - if (reg == RTC_DISABLE_ROM_LOG) { - xtal_freq_mhz |= 1; - } - WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16)); -} - -/** - * @brief Load XTAL_CLK frequency from RTC storage register - * - * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit - * halves. These are the routines to work with that representation. - * - * @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid. - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void) -{ - // ESP32H4 has a fixed crystal frequency (32MHz), but we will still read from the RTC storage register - uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); - if ((xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX) != RTC_XTAL_FREQ_32M) { - return 0; - } - return (uint32_t)RTC_XTAL_FREQ_32M; -} - -/** - * @brief Store APB_CLK frequency in RTC storage register - * - * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit - * halves. These are the routines to work with that representation. - * - * @param apb_freq_hz APB frequency, in Hz - */ -static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_hz) -{ - uint32_t val = apb_freq_hz >> 12; - WRITE_PERI_REG(RTC_APB_FREQ_REG, (val & UINT16_MAX) | ((val & UINT16_MAX) << 16)); -} - -/** - * @brief Store RTC_SLOW_CLK calibration value in RTC storage register - * - * Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds, - * in Q13.19 fixed-point format). - * - * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format - */ -static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value) -{ - REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value); -} - -/** - * @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register - * - * This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches - * - * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format - */ -static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void) -{ - return REG_READ(RTC_SLOW_CLK_CAL_REG); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h deleted file mode 100644 index aa7577464e..0000000000 --- a/components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "riscv/csr.h" - -/*fast gpio*/ -#define CSR_GPIO_OEN_USER 0x803 -#define CSR_GPIO_IN_USER 0x804 -#define CSR_GPIO_OUT_USER 0x805 - -#ifdef __cplusplus -extern "C" { -#endif - -__attribute__((always_inline)) -static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) -{ - RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); -} - -__attribute__((always_inline)) -static inline void dedic_gpio_cpu_ll_write_all(uint32_t value) -{ - RV_WRITE_CSR(CSR_GPIO_OUT_USER, value); -} - -__attribute__((always_inline)) -static inline uint32_t dedic_gpio_cpu_ll_read_in(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER); - return value; -} - -__attribute__((always_inline)) -static inline uint32_t dedic_gpio_cpu_ll_read_out(void) -{ - uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER); - return value; -} - -__attribute__((always_inline)) -static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) -{ - RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); - RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/ds_ll.h b/components/hal/esp32h4/include/hal/ds_ll.h deleted file mode 100644 index 9f3e201808..0000000000 --- a/components/hal/esp32h4/include/hal/ds_ll.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use it in application code. - ******************************************************************************/ - -#pragma once - -#include -#include -#include - -#include "soc/hwcrypto_reg.h" -#include "soc/soc_caps.h" - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void ds_ll_start(void) -{ - REG_WRITE(DS_SET_START_REG, 1); -} - -/** - * @brief Wait until DS peripheral has finished any outstanding operation. - */ -static inline bool ds_ll_busy(void) -{ - return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; -} - -/** - * @brief Busy wait until the hardware is ready. - */ -static inline void ds_ll_wait_busy(void) -{ - while (ds_ll_busy()); -} - -/** - * @brief In case of a key error, check what caused it. - */ -static inline ds_key_check_t ds_ll_key_error_source(void) -{ - uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); - if (key_error == 0) { - return DS_NO_KEY_INPUT; - } else { - return DS_OTHER_WRONG; - } -} - -/** - * @brief Write the initialization vector to the corresponding register field. - */ -static inline void ds_ll_configure_iv(const uint32_t *iv) -{ - for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) { - REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]); - } -} - -/** - * @brief Write the message which should be signed. - * - * @param msg Pointer to the message. - * @param size Length of msg in bytes. It is the RSA signature length in bytes. - */ -static inline void ds_ll_write_message(const uint8_t *msg, size_t size) -{ - memcpy((uint8_t*) DS_X_BASE, msg, size); - asm volatile ("fence"); -} - -/** - * @brief Write the encrypted private key parameters. - */ -static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_params) -{ - /* Note: as the internal peripheral still has RSA 4096 structure, - but C is encrypted based on the actual max RSA length (ETS_DS_MAX_BITS), need to fragment it - when copying to hardware... - - (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment) - */ - typedef struct { uint32_t addr; size_t len; } frag_t; - const frag_t frags[] = { - {DS_C_Y_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, - {DS_C_M_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, - {DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, - {DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE}, - }; - const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t); - const uint8_t *from = encrypted_key_params; - - for (int i = 0; i < NUM_FRAGS; i++) { - memcpy((uint8_t *)frags[i].addr, from, frags[i].len); - asm volatile ("fence"); - from += frags[i].len; - } -} - -/** - * @brief Begin signing procedure. - */ -static inline void ds_ll_start_sign(void) -{ - REG_WRITE(DS_SET_ME_REG, 1); -} - -/** - * @brief check the calculated signature. - * - * @return - * - DS_SIGNATURE_OK if no issue is detected with the signature. - * - DS_SIGNATURE_PADDING_FAIL if the padding of the private key parameters is wrong. - * - DS_SIGNATURE_MD_FAIL if the message digest check failed. This means that the message digest calculated using - * the private key parameters fails, i.e., the integrity of the private key parameters is not protected. - * - DS_SIGNATURE_PADDING_AND_MD_FAIL if both padding and message digest check fail. - */ -static inline ds_signature_check_t ds_ll_check_signature(void) -{ - uint32_t result = REG_READ(DS_QUERY_CHECK_REG); - switch(result) { - case 0: - return DS_SIGNATURE_OK; - case 1: - return DS_SIGNATURE_MD_FAIL; - case 2: - return DS_SIGNATURE_PADDING_FAIL; - default: - return DS_SIGNATURE_PADDING_AND_MD_FAIL; - } -} - -/** - * @brief Read the signature from the hardware. - * - * @param result The signature result. - * @param size Length of signature result in bytes. It is the RSA signature length in bytes. - */ -static inline void ds_ll_read_result(uint8_t *result, size_t size) -{ - memcpy(result, (uint8_t*) DS_Z_BASE, size); - asm volatile ("fence"); -} - -/** - * @brief Exit the signature operation. - * - * @note This does not deactivate the module. Corresponding clock/reset bits have to be triggered for deactivation. - */ -static inline void ds_ll_finish(void) -{ - REG_WRITE(DS_SET_FINISH_REG, 1); - ds_ll_wait_busy(); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/ecc_ll.h b/components/hal/esp32h4/include/hal/ecc_ll.h deleted file mode 100644 index b13bc044ba..0000000000 --- a/components/hal/esp32h4/include/hal/ecc_ll.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include -#include "hal/assert.h" -#include "rev2/soc/ecc_mult_reg.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ECC_PARAM_PX = 0x0, - ECC_PARAM_PY, - ECC_PARAM_K, -} ecc_ll_param_t; - -static inline void ecc_ll_enable_interrupt(void) -{ - REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); -} - -static inline void ecc_ll_disable_interrupt(void) -{ - REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0); -} - -static inline void ecc_ll_clear_interrupt(void) -{ - REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1); -} - -static inline void ecc_ll_set_mode(ecc_mode_t mode) -{ - switch(mode) { - case ECC_MODE_POINT_MUL: - REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0); - break; - case ECC_MODE_INVERSE_MUL: - REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 1); - break; - case ECC_MODE_VERIFY: - REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2); - break; - case ECC_MODE_VERIFY_THEN_POINT_MUL: - REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3); - break; - default: - HAL_ASSERT(false && "Unsupported mode"); - break; - } -} - -static inline void ecc_ll_set_curve(ecc_curve_t curve) -{ - switch(curve) { - case ECC_CURVE_SECP256R1: - REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); - break; - case ECC_CURVE_SECP192R1: - REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); - break; - default: - HAL_ASSERT(false && "Unsupported curve"); - return; - } -} - -static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len) -{ - uint32_t reg; - uint32_t word; - switch (param) { - case ECC_PARAM_PX: - reg = ECC_MULT_PX_1_REG; - break; - case ECC_PARAM_PY: - reg = ECC_MULT_PY_1_REG; - break; - case ECC_PARAM_K: - reg = ECC_MULT_K_1_REG; - break; - default: - HAL_ASSERT(false && "Invalid parameter"); - return; - } - - for (int i = 0; i < len; i += 4) { - memcpy(&word, buf + i, 4); - REG_WRITE(reg + i, word); - } -} - -static inline void ecc_ll_start_calc(void) -{ - REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START); -} - -static inline int ecc_ll_is_calc_finished(void) -{ - return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW); -} - -static inline ecc_mode_t ecc_ll_get_mode(void) -{ - return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE); -} - -static inline int ecc_ll_get_verification_result(void) -{ - return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT); -} - -static inline ecc_curve_t ecc_ll_get_curve(void) -{ - return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); -} - -static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len) -{ - uint32_t reg; - switch (param) { - case ECC_PARAM_PX: - reg = ECC_MULT_PX_1_REG; - break; - case ECC_PARAM_PY: - reg = ECC_MULT_PY_1_REG; - break; - case ECC_PARAM_K: - reg = ECC_MULT_K_1_REG; - break; - default: - HAL_ASSERT(false && "Invalid parameter"); - return; - } - - memcpy(buf, (void *)reg, len); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/efuse_hal.h b/components/hal/esp32h4/include/hal/efuse_hal.h deleted file mode 100644 index ec1cf007ef..0000000000 --- a/components/hal/esp32h4/include/hal/efuse_hal.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "soc/soc_caps.h" -#include "hal/efuse_ll.h" -#include_next "hal/efuse_hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief set eFuse timings - * - * @param apb_freq_hz APB frequency in Hz - */ -void efuse_hal_set_timing(uint32_t apb_freq_hz); - -/** - * @brief trigger eFuse read operation - */ -void efuse_hal_read(void); - -/** - * @brief clear registers for programming eFuses - */ -void efuse_hal_clear_program_registers(void); - -/** - * @brief burn eFuses written in programming registers (one block at once) - * - * @param block block number - */ -void efuse_hal_program(uint32_t block); - -/** - * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. - * - * @param data Pointer to data buffer (length 32 bytes) - * @param rs_values Pointer to write encoded data to (length 12 bytes) - */ -void efuse_hal_rs_calculate(const void *data, void *rs_values); - -/** - * @brief Checks coding error in a block - * - * @param block Index of efuse block - * - * @return True - block has an error. - * False - no error. - */ -bool efuse_hal_is_coding_error_in_block(unsigned block); - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/efuse_ll.h b/components/hal/esp32h4/include/hal/efuse_ll.h deleted file mode 100644 index 15dcaaa6ac..0000000000 --- a/components/hal/esp32h4/include/hal/efuse_ll.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include -#include "soc/efuse_periph.h" -#include "hal/assert.h" -#include "esp32h4/rom/efuse.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Always inline these functions even no gcc optimization is applied. - -/******************* eFuse fields *************************/ - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) -{ - return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) -{ - return EFUSE.rd_repeat_data1.wdt_delay_sel; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) -{ - return EFUSE.rd_mac_spi_sys_0.mac_0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) -{ - return EFUSE.rd_mac_spi_sys_1.mac_1; -} - -__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) -{ - return EFUSE.rd_repeat_data2.secure_boot_en; -} - -// use efuse_hal_get_major_chip_version() to get major chip version -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) -{ - return EFUSE.rd_mac_spi_sys_3.wafer_version; -} - -// use efuse_hal_get_minor_chip_version() to get minor chip version -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) -{ - return 0; -} - -__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) -{ - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) -{ - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) -{ - return 0; -} - -__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) -{ - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) -{ - return EFUSE.rd_mac_spi_sys_3.pkg_version; -} - -/******************* eFuse control functions *************************/ - -__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) -{ - return EFUSE.cmd.read_cmd; -} - -__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) -{ - return EFUSE.cmd.pgm_cmd; -} - -__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) -{ - EFUSE.cmd.read_cmd = 1; -} - -__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) -{ - HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); - EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; -} - -__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) -{ - EFUSE.conf.op_code = EFUSE_READ_OP_CODE; -} - -__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) -{ - EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; -} - -__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) -{ - EFUSE.wr_tim_conf2.pwr_off_num = value; -} - -/******************* eFuse control functions *************************/ - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/gdma_ll.h b/components/hal/esp32h4/include/hal/gdma_ll.h deleted file mode 100644 index 3ccb5a0fac..0000000000 --- a/components/hal/esp32h4/include/hal/gdma_ll.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include /* Required for NULL constant */ -#include -#include -#include "hal/gdma_types.h" -#include "soc/gdma_struct.h" -#include "soc/gdma_reg.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL) - -#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5] - -#define GDMA_LL_RX_EVENT_MASK (0x06A7) -#define GDMA_LL_TX_EVENT_MASK (0x1958) - -// any "valid" peripheral ID can be used for M2M mode -#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1CD) -#define GDMA_LL_INVALID_PERIPH_ID (0x3F) - -#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12) -#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11) -#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<10) -#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<9) -#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<8) -#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<7) -#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<6) -#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<5) -#define GDMA_LL_EVENT_TX_EOF (1<<4) -#define GDMA_LL_EVENT_TX_DONE (1<<3) -#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2) -#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) -#define GDMA_LL_EVENT_RX_DONE (1<<0) - -///////////////////////////////////// Common ///////////////////////////////////////// -/** - * @brief Enable DMA clock gating - */ -static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable) -{ - dev->misc_conf.clk_en = enable; -} - -///////////////////////////////////// RX ///////////////////////////////////////// -/** - * @brief Get DMA RX channel interrupt status word - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) -{ - return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK; -} - -/** - * @brief Enable DMA RX channel interrupt - */ -static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) -{ - if (enable) { - dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK); - } else { - dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK); - } -} - -/** - * @brief Clear DMA RX channel interrupt - */ -__attribute__((always_inline)) -static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) -{ - dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK); -} - -/** - * @brief Get DMA RX channel interrupt status register address - */ -static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) -{ - return (volatile void *)(&dev->intr[channel].st); -} - -/** - * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default - */ -static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].in.in_conf1.in_check_owner = enable; -} - -/** - * @brief Enable DMA RX channel burst reading data, disabled by default - */ -static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].in.in_conf0.in_data_burst_en = enable; -} - -/** - * @brief Enable DMA RX channel burst reading descriptor link, disabled by default - */ -static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].in.in_conf0.indscr_burst_en = enable; -} - -/** - * @brief Reset DMA RX channel FSM and FIFO pointer - */ -__attribute__((always_inline)) -static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].in.in_conf0.in_rst = 1; - dev->channel[channel].in.in_conf0.in_rst = 0; -} - -/** - * @brief Check if DMA RX FIFO is full - * @param fifo_level only supports level 1 - */ -static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) -{ - return dev->channel[channel].in.infifo_status.val & 0x01; -} - -/** - * @brief Check if DMA RX FIFO is empty - * @param fifo_level only supports level 1 - */ -static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) -{ - return dev->channel[channel].in.infifo_status.val & 0x02; -} - -/** - * @brief Get number of bytes in RX FIFO - * @param fifo_level only supports level 1 - */ -static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) -{ - return dev->channel[channel].in.infifo_status.infifo_cnt; -} - -/** - * @brief Pop data from DMA RX FIFO - */ -static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].in.in_pop.infifo_pop = 1; - return dev->channel[channel].in.in_pop.infifo_rdata; -} - -/** - * @brief Set the descriptor link base address for RX channel - */ -__attribute__((always_inline)) -static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) -{ - dev->channel[channel].in.in_link.addr = addr; -} - -/** - * @brief Start dealing with RX descriptors - */ -__attribute__((always_inline)) -static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].in.in_link.start = 1; -} - -/** - * @brief Stop dealing with RX descriptors - */ -__attribute__((always_inline)) -static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].in.in_link.stop = 1; -} - -/** - * @brief Restart a new inlink right after the last descriptor - */ -__attribute__((always_inline)) -static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].in.in_link.restart = 1; -} - -/** - * @brief Enable DMA RX to return the address of current descriptor when receives error - */ -static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].in.in_link.auto_ret = enable; -} - -/** - * @brief Check if DMA RX FSM is in IDLE state - */ -static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].in.in_link.park; -} - -/** - * @brief Get RX success EOF descriptor's address - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].in.in_suc_eof_des_addr; -} - -/** - * @brief Get RX error EOF descriptor's address - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].in.in_err_eof_des_addr; -} - -/** - * @brief Get current RX descriptor's address - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].in.in_dscr; -} - -/** - * @brief Set priority for DMA RX channel - */ -static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) -{ - dev->channel[channel].in.in_pri.rx_pri = prio; -} - -/** - * @brief Connect DMA RX channel to a given peripheral - */ -static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) -{ - dev->channel[channel].in.in_peri_sel.sel = periph_id; - dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M); -} - -/** - * @brief Disconnect DMA RX channel from peripheral - */ -static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].in.in_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID; - dev->channel[channel].in.in_conf0.mem_trans_en = false; -} - -///////////////////////////////////// TX ///////////////////////////////////////// -/** - * @brief Get DMA TX channel interrupt status word - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) -{ - return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK; -} - -/** - * @brief Enable DMA TX channel interrupt - */ -static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) -{ - if (enable) { - dev->intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK); - } else { - dev->intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK); - } -} - -/** - * @brief Clear DMA TX channel interrupt - */ -__attribute__((always_inline)) -static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) -{ - dev->intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK); -} - -/** - * @brief Get DMA TX channel interrupt status register address - */ -static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) -{ - return (volatile void *)(&dev->intr[channel].st); -} - -/** - * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default - */ -static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].out.out_conf1.out_check_owner = enable; -} - -/** - * @brief Enable DMA TX channel burst sending data, disabled by default - */ -static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].out.out_conf0.out_data_burst_en = enable; -} - -/** - * @brief Enable DMA TX channel burst reading descriptor link, disabled by default - */ -static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].out.out_conf0.outdscr_burst_en = enable; -} - -/** - * @brief Set TX channel EOF mode - */ -static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) -{ - dev->channel[channel].out.out_conf0.out_eof_mode = mode; -} - -/** - * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default - */ -static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->channel[channel].out.out_conf0.out_auto_wrback = enable; -} - -/** - * @brief Reset DMA TX channel FSM and FIFO pointer - */ -__attribute__((always_inline)) -static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].out.out_conf0.out_rst = 1; - dev->channel[channel].out.out_conf0.out_rst = 0; -} - -/** - * @brief Check if DMA TX FIFO is full - * @param fifo_level only supports level 1 - */ -static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) -{ - return dev->channel[channel].out.outfifo_status.val & 0x01; -} - -/** - * @brief Check if DMA TX FIFO is empty - * @param fifo_level only supports level 1 - */ -static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) -{ - return dev->channel[channel].out.outfifo_status.val & 0x02; -} - -/** - * @brief Get number of bytes in TX FIFO - * @param fifo_level only supports level 1 - */ -static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) -{ - return dev->channel[channel].out.outfifo_status.outfifo_cnt; -} - -/** - * @brief Push data into DMA TX FIFO - */ -static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) -{ - dev->channel[channel].out.out_push.outfifo_wdata = data; - dev->channel[channel].out.out_push.outfifo_push = 1; -} - -/** - * @brief Set the descriptor link base address for TX channel - */ -__attribute__((always_inline)) -static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) -{ - dev->channel[channel].out.out_link.addr = addr; -} - -/** - * @brief Start dealing with TX descriptors - */ -__attribute__((always_inline)) -static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].out.out_link.start = 1; -} - -/** - * @brief Stop dealing with TX descriptors - */ -__attribute__((always_inline)) -static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].out.out_link.stop = 1; -} - -/** - * @brief Restart a new outlink right after the last descriptor - */ -__attribute__((always_inline)) -static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].out.out_link.restart = 1; -} - -/** - * @brief Check if DMA TX FSM is in IDLE state - */ -static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].out.out_link.park; -} - -/** - * @brief Get TX EOF descriptor's address - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].out.out_eof_des_addr; -} - -/** - * @brief Get current TX descriptor's address - */ -__attribute__((always_inline)) -static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) -{ - return dev->channel[channel].out.out_dscr; -} - -/** - * @brief Set priority for DMA TX channel - */ -static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) -{ - dev->channel[channel].out.out_pri.tx_pri = prio; -} - -/** - * @brief Connect DMA TX channel to a given peripheral - */ -static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id) -{ - (void)periph; - dev->channel[channel].out.out_peri_sel.sel = periph_id; -} - -/** - * @brief Disconnect DMA TX channel from peripheral - */ -static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel) -{ - dev->channel[channel].out.out_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/gpspi_flash_ll.h b/components/hal/esp32h4/include/hal/gpspi_flash_ll.h deleted file mode 100644 index 217b699a89..0000000000 --- a/components/hal/esp32h4/include/hal/gpspi_flash_ll.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The ll is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md - ******************************************************************************/ - -// The Lowlevel layer for SPI Flash - -#pragma once - -#include -#include "soc/spi_periph.h" -#include "soc/spi_struct.h" -#include "hal/spi_types.h" -#include "hal/spi_flash_types.h" -#include // For MIN/MAX -#include -#include -#include "hal/misc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -//NOTE: These macros are changed on h4 for build. MODIFY these when bringup flash. -#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) ) -#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 ) - -typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t; - -#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (48) -/*------------------------------------------------------------------------------ - * Control - *----------------------------------------------------------------------------*/ -/** - * Reset peripheral registers before configuration and starting control - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void gpspi_flash_ll_reset(spi_dev_t *dev) -{ - dev->user.val = 0; - dev->ctrl.val = 0; - - dev->clk_gate.clk_en = 1; - dev->clk_gate.mst_clk_active = 1; - dev->clk_gate.mst_clk_sel = 1; - - dev->dma_conf.val = 0; - dev->dma_conf.tx_seg_trans_clr_en = 1; - dev->dma_conf.rx_seg_trans_clr_en = 1; - dev->dma_conf.dma_seg_trans_en = 0; -} - -/** - * Check whether the previous operation is done. - * - * @param dev Beginning address of the peripheral registers. - * - * @return true if last command is done, otherwise false. - */ -static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev) -{ - return (dev->cmd.usr == 0); -} - -/** - * Get the read data from the buffer after ``gpspi_flash_ll_read`` is done. - * - * @param dev Beginning address of the peripheral registers. - * @param buffer Buffer to hold the output data - * @param read_len Length to get out of the buffer - */ -static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len) -{ - if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { - // If everything is word-aligned, do a faster memcpy - memcpy(buffer, (void *)dev->data_buf, read_len); - } else { - // Otherwise, slow(er) path copies word by word - int copy_len = read_len; - for (int i = 0; i < (read_len + 3) / 4; i++) { - int word_len = MIN(sizeof(uint32_t), copy_len); - uint32_t word = dev->data_buf[i]; - memcpy(buffer, &word, word_len); - buffer = (void *)((intptr_t)buffer + word_len); - copy_len -= word_len; - } - } -} - -/** - * Write a word to the data buffer. - * - * @param dev Beginning address of the peripheral registers. - * @param word Data to write at address 0. - */ -static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word) -{ - dev->data_buf[0] = word; -} - -/** - * Set the data to be written in the data buffer. - * - * @param dev Beginning address of the peripheral registers. - * @param buffer Buffer holding the data - * @param length Length of data in bytes. - */ -static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length) -{ - // Load data registers, word at a time - int num_words = (length + 3) / 4; - for (int i = 0; i < num_words; i++) { - uint32_t word = 0; - uint32_t word_len = MIN(length, sizeof(word)); - memcpy(&word, buffer, word_len); - dev->data_buf[i] = word; - length -= word_len; - buffer = (void *)((intptr_t)buffer + word_len); - } -} - -/** - * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, - * should be configured before this is called. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void gpspi_flash_ll_user_start(spi_dev_t *dev) -{ - dev->cmd.update = 1; - while (dev->cmd.update); - dev->cmd.usr = 1; -} - -/** - * Set HD pin high when flash work at spi mode. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val) -{ - dev->ctrl.hold_pol = pol_val; -} - -/** - * Check whether the host is idle to perform new commands. - * - * @param dev Beginning address of the peripheral registers. - * - * @return true if the host is idle, otherwise false - */ -static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) -{ - return dev->cmd.usr == 0; -} - -/** - * Set phases for user-defined transaction to read - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) -{ - typeof (dev->user) user = { - .usr_command = 1, - .usr_mosi = 0, - .usr_miso = 1, - .usr_addr = 1, - }; - dev->user = user; -} -/*------------------------------------------------------------------------------ - * Configs - *----------------------------------------------------------------------------*/ -/** - * Select which pin to use for the flash - * - * @param dev Beginning address of the peripheral registers. - * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. - */ -static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) -{ - dev->misc.cs0_dis = (pin == 0) ? 0 : 1; - dev->misc.cs1_dis = (pin == 1) ? 0 : 1; -} - -/** - * Set the read io mode. - * - * @param dev Beginning address of the peripheral registers. - * @param read_mode I/O mode to use in the following transactions. - */ -static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode) -{ - typeof (dev->ctrl) ctrl = dev->ctrl; - typeof (dev->user) user = dev->user; - - ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); - user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); - - switch (read_mode) { - case SPI_FLASH_FASTRD: - //the default option - case SPI_FLASH_SLOWRD: - break; - case SPI_FLASH_QIO: - ctrl.fread_quad = 1; - ctrl.faddr_quad = 1; - user.fwrite_quad = 1; - break; - case SPI_FLASH_QOUT: - ctrl.fread_quad = 1; - user.fwrite_quad = 1; - break; - case SPI_FLASH_DIO: - ctrl.fread_dual = 1; - ctrl.faddr_dual = 1; - user.fwrite_dual = 1; - break; - case SPI_FLASH_DOUT: - ctrl.fread_dual = 1; - user.fwrite_dual = 1; - break; - default: - abort(); - } - - dev->ctrl = ctrl; - dev->user = user; -} - -/** - * Set clock frequency to work at. - * - * @param dev Beginning address of the peripheral registers. - * @param clock_val pointer to the clock value to set - */ -static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val) -{ - dev->clock.val = *clock_val; -} - -/** - * Set the input length, in bits. - * - * @param dev Beginning address of the peripheral registers. - * @param bitlen Length of input, in bits. - */ -static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) -{ - dev->user.usr_miso = bitlen > 0; - if (bitlen) { - dev->ms_dlen.ms_data_bitlen = bitlen - 1; - } -} - -/** - * Set the output length, in bits (not including command, address and dummy - * phases) - * - * @param dev Beginning address of the peripheral registers. - * @param bitlen Length of output, in bits. - */ -static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) -{ - dev->user.usr_mosi = bitlen > 0; - if (bitlen) { - dev->ms_dlen.ms_data_bitlen = bitlen - 1; - } -} - -/** - * Set the command. - * - * @param dev Beginning address of the peripheral registers. - * @param command Command to send - * @param bitlen Length of the command - */ -static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen) -{ - dev->user.usr_command = 1; - typeof(dev->user2) user2 = { - .usr_command_value = command, - .usr_command_bitlen = (bitlen - 1), - }; - dev->user2 = user2; -} - -/** - * Get the address length that is set in register, in bits. - * - * @param dev Beginning address of the peripheral registers. - * - */ -static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev) -{ - return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; -} - -/** - * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... - * - * @param dev Beginning address of the peripheral registers. - * @param bitlen Length of the address, in bits - */ -static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen) -{ - dev->user1.usr_addr_bitlen = (bitlen - 1); - dev->user.usr_addr = bitlen ? 1 : 0; -} - -/** - * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... - * - * @param dev Beginning address of the peripheral registers. - * @param addr Address to send - */ -static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen) -{ - // The blank region should be all ones - uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen); - dev->addr = (addr << (32 - bitlen)) | padding_ones; -} - -/** - * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... - * - * @param dev Beginning address of the peripheral registers. - * @param addr Address to send - */ -static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) -{ - dev->addr = addr; -} - -/** - * Set the length of dummy cycles. - * - * @param dev Beginning address of the peripheral registers. - * @param dummy_n Cycles of dummy phases - */ -static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) -{ - dev->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); -} - -/** - * Set D/Q output level during dummy phase - * - * @param dev Beginning address of the peripheral registers. - * @param out_en whether to enable IO output for dummy phase - * @param out_level dummy output level - */ -static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev) -{ - dev->ctrl.dummy_out = out_en; - dev->ctrl.q_pol = out_lev; - dev->ctrl.d_pol = out_lev; -} - -/** - * Set extra hold time of CS after the clocks. - * - * @param dev Beginning address of the peripheral registers. - * @param hold_n Cycles of clocks before CS is inactive - */ -static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) -{ - dev->user1.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); -} - -static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time) -{ - dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->user1.cs_setup_time = cs_setup_time - 1; -} - -/** - * Calculate spi_flash clock frequency division parameters for register. - * - * @param clkdiv frequency division factor - * - * @return Register setting for the given clock division factor. - */ -static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv) -{ - uint32_t div_parameter; - // See comments of `clock` in `spi_struct.h` - if (clkdiv == 1) { - div_parameter = (1 << 31); - } else { - div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12)); - } - return div_parameter; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/hmac_ll.h b/components/hal/esp32h4/include/hal/hmac_ll.h deleted file mode 100644 index 7cbdf63275..0000000000 --- a/components/hal/esp32h4/include/hal/hmac_ll.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use it in application code. - * See readme.md in soc/include/hal/readme.md - ******************************************************************************/ - -#pragma once - -#include - -#include "soc/system_reg.h" -#include "soc/hwcrypto_reg.h" -#include "hal/hmac_hal.h" - -#define SHA256_BLOCK_SZ 64 -#define SHA256_DIGEST_SZ 32 - -#define EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG 6 -#define EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE 7 -#define EFUSE_KEY_PURPOSE_HMAC_UP 8 -#define EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL 5 - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Makes the peripheral ready for use, after enabling it. - */ -static inline void hmac_ll_start(void) -{ - REG_WRITE(HMAC_SET_START_REG, 1); -} - -/** - * @brief Determine where the HMAC output should go. - * - * The HMAC peripheral can be configured to deliver its output to the user directly, or to deliver - * the output directly to another peripheral instead, e.g. the Digital Signature peripheral. - */ -static inline void hmac_ll_config_output(hmac_hal_output_t config) -{ - switch(config) { - case HMAC_OUTPUT_USER: - REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP); - break; - case HMAC_OUTPUT_DS: - REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE); - break; - case HMAC_OUTPUT_JTAG_ENABLE: - REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); - break; - case HMAC_OUTPUT_ALL: - REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL); - break; - default: - ; // do nothing, error will be indicated by hmac_hal_config_error() - } -} - -/** - * @brief Selects which hardware key should be used. - */ -static inline void hmac_ll_config_hw_key_id(uint32_t key_id) -{ - REG_WRITE(HMAC_SET_PARA_KEY_REG, key_id); -} - -/** - * @brief Apply and check configuration. - * - * Afterwards, the configuration can be checked for errors with hmac_hal_config_error(). - */ -static inline void hmac_ll_config_finish(void) -{ - REG_WRITE(HMAC_SET_PARA_FINISH_REG, 1); -} - -/** - * - * @brief Query HMAC error state after configuration actions. - * - * @return - * - 1 or greater on error - * - 0 on success - */ -static inline uint32_t hmac_ll_config_error(void) -{ - return REG_READ(HMAC_QUERY_ERROR_REG); -} - -/** - * Wait until the HAL is ready for the next interaction. - */ -static inline void hmac_ll_wait_idle(void) -{ - uint32_t query; - do { - query = REG_READ(HMAC_QUERY_BUSY_REG); - } while(query != 0); -} - -/** - * @brief Write a message block of 512 bits to the HMAC peripheral. - */ -static inline void hmac_ll_write_block_512(const uint32_t *block) -{ - const size_t REG_WIDTH = sizeof(uint32_t); - for (size_t i = 0; i < SHA256_BLOCK_SZ / REG_WIDTH; i++) { - REG_WRITE(HMAC_WDATA_BASE + (i * REG_WIDTH), block[i]); - } - - REG_WRITE(HMAC_SET_MESSAGE_ONE_REG, 1); -} - -/** - * @brief Read the 256 bit HMAC. - */ -static inline void hmac_ll_read_result_256(uint32_t *result) -{ - const size_t REG_WIDTH = sizeof(uint32_t); - for (size_t i = 0; i < SHA256_DIGEST_SZ / REG_WIDTH; i++) { - result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); - } -} - -/** - * @brief Clean the HMAC result provided to other hardware. - */ -static inline void hmac_ll_clean(void) -{ - REG_WRITE(HMAC_SET_INVALIDATE_DS_REG, 1); - REG_WRITE(HMAC_SET_INVALIDATE_JTAG_REG, 1); -} - -/** - * @brief Signals that the following block will be the padded last block. - */ -static inline void hmac_ll_msg_padding(void) -{ - REG_WRITE(HMAC_SET_MESSAGE_PAD_REG, 1); -} - -/** - * @brief Signals that all blocks have been written and a padding block will automatically be applied by hardware. - * - * Only applies if the message length is a multiple of 512 bits. - * See ESP32H4 TRM HMAC chapter for more details. - */ -static inline void hmac_ll_msg_end(void) -{ - REG_WRITE(HMAC_SET_MESSAGE_END_REG, 1); -} - -/** - * @brief The message including padding fits into one block, so no further action needs to be taken. - * - * This is called after the one-block-message has been written. - */ -static inline void hmac_ll_msg_one_block(void) -{ - REG_WRITE(HMAC_ONE_BLOCK_REG, 1); -} - -/** - * @brief Indicate that more blocks will be written after the last block. - */ -static inline void hmac_ll_msg_continue(void) -{ - REG_WRITE(HMAC_SET_MESSAGE_ING_REG, 1); -} - -/** - * @brief Clear the HMAC result. - * - * Use this after reading the HMAC result or if aborting after any of the other steps above. - */ -static inline void hmac_ll_calc_finish(void) -{ - REG_WRITE(HMAC_SET_RESULT_FINISH_REG, 2); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/i2c_ll.h b/components/hal/esp32h4/include/hal/i2c_ll.h deleted file mode 100644 index f5af47eefc..0000000000 --- a/components/hal/esp32h4/include/hal/i2c_ll.h +++ /dev/null @@ -1,946 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for I2C register operations - -#pragma once - -#include "stdbool.h" -#include "hal/misc.h" -#include "soc/i2c_periph.h" -#include "soc/soc_caps.h" -#include "soc/i2c_struct.h" -#include "hal/i2c_types.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/clk_tree_defs.h" -#include "esp_rom_sys.h" -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief I2C hardware cmd register fields. - */ -typedef union { - struct { - uint32_t byte_num: 8, - ack_en: 1, - ack_exp: 1, - ack_val: 1, - op_code: 3, - reserved14: 17, - done: 1; - }; - uint32_t val; -} i2c_ll_hw_cmd_t; - -// I2C operation mode command -#define I2C_LL_CMD_RESTART 6 /*!clkm_div = clkm_div; - clk_cal->scl_low = half_cycle; - // default, scl_wait_high < scl_high - // Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency - // according to some hardware behaviors. - clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4); - clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high; - clk_cal->sda_hold = half_cycle / 4; - clk_cal->sda_sample = half_cycle / 2 + clk_cal->scl_wait_high; - clk_cal->setup = half_cycle; - clk_cal->hold = half_cycle; - //default we set the timeout value to about 10 bus cycles - // log(20*half_cycle)/log(2) = log(half_cycle)/log(2) + log(20)/log(2) - clk_cal->tout = (int)(sizeof(half_cycle) * 8 - __builtin_clz(5 * half_cycle)) + 2; -} - -/** - * @brief Update I2C configuration - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_update(i2c_dev_t *hw) -{ - hw->ctr.conf_upgate = 1; -} - -/** - * @brief Configure the I2C bus timing related register. - * - * @param hw Beginning address of the peripheral registers - * @param bus_cfg Pointer to the data structure holding the register configuration. - * - * @return None - */ -static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); - /* According to the Technical Reference Manual, the following timings must be subtracted by 1. - * However, according to the practical measurement and some hardware behaviour, if wait_high_period and scl_high minus one. - * The SCL frequency would be a little higher than expected. Therefore, the solution - * here is not to minus scl_high as well as scl_wait high, and the frequency will be absolutely accurate to all frequency - * to some extent. */ - hw->scl_low_period.period = bus_cfg->scl_low - 1; - hw->scl_high_period.period = bus_cfg->scl_high; - hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high; - //sda sample - hw->sda_hold.time = bus_cfg->sda_hold - 1; - hw->sda_sample.time = bus_cfg->sda_sample - 1; - //setup - hw->scl_rstart_setup.time = bus_cfg->setup - 1; - hw->scl_stop_setup.time = bus_cfg->setup - 1; - //hold - hw->scl_start_hold.time = bus_cfg->hold - 1; - hw->scl_stop_hold.time = bus_cfg->hold - 1; - hw->timeout.time_out_value = bus_cfg->tout; - hw->timeout.time_out_en = 1; -} - -/** - * @brief Reset I2C txFIFO - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_txfifo_rst(i2c_dev_t *hw) -{ - hw->fifo_conf.tx_fifo_rst = 1; - hw->fifo_conf.tx_fifo_rst = 0; -} - -/** - * @brief Reset I2C rxFIFO - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw) -{ - hw->fifo_conf.rx_fifo_rst = 1; - hw->fifo_conf.rx_fifo_rst = 0; -} - -/** - * @brief Configure I2C SCL timing - * - * @param hw Beginning address of the peripheral registers - * @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2) - * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) - * - * @return None. - */ -static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period) -{ - hw->scl_low_period.period = low_period - 1; - hw->scl_high_period.period = hight_period - 10; - hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.period; -} - -/** - * @brief Clear I2C interrupt status - * - * @param hw Beginning address of the peripheral registers - * @param mask Interrupt mask needs to be cleared - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask) -{ - hw->int_clr.val = mask; -} - -/** - * @brief Enable I2C interrupt - * - * @param hw Beginning address of the peripheral registers - * @param mask Interrupt mask needs to be enabled - * - * @return None - */ -static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask) -{ - hw->int_ena.val |= mask; -} - -/** - * @brief Disable I2C interrupt - * - * @param hw Beginning address of the peripheral registers - * @param mask Interrupt mask needs to be disabled - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_disable_intr_mask(i2c_dev_t *hw, uint32_t mask) -{ - hw->int_ena.val &= (~mask); -} - -/** - * @brief Get I2C interrupt status - * - * @param hw Beginning address of the peripheral registers - * - * @return I2C interrupt status - */ -__attribute__((always_inline)) -static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status) -{ - *intr_status = hw->int_status.val; -} - -/** - * @brief Configure I2C memory access mode, FIFO mode or non-FIFO mode - * - * @param hw Beginning address of the peripheral registers - * @param fifo_mode_en Set true to enable FIFO access mode, else, set it false - * - * @return None - */ -static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en) -{ - hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1; -} - -/** - * @brief Configure I2C timeout - * - * @param hw Beginning address of the peripheral registers - * @param tout_num The I2C timeout value needs to be set (2^tout in core clock cycle) - * - * @return None - */ -static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout) -{ - hw->timeout.time_out_value = tout; -} - -/** - * @brief Configure I2C slave address - * - * @param hw Beginning address of the peripheral registers - * @param slave_addr I2C slave address needs to be set - * @param addr_10bit_en Set true to enable 10-bit slave address mode, set false to enable 7-bit address mode - * - * @return None - */ -static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, bool addr_10bit_en) -{ - hw->slave_addr.addr = slave_addr; - hw->slave_addr.en_10bit = addr_10bit_en; -} - -/** - * @brief Write I2C hardware command register - * - * @param hw Beginning address of the peripheral registers - * @param cmd I2C hardware command - * @param cmd_idx The index of the command register, should be less than 16 - * - * @return None - */ -static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx) -{ - hw->command[cmd_idx].val = cmd.val; -} - -/** - * @brief Configure I2C start timing - * - * @param hw Beginning address of the peripheral registers - * @param start_setup The start condition setup period (in core clock cycle) - * @param start_hold The start condition hold period (in core clock cycle) - * - * @return None - */ -static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold) -{ - hw->scl_rstart_setup.time = start_setup; - hw->scl_start_hold.time = start_hold - 1; -} - -/** - * @brief Configure I2C stop timing - * - * @param hw Beginning address of the peripheral registers - * @param stop_setup The stop condition setup period (in core clock cycle) - * @param stop_hold The stop condition hold period (in core clock cycle) - * - * @return None - */ -static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold) -{ - hw->scl_stop_setup.time = stop_setup; - hw->scl_stop_hold.time = stop_hold; -} - -/** - * @brief Configure I2C stop timing - * - * @param hw Beginning address of the peripheral registers - * @param sda_sample The SDA sample time (in core clock cycle) - * @param sda_hold The SDA hold time (in core clock cycle) - * - * @return None - */ -static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_hold) -{ - hw->sda_hold.time = sda_hold; - hw->sda_sample.time = sda_sample; -} - -/** - * @brief Set I2C txFIFO empty threshold - * - * @param hw Beginning address of the peripheral registers - * @param empty_thr The txFIFO empty threshold - * - * @return None - */ -static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr) -{ - hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr; -} - -/** - * @brief Set I2C rxFIFO full threshold - * - * @param hw Beginning address of the peripheral registers - * @param full_thr The rxFIFO full threshold - * - * @return None - */ -static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr) -{ - hw->fifo_conf.rx_fifo_wm_thrhd = full_thr; -} - -/** - * @brief Set the I2C data mode, LSB or MSB - * - * @param hw Beginning address of the peripheral registers - * @param tx_mode Tx data bit mode - * @param rx_mode Rx data bit mode - * - * @return None - */ -static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode, i2c_trans_mode_t rx_mode) -{ - hw->ctr.tx_lsb_first = tx_mode; - hw->ctr.rx_lsb_first = rx_mode; -} - -/** - * @brief Get the I2C data mode - * - * @param hw Beginning address of the peripheral registers - * @param tx_mode Pointer to accept the received bytes mode - * @param rx_mode Pointer to accept the sended bytes mode - * - * @return None - */ -static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode) -{ - *tx_mode = hw->ctr.tx_lsb_first; - *rx_mode = hw->ctr.rx_lsb_first; -} - -/** - * @brief Get I2C sda timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param sda_sample Pointer to accept the SDA sample timing configuration - * @param sda_hold Pointer to accept the SDA hold timing configuration - * - * @return None - */ -static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold) -{ - *sda_hold = hw->sda_hold.time; - *sda_sample = hw->sda_sample.time; -} - -/** - * @brief Get the I2C hardware version - * - * @param hw Beginning address of the peripheral registers - * - * @return The I2C hardware version - */ -static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw) -{ - return hw->date; -} - -/** - * @brief Check if the I2C bus is busy - * - * @param hw Beginning address of the peripheral registers - * - * @return True if I2C state machine is busy, else false will be returned - */ -static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw) -{ - return hw->sr.bus_busy; -} - -/** - * @brief Check if I2C is master mode - * - * @param hw Beginning address of the peripheral registers - * - * @return True if I2C is master mode, else false will be returned - */ -static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) -{ - return hw->ctr.ms_mode; -} - -/** - * @brief Get the rxFIFO readable length - * - * @param hw Beginning address of the peripheral registers - * - * @return RxFIFO readable length - */ -__attribute__((always_inline)) -static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length) -{ - *length = hw->sr.rx_fifo_cnt; -} - -/** - * @brief Get I2C txFIFO writable length - * - * @param hw Beginning address of the peripheral registers - * - * @return TxFIFO writable length - */ -__attribute__((always_inline)) -static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length) -{ - *length = SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; -} - -/** - * @brief Get I2C timeout configuration - * - * @param hw Beginning address of the peripheral registers - * - * @return The I2C timeout value - */ -static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout) -{ - *timeout = hw->timeout.time_out_value; -} - -/** - * @brief Start I2C transfer - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_trans_start(i2c_dev_t *hw) -{ - hw->ctr.trans_start = 1; -} - -/** - * @brief Get I2C start timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param setup_time Pointer to accept the start condition setup period - * @param hold_time Pointer to accept the start condition hold period - * - * @return None - */ -static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time) -{ - *setup_time = hw->scl_rstart_setup.time; - *hold_time = hw->scl_start_hold.time + 1; -} - -/** - * @brief Get I2C stop timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param setup_time Pointer to accept the stop condition setup period - * @param hold_time Pointer to accept the stop condition hold period - * - * @return None - */ -static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *hold_time) -{ - *setup_time = hw->scl_stop_setup.time; - *hold_time = hw->scl_stop_hold.time; -} - -/** - * @brief Get I2C SCL timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param high_period Pointer to accept the SCL high period - * @param low_period Pointer to accept the SCL low period - * - * @return None - */ -static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period) -{ - *high_period = hw->scl_high_period.period + hw->scl_high_period.scl_wait_high_period; - *low_period = hw->scl_low_period.period + 1; -} - -/** - * @brief Write the I2C hardware txFIFO - * - * @param hw Beginning address of the peripheral registers - * @param ptr Pointer to data buffer - * @param len Amount of data needs to be writen - * - * @return None. - */ -__attribute__((always_inline)) -static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len) -{ - for (int i = 0; i< len; i++) { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]); - } -} - -/** - * @brief Read the I2C hardware rxFIFO - * - * @param hw Beginning address of the peripheral registers - * @param ptr Pointer to data buffer - * @param len Amount of data needs read - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) -{ - for(int i = 0; i < len; i++) { - ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data); - } -} - -/** - * @brief Configure I2C hardware filter - * - * @param hw Beginning address of the peripheral registers - * @param filter_num If the glitch period on the line is less than this value, it can be filtered out - * If `filter_num == 0`, the filter will be disabled - * - * @return None - */ -static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) -{ - if (filter_num > 0) { - hw->filter_cfg.scl_thres = filter_num; - hw->filter_cfg.sda_thres = filter_num; - hw->filter_cfg.scl_en = 1; - hw->filter_cfg.sda_en = 1; - } else { - hw->filter_cfg.scl_en = 0; - hw->filter_cfg.sda_en = 0; - } -} - -/** - * @brief Get I2C hardware filter configuration - * - * @param hw Beginning address of the peripheral registers - * - * @return The hardware filter configuration - */ -static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf) -{ - *filter_conf = hw->filter_cfg.scl_thres; -} - -/** - * @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) -{ - hw->ctr.fsm_rst = 1; -} - -/** - * @brief Clear I2C bus, when the slave is stuck in a deadlock and keeps pulling the bus low, - * master can controls the SCL bus to generate 9 CLKs. - * - * Note: The master cannot detect if deadlock happens, but when the scl_st_to interrupt is generated, a deadlock may occur. - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw) -{ - hw->scl_sp_conf.scl_rst_slv_num = 9; - hw->scl_sp_conf.scl_rst_slv_en = 1; - hw->ctr.conf_upgate = 1; - // hardward will clear scl_rst_slv_en after sending SCL pulses, - // and we should set conf_upgate bit to synchronize register value. - while (hw->scl_sp_conf.scl_rst_slv_en); - hw->ctr.conf_upgate = 1; -} - -/** - * @brief Set I2C source clock - * - * @param hw Beginning address of the peripheral registers - * @param src_clk Source clock of the I2C - * - * @return None - */ -static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_clk) -{ - // src_clk : (1) for RTC_CLK, (0) for XTAL - hw->clk_conf.sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0; -} - -/** - * @brief Enable I2C peripheral controller clock - * - * @param dev Peripheral instance address - * @param en True to enable, False to disable - */ -static inline void i2c_ll_enable_controller_clock(i2c_dev_t *hw, bool en) -{ - hw->clk_conf.sclk_active = en; -} - -/** - * @brief Init I2C master - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_init(i2c_dev_t *hw) -{ - typeof(hw->ctr) ctrl_reg; - ctrl_reg.val = 0; - ctrl_reg.ms_mode = 1; - ctrl_reg.clk_en = 1; - ctrl_reg.sda_force_out = 1; - ctrl_reg.scl_force_out = 1; - hw->ctr.val = ctrl_reg.val; -} - -/** - * @brief Init I2C slave - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_init(i2c_dev_t *hw) -{ - typeof(hw->ctr) ctrl_reg; - ctrl_reg.val = 0; - ctrl_reg.sda_force_out = 1; - ctrl_reg.scl_force_out = 1; - hw->ctr.val = ctrl_reg.val; - hw->fifo_conf.fifo_addr_cfg_en = 0; -} - -/** - * @brief Set whether slave should auto start, or only start with start signal from master - * - * @param hw Beginning address of the peripheral registers - * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0. - */ -static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en) -{ - hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en; -} - -/** - * @brief Get I2C interrupt status register address - */ -static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev) -{ - return &dev->int_status; -} - -//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// -/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// -/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -// I2C master TX interrupt bitmap -#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) -// I2C master RX interrupt bitmap -#define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) -// I2C slave TX interrupt bitmap -#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M) -// I2C slave RX interrupt bitmap -#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) -// I2C max timeout value -#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_REG_V - -#define I2C_LL_INTR_MASK (0xffff) /*!< I2C all interrupt bitmap */ - -/** - * @brief I2C interrupt event - */ -typedef enum { - I2C_INTR_EVENT_ERR, - I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */ - I2C_INTR_EVENT_NACK, /*!< I2C NACK event */ - I2C_INTR_EVENT_TOUT, /*!< I2C time out event */ - I2C_INTR_EVENT_END_DET, /*!< I2C end detected event */ - I2C_INTR_EVENT_TRANS_DONE, /*!< I2C trans done event */ - I2C_INTR_EVENT_RXFIFO_FULL, /*!< I2C rxfifo full event */ - I2C_INTR_EVENT_TXFIFO_EMPTY, /*!< I2C txfifo empty event */ -} i2c_intr_event_t; - -/** - * @brief Configure I2C SCL timing - * - * @param hw Beginning address of the peripheral registers - * @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2) - * @param low_period The I2C SCL low period (in core clock cycle, low_period > 1) - * @param wait_high_period The I2C SCL wait rising edge period. - * - * @return None. - */ -static inline void i2c_ll_set_scl_clk_timing(i2c_dev_t *hw, int high_period, int low_period, int wait_high_period) -{ - hw->scl_low_period.period = low_period; - hw->scl_high_period.period = high_period; - hw->scl_high_period.scl_wait_high_period = wait_high_period; -} - -/** - * @brief Get I2C SCL timing configuration - * - * @param hw Beginning address of the peripheral registers - * @param high_period Pointer to accept the SCL high period - * @param low_period Pointer to accept the SCL low period - * - * @return None - */ -static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, int *low_period, int *wait_high_period) -{ - *high_period = hw->scl_high_period.period; - *wait_high_period = hw->scl_high_period.scl_wait_high_period; - *low_period = hw->scl_low_period.period; -} - -/** - * @brief Get I2C master interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost) { - *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack) { - *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out) { - *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect) { - *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - -/** - * @brief Get I2C slave interrupt event - * - * @param hw Beginning address of the peripheral registers - * @param event Pointer to accept the interrupt event - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) -{ - typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_wm) { - *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete) { - *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_wm) { - *event = I2C_INTR_EVENT_RXFIFO_FULL; - } else { - *event = I2C_INTR_EVENT_ERR; - } -} - -/** - * @brief Enable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = UINT32_MAX; - hw->int_ena.val = I2C_LL_MASTER_TX_INT; -} - -/** - * @brief Enable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_clr.val = UINT32_MAX; - hw->int_ena.val = I2C_LL_MASTER_RX_INT; -} - -/** - * @brief Disable I2C master TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_master_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); -} - -/** - * @brief Disable I2C master RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); -} - -/** - * @brief - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; -} - -/** - * @brief Enable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_enable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; -} - -/** - * @brief Disable I2C slave TX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -__attribute__((always_inline)) -static inline void i2c_ll_slave_disable_tx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); -} - -/** - * @brief Disable I2C slave RX interrupt - * - * @param hw Beginning address of the peripheral registers - * - * @return None - */ -static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw) -{ - hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/i2s_ll.h b/components/hal/esp32h4/include/hal/i2s_ll.h deleted file mode 100644 index c715ad426a..0000000000 --- a/components/hal/esp32h4/include/hal/i2s_ll.h +++ /dev/null @@ -1,1180 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md - ******************************************************************************/ - -// The LL layer for ESP32-H4 I2S register operations - -#pragma once -#include -#include "hal/misc.h" -#include "hal/assert.h" -#include "soc/i2s_periph.h" -#include "soc/i2s_struct.h" -#include "hal/i2s_types.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL) - -#define I2S_LL_TDM_CH_MASK (0xffff) -#define I2S_LL_PDM_BCK_FACTOR (64) - -#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) -#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) - -#define I2S_LL_PLL_F96M_CLK_FREQ (96 * 1000000) // PLL_F96M_CLK: 96MHz -#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F96M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT - -/* I2S clock configuration structure */ -typedef struct { - uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) - uint16_t a; - uint16_t b; // The decimal part of module clock divider, the decimal is: b/a -} i2s_ll_mclk_div_t; - -/** - * @brief I2S module general init, enable I2S clock. - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_enable_clock(i2s_dev_t *hw) -{ - hw->tx_clkm_conf.clk_en = 1; -} - -/** - * @brief I2S module disable I2S clock. - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_disable_clock(i2s_dev_t *hw) -{ - hw->tx_clkm_conf.clk_en = 0; -} - -/** - * @brief Enable I2S tx module clock - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) -{ - hw->tx_clkm_conf.tx_clk_active = 1; -} - -/** - * @brief Enable I2S rx module clock - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) -{ - hw->rx_clkm_conf.rx_clk_active = 1; -} - -/** - * @brief Disable I2S tx module clock - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) -{ - hw->tx_clkm_conf.tx_clk_active = 0; -} - -/** - * @brief Disable I2S rx module clock - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw) -{ - hw->rx_clkm_conf.rx_clk_active = 0; -} - -/** - * @brief I2S mclk use tx module clock - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw) -{ - hw->rx_clkm_conf.mclk_sel = 0; -} - -/** - * @brief I2S mclk use rx module clock - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_mclk_bind_to_rx_clk(i2s_dev_t *hw) -{ - hw->rx_clkm_conf.mclk_sel = 1; -} - -/** - * @brief Enable I2S TX slave mode - * - * @param hw Peripheral I2S hardware instance address. - * @param slave_en Set true to enable slave mode - */ -static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en) -{ - hw->tx_conf.tx_slave_mod = slave_en; -} - -/** - * @brief Enable I2S RX slave mode - * - * @param hw Peripheral I2S hardware instance address. - * @param slave_en Set true to enable slave mode - */ -static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en) -{ - hw->rx_conf.rx_slave_mod = slave_en; -} - -/** - * @brief Reset I2S TX module - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_reset(i2s_dev_t *hw) -{ - hw->tx_conf.tx_reset = 1; - hw->tx_conf.tx_reset = 0; -} - -/** - * @brief Reset I2S RX module - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_reset(i2s_dev_t *hw) -{ - hw->rx_conf.rx_reset = 1; - hw->rx_conf.rx_reset = 0; -} - -/** - * @brief Reset I2S TX FIFO - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_reset_fifo(i2s_dev_t *hw) -{ - hw->tx_conf.tx_fifo_reset = 1; - hw->tx_conf.tx_fifo_reset = 0; -} - -/** - * @brief Reset I2S RX FIFO - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw) -{ - hw->rx_conf.rx_fifo_reset = 1; - hw->rx_conf.rx_fifo_reset = 0; -} - -/** - * @brief Set TX source clock - * - * @param hw Peripheral I2S hardware instance address. - * @param src I2S source clock. - */ -static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) -{ - switch (src) - { - case I2S_CLK_SRC_XTAL: - hw->tx_clkm_conf.tx_clk_sel = 0; - break; - case I2S_CLK_SRC_PLL_96M: - hw->tx_clkm_conf.tx_clk_sel = 2; - break; - default: - HAL_ASSERT(false && "unsupported clock source"); - break; - } -} - -/** - * @brief Set RX source clock - * - * @param hw Peripheral I2S hardware instance address. - * @param src I2S source clock - */ -static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src) -{ - switch (src) - { - case I2S_CLK_SRC_XTAL: - hw->rx_clkm_conf.rx_clk_sel = 0; - break; - case I2S_CLK_SRC_PLL_96M: - hw->rx_clkm_conf.rx_clk_sel = 2; - break; - default: - HAL_ASSERT(false && "unsupported clock source"); - break; - } -} - -/** - * @brief Set I2S tx bck div num - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set tx bck div num - */ -static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) -{ - hw->tx_conf1.tx_bck_div_num = val - 1; -} - -/** - * @brief Set I2S tx raw clock division - * - * @param hw Peripheral I2S hardware instance address. - * @param x div x - * @param y div y - * @param z div z - * @param yn1 yn1 - */ -static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) -{ - hw->tx_clkm_div_conf.tx_clkm_div_x = x; - hw->tx_clkm_div_conf.tx_clkm_div_y = y; - hw->tx_clkm_div_conf.tx_clkm_div_z = z; - hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1; -} - -/** - * @brief Set I2S rx raw clock division - * - * @param hw Peripheral I2S hardware instance address. - * @param x div x - * @param y div y - * @param z div z - * @param yn1 yn1 - */ -static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) -{ - hw->rx_clkm_div_conf.rx_clkm_div_x = x; - hw->rx_clkm_div_conf.rx_clkm_div_y = y; - hw->rx_clkm_div_conf.rx_clkm_div_z = z; - hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1; -} - -/** - * @brief Configure I2S TX module clock divider - * - * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock - * @param mclk module clock - * @param mclk_div integer part of the division from sclk to mclk - */ -static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) -{ - int ma = 0; - int mb = 0; - int denominator = 1; - int numerator = 0; - - uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); - if (!freq_diff) { - goto finish; - } - float decimal = freq_diff / (float)mclk; - // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0 - if (decimal > 125.0 / 126.0) { - mclk_div++; - goto finish; - } - uint32_t min = ~0; - for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) { - int b = (int)(a * (freq_diff / (double)mclk) + 0.5); - ma = freq_diff * a; - mb = mclk * b; - if (ma == mb) { - denominator = a; - numerator = b; - goto finish; - } - if (abs((mb - ma)) < min) { - denominator = a; - numerator = b; - min = abs(mb - ma); - } - } -finish: - if (denominator == 0 || numerator == 0) { - hw->tx_clkm_div_conf.tx_clkm_div_x = 0; - hw->tx_clkm_div_conf.tx_clkm_div_y = 0; - hw->tx_clkm_div_conf.tx_clkm_div_z = 0; - } else { - if (numerator > denominator / 2) { - hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1; - hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator); - hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator; - hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1; - } else { - hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1; - hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator; - hw->tx_clkm_div_conf.tx_clkm_div_z = numerator; - hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0; - } - } - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div); -} - -/** - * @brief Set I2S rx bck div num - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set rx bck div num - */ -static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val) -{ - hw->rx_conf1.rx_bck_div_num = val - 1; -} - -/** - * @brief Configure I2S RX module clock divider - * @note mclk on ESP32 is shared by both TX and RX channel - * - * @param hw Peripheral I2S hardware instance address. - * @param sclk system clock, 0 means use apll - * @param mclk module clock - * @param mclk_div integer part of the division from sclk to mclk - */ -static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) -{ - int ma = 0; - int mb = 0; - int denominator = 1; - int numerator = 0; - - uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); - if (!freq_diff) { - goto finish; - } - float decimal = freq_diff / (float)mclk; - // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0 - if (decimal > 125.0 / 126.0) { - mclk_div++; - goto finish; - } - uint32_t min = ~0; - for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) { - int b = (int)(a * (freq_diff / (double)mclk) + 0.5); - ma = freq_diff * a; - mb = mclk * b; - if (ma == mb) { - denominator = a; - numerator = b; - goto finish; - } - if (abs((mb - ma)) < min) { - denominator = a; - numerator = b; - min = abs(mb - ma); - } - } -finish: - if (denominator == 0 || numerator == 0) { - hw->rx_clkm_div_conf.rx_clkm_div_x = 0; - hw->rx_clkm_div_conf.rx_clkm_div_y = 0; - hw->rx_clkm_div_conf.rx_clkm_div_z = 0; - } else { - if (numerator > denominator / 2) { - hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1; - hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator); - hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator; - hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1; - } else { - hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1; - hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator; - hw->rx_clkm_div_conf.rx_clkm_div_z = numerator; - hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0; - } - } - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div); -} - -/** - * @brief Start I2S TX - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_start(i2s_dev_t *hw) -{ - // Have to update registers before start - hw->tx_conf.tx_update = 1; - while (hw->tx_conf.tx_update); - hw->tx_conf.tx_start = 1; -} - -/** - * @brief Start I2S RX - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_start(i2s_dev_t *hw) -{ - // Have to update registers before start - hw->rx_conf.rx_update = 1; - while (hw->rx_conf.rx_update); - hw->rx_conf.rx_start = 1; -} - -/** - * @brief Stop I2S TX - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_stop(i2s_dev_t *hw) -{ - hw->tx_conf.tx_start = 0; -} - -/** - * @brief Stop I2S RX - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_stop(i2s_dev_t *hw) -{ - hw->rx_conf.rx_start = 0; -} - -/** - * @brief Configure TX WS signal width - * - * @param hw Peripheral I2S hardware instance address. - * @param width WS width in BCK cycle - */ -static inline void i2s_ll_tx_set_ws_width(i2s_dev_t *hw, int width) -{ - hw->tx_conf1.tx_tdm_ws_width = width - 1; -} - -/** - * @brief Configure RX WS signal width - * - * @param hw Peripheral I2S hardware instance address. - * @param width WS width in BCK cycle - */ -static inline void i2s_ll_rx_set_ws_width(i2s_dev_t *hw, int width) -{ - hw->rx_conf1.rx_tdm_ws_width = width - 1; -} - -/** - * @brief Configure the received length to trigger in_suc_eof interrupt - * - * @param hw Peripheral I2S hardware instance address. - * @param eof_num the byte length to trigger in_suc_eof interrupt - */ -static inline void i2s_ll_rx_set_eof_num(i2s_dev_t *hw, int eof_num) -{ - hw->rx_eof_num.rx_eof_num = eof_num; -} - -/** - * @brief Congfigure TX chan bit and audio data bit - * - * @param hw Peripheral I2S hardware instance address. - * @param chan_bit The chan bit width - * @param data_bit The audio data bit width - */ -static inline void i2s_ll_tx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit) -{ - hw->tx_conf1.tx_bits_mod = data_bit - 1; - hw->tx_conf1.tx_tdm_chan_bits = chan_bit - 1; -} - -/** - * @brief Congfigure RX chan bit and audio data bit - * - * @param hw Peripheral I2S hardware instance address. - * @param chan_bit The chan bit width - * @param data_bit The audio data bit width - */ -static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit) -{ - hw->rx_conf1.rx_bits_mod = data_bit - 1; - hw->rx_conf1.rx_tdm_chan_bits = chan_bit - 1; -} - -/** - * @brief Configure RX half_sample_bit - * - * @param hw Peripheral I2S hardware instance address. - * @param half_sample_bits half sample bit width - */ -static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits) -{ - hw->tx_conf1.tx_half_sample_bits = half_sample_bits - 1; -} - -/** - * @brief Configure RX half_sample_bit - * - * @param hw Peripheral I2S hardware instance address. - * @param half_sample_bits half sample bit width - */ -static inline void i2s_ll_rx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits) -{ - hw->rx_conf1.rx_half_sample_bits = half_sample_bits - 1; -} - -/** - * @brief Enable TX MSB shift, the data will be launch at the first BCK clock - * - * @param hw Peripheral I2S hardware instance address. - * @param msb_shift_enable Set true to enable MSB shift - */ -static inline void i2s_ll_tx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable) -{ - hw->tx_conf1.tx_msb_shift = msb_shift_enable; -} - -/** - * @brief Enable RX MSB shift, the data will be launch at the first BCK clock - * - * @param hw Peripheral I2S hardware instance address. - * @param msb_shift_enable Set true to enable MSB shift - */ -static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable) -{ - hw->rx_conf1.rx_msb_shift = msb_shift_enable; -} - -/** - * @brief Configure TX total chan number - * - * @param hw Peripheral I2S hardware instance address. - * @param total_num Total chan number - */ -static inline void i2s_ll_tx_set_chan_num(i2s_dev_t *hw, int total_num) -{ - hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num - 1; -} - -/** - * @brief Configure RX total chan number - * - * @param hw Peripheral I2S hardware instance address. - * @param total_num Total chan number - */ -static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num) -{ - hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1; -} - -/** - * @brief Set the bimap of the active TX chan, only the active chan can launch audio data. - * - * @param hw Peripheral I2S hardware instance address. - * @param chan_mask mask of tx active chan - */ -static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) -{ - typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl; - tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; - tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; - hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val; -} - -/** - * @brief Set the bimap of the active RX chan, only the active chan can receive audio data. - * - * @param hw Peripheral I2S hardware instance address. - * @param chan_mask mask of rx active chan - */ -static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) -{ - typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl; - tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; - tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; - hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val; -} - -/** - * @brief Set I2S tx chan mode - * - * @param hw Peripheral I2S hardware instance address. - * @param slot_mask select slot to send data - */ -static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask) -{ - /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot - * Otherwise always enable the first two slots */ - hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1 - hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; - switch (slot_mask) - { - case I2S_STD_SLOT_LEFT: - hw->tx_tdm_ctrl.val |= 0x01; - break; - case I2S_STD_SLOT_RIGHT: - hw->tx_tdm_ctrl.val |= 0x02; - break; - case I2S_STD_SLOT_BOTH: - hw->tx_tdm_ctrl.val |= 0x03; - break; - default: - break; - } -} - -/** - * @brief Set I2S rx chan mode - * - * @param hw Peripheral I2S hardware instance address. - * @param slot_mask select slot to receive data - */ -static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask) -{ - /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot - * Otherwise always enable the first two slots */ - hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 - hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; - switch (slot_mask) - { - case I2S_STD_SLOT_LEFT: - hw->rx_tdm_ctrl.val |= 0x01; - break; - case I2S_STD_SLOT_RIGHT: - hw->rx_tdm_ctrl.val |= 0x02; - break; - case I2S_STD_SLOT_BOTH: - hw->rx_tdm_ctrl.val |= 0x03; - break; - default: - break; - } -} - -/** - * @brief PDM slot mode - * - * @param hw Peripheral I2S hardware instance address. - * @param mod Channel mode - * while tx_ws_idle_pol = 0: - * 0: stereo - * 1: Both slots transmit left - * 2: Both slots transmit right - * 3: Left transmits `conf_single_data` right transmits data - * 4: Right transmits `conf_single_data` left transmits data - * while tx_ws_idle_pol = 1: - 0: stereo - * 1: Both slots transmit right - * 2: Both slots transmit left - * 3: Right transmits `conf_single_data` left transmits data - * 4: Left transmits `conf_single_data` right transmits data - */ -static inline void i2s_ll_tx_set_pdm_chan_mod(i2s_dev_t *hw, uint32_t mod) -{ - hw->tx_conf.tx_chan_mod = mod; -} - -/** - * @brief Set TX WS signal pol level - * - * @param hw Peripheral I2S hardware instance address. - * @param ws_pol_level pin level of WS(output) when receiving left channel data - */ -static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level) -{ - hw->tx_conf.tx_ws_idle_pol = ws_pol_level; -} - -/** - * @brief Set RX WS signal pol level - * - * @param hw Peripheral I2S hardware instance address. - * @param ws_pol_level pin level of WS(input) when receiving left channel data - */ -static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level) -{ - hw->rx_conf.rx_ws_idle_pol = ws_pol_level; -} - -/** - * @brief Enable I2S TX TDM mode - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_enable_tdm(i2s_dev_t *hw) -{ - hw->tx_conf.tx_pdm_en = false; - hw->tx_conf.tx_tdm_en = true; - hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = false; -} - -/** - * @brief Enable I2S RX TDM mode - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw) -{ - hw->rx_conf.rx_pdm_en = false; - hw->rx_conf.rx_tdm_en = true; -} - -/** - * @brief Enable I2S TX STD mode - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_enable_std(i2s_dev_t *hw) -{ - i2s_ll_tx_enable_tdm(hw); -} - -/** - * @brief Enable I2S RX STD mode - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_enable_std(i2s_dev_t *hw) -{ - i2s_ll_rx_enable_tdm(hw); -} - -/** - * @brief Enable TX PDM mode. - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw) -{ - hw->tx_conf.tx_pdm_en = true; - hw->tx_conf.tx_tdm_en = false; - hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = true; -} - -/** - * @brief Set I2S TX PDM prescale - * - * @param hw Peripheral I2S hardware instance address. - * @param prescale I2S TX PDM prescale - */ -static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale); -} - -/** - * @brief Set I2S TX PDM high pass filter scaling - * - * @param hw Peripheral I2S hardware instance address. - * @param sig_scale I2S TX PDM signal scaling before transmit to the filter - */ -static inline void i2s_ll_tx_set_pdm_hp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) -{ - hw->tx_pcm2pdm_conf.tx_pdm_hp_in_shift = sig_scale; -} - -/** - * @brief Set I2S TX PDM low pass filter scaling - * - * @param hw Peripheral I2S hardware instance address. - * @param sig_scale I2S TX PDM signal scaling before transmit to the filter - */ -static inline void i2s_ll_tx_set_pdm_lp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) -{ - hw->tx_pcm2pdm_conf.tx_pdm_lp_in_shift = sig_scale; -} - -/** - * @brief Set I2S TX PDM sinc filter scaling - * - * @param hw Peripheral I2S hardware instance address. - * @param sig_scale I2S TX PDM signal scaling before transmit to the filter - */ -static inline void i2s_ll_tx_set_pdm_sinc_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) -{ - hw->tx_pcm2pdm_conf.tx_pdm_sinc_in_shift = sig_scale; -} - -/** - * @brief Set I2S TX PDM sigma-delta filter scaling - * - * @param hw Peripheral I2S hardware instance address. - * @param sig_scale I2S TX PDM signal scaling before transmit to the filter - */ -static inline void i2s_ll_tx_set_pdm_sd_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale) -{ - hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_in_shift = sig_scale; -} - -/** - * @brief Set I2S TX PDM high pass filter param0 - * - * @param hw Peripheral I2S hardware instance address. - * @param param The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) - */ -static inline void i2s_ll_tx_set_pdm_hp_filter_param0(i2s_dev_t *hw, uint32_t param) -{ - hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_0 = param; -} - -/** - * @brief Set I2S TX PDM high pass filter param5 - * - * @param hw Peripheral I2S hardware instance address. - * @param param The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) - */ -static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t param) -{ - hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_5 = param; -} - -/** - * @brief Enable I2S TX PDM high pass filter - * - * @param hw Peripheral I2S hardware instance address. - * @param enable Set true to enable I2S TX PDM high pass filter, set false to bypass it - */ -static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable) -{ - hw->tx_pcm2pdm_conf.tx_pdm_hp_bypass = !enable; -} - -/** - * @brief Set I2S TX PDM sigma-delta codec dither - * - * @param hw Peripheral I2S hardware instance address. - * @param dither I2S TX PDM sigmadelta dither value - */ -static inline void i2s_ll_tx_set_pdm_sd_dither(i2s_dev_t *hw, uint32_t dither) -{ - hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither = dither; -} - -/** - * @brief Set I2S TX PDM sigma-delta codec dither - * - * @param hw Peripheral I2S hardware instance address. - * @param dither2 I2S TX PDM sigmadelta dither2 value - */ -static inline void i2s_ll_tx_set_pdm_sd_dither2(i2s_dev_t *hw, uint32_t dither2) -{ - hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither2 = dither2; -} - -/** - * @brief Set the PDM TX over sampling ratio - * - * @param hw Peripheral I2S hardware instance address. - * @param ovr Over sampling ratio - */ -static inline void i2s_ll_tx_set_pdm_over_sample_ratio(i2s_dev_t *hw, uint32_t ovr) -{ - hw->tx_pcm2pdm_conf.tx_pdm_sinc_osr2 = ovr; -} - -/** - * @brief Configure I2S TX PDM sample rate - * Fpdm = 64*Fpcm*fp/fs - * - * @param hw Peripheral I2S hardware instance address. - * @param fp The fp value of TX PDM filter module group0. - * @param fs The fs value of TX PDM filter module group0. - */ -static inline void i2s_ll_tx_set_pdm_fpfs(i2s_dev_t *hw, uint32_t fp, uint32_t fs) -{ - hw->tx_pcm2pdm_conf1.tx_pdm_fp = fp; - hw->tx_pcm2pdm_conf1.tx_pdm_fs = fs; -} - -/** - * @brief Get I2S TX PDM fp configuration paramater - * - * @param hw Peripheral I2S hardware instance address. - * @return - * - fp configuration paramater - */ -static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw) -{ - return hw->tx_pcm2pdm_conf1.tx_pdm_fp; -} - -/** - * @brief Get I2S TX PDM fs configuration paramater - * - * @param hw Peripheral I2S hardware instance address. - * @return - * - fs configuration paramater - */ -static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw) -{ - return hw->tx_pcm2pdm_conf1.tx_pdm_fs; -} - -/** - * @brief Enable RX PDM mode. - * - * @param hw Peripheral I2S hardware instance address. - * @param pdm_enable Set true to RX enable PDM mode - */ -static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable) -{ - // Due to the lack of `PDM to PCM` module on ESP32-H4, PDM RX is not available - HAL_ASSERT(!pdm_enable); - hw->rx_conf.rx_pdm_en = pdm_enable; - hw->rx_conf.rx_tdm_en = !pdm_enable; -} - -/** - * @brief Configura TX a/u-law decompress or compress - * - * @param hw Peripheral I2S hardware instance address. - * @param pcm_cfg PCM configuration paramater - */ -static inline void i2s_ll_tx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg) -{ - hw->tx_conf.tx_pcm_conf = pcm_cfg; - hw->tx_conf.tx_pcm_bypass = !pcm_cfg; -} - -/** - * @brief Configure RX a/u-law decompress or compress - * - * @param hw Peripheral I2S hardware instance address. - * @param pcm_cfg PCM configuration paramater - */ -static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg) -{ - hw->rx_conf.rx_pcm_conf = pcm_cfg; - hw->rx_conf.rx_pcm_bypass = !pcm_cfg; -} - -/** - * @brief Enable TX audio data left alignment - * - * @param hw Peripheral I2S hardware instance address. - * @param ena Set true to enable left alignment - */ -static inline void i2s_ll_tx_enable_left_align(i2s_dev_t *hw, bool ena) -{ - hw->tx_conf.tx_left_align = ena; -} - -/** - * @brief Enable RX audio data left alignment - * - * @param hw Peripheral I2S hardware instance address. - * @param ena Set true to enable left alignment - */ -static inline void i2s_ll_rx_enable_left_align(i2s_dev_t *hw, bool ena) -{ - hw->rx_conf.rx_left_align = ena; -} - -/** - * @brief Enable TX big endian mode - * - * @param hw Peripheral I2S hardware instance address. - * @param ena Set true to enable big endian mode - */ -static inline void i2s_ll_rx_enable_big_endian(i2s_dev_t *hw, bool ena) -{ - hw->rx_conf.rx_big_endian = ena; -} - -/** - * @brief Enable RX big endian mode - * - * @param hw Peripheral I2S hardware instance address. - * @param ena Set true to enable big endian mode - */ -static inline void i2s_ll_tx_enable_big_endian(i2s_dev_t *hw, bool ena) -{ - hw->tx_conf.tx_big_endian = ena; -} - -/** - * @brief Configure TX bit order - * - * @param hw Peripheral I2S hardware instance address. - * @param lsb_order_ena Set true to enable LSB bit order - */ -static inline void i2s_ll_tx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena) -{ - hw->tx_conf.tx_bit_order = lsb_order_ena; -} - -/** - * @brief Configure RX bit order - * - * @param hw Peripheral I2S hardware instance address. - * @param lsb_order_ena Set true to enable LSB bit order - */ -static inline void i2s_ll_rx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena) -{ - hw->rx_conf.rx_bit_order = lsb_order_ena; -} - -/** - * @brief Configure TX skip mask enable - * - * @param hw Peripheral I2S hardware instance address. - * @param skip_mask_ena Set true to skip inactive channels. - */ -static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena) -{ - hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena; -} - - -/** - * @brief Configure single data - * - * @param hw Peripheral I2S hardware instance address. - * @param data Single data to be set - */ -static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data) -{ - hw->conf_single_data = data; -} - -/** - * @brief Enable loopback mode - * - * @param hw Peripheral I2S hardware instance address. - * @param ena Set true to share BCK and WS signal for tx module and rx module. - */ -static inline void i2s_ll_share_bck_ws(i2s_dev_t *hw, bool ena) -{ - hw->tx_conf.sig_loopback = ena; -} - -/** - * @brief Set I2S pdm2pcm conv en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set pdm2pcm conv en - */ -static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) -{ - abort(); // TODO ESP32-H4 IDF-2098 - -} - -/** - * @brief Enable TX mono mode - * @note MONO in hardware means only one channel got data, but another doesn't - * MONO in software means two channel share same data - * This function aims to use MONO in software meaning - * so 'tx_mono' and 'tx_chan_equal' should be enabled at the same time - * - * @param hw Peripheral I2S hardware instance address. - * @param mono_ena Set true to enable mono mde. - */ -static inline void i2s_ll_tx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena) -{ - hw->tx_conf.tx_mono = mono_ena; - hw->tx_conf.tx_chan_equal = mono_ena; -} - -/** - * @brief Enable RX mono mode - * - * @param hw Peripheral I2S hardware instance address. - * @param mono_ena Set true to enable mono mde. - */ -static inline void i2s_ll_rx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena) -{ - hw->rx_conf.rx_mono = mono_ena; - hw->rx_conf.rx_mono_fst_vld = mono_ena; -} - -/** - * @brief PDM TX DMA data take mode - * - * @param hw Peripheral I2S hardware instance address. - * @param is_mono The DMA data only has one slot (mono) or contains two slots (stereo) - * @param is_fst_valid Whether take the DMA data at the first half period - * Only take effet when 'is_mono' is true - */ -static inline void i2s_ll_tx_pdm_dma_take_mode(i2s_dev_t *hw, bool is_mono, bool is_fst_valid) -{ - hw->tx_conf.tx_mono = is_mono; - hw->tx_conf.tx_mono_fst_vld = is_fst_valid; -} - -/** - * @brief PDM TX slot mode - * @note Mode Left Slot Right Slot Chan Mode WS Pol - * ----------------------------------------------------------------- - * Stereo Left Right 0 x - * ----------------------------------------------------------------- - * Mono Left Left 1 0 - * Mono Right Right 2 0 - * Mono Single Right 3 0 - * Mono Left Single 4 0 - * ----------------------------------------------------------------- - * Mono Right Right 1 1 - * Mono Left Left 2 1 - * Mono Left Single 3 1 - * Mono Single Right 4 1 - * @note The 'Single' above means always sending the value of `conf_single_data` reg - * The default value of `conf_single_data` reg is '0', it is not public for now - * - * @param hw Peripheral I2S hardware instance address. - * @param is_mono The DMA data only has one slot (mono) or contains two slots (stereo) - * @param is_copy Whether the un-selected slot copies the data from the selected one - * If not, the un-selected slot will transmit the data from 'conf_single_data' - * @param mask The slot mask to selet the slot - */ -static inline void i2s_ll_tx_pdm_slot_mode(i2s_dev_t *hw, bool is_mono, bool is_copy, i2s_pdm_slot_mask_t mask) -{ - if (is_mono) { - /* The default tx_ws_idle_pol is false */ - if (is_copy) { - hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2; - } else { - hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3; - } - } else { - hw->tx_conf.tx_chan_mod = 0; - } -} - -/** - * @brief PDM TX line mode - * @note Mode DAC Mode 2 lines output - * ------------------------------------------- - * PDM codec 0 1 - * DAC 1-line 1 0 - * DAC 2-line 1 1 - * - * @param hw Peripheral I2S hardware instance address. - * @param line_mode PDM TX line mode - */ -static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode) -{ - hw->tx_pcm2pdm_conf.tx_pdm_dac_mode_en = line_mode > I2S_PDM_TX_ONE_LINE_CODEC; - hw->tx_pcm2pdm_conf.tx_pdm_dac_2out_en = line_mode != I2S_PDM_TX_ONE_LINE_DAC; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/ledc_ll.h b/components/hal/esp32h4/include/hal/ledc_ll.h deleted file mode 100644 index 0edca33890..0000000000 --- a/components/hal/esp32h4/include/hal/ledc_ll.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for LEDC register operations. -// Note that most of the register operations in this layer are non-atomic operations. - -#pragma once - -#include "hal/ledc_types.h" -#include "soc/ledc_periph.h" -#include "soc/ledc_struct.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define LEDC_LL_GET_HW() &LEDC - -#define LEDC_LL_DUTY_NUM_MAX (LEDC_DUTY_NUM_LSCH0_V) -#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_LSCH0_V) -#define LEDC_LL_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_LSCH0_V) -#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH0_V) -#define LEDC_LL_FRACTIONAL_BITS (8) -#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) - -#define LEDC_LL_GLOBAL_CLOCKS { \ - LEDC_SLOW_CLK_APB, \ - LEDC_SLOW_CLK_XTAL, \ - LEDC_SLOW_CLK_RC_FAST, \ - } - -#define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST - -/** - * @brief Set LEDC low speed timer clock - * - * @param hw Beginning address of the peripheral registers - * @param slow_clk_sel LEDC low speed timer clock source - * - * @return None - */ -static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel) -{ - uint32_t clk_sel_val = 0; - if (slow_clk_sel == LEDC_SLOW_CLK_APB) { - clk_sel_val = 1; - } else if (slow_clk_sel == LEDC_SLOW_CLK_RC_FAST) { - clk_sel_val = 2; - } else if (slow_clk_sel == LEDC_SLOW_CLK_XTAL) { - clk_sel_val = 3; - } - hw->conf.apb_clk_sel = clk_sel_val; -} - -/** - * @brief Get LEDC low speed timer clock - * - * @param hw Beginning address of the peripheral registers - * @param slow_clk_sel LEDC low speed timer clock source - * - * @return None - */ -static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel) -{ - uint32_t clk_sel_val = hw->conf.apb_clk_sel; - if (clk_sel_val == 1) { - *slow_clk_sel = LEDC_SLOW_CLK_APB; - } else if (clk_sel_val == 2) { - *slow_clk_sel = LEDC_SLOW_CLK_RC_FAST; - } else if (clk_sel_val == 3) { - *slow_clk_sel = LEDC_SLOW_CLK_XTAL; - } else { - abort(); - } -} - -/** - * @brief Update LEDC low speed timer - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * - * @return None - */ -static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) -{ - hw->timer_group[speed_mode].timer[timer_sel].conf.low_speed_update = 1; -} - -/** - * @brief Reset LEDC timer - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * - * @return None - */ -static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) -{ - hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1; - hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0; -} - -/** - * @brief Pause LEDC timer - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * - * @return None - */ -static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) -{ - hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1; -} - -/** - * @brief Resume LEDC timer - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * - * @return None - */ -static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) -{ - hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0; -} - -/** - * @brief Set LEDC timer clock divider - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source - * - * @return None - */ -static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider) -{ - hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider = clock_divider; -} - -/** - * @brief Get LEDC timer clock divider - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source - * - * @return None - */ -static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider) -{ - *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider; -} - -/** - * @brief Get LEDC timer clock source - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * @param clk_src Pointer to accept the timer clock source - * - * @return None - */ -static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) -{ - *clk_src = LEDC_APB_CLK; -} - -/** - * @brief Set LEDC duty resolution - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)] - * - * @return None - */ -static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution) -{ - hw->timer_group[speed_mode].timer[timer_sel].conf.duty_resolution = duty_resolution; -} - -/** - * @brief Get LEDC duty resolution - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * @param duty_resolution Pointer to accept the resolution of duty setting in number of bits. - * - * @return None - */ -static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution) -{ - *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_resolution; -} - -/** - * @brief Update channel configure when select low speed mode - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * - * @return None - */ -static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) -{ - hw->channel_group[speed_mode].channel[channel_num].conf0.low_speed_update = 1; -} - -/** - * @brief Get LEDC max duty - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param max_duty Pointer to accept the max duty - * - * @return None - */ -static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *max_duty) -{ - uint32_t timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel; - *max_duty = (1 << (LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_resolution)); -} - -/** - * @brief Set LEDC hpoint value - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param hpoint_val LEDC hpoint value(max: 0xfffff) - * - * @return None - */ -static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val) -{ - hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; -} - -/** - * @brief Get LEDC hpoint value - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff) - * - * @return None - */ -static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val) -{ - *hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint; -} - -/** - * @brief Set LEDC the integer part of duty value - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)] - * - * @return None - */ -static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val) -{ - hw->channel_group[speed_mode].channel[channel_num].duty.duty = duty_val << 4; -} - -/** - * @brief Get LEDC duty value - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_val Pointer to accept the LEDC duty value - * - * @return None - */ -static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) -{ - *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_rd.duty_read >> 4); -} - -/** - * @brief Set LEDC duty change direction - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_direction LEDC duty change direction, increase or decrease - * - * @return None - */ -static inline void ledc_ll_set_duty_direction(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_duty_direction_t duty_direction) -{ - hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc = duty_direction; -} - -/** - * @brief Get LEDC duty change direction - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_direction Pointer to accept the LEDC duty change direction, increase or decrease - * - * @return None - */ -static inline void ledc_ll_get_duty_direction(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_duty_direction_t *duty_direction) -{ - *duty_direction = hw->channel_group[speed_mode].channel[channel_num].conf1.duty_inc; -} - -/** - * @brief Set the number of increased or decreased times - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_num The number of increased or decreased times - * - * @return None - */ -static inline void ledc_ll_set_duty_num(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_num) -{ - hw->channel_group[speed_mode].channel[channel_num].conf1.duty_num = duty_num; -} - -/** - * @brief Set the duty cycles of increase or decrease - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_cycle The duty cycles - * - * @return None - */ -static inline void ledc_ll_set_duty_cycle(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_cycle) -{ - hw->channel_group[speed_mode].channel[channel_num].conf1.duty_cycle = duty_cycle; -} - -/** - * @brief Set the step scale of increase or decrease - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_scale The step scale - * - * @return None - */ -static inline void ledc_ll_set_duty_scale(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_scale) -{ - hw->channel_group[speed_mode].channel[channel_num].conf1.duty_scale = duty_scale; -} - -/** - * @brief Set the output enable - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param sig_out_en The output enable status - * - * @return None - */ -static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en) -{ - hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en; -} - -/** - * @brief Set the duty start - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_start The duty start - * - * @return None - */ -static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool duty_start) -{ - hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; -} - -/** - * @brief Set output idle level - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param idle_level The output idle level - * - * @return None - */ -static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level) -{ - hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1; -} - -/** - * @brief Set fade end interrupt enable - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param fade_end_intr_en The fade end interrupt enable status - * - * @return None - */ -static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en) -{ - uint32_t value = hw->int_ena.val; - uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; - hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num)))); -} - -/** - * @brief Get fade end interrupt status - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param intr_status The fade end interrupt status - * - * @return None - */ -static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status) -{ - uint32_t value = hw->int_st.val; - uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; - *intr_status = (value >> int_en_base) & 0xff; -} - -/** - * @brief Clear fade end interrupt status - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * - * @return None - */ -static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) -{ - uint32_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; - hw->int_clr.val = BIT(int_en_base + channel_num); -} - -/** - * @brief Set timer index of the specified channel - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t - * - * @return None - */ -static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel) -{ - hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel; -} - -/** - * @brief Get timer index of the specified channel - * - * @param hw Beginning address of the peripheral registers - * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param timer_sel Pointer to accept the LEDC timer index - * - * @return None - */ -static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel) -{ - *timer_sel = hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/memprot_ll.h b/components/hal/esp32h4/include/hal/memprot_ll.h deleted file mode 100644 index 244d6f2213..0000000000 --- a/components/hal/esp32h4/include/hal/memprot_ll.h +++ /dev/null @@ -1,564 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/sensitive_reg.h" -#include "soc/ext_mem_defs.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* ****************************************************************************************************** - * *** GLOBALS *** - * NOTE: in this version, all the configurations apply only to WORLD_0 - */ - -#define IRAM_SRAM_START 0x4037C000 -#define DRAM_SRAM_START 0x3FC7C000 - -/* ICache size is fixed to 16KB on ESP32-H4 */ -#ifndef ICACHE_SIZE -#define ICACHE_SIZE 0x4000 -#endif - -#ifndef I_D_SRAM_SEGMENT_SIZE -#define I_D_SRAM_SEGMENT_SIZE 0x20000 -#endif - -#define I_D_SPLIT_LINE_SHIFT 0x9 -#define I_D_FAULT_ADDR_SHIFT 0x2 - -static inline void memprot_ll_set_iram0_dram0_split_line_lock(void) -{ - REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, 1); -} - -static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void) -{ - return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; -} - -static inline void* memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t base) -{ - return (void*) - (base + ((regval & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M) - >> (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S - I_D_SPLIT_LINE_SHIFT))); -} - -/* ****************************************************************************************************** - * *** IRAM0 *** - */ - -//16kB (CACHE) -#define IRAM0_SRAM_LEVEL_0_LOW IRAM_SRAM_START //0x40370000 -#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x4037FFFF - -//128kB (LEVEL 1) -#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 -#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF - -//128kB (LEVEL 2) -#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 -#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF - -//128kB (LEVEL 3) -#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 -#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF - -//permission bits -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F 0x4 - -static inline uint32_t memprot_ll_iram0_get_intr_source_num(void) -{ - return ETS_CORE0_IRAM0_PMS_INTR_SOURCE; -} - - -/////////////////////////////////// -// IRAM0 - SPLIT LINES -/////////////////////////////////// - -static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg) -{ - uint32_t addr = (uint32_t)line_addr; - HAL_ASSERT( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH ); - - uint32_t category[3] = {0}; - if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) { - category[0] = 0x2; - category[1] = category[2] = 0x3; - } else if (addr >= IRAM0_SRAM_LEVEL_2_LOW && addr <= IRAM0_SRAM_LEVEL_2_HIGH) { - category[1] = 0x2; - category[2] = 0x3; - } else { - category[2] = 0x2; - } - - //NOTE: category & split line address bits are the same for all the areas - uint32_t category_bits = - (category[0] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) | - (category[1] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) | - (category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S); - - uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S; - - uint32_t reg_cfg = conf_addr | category_bits; - - REG_WRITE(sensitive_reg, reg_cfg); -} - -/* can be both IRAM0/DRAM0 address */ -static inline void memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr) -{ - memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG); -} - -static inline void memprot_ll_set_iram0_split_line_I_0(const void *line_addr) -{ - memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); -} - -static inline void memprot_ll_set_iram0_split_line_I_1(const void *line_addr) -{ - memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); -} - -static inline void* memprot_ll_get_iram0_split_line_main_I_D(void) -{ - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG), SOC_DIRAM_IRAM_LOW); -} - -static inline void* memprot_ll_get_iram0_split_line_I_0(void) -{ - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_IRAM_LOW); -} - -static inline void* memprot_ll_get_iram0_split_line_I_1(void) -{ - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_IRAM_LOW); -} - - -/////////////////////////////////// -// IRAM0 - PMS CONFIGURATION -/////////////////////////////////// - -// lock -static inline void memprot_ll_iram0_set_pms_lock(void) -{ - REG_WRITE(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG, 1); -} - -static inline bool memprot_ll_iram0_get_pms_lock(void) -{ - return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1; -} - -// permission settings -static inline uint32_t memprot_ll_iram0_set_permissions(bool r, bool w, bool x) -{ - uint32_t permissions = 0; - if ( r ) { - permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; - } - if ( w ) { - permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; - } - if ( x ) { - permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F; - } - - return permissions; -} - -static inline void memprot_ll_iram0_set_pms_area_0(bool r, bool w, bool x) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_iram0_set_permissions(r, w, x)); -} - -static inline void memprot_ll_iram0_set_pms_area_1(bool r, bool w, bool x) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_iram0_set_permissions(r, w, x)); -} - -static inline void memprot_ll_iram0_set_pms_area_2(bool r, bool w, bool x) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_iram0_set_permissions(r, w, x)); -} - -static inline void memprot_ll_iram0_set_pms_area_3(bool r, bool w, bool x) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_iram0_set_permissions(r, w, x)); -} - -static inline void memprot_ll_iram0_get_permissions(uint32_t perms, bool *r, bool *w, bool *x) -{ - *r = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; - *w = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; - *x = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F; -} - -static inline void memprot_ll_iram0_get_pms_area_0(bool *r, bool *w, bool *x) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0); - memprot_ll_iram0_get_permissions( permissions, r, w, x); -} - -static inline void memprot_ll_iram0_get_pms_area_1(bool *r, bool *w, bool *x) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1); - memprot_ll_iram0_get_permissions( permissions, r, w, x); -} - -static inline void memprot_ll_iram0_get_pms_area_2(bool *r, bool *w, bool *x) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2); - memprot_ll_iram0_get_permissions( permissions, r, w, x); -} - -static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3); - memprot_ll_iram0_get_permissions( permissions, r, w, x); -} - - -/////////////////////////////////// -// IRAM0 - MONITOR -/////////////////////////////////// - -// lock -static inline void memprot_ll_iram0_set_monitor_lock(void) -{ - REG_WRITE(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG, 1); -} - -static inline bool memprot_ll_iram0_get_monitor_lock(void) -{ - return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; -} - -// interrupt enable/clear -static inline void memprot_ll_iram0_set_monitor_en(bool enable) -{ - if ( enable ) { - REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ); - } else { - REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ); - } -} - -static inline bool memprot_ll_iram0_get_monitor_en(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ) == 1; -} - -static inline void memprot_ll_iram0_clear_monitor_intr(void) -{ - REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR ); -} - -static inline void memprot_ll_iram0_reset_clear_monitor_intr(void) -{ - REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR ); -} - -static inline uint32_t memprot_ll_iram0_get_monitor_enable_register(void) -{ - return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); -} - -// // permission violation status -static inline uint32_t memprot_ll_iram0_get_monitor_status_intr(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR ); -} - -static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_wr(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR ); -} - -static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_loadstore(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE ); -} - -static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_world(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD ); -} - -static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_addr(void) -{ - uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR ); - return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0; -} - -static inline uint32_t memprot_ll_iram0_get_monitor_status_register(void) -{ - return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); -} - - -/* ****************************************************************************************************** - * *** DRAM0 *** - */ - -//cache not available from DRAM (!) -#define DRAM0_SRAM_LEVEL_0_LOW DRAM_SRAM_START //0x3FC7C000 -#define DRAM0_SRAM_LEVEL_0_HIGH (DRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x3FC7FFFF - -//128kB -#define DRAM0_SRAM_LEVEL_1_LOW (DRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x3FC80000 -#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF - -//128kB -#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 -#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF - -//128kB -#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 -#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF - -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1 - - -static inline uint32_t memprot_ll_dram0_get_intr_source_num(void) -{ - return ETS_CORE0_DRAM0_PMS_INTR_SOURCE; -} - - -/////////////////////////////////// -// DRAM0 - SPLIT LINES -/////////////////////////////////// - -static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg) -{ - uint32_t addr = (uint32_t)line_addr; - HAL_ASSERT( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH ); - - uint32_t category[3] = {0}; - if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) { - category[0] = 0x2; - category[1] = category[2] = 0x3; - } else if (addr >= DRAM0_SRAM_LEVEL_2_LOW && addr <= DRAM0_SRAM_LEVEL_2_HIGH) { - category[1] = 0x2; - category[2] = 0x3; - } else { - category[2] = 0x2; - } - - //NOTE: line address & category bits, shifts and masks are the same for all the areas - uint32_t category_bits = - (category[0] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) | - (category[1] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) | - (category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S); - - uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S; - - uint32_t reg_cfg = conf_addr | category_bits; - - REG_WRITE(sensitive_reg, reg_cfg); -} - -static inline void memprot_ll_set_dram0_split_line_D_0(const void *line_addr) -{ - memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); -} - -static inline void memprot_ll_set_dram0_split_line_D_1(const void *line_addr) -{ - memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); -} - -static inline void* memprot_ll_get_dram0_split_line_D_0(void) -{ - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_DRAM_LOW); -} - -static inline void* memprot_ll_get_dram0_split_line_D_1(void) -{ - return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_DRAM_LOW); -} - - -/////////////////////////////////// -// DRAM0 - PMS CONFIGURATION -/////////////////////////////////// - -// lock -static inline void memprot_ll_dram0_set_pms_lock(void) -{ - REG_WRITE(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG, 1); -} - -static inline bool memprot_ll_dram0_get_pms_lock(void) -{ - return REG_READ(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG) == 1; -} - -// permission settings -static inline uint32_t memprot_ll_dram0_set_permissions(bool r, bool w) -{ - uint32_t permissions = 0; - if ( r ) { - permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; - } - if ( w ) { - permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; - } - - return permissions; -} - -static inline void memprot_ll_dram0_set_pms_area_0(bool r, bool w) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_dram0_set_permissions(r, w)); -} - -static inline void memprot_ll_dram0_set_pms_area_1(bool r, bool w) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_dram0_set_permissions(r, w)); -} - -static inline void memprot_ll_dram0_set_pms_area_2(bool r, bool w) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_dram0_set_permissions(r, w)); -} - -static inline void memprot_ll_dram0_set_pms_area_3(bool r, bool w) -{ - REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_dram0_set_permissions(r, w)); -} - -static inline void memprot_ll_dram0_get_permissions(uint32_t perms, bool *r, bool *w ) -{ - *r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R; - *w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W; -} - -static inline void memprot_ll_dram0_get_pms_area_0(bool *r, bool *w) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0); - memprot_ll_dram0_get_permissions( permissions, r, w); -} - -static inline void memprot_ll_dram0_get_pms_area_1(bool *r, bool *w) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1); - memprot_ll_dram0_get_permissions( permissions, r, w); -} - -static inline void memprot_ll_dram0_get_pms_area_2(bool *r, bool *w) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2); - memprot_ll_dram0_get_permissions( permissions, r, w); -} - -static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w) -{ - uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3); - memprot_ll_dram0_get_permissions( permissions, r, w); -} - -/////////////////////////////////// -// DRAM0 - MONITOR -/////////////////////////////////// - -// lock -static inline void memprot_ll_dram0_set_monitor_lock(void) -{ - REG_WRITE(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG, 1); -} - -static inline bool memprot_ll_dram0_get_monitor_lock(void) -{ - return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1; -} - -// interrupt enable/clear -static inline void memprot_ll_dram0_set_monitor_en(bool enable) -{ - if ( enable ) { - REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ); - } else { - REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ); - } -} - -static inline bool memprot_ll_dram0_get_monitor_en(void) -{ - return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ) == 1; -} - -static inline void memprot_ll_dram0_clear_monitor_intr(void) -{ - REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR ); -} - -static inline void memprot_ll_dram0_reset_clear_monitor_intr(void) -{ - REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR ); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_enable_register(void) -{ - return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG); -} - -// permission violation status -static inline uint32_t memprot_ll_dram0_get_monitor_status_intr(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR ); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_lock(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK ); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_world(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD ); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_addr(void) -{ - uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR ); - return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + DRAM0_ADDRESS_LOW : 0; -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_wr(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR ); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_byte_en(void) -{ - return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN ); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_register_1(void) -{ - return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG); -} - -static inline uint32_t memprot_ll_dram0_get_monitor_status_register_2(void) -{ - return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/mmu_ll.h b/components/hal/esp32h4/include/hal/mmu_ll.h deleted file mode 100644 index 45ad59928f..0000000000 --- a/components/hal/esp32h4/include/hal/mmu_ll.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for MMU register operations - -#pragma once - -#include "esp_types.h" -#include "soc/extmem_reg.h" -#include "soc/ext_mem_defs.h" -#include "hal/assert.h" -#include "hal/mmu_types.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Convert MMU virtual address to linear address - * - * @param vaddr virtual address - * - * @return linear address - */ -static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) -{ - return vaddr & SOC_MMU_LINEAR_ADDR_MASK; -} - -/** - * Convert MMU linear address to virtual address - * - * @param laddr linear address - * @param vaddr_type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` - * - * @return virtual address - */ -static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type) -{ - uint32_t vaddr_base = 0; - if (vaddr_type == MMU_VADDR_DATA) { - vaddr_base = SOC_MMU_DBUS_VADDR_BASE; - } else { - vaddr_base = SOC_MMU_IBUS_VADDR_BASE; - } - - return vaddr_base | laddr; -} - -/** - * Get MMU page size - * - * @param mmu_id MMU ID - * - * @return MMU page size code - */ -__attribute__((always_inline)) -static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id) -{ - (void)mmu_id; - //On esp32h4, MMU page size is always 64KB - return MMU_PAGE_64KB; -} - -/** - * Set MMU page size - * - * @param size MMU page size - * - * @note On esp32h4, only supports `MMU_PAGE_64KB` - */ -__attribute__((always_inline)) -static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size) -{ - HAL_ASSERT(size == MMU_PAGE_64KB); -} - -/** - * Check if the external memory vaddr region is valid - * - * @param mmu_id MMU ID - * @param vaddr_start start of the virtual address - * @param len length, in bytes - * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` - * - * @return - * True for valid - */ -__attribute__((always_inline)) -static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type) -{ - (void)mmu_id; - uint32_t vaddr_end = vaddr_start + len - 1; - bool valid = false; - - if (type & MMU_VADDR_INSTRUCTION) { - valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)); - } - - if (type & MMU_VADDR_DATA) { - valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end)); - } - - return valid; -} - -/** - * Check if the paddr region is valid - * - * @param mmu_id MMU ID - * @param paddr_start start of the physical address - * @param len length, in bytes - * - * @return - * True for valid - */ -static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len) -{ - (void)mmu_id; - return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && - (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) && - ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)); -} - -/** - * To get the MMU table entry id to be mapped - * - * @param mmu_id MMU ID - * @param vaddr virtual address to be mapped - * - * @return - * MMU table entry id - */ -__attribute__((always_inline)) -static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) -{ - (void)mmu_id; - return ((vaddr & MMU_VADDR_MASK) >> 16); -} - -/** - * Format the paddr to be mappable - * - * @param mmu_id MMU ID - * @param paddr physical address to be mapped - * @param target paddr memory target, not used - * - * @return - * mmu_val - paddr in MMU table supported format - */ -__attribute__((always_inline)) -static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target) -{ - (void)mmu_id; - (void)target; - return paddr >> 16; -} - -/** - * Write to the MMU table to map the virtual memory and the physical memory - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - * @param mmu_val Value to be set into an MMU entry, for physical address - * @param target MMU target physical memory. - */ -__attribute__((always_inline)) -static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target) -{ - (void)mmu_id; - HAL_ASSERT(target == MMU_TARGET_FLASH0); - HAL_ASSERT(entry_id < MMU_ENTRY_NUM); - - *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; -} - -/** - * Read the raw value from MMU table - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - * @param mmu_val Value to be read from MMU table - */ -__attribute__((always_inline)) -static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id) -{ - (void)mmu_id; - HAL_ASSERT(entry_id < MMU_ENTRY_NUM); - - return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4); -} - -/** - * Set MMU table entry as invalid - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - */ -__attribute__((always_inline)) -static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id) -{ - (void)mmu_id; - HAL_ASSERT(entry_id < MMU_ENTRY_NUM); - - *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; -} - -/** - * Unmap all the items in the MMU table - * - * @param mmu_id MMU ID - */ -__attribute__((always_inline)) -static inline void mmu_ll_unmap_all(uint32_t mmu_id) -{ - for (int i = 0; i < MMU_ENTRY_NUM; i++) { - mmu_ll_set_entry_invalid(mmu_id, i); - } -} - -/** - * Check MMU table entry value is valid - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - * - * @return Ture for MMU entry is valid; False for invalid - */ -static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id) -{ - (void)mmu_id; - HAL_ASSERT(entry_id < MMU_ENTRY_NUM); - - return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true; -} - -/** - * Get the MMU table entry target - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - * - * @return Target, see `mmu_target_t` - */ -static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id) -{ - (void)mmu_id; - HAL_ASSERT(entry_id < MMU_ENTRY_NUM); - - return MMU_TARGET_FLASH0; -} - -/** - * Convert MMU entry ID to paddr base - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - * - * @return paddr base - */ -static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id) -{ - (void)mmu_id; - HAL_ASSERT(entry_id < MMU_ENTRY_NUM); - - return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; -} - -/** - * Find the MMU table entry ID based on table map value - * @note This function can only find the first match entry ID. However it is possible that a physical address - * is mapped to multiple virtual addresses - * - * @param mmu_id MMU ID - * @param mmu_val map value to be read from MMU table standing for paddr - * @param target physical memory target, see `mmu_target_t` - * - * @return MMU entry ID, -1 for invalid - */ -static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target) -{ - (void)mmu_id; - for (int i = 0; i < MMU_ENTRY_NUM; i++) { - if (mmu_ll_check_entry_valid(mmu_id, i)) { - if (mmu_ll_get_entry_target(mmu_id, i) == target) { - if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { - return i; - } - } - } - } - - return -1; -} - -/** - * Convert MMU entry ID to vaddr base - * - * @param mmu_id MMU ID - * @param entry_id MMU entry ID - * @param type virtual address type, could be instruction type or data type. See `mmu_vaddr_t` - */ -static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type) -{ - (void)mmu_id; - uint32_t laddr = entry_id << 16; - - return mmu_ll_laddr_to_vaddr(laddr, type); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/mpu_ll.h b/components/hal/esp32h4/include/hal/mpu_ll.h deleted file mode 100644 index c1131ef593..0000000000 --- a/components/hal/esp32h4/include/hal/mpu_ll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include "soc/soc_caps.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* This LL is currently unused for ESP32-H4 - IDF-2375 */ - -static inline uint32_t mpu_ll_id_to_addr(unsigned id) -{ - abort(); -} - -static inline void mpu_ll_set_region_rw(uint32_t addr) -{ - abort(); -} - -static inline void mpu_ll_set_region_rwx(uint32_t addr) -{ - abort(); -} - -static inline void mpu_ll_set_region_x(uint32_t addr) -{ - abort(); -} - - -static inline void mpu_ll_set_region_illegal(uint32_t addr) -{ - abort(); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/mwdt_ll.h b/components/hal/esp32h4/include/hal/mwdt_ll.h deleted file mode 100644 index bf34716165..0000000000 --- a/components/hal/esp32h4/include/hal/mwdt_ll.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for Timer Group register operations. -// Note that most of the register operations in this layer are non-atomic operations. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "soc/timer_periph.h" -#include "soc/timer_group_struct.h" -#include "hal/wdt_types.h" -#include "hal/assert.h" -#include "esp_attr.h" -#include "esp_assert.h" -#include "hal/misc.h" - -/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */ -#define MWDT_LL_DEFAULT_CLK_PRESCALER 40000 - -//Type check wdt_stage_action_t -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -//Type check wdt_reset_sig_length_t -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); - -/** - * @brief Enable the MWDT - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw) -{ - hw->wdtconfig0.wdt_en = 1; -} - -/** - * @brief Disable the MWDT - * - * @param hw Start address of the peripheral registers. - * @note This function does not disable the flashboot mode. Therefore, given that - * the MWDT is disabled using this function, a timeout can still occur - * if the flashboot mode is simultaneously enabled. - */ -FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw) -{ - hw->wdtconfig0.wdt_en = 0; -} - -/** - * Check if the MWDT is enabled - * - * @param hw Start address of the peripheral registers. - * @return True if the MWDT is enabled, false otherwise - */ -FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw) -{ - return (hw->wdtconfig0.wdt_en) ? true : false; -} - -/** - * @brief Configure a particular stage of the MWDT - * - * @param hw Start address of the peripheral registers. - * @param stage Which stage to configure - * @param timeout Number of timer ticks for the stage to timeout - * @param behavior What action to take when the stage times out - */ -FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior) -{ - switch (stage) { - case WDT_STAGE0: - hw->wdtconfig0.wdt_stg0 = behavior; - hw->wdtconfig2.wdt_stg0_hold = timeout; - break; - case WDT_STAGE1: - hw->wdtconfig0.wdt_stg1 = behavior; - hw->wdtconfig3.wdt_stg1_hold = timeout; - break; - case WDT_STAGE2: - hw->wdtconfig0.wdt_stg2 = behavior; - hw->wdtconfig4.wdt_stg2_hold = timeout; - break; - case WDT_STAGE3: - hw->wdtconfig0.wdt_stg3 = behavior; - hw->wdtconfig5.wdt_stg3_hold = timeout; - break; - default: - HAL_ASSERT(false && "unsupported WDT stage"); - break; - } - //Config registers are updated asynchronously - hw->wdtconfig0.wdt_conf_update_en = 1; -} - -/** - * @brief Disable a particular stage of the MWDT - * - * @param hw Start address of the peripheral registers. - * @param stage Which stage to disable - */ -FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage) -{ - switch (stage) { - case WDT_STAGE0: - hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF; - break; - case WDT_STAGE1: - hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF; - break; - case WDT_STAGE2: - hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF; - break; - case WDT_STAGE3: - hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF; - break; - default: - HAL_ASSERT(false && "unsupported WDT stage"); - break; - } - //Config registers are updated asynchronously - hw->wdtconfig0.wdt_conf_update_en = 1; -} - -/** - * @brief Set the length of the CPU reset action - * - * @param hw Start address of the peripheral registers. - * @param length Length of CPU reset signal - */ -FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) -{ - hw->wdtconfig0.wdt_cpu_reset_length = length; - //Config registers are updated asynchronously - hw->wdtconfig0.wdt_conf_update_en = 1; -} - -/** - * @brief Set the length of the system reset action - * - * @param hw Start address of the peripheral registers. - * @param length Length of system reset signal - */ -FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length) -{ - hw->wdtconfig0.wdt_sys_reset_length = length; - //Config registers are updated asynchronously - hw->wdtconfig0.wdt_conf_update_en = 1; -} - -/** - * @brief Enable/Disable the MWDT flashboot mode. - * - * @param hw Beginning address of the peripheral registers. - * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode. - * - * @note Flashboot mode is independent and can trigger a WDT timeout event if the - * WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled - * on flashboot, and should be disabled by software when flashbooting completes. - */ -FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) -{ - hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0; - //Config registers are updated asynchronously - hw->wdtconfig0.wdt_conf_update_en = 1; -} - -/** - * @brief Set the clock prescaler of the MWDT - * - * @param hw Start address of the peripheral registers. - * @param prescaler Prescaler value between 1 to 65535 - */ -FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) -{ - // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register) - // We take care of the "read-modify-write" procedure by ourselves. - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler); - //Config registers are updated asynchronously - hw->wdtconfig0.wdt_conf_update_en = 1; -} - -/** - * @brief Feed the MWDT - * - * Resets the current timer count and current stage. - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw) -{ - hw->wdtfeed.wdt_feed = 1; -} - -/** - * @brief Enable write protection of the MWDT registers - * - * Locking the MWDT will prevent any of the MWDT's registers from being modified - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw) -{ - hw->wdtwprotect.wdt_wkey = 0; -} - -/** - * @brief Disable write protection of the MWDT registers - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw) -{ - hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE; -} - -/** - * @brief Clear the MWDT interrupt status. - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw) -{ - hw->int_clr_timers.wdt_int_clr = 1; -} - -/** - * @brief Set the interrupt enable bit for the MWDT interrupt. - * - * @param hw Beginning address of the peripheral registers. - * @param enable Whether to enable the MWDT interrupt - */ -FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable) -{ - hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0; -} - -/** - * @brief Set the clock source for the MWDT. - * - * @param hw Beginning address of the peripheral registers. - * @param clk_src Clock source - */ -FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src) -{ - switch (clk_src) { - case MWDT_CLK_SRC_APB: - hw->wdtconfig0.wdt_use_xtal = 0; - break; - case MWDT_CLK_SRC_XTAL: - hw->wdtconfig0.wdt_use_xtal = 1; - break; - default: - HAL_ASSERT(false); - break; - } -} - -/** - * @brief Enable MWDT module clock - * - * @param hw Beginning address of the peripheral registers. - * @param en true to enable, false to disable - */ -__attribute__((always_inline)) -static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en) -{ - hw->regclk.wdt_clk_is_active = en; -} - - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h deleted file mode 100644 index 77e88bf781..0000000000 --- a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "soc/soc.h" -#include "soc/regi2c_defs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Reset (Disable) the I2C internal bus for all regi2c registers - */ -static inline void regi2c_ctrl_ll_i2c_reset(void) -{ - // On ESP32-H4, don't need to do anything (indeed do need? not fully supported yet?) - - // SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S); -} - -/** - * @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register - */ -static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void) -{ - // On ESP32-H4, don't need to do anything (indeed do need? not fully supported yet?) - - // CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M); -} - -/** - * @brief Start BBPLL self-calibration - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); -} - -/** - * @brief Stop BBPLL self-calibration - * - * This helps to prevent BBPLL jitter (phenomenon is significant on ESP32H4) - */ -static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) -{ - REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); - REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/** - * @brief Check whether BBPLL calibration is done - * - * @return True if calibration is done; otherwise false - */ -static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) -{ - return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); -} - -/** - * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register - */ -static inline void regi2c_ctrl_ll_i2c_saradc_enable(void) -{ - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); -} - -/** - * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register - */ -static inline void regi2c_ctrl_ll_i2c_saradc_disable(void) -{ - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU); - SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/rmt_ll.h b/components/hal/esp32h4/include/hal/rmt_ll.h deleted file mode 100644 index 826227ffa9..0000000000 --- a/components/hal/esp32h4/include/hal/rmt_ll.h +++ /dev/null @@ -1,834 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @note TX and RX channels are index from 0 in the LL driver, i.e. tx_channel = [0,1], rx_channel = [0,1] - */ - -#pragma once - -#include -#include -#include -#include "hal/misc.h" -#include "hal/assert.h" -#include "soc/rmt_struct.h" -#include "hal/rmt_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) -#define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) -#define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) -#define RMT_LL_EVENT_TX_ERROR(channel) (1 << ((channel) + 4)) -#define RMT_LL_EVENT_RX_DONE(channel) (1 << ((channel) + 2)) -#define RMT_LL_EVENT_RX_THRES(channel) (1 << ((channel) + 10)) -#define RMT_LL_EVENT_RX_ERROR(channel) (1 << ((channel) + 6)) -#define RMT_LL_EVENT_TX_MASK(channel) (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) | RMT_LL_EVENT_TX_LOOP_END(channel)) -#define RMT_LL_EVENT_RX_MASK(channel) (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(channel)) - -#define RMT_LL_MAX_LOOP_COUNT_PER_BATCH 1023 - -typedef enum { - RMT_LL_MEM_OWNER_SW = 0, - RMT_LL_MEM_OWNER_HW = 1, -} rmt_ll_mem_owner_t; - -/** - * @brief Enable clock gate for register and memory - * - * @param dev Peripheral instance address - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_enable_periph_clock(rmt_dev_t *dev, bool enable) -{ - dev->sys_conf.clk_en = enable; // register clock gating - dev->sys_conf.mem_clk_force_on = enable; // memory clock gating -} - -/** - * @brief Power down memory - * - * @param dev Peripheral instance address - * @param enable True to power down, False to power up - */ -static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable) -{ - dev->sys_conf.mem_force_pu = !enable; - dev->sys_conf.mem_force_pd = enable; -} - -/** - * @brief Enable APB accessing RMT memory in nonfifo mode - * - * @param dev Peripheral instance address - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_enable_mem_access_nonfifo(rmt_dev_t *dev, bool enable) -{ - dev->sys_conf.fifo_mask = enable; -} - -/** - * @brief Set clock source and divider for RMT channel group - * - * @param dev Peripheral instance address - * @param channel not used as clock source is set for all channels - * @param src Clock source - * @param divider_integral Integral part of the divider - * @param divider_denominator Denominator part of the divider - * @param divider_numerator Numerator part of the divider - */ -static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, rmt_clock_source_t src, - uint32_t divider_integral, uint32_t divider_denominator, uint32_t divider_numerator) -{ - // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) - (void)channel; // the source clock is set for all channels - HAL_ASSERT(divider_integral >= 1); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, divider_integral - 1); - dev->sys_conf.sclk_div_a = divider_numerator; - dev->sys_conf.sclk_div_b = divider_denominator; - switch (src) { - case RMT_CLK_SRC_AHB: - dev->sys_conf.sclk_sel = 1; - break; - case RMT_CLK_SRC_XTAL: - dev->sys_conf.sclk_sel = 3; - break; - default: - HAL_ASSERT(false && "unsupported RMT clock source"); - break; - } -} - -/** - * @brief Enable RMT peripheral source clock - * - * @param dev Peripheral instance address - * @param en True to enable, False to disable - */ -static inline void rmt_ll_enable_group_clock(rmt_dev_t *dev, bool en) -{ - dev->sys_conf.sclk_active = en; -} - -////////////////////////////////////////TX Channel Specific///////////////////////////////////////////////////////////// - -/** - * @brief Reset clock divider for TX channels by mask - * - * @param dev Peripheral instance address - * @param channel_mask Mask of TX channels - */ -static inline void rmt_ll_tx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) -{ - // write 1 to reset - dev->ref_cnt_rst.val |= channel_mask & 0x03; -} - -/** - * @brief Set TX channel clock divider - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param div Division value - */ -static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) -{ - HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); - // limit the maximum divider to 256 - if (div >= 256) { - div = 0; // 0 means 256 division - } - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); -} - -/** - * @brief Reset RMT reading pointer for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) -{ - dev->tx_conf[channel].mem_rd_rst = 1; - dev->tx_conf[channel].mem_rd_rst = 0; - dev->tx_conf[channel].mem_rst = 1; - dev->tx_conf[channel].mem_rst = 0; -} - -/** - * @brief Start transmitting for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) -{ - // update other configuration registers before start transmitting - dev->tx_conf[channel].conf_update = 1; - dev->tx_conf[channel].tx_start = 1; -} - -/** - * @brief Stop transmitting for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) -{ - dev->tx_conf[channel].tx_stop = 1; - // stop won't take place until configurations updated - dev->tx_conf[channel].conf_update = 1; -} - -/** - * @brief Set memory block number for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param block_num memory block number - */ -static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) -{ - dev->tx_conf[channel].mem_size = block_num; -} - -/** - * @brief Enable TX wrap - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->tx_conf[channel].mem_tx_wrap_en = enable; -} - -/** - * @brief Enable transmitting in a loop - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param enable True to enable, False to disable - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->tx_conf[channel].tx_conti_mode = enable; -} - -/** - * @brief Set loop count for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param count TX loop count - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) -{ - HAL_ASSERT(count <= RMT_LL_MAX_LOOP_COUNT_PER_BATCH && "loop count out of range"); - dev->tx_lim[channel].tx_loop_num = count; -} - -/** - * @brief Reset loop count for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_reset_loop_count(rmt_dev_t *dev, uint32_t channel) -{ - dev->tx_lim[channel].loop_count_reset = 1; - dev->tx_lim[channel].loop_count_reset = 0; -} - -/** - * @brief Enable loop count for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param enable True to enable, False to disable - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->tx_lim[channel].tx_loop_cnt_en = enable; -} - -/** - * @brief Enable transmit multiple channels synchronously - * - * @param dev Peripheral instance address - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) -{ - dev->tx_sim.en = enable; -} - -/** - * @brief Clear the TX channels synchronous group - * - * @param dev Peripheral instance address - */ -static inline void rmt_ll_tx_clear_sync_group(rmt_dev_t *dev) -{ - dev->tx_sim.val &= ~(0x03); -} - -/** - * @brief Add TX channels to the synchronous group - * - * @param dev Peripheral instance address - * @param channel_mask Mask of TX channels to be added to the synchronous group - */ -static inline void rmt_ll_tx_sync_group_add_channels(rmt_dev_t *dev, uint32_t channel_mask) -{ - dev->tx_sim.val |= (channel_mask & 0x03); -} - -/** - * @brief Remove TX channels from the synchronous group - * - * @param dev Peripheral instance address - * @param channel_mask Mask of TX channels to be removed from the synchronous group - */ -static inline void rmt_ll_tx_sync_group_remove_channels(rmt_dev_t *dev, uint32_t channel_mask) -{ - dev->tx_sim.val &= ~channel_mask; -} - -/** - * @brief Fix the output level when TX channel is in IDLE state - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param level IDLE level (1 => high, 0 => low) - * @param enable True to fix the IDLE level, otherwise the IDLE level is determined by EOF encoder - */ -__attribute__((always_inline)) -static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level, bool enable) -{ - dev->tx_conf[channel].idle_out_en = enable; - dev->tx_conf[channel].idle_out_lv = level; -} - -/** - * @brief Set the amount of RMT symbols that can trigger the limitation interrupt - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param limit Specify the number of symbols - */ -static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) -{ - dev->tx_lim[channel].limit = limit; -} - -/** - * @brief Set high and low duration of carrier signal - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param high_ticks Duration of high level - * @param low_ticks Duration of low level - */ -static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) -{ - HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks"); - // ticks=0 means 65536 in hardware - if (high_ticks >= 65536) { - high_ticks = 0; - } - if (low_ticks >= 65536) { - low_ticks = 0; - } - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_carrier[channel], high, high_ticks); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_carrier[channel], low, low_ticks); -} - -/** - * @brief Enable modulating carrier signal to TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->tx_conf[channel].carrier_en = enable; -} - -/** - * @brief Set on high or low to modulate the carrier signal - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param level Which level to modulate on (0=>low level, 1=>high level) - */ -static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) -{ - dev->tx_conf[channel].carrier_out_lv = level; -} - -/** - * @brief Enable to always output carrier signal, regardless of a valid data transmission - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @param enable True to output carrier signal in all RMT state, False to only ouput carrier signal for effective data - */ -static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->tx_conf[channel].carrier_eff_en = !enable; -} - -////////////////////////////////////////RX Channel Specific///////////////////////////////////////////////////////////// - -/** - * @brief Reset clock divider for RX channels by mask - * - * @param dev Peripheral instance address - * @param channel_mask Mask of RX channels - */ -static inline void rmt_ll_rx_reset_channels_clock_div(rmt_dev_t *dev, uint32_t channel_mask) -{ - // write 1 to reset - dev->ref_cnt_rst.val |= ((channel_mask & 0x03) << 2); -} - -/** - * @brief Set RX channel clock divider - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param div Division value - */ -static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) -{ - HAL_ASSERT(div >= 1 && div <= 256 && "divider out of range"); - // limit the maximum divider to 256 - if (div >= 256) { - div = 0; // 0 means 256 division - } - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); -} - -/** - * @brief Reset RMT writing pointer for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - */ -static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) -{ - dev->rx_conf[channel].conf1.mem_wr_rst = 1; - dev->rx_conf[channel].conf1.mem_wr_rst = 0; - dev->rx_conf[channel].conf1.mem_rst = 1; - dev->rx_conf[channel].conf1.mem_rst = 0; -} - -/** - * @brief Enable receiving for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param enable True to enable, False to disable - */ -__attribute__((always_inline)) -static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->rx_conf[channel].conf1.rx_en = enable; - // rx won't be enabled until configurations updated - dev->rx_conf[channel].conf1.conf_update = 1; -} - -/** - * @brief Set memory block number for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param block_num memory block number - */ -static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) -{ - dev->rx_conf[channel].conf0.mem_size = block_num; -} - -/** - * @brief Set the time length for RX channel before going into IDLE state - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param thres Time length threshold - */ -static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) -{ - dev->rx_conf[channel].conf0.idle_thres = thres; -} - -/** - * @brief Set RMT memory owner for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param owner Memory owner - */ -__attribute__((always_inline)) -static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt_ll_mem_owner_t owner) -{ - dev->rx_conf[channel].conf1.mem_owner = owner; -} - -/** - * @brief Enable filter for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX chanenl number - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->rx_conf[channel].conf1.rx_filter_en = enable; -} - -/** - * @brief Set RX channel filter threshold (i.e. the maximum width of one pulse signal that would be treated as a noise) - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param thres Filter threshold - */ -static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf1, rx_filter_thres, thres); -} - -/** - * @brief Get RMT memory write cursor offset - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @return writer offset - */ -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32_t channel) -{ - return dev->rx_status[channel].mem_waddr_ex - (channel + 2) * 48; -} - -/** - * @brief Set the amount of RMT symbols that can trigger the limitation interrupt - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param limit Specify the number of symbols - */ -static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) -{ - dev->rx_lim[channel].rx_lim = limit; -} - -/** - * @brief Set high and low duration of carrier signal - * - * @param dev dev Peripheral instance address - * @param channel RMT TX channel number - * @param high_ticks Duration of high level - * @param low_ticks Duration of low level - */ -static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) -{ - HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks"); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_carrier[channel], high_thres, high_ticks - 1); - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_carrier[channel], low_thres, low_ticks - 1); -} - -/** - * @brief Enable demodulating the carrier on RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->rx_conf[channel].conf0.carrier_en = enable; -} - -/** - * @brief Set on high or low to demodulate the carrier signal - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param level Which level to demodulate (0=>low level, 1=>high level) - */ -static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) -{ - dev->rx_conf[channel].conf0.carrier_out_lv = level; -} - -/** - * @brief Enable RX wrap - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @param enable True to enable, False to disable - */ -static inline void rmt_ll_rx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable) -{ - dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; -} - -//////////////////////////////////////////Interrupt Specific//////////////////////////////////////////////////////////// - -/** - * @brief Enable RMT interrupt for specific event mask - * - * @param dev Peripheral instance address - * @param mask Event mask - * @param enable True to enable, False to disable - */ -__attribute__((always_inline)) -static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) -{ - if (enable) { - dev->int_ena.val |= mask; - } else { - dev->int_ena.val &= ~mask; - } -} - -/** - * @brief Clear RMT interrupt status by mask - * - * @param dev Peripheral instance address - * @param mask Interupt status mask - */ -__attribute__((always_inline)) -static inline void rmt_ll_clear_interrupt_status(rmt_dev_t *dev, uint32_t mask) -{ - dev->int_clr.val = mask; -} - -/** - * @brief Get interrupt status register address - * - * @param dev Peripheral instance address - * @return Register address - */ -static inline volatile void *rmt_ll_get_interrupt_status_reg(rmt_dev_t *dev) -{ - return &dev->int_st; -} - -/** - * @brief Get interrupt status for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @return Interrupt status - */ -__attribute__((always_inline)) -static inline uint32_t rmt_ll_tx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel) -{ - return dev->int_st.val & RMT_LL_EVENT_TX_MASK(channel); -} - -/** - * @brief Get interrupt raw status for TX channel - * - * @param dev Peripheral instance address - * @param channel RMT TX channel number - * @return Interrupt raw status - */ -static inline uint32_t rmt_ll_tx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel) -{ - return dev->int_raw.val & (RMT_LL_EVENT_TX_MASK(channel) | RMT_LL_EVENT_TX_ERROR(channel)); -} - -/** - * @brief Get interrupt raw status for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @return Interrupt raw status - */ -static inline uint32_t rmt_ll_rx_get_interrupt_status_raw(rmt_dev_t *dev, uint32_t channel) -{ - return dev->int_raw.val & (RMT_LL_EVENT_RX_MASK(channel) | RMT_LL_EVENT_RX_ERROR(channel)); -} - -/** - * @brief Get interrupt status for RX channel - * - * @param dev Peripheral instance address - * @param channel RMT RX channel number - * @return Interrupt status - */ -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t channel) -{ - return dev->int_st.val & RMT_LL_EVENT_RX_MASK(channel); -} - -//////////////////////////////////////////Deprecated Functions////////////////////////////////////////////////////////// -/////////////////////////////The following functions are only used by the legacy driver///////////////////////////////// -/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)////////////////////////////// -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel) -{ - return dev->tx_status[channel].val; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel) -{ - return dev->rx_status[channel].val; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) -{ - uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); - return div == 0 ? 256 : div; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) -{ - uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); - return div == 0 ? 256 : div; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) -{ - return dev->rx_conf[channel].conf0.idle_thres; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) -{ - return dev->tx_conf[channel].mem_size; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) -{ - return dev->rx_conf[channel].conf0.mem_size; -} - -__attribute__((always_inline)) -static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel) -{ - return dev->tx_conf[channel].tx_conti_mode; -} - -__attribute__((always_inline)) -static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel) -{ - rmt_clock_source_t clk_src = RMT_CLK_SRC_AHB; - switch (dev->sys_conf.sclk_sel) { - case 1: - clk_src = RMT_CLK_SRC_AHB; - break; - case 3: - clk_src = RMT_CLK_SRC_XTAL; - break; - } - return clk_src; -} - -__attribute__((always_inline)) -static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel) -{ - return dev->tx_conf[channel].idle_out_en; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) -{ - return dev->tx_conf[channel].idle_out_lv; -} - -static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev) -{ - // the RTC domain can also power down RMT memory - // so it's probably not enough to detect whether it's powered down or not - // mem_force_pd has higher priority than mem_force_pu - return (dev->sys_conf.mem_force_pd) || !(dev->sys_conf.mem_force_pu); -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) -{ - return dev->rx_conf[channel].conf1.mem_owner; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) -{ - return dev->rx_lim[channel].rx_lim; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev) -{ - return dev->int_st.val & 0x03; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev) -{ - return (dev->int_st.val >> 2) & 0x03; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev) -{ - return (dev->int_st.val >> 4) & 0x03; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev) -{ - return (dev->int_st.val >> 6) & 0x03; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev) -{ - return (dev->int_st.val >> 8) & 0x03; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev) -{ - return (dev->int_st.val >> 10) & 0x03; -} - -__attribute__((always_inline)) -static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) -{ - return (dev->int_st.val >> 12) & 0x03; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/rtc_cntl_ll.h b/components/hal/esp32h4/include/hal/rtc_cntl_ll.h deleted file mode 100644 index 0f086e5f62..0000000000 --- a/components/hal/esp32h4/include/hal/rtc_cntl_ll.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" -#include "soc/rtc.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/syscon_reg.h" -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) -{ - WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); - WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); - - SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); - SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); -} - -FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) -{ - return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); -} - -FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) -{ - REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); - REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); -} - -FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) -{ - // ESP32H4-TODO: IDF-3383 -} - -FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) -{ - // ESP32H4-TODO: IDF-3383 -} - -FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) -{ - REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); -} - -FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) -{ - REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); -} - -FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); -} - -FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); - uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); - t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; - return t; -} - -FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) -{ - uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); - return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); -} - -FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) -{ - return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/rwdt_ll.h b/components/hal/esp32h4/include/hal/rwdt_ll.h deleted file mode 100644 index 31aacd8529..0000000000 --- a/components/hal/esp32h4/include/hal/rwdt_ll.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "hal/misc.h" -#include "hal/wdt_types.h" -#include "soc/rtc_cntl_periph.h" -#include "soc/rtc_cntl_struct.h" -#include "hal/efuse_ll.h" -#include "esp_attr.h" -#include "esp_assert.h" - -//Type check wdt_stage_action_t -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); -//Type check wdt_reset_sig_length_t -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); -ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t"); - -typedef rtc_cntl_dev_t rwdt_dev_t; - -#define RWDT_DEV_GET() &RTCCNTL - -/** - * @brief Enable the RWDT - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void rwdt_ll_enable(rtc_cntl_dev_t *hw) -{ - hw->wdt_config0.en = 1; -} - -/** - * @brief Disable the RWDT - * - * @param hw Start address of the peripheral registers. - * @note This function does not disable the flashboot mode. Therefore, given that - * the MWDT is disabled using this function, a timeout can still occur - * if the flashboot mode is simultaneously enabled. - */ -FORCE_INLINE_ATTR void rwdt_ll_disable(rtc_cntl_dev_t *hw) -{ - hw->wdt_config0.en = 0; -} - -/** - * @brief Check if the RWDT is enabled - * - * @param hw Start address of the peripheral registers. - * @return True if RTC WDT is enabled - */ -FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rtc_cntl_dev_t *hw) -{ - return (hw->wdt_config0.en) ? true : false; -} - -/** - * @brief Configure a particular stage of the RWDT - * - * @param hw Start address of the peripheral registers. - * @param stage Which stage to configure - * @param timeout Number of timer ticks for the stage to timeout (see note). - * @param behavior What action to take when the stage times out - * - * @note The value of of RWDT stage 0 timeout register is special, in - * that an implicit multiplier is applied to that value to produce - * and effective timeout tick value. The multiplier is dependent - * on an EFuse value. Therefore, when configuring stage 0, the valid - * values for the timeout argument are: - * - If Efuse value is 0, any even number between [2,2*UINT32_MAX] - * - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX] - * - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX] - * - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX] - */ -FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior) -{ - switch (stage) { - case WDT_STAGE0: - hw->wdt_config0.stg0 = behavior; - //Account of implicty multiplier applied to stage 0 timeout tick config value - hw->wdt_config1 = timeout_ticks >> (1 + efuse_ll_get_wdt_delay_sel()); - break; - case WDT_STAGE1: - hw->wdt_config0.stg1 = behavior; - hw->wdt_config2 = timeout_ticks; - break; - case WDT_STAGE2: - hw->wdt_config0.stg2 = behavior; - hw->wdt_config3 = timeout_ticks; - break; - case WDT_STAGE3: - hw->wdt_config0.stg3 = behavior; - hw->wdt_config4 = timeout_ticks; - break; - default: - abort(); - } -} - -/** - * @brief Disable a particular stage of the RWDT - * - * @param hw Start address of the peripheral registers. - * @param stage Which stage to disable - */ -FORCE_INLINE_ATTR void rwdt_ll_disable_stage(rtc_cntl_dev_t *hw, wdt_stage_t stage) -{ - switch (stage) { - case WDT_STAGE0: - hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF; - break; - case WDT_STAGE1: - hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF; - break; - case WDT_STAGE2: - hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF; - break; - case WDT_STAGE3: - hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF; - break; - default: - abort(); - } -} - -/** - * @brief Set the length of the CPU reset action - * - * @param hw Start address of the peripheral registers. - * @param length Length of CPU reset signal - */ -FORCE_INLINE_ATTR void rwdt_ll_set_cpu_reset_length(rtc_cntl_dev_t *hw, wdt_reset_sig_length_t length) -{ - hw->wdt_config0.cpu_reset_length = length; -} - -/** - * @brief Set the length of the system reset action - * - * @param hw Start address of the peripheral registers. - * @param length Length of system reset signal - */ -FORCE_INLINE_ATTR void rwdt_ll_set_sys_reset_length(rtc_cntl_dev_t *hw, wdt_reset_sig_length_t length) -{ - hw->wdt_config0.sys_reset_length = length; -} - -/** - * @brief Enable/Disable the RWDT flashboot mode. - * - * @param hw Start address of the peripheral registers. - * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode. - * - * @note Flashboot mode is independent and can trigger a WDT timeout event if the - * WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled - * on flashboot, and should be disabled by software when flashbooting completes. - */ -FORCE_INLINE_ATTR void rwdt_ll_set_flashboot_en(rtc_cntl_dev_t *hw, bool enable) -{ - hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0; -} - -/** - * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU - * - * @param hw Start address of the peripheral registers. - * @param enable True to enable CPU0 to be reset, false to disable. - */ -FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rtc_cntl_dev_t *hw, bool enable) -{ - hw->wdt_config0.procpu_reset_en = (enable) ? 1 : 0; -} - -/** - * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU - * - * @param hw Start address of the peripheral registers. - * @param enable True to enable CPU1 to be reset, false to disable. - */ -FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rtc_cntl_dev_t *hw, bool enable) -{ - hw->wdt_config0.appcpu_reset_en = (enable) ? 1 : 0; -} - -/** - * @brief Enable/Disable the RWDT pause during sleep functionality - * - * @param hw Start address of the peripheral registers. - * @param enable True to enable, false to disable. - */ -FORCE_INLINE_ATTR void rwdt_ll_set_pause_in_sleep_en(rtc_cntl_dev_t *hw, bool enable) -{ - hw->wdt_config0.pause_in_slp = (enable) ? 1 : 0; -} - -/** - * @brief Enable/Disable chip reset on RWDT timeout. - * - * A chip reset also resets the analog portion of the chip. It will appear as a - * POWERON reset rather than an RTC reset. - * - * @param hw Start address of the peripheral registers. - * @param enable True to enable, false to disable. - */ -FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable) -{ - hw->wdt_config0.chip_reset_en = (enable) ? 1 : 0; -} - -/** - * @brief Set width of chip reset signal - * - * @param hw Start address of the peripheral registers. - * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles - */ -FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width); -} - -/** - * @brief Feed the RWDT - * - * Resets the current timer count and current stage. - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void rwdt_ll_feed(rtc_cntl_dev_t *hw) -{ - hw->wdt_feed.feed = 1; -} - -/** - * @brief Enable write protection of the RWDT registers - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void rwdt_ll_write_protect_enable(rtc_cntl_dev_t *hw) -{ - hw->wdt_wprotect = 0; -} - -/** - * @brief Disable write protection of the RWDT registers - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void rwdt_ll_write_protect_disable(rtc_cntl_dev_t *hw) -{ - hw->wdt_wprotect = RTC_CNTL_WDT_WKEY_VALUE; -} - -/** - * @brief Enable the RWDT interrupt. - * - * @param hw Start address of the peripheral registers. - * @param enable True to enable RWDT interrupt, false to disable. - */ -FORCE_INLINE_ATTR void rwdt_ll_set_intr_enable(rtc_cntl_dev_t *hw, bool enable) -{ - hw->int_ena.rtc_wdt = (enable) ? 1 : 0; -} - -/** - * @brief Check if the RWDT interrupt has been triggered - * - * @param hw Start address of the peripheral registers. - * @return True if the RWDT interrupt was triggered - */ -FORCE_INLINE_ATTR bool rwdt_ll_check_intr_status(rtc_cntl_dev_t *hw) -{ - return (hw->int_st.rtc_wdt) ? true : false; -} - -/** - * @brief Clear the RWDT interrupt status. - * - * @param hw Start address of the peripheral registers. - */ -FORCE_INLINE_ATTR void rwdt_ll_clear_intr_status(rtc_cntl_dev_t *hw) -{ - hw->int_clr.rtc_wdt = 1; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/sar_ctrl_ll.h b/components/hal/esp32h4/include/hal/sar_ctrl_ll.h deleted file mode 100644 index 072a6539b0..0000000000 --- a/components/hal/esp32h4/include/hal/sar_ctrl_ll.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * SAR related peripherals are interdependent. - * Related peripherals are: - * - ADC - * - PWDET - * - Temp Sensor - * - * All of above peripherals require SAR to work correctly. - * As SAR has some registers that will influence above mentioned peripherals. - * This file gives an abstraction for such registers - */ - -#pragma once - -#include -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PWDET_CONF_REG 0x600A8010 -#define PWDET_SAR_POWER_FORCE BIT(24) -#define PWDET_SAR_POWER_CNTL BIT(23) - - -typedef enum { - SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM - SAR_CTRL_LL_POWER_ON, //SAR power on - SAR_CTRL_LL_POWER_OFF, //SAR power off -} sar_ctrl_ll_power_t; - -/*--------------------------------------------------------------- - SAR power control ----------------------------------------------------------------*/ -/** - * @brief Set SAR power mode when controlled by PWDET - * - * @param[in] mode See `sar_ctrl_ll_power_t` - */ -static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode) -{ - if (mode == SAR_CTRL_LL_POWER_FSM) { - REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); - } else if (mode == SAR_CTRL_LL_POWER_ON) { - REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); - REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); - } else if (mode == SAR_CTRL_LL_POWER_OFF) { - REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE); - REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL); - } -} - - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/sdm_ll.h b/components/hal/esp32h4/include/hal/sdm_ll.h deleted file mode 100644 index a705f4208b..0000000000 --- a/components/hal/esp32h4/include/hal/sdm_ll.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "hal/misc.h" -#include "hal/assert.h" -#include "soc/gpio_sd_struct.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Set Sigma-delta enable - * - * @param hw Peripheral SIGMADELTA hardware instance address. - * @param en Sigma-delta enable value - */ -static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en) -{ - hw->misc.function_clk_en = en; -} - -/** - * @brief Set Sigma-delta channel duty. - * - * @param hw Peripheral SIGMADELTA hardware instance address. - * @param channel Sigma-delta channel number - * @param density Sigma-delta quantized density of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90. - * The waveform is more like a random one in this range. - */ -__attribute__((always_inline)) -static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)density); -} - -/** - * @brief Set Sigma-delta channel's clock pre-scale value. - * - * @param hw Peripheral SIGMADELTA hardware instance address. - * @param channel Sigma-delta channel number - * @param prescale The divider of source clock, ranges from 1 to 256 - */ -static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale) -{ - HAL_ASSERT(prescale && prescale <= 256); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale - 1); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/sha_ll.h b/components/hal/esp32h4/include/hal/sha_ll.h deleted file mode 100644 index 5bb746732a..0000000000 --- a/components/hal/esp32h4/include/hal/sha_ll.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/hwcrypto_reg.h" -#include "hal/sha_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @brief Start a new SHA block conversions (no initial hash in HW) - * - * @param sha_type The SHA algorithm type - */ -static inline void sha_ll_start_block(esp_sha_type sha_type) -{ - REG_WRITE(SHA_MODE_REG, sha_type); - REG_WRITE(SHA_START_REG, 1); -} - -/** - * @brief Continue a SHA block conversion (initial hash in HW) - * - * @param sha_type The SHA algorithm type - */ -static inline void sha_ll_continue_block(esp_sha_type sha_type) -{ - REG_WRITE(SHA_MODE_REG, sha_type); - REG_WRITE(SHA_CONTINUE_REG, 1); -} - -/** - * @brief Start a new SHA message conversion using DMA (no initial hash in HW) - * - * @param sha_type The SHA algorithm type - */ -static inline void sha_ll_start_dma(esp_sha_type sha_type) -{ - REG_WRITE(SHA_MODE_REG, sha_type); - REG_WRITE(SHA_DMA_START_REG, 1); -} - -/** - * @brief Continue a SHA message conversion using DMA (initial hash in HW) - * - * @param sha_type The SHA algorithm type - */ -static inline void sha_ll_continue_dma(esp_sha_type sha_type) -{ - REG_WRITE(SHA_MODE_REG, sha_type); - REG_WRITE(SHA_DMA_CONTINUE_REG, 1); -} - -/** - * @brief Load the current hash digest to digest register - * - * @note Happens automatically on ESP32S3 - * - * @param sha_type The SHA algorithm type - */ -static inline void sha_ll_load(esp_sha_type sha_type) -{ -} - -/** - * @brief Sets the number of message blocks to be hashed - * - * @note DMA operation only - * - * @param num_blocks Number of message blocks to process - */ -static inline void sha_ll_set_block_num(size_t num_blocks) -{ - REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); -} - -/** - * @brief Checks if the SHA engine is currently busy hashing a block - * - * @return true SHA engine busy - * @return false SHA engine idle - */ -static inline bool sha_ll_busy(void) -{ - return REG_READ(SHA_BUSY_REG); -} - -/** - * @brief Write a text (message) block to the SHA engine - * - * @param input_text Input buffer to be written to the SHA engine - * @param block_word_len Number of words in block - */ -static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) -{ - uint32_t *data_words = (uint32_t *)input_text; - uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE); - - for (int i = 0; i < block_word_len; i++) { - REG_WRITE(®_addr_buf[i], data_words[i]); - } -} - -/** - * @brief Read the message digest from the SHA engine - * - * @param sha_type The SHA algorithm type - * @param digest_state Buffer that message digest will be written to - * @param digest_word_len Length of the message digest - */ -static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) -{ - uint32_t *digest_state_words = (uint32_t *)digest_state; - const size_t REG_WIDTH = sizeof(uint32_t); - - for (size_t i = 0; i < digest_word_len; i++) { - digest_state_words[i] = REG_READ(SHA_H_BASE + (i * REG_WIDTH)); - } - -} - -/** - * @brief Write the message digest to the SHA engine - * - * @param sha_type The SHA algorithm type - * @param digest_state Message digest to be written to SHA engine - * @param digest_word_len Length of the message digest - */ -static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) -{ - uint32_t *digest_state_words = (uint32_t *)digest_state; - uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE); - - for (int i = 0; i < digest_word_len; i++) { - REG_WRITE(®_addr_buf[i], digest_state_words[i]); - } -} - - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32h4/include/hal/spi_flash_encrypted_ll.h deleted file mode 100644 index f66584369c..0000000000 --- a/components/hal/esp32h4/include/hal/spi_flash_encrypted_ll.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The ll is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - -// The Lowlevel layer for SPI Flash Encryption. - -#include "hal/assert.h" -#include "soc/system_reg.h" -#include "soc/hwcrypto_reg.h" -#include "soc/soc.h" -#include "string.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/// Choose type of chip you want to encrypt manully -typedef enum -{ - FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip. - PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip. -} flash_encrypt_ll_type_t; - -/** - * Enable the flash encryption function under spi boot mode and download boot mode. - */ -static inline void spi_flash_encrypt_ll_enable(void) -{ - REG_SET_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, - SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT | - SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); -} - -/* - * Disable the flash encryption mode. - */ -static inline void spi_flash_encrypt_ll_disable(void) -{ - REG_CLR_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, - SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT); -} - -/** - * Choose type of chip you want to encrypt manully - * - * @param type The type of chip to be encrypted - * - * @note The hardware currently support flash encryption. - */ -static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) -{ - // Our hardware only support flash encryption - HAL_ASSERT(type == FLASH_ENCRYPTION_MANU); - REG_WRITE(AES_XTS_DESTINATION_REG, type); -} - -/** - * Configure the data size of a single encryption. - * - * @param block_size Size of the desired block. - */ -static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size) -{ - // Desired block should not be larger than the block size. - REG_WRITE(AES_XTS_SIZE_REG, size >> 5); -} - -/** - * Save 32-bit piece of plaintext. - * - * @param address the address of written flash partition. - * @param buffer Buffer to store the input data. - * @param size Buffer size. - * - */ -static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size) -{ - uint32_t plaintext_offs = (address % 64); - memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size); -} - -/** - * Copy the flash address to XTS_AES physical address - * - * @param flash_addr flash address to write. - */ -static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) -{ - REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr); -} - -/** - * Start flash encryption - */ -static inline void spi_flash_encrypt_ll_calculate_start(void) -{ - REG_WRITE(AES_XTS_TRIGGER_REG, 1); -} - -/** - * Wait for flash encryption termination - */ -static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) -{ - while(REG_READ(AES_XTS_STATE_REG) == 0x1) { - } -} - -/** - * Finish the flash encryption and make encrypted result accessible to SPI. - */ -static inline void spi_flash_encrypt_ll_done(void) -{ - REG_WRITE(AES_XTS_RELEASE_REG, 1); - while(REG_READ(AES_XTS_STATE_REG) != 0x3) { - } -} - -/** - * Set to destroy encrypted result - */ -static inline void spi_flash_encrypt_ll_destroy(void) -{ - REG_WRITE(AES_XTS_DESTROY_REG, 1); -} - -/** - * Check if is qualified to encrypt the buffer - * - * @param address the address of written flash partition. - * @param length Buffer size. - */ -static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length) -{ - return ((address % length) == 0) ? true : false; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/spi_flash_ll.h b/components/hal/esp32h4/include/hal/spi_flash_ll.h deleted file mode 100644 index fea625a6fb..0000000000 --- a/components/hal/esp32h4/include/hal/spi_flash_ll.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The ll is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md - ******************************************************************************/ - -// The Lowlevel layer for SPI Flash - -#pragma once - -#include "gpspi_flash_ll.h" -#include "spimem_flash_ll.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \ - : gpspi_flash_ll_calculate_clock_reg(clock_div)) - -#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ) - -#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \ - : gpspi_flash_ll_get_hw(host_id))) - -#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \ - if (dev_id < 0) {\ - dev_id = gpspi_flash_ll_hw_get_id(dev);\ - }\ - dev_id; \ - }) - - -typedef union { - gpspi_flash_ll_clock_reg_t gpspi; - spimem_flash_ll_clock_reg_t spimem; -} spi_flash_ll_clock_reg_t; - -#ifdef GPSPI_BUILD -#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev) -#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev) -#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len) -#define spi_flash_ll_set_buffer_data(dev, buffer, len) gpspi_flash_ll_set_buffer_data((spi_dev_t*)dev, buffer, len) -#define spi_flash_ll_user_start(dev) gpspi_flash_ll_user_start((spi_dev_t*)dev) -#define spi_flash_ll_host_idle(dev) gpspi_flash_ll_host_idle((spi_dev_t*)dev) -#define spi_flash_ll_read_phase(dev) gpspi_flash_ll_read_phase((spi_dev_t*)dev) -#define spi_flash_ll_set_cs_pin(dev, pin) gpspi_flash_ll_set_cs_pin((spi_dev_t*)dev, pin) -#define spi_flash_ll_set_read_mode(dev, read_mode) gpspi_flash_ll_set_read_mode((spi_dev_t*)dev, read_mode) -#define spi_flash_ll_set_clock(dev, clk) gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk) -#define spi_flash_ll_set_miso_bitlen(dev, bitlen) gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen) -#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen) -#define spi_flash_ll_set_command(dev, cmd, bitlen) gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen) -#define spi_flash_ll_set_addr_bitlen(dev, bitlen) gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen) -#define spi_flash_ll_get_addr_bitlen(dev) gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev) -#define spi_flash_ll_set_address(dev, addr) gpspi_flash_ll_set_address((spi_dev_t*)dev, addr) -#define spi_flash_ll_set_usr_address(dev, addr, bitlen) gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen) -#define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy) -#define spi_flash_ll_set_dummy_out(dev, en, lev) gpspi_flash_ll_set_dummy_out((spi_dev_t*)dev, en, lev) -#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n) -#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time) -#else -#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev) -#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev) -#define spi_flash_ll_erase_chip(dev) spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev) -#define spi_flash_ll_erase_sector(dev) spimem_flash_ll_erase_sector((spi_mem_dev_t*)dev) -#define spi_flash_ll_erase_block(dev) spimem_flash_ll_erase_block((spi_mem_dev_t*)dev) -#define spi_flash_ll_set_write_protect(dev, wp) spimem_flash_ll_set_write_protect((spi_mem_dev_t*)dev, wp) -#define spi_flash_ll_get_buffer_data(dev, buffer, read_len) spimem_flash_ll_get_buffer_data((spi_mem_dev_t*)dev, buffer, read_len) -#define spi_flash_ll_set_buffer_data(dev, buffer, len) spimem_flash_ll_set_buffer_data((spi_mem_dev_t*)dev, buffer, len) -#define spi_flash_ll_program_page(dev, buffer, len) spimem_flash_ll_program_page((spi_mem_dev_t*)dev, buffer, len) -#define spi_flash_ll_user_start(dev) spimem_flash_ll_user_start((spi_mem_dev_t*)dev) -#define spi_flash_ll_host_idle(dev) spimem_flash_ll_host_idle((spi_mem_dev_t*)dev) -#define spi_flash_ll_read_phase(dev) spimem_flash_ll_read_phase((spi_mem_dev_t*)dev) -#define spi_flash_ll_set_cs_pin(dev, pin) spimem_flash_ll_set_cs_pin((spi_mem_dev_t*)dev, pin) -#define spi_flash_ll_set_read_mode(dev, read_mode) spimem_flash_ll_set_read_mode((spi_mem_dev_t*)dev, read_mode) -#define spi_flash_ll_set_clock(dev, clk) spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk) -#define spi_flash_ll_set_miso_bitlen(dev, bitlen) spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen) -#define spi_flash_ll_set_mosi_bitlen(dev, bitlen) spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen) -#define spi_flash_ll_set_command(dev, cmd, bitlen) spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen) -#define spi_flash_ll_set_addr_bitlen(dev, bitlen) spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen) -#define spi_flash_ll_get_addr_bitlen(dev) spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev) -#define spi_flash_ll_set_address(dev, addr) spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr) -#define spi_flash_ll_set_usr_address(dev, addr, bitlen) spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen) -#define spi_flash_ll_set_dummy(dev, dummy) spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy) -#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) -#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) -#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) - -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/spi_ll.h b/components/hal/esp32h4/include/hal/spi_ll.h deleted file mode 100644 index b4df8b61fd..0000000000 --- a/components/hal/esp32h4/include/hal/spi_ll.h +++ /dev/null @@ -1,1199 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md - ******************************************************************************/ - -// The LL layer for SPI register operations - -#pragma once - -#include //for abs() -#include -#include "esp_attr.h" -#include "esp_types.h" -#include "soc/spi_periph.h" -#include "soc/spi_struct.h" -#include "soc/lldesc.h" -#include "hal/assert.h" -#include "hal/misc.h" -#include "hal/spi_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// Interrupt not used. Don't use in app. -#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA) -/// These 2 masks together will set SPI transaction to one line mode -#define SPI_LL_ONE_LINE_CTRL_MASK (SPI_FREAD_QUAD | SPI_FREAD_DUAL | SPI_FCMD_QUAD | SPI_FCMD_DUAL | SPI_FADDR_QUAD | SPI_FADDR_DUAL) -#define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_QUAD | SPI_FWRITE_DUAL) -/// Swap the bit order to its correct place to send -#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len)) -#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2) - -#define SPI_LL_DATA_MAX_BIT_LEN (1 << 18) - -/** - * The data structure holding calculated clock configuration. Since the - * calculation needs long time, it should be calculated during initialization and - * stored somewhere to be quickly used. - */ -typedef uint32_t spi_ll_clock_val_t; -typedef spi_dev_t spi_dma_dev_t; - -// Type definition of all supported interrupts -typedef enum { - SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done - SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD. - SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD. - SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD. - SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD. - SPI_LL_INTR_CMD7 = BIT(10), ///< Has received CMD7 command. Only available in slave HD. - SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD. - SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD. - SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD. - SPI_LL_INTR_SEG_DONE = BIT(14), -} spi_ll_intr_t; -FLAG_ATTR(spi_ll_intr_t) - -// Flags for conditions under which the transaction length should be recorded -typedef enum { - SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded - SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded - SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded - SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded -} spi_ll_trans_len_cond_t; -FLAG_ATTR(spi_ll_trans_len_cond_t) - -// SPI base command in esp32h4 -typedef enum { - /* Slave HD Only */ - SPI_LL_BASE_CMD_HD_WRBUF = 0x01, - SPI_LL_BASE_CMD_HD_RDBUF = 0x02, - SPI_LL_BASE_CMD_HD_WRDMA = 0x03, - SPI_LL_BASE_CMD_HD_RDDMA = 0x04, - SPI_LL_BASE_CMD_HD_SEG_END = 0x05, - SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, - SPI_LL_BASE_CMD_HD_WR_END = 0x07, - SPI_LL_BASE_CMD_HD_INT0 = 0x08, - SPI_LL_BASE_CMD_HD_INT1 = 0x09, - SPI_LL_BASE_CMD_HD_INT2 = 0x0A, -} spi_ll_base_command_t; - -/*------------------------------------------------------------------------------ - * Control - *----------------------------------------------------------------------------*/ - -/** - * Select SPI peripheral clock source (master). - * - * @param hw Beginning address of the peripheral registers. - * @param clk_source clock source to select, see valid sources in type `spi_clock_source_t` - */ -static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) -{ - switch (clk_source) - { - case SPI_CLK_SRC_XTAL: - hw->clk_gate.mst_clk_sel = 0; - break; - default: - hw->clk_gate.mst_clk_sel = 1; - break; - } -} - -/** - * Initialize SPI peripheral (master). - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_master_init(spi_dev_t *hw) -{ - //Reset timing - hw->user1.cs_setup_time = 0; - hw->user1.cs_hold_time = 0; - - //use all 64 bytes of the buffer - hw->user.usr_miso_highpart = 0; - hw->user.usr_mosi_highpart = 0; - - //Disable unneeded ints - hw->slave.val = 0; - hw->user.val = 0; - - hw->clk_gate.clk_en = 1; - hw->clk_gate.mst_clk_active = 1; - hw->clk_gate.mst_clk_sel = 1; - - hw->dma_conf.val = 0; - hw->dma_conf.tx_seg_trans_clr_en = 1; - hw->dma_conf.rx_seg_trans_clr_en = 1; - hw->dma_conf.dma_seg_trans_en = 0; -} - -/** - * Initialize SPI peripheral (slave). - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_slave_init(spi_dev_t *hw) -{ - //Configure slave - hw->clock.val = 0; - hw->user.val = 0; - hw->ctrl.val = 0; - hw->user.doutdin = 1; //we only support full duplex - hw->user.sio = 0; - hw->slave.slave_mode = 1; - hw->slave.soft_reset = 1; - hw->slave.soft_reset = 0; - //use all 64 bytes of the buffer - hw->user.usr_miso_highpart = 0; - hw->user.usr_mosi_highpart = 0; - - hw->dma_conf.dma_seg_trans_en = 0; - - //Disable unneeded ints - hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; -} - -/** - * Initialize SPI peripheral (slave half duplex mode) - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_slave_hd_init(spi_dev_t *hw) -{ - hw->clock.val = 0; - hw->user.val = 0; - hw->ctrl.val = 0; - hw->user.doutdin = 0; - hw->user.sio = 0; - - hw->slave.soft_reset = 1; - hw->slave.soft_reset = 0; - hw->slave.slave_mode = 1; -} - -/** - * Check whether user-defined transaction is done. - * - * @param hw Beginning address of the peripheral registers. - * - * @return True if transaction is done, otherwise false. - */ -static inline bool spi_ll_usr_is_done(spi_dev_t *hw) -{ - return hw->dma_int_raw.trans_done; -} - -/** - * Trigger start of user-defined transaction for master. - * The synchronization between two clock domains is required in ESP32-S3 - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_master_user_start(spi_dev_t *hw) -{ - hw->cmd.update = 1; - while (hw->cmd.update); - hw->cmd.usr = 1; -} - -/** - * Trigger start of user-defined transaction for slave. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_slave_user_start(spi_dev_t *hw) -{ - hw->cmd.usr = 1; -} - -/** - * Get current running command bit-mask. (Preview) - * - * @param hw Beginning address of the peripheral registers. - * - * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. - */ -static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) -{ - return hw->cmd.val; -} - -/** - * Reset the slave peripheral before next transaction. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_slave_reset(spi_dev_t *hw) -{ - hw->slave.soft_reset = 1; - hw->slave.soft_reset = 0; -} - -/** - * Reset SPI CPU TX FIFO - * - * On ESP32H4, this function is not seperated - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw) -{ - hw->dma_conf.buf_afifo_rst = 1; - hw->dma_conf.buf_afifo_rst = 0; -} - -/** - * Reset SPI CPU RX FIFO - * - * On ESP32H4, this function is not seperated - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw) -{ - hw->dma_conf.rx_afifo_rst = 1; - hw->dma_conf.rx_afifo_rst = 0; -} - -/** - * Reset SPI DMA TX FIFO - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw) -{ - hw->dma_conf.dma_afifo_rst = 1; - hw->dma_conf.dma_afifo_rst = 0; -} - -/** - * Reset SPI DMA RX FIFO - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) -{ - hw->dma_conf.rx_afifo_rst = 1; - hw->dma_conf.rx_afifo_rst = 0; -} - -/** - * Clear in fifo full error - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) -{ - hw->dma_int_clr.infifo_full_err = 1; -} - -/** - * Clear out fifo empty error - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) -{ - hw->dma_int_clr.outfifo_empty_err = 1; -} - -/*------------------------------------------------------------------------------ - * DMA - *----------------------------------------------------------------------------*/ -/** - * Enable/Disable RX DMA (Peripherals->DMA->RAM) - * - * @param hw Beginning address of the peripheral registers. - * @param enable 1: enable; 2: disable - */ -static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) -{ - hw->dma_conf.dma_rx_ena = enable; -} - -/** - * Enable/Disable TX DMA (RAM->DMA->Peripherals) - * - * @param hw Beginning address of the peripheral registers. - * @param enable 1: enable; 2: disable - */ -static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) -{ - hw->dma_conf.dma_tx_ena = enable; -} - -/** - * Configuration of RX DMA EOF interrupt generation way - * - * @param hw Beginning address of the peripheral registers. - * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. - */ -static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable) -{ - hw->dma_conf.rx_eof_en = enable; -} - -/*------------------------------------------------------------------------------ - * Buffer - *----------------------------------------------------------------------------*/ -/** - * Write to SPI hardware data buffer. - * - * @param hw Beginning address of the peripheral registers. - * @param buffer_to_send Address of the data to be written to the hardware data buffer. - * @param bitlen Length to write, in bits. - */ -static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) -{ - for (int x = 0; x < bitlen; x += 32) { - //Use memcpy to get around alignment issues for txdata - uint32_t word; - memcpy(&word, &buffer_to_send[x / 8], 4); - hw->data_buf[(x / 32)] = word; - } -} - -/** - * Write to SPI hardware data buffer by buffer ID (address) - * - * @param hw Beginning address of the peripheral registers - * @param byte_id Start ID (address) of the hardware buffer to be written - * @param data Address of the data to be written to the hardware data buffer. - * @param len Length to write, in bytes. - */ -static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *data, int len) -{ - HAL_ASSERT(byte_id + len <= 64); - HAL_ASSERT(len > 0); - HAL_ASSERT(byte_id >= 0); - - while (len > 0) { - uint32_t word; - int offset = byte_id % 4; - int copy_len = 4 - offset; - if (copy_len > len) { - copy_len = len; - } - - //read-modify-write - if (copy_len != 4) { - word = hw->data_buf[byte_id / 4]; //read - } - memcpy(((uint8_t *)&word) + offset, data, copy_len); //modify - hw->data_buf[byte_id / 4] = word; //write - - data += copy_len; - byte_id += copy_len; - len -= copy_len; - } -} - -/** - * Read from SPI hardware data buffer. - * - * @param hw Beginning address of the peripheral registers. - * @param buffer_to_rcv Address of a buffer to read data from hardware data buffer - * @param bitlen Length to read, in bits. - */ -static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) -{ - for (int x = 0; x < bitlen; x += 32) { - //Do a memcpy to get around possible alignment issues in rx_buffer - uint32_t word = hw->data_buf[x / 32]; - int len = bitlen - x; - if (len > 32) { - len = 32; - } - memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); - } -} - -/** - * Read from SPI hardware data buffer by buffer ID (address) - * - * @param hw Beginning address of the peripheral registers - * @param byte_id Start ID (address) of the hardware buffer to be read - * @param data Address of a buffer to read data from hardware data buffer - * @param len Length to read, in bytes. - */ -static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_id, uint8_t *out_data, int len) -{ - while (len > 0) { - uint32_t word = hw->data_buf[byte_id / 4]; - int offset = byte_id % 4; - int copy_len = 4 - offset; - if (copy_len > len) { - copy_len = len; - } - - memcpy(out_data, ((uint8_t *)&word) + offset, copy_len); - byte_id += copy_len; - out_data += copy_len; - len -= copy_len; - } -} - -/*------------------------------------------------------------------------------ - * Configs: mode - *----------------------------------------------------------------------------*/ -/** - * Enable/disable the postive-cs feature. - * - * @param hw Beginning address of the peripheral registers. - * @param cs One of the CS (0-2) to enable/disable the feature. - * @param pos_cs True to enable the feature, otherwise disable (default). - */ -static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_cs) -{ - if (pos_cs) { - hw->misc.master_cs_pol |= (1 << cs); - } else { - hw->misc.master_cs_pol &= ~(1 << cs); - } -} - -/** - * Enable/disable the LSBFIRST feature for TX data. - * - * @param hw Beginning address of the peripheral registers. - * @param lsbfirst True if LSB of TX data to be sent first, otherwise MSB is sent first (default). - */ -static inline void spi_ll_set_tx_lsbfirst(spi_dev_t *hw, bool lsbfirst) -{ - hw->ctrl.wr_bit_order = lsbfirst; -} - -/** - * Enable/disable the LSBFIRST feature for RX data. - * - * @param hw Beginning address of the peripheral registers. - * @param lsbfirst True if first bit received as LSB, otherwise as MSB (default). - */ -static inline void spi_ll_set_rx_lsbfirst(spi_dev_t *hw, bool lsbfirst) -{ - hw->ctrl.rd_bit_order = lsbfirst; -} - -/** - * Set SPI mode for the peripheral as master. - * - * @param hw Beginning address of the peripheral registers. - * @param mode SPI mode to work at, 0-3. - */ -static inline void spi_ll_master_set_mode(spi_dev_t *hw, uint8_t mode) -{ - //Configure polarity - if (mode == 0) { - hw->misc.ck_idle_edge = 0; - hw->user.ck_out_edge = 0; - } else if (mode == 1) { - hw->misc.ck_idle_edge = 0; - hw->user.ck_out_edge = 1; - } else if (mode == 2) { - hw->misc.ck_idle_edge = 1; - hw->user.ck_out_edge = 1; - } else if (mode == 3) { - hw->misc.ck_idle_edge = 1; - hw->user.ck_out_edge = 0; - } -} - -/** - * Set SPI mode for the peripheral as slave. - * - * @param hw Beginning address of the peripheral registers. - * @param mode SPI mode to work at, 0-3. - */ -static inline void spi_ll_slave_set_mode(spi_dev_t *hw, const int mode, bool dma_used) -{ - if (mode == 0) { - hw->misc.ck_idle_edge = 0; - hw->user.rsck_i_edge = 0; - hw->user.tsck_i_edge = 0; - hw->slave.clk_mode_13 = 0; - } else if (mode == 1) { - hw->misc.ck_idle_edge = 0; - hw->user.rsck_i_edge = 1; - hw->user.tsck_i_edge = 1; - hw->slave.clk_mode_13 = 1; - } else if (mode == 2) { - hw->misc.ck_idle_edge = 1; - hw->user.rsck_i_edge = 1; - hw->user.tsck_i_edge = 1; - hw->slave.clk_mode_13 = 0; - } else if (mode == 3) { - hw->misc.ck_idle_edge = 1; - hw->user.rsck_i_edge = 0; - hw->user.tsck_i_edge = 0; - hw->slave.clk_mode_13 = 1; - } - hw->slave.rsck_data_out = 0; -} - -/** - * Set SPI to work in full duplex or half duplex mode. - * - * @param hw Beginning address of the peripheral registers. - * @param half_duplex True to work in half duplex mode, otherwise in full duplex mode. - */ -static inline void spi_ll_set_half_duplex(spi_dev_t *hw, bool half_duplex) -{ - hw->user.doutdin = !half_duplex; -} - -/** - * Set SPI to work in SIO mode or not. - * - * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode. - * - * @param hw Beginning address of the peripheral registers. - * @param sio_mode True to work in SIO mode, otherwise false. - */ -static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) -{ - hw->user.sio = sio_mode; -} - -/** - * Configure the SPI transaction line mode for the master to use. - * - * @param hw Beginning address of the peripheral registers. - * @param line_mode SPI transaction line mode to use, see ``spi_line_mode_t``. - */ -static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode) -{ - hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK; - hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK; - hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2); - hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4); - hw->ctrl.faddr_dual = (line_mode.addr_lines == 2); - hw->ctrl.faddr_quad = (line_mode.addr_lines == 4); - hw->ctrl.fread_dual = (line_mode.data_lines == 2); - hw->user.fwrite_dual = (line_mode.data_lines == 2); - hw->ctrl.fread_quad = (line_mode.data_lines == 4); - hw->user.fwrite_quad = (line_mode.data_lines == 4); -} - -/** - * Set the SPI slave to work in segment transaction mode - * - * @param hw Beginning address of the peripheral registers. - * @param seg_trans True to work in seg mode, otherwise false. - */ -static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) -{ - hw->dma_conf.dma_seg_trans_en = seg_trans; -} - -/** - * Select one of the CS to use in current transaction. - * - * @param hw Beginning address of the peripheral registers. - * @param cs_id The cs to use, 0-2, otherwise none of them is used. - */ -static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) -{ - hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; - hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; - hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; - hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; - hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; - hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; -} - -/** - * Keep Chip Select activated after the current transaction. - * - * @param hw Beginning address of the peripheral registers. - * @param keep_active if 0 don't keep CS activated, else keep CS activated - */ -static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) -{ - hw->misc.cs_keep_active = (keep_active != 0) ? 1 : 0; -} - -/*------------------------------------------------------------------------------ - * Configs: parameters - *----------------------------------------------------------------------------*/ -/** - * Set the clock for master by stored value. - * - * @param hw Beginning address of the peripheral registers. - * @param val Stored clock configuration calculated before (by ``spi_ll_cal_clock``). - */ -static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) -{ - hw->clock.val = *(uint32_t *)val; -} - -/** - * Get the frequency of given dividers. Don't use in app. - * - * @param fapb APB clock of the system. - * @param pre Pre devider. - * @param n Main divider. - * - * @return Frequency of given dividers. - */ -static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n) -{ - return (fapb / (pre * n)); -} - -/** - * Calculate the nearest frequency avaliable for master. - * - * @param fapb APB clock of the system. - * @param hz Frequncy desired. - * @param duty_cycle Duty cycle desired. - * @param out_reg Output address to store the calculated clock configurations for the return frequency. - * - * @return Actual (nearest) frequency. - */ -static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_ll_clock_val_t *out_reg) -{ - typeof(GPSPI2.clock) reg; - int eff_clk; - - //In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value. - if (hz > ((fapb / 4) * 3)) { - //Using Fapb directly will give us the best result here. - reg.clkcnt_l = 0; - reg.clkcnt_h = 0; - reg.clkcnt_n = 0; - reg.clkdiv_pre = 0; - reg.clk_equ_sysclk = 1; - eff_clk = fapb; - } else { - //For best duty cycle resolution, we want n to be as close to 32 as possible, but - //we also need a pre/n combo that gets us as close as possible to the intended freq. - //To do this, we bruteforce n and calculate the best pre to go along with that. - //If there's a choice between pre/n combos that give the same result, use the one - //with the higher n. - int pre, n, h, l; - int bestn = -1; - int bestpre = -1; - int besterr = 0; - int errval; - for (n = 2; n <= 64; n++) { //Start at 2: we need to be able to set h/l so we have at least one high and one low pulse. - //Effectively, this does pre=round((fapb/n)/hz). - pre = ((fapb / n) + (hz / 2)) / hz; - if (pre <= 0) { - pre = 1; - } - if (pre > 16) { - pre = 16; - } - errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz); - if (bestn == -1 || errval <= besterr) { - besterr = errval; - bestn = n; - bestpre = pre; - } - } - - n = bestn; - pre = bestpre; - l = n; - //This effectively does round((duty_cycle*n)/256) - h = (duty_cycle * n + 127) / 256; - if (h <= 0) { - h = 1; - } - - reg.clk_equ_sysclk = 0; - reg.clkcnt_n = n - 1; - reg.clkdiv_pre = pre - 1; - reg.clkcnt_h = h - 1; - reg.clkcnt_l = l - 1; - eff_clk = spi_ll_freq_for_pre_n(fapb, pre, n); - } - if (out_reg != NULL) { - *(uint32_t *)out_reg = reg.val; - } - return eff_clk; -} - -/** - * Calculate and set clock for SPI master according to desired parameters. - * - * This takes long, suggest to calculate the configuration during - * initialization by ``spi_ll_master_cal_clock`` and store the result, then - * configure the clock by stored value when used by - * ``spi_ll_msater_set_clock_by_reg``. - * - * @param hw Beginning address of the peripheral registers. - * @param fapb APB clock of the system. - * @param hz Frequncy desired. - * @param duty_cycle Duty cycle desired. - * - * @return Actual frequency that is used. - */ -static inline int spi_ll_master_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) -{ - spi_ll_clock_val_t reg_val; - int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); - spi_ll_master_set_clock_by_reg(hw, ®_val); - return freq; -} - -/** - * Set the mosi delay after the output edge to the signal. (Preview) - * - * The delay mode/num is a Espressif conception, may change in the new chips. - * - * @param hw Beginning address of the peripheral registers. - * @param delay_mode Delay mode, see TRM. - * @param delay_num APB clocks to delay. - */ -static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int delay_num) -{ -} - -/** - * Set the miso delay applied to the input signal before the internal peripheral. (Preview) - * - * The delay mode/num is a Espressif conception, may change in the new chips. - * - * @param hw Beginning address of the peripheral registers. - * @param delay_mode Delay mode, see TRM. - * @param delay_num APB clocks to delay. - */ -static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int delay_num) -{ -} - -/** - * Set the delay of SPI clocks before the CS inactive edge after the last SPI clock. - * - * @param hw Beginning address of the peripheral registers. - * @param hold Delay of SPI clocks after the last clock, 0 to disable the hold phase. - */ -static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold) -{ - hw->user1.cs_hold_time = hold - 1; - hw->user.cs_hold = hold ? 1 : 0; -} - -/** - * Set the delay of SPI clocks before the first SPI clock after the CS active edge. - * - * Note ESP32 doesn't support to use this feature when command/address phases - * are used in full duplex mode. - * - * @param hw Beginning address of the peripheral registers. - * @param setup Delay of SPI clocks after the CS active edge, 0 to disable the setup phase. - */ -static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) -{ - hw->user1.cs_setup_time = setup - 1; - hw->user.cs_setup = setup ? 1 : 0; -} - -/*------------------------------------------------------------------------------ - * Configs: data - *----------------------------------------------------------------------------*/ -/** - * Set the output length (master). - * This should be called before master setting MISO(input) length - * - * @param hw Beginning address of the peripheral registers. - * @param bitlen output length, in bits. - */ -static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) -{ - if (bitlen > 0) { - hw->ms_dlen.ms_data_bitlen = bitlen - 1; - } -} - -/** - * Set the input length (master). - * - * @param hw Beginning address of the peripheral registers. - * @param bitlen input length, in bits. - */ -static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) -{ - if (bitlen > 0) { - hw->ms_dlen.ms_data_bitlen = bitlen - 1; - } -} - -/** - * Set the maximum input length (slave). - * - * @param hw Beginning address of the peripheral registers. - * @param bitlen Input length, in bits. - */ -static inline void spi_ll_slave_set_rx_bitlen(spi_dev_t *hw, size_t bitlen) -{ - spi_ll_set_mosi_bitlen(hw, bitlen); -} - -/** - * Set the maximum output length (slave). - * - * @param hw Beginning address of the peripheral registers. - * @param bitlen Output length, in bits. - */ -static inline void spi_ll_slave_set_tx_bitlen(spi_dev_t *hw, size_t bitlen) -{ - spi_ll_set_mosi_bitlen(hw, bitlen); -} - -/** - * Set the length of command phase. - * - * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit - * command phases takes 4 cycles in 4-bit mode. - * - * @param hw Beginning address of the peripheral registers. - * @param bitlen Length of command phase, in bits. 0 to disable the command phase. - */ -static inline void spi_ll_set_command_bitlen(spi_dev_t *hw, int bitlen) -{ - hw->user2.usr_command_bitlen = bitlen - 1; - hw->user.usr_command = bitlen ? 1 : 0; -} - -/** - * Set the length of address phase. - * - * When in 4-bit mode, the SPI cycles of the phase will be shorter. E.g. 16-bit - * address phases takes 4 cycles in 4-bit mode. - * - * @param hw Beginning address of the peripheral registers. - * @param bitlen Length of address phase, in bits. 0 to disable the address phase. - */ -static inline void spi_ll_set_addr_bitlen(spi_dev_t *hw, int bitlen) -{ - hw->user1.usr_addr_bitlen = bitlen - 1; - hw->user.usr_addr = bitlen ? 1 : 0; -} - -/** - * Set the address value in an intuitive way. - * - * The length and lsbfirst is required to shift and swap the address to the right place. - * - * @param hw Beginning address of the peripheral registers. - * @param address Address to set - * @param addrlen Length of the address phase - * @param lsbfirst Whether the LSB first feature is enabled. - */ -static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, uint32_t lsbfirst) -{ - if (lsbfirst) { - /* The output address start from the LSB of the highest byte, i.e. - * addr[24] -> addr[31] - * ... - * addr[0] -> addr[7] - * So swap the byte order to let the LSB sent first. - */ - addr = HAL_SWAP32(addr); - //otherwise only addr register is sent - hw->addr = addr; - } else { - // shift the address to MSB of addr register. - // output address will be sent from MSB to LSB of addr register - hw->addr = addr << (32 - addrlen); - } -} - -/** - * Set the command value in an intuitive way. - * - * The length and lsbfirst is required to shift and swap the command to the right place. - * - * @param hw Beginning command of the peripheral registers. - * @param command Command to set - * @param addrlen Length of the command phase - * @param lsbfirst Whether the LSB first feature is enabled. - */ -static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, bool lsbfirst) -{ - if (lsbfirst) { - // The output command start from bit0 to bit 15, kept as is. - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); - } else { - /* Output command will be sent from bit 7 to 0 of command_value, and - * then bit 15 to 8 of the same register field. Shift and swap to send - * more straightly. - */ - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); - } -} - -/** - * Set dummy clocks to output before RX phase (master), or clocks to skip - * before the data phase and after the address phase (slave). - * - * Note this phase is also used to compensate RX timing in half duplex mode. - * - * @param hw Beginning address of the peripheral registers. - * @param dummy_n Dummy cycles used. 0 to disable the dummy phase. - */ -static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) -{ - hw->user.usr_dummy = dummy_n ? 1 : 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); -} - -/** - * Enable/disable the RX data phase. - * - * @param hw Beginning address of the peripheral registers. - * @param enable True if RX phase exist, otherwise false. - */ -static inline void spi_ll_enable_miso(spi_dev_t *hw, int enable) -{ - hw->user.usr_miso = enable; -} - -/** - * Enable/disable the TX data phase. - * - * @param hw Beginning address of the peripheral registers. - * @param enable True if TX phase exist, otherwise false. - */ -static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) -{ - hw->user.usr_mosi = enable; -} - -/** - * Get the received bit length of the slave. - * - * @param hw Beginning address of the peripheral registers. - * - * @return Received bits of the slave. - */ -static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) -{ - return hw->slave1.data_bitlen; -} - -/*------------------------------------------------------------------------------ - * Interrupts - *----------------------------------------------------------------------------*/ -//helper macros to generate code for each interrupts -#define FOR_EACH_ITEM(op, list) do { list(op) } while(0) -#define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done, dma_int_set.rd_buf_done_int_set) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done, dma_int_set.wr_dma_done_int_set) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8, dma_int_set.cmd8_int_set) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9, dma_int_set.cmd9_int_set) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set) - - -static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) -{ -#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; - FOR_EACH_ITEM(ENA_INTR, INTR_LIST); -#undef ENA_INTR -} - -static inline void spi_ll_disable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) -{ -#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; - FOR_EACH_ITEM(DIS_INTR, INTR_LIST); -#undef DIS_INTR -} - -static inline void spi_ll_set_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) -{ -#define SET_INTR(intr_bit, _, __, ___, set_reg) if (intr_mask & (intr_bit)) hw->set_reg = 1; - FOR_EACH_ITEM(SET_INTR, INTR_LIST); -#undef SET_INTR -} - -static inline void spi_ll_clear_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) -{ -#define CLR_INTR(intr_bit, _, __, clr_reg, ...) if (intr_mask & (intr_bit)) hw->clr_reg = 1; - FOR_EACH_ITEM(CLR_INTR, INTR_LIST); -#undef CLR_INTR -} - -static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) -{ -#define GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; - FOR_EACH_ITEM(GET_INTR, INTR_LIST); - return false; -#undef GET_INTR -} - -#undef FOR_EACH_ITEM -#undef INTR_LIST - -/** - * Disable the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_disable_int(spi_dev_t *hw) -{ - hw->dma_int_ena.trans_done = 0; -} - -/** - * Clear the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_clear_int_stat(spi_dev_t *hw) -{ - hw->dma_int_clr.trans_done = 1; -} - -/** - * Set the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_set_int_stat(spi_dev_t *hw) -{ - hw->dma_int_set.trans_done_int_set = 1; -} - -/** - * Enable the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_enable_int(spi_dev_t *hw) -{ - hw->dma_int_ena.trans_done = 1; -} - -/*------------------------------------------------------------------------------ - * Slave HD - *----------------------------------------------------------------------------*/ -static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) -{ - hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; -} - -static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) -{ - return hw->slave1.data_bitlen / 8; -} - -static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) -{ - return hw->slave1.last_addr; -} - -#undef SPI_LL_RST_MASK -#undef SPI_LL_UNUSED_INT_MASK - -/** - * Get the base spi command in esp32h4 - * - * @param cmd_t Command value - */ -static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) -{ - uint8_t cmd_base = 0x00; - switch (cmd_t) - { - case SPI_CMD_HD_WRBUF: - cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; - break; - case SPI_CMD_HD_RDBUF: - cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; - break; - case SPI_CMD_HD_WRDMA: - cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; - break; - case SPI_CMD_HD_RDDMA: - cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; - break; - case SPI_CMD_HD_SEG_END: - cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; - break; - case SPI_CMD_HD_EN_QPI: - cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; - break; - case SPI_CMD_HD_WR_END: - cmd_base = SPI_LL_BASE_CMD_HD_WR_END; - break; - case SPI_CMD_HD_INT0: - cmd_base = SPI_LL_BASE_CMD_HD_INT0; - break; - case SPI_CMD_HD_INT1: - cmd_base = SPI_LL_BASE_CMD_HD_INT1; - break; - case SPI_CMD_HD_INT2: - cmd_base = SPI_LL_BASE_CMD_HD_INT2; - break; - default: - HAL_ASSERT(cmd_base); - } - return cmd_base; -} - -/** - * Get the spi communication command - * - * @param cmd_t Base command value - * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. - */ -static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) -{ - uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); - uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit - - if (line_mode.data_lines == 2) { - if (line_mode.addr_lines == 2) { - cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit - } else { - cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit - } - } else if (line_mode.data_lines == 4) { - if (line_mode.addr_lines == 4) { - cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit - } else { - cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit - } - } - if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { - cmd_mod = 0x00; - } - - return cmd_base | cmd_mod; -} - -/** - * Get the dummy bits - * - * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. - */ -static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) -{ - return 8; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/spimem_flash_ll.h b/components/hal/esp32h4/include/hal/spimem_flash_ll.h deleted file mode 100644 index a1b425db09..0000000000 --- a/components/hal/esp32h4/include/hal/spimem_flash_ll.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The ll is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md - ******************************************************************************/ - -// The Lowlevel layer for SPI Flash - -#pragma once - -#include -#include // For MIN/MAX -#include -#include - -#include "soc/spi_periph.h" -#include "soc/spi_mem_struct.h" -#include "hal/assert.h" -#include "hal/spi_types.h" -#include "hal/spi_flash_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL )) -#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1) - -typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t; - -/*------------------------------------------------------------------------------ - * Control - *----------------------------------------------------------------------------*/ -/** - * Reset peripheral registers before configuration and starting control - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev) -{ - dev->user.val = 0; - dev->ctrl.val = 0; -} - -/** - * Check whether the previous operation is done. - * - * @param dev Beginning address of the peripheral registers. - * - * @return true if last command is done, otherwise false. - */ -static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev) -{ - return (dev->cmd.val == 0); -} - -/** - * Erase the flash chip. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_erase_chip(spi_mem_dev_t *dev) -{ - dev->cmd.flash_ce = 1; -} - -/** - * Erase the sector, the address should be set by spimem_flash_ll_set_address. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev) -{ - dev->ctrl.val = 0; - dev->cmd.flash_se = 1; -} - -/** - * Erase the block, the address should be set by spimem_flash_ll_set_address. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev) -{ - dev->cmd.flash_be = 1; -} - -/** - * Suspend erase/program operation. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev) -{ - dev->flash_sus_ctrl.flash_pes = 1; -} - -/** - * Resume suspended erase/program operation. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev) -{ - dev->flash_sus_ctrl.flash_per = 1; -} - -/** - * Initialize auto suspend mode, and esp32h4 doesn't support disable auto-suspend. - * - * @param dev Beginning address of the peripheral registers. - * @param auto_sus Enable/disable Flash Auto-Suspend. - */ -static inline void spimem_flash_ll_auto_suspend_init(spi_mem_dev_t *dev, bool auto_sus) -{ - dev->flash_sus_ctrl.flash_pes_en = auto_sus; -} - -/** - * Initialize auto resume mode - * - * @param dev Beginning address of the peripheral registers. - * @param auto_res Enable/Disable Flash Auto-Resume. - * - */ -static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool auto_res) -{ - dev->flash_sus_ctrl.pes_per_en = auto_res; -} - -/** - * Setup the flash suspend command, may vary from chips to chips. - * - * @param dev Beginning address of the peripheral registers. - * @param sus_cmd Flash suspend command. - * - */ -static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd); -} - -/** - * Setup the flash resume command, may vary from chips to chips. - * - * @param dev Beginning address of the peripheral registers. - * @param res_cmd Flash resume command. - * - */ -static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_per_command, res_cmd); -} - -/** - * Setup the flash read suspend status command, may vary from chips to chips. - * - * @param dev Beginning address of the peripheral registers. - * @param pesr_cmd Flash read suspend status command. - * - */ -static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd); -} - -/** - * Setup to check SUS/SUS1/SUS2 to ensure the suspend status of flashs. - * - * @param dev Beginning address of the peripheral registers. - * @param sus_check_sus_en 1: enable, 0: disable. - * - */ -static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en) -{ - dev->flash_sus_ctrl.sus_timeout_cnt = 5; - dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en; -} - -/** - * Setup to check SUS/SUS1/SUS2 to ensure the resume status of flashs. - * - * @param dev Beginning address of the peripheral registers. - * @param sus_check_sus_en 1: enable, 0: disable. - * - */ -static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en) -{ - dev->flash_sus_ctrl.sus_timeout_cnt = 5; - dev->flash_sus_ctrl.per_end_en = res_check_sus_en; -} - -/** - * Set 8 bit command to read suspend status - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf) -{ - dev->flash_sus_ctrl.frd_sus_2b = 0; - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); -} - -/** - * Initialize auto wait idle mode - * - * @param dev Beginning address of the peripheral registers. - * @param auto_waiti Enable/disable auto wait-idle function - */ -static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); - dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti; - dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; -} - -/** - * Return the suspend status of erase or program operations. - * - * @param dev Beginning address of the peripheral registers. - * - * @return true if suspended, otherwise false. - */ -static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev) -{ - return dev->sus_status.flash_sus; -} - -/** - * Enable/disable write protection for the flash chip. - * - * @param dev Beginning address of the peripheral registers. - * @param wp true to enable the protection, false to disable (write enable). - */ -static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp) -{ - if (wp) { - dev->cmd.flash_wrdi = 1; - } else { - dev->cmd.flash_wren = 1; - } -} - -/** - * Get the read data from the buffer after ``spimem_flash_ll_read`` is done. - * - * @param dev Beginning address of the peripheral registers. - * @param buffer Buffer to hold the output data - * @param read_len Length to get out of the buffer - */ -static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len) -{ - if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) { - // If everything is word-aligned, do a faster memcpy - memcpy(buffer, (void *)dev->data_buf, read_len); - } else { - // Otherwise, slow(er) path copies word by word - int copy_len = read_len; - for (int i = 0; i < (read_len + 3) / 4; i++) { - int word_len = MIN(sizeof(uint32_t), copy_len); - uint32_t word = dev->data_buf[i]; - memcpy(buffer, &word, word_len); - buffer = (void *)((intptr_t)buffer + word_len); - copy_len -= word_len; - } - } -} - -/** - * Set the data to be written in the data buffer. - * - * @param dev Beginning address of the peripheral registers. - * @param buffer Buffer holding the data - * @param length Length of data in bytes. - */ -static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length) -{ - // Load data registers, word at a time - int num_words = (length + 3) / 4; - for (int i = 0; i < num_words; i++) { - uint32_t word = 0; - uint32_t word_len = MIN(length, sizeof(word)); - memcpy(&word, buffer, word_len); - dev->data_buf[i] = word; - length -= word_len; - buffer = (void *)((intptr_t)buffer + word_len); - } -} - - -/** - * Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before - * this to set the address to program. - * - * @param dev Beginning address of the peripheral registers. - * @param buffer Buffer holding the data to program - * @param length Length to program. - */ -static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *buffer, uint32_t length) -{ - dev->user.usr_dummy = 0; - spimem_flash_ll_set_buffer_data(dev, buffer, length); - dev->cmd.flash_pp = 1; -} - -/** - * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases, - * should be configured before this is called. - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev) -{ - dev->cmd.usr = 1; -} - -/** - * Check whether the host is idle to perform new commands. - * - * @param dev Beginning address of the peripheral registers. - * - * @return true if the host is idle, otherwise false - */ -static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) -{ - return dev->fsm.spi0_mst_st == 0; -} - -/** - * Set phases for user-defined transaction to read - * - * @param dev Beginning address of the peripheral registers. - */ -static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) -{ - typeof (dev->user) user = { - .usr_command = 1, - .usr_mosi = 0, - .usr_miso = 1, - .usr_addr = 1, - }; - dev->user = user; -} -/*------------------------------------------------------------------------------ - * Configs - *----------------------------------------------------------------------------*/ -/** - * Select which pin to use for the flash - * - * @param dev Beginning address of the peripheral registers. - * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. - */ -static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) -{ - dev->misc.cs0_dis = (pin == 0) ? 0 : 1; - dev->misc.cs1_dis = (pin == 1) ? 0 : 1; -} - -/** - * Set the read io mode. - * - * @param dev Beginning address of the peripheral registers. - * @param read_mode I/O mode to use in the following transactions. - */ -static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode) -{ - typeof (dev->ctrl) ctrl = dev->ctrl; - ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); - ctrl.val |= SPI_MEM_FASTRD_MODE_M; - switch (read_mode) { - case SPI_FLASH_FASTRD: - //the default option - break; - case SPI_FLASH_QIO: - ctrl.fread_qio = 1; - break; - case SPI_FLASH_QOUT: - ctrl.fread_quad = 1; - break; - case SPI_FLASH_DIO: - ctrl.fread_dio = 1; - break; - case SPI_FLASH_DOUT: - ctrl.fread_dual = 1; - break; - case SPI_FLASH_SLOWRD: - ctrl.fastrd_mode = 0; - break; - default: - abort(); - } - dev->ctrl = ctrl; -} - -/** - * Set clock frequency to work at. - * - * @param dev Beginning address of the peripheral registers. - * @param clock_val pointer to the clock value to set - */ -static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll_clock_reg_t *clock_val) -{ - dev->clock.val = *clock_val; -} - -/** - * Set the input length, in bits. - * - * @param dev Beginning address of the peripheral registers. - * @param bitlen Length of input, in bits. - */ -static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) -{ - dev->user.usr_miso = bitlen > 0; - dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0; -} - -/** - * Set the output length, in bits (not including command, address and dummy - * phases) - * - * @param dev Beginning address of the peripheral registers. - * @param bitlen Length of output, in bits. - */ -static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) -{ - dev->user.usr_mosi = bitlen > 0; - dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0; -} - -/** - * Set the command. - * - * @param dev Beginning address of the peripheral registers. - * @param command Command to send - * @param bitlen Length of the command - */ -static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen) -{ - dev->user.usr_command = 1; - typeof(dev->user2) user2 = { - .usr_command_value = command, - .usr_command_bitlen = (bitlen - 1), - }; - dev->user2 = user2; -} - -/** - * Get the address length that is set in register, in bits. - * - * @param dev Beginning address of the peripheral registers. - * - */ -static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev) -{ - return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0; -} - -/** - * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write... - * - * @param dev Beginning address of the peripheral registers. - * @param bitlen Length of the address, in bits - */ -static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen) -{ - dev->user1.usr_addr_bitlen = (bitlen - 1); - dev->user.usr_addr = bitlen ? 1 : 0; -} - -/** - * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write... - * - * @param dev Beginning address of the peripheral registers. - * @param addr Address to send - */ -static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr) -{ - dev->addr = addr; -} - -/** - * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write... - * - * @param dev Beginning address of the peripheral registers. - * @param addr Address to send - */ -static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen) -{ - (void)bitlen; - spimem_flash_ll_set_address(dev, addr); -} - -/** - * Set the length of dummy cycles. - * - * @param dev Beginning address of the peripheral registers. - * @param dummy_n Cycles of dummy phases - */ -static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) -{ - dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; -} - -/** - * Set D/Q output level during dummy phase - * - * @param dev Beginning address of the peripheral registers. - * @param out_en whether to enable IO output for dummy phase - * @param out_level dummy output level - */ -static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t out_en, uint32_t out_lev) -{ - dev->ctrl.fdummy_out = out_en; - dev->ctrl.q_pol = out_lev; - dev->ctrl.d_pol = out_lev; -} - -/** - * Set CS hold time. - * - * @param dev Beginning address of the peripheral registers. - * @param hold_n CS hold time config used by the host. - */ -static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) -{ - dev->ctrl2.cs_hold_time = hold_n - 1; - dev->user.cs_hold = (hold_n > 0? 1: 0); -} - -static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) -{ - dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); - dev->ctrl2.cs_setup_time = cs_setup_time - 1; -} - -/** - * Get the spi flash source clock frequency. Used for calculating - * the divider parameters. - * - * @param None - * - * @return the frequency of spi flash clock source.(MHz) - */ -static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) -{ - // TODO: Default is PLL480M, this is hard-coded. - // In the future, we can get the CPU clock source by calling interface. - uint8_t clock_val = 0; - switch (SPIMEM0.core_clk_sel.spi01_clk_sel) { - case 0: - clock_val = 48; - break; - default: - abort(); - } - return clock_val; -} - -/** - * Calculate spi_flash clock frequency division parameters for register. - * - * @param clkdiv frequency division factor - * - * @return Register setting for the given clock division factor. - */ -static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) -{ - uint32_t div_parameter; - // See comments of `clock` in `spi_mem_struct.h` - if (clkdiv == 1) { - div_parameter = (1 << 31); - } else { - div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16)); - } - return div_parameter; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/systimer_ll.h b/components/hal/esp32h4/include/hal/systimer_ll.h deleted file mode 100644 index 44058c8b1c..0000000000 --- a/components/hal/esp32h4/include/hal/systimer_ll.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include -#include "soc/systimer_struct.h" -#include "soc/clk_tree_defs.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// All these functions get invoked either from ISR or HAL that linked to IRAM. -// Always inline these functions even no gcc optimization is applied. - -/******************* Clock *************************/ - -__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) -{ - dev->conf.clk_en = en; -} - -static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src) -{ - (void)clk_src; -} - -static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void) -{ - return SYSTIMER_CLK_SRC_XTAL; -} - -/******************* Counter *************************/ - -__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) -{ - if (en) { - dev->conf.val |= 1 << (30 - counter_id); - } else { - dev->conf.val &= ~(1 << (30 - counter_id)); - } -} - -__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) -{ - if (can) { - dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id); - } else { - dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id)); - } -} - -__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) -{ - dev->unit_op[counter_id].timer_unit_update = 1; -} - -__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) -{ - return dev->unit_op[counter_id].timer_unit_value_valid; -} - -__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) -{ - dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32; - dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF; -} - -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) -{ - return dev->unit_val[counter_id].lo.timer_unit_value_lo; -} - -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) -{ - return dev->unit_val[counter_id].hi.timer_unit_value_hi; -} - -__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) -{ - dev->unit_load[counter_id].val = 0x01; -} - -/******************* Alarm *************************/ - -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) -{ - dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; - dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF; -} - -__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) -{ - return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; -} - -__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) -{ - dev->target_conf[alarm_id].target_timer_unit_sel = counter_id; -} - -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) -{ - dev->target_conf[alarm_id].target_period_mode = 0; -} - -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) -{ - dev->target_conf[alarm_id].target_period_mode = 1; -} - -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) -{ - HAL_ASSERT(period < (1 << 26)); - dev->target_conf[alarm_id].target_period = period; -} - -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) -{ - return dev->target_conf[alarm_id].target_period; -} - -__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) -{ - dev->comp_load[alarm_id].val = 0x01; -} - -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) -{ - if (en) { - dev->conf.val |= 1 << (24 - alarm_id); - } else { - dev->conf.val &= ~(1 << (24 - alarm_id)); - } -} - -/******************* Interrupt *************************/ - -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) -{ - if (en) { - dev->int_ena.val |= 1 << alarm_id; - } else { - dev->int_ena.val &= ~(1 << alarm_id); - } -} - -__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) -{ - return dev->int_st.val & (1 << alarm_id); -} - -__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) -{ - dev->int_clr.val |= 1 << alarm_id; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/temperature_sensor_ll.h b/components/hal/esp32h4/include/hal/temperature_sensor_ll.h deleted file mode 100644 index 974c37b808..0000000000 --- a/components/hal/esp32h4/include/hal/temperature_sensor_ll.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in component/hal/readme.md - ******************************************************************************/ - -// The LL for temperature sensor - -#pragma once - -#include -#include -#include "hal/regi2c_ctrl.h" -#include "soc/regi2c_saradc.h" -#include "soc/apb_saradc_struct.h" -#include "soc/soc.h" -#include "soc/soc_caps.h" -#include "hal/temperature_sensor_types.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define TEMPERATURE_SENSOR_LL_ADC_FACTOR (0.4386) -#define TEMPERATURE_SENSOR_LL_DAC_FACTOR (27.88) -#define TEMPERATURE_SENSOR_LL_OFFSET_FACTOR (20.52) - -/** - * @brief Enable the temperature sensor power. - * - * @param enable true: enable the power. - */ -static inline void temperature_sensor_ll_enable(bool enable) -{ - APB_SARADC.apb_tsens_ctrl.tsens_pu = enable; -} - -/** - * @brief Enable the clock - */ -static inline void temperature_sensor_ll_clk_enable(bool enable) -{ - // No need to enable the temperature clock on esp32h4 -} - -/** - * @brief Select the clock source for temperature sensor. On ESP32-H4, temperature sensor - * can use XTAL or FOSC. To make it convenience, suggest using XTAL all the time. - * - * @param clk_src refer to ``temperature_sensor_clk_src_t`` - */ -static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t clk_src) -{ - uint8_t clk_sel = 0; - switch (clk_src) { - case TEMPERATURE_SENSOR_CLK_SRC_XTAL: - clk_sel = 1; - break; - case TEMPERATURE_SENSOR_CLK_SRC_RC_FAST: - clk_sel = 0; - break; - default: - HAL_ASSERT(false); - break; - } - APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = clk_sel; -} - -/** - * @brief Set the hardware range, you can refer to the table ``temperature_sensor_attributes`` - * - * @param tsens_dac ``reg_val`` in table ``temperature_sensor_attributes`` - */ -static inline void temperature_sensor_ll_set_range(uint32_t range) -{ - REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, range); -} - -/** - * @brief Get the raw value of temperature sensor. - * - * @return uint32_t raw_value - */ -static inline uint32_t temperature_sensor_ll_get_raw_value(void) -{ - return APB_SARADC.apb_tsens_ctrl.tsens_out; -} - -/** - * @brief Get the offset value of temperature sensor. - * - * @note This function is only used in legacy driver - * - * @return uint32_t offset value - */ -static inline uint32_t temperature_sensor_ll_get_offset(void) -{ - return REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); -} - -/** - * @brief Get the clock division factor value. - * - * @note This function is only used in legacy driver - * - * @return uint32_t clock division factor - */ -static inline uint32_t temperature_sensor_ll_get_clk_div(void) -{ - return APB_SARADC.apb_tsens_ctrl.tsens_clk_div; -} - -/** - * @brief Set the clock division factor value, actually this has no impact on temperature sensor. - * Suggest just keep it as default value 6. - * - * @note This function is only used in legacy driver - * - * @param clk_div clock division factor, range from 1-10 - */ -static inline void temperature_sensor_ll_set_clk_div(uint8_t clk_div) -{ - APB_SARADC.apb_tsens_ctrl.tsens_clk_div = clk_div; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/timer_ll.h b/components/hal/esp32h4/include/hal/timer_ll.h deleted file mode 100644 index b0fe1c7b6a..0000000000 --- a/components/hal/esp32h4/include/hal/timer_ll.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// Note that most of the register operations in this layer are non-atomic operations. - -#pragma once - -#include -#include "hal/assert.h" -#include "hal/misc.h" -#include "hal/timer_types.h" -#include "soc/timer_group_struct.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Get timer group register base address with giving group number -#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) -#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) - -/** - * @brief Set clock source for timer - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param clk_src Clock source - */ -static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src) -{ - switch (clk_src) { - case GPTIMER_CLK_SRC_AHB: - hw->hw_timer[timer_num].config.tx_use_xtal = 0; - break; - case GPTIMER_CLK_SRC_XTAL: - hw->hw_timer[timer_num].config.tx_use_xtal = 1; - break; - default: - HAL_ASSERT(false && "unsupported clock source"); - break; - } -} - -/** - * @brief Enable Timer Group (GPTimer) module clock - * - * @param hw Timer Group register base address - * @param timer_num Timer index in the group - * @param en true to enable, false to disable - */ -static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) -{ - (void)timer_num; // only one timer in the group - hw->regclk.timer_clk_is_active = en; -} - -/** - * @brief Enable alarm event - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param en True: enable alarm - * False: disable alarm - */ -__attribute__((always_inline)) -static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en) -{ - hw->hw_timer[timer_num].config.tx_alarm_en = en; -} - -/** - * @brief Set clock prescale for timer - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param divider Prescale value (0 and 1 are not valid) - */ -static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) -{ - HAL_ASSERT(divider >= 2 && divider <= 65536); - if (divider >= 65536) { - divider = 0; - } - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); - hw->hw_timer[timer_num].config.tx_divcnt_rst = 1; -} - -/** - * @brief Enable auto-reload mode - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param en True: enable auto reload mode - * False: disable auto reload mode - */ -__attribute__((always_inline)) -static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en) -{ - hw->hw_timer[timer_num].config.tx_autoreload = en; -} - -/** - * @brief Set count direction - * - * @param hw Timer peripheral register base address - * @param timer_num Timer number in the group - * @param direction Count direction - */ -static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction) -{ - hw->hw_timer[timer_num].config.tx_increase = direction == GPTIMER_COUNT_UP; -} - -/** - * @brief Enable timer, start couting - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param en True: enable the counter - * False: disable the counter - */ -__attribute__((always_inline)) -static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en) -{ - hw->hw_timer[timer_num].config.tx_en = en; -} - -/** - * @brief Trigger software capture event - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - */ -__attribute__((always_inline)) -static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) -{ - hw->hw_timer[timer_num].update.tx_update = 1; - // Timer register is in a different clock domain from Timer hardware logic - // We need to wait for the update to take effect before fetching the count value - while (hw->hw_timer[timer_num].update.tx_update) { - } -} - -/** - * @brief Get counter value - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * - * @return counter value - */ -__attribute__((always_inline)) -static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) -{ - return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); -} - -/** - * @brief Set alarm value - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param alarm_value When counter reaches alarm value, alarm event will be triggered - */ -__attribute__((always_inline)) -static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) -{ - hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32); - hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value; -} - -/** - * @brief Set reload value - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @param reload_val Reload counter value - */ -__attribute__((always_inline)) -static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val) -{ - hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32); - hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val; -} - -/** - * @brief Get reload value - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - * @return reload count value - */ -static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num) -{ - return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo); -} - -/** - * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately - * - * @param hw Timer Group register base address - * @param timer_num Timer number in the group - */ -static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num) -{ - hw->hw_timer[timer_num].load.tx_load = 1; -} - -/** - * @brief Enable timer interrupt by mask - * - * @param hw Timer Group register base address - * @param mask Mask of interrupt events - * @param en True: enable interrupt - * False: disable interrupt - */ -__attribute__((always_inline)) -static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en) -{ - if (en) { - hw->int_ena_timers.val |= mask; - } else { - hw->int_ena_timers.val &= ~mask; - } -} - -/** - * @brief Get interrupt status - * - * @param hw Timer Group register base address - * - * @return Interrupt status - */ -__attribute__((always_inline)) -static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw) -{ - return hw->int_st_timers.val & 0x01; -} - -/** - * @brief Clear interrupt status by mask - * - * @param hw Timer Group register base address - * @param mask Interrupt events mask - */ -__attribute__((always_inline)) -static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask) -{ - hw->int_clr_timers.val = mask; -} - -/** - * @brief Enable the register clock forever - * - * @param hw Timer Group register base address - * @param en True: Enable the register clock forever - * False: Register clock is enabled only when register operation happens - */ -static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en) -{ - hw->regclk.clk_en = en; -} - -/** - * @brief Get interrupt status register address - * - * @param hw Timer Group register base address - * - * @return Interrupt status register address - */ -static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw) -{ - return &hw->int_st_timers.val; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/uart_ll.h b/components/hal/esp32h4/include/hal/uart_ll.h deleted file mode 100644 index ae37584acd..0000000000 --- a/components/hal/esp32h4/include/hal/uart_ll.h +++ /dev/null @@ -1,1025 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for UART register operations. -// Note that most of the register operations in this layer are non-atomic operations. - - -#pragma once - -#include "hal/misc.h" -#include "hal/uart_types.h" -#include "soc/uart_periph.h" -#include "soc/uart_struct.h" -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// The default fifo depth -#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN) -// Get UART hardware instance with giving uart num -#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1)) - -#define UART_LL_MIN_WAKEUP_THRESH (2) -#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask - -#define UART_LL_FSM_IDLE (0x0) -#define UART_LL_FSM_TX_WAIT_SEND (0xf) - -// Define UART interrupts -typedef enum { - UART_INTR_RXFIFO_FULL = (0x1 << 0), - UART_INTR_TXFIFO_EMPTY = (0x1 << 1), - UART_INTR_PARITY_ERR = (0x1 << 2), - UART_INTR_FRAM_ERR = (0x1 << 3), - UART_INTR_RXFIFO_OVF = (0x1 << 4), - UART_INTR_DSR_CHG = (0x1 << 5), - UART_INTR_CTS_CHG = (0x1 << 6), - UART_INTR_BRK_DET = (0x1 << 7), - UART_INTR_RXFIFO_TOUT = (0x1 << 8), - UART_INTR_SW_XON = (0x1 << 9), - UART_INTR_SW_XOFF = (0x1 << 10), - UART_INTR_GLITCH_DET = (0x1 << 11), - UART_INTR_TX_BRK_DONE = (0x1 << 12), - UART_INTR_TX_BRK_IDLE = (0x1 << 13), - UART_INTR_TX_DONE = (0x1 << 14), - UART_INTR_RS485_PARITY_ERR = (0x1 << 15), - UART_INTR_RS485_FRM_ERR = (0x1 << 16), - UART_INTR_RS485_CLASH = (0x1 << 17), - UART_INTR_CMD_CHAR_DET = (0x1 << 18), - UART_INTR_WAKEUP = (0x1 << 19), -} uart_intr_t; - -/** - * @brief Configure the UART core reset. - * - * @param hw Beginning address of the peripheral registers. - * @param core_rst_en True to enable the core reset, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) -{ - hw->clk_conf.rst_core = core_rst_en; -} - -/** - * @brief Enable the UART clock. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) -{ - hw->clk_conf.sclk_en = 1; - hw->clk_conf.rx_sclk_en = 1; - hw->clk_conf.tx_sclk_en = 1; -} - -/** - * @brief Disable the UART clock. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) -{ - hw->clk_conf.sclk_en = 0; - hw->clk_conf.rx_sclk_en = 0; - hw->clk_conf.tx_sclk_en = 0; -} - -/** - * @brief Set the UART source clock. - * - * @param hw Beginning address of the peripheral registers. - * @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock. - * If the source clock is RTC/XTAL, the UART can still work when the APB changes. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) -{ - switch (source_clk) { - default: - case UART_SCLK_AHB: - hw->clk_conf.sclk_sel = 1; - break; - case UART_SCLK_RTC: - hw->clk_conf.sclk_sel = 2; - break; - case UART_SCLK_XTAL: - hw->clk_conf.sclk_sel = 3; - break; - } -} - -/** - * @brief Get the UART source clock type. - * - * @param hw Beginning address of the peripheral registers. - * @param source_clk The pointer to accept the UART source clock type. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) -{ - switch (hw->clk_conf.sclk_sel) { - default: - case 1: - *source_clk = UART_SCLK_AHB; - break; - case 2: - *source_clk = UART_SCLK_RTC; - break; - case 3: - *source_clk = UART_SCLK_XTAL; - break; - } -} - -/** - * @brief Configure the baud-rate. - * - * @param hw Beginning address of the peripheral registers. - * @param baud The baud rate to be set. - * @param sclk_freq Frequency of the clock source of UART, in Hz. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) -{ -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - int sclk_div = DIV_UP(sclk_freq, max_div * baud); - - uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. - hw->clk_div.div_int = clk_div >> 4; - hw->clk_div.div_frag = clk_div & 0xf; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP -} - -/** - * @brief Get the current baud-rate. - * - * @param hw Beginning address of the peripheral registers. - * @param sclk_freq Frequency of the clock source of UART, in Hz. - * - * @return The current baudrate - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) -{ - typeof(hw->clk_div) div_reg; - div_reg.val = hw->clk_div.val; - return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); -} - -/** - * @brief Enable the UART interrupt based on the given mask. - * - * @param hw Beginning address of the peripheral registers. - * @param mask The bitmap of the interrupts need to be enabled. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) -{ - hw->int_ena.val |= mask; -} - -/** - * @brief Disable the UART interrupt based on the given mask. - * - * @param hw Beginning address of the peripheral registers. - * @param mask The bitmap of the interrupts need to be disabled. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) -{ - hw->int_ena.val &= (~mask); -} - -/** - * @brief Get the UART raw interrupt status. - * - * @param hw Beginning address of the peripheral registers. - * - * @return The UART interrupt status. - */ -static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw) -{ - return hw->int_raw.val; -} - -/** - * @brief Get the UART interrupt status. - * - * @param hw Beginning address of the peripheral registers. - * - * @return The UART interrupt status. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) -{ - return hw->int_st.val; -} - -/** - * @brief Clear the UART interrupt status based on the given mask. - * - * @param hw Beginning address of the peripheral registers. - * @param mask The bitmap of the interrupts need to be cleared. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) -{ - hw->int_clr.val = mask; -} - -/** - * @brief Get status of enabled interrupt. - * - * @param hw Beginning address of the peripheral registers. - * - * @return interrupt enable value - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) -{ - return hw->int_ena.val; -} - -/** - * @brief Read the UART rxfifo. - * - * @param hw Beginning address of the peripheral registers. - * @param buf The data buffer. The buffer size should be large than 128 byts. - * @param rd_len The data length needs to be read. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) -{ - for (int i = 0; i < (int)rd_len; i++) { - buf[i] = hw->ahb_fifo.rw_byte; - } -} - -/** - * @brief Write byte to the UART txfifo. - * - * @param hw Beginning address of the peripheral registers. - * @param buf The data buffer. - * @param wr_len The data length needs to be writen. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) -{ - for (int i = 0; i < (int)wr_len; i++) { - hw->ahb_fifo.rw_byte = buf[i]; - } -} - -/** - * @brief Reset the UART hw rxfifo. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) -{ - hw->conf0.rxfifo_rst = 1; - hw->conf0.rxfifo_rst = 0; -} - -/** - * @brief Reset the UART hw txfifo. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) -{ - hw->conf0.txfifo_rst = 1; - hw->conf0.txfifo_rst = 0; -} - -/** - * @brief Get the length of readable data in UART rxfifo. - * - * @param hw Beginning address of the peripheral registers. - * - * @return The readable data length in rxfifo. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) -{ - return hw->status.rxfifo_cnt; -} - -/** - * @brief Get the writable data length of UART txfifo. - * - * @param hw Beginning address of the peripheral registers. - * - * @return The data length of txfifo can be written. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) -{ - return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; -} - -/** - * @brief Configure the UART stop bit. - * - * @param hw Beginning address of the peripheral registers. - * @param stop_bit The stop bit number to be set. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) -{ - hw->conf0.stop_bit_num = stop_bit; -} - -/** - * @brief Get the configuration of the UART stop bit. - * - * @param hw Beginning address of the peripheral registers. - * @param stop_bit The pointer to accept the stop bit configuration - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) -{ - *stop_bit = (uart_stop_bits_t)hw->conf0.stop_bit_num; -} - -/** - * @brief Configure the UART parity check mode. - * - * @param hw Beginning address of the peripheral registers. - * @param parity_mode The parity check mode to be set. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) -{ - if (parity_mode != UART_PARITY_DISABLE) { - hw->conf0.parity = parity_mode & 0x1; - } - hw->conf0.parity_en = (parity_mode >> 1) & 0x1; -} - -/** - * @brief Get the UART parity check mode configuration. - * - * @param hw Beginning address of the peripheral registers. - * @param parity_mode The pointer to accept the parity check mode configuration. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) -{ - if (hw->conf0.parity_en) { - *parity_mode = (uart_parity_t)(0x2 | hw->conf0.parity); - } else { - *parity_mode = UART_PARITY_DISABLE; - } -} - -/** - * @brief Set the UART rxfifo full threshold value. When the data in rxfifo is more than the threshold value, - * it will produce rxfifo_full_int_raw interrupt. - * - * @param hw Beginning address of the peripheral registers. - * @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `UART_LL_FIFO_DEF_LEN`. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) -{ - hw->conf1.rxfifo_full_thrhd = full_thrhd; -} - -/** - * @brief Set the txfifo empty threshold. when the data length in txfifo is less than threshold value, - * it will produce txfifo_empty_int_raw interrupt. - * - * @param hw Beginning address of the peripheral registers. - * @param empty_thrhd The empty threshold of txfifo. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) -{ - hw->conf1.txfifo_empty_thrhd = empty_thrhd; -} - -/** - * @brief Set the UART rx-idle threshold value. when receiver takes more time than rx_idle_thrhd to receive a byte data, - * it will produce frame end signal for uhci to stop receiving data. - * - * @param hw Beginning address of the peripheral registers. - * @param rx_idle_thr The rx-idle threshold to be set. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) -{ - hw->idle_conf.rx_idle_thrhd = rx_idle_thr; -} - -/** - * @brief Configure the duration time between transfers. - * - * @param hw Beginning address of the peripheral registers. - * @param idle_num the duration time between transfers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) -{ - hw->idle_conf.tx_idle_num = idle_num; -} - -/** - * @brief Configure the transmiter to send break chars. - * - * @param hw Beginning address of the peripheral registers. - * @param break_num The number of the break chars need to be send. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) -{ - if (break_num > 0) { - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); - hw->conf0.txd_brk = 1; - } else { - hw->conf0.txd_brk = 0; - } -} - -/** - * @brief Configure the UART hardware flow control. - * - * @param hw Beginning address of the peripheral registers. - * @param flow_ctrl The hw flow control configuration. - * @param rx_thrs The rx flow control signal will be active if the data length in rxfifo is more than this value. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs) -{ - //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. - if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { - hw->mem_conf.rx_flow_thrhd = rx_thrs; - hw->conf1.rx_flow_en = 1; - } else { - hw->conf1.rx_flow_en = 0; - } - if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { - hw->conf0.tx_flow_en = 1; - } else { - hw->conf0.tx_flow_en = 0; - } -} - -/** - * @brief Configure the hardware flow control. - * - * @param hw Beginning address of the peripheral registers. - * @param flow_ctrl A pointer to accept the hw flow control configuration. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) -{ - *flow_ctrl = UART_HW_FLOWCTRL_DISABLE; - if (hw->conf1.rx_flow_en) { - *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS); - } - if (hw->conf0.tx_flow_en) { - *flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS); - } -} - -/** - * @brief Configure the software flow control. - * - * @param hw Beginning address of the peripheral registers. - * @param flow_ctrl The UART sofware flow control settings. - * @param sw_flow_ctrl_en Set true to enable software flow control, otherwise set it false. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en) -{ - if (sw_flow_ctrl_en) { - hw->flow_conf.xonoff_del = 1; - hw->flow_conf.sw_flow_con_en = 1; - hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; - hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); - } else { - hw->flow_conf.sw_flow_con_en = 0; - hw->flow_conf.xonoff_del = 0; - } -} - -/** - * @brief Configure the AT cmd char. When the receiver receives a continuous AT cmd char, it will produce at_cmd_char_det interrupt. - * - * @param hw Beginning address of the peripheral registers. - * @param cmd_char The AT cmd char configuration.The configuration member is: - * - cmd_char The AT cmd character - * - char_num The number of received AT cmd char must be equal to or greater than this value - * - gap_tout The interval between each AT cmd char, when the duration is less than this value, it will not take this data as AT cmd char - * - pre_idle The idle time before the first AT cmd char, when the duration is less than this value, it will not take the previous data as the last AT cmd char - * - post_idle The idle time after the last AT cmd char, when the duration is less than this value, it will not take this data as the first AT cmd char - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); -} - -/** - * @brief Set the UART data bit mode. - * - * @param hw Beginning address of the peripheral registers. - * @param data_bit The data bit mode to be set. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) -{ - hw->conf0.bit_num = data_bit; -} - -/** - * @brief Set the rts active level. - * - * @param hw Beginning address of the peripheral registers. - * @param level The rts active level, 0 or 1. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) -{ - hw->conf0.sw_rts = level & 0x1; -} - -/** - * @brief Set the dtr active level. - * - * @param hw Beginning address of the peripheral registers. - * @param level The dtr active level, 0 or 1. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) -{ - hw->conf0.sw_dtr = level & 0x1; -} - -/** - * @brief Set the UART wakeup threshold. - * - * @param hw Beginning address of the peripheral registers. - * @param wakeup_thrd The wakeup threshold value to be set. When the input rx edge changes more than this value, - * the UART will active from light sleeping mode. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) -{ - hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; -} - -/** - * @brief Configure the UART work in normal mode. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) -{ - hw->rs485_conf.en = 0; - hw->rs485_conf.tx_rx_en = 0; - hw->rs485_conf.rx_busy_tx_en = 0; - hw->conf0.irda_en = 0; -} - -/** - * @brief Configure the UART work in rs485_app_ctrl mode. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) -{ - // Application software control, remove echo - hw->rs485_conf.rx_busy_tx_en = 1; - hw->conf0.irda_en = 0; - hw->conf0.sw_rts = 0; - hw->conf0.irda_en = 0; - hw->rs485_conf.dl0_en = 1; - hw->rs485_conf.dl1_en = 1; - hw->rs485_conf.en = 1; -} - -/** - * @brief Configure the UART work in rs485_half_duplex mode. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) -{ - // Enable receiver, sw_rts = 1 generates low level on RTS pin - hw->conf0.sw_rts = 1; - // Half duplex mode - hw->rs485_conf.tx_rx_en = 0; - // Setting this bit will allow data to be transmitted while receiving data(full-duplex mode). - // But note that this full-duplex mode has no conflict detection function - hw->rs485_conf.rx_busy_tx_en = 0; - hw->conf0.irda_en = 0; - hw->rs485_conf.dl0_en = 1; - hw->rs485_conf.dl1_en = 1; - hw->rs485_conf.en = 1; -} - -/** - * @brief Configure the UART work in collision_detect mode. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) -{ - hw->conf0.irda_en = 0; - // Enable full-duplex mode - hw->rs485_conf.tx_rx_en = 1; - // Transmitter should send data when the receiver is busy, - hw->rs485_conf.rx_busy_tx_en = 1; - hw->rs485_conf.dl0_en = 1; - hw->rs485_conf.dl1_en = 1; - hw->conf0.sw_rts = 0; - hw->rs485_conf.en = 1; -} - -/** - * @brief Configure the UART work in irda mode. - * - * @param hw Beginning address of the peripheral registers. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) -{ - hw->rs485_conf.en = 0; - hw->rs485_conf.tx_rx_en = 0; - hw->rs485_conf.rx_busy_tx_en = 0; - hw->conf0.sw_rts = 0; - hw->conf0.irda_en = 1; -} - -/** - * @brief Set uart mode. - * - * @param hw Beginning address of the peripheral registers. - * @param mode The UART mode to be set. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) -{ - switch (mode) { - default: - case UART_MODE_UART: - uart_ll_set_mode_normal(hw); - break; - case UART_MODE_RS485_COLLISION_DETECT: - uart_ll_set_mode_collision_detect(hw); - break; - case UART_MODE_RS485_APP_CTRL: - uart_ll_set_mode_rs485_app_ctrl(hw); - break; - case UART_MODE_RS485_HALF_DUPLEX: - uart_ll_set_mode_rs485_half_duplex(hw); - break; - case UART_MODE_IRDA: - uart_ll_set_mode_irda(hw); - break; - } -} - -/** - * @brief Get the UART AT cmd char configuration. - * - * @param hw Beginning address of the peripheral registers. - * @param cmd_char The Pointer to accept value of UART AT cmd char. - * @param char_num Pointer to accept the repeat number of UART AT cmd char. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) -{ - *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); - *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); -} - -/** - * @brief Get the UART wakeup threshold value. - * - * @param hw Beginning address of the peripheral registers. - * - * @return The UART wakeup threshold value. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) -{ - return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH; -} - -/** - * @brief Get the UART data bit configuration. - * - * @param hw Beginning address of the peripheral registers. - * @param data_bit The pointer to accept the UART data bit configuration. - * - * @return The bit mode. - */ -FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) -{ - *data_bit = (uart_word_length_t)hw->conf0.bit_num; -} - -/** - * @brief Check if the UART sending state machine is in the IDLE state. - * - * @param hw Beginning address of the peripheral registers. - * - * @return True if the state machine is in the IDLE state, otherwise false is returned. - */ -FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) -{ - return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); -} - -/** - * @brief Check if the UART rts flow control is enabled. - * - * @param hw Beginning address of the peripheral registers. - * - * @return True if hw rts flow control is enabled, otherwise false is returned. - */ -FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) -{ - return hw->conf1.rx_flow_en; -} - -/** - * @brief Check if the UART cts flow control is enabled. - * - * @param hw Beginning address of the peripheral registers. - * - * @return True if hw cts flow control is enabled, otherwise false is returned. - */ -FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) -{ - return hw->conf0.tx_flow_en; -} - -/** - * @brief Configure TX signal loop back to RX module, just for the testing purposes - * - * @param hw Beginning address of the peripheral registers. - * @param loop_back_en Set ture to enable the loop back function, else set it false. - * - * @return None - */ -FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) -{ - hw->conf0.loopback = loop_back_en; -} - -FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) -{ - hw->flow_conf.force_xon = 1; - if(!always_on) { - hw->flow_conf.force_xon = 0; - } -} - -/** - * @brief Inverse the UART signal with the given mask. - * - * @param hw Beginning address of the peripheral registers. - * @param inv_mask The UART signal bitmap needs to be inversed. - * Use the ORred mask of `uart_signal_inv_t`; - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) -{ - typeof(hw->conf0) conf0_reg; - conf0_reg.val = hw->conf0.val; - conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0; - conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0; - conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0; - conf0_reg.cts_inv = (inv_mask & UART_SIGNAL_CTS_INV) ? 1 : 0; - conf0_reg.dsr_inv = (inv_mask & UART_SIGNAL_DSR_INV) ? 1 : 0; - conf0_reg.txd_inv = (inv_mask & UART_SIGNAL_TXD_INV) ? 1 : 0; - conf0_reg.rts_inv = (inv_mask & UART_SIGNAL_RTS_INV) ? 1 : 0; - conf0_reg.dtr_inv = (inv_mask & UART_SIGNAL_DTR_INV) ? 1 : 0; - hw->conf0.val = conf0_reg.val; -} - -/** - * @brief Configure the timeout value for receiver receiving a byte, and enable rx timeout function. - * - * @param hw Beginning address of the peripheral registers. - * @param tout_thrd The timeout value as UART bit time. The rx timeout function will be disabled if `tout_thrd == 0`. - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) -{ - uint16_t tout_val = tout_thrd; - if(tout_thrd > 0) { - hw->mem_conf.rx_tout_thrhd = tout_val; - hw->conf1.rx_tout_en = 1; - } else { - hw->conf1.rx_tout_en = 0; - } -} - -/** - * @brief Get the timeout value for receiver receiving a byte. - * - * @param hw Beginning address of the peripheral registers. - * - * @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0. - */ -FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) -{ - uint16_t tout_thrd = 0; - if(hw->conf1.rx_tout_en > 0) { - tout_thrd = hw->mem_conf.rx_tout_thrhd; - } - return tout_thrd; -} - -/** - * @brief Get UART maximum timeout threshold. - * - * @param hw Beginning address of the peripheral registers. - * - * @return maximum timeout threshold. - */ -FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) -{ - return UART_RX_TOUT_THRHD_V; -} - -/** - * @brief Configure the auto baudrate. - * - * @param hw Beginning address of the peripheral registers. - * @param enable Boolean marking whether the auto baudrate should be enabled or not. - */ -FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) -{ - hw->conf0.autobaud_en = enable ? 1 : 0; -} - -/** - * @brief Get the RXD edge count. - * - * @param hw Beginning address of the peripheral registers. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) -{ - return hw->rxd_cnt.edge_cnt; -} - -/** - * @brief Get the positive pulse minimum count. - * - * @param hw Beginning address of the peripheral registers. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) -{ - return hw->pospulse.min_cnt; -} - -/** - * @brief Get the negative pulse minimum count. - * - * @param hw Beginning address of the peripheral registers. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) -{ - return hw->negpulse.min_cnt; -} - -/** - * @brief Get the high pulse minimum count. - * - * @param hw Beginning address of the peripheral registers. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) -{ - return hw->highpulse.min_cnt; -} - -/** - * @brief Get the low pulse minimum count. - * - * @param hw Beginning address of the peripheral registers. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) -{ - return hw->lowpulse.min_cnt; -} - -/** - * @brief Force UART xoff. - * - * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num) -{ - REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); - REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); - REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); -} - -/** - * @brief Force UART xon. - * - * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). - * - * @return None. - */ -FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num) -{ - REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XOFF); - REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON); - REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON); - REG_SET_BIT(UART_ID_REG(uart_num), UART_UPDATE); -} - -/** - * @brief Get UART final state machine status. - * - * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). - * - * @return UART module FSM status. - */ -FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num) -{ - return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT); -} - -/** - * @brief Configure UART whether to discard when receiving wrong data - * - * @param hw Beginning address of the peripheral registers. - * @param discard true: Receiver stops storing data into FIFO when data is wrong - * false: Receiver continue storing data into FIFO when data is wrong - */ -FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard) -{ - hw->conf0.err_wr_mask = discard ? 1 : 0; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/uhci_ll.h b/components/hal/esp32h4/include/hal/uhci_ll.h deleted file mode 100644 index 8a31a42647..0000000000 --- a/components/hal/esp32h4/include/hal/uhci_ll.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer for UHCI register operations. -// Note that most of the register operations in this layer are non-atomic operations. - - -#pragma once -#include -#include "hal/uhci_types.h" -#include "soc/uhci_struct.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL)) - -typedef enum { - UHCI_RX_BREAK_CHR_EOF = 0x1, - UHCI_RX_IDLE_EOF = 0x2, - UHCI_RX_LEN_EOF = 0x4, - UHCI_RX_EOF_MAX = 0x7, -} uhci_rxeof_cfg_t; - -static inline void uhci_ll_init(uhci_dev_t *hw) -{ - typeof(hw->conf0) conf0_reg; - hw->conf0.clk_en = 1; - conf0_reg.val = 0; - conf0_reg.clk_en = 1; - hw->conf0.val = conf0_reg.val; - hw->conf1.val = 0; -} - -static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num) -{ - hw->conf0.uart0_ce = (uart_num == 0)? 1: 0; - hw->conf0.uart1_ce = (uart_num == 1)? 1: 0; -} - -static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char) -{ - if (seper_char->sub_chr_en) { - typeof(hw->esc_conf0) esc_conf0_reg = hw->esc_conf0; - esc_conf0_reg.seper_char = seper_char->seper_chr; - esc_conf0_reg.seper_esc_char0 = seper_char->sub_chr1; - esc_conf0_reg.seper_esc_char1 = seper_char->sub_chr2; - hw->esc_conf0.val = esc_conf0_reg.val; - hw->escape_conf.tx_c0_esc_en = 1; - hw->escape_conf.rx_c0_esc_en = 1; - } else { - hw->escape_conf.tx_c0_esc_en = 0; - hw->escape_conf.rx_c0_esc_en = 0; - } -} - -static inline void uhci_ll_get_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_chr) -{ - (void)hw; - (void)seper_chr; -} - -static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr) -{ - typeof(hw->escape_conf) escape_conf_reg = hw->escape_conf; - if (sub_ctr->flow_en == 1) { - typeof(hw->esc_conf2) esc_conf2_reg = hw->esc_conf2; - typeof(hw->esc_conf3) esc_conf3_reg = hw->esc_conf3; - esc_conf2_reg.seq1 = sub_ctr->xon_chr; - esc_conf2_reg.seq1_char0 = sub_ctr->xon_sub1; - esc_conf2_reg.seq1_char1 = sub_ctr->xon_sub2; - esc_conf3_reg.seq2 = sub_ctr->xoff_chr; - esc_conf3_reg.seq2_char0 = sub_ctr->xoff_sub1; - esc_conf3_reg.seq2_char1 = sub_ctr->xoff_sub2; - escape_conf_reg.tx_11_esc_en = 1; - escape_conf_reg.tx_13_esc_en = 1; - escape_conf_reg.rx_11_esc_en = 1; - escape_conf_reg.rx_13_esc_en = 1; - hw->esc_conf2.val = esc_conf2_reg.val; - hw->esc_conf3.val = esc_conf3_reg.val; - } else { - escape_conf_reg.tx_11_esc_en = 0; - escape_conf_reg.tx_13_esc_en = 0; - escape_conf_reg.rx_11_esc_en = 0; - escape_conf_reg.rx_13_esc_en = 0; - } - hw->escape_conf.val = escape_conf_reg.val; -} - -static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask) -{ - hw->int_ena.val |= intr_mask; -} - -static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask) -{ - hw->int_ena.val &= (~intr_mask); -} - -static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask) -{ - hw->int_clr.val = intr_mask; -} - -static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw) -{ - return hw->int_st.val; -} - - -static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode) -{ - if (eof_mode & UHCI_RX_BREAK_CHR_EOF) { - hw->conf0.uart_rx_brk_eof_en = 1; - } - if (eof_mode & UHCI_RX_IDLE_EOF) { - hw->conf0.uart_idle_eof_en = 1; - } - if (eof_mode & UHCI_RX_LEN_EOF) { - hw->conf0.len_eof_en = 1; - } -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/uhci_types.h b/components/hal/esp32h4/include/hal/uhci_types.h deleted file mode 100644 index 767ff66d27..0000000000 --- a/components/hal/esp32h4/include/hal/uhci_types.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - - -// Though the UHCI driver hasn't been published, some types are defined here -// for users to develop over the HAL. See example: controller_hci_uart_esp32h4 - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * @brief UHCI escape sequence - */ -typedef struct { - uint8_t seper_chr; /*!< escape sequence character */ - uint8_t sub_chr1; /*!< escape sequence sub-character 1 */ - uint8_t sub_chr2; /*!< escape sequence sub-character 2 */ - bool sub_chr_en; /*!< enable use of sub-chaacter of escape sequence */ -} uhci_seper_chr_t; - -/** - * @brief UHCI software flow control - */ -typedef struct { - uint8_t xon_chr; /*!< character for XON */ - uint8_t xon_sub1; /*!< sub-character 1 for XON */ - uint8_t xon_sub2; /*!< sub-character 2 for XON */ - uint8_t xoff_chr; /*!< character 2 for XOFF */ - uint8_t xoff_sub1; /*!< sub-character 1 for XOFF */ - uint8_t xoff_sub2; /*!< sub-character 2 for XOFF */ - uint8_t flow_en; /*!< enable use of software flow control */ -} uhci_swflow_ctrl_sub_chr_t; - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/usb_phy_ll.h b/components/hal/esp32h4/include/hal/usb_phy_ll.h deleted file mode 100644 index 40d4cd1800..0000000000 --- a/components/hal/esp32h4/include/hal/usb_phy_ll.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/usb_serial_jtag_struct.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Configures the internal PHY for USB_Serial_JTAG - * - * @param hw Start address of the USB Serial_JTAG registers - */ -static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw) -{ - // USB_Serial_JTAG use internal PHY - hw->conf0.phy_sel = 0; - // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) - hw->conf0.pad_pull_override = 0; - // Enable USB D+ pullup - hw->conf0.dp_pullup = 1; - // Enable USB pad function - hw->conf0.usb_pad_enable = 1; -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32h4/include/hal/usb_serial_jtag_ll.h deleted file mode 100644 index 304bbeaa42..0000000000 --- a/components/hal/esp32h4/include/hal/usb_serial_jtag_ll.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The LL layer of the USB-serial-jtag controller - -#pragma once - -#include "hal/misc.h" -#include "soc/usb_serial_jtag_reg.h" -#include "soc/usb_serial_jtag_struct.h" - -#ifdef __cplusplus -extern "C" { -#endif - -//The in and out endpoints are this long. -#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64 - -#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask - -// Define USB_SERIAL_JTAG interrupts -// Note the hardware has more interrupts, but they're only useful for debugging -// the hardware. -typedef enum { - USB_SERIAL_JTAG_INTR_SOF = (1 << 1), - USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2), - USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3), - USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8), - USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9), - USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10), -} usb_serial_jtag_intr_t; - -/** - * @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask. - * - * @param mask The bitmap of the interrupts need to be enabled. - * - * @return None - */ -static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask) -{ - USB_SERIAL_JTAG.int_ena.val |= mask; -} - -/** - * @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask. - * - * @param mask The bitmap of the interrupts need to be disabled. - * - * @return None - */ -static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask) -{ - USB_SERIAL_JTAG.int_ena.val &= (~mask); -} - -/** - * @brief Get the USB_SERIAL_JTAG interrupt status. - * - * @return The USB_SERIAL_JTAG interrupt status. - */ -static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void) -{ - return USB_SERIAL_JTAG.int_st.val; -} - -/** - * @brief Get the USB_SERIAL_JTAG raw interrupt status. - * - * @return The USB_SERIAL_JTAG raw interrupt status. - */ -static inline __attribute__((always_inline)) uint32_t usb_serial_jtag_ll_get_intraw_mask(void) -{ - return USB_SERIAL_JTAG.int_raw.val; -} - -/** - * @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask. - * - * @param mask The bitmap of the interrupts need to be cleared. - * - * @return None - */ -static inline __attribute__((always_inline)) void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask) -{ - USB_SERIAL_JTAG.int_clr.val = mask; -} - -/** - * @brief Get status of enabled interrupt. - * - * @return interrupt enable value - */ -static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void) -{ - return USB_SERIAL_JTAG.int_ena.val; -} - -/** - * @brief Read the bytes from the USB_SERIAL_JTAG rxfifo. - * - * @param buf The data buffer. - * @param rd_len The data length needs to be read. - * - * @return amount of bytes read - */ -static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) -{ - int i; - for (i = 0; i < (int)rd_len; i++) { - if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte); - } - return i; -} - -/** - * @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there - * is room in the buffer. - * - * @param buf The data buffer. - * @param wr_len The data length needs to be writen. - * - * @return Amount of bytes actually written. May be less than wr_len. - */ -static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len) -{ - int i; - for (i = 0; i < (int)wr_len; i++) { - if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]); - } - return i; -} - -/** - * @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available. - * - * @return 0 if no data available, 1 if data available - */ -static inline int usb_serial_jtag_ll_rxfifo_data_available(void) -{ - return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail; -} - -/** - * @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room. - * - * @return 0 if no data available, 1 if data available - */ -static inline int usb_serial_jtag_ll_txfifo_writable(void) -{ - return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free; -} - -/** - * @brief Flushes the TX buffer, that is, make it available for the - * host to pick up. - * - * @return na - */ -static inline void usb_serial_jtag_ll_txfifo_flush(void) -{ - USB_SERIAL_JTAG.ep1_conf.wr_done=1; -} - - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/rev1/hal/gpio_ll.h b/components/hal/esp32h4/include/rev1/hal/gpio_ll.h deleted file mode 100644 index 37c0bc928c..0000000000 --- a/components/hal/esp32h4/include/rev1/hal/gpio_ll.h +++ /dev/null @@ -1,697 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - -// The LL layer for ESP32-H4 GPIO register operations - -#pragma once - -#include -#include -#include "soc/soc.h" -#include "soc/gpio_periph.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/gpio_struct.h" -#include "soc/usb_serial_jtag_reg.h" -#include "hal/gpio_types.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Get GPIO hardware instance with giving gpio num -#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) - -#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) -#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) -/** - * @brief Enable pull-up on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); -} - -/** - * @brief Disable pull-up on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value - // USB DP pin is default to PU enabled - if (gpio_num == USB_DP_GPIO_NUM) { - SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); - CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); - } - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); -} - -/** - * @brief Enable pull-down on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); -} - -/** - * @brief Disable pull-down on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); -} - -/** - * @brief GPIO set interrupt trigger type - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); - * @param intr_type Interrupt type, select from gpio_int_type_t - */ -static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) -{ - hw->pin[gpio_num].pin_int_type = intr_type; -} - -/** - * @brief Get GPIO interrupt status - * - * @param hw Peripheral GPIO hardware instance address. - * @param core_id interrupt core id - * @param status interrupt status - */ -__attribute__((always_inline)) -static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) -{ - *status = hw->pcpu_int.procpu_int; -} - -/** - * @brief Get GPIO interrupt status high - * - * @param hw Peripheral GPIO hardware instance address. - * @param core_id interrupt core id - * @param status interrupt status high - */ -__attribute__((always_inline)) -static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) -{ - *status = hw->pcpu_int1.procpu_int1; -} - -/** - * @brief Clear GPIO interrupt status - * - * @param hw Peripheral GPIO hardware instance address. - * @param mask interrupt status clear mask - */ -__attribute__((always_inline)) -static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) -{ - hw->status_w1tc.status_w1tc = mask; -} - -/** - * @brief Clear GPIO interrupt status high - * - * @param hw Peripheral GPIO hardware instance address. - * @param mask interrupt status high clear mask - */ -__attribute__((always_inline)) -static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) -{ - hw->status1_w1tc.status1_w1tc = mask; -} - -/** - * @brief Enable GPIO module interrupt signal - * - * @param hw Peripheral GPIO hardware instance address. - * @param core_id Interrupt enabled CPU to corresponding ID - * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); - */ -__attribute__((always_inline)) -static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num) -{ - HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); - GPIO.pin[gpio_num].pin_int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr -} - -/** - * @brief Disable GPIO module interrupt signal - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); - */ -__attribute__((always_inline)) -static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_int_ena = 0; //disable GPIO intr -} - -/** - * @brief Disable input mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable input mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO pin filter - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number of the pad. - */ -static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_FILTER_EN(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pin filter - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number of the pad. - */ -static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_FILTER_DIS(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable output mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num < 32) { - hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); - } else { - hw->enable1_w1tc.enable1_w1tc = (0x1 << (gpio_num - 32)); - } - // Ensure no other output signal is routed via GPIO matrix to this pin - REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), - SIG_GPIO_OUT_IDX); -} - -/** - * @brief Enable output mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num < 32) { - hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); - } else { - hw->enable1_w1ts.enable1_w1ts = (0x1 << (gpio_num - 32)); - } -} - -/** - * @brief Disable open-drain mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_pad_driver = 0; -} - -/** - * @brief Enable open-drain mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_pad_driver = 1; -} - -/** - * @brief Select a function for the pin in the IOMUX - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - * @param func Function to assign to the pin - */ -static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) -{ - // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function - if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { - CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); - } - PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); -} - -/** - * @brief GPIO set output level - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); - * @param level Output level. 0: low ; 1: high - */ -__attribute__((always_inline)) -static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level) -{ - if (level) { - if (gpio_num < 32) { - hw->out_w1ts.out_w1ts = (1 << gpio_num); - } else { - hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32)); - } - } else { - if (gpio_num < 32) { - hw->out_w1tc.out_w1tc = (1 << gpio_num); - } else { - hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32)); - } - } -} - -/** - * @brief GPIO get input level - * - * @warning If the pad is not configured for input (or input and output) the returned value is always 0. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); - * - * @return - * - 0 the GPIO input level is 0 - * - 1 the GPIO input level is 1 - */ -static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num < 32) { - return (hw->in.in_data_next >> gpio_num) & 0x1; - } else { - return (hw->in1.in1_data_next >> (gpio_num - 32)) & 0x1; - } -} - -/** - * @brief Enable GPIO wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. - */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_wakeup_enable = 0x1; -} - -/** - * @brief Disable GPIO wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_wakeup_enable = 0; -} - -/** - * @brief Set GPIO pad drive capability - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - * @param strength Drive capability of the pad - */ -static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) -{ - SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); -} - -/** - * @brief Get GPIO pad drive capability - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - * @param strength Pointer to accept drive capability of the pad - */ -static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) -{ - *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); -} - -/** - * @brief Enable all digital gpio pad hold function during Deep-sleep. - * - * @param hw Peripheral GPIO hardware instance address. - */ -static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); -} - -/** - * @brief Disable all digital gpio pad hold function during Deep-sleep. - * - * @param hw Peripheral GPIO hardware instance address. - */ -static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) -{ - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); -} - -/** - * @brief Get deep sleep hold status - * - * @param hw Peripheral GPIO hardware instance address. - * - * @return - * - true deep sleep hold is enabled - * - false deep sleep hold is disabled - */ -__attribute__((always_inline)) -static inline bool gpio_ll_deep_sleep_hold_is_en(gpio_dev_t *hw) -{ - return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); -} - -/** - * @brief Enable gpio pad hold function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - */ -static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num <= GPIO_NUM_5) { - REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); - } else if (gpio_num <= GPIO_NUM_31) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); - } else { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); - } -} - -/** - * @brief Disable gpio pad hold function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - */ -static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num <= GPIO_NUM_5) { - REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); - } else if (gpio_num <= GPIO_NUM_31) { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); - } -} - -/** - * @brief Get digital gpio pad hold status. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - * - * @note caller must ensure that gpio_num is a digital io pad - * - * @return - * - true digital gpio pad is held - * - false digital gpio pad is unheld - */ -__attribute__((always_inline)) -static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) -{ - return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); -} - -/** - * @brief Set pad input to a peripheral signal through the IOMUX. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number of the pad. - * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. - */ -__attribute__((always_inline)) -static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) -{ - hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; - PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); -} - -/** - * @brief Select a function for the pin in the IOMUX - * - * @param pin_name Pin name to configure - * @param func Function to assign to the pin - */ -static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) -{ - // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function - if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { - CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); - } - PIN_FUNC_SELECT(pin_name, func); -} - -/** - * @brief Set peripheral output to an GPIO pad through the IOMUX. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num gpio_num GPIO number of the pad. - * @param func The function number of the peripheral pin to output pin. - * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. - * @param oen_inv True if the output enable needs to be inverted, otherwise False. - */ -static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) -{ - hw->func_out_sel_cfg[gpio_num].func_oen_sel = 0; - hw->func_out_sel_cfg[gpio_num].func_oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); -} - -/** - * @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads. - * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. - */ -static inline void gpio_ll_force_hold_all(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); -} - -/** - * @brief Force unhold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads. - * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. - */ -static inline void gpio_ll_force_unhold_all(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); -} - -/** - * @brief Enable GPIO pin used for wakeup from sleep. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pin used for wakeup from sleep. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pull-up in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO pull-up in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO pull-down in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pull-down in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO input in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO input in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO output in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO output in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO deep-sleep wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. - */ -static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) -{ - HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); - - REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); - REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); - SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); - uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG); - reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3))); - reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3)); - REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg); -} - -/** - * @brief Disable GPIO deep-sleep wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); - - CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); - CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3); -} - -/** - * @brief Get the status of whether an IO is used for deep-sleep wake-up. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - * @return True if the pin is enabled to wake up from deep-sleep - */ -static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num) -{ - HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); - - return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/include/rev2/hal/gpio_ll.h b/components/hal/esp32h4/include/rev2/hal/gpio_ll.h deleted file mode 100644 index 7051c50d95..0000000000 --- a/components/hal/esp32h4/include/rev2/hal/gpio_ll.h +++ /dev/null @@ -1,627 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/******************************************************************************* - * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in hal/include/hal/readme.md - ******************************************************************************/ - -// The LL layer for ESP32-H4 GPIO register operations - -#pragma once - -#include -#include -#include "soc/soc.h" -#include "soc/gpio_periph.h" -#include "soc/rtc_cntl_reg.h" -#include "soc/gpio_struct.h" -#include "soc/usb_serial_jtag_reg.h" -#include "hal/gpio_types.h" -#include "hal/assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Get GPIO hardware instance with giving gpio num -#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) - -#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) -#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) -/** - * @brief Enable pull-up on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); -} - -/** - * @brief Disable pull-up on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value - // USB DP pin is default to PU enabled - if (gpio_num == USB_DP_GPIO_NUM) { - SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); - CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); - } - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); -} - -/** - * @brief Enable pull-down on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); -} - -/** - * @brief Disable pull-down on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); -} - -/** - * @brief GPIO set interrupt trigger type - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16); - * @param intr_type Interrupt type, select from gpio_int_type_t - */ -static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) -{ - hw->pin[gpio_num].pin_int_type = intr_type; -} - -/** - * @brief Get GPIO interrupt status - * - * @param hw Peripheral GPIO hardware instance address. - * @param core_id interrupt core id - * @param status interrupt status - */ -__attribute__((always_inline)) -static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) -{ - *status = hw->pcpu_int.procpu_int; -} - -/** - * @brief Get GPIO interrupt status high - * - * @param hw Peripheral GPIO hardware instance address. - * @param core_id interrupt core id - * @param status interrupt status high - */ -__attribute__((always_inline)) -static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) -{ - *status = 0; // Less than 32 GPIOs in ESP32-H4Beta2 -} - -/** - * @brief Clear GPIO interrupt status - * - * @param hw Peripheral GPIO hardware instance address. - * @param mask interrupt status clear mask - */ -__attribute__((always_inline)) -static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) -{ - hw->status_w1tc.status_w1tc = mask; -} - -/** - * @brief Clear GPIO interrupt status high - * - * @param hw Peripheral GPIO hardware instance address. - * @param mask interrupt status high clear mask - */ -__attribute__((always_inline)) -static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) -{ - // Less than 32 GPIOs in ESP32-H4Beta2. Do nothing. -} - -/** - * @brief Enable GPIO module interrupt signal - * - * @param hw Peripheral GPIO hardware instance address. - * @param core_id Interrupt enabled CPU to corresponding ID - * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); - */ -__attribute__((always_inline)) -static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num) -{ - HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); - GPIO.pin[gpio_num].pin_int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr -} - -/** - * @brief Disable GPIO module interrupt signal - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); - */ -__attribute__((always_inline)) -static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_int_ena = 0; //disable GPIO intr -} - -/** - * @brief Disable input mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable input mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO pin filter - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number of the pad. - */ -static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_FILTER_EN(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pin filter - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number of the pad. - */ -static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_FILTER_DIS(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable output mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); - // Ensure no other output signal is routed via GPIO matrix to this pin - REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), - SIG_GPIO_OUT_IDX); -} - -/** - * @brief Enable output mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); -} - -/** - * @brief Disable open-drain mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_pad_driver = 0; -} - -/** - * @brief Enable open-drain mode on GPIO. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_pad_driver = 1; -} - -/** - * @brief GPIO set output level - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16); - * @param level Output level. 0: low ; 1: high - */ -__attribute__((always_inline)) -static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level) -{ - if (level) { - hw->out_w1ts.out_w1ts = (1 << gpio_num); - } else { - hw->out_w1tc.out_w1tc = (1 << gpio_num); - } -} - -/** - * @brief GPIO get input level - * - * @warning If the pad is not configured for input (or input and output) the returned value is always 0. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16); - * - * @return - * - 0 the GPIO input level is 0 - * - 1 the GPIO input level is 1 - */ -static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num) -{ - return (hw->in.in_data_next >> gpio_num) & 0x1; -} - -/** - * @brief Enable GPIO wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. - */ -static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_wakeup_enable = 0x1; -} - -/** - * @brief Disable GPIO wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - hw->pin[gpio_num].pin_wakeup_enable = 0; -} - -/** - * @brief Set GPIO pad drive capability - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - * @param strength Drive capability of the pad - */ -static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) -{ - SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); -} - -/** - * @brief Get GPIO pad drive capability - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - * @param strength Pointer to accept drive capability of the pad - */ -static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) -{ - *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); -} - -/** - * @brief Enable all digital gpio pad hold function during Deep-sleep. - * - * @param hw Peripheral GPIO hardware instance address. - */ -static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); -} - -/** - * @brief Disable all digital gpio pad hold function during Deep-sleep. - * - * @param hw Peripheral GPIO hardware instance address. - */ -static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) -{ - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); -} - -/** - * @brief Enable gpio pad hold function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - */ -static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) { - REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); - } else { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); - } -} - -/** - * @brief Disable gpio pad hold function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number, only support output GPIOs - */ -static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - if (gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) { - REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]); - } -} - -/** - * @brief Set pad input to a peripheral signal through the IOMUX. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number of the pad. - * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``. - */ -__attribute__((always_inline)) -static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) -{ - hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; - PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); -} - -/** - * @brief Select a function for the pin in the IOMUX - * - * @param pin_name Pin name to configure - * @param func Function to assign to the pin - */ -static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) -{ - // Disable USB Serial JTAG if pin 24 or pin 25 needs to select an IOMUX function - if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) { - CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); - } - PIN_FUNC_SELECT(pin_name, func); -} - -/** - * @brief Set peripheral output to an GPIO pad through the IOMUX. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num gpio_num GPIO number of the pad. - * @param func The function number of the peripheral pin to output pin. - * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``. - * @param oen_inv True if the output enable needs to be inverted, otherwise False. - */ -static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) -{ - hw->func_out_sel_cfg[gpio_num].func_oen_sel = 0; - hw->func_out_sel_cfg[gpio_num].func_oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); -} - -/** - * @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads. - * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. - */ -static inline void gpio_ll_force_hold_all(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); -} - -/** - * @brief Force unhold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads. - * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. - */ -static inline void gpio_ll_force_unhold_all(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); - SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M); -} - -/** - * @brief Enable GPIO pin used for wakeup from sleep. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pin used for wakeup from sleep. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pull-up in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO pull-up in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO pull-down in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO pull-down in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO input in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO input in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Disable GPIO output in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO output in sleep mode. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) -{ - PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); -} - -/** - * @brief Enable GPIO deep-sleep wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. - */ -static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) -{ - HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) && - "only gpio7~12 support deep sleep wake-up function"); - - REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); - REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); - SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - (gpio_num - 7))); - uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG); - reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - (gpio_num - 7) * 3))); - reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - (gpio_num - 7) * 3)); - REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg); -} - -/** - * @brief Disable GPIO deep-sleep wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ - HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) && - "only gpio7~12 support deep sleep wake-up function"); - - CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - (gpio_num - 7))); - CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - (gpio_num - 7) * 3); -} - -/** - * @brief Get the status of whether an IO is used for deep-sleep wake-up. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - * @return True if the pin is enabled to wake up from deep-sleep - */ -static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num) -{ - HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) && - "only gpio7~12 support deep sleep wake-up function"); - - return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - (gpio_num - 7))); -} - -#ifdef __cplusplus -} -#endif diff --git a/components/hal/esp32h4/rtc_cntl_hal.c b/components/hal/esp32h4/rtc_cntl_hal.c deleted file mode 100644 index 7ee75a484d..0000000000 --- a/components/hal/esp32h4/rtc_cntl_hal.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// The HAL layer for RTC CNTL (common part) - -#include "soc/soc_caps.h" -#include "soc/lldesc.h" -#include "hal/rtc_hal.h" -#include "hal/assert.h" -#include "esp_attr.h" - -#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ - -typedef struct rtc_cntl_link_buf_conf { - uint32_t cfg[4]; /* 4 word for dma link buffer configuration */ -} rtc_cntl_link_buf_conf_t; - -void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next) -{ - HAL_ASSERT(elem != NULL); - HAL_ASSERT(buff != NULL); - HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN); - - lldesc_t *plink = (lldesc_t *)elem; - - plink->eof = next ? 0 : 1; - plink->owner = 1; - plink->size = size >> 4; /* in unit of 16 bytes */ - plink->length = size >> 4; - plink->buf = buff; - plink->offset = 0; - plink->sosf = 0; - STAILQ_NEXT(plink, qe) = next; - return (void *)plink; -} - -#if SOC_PM_SUPPORT_CPU_PD -void rtc_cntl_hal_enable_cpu_retention(void *addr) -{ - if (addr) { - lldesc_t *plink = (lldesc_t *)addr; - - /* dma link buffer configure */ - rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf; - pbuf->cfg[0] = 0; - pbuf->cfg[1] = 0; - pbuf->cfg[2] = 0; - pbuf->cfg[3] = (uint32_t)-1; - - rtc_cntl_ll_enable_cpu_retention((uint32_t)addr); - } -} - -void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr) -{ - rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr; - - if (addr) { - if (retent->cpu_pd_mem) { - rtc_cntl_ll_disable_cpu_retention(); - } - } -} - -#endif // SOC_PM_SUPPORT_CPU_PD diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index 53b501889c..16dfa20d19 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -144,7 +144,7 @@ typedef struct { }; } adc_digi_output_data_t; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 /** * @brief ADC digital controller (DMA mode) output data format. * Used to analyze the acquired ADC (DMA) data. diff --git a/components/hal/include/hal/adc_types_private.h b/components/hal/include/hal/adc_types_private.h index aa65371465..9a9b0d6b26 100644 --- a/components/hal/include/hal/adc_types_private.h +++ b/components/hal/include/hal/adc_types_private.h @@ -70,7 +70,7 @@ typedef enum { * MONITOR_LOW: If ADC_OUT < threshold, Generates monitor interrupt. */ typedef enum { -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 ADC_DIGI_MONITOR_DIS = 0, /*! threshold, Generates monitor interrupt. */ diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index 893526539f..c85f40d373 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -242,85 +242,6 @@ typedef enum { GPIO_NUM_MAX, /** @endcond */ } gpio_num_t; -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -typedef enum { - GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ - GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ - GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ - GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ - GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ - GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ - GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ - GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ - GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ - GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ - GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ - GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ - GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ - GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ - GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ - GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ - GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ - GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ - GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ - GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ - GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ - GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ - GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ - GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ - GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ - GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ - GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ - GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ - GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ - GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ - GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ - GPIO_NUM_31 = 31, /*!< GPIO31, input and output */ - GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ - GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ - GPIO_NUM_34 = 34, /*!< GPIO34, input and output */ - GPIO_NUM_35 = 35, /*!< GPIO35, input and output */ - GPIO_NUM_36 = 36, /*!< GPIO36, input and output */ - GPIO_NUM_37 = 37, /*!< GPIO37, input and output */ - GPIO_NUM_38 = 38, /*!< GPIO38, input and output */ - GPIO_NUM_39 = 39, /*!< GPIO39, input and output */ - GPIO_NUM_40 = 40, /*!< GPIO40, input and output */ - GPIO_NUM_MAX, -/** @endcond */ -} gpio_num_t; -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -typedef enum { - GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ - GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ - GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ - GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ - GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ - GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ - GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ - GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ - GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ - GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ - GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ - GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ - GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ - GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ - GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ - GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ - GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ - GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ - GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ - GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ - GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ - GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ - GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ - GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ - GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ - GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ - GPIO_NUM_MAX, -/** @endcond */ -} gpio_num_t; #elif CONFIG_IDF_TARGET_ESP32C2 typedef enum { GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ diff --git a/components/hal/include/hal/sha_types.h b/components/hal/include/hal/sha_types.h index df3387c7c7..c5b47ad4ec 100644 --- a/components/hal/include/hal/sha_types.h +++ b/components/hal/include/hal/sha_types.h @@ -17,8 +17,6 @@ #include "esp32s3/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/sha.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/heap/port/esp32h4/memory_layout.c b/components/heap/port/esp32h4/memory_layout.c deleted file mode 100644 index d0875728c5..0000000000 --- a/components/heap/port/esp32h4/memory_layout.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "esp_attr.h" -#include "sdkconfig.h" -#include "soc/soc.h" -#include "heap_memory_layout.h" -#include "esp_heap_caps.h" - -/** - * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. - * Each type of memory map consists of one or more regions in the address space. - * Each type contains an array of prioritized capabilities. - * Types with later entries are only taken if earlier ones can't fulfill the memory request. - * - * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory. - * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM. - * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM. - * - Most other malloc caps only fit in one region anyway. - * - */ -/* Index of memory in `soc_memory_types[]` */ -enum { - SOC_MEMORY_TYPE_DRAM = 0, - SOC_MEMORY_TYPE_STACK_DRAM = 1, - SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_STACK_DIRAM = 3, - SOC_MEMORY_TYPE_RTCRAM = 4, - SOC_MEMORY_TYPE_NUM, -}; - -const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { - // Type 0: DRAM - [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, - // Type 1: DRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, - // Type 2: DRAM which has an alias on the I-port - [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: DIRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, - // Type 4: RTCRAM - [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, -}; - -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE -#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM -#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM -#else -#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM -#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM -#endif - -const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); - -/** - * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type. - * - * @note Because of requirements in the coalescing code which merges adjacent regions, - * this list should always be sorted from low to high by start address. - * - */ - -/** - * Register the shared buffer area of the last memory block into the heap during heap initialization - */ -#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) - -const soc_memory_region_t soc_memory_regions[] = { - { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory - { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory - { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) -#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory -#endif -}; - -const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); - - -extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; - -/** - * Reserved memory regions. - * These are removed from the soc_memory_regions array when heaps are created. - * - */ - -// Static data region. DRAM used by data+bss and possibly rodata -SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); - -// Target has a big D/IRAM region, the part used by code is reserved -// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address -#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) -SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); - -#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP -/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW - region on H4, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections. -*/ -SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data); -#endif diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c index e10aa48209..b9c6def99e 100644 --- a/components/heap/port/memory_layout_utils.c +++ b/components/heap/port/memory_layout_utils.c @@ -15,8 +15,6 @@ #include "esp32c3/rom/rom_layout.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/rom_layout.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rom_layout.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rom_layout.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/idf_test/include/esp32h4/idf_performance_target.h b/components/idf_test/include/esp32h4/idf_performance_target.h deleted file mode 100644 index 8e3a78e259..0000000000 --- a/components/idf_test/include/esp32h4/idf_performance_target.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 43 - -// SHA256 hardware throughput at 160 MHz, threshold set lower than worst case -#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90 -// esp_sha() time to process 32KB of input data from RAM -#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 560 - -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000 -#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000 -#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PUBLIC_OP 45000 -#define IDF_PERFORMANCE_MAX_RSA_3072KEY_PRIVATE_OP 670000 - -#define IDF_PERFORMANCE_MAX_ECP_P192_POINT_MULTIPLY_OP 9000 -#define IDF_PERFORMANCE_MAX_ECP_P192_POINT_VERIFY_OP 300 -#define IDF_PERFORMANCE_MAX_ECP_P256_POINT_MULTIPLY_OP 14000 -#define IDF_PERFORMANCE_MAX_ECP_P256_POINT_VERIFY_OP 300 - -#define IDF_PERFORMANCE_MAX_ECDSA_P192_VERIFY_OP 32000 -#define IDF_PERFORMANCE_MAX_ECDSA_P256_VERIFY_OP 49000 - -#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 - -// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) -#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 -#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/components/ieee802154/CMakeLists.txt b/components/ieee802154/CMakeLists.txt index 4826838b6e..55a1ec7b09 100644 --- a/components/ieee802154/CMakeLists.txt +++ b/components/ieee802154/CMakeLists.txt @@ -13,18 +13,7 @@ if(CONFIG_IEEE802154_ENABLED) target_link_libraries(${COMPONENT_LIB} INTERFACE $ $ libphy.a libbtbb.a $) else() - if(IDF_TARGET STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - target_link_libraries(${COMPONENT_LIB} INTERFACE - "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}/rev1") - endif() - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - target_link_libraries(${COMPONENT_LIB} INTERFACE - "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}/rev2") - endif() - else() - target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}") - endif() + target_link_directories(${COMPONENT_LIB} INTERFACE "${CMAKE_CURRENT_SOURCE_DIR}/lib/${idf_target}") target_link_libraries(${COMPONENT_LIB} INTERFACE $ lib802154.a libphy.a libbtbb.a $ $) endif() diff --git a/components/mbedtls/port/esp32h4/bignum.c b/components/mbedtls/port/esp32h4/bignum.c deleted file mode 100644 index 4a674ee8b0..0000000000 --- a/components/mbedtls/port/esp32h4/bignum.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Multi-precision integer library - * ESP32 H4 hardware accelerated parts based on mbedTLS implementation - * - * SPDX-FileCopyrightText: The Mbed TLS Contributors - * - * SPDX-License-Identifier: Apache-2.0 - * - * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD - */ -#include -#include -#include "soc/hwcrypto_periph.h" -#include "esp_private/periph_ctrl.h" -#include "mbedtls/bignum.h" -#include "bignum_impl.h" -#include "soc/system_reg.h" -#include "soc/periph_defs.h" -#include "esp_crypto_lock.h" - - -size_t esp_mpi_hardware_words(size_t words) -{ - return words; -} - -void esp_mpi_enable_hardware_hw_op( void ) -{ - esp_crypto_mpi_lock_acquire(); - - /* Enable RSA hardware */ - periph_module_enable(PERIPH_RSA_MODULE); - - REG_CLR_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD); - - while (REG_READ(RSA_QUERY_CLEAN_REG) != 1) { - } - // Note: from enabling RSA clock to here takes about 1.3us - - REG_WRITE(RSA_INTERRUPT_REG, 0); -} - -void esp_mpi_disable_hardware_hw_op( void ) -{ - REG_SET_BIT(SYSTEM_RSA_PD_CTRL_REG, SYSTEM_RSA_MEM_PD); - - /* Disable RSA hardware */ - periph_module_disable(PERIPH_RSA_MODULE); - - esp_crypto_mpi_lock_release(); -} - -void esp_mpi_interrupt_enable( bool enable ) -{ - REG_WRITE(RSA_INTERRUPT_REG, enable); -} - -void esp_mpi_interrupt_clear( void ) -{ - REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); -} - -/* Copy mbedTLS MPI bignum 'mpi' to hardware memory block at 'mem_base'. - - If num_words is higher than the number of words in the bignum then - these additional words will be zeroed in the memory buffer. -*/ -static inline void mpi_to_mem_block(uint32_t mem_base, const mbedtls_mpi *mpi, size_t num_words) -{ - uint32_t *pbase = (uint32_t *)mem_base; - uint32_t copy_words = MIN(num_words, mpi->MBEDTLS_PRIVATE(n)); - - /* Copy MPI data to memory block registers */ - for (int i = 0; i < copy_words; i++) { - pbase[i] = mpi->MBEDTLS_PRIVATE(p)[i]; - } - - /* Zero any remaining memory block data */ - for (int i = copy_words; i < num_words; i++) { - pbase[i] = 0; - } -} - -/* Read mbedTLS MPI bignum back from hardware memory block. - - Reads num_words words from block. -*/ -static inline void mem_block_to_mpi(mbedtls_mpi *x, uint32_t mem_base, int num_words) -{ - - /* Copy data from memory block registers */ - const size_t REG_WIDTH = sizeof(uint32_t); - for (size_t i = 0; i < num_words; i++) { - x->MBEDTLS_PRIVATE(p)[i] = REG_READ(mem_base + (i * REG_WIDTH)); - } - /* Zero any remaining limbs in the bignum, if the buffer is bigger - than num_words */ - for (size_t i = num_words; i < x->MBEDTLS_PRIVATE(n); i++) { - x->MBEDTLS_PRIVATE(p)[i] = 0; - } -} - - - -/* Begin an RSA operation. op_reg specifies which 'START' register - to write to. -*/ -static inline void start_op(uint32_t op_reg) -{ - /* Clear interrupt status */ - REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); - - /* Note: above REG_WRITE includes a memw, so we know any writes - to the memory blocks are also complete. */ - - REG_WRITE(op_reg, 1); -} - -/* Wait for an RSA operation to complete. -*/ -static inline void wait_op_complete(void) -{ - while (REG_READ(RSA_QUERY_INTERRUPT_REG) != 1) - { } - - /* clear the interrupt */ - REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); -} - - -/* Read result from last MPI operation */ -void esp_mpi_read_result_hw_op(mbedtls_mpi *Z, size_t z_words) -{ - wait_op_complete(); - mem_block_to_mpi(Z, RSA_MEM_Z_BLOCK_BASE, z_words); -} - - -/* Z = (X * Y) mod M - - Not an mbedTLS function -*/ -void esp_mpi_mul_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words) -{ - REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); - - /* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); - mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); - mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); - REG_WRITE(RSA_M_DASH_REG, Mprime); - - start_op(RSA_MOD_MULT_START_REG); -} - -/* Z = (X ^ Y) mod M -*/ -void esp_mpi_exp_mpi_mod_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, const mbedtls_mpi *Rinv, mbedtls_mpi_uint Mprime, size_t num_words) -{ - size_t y_bits = mbedtls_mpi_bitlen(Y); - - REG_WRITE(RSA_LENGTH_REG, (num_words - 1)); - - /* Load M, X, Rinv, Mprime (Mprime is mod 2^32) */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); - mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); - mpi_to_mem_block(RSA_MEM_RB_BLOCK_BASE, Rinv, num_words); - REG_WRITE(RSA_M_DASH_REG, Mprime); - - /* Enable acceleration options */ - REG_WRITE(RSA_CONSTANT_TIME_REG, 0); - REG_WRITE(RSA_SEARCH_ENABLE_REG, 1); - REG_WRITE(RSA_SEARCH_POS_REG, y_bits - 1); - - /* Execute first stage montgomery multiplication */ - start_op(RSA_MODEXP_START_REG); - - REG_WRITE(RSA_SEARCH_ENABLE_REG, 0); -} - - -/* Z = X * Y */ -void esp_mpi_mul_mpi_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words) -{ - /* Copy X (right-extended) & Y (left-extended) to memory block */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Z_BLOCK_BASE + num_words * 4, Y, num_words); - /* NB: as Y is left-extended, we don't zero the bottom words_mult words of Y block. - This is OK for now because zeroing is done by hardware when we do esp_mpi_acquire_hardware(). - */ - REG_WRITE(RSA_LENGTH_REG, (num_words * 2 - 1)); - start_op(RSA_MULT_START_REG); -} - - - -/** - * @brief Special-case of (X * Y), where we use hardware montgomery mod - multiplication to calculate result where either A or B are >2048 bits so - can't use the standard multiplication method. - * - */ -void esp_mpi_mult_mpi_failover_mod_mult_hw_op(const mbedtls_mpi *X, const mbedtls_mpi *Y, size_t num_words) -{ - /* M = 2^num_words - 1, so block is entirely FF */ - for (int i = 0; i < num_words; i++) { - REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); - } - - /* Mprime = 1 */ - REG_WRITE(RSA_M_DASH_REG, 1); - REG_WRITE(RSA_LENGTH_REG, num_words - 1); - - /* Load X & Y */ - mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); - mpi_to_mem_block(RSA_MEM_Y_BLOCK_BASE, Y, num_words); - - /* Rinv = 1, write first word */ - REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); - - /* Zero out rest of the Rinv words */ - for (int i = 1; i < num_words; i++) { - REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); - } - - start_op(RSA_MOD_MULT_START_REG); -} diff --git a/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c b/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c index 320775d90e..cbe30e1cf7 100644 --- a/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c +++ b/components/mbedtls/port/esp_ds/esp_rsa_sign_alt.c @@ -12,8 +12,6 @@ #include "esp32s2/rom/digital_signature.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/digital_signature.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/digital_signature.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/digital_signature.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/mbedtls/port/sha/dma/sha.c b/components/mbedtls/port/sha/dma/sha.c index 59ad40e887..35e76be8ae 100644 --- a/components/mbedtls/port/sha/dma/sha.c +++ b/components/mbedtls/port/sha/dma/sha.c @@ -54,8 +54,6 @@ #include "esp32s3/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32s3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" #endif diff --git a/components/newlib/newlib_init.c b/components/newlib/newlib_init.c index 9b5bf18474..ffad04c20b 100644 --- a/components/newlib/newlib_init.c +++ b/components/newlib/newlib_init.c @@ -29,8 +29,6 @@ #include "esp32s3/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/libc_stubs.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32C6 @@ -113,7 +111,7 @@ static struct syscall_stub_table s_stub_table = { ._printf_float = NULL, ._scanf_float = NULL, #endif -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 \ +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 \ || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 /* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM assertion failures (as function names & source file names will be similar) @@ -137,7 +135,7 @@ void esp_newlib_init(void) syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table; #elif CONFIG_IDF_TARGET_ESP32S2 syscall_table_ptr_pro = &s_stub_table; -#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 \ +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 \ || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 syscall_table_ptr = &s_stub_table; #endif diff --git a/components/newlib/port/esp_time_impl.c b/components/newlib/port/esp_time_impl.c index 3a068ce283..79fc8b8d2a 100644 --- a/components/newlib/port/esp_time_impl.c +++ b/components/newlib/port/esp_time_impl.c @@ -33,9 +33,6 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/rtc.h" -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" #include "esp32c2/rtc.h" diff --git a/components/newlib/test/test_newlib.c b/components/newlib/test/test_newlib.c index 6c1160ea16..d6d9ddbf90 100644 --- a/components/newlib/test/test_newlib.c +++ b/components/newlib/test/test_newlib.c @@ -139,7 +139,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]") TEST_ASSERT_FALSE(fn_in_rom(vfprintf)); #endif // CONFIG_NEWLIB_NANO_FORMAT || ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT -#if (CONFIG_NEWLIB_NANO_FORMAT && (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4)) || ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT +#if (CONFIG_NEWLIB_NANO_FORMAT && (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2)) || ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT TEST_ASSERT(fn_in_rom(sscanf)); #else TEST_ASSERT_FALSE(fn_in_rom(sscanf)); @@ -148,7 +148,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]") #if defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_SPIRAM) TEST_ASSERT(fn_in_rom(atoi)); TEST_ASSERT(fn_in_rom(strtol)); -#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H4)\ +#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) \ || defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C6) /* S3 and C3 always use these from ROM */ TEST_ASSERT(fn_in_rom(atoi)); diff --git a/components/newlib/test/test_time.c b/components/newlib/test/test_time.c index e4f8f5879f..6ba8a7998a 100644 --- a/components/newlib/test/test_time.c +++ b/components/newlib/test/test_time.c @@ -35,8 +35,6 @@ #include "esp32s3/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/openthread/port/esp_openthread_radio.c b/components/openthread/port/esp_openthread_radio.c index 1d376ec48d..5dd4161954 100644 --- a/components/openthread/port/esp_openthread_radio.c +++ b/components/openthread/port/esp_openthread_radio.c @@ -298,9 +298,6 @@ otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) aFrame->mPsdu[-1] = aFrame->mLength; // lenth locates one byte before the psdu (esp_openthread_radio_tx_psdu); -// TODO: remove this macro check when esp32h4 unsupported. -#if !CONFIG_IDF_TARGET_ESP32H4 - // esp32h4 do not support tx security if (otMacFrameIsSecurityEnabled(aFrame) && !aFrame->mInfo.mTxInfo.mIsSecurityProcessed) { otMacFrameSetFrameCounter(aFrame, s_mac_frame_counter++); if (otMacFrameIsKeyIdMode1(aFrame)) { @@ -314,12 +311,10 @@ otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame) esp_ieee802154_set_transmit_security(&aFrame->mPsdu[-1], s_security_key, s_security_addr); } - // esp32h4 do not support transmit at if (aFrame->mInfo.mTxInfo.mTxDelay != 0) { esp_ieee802154_transmit_at(&aFrame->mPsdu[-1], aFrame->mInfo.mTxInfo.mCsmaCaEnabled, (aFrame->mInfo.mTxInfo.mTxDelayBaseTime + aFrame->mInfo.mTxInfo.mTxDelay)); } else -#endif { esp_ieee802154_transmit(&aFrame->mPsdu[-1], aFrame->mInfo.mTxInfo.mCsmaCaEnabled); } @@ -342,22 +337,15 @@ int8_t otPlatRadioGetRssi(otInstance *aInstance) otRadioCaps otPlatRadioGetCaps(otInstance *aInstance) { return (otRadioCaps)(OT_RADIO_CAPS_ENERGY_SCAN | -// TODO: remove this macro check when esp32h4 unsupported. -#if !CONFIG_IDF_TARGET_ESP32H4 OT_RADIO_CAPS_TRANSMIT_SEC | OT_RADIO_CAPS_RECEIVE_TIMING | OT_RADIO_CAPS_TRANSMIT_TIMING | -#endif OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_SLEEP_TO_TX); } -// TODO: remove this macro check when esp32h4 unsupported. -#if !CONFIG_IDF_TARGET_ESP32H4 -// esp32h4 do not support receive at otError otPlatRadioReceiveAt(otInstance *aInstance, uint8_t aChannel, uint32_t aStart, uint32_t aDuration) { esp_ieee802154_receive_at((aStart + aDuration)); return OT_ERROR_NONE; } -#endif bool otPlatRadioGetPromiscuous(otInstance *aInstance) { diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index 9255e70f77..4c4fb9160c 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -13,13 +13,6 @@ set(includes "include" "${target}") if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target}/include") list(APPEND includes "${target}/include") - if(target STREQUAL "esp32h4") - if(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1) - list(APPEND includes "${target}/include/rev1") - elseif(CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2) - list(APPEND includes "${target}/include/rev2") - endif() - endif() endif() if(target STREQUAL "esp32") diff --git a/components/soc/esp32h4/adc_periph.c b/components/soc/esp32h4/adc_periph.c deleted file mode 100644 index 57d916e86b..0000000000 --- a/components/soc/esp32h4/adc_periph.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/adc_periph.h" - -/* Store IO number corresponding to the ADC channel number. */ -const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { - /* ADC1 */ - { - ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM - } -}; diff --git a/components/soc/esp32h4/dedic_gpio_periph.c b/components/soc/esp32h4/dedic_gpio_periph.c deleted file mode 100644 index 711274f893..0000000000 --- a/components/soc/esp32h4/dedic_gpio_periph.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/gpio_sig_map.h" -#include "soc/dedic_gpio_periph.h" - -const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = { - .module = -1, - .irq = -1, - .cores = { - [0] = { - .in_sig_per_channel = { - [0] = CPU_GPIO_IN0_IDX, - [1] = CPU_GPIO_IN1_IDX, - [2] = CPU_GPIO_IN2_IDX, - [3] = CPU_GPIO_IN3_IDX, - [4] = CPU_GPIO_IN4_IDX, - [5] = CPU_GPIO_IN5_IDX, - [6] = CPU_GPIO_IN6_IDX, - [7] = CPU_GPIO_IN7_IDX, - }, - .out_sig_per_channel = { - [0] = CPU_GPIO_OUT0_IDX, - [1] = CPU_GPIO_OUT1_IDX, - [2] = CPU_GPIO_OUT2_IDX, - [3] = CPU_GPIO_OUT3_IDX, - [4] = CPU_GPIO_OUT4_IDX, - [5] = CPU_GPIO_OUT5_IDX, - [6] = CPU_GPIO_OUT6_IDX, - [7] = CPU_GPIO_OUT7_IDX, - } - }, - }, -}; diff --git a/components/soc/esp32h4/gdma_periph.c b/components/soc/esp32h4/gdma_periph.c deleted file mode 100644 index 95f6334112..0000000000 --- a/components/soc/esp32h4/gdma_periph.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/gdma_periph.h" - -const gdma_signal_conn_t gdma_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_GDMA_MODULE, - .pairs = { - [0] = { - .rx_irq_id = ETS_DMA_CH0_INTR_SOURCE, - .tx_irq_id = ETS_DMA_CH0_INTR_SOURCE, - }, - [1] = { - .rx_irq_id = ETS_DMA_CH1_INTR_SOURCE, - .tx_irq_id = ETS_DMA_CH1_INTR_SOURCE, - }, - [2] = { - .rx_irq_id = ETS_DMA_CH2_INTR_SOURCE, - .tx_irq_id = ETS_DMA_CH2_INTR_SOURCE, - } - } - } - } -}; diff --git a/components/soc/esp32h4/gpio_periph.c b/components/soc/esp32h4/gpio_periph.c deleted file mode 100644 index d9bff84970..0000000000 --- a/components/soc/esp32h4/gpio_periph.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/gpio_periph.h" - -const uint32_t GPIO_PIN_MUX_REG[] = { - IO_MUX_GPIO0_REG, - IO_MUX_GPIO1_REG, - IO_MUX_GPIO2_REG, - IO_MUX_GPIO3_REG, - IO_MUX_GPIO4_REG, - IO_MUX_GPIO5_REG, - IO_MUX_GPIO6_REG, - IO_MUX_GPIO7_REG, - IO_MUX_GPIO8_REG, - IO_MUX_GPIO9_REG, - IO_MUX_GPIO10_REG, - IO_MUX_GPIO11_REG, - IO_MUX_GPIO12_REG, - IO_MUX_GPIO13_REG, - IO_MUX_GPIO14_REG, - IO_MUX_GPIO15_REG, - IO_MUX_GPIO16_REG, - IO_MUX_GPIO17_REG, - IO_MUX_GPIO18_REG, - IO_MUX_GPIO19_REG, - IO_MUX_GPIO20_REG, - IO_MUX_GPIO21_REG, - IO_MUX_GPIO22_REG, - IO_MUX_GPIO23_REG, - IO_MUX_GPIO24_REG, - IO_MUX_GPIO25_REG, -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 - IO_MUX_GPIO26_REG, - IO_MUX_GPIO27_REG, - IO_MUX_GPIO28_REG, - IO_MUX_GPIO29_REG, - IO_MUX_GPIO30_REG, - IO_MUX_GPIO31_REG, - IO_MUX_GPIO32_REG, - IO_MUX_GPIO33_REG, - IO_MUX_GPIO34_REG, - IO_MUX_GPIO35_REG, - IO_MUX_GPIO36_REG, - IO_MUX_GPIO37_REG, - IO_MUX_GPIO38_REG, - IO_MUX_GPIO39_REG, - IO_MUX_GPIO40_REG, -#endif -}; - -_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); - -const uint32_t GPIO_HOLD_MASK[] = { -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 - BIT(0), //GPIO0 - BIT(1), //GPIO1 - BIT(2), //GPIO2 - BIT(3), //GPIO3 - BIT(4), //GPIO4 - BIT(5), //GPIO5 - BIT(6), //GPIO6 - BIT(7), //GPIO7 - BIT(8), //GPIO8 - BIT(9), //GPIO9 - BIT(10), //GPIO10 - BIT(11), //GPIO11 - BIT(12), //GPIO12 - BIT(13), //GPIO13 - BIT(14), //GPIO14 - BIT(15), //GPIO15 - BIT(16), //GPIO16 - BIT(17), //GPIO17 - BIT(18), //GPIO18 - BIT(19), //GPIO19 - BIT(20), //GPIO20 - BIT(21), //GPIO21 - BIT(22), //GPIO22 - BIT(23), //GPIO23 - BIT(24), //GPIO24 - BIT(25), //GPIO25 - BIT(26), //GPIO26 - BIT(27), //GPIO27 - BIT(28), //GPIO28 - BIT(29), //GPIO29 - BIT(30), //GPIO30 - BIT(31), //GPIO31 - BIT(0), //GPIO32 - BIT(1), //GPIO33 - BIT(2), //GPIO34 - BIT(3), //GPIO35 - BIT(4), //GPIO36 - BIT(5), //GPIO37 - BIT(6), //GPIO38 - BIT(7), //GPIO39 - BIT(8), //GPIO40 -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 - BIT(0), //GPIO0 - BIT(1), //GPIO1 - BIT(2), //GPIO2 - BIT(3), //GPIO3 - BIT(4), //GPIO4 - BIT(5), //GPIO5 - BIT(6), //GPIO6 - BIT(0), //GPIO7 - BIT(1), //GPIO8 - BIT(2), //GPIO9 - BIT(4), //GPIO10 - BIT(3), //GPIO11 - BIT(5), //GPIO12 - BIT(13), //GPIO13 - BIT(14), //GPIO14 - BIT(15), //GPIO15 - BIT(16), //GPIO16 - BIT(17), //GPIO17 - BIT(18), //GPIO18 - BIT(19), //GPIO19 - BIT(20), //GPIO20 - BIT(21), //GPIO21 - BIT(22), //GPIO22 - BIT(23), //GPIO23 - BIT(24), //GPIO24 - BIT(25), //GPIO25 -#endif -}; - -_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32h4/i2c_bias.h b/components/soc/esp32h4/i2c_bias.h deleted file mode 100644 index a7ea588270..0000000000 --- a/components/soc/esp32h4/i2c_bias.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define I2C_BIAS 0x6a -#define I2C_BIAS_HOSTID 0 - -#define I2C_BIAS_DREG_1P6 0 -#define I2C_BIAS_DREG_1P6_MSB 3 -#define I2C_BIAS_DREG_1P6_LSB 0 - -#define I2C_BIAS_DREG_0P8 0 -#define I2C_BIAS_DREG_0P8_MSB 7 -#define I2C_BIAS_DREG_0P8_LSB 4 - -#define I2C_BIAS_DREG_1P1_PVT 1 -#define I2C_BIAS_DREG_1P1_PVT_MSB 3 -#define I2C_BIAS_DREG_1P1_PVT_LSB 0 - -#define I2C_BIAS_DREG_1P2 1 -#define I2C_BIAS_DREG_1P2_MSB 7 -#define I2C_BIAS_DREG_1P2_LSB 4 - -#define I2C_BIAS_ENT_CPREG 2 -#define I2C_BIAS_ENT_CPREG_MSB 0 -#define I2C_BIAS_ENT_CPREG_LSB 0 - -#define I2C_BIAS_ENT_CGM 2 -#define I2C_BIAS_ENT_CGM_MSB 1 -#define I2C_BIAS_ENT_CGM_LSB 1 - -#define I2C_BIAS_CGM_BIAS 2 -#define I2C_BIAS_CGM_BIAS_MSB 3 -#define I2C_BIAS_CGM_BIAS_LSB 2 - -#define I2C_BIAS_DREF_IGM 2 -#define I2C_BIAS_DREF_IGM_MSB 4 -#define I2C_BIAS_DREF_IGM_LSB 4 - -#define I2C_BIAS_RC_DVREF 2 -#define I2C_BIAS_RC_DVREF_MSB 6 -#define I2C_BIAS_RC_DVREF_LSB 5 - -#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP 2 -#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_MSB 7 -#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_LSB 7 - -#define I2C_BIAS_RC_ENX 3 -#define I2C_BIAS_RC_ENX_MSB 0 -#define I2C_BIAS_RC_ENX_LSB 0 - -#define I2C_BIAS_RC_START 3 -#define I2C_BIAS_RC_START_MSB 1 -#define I2C_BIAS_RC_START_LSB 1 - -#define I2C_BIAS_RC_DCAP_EXT 3 -#define I2C_BIAS_RC_DCAP_EXT_MSB 7 -#define I2C_BIAS_RC_DCAP_EXT_LSB 2 - -#define I2C_BIAS_XPD_RC 4 -#define I2C_BIAS_XPD_RC_MSB 0 -#define I2C_BIAS_XPD_RC_LSB 0 - -#define I2C_BIAS_ENT_CONSTI 4 -#define I2C_BIAS_ENT_CONSTI_MSB 1 -#define I2C_BIAS_ENT_CONSTI_LSB 1 - -#define I2C_BIAS_XPD_ICX 4 -#define I2C_BIAS_XPD_ICX_MSB 2 -#define I2C_BIAS_XPD_ICX_LSB 2 - -#define I2C_BIAS_RC_RSTB 4 -#define I2C_BIAS_RC_RSTB_MSB 3 -#define I2C_BIAS_RC_RSTB_LSB 3 - -#define I2C_BIAS_RC_DIV 4 -#define I2C_BIAS_RC_DIV_MSB 7 -#define I2C_BIAS_RC_DIV_LSB 4 - -#define I2C_BIAS_RC_CAP 5 -#define I2C_BIAS_RC_CAP_MSB 5 -#define I2C_BIAS_RC_CAP_LSB 0 - -#define I2C_BIAS_RC_UD 5 -#define I2C_BIAS_RC_UD_MSB 6 -#define I2C_BIAS_RC_UD_LSB 6 - -#define I2C_BIAS_RC_LOCKB 5 -#define I2C_BIAS_RC_LOCKB_MSB 7 -#define I2C_BIAS_RC_LOCKB_LSB 7 - -#define I2C_BIAS_RC_CHG_COUNT 6 -#define I2C_BIAS_RC_CHG_COUNT_MSB 4 -#define I2C_BIAS_RC_CHG_COUNT_LSB 0 - -#define I2C_BIAS_XPD_CPREG 7 -#define I2C_BIAS_XPD_CPREG_MSB 0 -#define I2C_BIAS_XPD_CPREG_LSB 0 - -#define I2C_BIAS_XPD_CGM 7 -#define I2C_BIAS_XPD_CGM_MSB 1 -#define I2C_BIAS_XPD_CGM_LSB 1 - -#define I2C_BIAS_DTEST 7 -#define I2C_BIAS_DTEST_MSB 3 -#define I2C_BIAS_DTEST_LSB 2 - -#define I2C_BIAS_DRES12K 7 -#define I2C_BIAS_DRES12K_MSB 7 -#define I2C_BIAS_DRES12K_LSB 4 diff --git a/components/soc/esp32h4/i2c_periph.c b/components/soc/esp32h4/i2c_periph.c deleted file mode 100644 index cb8e7fa246..0000000000 --- a/components/soc/esp32h4/i2c_periph.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/i2c_periph.h" -#include "soc/gpio_sig_map.h" - -/* - Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc -*/ -const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { - { - .sda_out_sig = I2CEXT0_SDA_OUT_IDX, - .sda_in_sig = I2CEXT0_SDA_IN_IDX, - .scl_out_sig = I2CEXT0_SCL_OUT_IDX, - .scl_in_sig = I2CEXT0_SCL_IN_IDX, - .irq = ETS_I2C_EXT0_INTR_SOURCE, - .module = PERIPH_I2C0_MODULE, - }, -}; diff --git a/components/soc/esp32h4/i2c_pmu.h b/components/soc/esp32h4/i2c_pmu.h deleted file mode 100644 index de1e7d6aea..0000000000 --- a/components/soc/esp32h4/i2c_pmu.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define I2C_PMU 0x6d -#define I2C_PMU_HOSTID 0 - -#define I2C_PMU_THRES_HIGH_7_0 0 -#define I2C_PMU_THRES_HIGH_7_0_MSB 7 -#define I2C_PMU_THRES_HIGH_7_0_LSB 0 - -#define I2C_PMU_THRES_LOW_7_0 1 -#define I2C_PMU_THRES_LOW_7_0_MSB 7 -#define I2C_PMU_THRES_LOW_7_0_LSB 0 - -#define I2C_PMU_THRES_HIGH_11_8 2 -#define I2C_PMU_THRES_HIGH_11_8_MSB 3 -#define I2C_PMU_THRES_HIGH_11_8_LSB 0 - -#define I2C_PMU_THRES_LOW_11_8 2 -#define I2C_PMU_THRES_LOW_11_8_MSB 7 -#define I2C_PMU_THRES_LOW_11_8_LSB 4 - -#define I2C_PMU_PVT_DELAY_INIT 3 -#define I2C_PMU_PVT_DELAY_INIT_MSB 7 -#define I2C_PMU_PVT_DELAY_INIT_LSB 0 - -#define I2C_PMU_PVT_DELAY_COUNT 4 -#define I2C_PMU_PVT_DELAY_COUNT_MSB 5 -#define I2C_PMU_PVT_DELAY_COUNT_LSB 0 - -#define I2C_PMU_OR_EN_CONT_CAL 4 -#define I2C_PMU_OR_EN_CONT_CAL_MSB 7 -#define I2C_PMU_OR_EN_CONT_CAL_LSB 7 - -#define I2C_PMU_I2C_RTC_DREG 5 -#define I2C_PMU_I2C_RTC_DREG_MSB 4 -#define I2C_PMU_I2C_RTC_DREG_LSB 0 - -#define I2C_PMU_I2C_DIG_DREG 6 -#define I2C_PMU_I2C_DIG_DREG_MSB 4 -#define I2C_PMU_I2C_DIG_DREG_LSB 0 - -#define I2C_PMU_I2C_RTC_DREG_SLP 7 -#define I2C_PMU_I2C_RTC_DREG_SLP_MSB 3 -#define I2C_PMU_I2C_RTC_DREG_SLP_LSB 0 - -#define I2C_PMU_I2C_DIG_DREG_SLP 7 -#define I2C_PMU_I2C_DIG_DREG_SLP_MSB 7 -#define I2C_PMU_I2C_DIG_DREG_SLP_LSB 4 - -#define I2C_PMU_EN_I2C_RTC_DREG 10 -#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0 -#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0 - -#define I2C_PMU_EN_I2C_DIG_DREG 10 -#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1 -#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1 - -#define I2C_PMU_EN_I2C_RTC_DREG_SLP 10 -#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2 -#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2 - -#define I2C_PMU_EN_I2C_DIG_DREG_SLP 10 -#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3 -#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3 - -#define I2C_PMU_ENX_RTC_DREG 11 -#define I2C_PMU_ENX_RTC_DREG_MSB 0 -#define I2C_PMU_ENX_RTC_DREG_LSB 0 - -#define I2C_PMU_ENX_DIG_DREG 11 -#define I2C_PMU_ENX_DIG_DREG_MSB 1 -#define I2C_PMU_ENX_DIG_DREG_LSB 1 - -#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3 11 -#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_MSB 2 -#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_LSB 2 - -#define I2C_PMU_OR_XPD_RTC_REG 11 -#define I2C_PMU_OR_XPD_RTC_REG_MSB 4 -#define I2C_PMU_OR_XPD_RTC_REG_LSB 4 - -#define I2C_PMU_OR_XPD_DIG_REG 11 -#define I2C_PMU_OR_XPD_DIG_REG_MSB 5 -#define I2C_PMU_OR_XPD_DIG_REG_LSB 5 - -#define I2C_PMU_OR_PD_RTC_REG_SLP 11 -#define I2C_PMU_OR_PD_RTC_REG_SLP_MSB 6 -#define I2C_PMU_OR_PD_RTC_REG_SLP_LSB 6 - -#define I2C_PMU_OR_PD_DIG_REG_SLP 11 -#define I2C_PMU_OR_PD_DIG_REG_SLP_MSB 7 -#define I2C_PMU_OR_PD_DIG_REG_SLP_LSB 7 - -#define I2C_PMU_INT_DREG 12 -#define I2C_PMU_INT_DREG_MSB 4 -#define I2C_PMU_INT_DREG_LSB 0 - -#define I2C_PMU_O_UDF 12 -#define I2C_PMU_O_UDF_MSB 5 -#define I2C_PMU_O_UDF_LSB 5 - -#define I2C_PMU_O_OVF 12 -#define I2C_PMU_O_OVF_MSB 6 -#define I2C_PMU_O_OVF_LSB 6 - -#define I2C_PMU_O_UPDATE 12 -#define I2C_PMU_O_UPDATE_MSB 7 -#define I2C_PMU_O_UPDATE_LSB 7 - -#define I2C_PMU_PVT_COUNT_7_0 13 -#define I2C_PMU_PVT_COUNT_7_0_MSB 7 -#define I2C_PMU_PVT_COUNT_7_0_LSB 0 - -#define I2C_PMU_PVT_COUNT_11_8 14 -#define I2C_PMU_PVT_COUNT_11_8_MSB 3 -#define I2C_PMU_PVT_COUNT_11_8_LSB 0 - -#define I2C_PMU_IC_VGOOD_LVDET 14 -#define I2C_PMU_IC_VGOOD_LVDET_MSB 4 -#define I2C_PMU_IC_VGOOD_LVDET_LSB 4 - -#define I2C_PMU_IC_POWER_GOOD_DCDC 14 -#define I2C_PMU_IC_POWER_GOOD_DCDC_MSB 5 -#define I2C_PMU_IC_POWER_GOOD_DCDC_LSB 5 - -#define I2C_PMU_IC_VGOOD_DIGDET 14 -#define I2C_PMU_IC_VGOOD_DIGDET_MSB 6 -#define I2C_PMU_IC_VGOOD_DIGDET_LSB 6 - -#define I2C_PMU_OR_XPD_DCDC 15 -#define I2C_PMU_OR_XPD_DCDC_MSB 0 -#define I2C_PMU_OR_XPD_DCDC_LSB 0 - -#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC 15 -#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_MSB 1 -#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_LSB 1 - -#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC 15 -#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_MSB 2 -#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_LSB 2 - -#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC 15 -#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_MSB 3 -#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_LSB 3 - -#define I2C_PMU_OR_ENX_REG_DCDC 15 -#define I2C_PMU_OR_ENX_REG_DCDC_MSB 4 -#define I2C_PMU_OR_ENX_REG_DCDC_LSB 4 - -#define I2C_PMU_OR_UNLOCK_DCDC 15 -#define I2C_PMU_OR_UNLOCK_DCDC_MSB 5 -#define I2C_PMU_OR_UNLOCK_DCDC_LSB 5 - -#define I2C_PMU_OR_FORCE_LOCK_DCDC 15 -#define I2C_PMU_OR_FORCE_LOCK_DCDC_MSB 6 -#define I2C_PMU_OR_FORCE_LOCK_DCDC_LSB 6 - -#define I2C_PMU_OR_ENB_SLOW_CLK 15 -#define I2C_PMU_OR_ENB_SLOW_CLK_MSB 7 -#define I2C_PMU_OR_ENB_SLOW_CLK_LSB 7 - -#define I2C_PMU_OC_SCK_DCAP 16 -#define I2C_PMU_OC_SCK_DCAP_MSB 7 -#define I2C_PMU_OC_SCK_DCAP_LSB 0 - -#define I2C_PMU_OC_XPD_LVDET 17 -#define I2C_PMU_OC_XPD_LVDET_MSB 0 -#define I2C_PMU_OC_XPD_LVDET_LSB 0 - -#define I2C_PMU_OC_MODE_LVDET 17 -#define I2C_PMU_OC_MODE_LVDET_MSB 1 -#define I2C_PMU_OC_MODE_LVDET_LSB 1 - -#define I2C_PMU_OR_XPD_TRX 17 -#define I2C_PMU_OR_XPD_TRX_MSB 2 -#define I2C_PMU_OR_XPD_TRX_LSB 2 - -#define I2C_PMU_OR_EN_RESET_CHIP 17 -#define I2C_PMU_OR_EN_RESET_CHIP_MSB 3 -#define I2C_PMU_OR_EN_RESET_CHIP_LSB 3 - -#define I2C_PMU_OC_DREF_LVDET 17 -#define I2C_PMU_OC_DREF_LVDET_MSB 6 -#define I2C_PMU_OC_DREF_LVDET_LSB 4 - -#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE 17 -#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_MSB 7 -#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_LSB 7 - -#define I2C_PMU_DTEST 18 -#define I2C_PMU_DTEST_MSB 1 -#define I2C_PMU_DTEST_LSB 0 - -#define I2C_PMU_ENT_BIAS 18 -#define I2C_PMU_ENT_BIAS_MSB 2 -#define I2C_PMU_ENT_BIAS_LSB 2 - -#define I2C_PMU_ENT_VDD 18 -#define I2C_PMU_ENT_VDD_MSB 5 -#define I2C_PMU_ENT_VDD_LSB 3 - -#define I2C_PMU_EN_DMUX 18 -#define I2C_PMU_EN_DMUX_MSB 6 -#define I2C_PMU_EN_DMUX_LSB 6 - -#define I2C_PMU_WD_DISABLE 18 -#define I2C_PMU_WD_DISABLE_MSB 7 -#define I2C_PMU_WD_DISABLE_LSB 7 - -#define I2C_PMU_DTEST_DCDC 19 -#define I2C_PMU_DTEST_DCDC_MSB 0 -#define I2C_PMU_DTEST_DCDC_LSB 0 - -#define I2C_PMU_TESTEN_DCDC 19 -#define I2C_PMU_TESTEN_DCDC_MSB 1 -#define I2C_PMU_TESTEN_DCDC_LSB 1 - -#define I2C_PMU_ADD_DCDC 19 -#define I2C_PMU_ADD_DCDC_MSB 6 -#define I2C_PMU_ADD_DCDC_LSB 4 - -#define I2C_PMU_OR_POCPENB_DCDC 20 -#define I2C_PMU_OR_POCPENB_DCDC_MSB 0 -#define I2C_PMU_OR_POCPENB_DCDC_LSB 0 - -#define I2C_PMU_OR_SSTIME_DCDC 20 -#define I2C_PMU_OR_SSTIME_DCDC_MSB 1 -#define I2C_PMU_OR_SSTIME_DCDC_LSB 1 - -#define I2C_PMU_OR_CCM_DCDC 20 -#define I2C_PMU_OR_CCM_DCDC_MSB 2 -#define I2C_PMU_OR_CCM_DCDC_LSB 2 - -#define I2C_PMU_OR_VSET_LOW_DCDC 20 -#define I2C_PMU_OR_VSET_LOW_DCDC_MSB 7 -#define I2C_PMU_OR_VSET_LOW_DCDC_LSB 3 - -#define I2C_PMU_OR_FSW_DCDC 21 -#define I2C_PMU_OR_FSW_DCDC_MSB 2 -#define I2C_PMU_OR_FSW_DCDC_LSB 0 - -#define I2C_PMU_OR_DCMLEVEL_DCDC 21 -#define I2C_PMU_OR_DCMLEVEL_DCDC_MSB 4 -#define I2C_PMU_OR_DCMLEVEL_DCDC_LSB 3 - -#define I2C_PMU_OR_DCM2ENB_DCDC 21 -#define I2C_PMU_OR_DCM2ENB_DCDC_MSB 5 -#define I2C_PMU_OR_DCM2ENB_DCDC_LSB 5 - -#define I2C_PMU_OR_RAMP_DCDC 21 -#define I2C_PMU_OR_RAMP_DCDC_MSB 6 -#define I2C_PMU_OR_RAMP_DCDC_LSB 6 - -#define I2C_PMU_OR_RAMPLEVEL_DCDC 21 -#define I2C_PMU_OR_RAMPLEVEL_DCDC_MSB 7 -#define I2C_PMU_OR_RAMPLEVEL_DCDC_LSB 7 - -#define I2C_PMU_OR_VSET_HIGH_DCDC 22 -#define I2C_PMU_OR_VSET_HIGH_DCDC_MSB 4 -#define I2C_PMU_OR_VSET_HIGH_DCDC_LSB 0 - -#define I2C_PMU_OC_DEL_SSEND 22 -#define I2C_PMU_OC_DEL_SSEND_MSB 7 -#define I2C_PMU_OC_DEL_SSEND_LSB 5 - -#define I2C_PMU_OC_XPD_DIGDET 23 -#define I2C_PMU_OC_XPD_DIGDET_MSB 0 -#define I2C_PMU_OC_XPD_DIGDET_LSB 0 - -#define I2C_PMU_OC_MODE_DIGDET 23 -#define I2C_PMU_OC_MODE_DIGDET_MSB 1 -#define I2C_PMU_OC_MODE_DIGDET_LSB 1 - -#define I2C_PMU_OC_DREF_DIGDET 23 -#define I2C_PMU_OC_DREF_DIGDET_MSB 6 -#define I2C_PMU_OC_DREF_DIGDET_LSB 4 diff --git a/components/soc/esp32h4/i2c_ulp.h b/components/soc/esp32h4/i2c_ulp.h deleted file mode 100644 index 5751f01936..0000000000 --- a/components/soc/esp32h4/i2c_ulp.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define I2C_ULP 0x61 -#define I2C_ULP_HOSTID 0 - -#define I2C_ULP_IR_RESETB 0 -#define I2C_ULP_IR_RESETB_MSB 0 -#define I2C_ULP_IR_RESETB_LSB 0 - -#define I2C_ULP_XPD_REG_SLP 0 -#define I2C_ULP_XPD_REG_SLP_MSB 1 -#define I2C_ULP_XPD_REG_SLP_LSB 1 - -#define I2C_ULP_DBIAS_SLP 0 -#define I2C_ULP_DBIAS_SLP_MSB 7 -#define I2C_ULP_DBIAS_SLP_LSB 4 - -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1 -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1 -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1 - -#define I2C_ULP_IR_FORCE_XPD_IPH 1 -#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2 -#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2 - -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1 -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3 -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3 - -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1 -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4 -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4 - -#define I2C_ULP_IR_ZOS_XPD 2 -#define I2C_ULP_IR_ZOS_XPD_MSB 0 -#define I2C_ULP_IR_ZOS_XPD_LSB 0 - -#define I2C_ULP_IR_ZOS_RSTB 2 -#define I2C_ULP_IR_ZOS_RSTB_MSB 1 -#define I2C_ULP_IR_ZOS_RSTB_LSB 1 - -#define I2C_ULP_IR_ZOS_RESTART 2 -#define I2C_ULP_IR_ZOS_RESTART_MSB 2 -#define I2C_ULP_IR_ZOS_RESTART_LSB 2 - -#define I2C_ULP_DTEST 3 -#define I2C_ULP_DTEST_MSB 1 -#define I2C_ULP_DTEST_LSB 0 - -#define I2C_ULP_ENT_BG 3 -#define I2C_ULP_ENT_BG_MSB 2 -#define I2C_ULP_ENT_BG_LSB 2 - -#define I2C_ULP_MODE_LVDET 3 -#define I2C_ULP_MODE_LVDET_MSB 3 -#define I2C_ULP_MODE_LVDET_LSB 3 - -#define I2C_ULP_DREF_LVDET 3 -#define I2C_ULP_DREF_LVDET_MSB 6 -#define I2C_ULP_DREF_LVDET_LSB 4 - -#define I2C_ULP_XPD_LVDET 3 -#define I2C_ULP_XPD_LVDET_MSB 7 -#define I2C_ULP_XPD_LVDET_LSB 7 - -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4 -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0 -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0 - -#define I2C_ULP_INT_XPD_XTAL_BUF 4 -#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1 -#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1 - -#define I2C_ULP_INT_XPD_RC_CK 4 -#define I2C_ULP_INT_XPD_RC_CK_MSB 2 -#define I2C_ULP_INT_XPD_RC_CK_LSB 2 - -#define I2C_ULP_XTAL_DPHASE 4 -#define I2C_ULP_XTAL_DPHASE_MSB 3 -#define I2C_ULP_XTAL_DPHASE_LSB 3 - -#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4 -#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4 -#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4 - -#define I2C_ULP_XTAL_RESTART_DC_CAL 4 -#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5 -#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5 - -#define I2C_ULP_XTAL_DAC 5 -#define I2C_ULP_XTAL_DAC_MSB 3 -#define I2C_ULP_XTAL_DAC_LSB 0 - -#define I2C_ULP_XTAL_DBLEED 6 -#define I2C_ULP_XTAL_DBLEED_MSB 4 -#define I2C_ULP_XTAL_DBLEED_LSB 0 - -#define I2C_ULP_XTAL_CAL_DONE 6 -#define I2C_ULP_XTAL_CAL_DONE_MSB 5 -#define I2C_ULP_XTAL_CAL_DONE_LSB 5 - -#define I2C_ULP_ZOS_DONE 6 -#define I2C_ULP_ZOS_DONE_MSB 6 -#define I2C_ULP_ZOS_DONE_LSB 6 diff --git a/components/soc/esp32h4/i2s_periph.c b/components/soc/esp32h4/i2s_periph.c deleted file mode 100644 index 26a3d5503c..0000000000 --- a/components/soc/esp32h4/i2s_periph.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/i2s_periph.h" -#include "soc/gpio_sig_map.h" - -/* - Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc -*/ -const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { - { - .mck_out_sig = I2S_MCLK_OUT_IDX, - - .m_tx_bck_sig = I2SO_BCK_OUT_IDX, - .m_rx_bck_sig = I2SI_BCK_OUT_IDX, - .m_tx_ws_sig = I2SO_WS_OUT_IDX, - .m_rx_ws_sig = I2SI_WS_OUT_IDX, - - .s_tx_bck_sig = I2SO_BCK_IN_IDX, - .s_rx_bck_sig = I2SI_BCK_IN_IDX, - .s_tx_ws_sig = I2SO_WS_IN_IDX, - .s_rx_ws_sig = I2SI_WS_IN_IDX, - - .data_out_sigs[0] = I2SO_SD_OUT_IDX, - .data_out_sigs[1] = I2SO_SD1_OUT_IDX, - .data_in_sig = I2SI_SD_IN_IDX, - - .irq = ETS_I2S1_INTR_SOURCE, - .module = PERIPH_I2S1_MODULE, - } -}; diff --git a/components/soc/esp32h4/include/rev1/soc/assist_debug_reg.h b/components/soc/esp32h4/include/rev1/soc/assist_debug_reg.h deleted file mode 100644 index 2307e36149..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/assist_debug_reg.h +++ /dev/null @@ -1,683 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_ASSIST_DEBUG_REG_H_ -#define _SOC_ASSIST_DEBUG_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) -/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 -/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 - -#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004) -/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 -/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 - -#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008) -/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 -/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 - -#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C) -/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 -/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 -/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1 -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010) -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014) -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018) -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C) -/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020) -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024) -/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x028) -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x02C) -/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x030) -/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S)) -#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 - -#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x034) -/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S)) -#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 - -#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x038) -/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S)) -#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 - -#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x03C) -/* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S)) -#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 - -#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x040) -/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S)) -#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 - -#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x044) -/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable CPU Pdebug function if enable CPU will update PdebugPC*/ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (BIT(1)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x1 -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 -/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable recording function if enable assist_debug will update - PdebugPC so you can read it*/ -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (BIT(0)) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x1 -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 - -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x048) -/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 - -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x04C) -/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 - -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x050) -/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 -/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 -/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 - -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x054) -/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 -/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1 -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 -/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 - -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x058) -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000F -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(24)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1 -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0xFFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 - -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x05C) -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 - -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x060) -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000F -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(24)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1 -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0xFFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 - -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x064) -/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 - -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x068) -/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 - -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x06C) -/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 - -#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x070) -/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7)) -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(7)) -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1 -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7 -/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MODE 0x0000000F -#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S)) -#define ASSIST_DEBUG_LOG_MODE_V 0xF -#define ASSIST_DEBUG_LOG_MODE_S 3 -/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_ENA 0x00000007 -#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S)) -#define ASSIST_DEBUG_LOG_ENA_V 0x7 -#define ASSIST_DEBUG_LOG_ENA_S 0 - -#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x074) -/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S)) -#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_DATA_0_S 0 - -#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x078) -/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF -#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S)) -#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF -#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0 - -#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x07C) -/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S)) -#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MIN_S 0 - -#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x080) -/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S)) -#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MAX_S 0 - -#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x084) -/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S)) -#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MEM_START_S 0 - -#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x088) -/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S)) -#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MEM_END_S 0 - -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x08C) -/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)) -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0 - -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x090) -/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1)) -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (BIT(1)) -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x1 -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1 -/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0)) -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0)) -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1 -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0 - -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094) -/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)) -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 - -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098) -/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (BIT(1)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x1 -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 -/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x1 -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 - -#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC) -/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */ -/*description: */ -#define ASSIST_DEBUG_DATE 0x0FFFFFFF -#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S)) -#define ASSIST_DEBUG_DATE_V 0xFFFFFFF -#define ASSIST_DEBUG_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_ASSIST_DEBUG_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/clkrst_reg.h b/components/soc/esp32h4/include/rev1/soc/clkrst_reg.h deleted file mode 100644 index 727ce1e34e..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/clkrst_reg.h +++ /dev/null @@ -1,1043 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_CLKRST_REG_H_ -#define _SOC_CLKRST_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0000) -/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h3 ; */ -/*description: */ -#define SYSTEM_SOC_CLK_SEL 0x00000003 -#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) -#define SYSTEM_SOC_CLK_SEL_V 0x3 -#define SYSTEM_SOC_CLK_SEL_S 16 -/* SYSTEM_SPLL_FREQ : RO ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define SYSTEM_SPLL_FREQ 0x000000FF -#define SYSTEM_SPLL_FREQ_M ((SYSTEM_SPLL_FREQ_V)<<(SYSTEM_SPLL_FREQ_S)) -#define SYSTEM_SPLL_FREQ_V 0xFF -#define SYSTEM_SPLL_FREQ_S 8 -/* SYSTEM_XTAL_FREQ : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SYSTEM_CLK_XTAL_FREQ 0x000000FF -#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) -#define SYSTEM_CLK_XTAL_FREQ_V 0xFF -#define SYSTEM_CLK_XTAL_FREQ_S 0 - -#define SYSTEM_CPUCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0004) -/* SYSTEM_CPU_DIV_DENOMINATOR : R/W ;bitpos:[21:16] ;default: 6'h0 ; */ -/*description: */ -#define SYSTEM_CPU_DIV_DENOMINATOR 0x0000003F -#define SYSTEM_CPU_DIV_DENOMINATOR_M ((SYSTEM_CPU_DIV_DENOMINATOR_V)<<(SYSTEM_CPU_DIV_DENOMINATOR_S)) -#define SYSTEM_CPU_DIV_DENOMINATOR_V 0x3F -#define SYSTEM_CPU_DIV_DENOMINATOR_S 16 -/* SYSTEM_CPU_DIV_NUMERATOR : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ -/*description: */ -#define SYSTEM_CPU_DIV_NUMERATOR 0x0000003F -#define SYSTEM_CPU_DIV_NUMERATOR_M ((SYSTEM_CPU_DIV_NUMERATOR_V)<<(SYSTEM_CPU_DIV_NUMERATOR_S)) -#define SYSTEM_CPU_DIV_NUMERATOR_V 0x3F -#define SYSTEM_CPU_DIV_NUMERATOR_S 8 -/* SYSTEM_CPU_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SYSTEM_CPU_DIV_NUM 0x000000FF -#define SYSTEM_CPU_DIV_NUM_M ((SYSTEM_CPU_DIV_NUM_V)<<(SYSTEM_CPU_DIV_NUM_S)) -#define SYSTEM_CPU_DIV_NUM_V 0xFF -#define SYSTEM_CPU_DIV_NUM_S 0 - -#define SYSTEM_PRE_DIV_CNT SYSTEM_CPU_DIV_NUM -#define SYSTEM_PRE_DIV_CNT_M SYSTEM_CPU_DIV_NUM_M -#define SYSTEM_PRE_DIV_CNT_V SYSTEM_CPU_DIV_NUM_V -#define SYSTEM_PRE_DIV_CNT_S SYSTEM_CPU_DIV_NUM_S - -#define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0008) -/* SYSTEM_AHB_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define SYSTEM_AHB_DIV_NUM 0x000000FF -#define SYSTEM_AHB_DIV_NUM_M ((SYSTEM_AHB_DIV_NUM_V)<<(SYSTEM_AHB_DIV_NUM_S)) -#define SYSTEM_AHB_DIV_NUM_V 0xFF -#define SYSTEM_AHB_DIV_NUM_S 8 -/* SYSTEM_APB_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SYSTEM_APB_DIV_NUM 0x000000FF -#define SYSTEM_APB_DIV_NUM_M ((SYSTEM_APB_DIV_NUM_V)<<(SYSTEM_APB_DIV_NUM_S)) -#define SYSTEM_APB_DIV_NUM_V 0xFF -#define SYSTEM_APB_DIV_NUM_S 0 - -#define SYSTEM_MODCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x000C) -/* SYSTEM_MODEM_CLK_SEL : R/W ;bitpos:[1:0] ;default: 1'h1 ; */ -/*description: */ -#define SYSTEM_MODEM_CLK_SEL 0x00000003 -#define SYSTEM_MODEM_CLK_SEL_M ((SYSTEM_MODEM_CLK_SEL_V)<<(SYSTEM_MODEM_CLK_SEL_S)) -#define SYSTEM_MODEM_CLK_SEL_V 0x3 -#define SYSTEM_MODEM_CLK_SEL_S 0 - -#define SYSTEM_CLK_OUT_EN_REG (DR_REG_CLKRST_BASE + 0x0010) -/* SYSTEM_CLK_RFADC_OEN : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_RFADC_OEN (BIT(12)) -#define SYSTEM_CLK_RFADC_OEN_M (BIT(12)) -#define SYSTEM_CLK_RFADC_OEN_V 0x1 -#define SYSTEM_CLK_RFADC_OEN_S 12 -/* SYSTEM_CLK_RFDAC_OEN : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_RFDAC_OEN (BIT(11)) -#define SYSTEM_CLK_RFDAC_OEN_M (BIT(11)) -#define SYSTEM_CLK_RFDAC_OEN_V 0x1 -#define SYSTEM_CLK_RFDAC_OEN_S 11 -/* SYSTEM_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_XTAL_OEN (BIT(10)) -#define SYSTEM_CLK_XTAL_OEN_M (BIT(10)) -#define SYSTEM_CLK_XTAL_OEN_V 0x1 -#define SYSTEM_CLK_XTAL_OEN_S 10 -/* SYSTEM_CLK_SPLL_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_SPLL_OEN (BIT(9)) -#define SYSTEM_CLK_SPLL_OEN_M (BIT(9)) -#define SYSTEM_CLK_SPLL_OEN_V 0x1 -#define SYSTEM_CLK_SPLL_OEN_S 9 -/* SYSTEM_CLK_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_CPU_OEN (BIT(8)) -#define SYSTEM_CLK_CPU_OEN_M (BIT(8)) -#define SYSTEM_CLK_CPU_OEN_V 0x1 -#define SYSTEM_CLK_CPU_OEN_S 8 -/* SYSTEM_CLK_AHB_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_AHB_OEN (BIT(7)) -#define SYSTEM_CLK_AHB_OEN_M (BIT(7)) -#define SYSTEM_CLK_AHB_OEN_V 0x1 -#define SYSTEM_CLK_AHB_OEN_S 7 -/* SYSTEM_CLK_APB_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_APB_OEN (BIT(6)) -#define SYSTEM_CLK_APB_OEN_M (BIT(6)) -#define SYSTEM_CLK_APB_OEN_V 0x1 -#define SYSTEM_CLK_APB_OEN_S 6 -/* SYSTEM_CLK_32M_BT_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_32M_BT_OEN (BIT(5)) -#define SYSTEM_CLK_32M_BT_OEN_M (BIT(5)) -#define SYSTEM_CLK_32M_BT_OEN_V 0x1 -#define SYSTEM_CLK_32M_BT_OEN_S 5 -/* SYSTEM_CLK_16M_BT_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_16M_BT_OEN (BIT(4)) -#define SYSTEM_CLK_16M_BT_OEN_M (BIT(4)) -#define SYSTEM_CLK_16M_BT_OEN_V 0x1 -#define SYSTEM_CLK_16M_BT_OEN_S 4 -/* SYSTEM_CLK_8M_BT_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_8M_BT_OEN (BIT(3)) -#define SYSTEM_CLK_8M_BT_OEN_M (BIT(3)) -#define SYSTEM_CLK_8M_BT_OEN_V 0x1 -#define SYSTEM_CLK_8M_BT_OEN_S 3 - -#define SYSTEM_MODEM_CLK_EN_REG (DR_REG_CLKRST_BASE + 0x0014) -/* SYSTEM_DATA_DUMP_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DATA_DUMP_CLK_EN (BIT(21)) -#define SYSTEM_DATA_DUMP_CLK_EN_M (BIT(21)) -#define SYSTEM_DATA_DUMP_CLK_EN_V 0x1 -#define SYSTEM_DATA_DUMP_CLK_EN_S 21 -/* SYSTEM_RFADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RFADC_CLK_EN (BIT(20)) -#define SYSTEM_RFADC_CLK_EN_M (BIT(20)) -#define SYSTEM_RFADC_CLK_EN_V 0x1 -#define SYSTEM_RFADC_CLK_EN_S 20 -/* SYSTEM_RFDAC_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RFDAC_CLK_EN (BIT(19)) -#define SYSTEM_RFDAC_CLK_EN_M (BIT(19)) -#define SYSTEM_RFDAC_CLK_EN_V 0x1 -#define SYSTEM_RFDAC_CLK_EN_S 19 -/* SYSTEM_BTLC_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BTLC_CLK_EN (BIT(18)) -#define SYSTEM_BTLC_CLK_EN_M (BIT(18)) -#define SYSTEM_BTLC_CLK_EN_V 0x1 -#define SYSTEM_BTLC_CLK_EN_S 18 -/* SYSTEM_BLE_SEC_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_CLK_EN (BIT(17)) -#define SYSTEM_BLE_SEC_CLK_EN_M (BIT(17)) -#define SYSTEM_BLE_SEC_CLK_EN_V 0x1 -#define SYSTEM_BLE_SEC_CLK_EN_S 17 -/* SYSTEM_BLE_SEC_BAH_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_BAH_CLK_EN (BIT(16)) -#define SYSTEM_BLE_SEC_BAH_CLK_EN_M (BIT(16)) -#define SYSTEM_BLE_SEC_BAH_CLK_EN_V 0x1 -#define SYSTEM_BLE_SEC_BAH_CLK_EN_S 16 -/* SYSTEM_BLE_SEC_CCM_CLK_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_CCM_CLK_EN (BIT(15)) -#define SYSTEM_BLE_SEC_CCM_CLK_EN_M (BIT(15)) -#define SYSTEM_BLE_SEC_CCM_CLK_EN_V 0x1 -#define SYSTEM_BLE_SEC_CCM_CLK_EN_S 15 -/* SYSTEM_BLE_SEC_ECB_CLK_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_ECB_CLK_EN (BIT(14)) -#define SYSTEM_BLE_SEC_ECB_CLK_EN_M (BIT(14)) -#define SYSTEM_BLE_SEC_ECB_CLK_EN_V 0x1 -#define SYSTEM_BLE_SEC_ECB_CLK_EN_S 14 -/* SYSTEM_IEEE802154MAC_CLK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_IEEE802154MAC_CLK_EN (BIT(13)) -#define SYSTEM_IEEE802154MAC_CLK_EN_M (BIT(13)) -#define SYSTEM_IEEE802154MAC_CLK_EN_V 0x1 -#define SYSTEM_IEEE802154MAC_CLK_EN_S 13 -/* SYSTEM_IEEE802154BB_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_IEEE802154BB_CLK_EN (BIT(12)) -#define SYSTEM_IEEE802154BB_CLK_EN_M (BIT(12)) -#define SYSTEM_IEEE802154BB_CLK_EN_V 0x1 -#define SYSTEM_IEEE802154BB_CLK_EN_S 12 -/* SYSTEM_COEX_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COEX_CLK_EN (BIT(11)) -#define SYSTEM_COEX_CLK_EN_M (BIT(11)) -#define SYSTEM_COEX_CLK_EN_V 0x1 -#define SYSTEM_COEX_CLK_EN_S 11 -/* SYSTEM_I2CMST_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_I2CMST_CLK_EN (BIT(10)) -#define SYSTEM_I2CMST_CLK_EN_M (BIT(10)) -#define SYSTEM_I2CMST_CLK_EN_V 0x1 -#define SYSTEM_I2CMST_CLK_EN_S 10 -/* SYSTEM_I2C_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_I2C_CLK_EN (BIT(9)) -#define SYSTEM_I2C_CLK_EN_M (BIT(9)) -#define SYSTEM_I2C_CLK_EN_V 0x1 -#define SYSTEM_I2C_CLK_EN_S 9 -/* SYSTEM_RW_BTMAC_CLK_EN : R/W ;bitpos:[8] ;default: 2'b0 ; */ -/*description: */ -#define SYSTEM_RW_BTMAC_CLK_EN (BIT(8)) -#define SYSTEM_RW_BTMAC_CLK_EN_M (BIT(8)) -#define SYSTEM_RW_BTMAC_CLK_EN_V 0x1 -#define SYSTEM_RW_BTMAC_CLK_EN_S 8 -/* SYSTEM_MACPWR_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_MACPWR_CLK_EN (BIT(7)) -#define SYSTEM_MACPWR_CLK_EN_M (BIT(7)) -#define SYSTEM_MACPWR_CLK_EN_V 0x1 -#define SYSTEM_MACPWR_CLK_EN_S 7 -/* SYSTEM_EMAC_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_EMAC_CLK_EN (BIT(6)) -#define SYSTEM_EMAC_CLK_EN_M (BIT(6)) -#define SYSTEM_EMAC_CLK_EN_V 0x1 -#define SYSTEM_EMAC_CLK_EN_S 6 -/* SYSTEM_SDIO_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SDIO_CLK_EN (BIT(5)) -#define SYSTEM_SDIO_CLK_EN_M (BIT(5)) -#define SYSTEM_SDIO_CLK_EN_V 0x1 -#define SYSTEM_SDIO_CLK_EN_S 5 -/* SYSTEM_BTMAC_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BTMAC_CLK_EN (BIT(4)) -#define SYSTEM_BTMAC_CLK_EN_M (BIT(4)) -#define SYSTEM_BTMAC_CLK_EN_V 0x1 -#define SYSTEM_BTMAC_CLK_EN_S 4 -/* SYSTEM_BT_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BT_CLK_EN (BIT(3)) -#define SYSTEM_BT_CLK_EN_M (BIT(3)) -#define SYSTEM_BT_CLK_EN_V 0x1 -#define SYSTEM_BT_CLK_EN_S 3 -/* SYSTEM_MAC_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MAC_CLK_EN (BIT(2)) -#define SYSTEM_MAC_CLK_EN_M (BIT(2)) -#define SYSTEM_MAC_CLK_EN_V 0x1 -#define SYSTEM_MAC_CLK_EN_S 2 -/* SYSTEM_FE_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_FE_CLK_EN (BIT(1)) -#define SYSTEM_FE_CLK_EN_M (BIT(1)) -#define SYSTEM_FE_CLK_EN_V 0x1 -#define SYSTEM_FE_CLK_EN_S 1 -/* SYSTEM_FE_CAL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_FE_CAL_CLK_EN (BIT(0)) -#define SYSTEM_FE_CAL_CLK_EN_M (BIT(0)) -#define SYSTEM_FE_CAL_CLK_EN_V 0x1 -#define SYSTEM_FE_CAL_CLK_EN_S 0 - -#define SYSTEM_MODEM_RST_EN_REG (DR_REG_CLKRST_BASE + 0x0018) -/* SYSTEM_DATA_DUMP_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DATA_DUMP_RST (BIT(20)) -#define SYSTEM_DATA_DUMP_RST_M (BIT(20)) -#define SYSTEM_DATA_DUMP_RST_V 0x1 -#define SYSTEM_DATA_DUMP_RST_S 20 -/* SYSTEM_APB_RET_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_APB_RET_RST (BIT(19)) -#define SYSTEM_APB_RET_RST_M (BIT(19)) -#define SYSTEM_APB_RET_RST_V 0x1 -#define SYSTEM_APB_RET_RST_S 19 -/* SYSTEM_BLE_SEC_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_RST (BIT(18)) -#define SYSTEM_BLE_SEC_RST_M (BIT(18)) -#define SYSTEM_BLE_SEC_RST_V 0x1 -#define SYSTEM_BLE_SEC_RST_S 18 -/* SYSTEM_BLE_SEC_BAH_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_BAH_RST (BIT(17)) -#define SYSTEM_BLE_SEC_BAH_RST_M (BIT(17)) -#define SYSTEM_BLE_SEC_BAH_RST_V 0x1 -#define SYSTEM_BLE_SEC_BAH_RST_S 17 -/* SYSTEM_BLE_SEC_CCM_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_CCM_RST (BIT(16)) -#define SYSTEM_BLE_SEC_CCM_RST_M (BIT(16)) -#define SYSTEM_BLE_SEC_CCM_RST_V 0x1 -#define SYSTEM_BLE_SEC_CCM_RST_S 16 -/* SYSTEM_BLE_SEC_ECB_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BLE_SEC_ECB_RST (BIT(15)) -#define SYSTEM_BLE_SEC_ECB_RST_M (BIT(15)) -#define SYSTEM_BLE_SEC_ECB_RST_V 0x1 -#define SYSTEM_BLE_SEC_ECB_RST_S 15 -/* SYSTEM_IEEE802154MAC_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_IEEE802154MAC_RST (BIT(14)) -#define SYSTEM_IEEE802154MAC_RST_M (BIT(14)) -#define SYSTEM_IEEE802154MAC_RST_V 0x1 -#define SYSTEM_IEEE802154MAC_RST_S 14 -/* SYSTEM_IEEE802154BB_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_IEEE802154BB_RST (BIT(13)) -#define SYSTEM_IEEE802154BB_RST_M (BIT(13)) -#define SYSTEM_IEEE802154BB_RST_V 0x1 -#define SYSTEM_IEEE802154BB_RST_S 13 -/* SYSTEM_COEX_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_COEX_RST (BIT(12)) -#define SYSTEM_COEX_RST_M (BIT(12)) -#define SYSTEM_COEX_RST_V 0x1 -#define SYSTEM_COEX_RST_S 12 -/* SYSTEM_BT_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BT_REG_RST (BIT(11)) -#define SYSTEM_BT_REG_RST_M (BIT(11)) -#define SYSTEM_BT_REG_RST_V 0x1 -#define SYSTEM_BT_REG_RST_S 11 -/* SYSTEM_RW_BTLPRST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RW_BTLPRST (BIT(10)) -#define SYSTEM_RW_BTLPRST_M (BIT(10)) -#define SYSTEM_RW_BTLPRST_V 0x1 -#define SYSTEM_RW_BTLPRST_S 10 -/* SYSTEM_RW_BTRST : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RW_BTRST (BIT(9)) -#define SYSTEM_RW_BTRST_M (BIT(9)) -#define SYSTEM_RW_BTRST_V 0x1 -#define SYSTEM_RW_BTRST_S 9 -/* SYSTEM_RW_BTLP_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RW_BTLP_RST (BIT(8)) -#define SYSTEM_RW_BTLP_RST_M (BIT(8)) -#define SYSTEM_RW_BTLP_RST_V 0x1 -#define SYSTEM_RW_BTLP_RST_S 8 -/* SYSTEM_RW_BTMAC_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RW_BTMAC_RST (BIT(7)) -#define SYSTEM_RW_BTMAC_RST_M (BIT(7)) -#define SYSTEM_RW_BTMAC_RST_V 0x1 -#define SYSTEM_RW_BTMAC_RST_S 7 -/* SYSTEM_MACPWR_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MACPWR_RST (BIT(6)) -#define SYSTEM_MACPWR_RST_M (BIT(6)) -#define SYSTEM_MACPWR_RST_V 0x1 -#define SYSTEM_MACPWR_RST_S 6 -/* SYSTEM_EMAC_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_EMAC_RST (BIT(5)) -#define SYSTEM_EMAC_RST_M (BIT(5)) -#define SYSTEM_EMAC_RST_V 0x1 -#define SYSTEM_EMAC_RST_S 5 -/* SYSTEM_SDIO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SDIO_RST (BIT(4)) -#define SYSTEM_SDIO_RST_M (BIT(4)) -#define SYSTEM_SDIO_RST_V 0x1 -#define SYSTEM_SDIO_RST_S 4 -/* SYSTEM_BTMAC_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BTMAC_RST (BIT(3)) -#define SYSTEM_BTMAC_RST_M (BIT(3)) -#define SYSTEM_BTMAC_RST_V 0x1 -#define SYSTEM_BTMAC_RST_S 3 -/* SYSTEM_BT_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_BT_RST (BIT(2)) -#define SYSTEM_BT_RST_M (BIT(2)) -#define SYSTEM_BT_RST_V 0x1 -#define SYSTEM_BT_RST_S 2 -/* SYSTEM_MAC_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MAC_RST (BIT(1)) -#define SYSTEM_MAC_RST_M (BIT(1)) -#define SYSTEM_MAC_RST_V 0x1 -#define SYSTEM_MAC_RST_S 1 -/* SYSTEM_FE_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_FE_RST (BIT(0)) -#define SYSTEM_FE_RST_M (BIT(0)) -#define SYSTEM_FE_RST_V 0x1 -#define SYSTEM_FE_RST_S 0 - -#define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_CLKRST_BASE + 0x001C) -/* SYSTEM_MSPI_DIV_NUM : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ -/*description: */ -#define SYSTEM_MSPI_DIV_NUM 0x000000FF -#define SYSTEM_MSPI_DIV_NUM_M ((SYSTEM_MSPI_DIV_NUM_V)<<(SYSTEM_MSPI_DIV_NUM_S)) -#define SYSTEM_MSPI_DIV_NUM_V 0xFF -#define SYSTEM_MSPI_DIV_NUM_S 24 -/* SYSTEM_TWAI_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ -/*description: */ -#define SYSTEM_TWAI_DIV_NUM 0x000000FF -#define SYSTEM_TWAI_DIV_NUM_M ((SYSTEM_TWAI_DIV_NUM_V)<<(SYSTEM_TWAI_DIV_NUM_S)) -#define SYSTEM_TWAI_DIV_NUM_V 0xFF -#define SYSTEM_TWAI_DIV_NUM_S 16 -/* SYSTEM_USB_DEVICE_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: */ -#define SYSTEM_USB_DEVICE_DIV_NUM 0x000000FF -#define SYSTEM_USB_DEVICE_DIV_NUM_M ((SYSTEM_USB_DEVICE_DIV_NUM_V)<<(SYSTEM_USB_DEVICE_DIV_NUM_S)) -#define SYSTEM_USB_DEVICE_DIV_NUM_V 0xFF -#define SYSTEM_USB_DEVICE_DIV_NUM_S 8 -/* SYSTEM_SEC_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: */ -#define SYSTEM_SEC_DIV_NUM 0x000000FF -#define SYSTEM_SEC_DIV_NUM_M ((SYSTEM_SEC_DIV_NUM_V)<<(SYSTEM_SEC_DIV_NUM_S)) -#define SYSTEM_SEC_DIV_NUM_V 0xFF -#define SYSTEM_SEC_DIV_NUM_S 0 - -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_CLKRST_BASE + 0x0020) -/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ -/*description: */ -#define SYSTEM_SPI4_CLK_EN (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_V 0x1 -#define SYSTEM_SPI4_CLK_EN_S 31 -/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 -#define SYSTEM_ADC2_ARB_CLK_EN_S 30 -/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 -#define SYSTEM_SYSTIMER_CLK_EN_S 29 -/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 -#define SYSTEM_APB_SARADC_CLK_EN_S 28 -/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 -#define SYSTEM_SPI3_DMA_CLK_EN_S 27 -/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM3_CLK_EN (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_V 0x1 -#define SYSTEM_PWM3_CLK_EN_S 26 -/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM2_CLK_EN (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_V 0x1 -#define SYSTEM_PWM2_CLK_EN_S 25 -/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_V 0x1 -#define SYSTEM_UART_MEM_CLK_EN_S 24 -/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) -#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) -#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 -#define SYSTEM_USB_DEVICE_CLK_EN_S 23 -/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 -#define SYSTEM_SPI2_DMA_CLK_EN_S 22 -/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S1_CLK_EN (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_V 0x1 -#define SYSTEM_I2S1_CLK_EN_S 21 -/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM1_CLK_EN (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_V 0x1 -#define SYSTEM_PWM1_CLK_EN_S 20 -/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TWAI_CLK_EN (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_V 0x1 -#define SYSTEM_TWAI_CLK_EN_S 19 -/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT1_CLK_EN_S 18 -/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM0_CLK_EN (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_V 0x1 -#define SYSTEM_PWM0_CLK_EN_S 17 -/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI3_CLK_EN (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_V 0x1 -#define SYSTEM_SPI3_CLK_EN_S 16 -/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 -/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_EFUSE_CLK_EN (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_V 0x1 -#define SYSTEM_EFUSE_CLK_EN_S 14 -/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP_CLK_EN_S 13 -/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI1_CLK_EN (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_V 0x1 -#define SYSTEM_UHCI1_CLK_EN_S 12 -/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LEDC_CLK_EN (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_V 0x1 -#define SYSTEM_LEDC_CLK_EN_S 11 -/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PCNT_CLK_EN (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_V 0x1 -#define SYSTEM_PCNT_CLK_EN_S 10 -/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RMT_CLK_EN (BIT(9)) -#define SYSTEM_RMT_CLK_EN_M (BIT(9)) -#define SYSTEM_RMT_CLK_EN_V 0x1 -#define SYSTEM_RMT_CLK_EN_S 9 -/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI0_CLK_EN (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_V 0x1 -#define SYSTEM_UHCI0_CLK_EN_S 8 -/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 -#define SYSTEM_I2C_EXT0_CLK_EN_S 7 -/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI2_CLK_EN (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_V 0x1 -#define SYSTEM_SPI2_CLK_EN_S 6 -/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART1_CLK_EN (BIT(5)) -#define SYSTEM_UART1_CLK_EN_M (BIT(5)) -#define SYSTEM_UART1_CLK_EN_V 0x1 -#define SYSTEM_UART1_CLK_EN_S 5 -/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S0_CLK_EN (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_V 0x1 -#define SYSTEM_I2S0_CLK_EN_S 4 -/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_WDG_CLK_EN (BIT(3)) -#define SYSTEM_WDG_CLK_EN_M (BIT(3)) -#define SYSTEM_WDG_CLK_EN_V 0x1 -#define SYSTEM_WDG_CLK_EN_S 3 -/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART_CLK_EN (BIT(2)) -#define SYSTEM_UART_CLK_EN_M (BIT(2)) -#define SYSTEM_UART_CLK_EN_V 0x1 -#define SYSTEM_UART_CLK_EN_S 2 -/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SPI01_CLK_EN (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_V 0x1 -#define SYSTEM_SPI01_CLK_EN_S 1 -/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_TIMERS_CLK_EN (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_V 0x1 -#define SYSTEM_TIMERS_CLK_EN_S 0 - -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_CLKRST_BASE + 0x0024) -/* SYSTEM_PVT_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_PVT_CLK_EN (BIT(15)) -#define SYSTEM_PVT_CLK_EN_M (BIT(15)) -#define SYSTEM_PVT_CLK_EN_V 0x1 -#define SYSTEM_PVT_CLK_EN_S 15 -/* SYSTEM_REGRET_CLK_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_REGRET_CLK_EN (BIT(14)) -#define SYSTEM_REGRET_CLK_EN_M (BIT(14)) -#define SYSTEM_REGRET_CLK_EN_V 0x1 -#define SYSTEM_REGRET_CLK_EN_S 14 -/* SYSTEM_TIMERGROUP3_CLK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP3_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP3_CLK_EN_M (BIT(13)) -#define SYSTEM_TIMERGROUP3_CLK_EN_V 0x1 -#define SYSTEM_TIMERGROUP3_CLK_EN_S 13 -/* SYSTEM_ETM_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ETM_CLK_EN (BIT(12)) -#define SYSTEM_ETM_CLK_EN_M (BIT(12)) -#define SYSTEM_ETM_CLK_EN_V 0x1 -#define SYSTEM_ETM_CLK_EN_S 12 -/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TSENS_CLK_EN (BIT(11)) -#define SYSTEM_TSENS_CLK_EN_M (BIT(11)) -#define SYSTEM_TSENS_CLK_EN_V 0x1 -#define SYSTEM_TSENS_CLK_EN_S 11 -/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_UART2_CLK_EN (BIT(10)) -#define SYSTEM_UART2_CLK_EN_M (BIT(10)) -#define SYSTEM_UART2_CLK_EN_V 0x1 -#define SYSTEM_UART2_CLK_EN_S 10 -/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LCD_CAM_CLK_EN (BIT(9)) -#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(9)) -#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 -#define SYSTEM_LCD_CAM_CLK_EN_S 9 -/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SDIO_HOST_CLK_EN (BIT(8)) -#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(8)) -#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 -#define SYSTEM_SDIO_HOST_CLK_EN_S 8 -/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DMA_CLK_EN (BIT(7)) -#define SYSTEM_DMA_CLK_EN_M (BIT(7)) -#define SYSTEM_DMA_CLK_EN_V 0x1 -#define SYSTEM_DMA_CLK_EN_S 7 -/* SYSTEM_CRYPTO_ECC_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(6)) -#define SYSTEM_CRYPTO_ECC_CLK_EN_M (BIT(6)) -#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_ECC_CLK_EN_S 6 -/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 -/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 -/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 -/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 -/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 -#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 -/* SYSTEM_RETENTION_TOP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RETENTION_TOP_CLK_EN (BIT(0)) -#define SYSTEM_RETENTION_TOP_CLK_EN_M (BIT(0)) -#define SYSTEM_RETENTION_TOP_CLK_EN_V 0x1 -#define SYSTEM_RETENTION_TOP_CLK_EN_S 0 - -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_CLKRST_BASE + 0x0028) -/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SYSTEM_SPI4_RST (BIT(31)) -#define SYSTEM_SPI4_RST_M (BIT(31)) -#define SYSTEM_SPI4_RST_V 0x1 -#define SYSTEM_SPI4_RST_S 31 -/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ADC2_ARB_RST (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_V 0x1 -#define SYSTEM_ADC2_ARB_RST_S 30 -/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SYSTIMER_RST (BIT(29)) -#define SYSTEM_SYSTIMER_RST_M (BIT(29)) -#define SYSTEM_SYSTIMER_RST_V 0x1 -#define SYSTEM_SYSTIMER_RST_S 29 -/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_APB_SARADC_RST (BIT(28)) -#define SYSTEM_APB_SARADC_RST_M (BIT(28)) -#define SYSTEM_APB_SARADC_RST_V 0x1 -#define SYSTEM_APB_SARADC_RST_S 28 -/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI3_DMA_RST (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_V 0x1 -#define SYSTEM_SPI3_DMA_RST_S 27 -/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM3_RST (BIT(26)) -#define SYSTEM_PWM3_RST_M (BIT(26)) -#define SYSTEM_PWM3_RST_V 0x1 -#define SYSTEM_PWM3_RST_S 26 -/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM2_RST (BIT(25)) -#define SYSTEM_PWM2_RST_M (BIT(25)) -#define SYSTEM_PWM2_RST_V 0x1 -#define SYSTEM_PWM2_RST_S 25 -/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART_MEM_RST (BIT(24)) -#define SYSTEM_UART_MEM_RST_M (BIT(24)) -#define SYSTEM_UART_MEM_RST_V 0x1 -#define SYSTEM_UART_MEM_RST_S 24 -/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_USB_DEVICE_RST (BIT(23)) -#define SYSTEM_USB_DEVICE_RST_M (BIT(23)) -#define SYSTEM_USB_DEVICE_RST_V 0x1 -#define SYSTEM_USB_DEVICE_RST_S 23 -/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI2_DMA_RST (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_V 0x1 -#define SYSTEM_SPI2_DMA_RST_S 22 -/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S1_RST (BIT(21)) -#define SYSTEM_I2S1_RST_M (BIT(21)) -#define SYSTEM_I2S1_RST_V 0x1 -#define SYSTEM_I2S1_RST_S 21 -/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM1_RST (BIT(20)) -#define SYSTEM_PWM1_RST_M (BIT(20)) -#define SYSTEM_PWM1_RST_V 0x1 -#define SYSTEM_PWM1_RST_S 20 -/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TWAI_RST (BIT(19)) -#define SYSTEM_TWAI_RST_M (BIT(19)) -#define SYSTEM_TWAI_RST_V 0x1 -#define SYSTEM_TWAI_RST_S 19 -/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT1_RST (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_V 0x1 -#define SYSTEM_I2C_EXT1_RST_S 18 -/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PWM0_RST (BIT(17)) -#define SYSTEM_PWM0_RST_M (BIT(17)) -#define SYSTEM_PWM0_RST_V 0x1 -#define SYSTEM_PWM0_RST_S 17 -/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI3_RST (BIT(16)) -#define SYSTEM_SPI3_RST_M (BIT(16)) -#define SYSTEM_SPI3_RST_V 0x1 -#define SYSTEM_SPI3_RST_S 16 -/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP1_RST (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_V 0x1 -#define SYSTEM_TIMERGROUP1_RST_S 15 -/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_EFUSE_RST (BIT(14)) -#define SYSTEM_EFUSE_RST_M (BIT(14)) -#define SYSTEM_EFUSE_RST_V 0x1 -#define SYSTEM_EFUSE_RST_S 14 -/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP_RST (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_V 0x1 -#define SYSTEM_TIMERGROUP_RST_S 13 -/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI1_RST (BIT(12)) -#define SYSTEM_UHCI1_RST_M (BIT(12)) -#define SYSTEM_UHCI1_RST_V 0x1 -#define SYSTEM_UHCI1_RST_S 12 -/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_LEDC_RST (BIT(11)) -#define SYSTEM_LEDC_RST_M (BIT(11)) -#define SYSTEM_LEDC_RST_V 0x1 -#define SYSTEM_LEDC_RST_S 11 -/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PCNT_RST (BIT(10)) -#define SYSTEM_PCNT_RST_M (BIT(10)) -#define SYSTEM_PCNT_RST_V 0x1 -#define SYSTEM_PCNT_RST_S 10 -/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RMT_RST (BIT(9)) -#define SYSTEM_RMT_RST_M (BIT(9)) -#define SYSTEM_RMT_RST_V 0x1 -#define SYSTEM_RMT_RST_S 9 -/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UHCI0_RST (BIT(8)) -#define SYSTEM_UHCI0_RST_M (BIT(8)) -#define SYSTEM_UHCI0_RST_V 0x1 -#define SYSTEM_UHCI0_RST_S 8 -/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2C_EXT0_RST (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_V 0x1 -#define SYSTEM_I2C_EXT0_RST_S 7 -/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI2_RST (BIT(6)) -#define SYSTEM_SPI2_RST_M (BIT(6)) -#define SYSTEM_SPI2_RST_V 0x1 -#define SYSTEM_SPI2_RST_S 6 -/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART1_RST (BIT(5)) -#define SYSTEM_UART1_RST_M (BIT(5)) -#define SYSTEM_UART1_RST_V 0x1 -#define SYSTEM_UART1_RST_S 5 -/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_I2S0_RST (BIT(4)) -#define SYSTEM_I2S0_RST_M (BIT(4)) -#define SYSTEM_I2S0_RST_V 0x1 -#define SYSTEM_I2S0_RST_S 4 -/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_WDG_RST (BIT(3)) -#define SYSTEM_WDG_RST_M (BIT(3)) -#define SYSTEM_WDG_RST_V 0x1 -#define SYSTEM_WDG_RST_S 3 -/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART_RST (BIT(2)) -#define SYSTEM_UART_RST_M (BIT(2)) -#define SYSTEM_UART_RST_V 0x1 -#define SYSTEM_UART_RST_S 2 -/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_SPI01_RST (BIT(1)) -#define SYSTEM_SPI01_RST_M (BIT(1)) -#define SYSTEM_SPI01_RST_V 0x1 -#define SYSTEM_SPI01_RST_S 1 -/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERS_RST (BIT(0)) -#define SYSTEM_TIMERS_RST_M (BIT(0)) -#define SYSTEM_TIMERS_RST_V 0x1 -#define SYSTEM_TIMERS_RST_S 0 - -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_CLKRST_BASE + 0x002C) -/* SYSTEM_PVT_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_PVT_RST (BIT(15)) -#define SYSTEM_PVT_RST_M (BIT(15)) -#define SYSTEM_PVT_RST_V 0x1 -#define SYSTEM_PVT_RST_S 15 -/* SYSTEM_REGRET_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_REGRET_RST (BIT(14)) -#define SYSTEM_REGRET_RST_M (BIT(14)) -#define SYSTEM_REGRET_RST_V 0x1 -#define SYSTEM_REGRET_RST_S 14 -/* SYSTEM_TIMERGROUP3_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TIMERGROUP3_RST (BIT(13)) -#define SYSTEM_TIMERGROUP3_RST_M (BIT(13)) -#define SYSTEM_TIMERGROUP3_RST_V 0x1 -#define SYSTEM_TIMERGROUP3_RST_S 13 -/* SYSTEM_ETM_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ETM_RST (BIT(12)) -#define SYSTEM_ETM_RST_M (BIT(12)) -#define SYSTEM_ETM_RST_V 0x1 -#define SYSTEM_ETM_RST_S 12 -/* SYSTEM_TSENS_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_TSENS_RST (BIT(11)) -#define SYSTEM_TSENS_RST_M (BIT(11)) -#define SYSTEM_TSENS_RST_V 0x1 -#define SYSTEM_TSENS_RST_S 11 -/* SYSTEM_UART2_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_UART2_RST (BIT(10)) -#define SYSTEM_UART2_RST_M (BIT(10)) -#define SYSTEM_UART2_RST_V 0x1 -#define SYSTEM_UART2_RST_S 10 -/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LCD_CAM_RST (BIT(9)) -#define SYSTEM_LCD_CAM_RST_M (BIT(9)) -#define SYSTEM_LCD_CAM_RST_V 0x1 -#define SYSTEM_LCD_CAM_RST_S 9 -/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_SDIO_HOST_RST (BIT(8)) -#define SYSTEM_SDIO_HOST_RST_M (BIT(8)) -#define SYSTEM_SDIO_HOST_RST_V 0x1 -#define SYSTEM_SDIO_HOST_RST_S 8 -/* SYSTEM_DMA_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_DMA_RST (BIT(7)) -#define SYSTEM_DMA_RST_M (BIT(7)) -#define SYSTEM_DMA_RST_V 0x1 -#define SYSTEM_DMA_RST_S 7 -/* SYSTEM_CRYPTO_ECC_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_ECC_RST (BIT(6)) -#define SYSTEM_CRYPTO_ECC_RST_M (BIT(6)) -#define SYSTEM_CRYPTO_ECC_RST_V 0x1 -#define SYSTEM_CRYPTO_ECC_RST_S 6 -/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 -#define SYSTEM_CRYPTO_HMAC_RST_S 5 -/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_DS_RST (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_V 0x1 -#define SYSTEM_CRYPTO_DS_RST_S 4 -/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_V 0x1 -#define SYSTEM_CRYPTO_RSA_RST_S 3 -/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_V 0x1 -#define SYSTEM_CRYPTO_SHA_RST_S 2 -/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CRYPTO_AES_RST (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_V 0x1 -#define SYSTEM_CRYPTO_AES_RST_S 1 -/* SYSTEM_RETENTION_TOP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RETENTION_TOP_RST (BIT(0)) -#define SYSTEM_RETENTION_TOP_RST_M (BIT(0)) -#define SYSTEM_RETENTION_TOP_RST_V 0x1 -#define SYSTEM_RETENTION_TOP_RST_S 0 - -#define SYSTEM_FPGA_DBG_REG (DR_REG_CLKRST_BASE + 0x0030) -/* SYSTEM_FPGA_DEBUG : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define SYSTEM_FPGA_DEBUG 0xFFFFFFFF -#define SYSTEM_FPGA_DEBUG_M ((SYSTEM_FPGA_DEBUG_V)<<(SYSTEM_FPGA_DEBUG_S)) -#define SYSTEM_FPGA_DEBUG_V 0xFFFFFFFF -#define SYSTEM_FPGA_DEBUG_S 0 - -#define SYSTEMCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0034) -/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (BIT(0)) -#define SYSTEM_CLK_EN_V 0x1 -#define SYSTEM_CLK_EN_S 0 - -#define SYSTEM_CLKRST_DATE_REG (DR_REG_CLKRST_BASE + 0x038) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103191 ; */ -/*description: */ -#define CLKRST_DATE 0x0FFFFFFF -#define CLKRST_DATE_M ((CLKRST_DATE_V)<<(CLKRST_DATE_S)) -#define CLKRST_DATE_V 0xFFFFFFF -#define CLKRST_DATE_S 0 - -#ifdef __cplusplus -} -#endif - -#endif /*_SOC_CLKRST_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/efuse_reg.h b/components/soc/esp32h4/include/rev1/soc/efuse_reg.h deleted file mode 100644 index 48ee3ac856..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/efuse_reg.h +++ /dev/null @@ -1,2001 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_EFUSE_REG_H_ -#define _SOC_EFUSE_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Disable programming of individual eFuses.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 - -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_POWER_GLITCH_DSENSE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Sample delay configuration of power glitch.*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 30 -/* EFUSE_POWERGLITCH_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable power glitch function.*/ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: Enable btlc gpio.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_VDD_SPI_AS_GPIO : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to vdd spi pin function as gpio.*/ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to exchange USB D+ and D- pins.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with - step of 80 mV stored in eFuse.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to disable flash encryption when in download boot modes.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: Set these bits to disable JTAG in the soft way (odd number 1 - means disable ). JTAG can be enabled in HMAC module.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag - through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to disable TWAI function.*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 -#define EFUSE_RPT4_RESERVED6_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to disable the function that forces chip into download mode.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_DEVICE : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to disable usb device.*/ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] - is 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to disable function of usb switch to jtag in module of usb device.*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to disable Icache.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved*/ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: Set this bit to disable reading from BlOCK4-10.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 - -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Purpose of Key1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: Purpose of Key0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking third secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking second secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking first secure boot key.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of - 1: enable. even number of 1: disable.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: Selects RTC watchdog timeout threshold in unit of slow clock - cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ -#define EFUSE_WAT_DELAY_SEL 0x00000003 -#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) -#define EFUSE_WAT_DELAY_SEL_V 0x3 -#define EFUSE_WAT_DELAY_SEL_S 16 -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED2 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFF -#define EFUSE_RPT4_RESERVED2_S 0 - -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00C) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: Configures flash waiting time after power-up in unit of ms. - If the value is less than 15 the waiting time is the configurable value*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable revoking aggressive secure boot.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure boot.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED3 0x0000000F -#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) -#define EFUSE_RPT4_RESERVED3_V 0xF -#define EFUSE_RPT4_RESERVED3_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: Purpose of Key5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: Purpose of Key4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: Purpose of Key3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Purpose of Key2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 - -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED1 0x00000003 -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: Secure version (used by ESP-IDF anti-rollback feature).*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_RPT4_RESERVED7 : R/W ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED7 0x0000001F -#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S)) -#define EFUSE_RPT4_RESERVED7_V 0x1F -#define EFUSE_RPT4_RESERVED7_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: Set the default UARTboot message output mode. 00: Enabled. 01: - Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable secure UART download mode.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to disable download through USB-Serial-JTAG.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED8 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_V 0x1 -#define EFUSE_RPT4_RESERVED8_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Disable USB-Serial-JTAG print during rom boot.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to disable direct boot..*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 - -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved (used for four backups method).*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the sixth 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_S 0 - -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01C) -/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the seventh 32-bit data to be programmed.*/ -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_S 0 - -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the 0th 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_S 0 - -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the first 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_S 0 - -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The content of the second 32-bit RS code to be programmed.*/ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_S 0 - -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02C) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The value of WR_DIS.*/ -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 - -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: The value of POWER_GLITCH_DSENSE.*/ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S)) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_S 30 -/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The value of POWERGLITCH_EN.*/ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_V 0x1 -#define EFUSE_POWERGLITCH_EN_S 29 -/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: The value of BTLC_GPIO_ENABLE.*/ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S)) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/* EFUSE_VDD_SPI_AS_GPIO : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The value of VDD_SPI_AS_GPIO.*/ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The value of USB_EXCHG_PINS.*/ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_V 0x1 -#define EFUSE_USB_EXCHG_PINS_S 25 -/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: The value of USB_DREFL.*/ -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) -#define EFUSE_USB_DREFL_V 0x3 -#define EFUSE_USB_DREFL_S 23 -/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: The value of USB_DREFH.*/ -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) -#define EFUSE_USB_DREFH_V 0x3 -#define EFUSE_USB_DREFH_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The value of DIS_PAD_JTAG.*/ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_V 0x1 -#define EFUSE_DIS_PAD_JTAG_S 19 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of SOFT_DIS_JTAG.*/ -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S)) -#define EFUSE_SOFT_DIS_JTAG_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_S 16 -/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The value of JTAG_SEL_ENABLE.*/ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The value of DIS_TWAI.*/ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (BIT(14)) -#define EFUSE_DIS_TWAI_V 0x1 -#define EFUSE_DIS_TWAI_S 14 -/* EFUSE_RPT4_RESERVED6 : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved (used for four backups method)..*/ -#define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 -#define EFUSE_RPT4_RESERVED6_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The value of DIS_FORCE_DOWNLOAD.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_DEVICE.*/ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_V 0x1 -#define EFUSE_DIS_USB_DEVICE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_ICACHE.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_JTAG.*/ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_V 0x1 -#define EFUSE_DIS_USB_JTAG_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of DIS_ICACHE.*/ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (BIT(8)) -#define EFUSE_DIS_ICACHE_V 0x1 -#define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved*/ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The value of RD_DIS.*/ -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0x7F -#define EFUSE_RD_DIS_S 0 - -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_1.*/ -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) -#define EFUSE_KEY_PURPOSE_1_V 0xF -#define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_0.*/ -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) -#define EFUSE_KEY_PURPOSE_0_V 0xF -#define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: The value of SPI_BOOT_CRYPT_CNT.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The value of WDT_DELAY_SEL.*/ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) -#define EFUSE_RPT4_RESERVED2_V 0xFFFF -#define EFUSE_RPT4_RESERVED2_S 0 - -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: The value of FLASH_TPUW.*/ -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) -#define EFUSE_FLASH_TPUW_V 0xF -#define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0 0x0000003F -#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) -#define EFUSE_RPT4_RESERVED0_V 0x3F -#define EFUSE_RPT4_RESERVED0_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The value of SECURE_BOOT_EN.*/ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_V 0x1 -#define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED3 0x0000000F -#define EFUSE_RPT4_RESERVED3_M ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S)) -#define EFUSE_RPT4_RESERVED3_V 0xF -#define EFUSE_RPT4_RESERVED3_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_5.*/ -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) -#define EFUSE_KEY_PURPOSE_5_V 0xF -#define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_4.*/ -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) -#define EFUSE_KEY_PURPOSE_4_V 0xF -#define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_3.*/ -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) -#define EFUSE_KEY_PURPOSE_3_V 0xF -#define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The value of KEY_PURPOSE_2.*/ -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) -#define EFUSE_KEY_PURPOSE_2_V 0xF -#define EFUSE_KEY_PURPOSE_2_S 0 - -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C) -/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1 0x00000003 -#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) -#define EFUSE_RPT4_RESERVED1_V 0x3 -#define EFUSE_RPT4_RESERVED1_S 30 -/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: The value of SECURE_VERSION.*/ -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) -#define EFUSE_SECURE_VERSION_V 0xFFFF -#define EFUSE_SECURE_VERSION_S 14 -/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The value of FORCE_SEND_RESUME.*/ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_S 13 -/* EFUSE_RPT4_RESERVED7 : RO ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED7 0x0000001F -#define EFUSE_RPT4_RESERVED7_M ((EFUSE_RPT4_RESERVED7_V)<<(EFUSE_RPT4_RESERVED7_S)) -#define EFUSE_RPT4_RESERVED7_V 0x1F -#define EFUSE_RPT4_RESERVED7_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: The value of UART_PRINT_CONTROL.*/ -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) -#define EFUSE_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/* EFUSE_RPT4_RESERVED8 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_V 0x1 -#define EFUSE_RPT4_RESERVED8_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The value of DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The value of DIS_DIRECT_BOOT.*/ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The value of DIS_DOWNLOAD_MODE.*/ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 - -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) -#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) -/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the low 32 bits of MAC address.*/ -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) -#define EFUSE_MAC_0_V 0xFFFFFFFF -#define EFUSE_MAC_0_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) -/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: Stores the zeroth part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) -#define EFUSE_SPI_PAD_CONF_0_V 0xFFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 -/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Stores the high 16 bits of MAC address.*/ -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) -#define EFUSE_MAC_1_V 0xFFFF -#define EFUSE_MAC_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04C) -/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Stores the fist 8 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_0 0x000000FF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0xFF -#define EFUSE_SYS_DATA_PART0_0_S 25 -/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: Package version 0:ESP32-H4 */ -#define EFUSE_PKG_VERSION 0x00000007 -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0x7 -#define EFUSE_PKG_VERSION_S 21 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: WAFER version 0:A */ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 - -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) -/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05C) -/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 - -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 - -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 - -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 - -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06C) -/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 - -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 - -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 - -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of the first part of system data.*/ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07C) -/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF -#define EFUSE_USR_DATA0_S 0 - -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) -/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF -#define EFUSE_USR_DATA1_S 0 - -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) -/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF -#define EFUSE_USR_DATA2_S 0 - -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) -/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF -#define EFUSE_USR_DATA3_S 0 - -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08C) -/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF -#define EFUSE_USR_DATA4_S 0 - -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) -/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF -#define EFUSE_USR_DATA5_S 0 - -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) -/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) -/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09C) -/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_S 0 - -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0A0) -/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_S 0 - -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0A4) -/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_S 0 - -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0A8) -/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_S 0 - -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0AC) -/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_S 0 - -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0B0) -/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_S 0 - -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0B4) -/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_S 0 - -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0B8) -/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY0.*/ -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_S 0 - -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0BC) -/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_S 0 - -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0C0) -/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_S 0 - -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0C4) -/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_S 0 - -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0C8) -/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_S 0 - -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0CC) -/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_S 0 - -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0D0) -/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_S 0 - -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0D4) -/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_S 0 - -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0D8) -/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY1.*/ -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_S 0 - -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0DC) -/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_S 0 - -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0E0) -/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_S 0 - -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0E4) -/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_S 0 - -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0E8) -/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_S 0 - -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0EC) -/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_S 0 - -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0F0) -/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_S 0 - -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0F4) -/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_S 0 - -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0F8) -/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY2.*/ -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_S 0 - -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0FC) -/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_S 0 - -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_S 0 - -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_S 0 - -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_S 0 - -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10C) -/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_S 0 - -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_S 0 - -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_S 0 - -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY3.*/ -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_S 0 - -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11C) -/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_S 0 - -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_S 0 - -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_S 0 - -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_S 0 - -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12C) -/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_S 0 - -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_S 0 - -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_S 0 - -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY4.*/ -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_S 0 - -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13C) -/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the zeroth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_S 0 - -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the first 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_S 0 - -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the second 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_S 0 - -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the third 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_S 0 - -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14C) -/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fourth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_S 0 - -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fifth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_S 0 - -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the sixth 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_S 0 - -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the seventh 32 bits of KEY5.*/ -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_S 0 - -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15C) -/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_S 0 - -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_S 0 - -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_S 0 - -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_S 0 - -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16C) -/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_S 0 - -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_S 0 - -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_S 0 - -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_S 0 - -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17C) -/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S)) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x3 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 -/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: If POWERGLITCH_EN is 1 then it indicates a programming error.*/ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_M (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x1 -#define EFUSE_POWERGLITCH_EN_ERR_S 29 -/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ -/*description: If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S)) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x3 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 -/* EFUSE_VDD_SPI_AS_GPIO_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ -#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x1 -#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) -#define EFUSE_USB_DREFL_ERR_V 0x3 -#define EFUSE_USB_DREFL_ERR_S 23 -/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) -#define EFUSE_USB_DREFH_ERR_V 0x3 -#define EFUSE_USB_DREFH_ERR_S 21 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S)) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x7 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x1 -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: If DIS_TWAI is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_V 0x1 -#define EFUSE_DIS_TWAI_ERR_S 14 -/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Reserved..*/ -#define EFUSE_RPT4_RESERVED6_ERR (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED6_ERR_S 13 -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x1 -#define EFUSE_DIS_USB_DEVICE_ERR_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: If DIS_USB_JTAG is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x1 -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_DIS_ICACHE_ERR_S 8 -/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Reserved*/ -#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED5_ERR_S 7 -/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) -#define EFUSE_RD_DIS_ERR_V 0x7F -#define EFUSE_RD_DIS_ERR_S 0 - -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFF -#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) -#define EFUSE_RPT4_RESERVED2_ERR_V 0xFFFF -#define EFUSE_RPT4_RESERVED2_ERR_S 0 - -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) -#define EFUSE_FLASH_TPUW_ERR_V 0xF -#define EFUSE_FLASH_TPUW_ERR_S 28 -/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x3F -#define EFUSE_RPT4_RESERVED0_ERR_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED3_ERR 0x0000000F -#define EFUSE_RPT4_RESERVED3_ERR_M ((EFUSE_RPT4_RESERVED3_ERR_V)<<(EFUSE_RPT4_RESERVED3_ERR_S)) -#define EFUSE_RPT4_RESERVED3_ERR_V 0xF -#define EFUSE_RPT4_RESERVED3_ERR_S 16 -/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 - -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED1_ERR 0x00000003 -#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S)) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x3 -#define EFUSE_RPT4_RESERVED1_ERR_S 30 -/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */ -/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) -#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF -#define EFUSE_SECURE_VERSION_ERR_S 14 -/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/* EFUSE_RPT4_RESERVED7_ERR : RO ;bitpos:[12:8] ;default: 5'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED7_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED7_ERR_M ((EFUSE_RPT4_RESERVED7_ERR_V)<<(EFUSE_RPT4_RESERVED7_ERR_S)) -#define EFUSE_RPT4_RESERVED7_ERR_V 0x1F -#define EFUSE_RPT4_RESERVED7_ERR_S 8 -/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/* EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: If DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/* EFUSE_RPT4_RESERVED8_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED8_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_M (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_V 0x1 -#define EFUSE_RPT4_RESERVED8_ERR_S 3 -/* EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: If DIS_USB_SERIAL_JTAG_ROM_PRINT is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x1 -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: If DIS_DIRECT_BOOT_ERR is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1 -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 - -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C) -/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Reserved.*/ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) -#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_S 0 - -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1C0) -/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (BIT(31)) -#define EFUSE_KEY4_FAIL_V 0x1 -#define EFUSE_KEY4_FAIL_S 31 -/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) -#define EFUSE_KEY4_ERR_NUM_V 0x7 -#define EFUSE_KEY4_ERR_NUM_S 28 -/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (BIT(27)) -#define EFUSE_KEY3_FAIL_V 0x1 -#define EFUSE_KEY3_FAIL_S 27 -/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) -#define EFUSE_KEY3_ERR_NUM_V 0x7 -#define EFUSE_KEY3_ERR_NUM_S 24 -/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (BIT(23)) -#define EFUSE_KEY2_FAIL_V 0x1 -#define EFUSE_KEY2_FAIL_S 23 -/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) -#define EFUSE_KEY2_ERR_NUM_V 0x7 -#define EFUSE_KEY2_ERR_NUM_S 20 -/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (BIT(19)) -#define EFUSE_KEY1_FAIL_V 0x1 -#define EFUSE_KEY1_FAIL_S 19 -/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) -#define EFUSE_KEY1_ERR_NUM_V 0x7 -#define EFUSE_KEY1_ERR_NUM_S 16 -/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of key$n is reliable 1: - Means that programming key$n failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (BIT(15)) -#define EFUSE_KEY0_FAIL_V 0x1 -#define EFUSE_KEY0_FAIL_S 15 -/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) -#define EFUSE_KEY0_ERR_NUM_V 0x7 -#define EFUSE_KEY0_ERR_NUM_S 12 -/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the user data is reliable 1: Means - that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_USR_DATA_FAIL_V 0x1 -#define EFUSE_USR_DATA_FAIL_S 11 -/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) -#define EFUSE_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part1 is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_V 0x1 -#define EFUSE_SYS_PART1_FAIL_S 7 -/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) -#define EFUSE_SYS_PART1_NUM_V 0x7 -#define EFUSE_SYS_PART1_NUM_S 4 -/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 - -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1C4) -/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of system part2 is reliable - 1: Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_V 0x1 -#define EFUSE_SYS_PART2_FAIL_S 7 -/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 0: Means no failure and that the data of KEY5 is reliable 1: - Means that programming user data failed and the number of error bytes is over 6.*/ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (BIT(3)) -#define EFUSE_KEY5_FAIL_V 0x1 -#define EFUSE_KEY5_FAIL_S 3 -/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: The value of this signal means the number of error bytes.*/ -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) -#define EFUSE_KEY5_ERR_NUM_V 0x7 -#define EFUSE_KEY5_ERR_NUM_S 0 - -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1C8) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit and force to enable clock signal of eFuse memory.*/ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into working mode.*/ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (BIT(2)) -#define EFUSE_MEM_FORCE_PU_V 0x1 -#define EFUSE_MEM_FORCE_PU_S 2 -/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 -#define EFUSE_MEM_CLK_FORCE_ON_S 1 -/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (BIT(0)) -#define EFUSE_MEM_FORCE_PD_V 0x1 -#define EFUSE_MEM_FORCE_PD_S 0 - -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xFFFF -#define EFUSE_OP_CODE_S 0 - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1D0) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ -/*description: Indicates the number of error bits during programming BLOCK0.*/ -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) -#define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 10 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_IS_SW.*/ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The value of OTP_PGENB_SW.*/ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (BIT(8)) -#define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 8 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The value of OTP_CSB_SW.*/ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (BIT(7)) -#define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 7 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The value of OTP_STROBE_SW.*/ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (BIT(6)) -#define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 6 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The value of OTP_VDDQ_C_SYNC2.*/ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The value of OTP_LOAD_SW.*/ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (BIT(4)) -#define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 4 -/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: Indicates the state of the eFuse state machine.*/ -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0xF -#define EFUSE_STATE_S 0 - -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1D4) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ -/*description: The serial number of the block to be programmed. Value 0-10 corresponds - to block number 0-10 respectively.*/ -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) -#define EFUSE_BLK_NUM_V 0xF -#define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to send programming command.*/ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to send read command.*/ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 -#define EFUSE_READ_CMD_S 0 - -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1D8) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 -#define EFUSE_READ_DONE_INT_RAW_S 0 - -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1DC) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 -#define EFUSE_READ_DONE_INT_ST_S 0 - -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1E0) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 -#define EFUSE_READ_DONE_INT_ENA_S 0 - -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1E4) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear signal for pgm_done interrupt.*/ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear signal for read_done interrupt.*/ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 -#define EFUSE_READ_DONE_INT_CLR_S 0 - -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1E8) -/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Reduces the power supply of the programming voltage.*/ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (BIT(17)) -#define EFUSE_OE_CLR_V 0x1 -#define EFUSE_OE_CLR_S 17 -/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ -/*description: Controls the rising period of the programming voltage.*/ -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) -#define EFUSE_DAC_NUM_V 0xFF -#define EFUSE_DAC_NUM_S 9 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Don't care.*/ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ -/*description: Controls the division factor of the rising clock of the programming voltage.*/ -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xFF -#define EFUSE_DAC_CLK_DIV_S 0 - -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1EC) -/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: Configures the initial read time of eFuse.*/ -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) -#define EFUSE_READ_INIT_NUM_V 0xFF -#define EFUSE_READ_INIT_NUM_S 24 - -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F0) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ -/*description: Configures the power up time for VDDQ.*/ -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) -#define EFUSE_PWR_ON_NUM_V 0xFFFF -#define EFUSE_PWR_ON_NUM_S 8 - -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F4) -/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ -/*description: Configures the power outage time for VDDQ.*/ -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) -#define EFUSE_PWR_OFF_NUM_V 0xFFFF -#define EFUSE_PWR_OFF_NUM_S 0 - -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007200 ; */ -/*description: Stores eFuse version.*/ -#define EFUSE_DATE 0x0FFFFFFF -#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xFFFFFFF -#define EFUSE_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_EFUSE_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/efuse_struct.h b/components/soc/esp32h4/include/rev1/soc/efuse_struct.h deleted file mode 100644 index c729d198f8..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/efuse_struct.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_EFUSE_STRUCT_H_ -#define _SOC_EFUSE_STRUCT_H_ -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/ - union { - struct { - uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/ - uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/ - uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ - uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/ - uint32_t dis_usb_device: 1; /*Set this bit to disable usb device.*/ - uint32_t dis_force_download: 1; /*Set this bit to disable the function that forces chip into download mode.*/ - uint32_t dis_usb: 1; /*Set this bit to disable USB function.*/ - uint32_t dis_twai: 1; /*Set this bit to disable TWAI function.*/ - uint32_t jtag_sel_enable: 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ - uint32_t soft_dis_jtag: 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ - uint32_t dis_pad_jtag: 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ - uint32_t dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ - uint32_t usb_drefh: 2; /*Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.*/ - uint32_t usb_drefl: 2; /*Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.*/ - uint32_t usb_exchg_pins: 1; /*Set this bit to exchange USB D+ and D- pins.*/ - uint32_t vdd_spi_as_gpio: 1; /*Set this bit to vdd spi pin function as gpio.*/ - uint32_t btlc_gpio_enable: 2; /*Enable btlc gpio.*/ - uint32_t powerglitch_en: 1; /*Set this bit to enable power glitch function.*/ - uint32_t power_glitch_dsense: 2; /*Sample delay configuration of power glitch.*/ - }; - uint32_t val; - } pgm_data1; - union { - struct { - uint32_t rpt4_reserved2: 16; /*Reserved (used for four backups method).*/ - uint32_t wat_delay_sel: 2; /*Selects RTC watchdog timeout threshold in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t spi_boot_crypt_cnt: 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t secure_boot_key_revoke0: 1; /*Set this bit to enable revoking first secure boot key.*/ - uint32_t secure_boot_key_revoke1: 1; /*Set this bit to enable revoking second secure boot key.*/ - uint32_t secure_boot_key_revoke2: 1; /*Set this bit to enable revoking third secure boot key.*/ - uint32_t key_purpose_0: 4; /*Purpose of Key0.*/ - uint32_t key_purpose_1: 4; /*Purpose of Key1.*/ - }; - uint32_t val; - } pgm_data2; - union { - struct { - uint32_t key_purpose_2: 4; /*Purpose of Key2.*/ - uint32_t key_purpose_3: 4; /*Purpose of Key3.*/ - uint32_t key_purpose_4: 4; /*Purpose of Key4.*/ - uint32_t key_purpose_5: 4; /*Purpose of Key5.*/ - uint32_t rpt4_reserved3: 4; /*Reserved (used for four backups method).*/ - uint32_t secure_boot_en: 1; /*Set this bit to enable secure boot.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ - uint32_t rpt4_reserved0: 6; /*Reserved (used for four backups method).*/ - uint32_t flash_tpuw: 4; /*Configures flash waiting time after power-up in unit of ms. If the value is less than 15 the waiting time is the configurable value*/ - }; - uint32_t val; - } pgm_data3; - union { - struct { - uint32_t dis_download_mode: 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ - uint32_t dis_direct_boot: 1; /*Set this bit to disable direct boot.*/ - uint32_t dis_usb_serial_jtag_rom_print: 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ - uint32_t rpt4_reserved8: 1; /*Reserved (used for four backups method).*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download mode through USB-Serial-JTAG.*/ - uint32_t enable_security_download: 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t uart_print_control: 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ - uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/ - uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ - uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/ - }; - uint32_t val; - } pgm_data4; - union { - struct { - uint32_t rpt4_reserved4:24; /*Reserved (used for four backups method).*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } pgm_data5; - uint32_t pgm_data6; /*Register 6 that stores data to be programmed.*/ - uint32_t pgm_data7; /*Register 7 that stores data to be programmed.*/ - uint32_t pgm_check_value0; /*Register 0 that stores the RS code to be programmed.*/ - uint32_t pgm_check_value1; /*Register 1 that stores the RS code to be programmed.*/ - uint32_t pgm_check_value2; /*Register 2 that stores the RS code to be programmed.*/ - uint32_t rd_wr_dis; /*BLOCK0 data register $n.*/ - union { - struct { - uint32_t rd_dis: 7; /*The value of RD_DIS.*/ - uint32_t rpt4_reserved5: 1; /*Reserved*/ - uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/ - uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/ - uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/ - uint32_t dis_usb_device: 1; /*The value of DIS_USB_DEVICE.*/ - uint32_t dis_force_download: 1; /*The value of DIS_FORCE_DOWNLOAD.*/ - uint32_t dis_usb: 1; /*The value of DIS_USB.*/ - uint32_t dis_twai: 1; /*The value of DIS_TWAI.*/ - uint32_t jtag_sel_enable: 1; /*The value of JTAG_SEL_ENABLE.*/ - uint32_t soft_dis_jtag: 3; /*The value of SOFT_DIS_JTAG.*/ - uint32_t dis_pad_jtag: 1; /*The value of DIS_PAD_JTAG.*/ - uint32_t dis_download_manual_encrypt: 1; /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ - uint32_t usb_drefh: 2; /*The value of USB_DREFH.*/ - uint32_t usb_drefl: 2; /*The value of USB_DREFL.*/ - uint32_t usb_exchg_pins: 1; /*The value of USB_EXCHG_PINS.*/ - uint32_t vdd_spi_as_gpio: 1; /*The value of VDD_SPI_AS_GPIO.*/ - uint32_t btlc_gpio_enable: 2; /*The value of BTLC_GPIO_ENABLE.*/ - uint32_t powerglitch_en: 1; /*The value of POWERGLITCH_EN.*/ - uint32_t power_glitch_dsense: 2; /*The value of POWER_GLITCH_DSENSE.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t rpt4_reserved2: 16; /*Reserved.*/ - uint32_t wdt_delay_sel: 2; /*The value of WDT_DELAY_SEL.*/ - uint32_t spi_boot_crypt_cnt: 3; /*The value of SPI_BOOT_CRYPT_CNT.*/ - uint32_t secure_boot_key_revoke0: 1; /*The value of SECURE_BOOT_KEY_REVOKE0.*/ - uint32_t secure_boot_key_revoke1: 1; /*The value of SECURE_BOOT_KEY_REVOKE1.*/ - uint32_t secure_boot_key_revoke2: 1; /*The value of SECURE_BOOT_KEY_REVOKE2.*/ - uint32_t key_purpose_0: 4; /*The value of KEY_PURPOSE_0.*/ - uint32_t key_purpose_1: 4; /*The value of KEY_PURPOSE_1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t key_purpose_2: 4; /*The value of KEY_PURPOSE_2.*/ - uint32_t key_purpose_3: 4; /*The value of KEY_PURPOSE_3.*/ - uint32_t key_purpose_4: 4; /*The value of KEY_PURPOSE_4.*/ - uint32_t key_purpose_5: 4; /*The value of KEY_PURPOSE_5.*/ - uint32_t rpt4_reserved3: 4; /*Reserved.*/ - uint32_t secure_boot_en: 1; /*The value of SECURE_BOOT_EN.*/ - uint32_t secure_boot_aggressive_revoke: 1; /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ - uint32_t rpt4_reserved0: 6; /*Reserved.*/ - uint32_t flash_tpuw: 4; /*The value of FLASH_TPUW.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t dis_download_mode: 1; /*The value of DIS_DOWNLOAD_MODE.*/ - uint32_t dis_direct_boot: 1; /*The value of DIS_DIRECT_BOOT.*/ - uint32_t dis_usb_serial_jtag_rom_print: 1; /*The value of DIS_USB_SERIAL_JTAG_ROM_PRINT.*/ - uint32_t rpt4_reserved8: 1; /*Reserved.*/ - uint32_t dis_usb_serial_jtag_download_mode: 1; /*The value of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.*/ - uint32_t enable_security_download: 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/ - uint32_t uart_print_control: 2; /*The value of UART_PRINT_CONTROL.*/ - uint32_t rpt4_reserved7: 5; /*Reserved.*/ - uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/ - uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/ - uint32_t rpt4_reserved1: 2; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t rpt4_reserved4:24; /*Reserved.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - union { - struct { - uint32_t mac_0; - }; - uint32_t val; - } rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t spi_pad_conf_0:16; /*Stores the zeroth part of SPI_PAD_CONF.*/ - }; - uint32_t val; - } rd_mac_spi_sys_1; - uint32_t rd_mac_spi_sys_2; /*BLOCK1 data register $n.*/ - union { - struct { - uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t wafer_version: 3; - uint32_t pkg_version: 3; - uint32_t sys_data_part0_0: 8; /*Stores the fist 14 bits of the zeroth part of system data.*/ - }; - uint32_t val; - } rd_mac_spi_sys_3; - uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ - uint32_t rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/ - uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_usr_data0; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data1; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data2; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data3; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data4; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data5; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data6; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_usr_data7; /*Register $n of BLOCK3 (user).*/ - uint32_t rd_key0_data0; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data1; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data2; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data3; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data4; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data5; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data6; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key0_data7; /*Register $n of BLOCK4 (KEY0).*/ - uint32_t rd_key1_data0; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data1; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data2; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data3; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data4; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data5; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data6; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key1_data7; /*Register $n of BLOCK5 (KEY1).*/ - uint32_t rd_key2_data0; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data1; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data2; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data3; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data4; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data5; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data6; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key2_data7; /*Register $n of BLOCK6 (KEY2).*/ - uint32_t rd_key3_data0; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data1; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data2; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data3; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data4; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data5; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data6; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key3_data7; /*Register $n of BLOCK7 (KEY3).*/ - uint32_t rd_key4_data0; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data1; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data2; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data3; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data4; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data5; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data6; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key4_data7; /*Register $n of BLOCK8 (KEY4).*/ - uint32_t rd_key5_data0; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data1; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data2; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data3; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data4; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data5; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data6; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_key5_data7; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_sys_part2_data0; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data1; /*Register $n of BLOCK9 (KEY5).*/ - uint32_t rd_sys_part2_data2; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data3; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data4; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data5; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data6; /*Register $n of BLOCK10 (system).*/ - uint32_t rd_sys_part2_data7; /*Register $n of BLOCK10 (system).*/ - union { - struct { - uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved5_err: 1; /*If RPT4_RESERVED5 is 1 then it indicates a programming error.*/ - uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/ - uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ - uint32_t dis_usb_device_err: 1; /*If DIS_USB_DEVICE is 1 then it indicates a programming error.*/ - uint32_t dis_force_download_err: 1; /*If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ - uint32_t dis_usb_err: 1; /*If DIS_USB is 1 then it indicates a programming error.*/ - uint32_t dis_twai_err: 1; /*If DIS_TWAI is 1 then it indicates a programming error.*/ - uint32_t jtag_sel_enable_err: 1; /*If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/ - uint32_t soft_dis_jtag_err: 3; /*If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_pad_jtag_err: 1; /*If DIS_PAD_JTAG is 1 then it indicates a programming error.*/ - uint32_t dis_download_manual_encrypt_err: 1; /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ - uint32_t usb_drefh_err: 2; /*If any bit in USB_DREFH is 1 then it indicates a programming error.*/ - uint32_t usb_drefl_err: 2; /*If any bit in USB_DREFL is 1 then it indicates a programming error.*/ - uint32_t usb_exchg_pins_err: 1; /*If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ - uint32_t vdd_spi_as_gpio_err: 1; /*If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/ - uint32_t btlc_gpio_enable_err: 2; /*If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/ - uint32_t powerglitch_en_err: 1; /*If POWERGLITCH_EN is 1 then it indicates a programming error.*/ - uint32_t power_glitch_dsense_err: 2; /*If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t rpt4_reserved2_err: 16; /*Reserved.*/ - uint32_t wdt_delay_sel_err: 2; /*If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ - uint32_t spi_boot_crypt_cnt_err: 3; /*If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke0_err: 1; /*If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke1_err: 1; /*If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ - uint32_t secure_boot_key_revoke2_err: 1; /*If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_0_err: 4; /*If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_1_err: 4; /*If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t key_purpose_2_err: 4; /*If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_3_err: 4; /*If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_4_err: 4; /*If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ - uint32_t key_purpose_5_err: 4; /*If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved3_err: 4; /*Reserved.*/ - uint32_t secure_boot_en_err: 1; /*If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ - uint32_t secure_boot_aggressive_revoke_err: 1; /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved0_err: 6; /*Reserved.*/ - uint32_t flash_tpuw_err: 4; /*If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t dis_download_mode_err: 1; /*If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ - uint32_t dis_direct_boot_err: 1; /*If DIS_DIRECT_BOOT is 1 then it indicates a programming error.*/ - uint32_t dis_usb_serial_jtag_rom_print_err: 1; /*If DIS_USB_SERIAL_JTAG_ROM_PRINT is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved8_err: 1; /*Reserved.*/ - uint32_t dis_usb_serial_jtag_download_mode_err: 1; /*If DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ - uint32_t enable_security_download_err: 1; /*If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ - uint32_t uart_print_control_err: 2; /*If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved7_err: 5; /*Reserved*/ - uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ - uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ - uint32_t rpt4_reserved1_err: 2; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t rpt4_reserved4_err:24; /*Reserved.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t sys_part2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t reserved8: 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3: 13; /*Reserved.*/ - uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17: 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16:16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ - uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ - uint32_t reserved6: 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ - uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reserved0: 24; /*Configures the setup time of read operation.*/ - uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - union { - struct { - uint32_t reserved0: 8; /*Configures the setup time of programming operation.*/ - uint32_t pwr_on_num:16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num:16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; - uint32_t reserved_1f8; - union { - struct { - uint32_t date: 28; /*Stores eFuse version.*/ - uint32_t reserved28: 4; /*Reserved.*/ - }; - uint32_t val; - } date; -} efuse_dev_t; -extern efuse_dev_t EFUSE; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_EFUSE_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/gpio_reg.h b/components/soc/esp32h4/include/rev1/soc/gpio_reg.h deleted file mode 100644 index d5d7b74f61..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/gpio_reg.h +++ /dev/null @@ -1,8173 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_GPIO_REG_H_ -#define _SOC_GPIO_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define GPIO_PIN_CONFIG_MSB 12 -#define GPIO_PIN_CONFIG_LSB 11 -#define GPIO_PIN_CONFIG_MASK 0x00001800 -#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) -#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) - -#define GPIO_WAKEUP_ENABLE 1 -#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) -#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 -#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) -#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) - -#define GPIO_PIN_INT_TYPE_MASK 0x380 -#define GPIO_PIN_INT_TYPE_MSB 9 -#define GPIO_PIN_INT_TYPE_LSB 7 -#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) - -#define GPIO_PAD_DRIVER_ENABLE 1 -#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) -#define GPIO_PIN_PAD_DRIVER_MSB 2 -#define GPIO_PIN_PAD_DRIVER_LSB 2 -#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 -#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) -#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) - -/** GPIO_BT_SELECT_REG register - * GPIO bit select register - */ -#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) -/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; - * GPIO bit select register - */ -#define GPIO_BT_SEL 0xFFFFFFFFU -#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) -#define GPIO_BT_SEL_V 0xFFFFFFFFU -#define GPIO_BT_SEL_S 0 - -/** GPIO_OUT_REG register - * GPIO output register for GPIO0-31 - */ -#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/** GPIO_OUT_DATA_ORIG : R/W/WS/WC; bitpos: [31:0]; default: 0; - * GPIO output register for GPIO0-31 - */ -#define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU -#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) -#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU -#define GPIO_OUT_DATA_ORIG_S 0 - -/** GPIO_OUT_W1TS_REG register - * GPIO output set register for GPIO0-31 - */ -#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; - * GPIO output set register for GPIO0-31 - */ -#define GPIO_OUT_W1TS 0xFFFFFFFFU -#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) -#define GPIO_OUT_W1TS_V 0xFFFFFFFFU -#define GPIO_OUT_W1TS_S 0 - -/** GPIO_OUT_W1TC_REG register - * GPIO output clear register for GPIO0-31 - */ -#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) -/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; - * GPIO output clear register for GPIO0-31 - */ -#define GPIO_OUT_W1TC 0xFFFFFFFFU -#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) -#define GPIO_OUT_W1TC_V 0xFFFFFFFFU -#define GPIO_OUT_W1TC_S 0 - -/** GPIO_OUT1_REG register - * GPIO output register for GPIO32-44 - */ -#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) -/** GPIO_OUT1_DATA_ORIG : R/W/WS/WC; bitpos: [12:0]; default: 0; - * GPIO output register for GPIO32-44 - */ -#define GPIO_OUT1_DATA_ORIG 0x00001FFFU -#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) -#define GPIO_OUT1_DATA_ORIG_V 0x00001FFFU -#define GPIO_OUT1_DATA_ORIG_S 0 - -/** GPIO_OUT1_W1TS_REG register - * GPIO output set register for GPIO32-44 - */ -#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) -/** GPIO_OUT1_W1TS : WT; bitpos: [12:0]; default: 0; - * GPIO output set register for GPIO32-44 - */ -#define GPIO_OUT1_W1TS 0x00001FFFU -#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) -#define GPIO_OUT1_W1TS_V 0x00001FFFU -#define GPIO_OUT1_W1TS_S 0 - -/** GPIO_OUT1_W1TC_REG register - * GPIO output clear register for GPIO32-44 - */ -#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) -/** GPIO_OUT1_W1TC : WT; bitpos: [12:0]; default: 0; - * GPIO output clear register for GPIO32-44 - */ -#define GPIO_OUT1_W1TC 0x00001FFFU -#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) -#define GPIO_OUT1_W1TC_V 0x00001FFFU -#define GPIO_OUT1_W1TC_S 0 - -/** GPIO_SDIO_SELECT_REG register - * GPIO sdio select register - */ -#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) -/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; - * GPIO sdio select register - */ -#define GPIO_SDIO_SEL 0x000000FFU -#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) -#define GPIO_SDIO_SEL_V 0x000000FFU -#define GPIO_SDIO_SEL_S 0 - -/** GPIO_ENABLE_REG register - * GPIO output enable register for GPIO0-31 - */ -#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) -/** GPIO_ENABLE_DATA : R/W/SS; bitpos: [31:0]; default: 0; - * GPIO output enable register for GPIO0-31 - */ -#define GPIO_ENABLE_DATA 0xFFFFFFFFU -#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) -#define GPIO_ENABLE_DATA_V 0xFFFFFFFFU -#define GPIO_ENABLE_DATA_S 0 - -/** GPIO_ENABLE_W1TS_REG register - * GPIO output enable set register for GPIO0-31 - */ -#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) -/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; - * GPIO output enable set register for GPIO0-31 - */ -#define GPIO_ENABLE_W1TS 0xFFFFFFFFU -#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) -#define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU -#define GPIO_ENABLE_W1TS_S 0 - -/** GPIO_ENABLE_W1TC_REG register - * GPIO output enable clear register for GPIO0-31 - */ -#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) -/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; - * GPIO output enable clear register for GPIO0-31 - */ -#define GPIO_ENABLE_W1TC 0xFFFFFFFFU -#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) -#define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU -#define GPIO_ENABLE_W1TC_S 0 - -/** GPIO_ENABLE1_REG register - * GPIO output enable register for GPIO32-44 - */ -#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c) -/** GPIO_ENABLE1_DATA : R/W/SS; bitpos: [12:0]; default: 0; - * GPIO output enable register for GPIO32-44 - */ -#define GPIO_ENABLE1_DATA 0x00001FFFU -#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) -#define GPIO_ENABLE1_DATA_V 0x00001FFFU -#define GPIO_ENABLE1_DATA_S 0 - -/** GPIO_ENABLE1_W1TS_REG register - * GPIO output enable set register for GPIO32-44 - */ -#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) -/** GPIO_ENABLE1_W1TS : WT; bitpos: [12:0]; default: 0; - * GPIO output enable set register for GPIO32-44 - */ -#define GPIO_ENABLE1_W1TS 0x00001FFFU -#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) -#define GPIO_ENABLE1_W1TS_V 0x00001FFFU -#define GPIO_ENABLE1_W1TS_S 0 - -/** GPIO_ENABLE1_W1TC_REG register - * GPIO output enable clear register for GPIO32-44 - */ -#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) -/** GPIO_ENABLE1_W1TC : WT; bitpos: [12:0]; default: 0; - * GPIO output enable clear register for GPIO32-44 - */ -#define GPIO_ENABLE1_W1TC 0x00001FFFU -#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) -#define GPIO_ENABLE1_W1TC_V 0x00001FFFU -#define GPIO_ENABLE1_W1TC_S 0 - -/** GPIO_STRAP_REG register - * pad strapping register - */ -#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) -/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; - * pad strapping register - */ -#define GPIO_STRAPPING 0x0000FFFFU -#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) -#define GPIO_STRAPPING_V 0x0000FFFFU -#define GPIO_STRAPPING_S 0 - -/** GPIO_IN_REG register - * GPIO input register for GPIO0-31 - */ -#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) -/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; - * GPIO input register for GPIO0-31 - */ -#define GPIO_IN_DATA_NEXT 0xFFFFFFFFU -#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) -#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU -#define GPIO_IN_DATA_NEXT_S 0 - -/** GPIO_IN1_REG register - * GPIO input register for GPIO32-44 - */ -#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) -/** GPIO_IN1_DATA_NEXT : RO; bitpos: [12:0]; default: 0; - * GPIO input register for GPIO32-44 - */ -#define GPIO_IN1_DATA_NEXT 0x00001FFFU -#define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) -#define GPIO_IN1_DATA_NEXT_V 0x00001FFFU -#define GPIO_IN1_DATA_NEXT_S 0 - -/** GPIO_STATUS_REG register - * GPIO interrupt status register for GPIO0-31 - */ -#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) -/** GPIO_STATUS_INTERRUPT : R/W/SS; bitpos: [31:0]; default: 0; - * GPIO interrupt status register for GPIO0-31 - */ -#define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU -#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) -#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU -#define GPIO_STATUS_INTERRUPT_S 0 - -/** GPIO_STATUS_W1TS_REG register - * GPIO interrupt status set register for GPIO0-31 - */ -#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) -/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; - * GPIO interrupt status set register for GPIO0-31 - */ -#define GPIO_STATUS_W1TS 0xFFFFFFFFU -#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) -#define GPIO_STATUS_W1TS_V 0xFFFFFFFFU -#define GPIO_STATUS_W1TS_S 0 - -/** GPIO_STATUS_W1TC_REG register - * GPIO interrupt status clear register for GPIO0-31 - */ -#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) -/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; - * GPIO interrupt status clear register for GPIO0-31 - */ -#define GPIO_STATUS_W1TC 0xFFFFFFFFU -#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) -#define GPIO_STATUS_W1TC_V 0xFFFFFFFFU -#define GPIO_STATUS_W1TC_S 0 - -/** GPIO_STATUS1_REG register - * GPIO interrupt status register for GPIO32-44 - */ -#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) -/** GPIO_STATUS1_INTERRUPT : R/W/SS; bitpos: [12:0]; default: 0; - * GPIO interrupt status register for GPIO32-44 - */ -#define GPIO_STATUS1_INTERRUPT 0x00001FFFU -#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) -#define GPIO_STATUS1_INTERRUPT_V 0x00001FFFU -#define GPIO_STATUS1_INTERRUPT_S 0 - -/** GPIO_STATUS1_W1TS_REG register - * GPIO interrupt status set register for GPIO32-44 - */ -#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) -/** GPIO_STATUS1_W1TS : WT; bitpos: [12:0]; default: 0; - * GPIO interrupt status set register for GPIO32-44 - */ -#define GPIO_STATUS1_W1TS 0x00001FFFU -#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) -#define GPIO_STATUS1_W1TS_V 0x00001FFFU -#define GPIO_STATUS1_W1TS_S 0 - -/** GPIO_STATUS1_W1TC_REG register - * GPIO interrupt status clear register for GPIO32-44 - */ -#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) -/** GPIO_STATUS1_W1TC : WT; bitpos: [12:0]; default: 0; - * GPIO interrupt status clear register for GPIO32-44 - */ -#define GPIO_STATUS1_W1TC 0x00001FFFU -#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) -#define GPIO_STATUS1_W1TC_V 0x00001FFFU -#define GPIO_STATUS1_W1TC_S 0 - -/** GPIO_PCPU_INT_REG register - * GPIO PRO_CPU interrupt status register for GPIO0-31 - */ -#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) -/** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; - * GPIO PRO_CPU interrupt status register for GPIO0-31 - */ -#define GPIO_PROCPU_INT 0xFFFFFFFFU -#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) -#define GPIO_PROCPU_INT_V 0xFFFFFFFFU -#define GPIO_PROCPU_INT_S 0 - -/** GPIO_PCPU_NMI_INT_REG register - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 - */ -#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) -/** GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 - */ -#define GPIO_PROCPU_NMI_INT 0xFFFFFFFFU -#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) -#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFFU -#define GPIO_PROCPU_NMI_INT_S 0 - -/** GPIO_CPUSDIO_INT_REG register - * GPIO CPUSDIO interrupt status register for GPIO0-31 - */ -#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) -/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; - * GPIO CPUSDIO interrupt status register for GPIO0-31 - */ -#define GPIO_SDIO_INT 0xFFFFFFFFU -#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) -#define GPIO_SDIO_INT_V 0xFFFFFFFFU -#define GPIO_SDIO_INT_S 0 - -/** GPIO_PCPU_INT1_REG register - * GPIO PRO_CPU interrupt status register for GPIO32-44 - */ -#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) -/** GPIO_PROCPU_INT1 : RO; bitpos: [12:0]; default: 0; - * GPIO PRO_CPU interrupt status register for GPIO32-44 - */ -#define GPIO_PROCPU_INT1 0x00001FFFU -#define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) -#define GPIO_PROCPU_INT1_V 0x00001FFFU -#define GPIO_PROCPU_INT1_S 0 - -/** GPIO_PCPU_NMI_INT1_REG register - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 - */ -#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6c) -/** GPIO_PROCPU_NMI_INT1 : RO; bitpos: [12:0]; default: 0; - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 - */ -#define GPIO_PROCPU_NMI_INT1 0x00001FFFU -#define GPIO_PROCPU_NMI_INT1_M (GPIO_PROCPU_NMI_INT1_V << GPIO_PROCPU_NMI_INT1_S) -#define GPIO_PROCPU_NMI_INT1_V 0x00001FFFU -#define GPIO_PROCPU_NMI_INT1_S 0 - -/** GPIO_CPUSDIO_INT1_REG register - * GPIO CPUSDIO interrupt status register for GPIO32-44 - */ -#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) -/** GPIO_SDIO_INT1 : RO; bitpos: [12:0]; default: 0; - * GPIO CPUSDIO interrupt status register for GPIO32-44 - */ -#define GPIO_SDIO_INT1 0x00001FFFU -#define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) -#define GPIO_SDIO_INT1_V 0x00001FFFU -#define GPIO_SDIO_INT1_S 0 - -/** GPIO_PIN0_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) -/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) -#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN0_SYNC2_BYPASS_S 0 -/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) -#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN0_PAD_DRIVER_S 2 -/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) -#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN0_SYNC1_BYPASS_S 3 -/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN0_INT_TYPE 0x00000007U -#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) -#define GPIO_PIN0_INT_TYPE_V 0x00000007U -#define GPIO_PIN0_INT_TYPE_S 7 -/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) -#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN0_WAKEUP_ENABLE_S 10 -/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN0_CONFIG 0x00000003U -#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) -#define GPIO_PIN0_CONFIG_V 0x00000003U -#define GPIO_PIN0_CONFIG_S 11 -/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN0_INT_ENA 0x0000001FU -#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) -#define GPIO_PIN0_INT_ENA_V 0x0000001FU -#define GPIO_PIN0_INT_ENA_S 13 - -/** GPIO_PIN1_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) -/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) -#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN1_SYNC2_BYPASS_S 0 -/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) -#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN1_PAD_DRIVER_S 2 -/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) -#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN1_SYNC1_BYPASS_S 3 -/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN1_INT_TYPE 0x00000007U -#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) -#define GPIO_PIN1_INT_TYPE_V 0x00000007U -#define GPIO_PIN1_INT_TYPE_S 7 -/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) -#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN1_WAKEUP_ENABLE_S 10 -/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN1_CONFIG 0x00000003U -#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) -#define GPIO_PIN1_CONFIG_V 0x00000003U -#define GPIO_PIN1_CONFIG_S 11 -/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN1_INT_ENA 0x0000001FU -#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) -#define GPIO_PIN1_INT_ENA_V 0x0000001FU -#define GPIO_PIN1_INT_ENA_S 13 - -/** GPIO_PIN2_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) -/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) -#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN2_SYNC2_BYPASS_S 0 -/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) -#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN2_PAD_DRIVER_S 2 -/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) -#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN2_SYNC1_BYPASS_S 3 -/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN2_INT_TYPE 0x00000007U -#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) -#define GPIO_PIN2_INT_TYPE_V 0x00000007U -#define GPIO_PIN2_INT_TYPE_S 7 -/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) -#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN2_WAKEUP_ENABLE_S 10 -/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN2_CONFIG 0x00000003U -#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) -#define GPIO_PIN2_CONFIG_V 0x00000003U -#define GPIO_PIN2_CONFIG_S 11 -/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN2_INT_ENA 0x0000001FU -#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) -#define GPIO_PIN2_INT_ENA_V 0x0000001FU -#define GPIO_PIN2_INT_ENA_S 13 - -/** GPIO_PIN3_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) -/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) -#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN3_SYNC2_BYPASS_S 0 -/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) -#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN3_PAD_DRIVER_S 2 -/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) -#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN3_SYNC1_BYPASS_S 3 -/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN3_INT_TYPE 0x00000007U -#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) -#define GPIO_PIN3_INT_TYPE_V 0x00000007U -#define GPIO_PIN3_INT_TYPE_S 7 -/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) -#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN3_WAKEUP_ENABLE_S 10 -/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN3_CONFIG 0x00000003U -#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) -#define GPIO_PIN3_CONFIG_V 0x00000003U -#define GPIO_PIN3_CONFIG_S 11 -/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN3_INT_ENA 0x0000001FU -#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) -#define GPIO_PIN3_INT_ENA_V 0x0000001FU -#define GPIO_PIN3_INT_ENA_S 13 - -/** GPIO_PIN4_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) -/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) -#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN4_SYNC2_BYPASS_S 0 -/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) -#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN4_PAD_DRIVER_S 2 -/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) -#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN4_SYNC1_BYPASS_S 3 -/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN4_INT_TYPE 0x00000007U -#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) -#define GPIO_PIN4_INT_TYPE_V 0x00000007U -#define GPIO_PIN4_INT_TYPE_S 7 -/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) -#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN4_WAKEUP_ENABLE_S 10 -/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN4_CONFIG 0x00000003U -#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) -#define GPIO_PIN4_CONFIG_V 0x00000003U -#define GPIO_PIN4_CONFIG_S 11 -/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN4_INT_ENA 0x0000001FU -#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) -#define GPIO_PIN4_INT_ENA_V 0x0000001FU -#define GPIO_PIN4_INT_ENA_S 13 - -/** GPIO_PIN5_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) -/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) -#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN5_SYNC2_BYPASS_S 0 -/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) -#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN5_PAD_DRIVER_S 2 -/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) -#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN5_SYNC1_BYPASS_S 3 -/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN5_INT_TYPE 0x00000007U -#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) -#define GPIO_PIN5_INT_TYPE_V 0x00000007U -#define GPIO_PIN5_INT_TYPE_S 7 -/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) -#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN5_WAKEUP_ENABLE_S 10 -/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN5_CONFIG 0x00000003U -#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) -#define GPIO_PIN5_CONFIG_V 0x00000003U -#define GPIO_PIN5_CONFIG_S 11 -/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN5_INT_ENA 0x0000001FU -#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) -#define GPIO_PIN5_INT_ENA_V 0x0000001FU -#define GPIO_PIN5_INT_ENA_S 13 - -/** GPIO_PIN6_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) -/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) -#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN6_SYNC2_BYPASS_S 0 -/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) -#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN6_PAD_DRIVER_S 2 -/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) -#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN6_SYNC1_BYPASS_S 3 -/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN6_INT_TYPE 0x00000007U -#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) -#define GPIO_PIN6_INT_TYPE_V 0x00000007U -#define GPIO_PIN6_INT_TYPE_S 7 -/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) -#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN6_WAKEUP_ENABLE_S 10 -/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN6_CONFIG 0x00000003U -#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) -#define GPIO_PIN6_CONFIG_V 0x00000003U -#define GPIO_PIN6_CONFIG_S 11 -/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN6_INT_ENA 0x0000001FU -#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) -#define GPIO_PIN6_INT_ENA_V 0x0000001FU -#define GPIO_PIN6_INT_ENA_S 13 - -/** GPIO_PIN7_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) -/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) -#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN7_SYNC2_BYPASS_S 0 -/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) -#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN7_PAD_DRIVER_S 2 -/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) -#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN7_SYNC1_BYPASS_S 3 -/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN7_INT_TYPE 0x00000007U -#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) -#define GPIO_PIN7_INT_TYPE_V 0x00000007U -#define GPIO_PIN7_INT_TYPE_S 7 -/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) -#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN7_WAKEUP_ENABLE_S 10 -/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN7_CONFIG 0x00000003U -#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) -#define GPIO_PIN7_CONFIG_V 0x00000003U -#define GPIO_PIN7_CONFIG_S 11 -/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN7_INT_ENA 0x0000001FU -#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) -#define GPIO_PIN7_INT_ENA_V 0x0000001FU -#define GPIO_PIN7_INT_ENA_S 13 - -/** GPIO_PIN8_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) -/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) -#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN8_SYNC2_BYPASS_S 0 -/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) -#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN8_PAD_DRIVER_S 2 -/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) -#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN8_SYNC1_BYPASS_S 3 -/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN8_INT_TYPE 0x00000007U -#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) -#define GPIO_PIN8_INT_TYPE_V 0x00000007U -#define GPIO_PIN8_INT_TYPE_S 7 -/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) -#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN8_WAKEUP_ENABLE_S 10 -/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN8_CONFIG 0x00000003U -#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) -#define GPIO_PIN8_CONFIG_V 0x00000003U -#define GPIO_PIN8_CONFIG_S 11 -/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN8_INT_ENA 0x0000001FU -#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) -#define GPIO_PIN8_INT_ENA_V 0x0000001FU -#define GPIO_PIN8_INT_ENA_S 13 - -/** GPIO_PIN9_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) -/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) -#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN9_SYNC2_BYPASS_S 0 -/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) -#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN9_PAD_DRIVER_S 2 -/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) -#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN9_SYNC1_BYPASS_S 3 -/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN9_INT_TYPE 0x00000007U -#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) -#define GPIO_PIN9_INT_TYPE_V 0x00000007U -#define GPIO_PIN9_INT_TYPE_S 7 -/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) -#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN9_WAKEUP_ENABLE_S 10 -/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN9_CONFIG 0x00000003U -#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) -#define GPIO_PIN9_CONFIG_V 0x00000003U -#define GPIO_PIN9_CONFIG_S 11 -/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN9_INT_ENA 0x0000001FU -#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) -#define GPIO_PIN9_INT_ENA_V 0x0000001FU -#define GPIO_PIN9_INT_ENA_S 13 - -/** GPIO_PIN10_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) -/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) -#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN10_SYNC2_BYPASS_S 0 -/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) -#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN10_PAD_DRIVER_S 2 -/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) -#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN10_SYNC1_BYPASS_S 3 -/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN10_INT_TYPE 0x00000007U -#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) -#define GPIO_PIN10_INT_TYPE_V 0x00000007U -#define GPIO_PIN10_INT_TYPE_S 7 -/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) -#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN10_WAKEUP_ENABLE_S 10 -/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN10_CONFIG 0x00000003U -#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) -#define GPIO_PIN10_CONFIG_V 0x00000003U -#define GPIO_PIN10_CONFIG_S 11 -/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN10_INT_ENA 0x0000001FU -#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) -#define GPIO_PIN10_INT_ENA_V 0x0000001FU -#define GPIO_PIN10_INT_ENA_S 13 - -/** GPIO_PIN11_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) -/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) -#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN11_SYNC2_BYPASS_S 0 -/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) -#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN11_PAD_DRIVER_S 2 -/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) -#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN11_SYNC1_BYPASS_S 3 -/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN11_INT_TYPE 0x00000007U -#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) -#define GPIO_PIN11_INT_TYPE_V 0x00000007U -#define GPIO_PIN11_INT_TYPE_S 7 -/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) -#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN11_WAKEUP_ENABLE_S 10 -/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN11_CONFIG 0x00000003U -#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) -#define GPIO_PIN11_CONFIG_V 0x00000003U -#define GPIO_PIN11_CONFIG_S 11 -/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN11_INT_ENA 0x0000001FU -#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) -#define GPIO_PIN11_INT_ENA_V 0x0000001FU -#define GPIO_PIN11_INT_ENA_S 13 - -/** GPIO_PIN12_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) -/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) -#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN12_SYNC2_BYPASS_S 0 -/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) -#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN12_PAD_DRIVER_S 2 -/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) -#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN12_SYNC1_BYPASS_S 3 -/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN12_INT_TYPE 0x00000007U -#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) -#define GPIO_PIN12_INT_TYPE_V 0x00000007U -#define GPIO_PIN12_INT_TYPE_S 7 -/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) -#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN12_WAKEUP_ENABLE_S 10 -/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN12_CONFIG 0x00000003U -#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) -#define GPIO_PIN12_CONFIG_V 0x00000003U -#define GPIO_PIN12_CONFIG_S 11 -/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN12_INT_ENA 0x0000001FU -#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) -#define GPIO_PIN12_INT_ENA_V 0x0000001FU -#define GPIO_PIN12_INT_ENA_S 13 - -/** GPIO_PIN13_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) -/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) -#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN13_SYNC2_BYPASS_S 0 -/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) -#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN13_PAD_DRIVER_S 2 -/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) -#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN13_SYNC1_BYPASS_S 3 -/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN13_INT_TYPE 0x00000007U -#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) -#define GPIO_PIN13_INT_TYPE_V 0x00000007U -#define GPIO_PIN13_INT_TYPE_S 7 -/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) -#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN13_WAKEUP_ENABLE_S 10 -/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN13_CONFIG 0x00000003U -#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) -#define GPIO_PIN13_CONFIG_V 0x00000003U -#define GPIO_PIN13_CONFIG_S 11 -/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN13_INT_ENA 0x0000001FU -#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) -#define GPIO_PIN13_INT_ENA_V 0x0000001FU -#define GPIO_PIN13_INT_ENA_S 13 - -/** GPIO_PIN14_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) -/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) -#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN14_SYNC2_BYPASS_S 0 -/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) -#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN14_PAD_DRIVER_S 2 -/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) -#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN14_SYNC1_BYPASS_S 3 -/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN14_INT_TYPE 0x00000007U -#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) -#define GPIO_PIN14_INT_TYPE_V 0x00000007U -#define GPIO_PIN14_INT_TYPE_S 7 -/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) -#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN14_WAKEUP_ENABLE_S 10 -/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN14_CONFIG 0x00000003U -#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) -#define GPIO_PIN14_CONFIG_V 0x00000003U -#define GPIO_PIN14_CONFIG_S 11 -/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN14_INT_ENA 0x0000001FU -#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) -#define GPIO_PIN14_INT_ENA_V 0x0000001FU -#define GPIO_PIN14_INT_ENA_S 13 - -/** GPIO_PIN15_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) -/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) -#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN15_SYNC2_BYPASS_S 0 -/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) -#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN15_PAD_DRIVER_S 2 -/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) -#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN15_SYNC1_BYPASS_S 3 -/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN15_INT_TYPE 0x00000007U -#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) -#define GPIO_PIN15_INT_TYPE_V 0x00000007U -#define GPIO_PIN15_INT_TYPE_S 7 -/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) -#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN15_WAKEUP_ENABLE_S 10 -/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN15_CONFIG 0x00000003U -#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) -#define GPIO_PIN15_CONFIG_V 0x00000003U -#define GPIO_PIN15_CONFIG_S 11 -/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN15_INT_ENA 0x0000001FU -#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) -#define GPIO_PIN15_INT_ENA_V 0x0000001FU -#define GPIO_PIN15_INT_ENA_S 13 - -/** GPIO_PIN16_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) -/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) -#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN16_SYNC2_BYPASS_S 0 -/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) -#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN16_PAD_DRIVER_S 2 -/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) -#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN16_SYNC1_BYPASS_S 3 -/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN16_INT_TYPE 0x00000007U -#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) -#define GPIO_PIN16_INT_TYPE_V 0x00000007U -#define GPIO_PIN16_INT_TYPE_S 7 -/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) -#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN16_WAKEUP_ENABLE_S 10 -/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN16_CONFIG 0x00000003U -#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) -#define GPIO_PIN16_CONFIG_V 0x00000003U -#define GPIO_PIN16_CONFIG_S 11 -/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN16_INT_ENA 0x0000001FU -#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) -#define GPIO_PIN16_INT_ENA_V 0x0000001FU -#define GPIO_PIN16_INT_ENA_S 13 - -/** GPIO_PIN17_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) -/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) -#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN17_SYNC2_BYPASS_S 0 -/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) -#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN17_PAD_DRIVER_S 2 -/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) -#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN17_SYNC1_BYPASS_S 3 -/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN17_INT_TYPE 0x00000007U -#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) -#define GPIO_PIN17_INT_TYPE_V 0x00000007U -#define GPIO_PIN17_INT_TYPE_S 7 -/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) -#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN17_WAKEUP_ENABLE_S 10 -/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN17_CONFIG 0x00000003U -#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) -#define GPIO_PIN17_CONFIG_V 0x00000003U -#define GPIO_PIN17_CONFIG_S 11 -/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN17_INT_ENA 0x0000001FU -#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) -#define GPIO_PIN17_INT_ENA_V 0x0000001FU -#define GPIO_PIN17_INT_ENA_S 13 - -/** GPIO_PIN18_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) -/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) -#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN18_SYNC2_BYPASS_S 0 -/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN18_PAD_DRIVER (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) -#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN18_PAD_DRIVER_S 2 -/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) -#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN18_SYNC1_BYPASS_S 3 -/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN18_INT_TYPE 0x00000007U -#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) -#define GPIO_PIN18_INT_TYPE_V 0x00000007U -#define GPIO_PIN18_INT_TYPE_S 7 -/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) -#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN18_WAKEUP_ENABLE_S 10 -/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN18_CONFIG 0x00000003U -#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) -#define GPIO_PIN18_CONFIG_V 0x00000003U -#define GPIO_PIN18_CONFIG_S 11 -/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN18_INT_ENA 0x0000001FU -#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) -#define GPIO_PIN18_INT_ENA_V 0x0000001FU -#define GPIO_PIN18_INT_ENA_S 13 - -/** GPIO_PIN19_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) -/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) -#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN19_SYNC2_BYPASS_S 0 -/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN19_PAD_DRIVER (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) -#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN19_PAD_DRIVER_S 2 -/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) -#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN19_SYNC1_BYPASS_S 3 -/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN19_INT_TYPE 0x00000007U -#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) -#define GPIO_PIN19_INT_TYPE_V 0x00000007U -#define GPIO_PIN19_INT_TYPE_S 7 -/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) -#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN19_WAKEUP_ENABLE_S 10 -/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN19_CONFIG 0x00000003U -#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) -#define GPIO_PIN19_CONFIG_V 0x00000003U -#define GPIO_PIN19_CONFIG_S 11 -/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN19_INT_ENA 0x0000001FU -#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) -#define GPIO_PIN19_INT_ENA_V 0x0000001FU -#define GPIO_PIN19_INT_ENA_S 13 - -/** GPIO_PIN20_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) -/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) -#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN20_SYNC2_BYPASS_S 0 -/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN20_PAD_DRIVER (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) -#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN20_PAD_DRIVER_S 2 -/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) -#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN20_SYNC1_BYPASS_S 3 -/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN20_INT_TYPE 0x00000007U -#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) -#define GPIO_PIN20_INT_TYPE_V 0x00000007U -#define GPIO_PIN20_INT_TYPE_S 7 -/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) -#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN20_WAKEUP_ENABLE_S 10 -/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN20_CONFIG 0x00000003U -#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) -#define GPIO_PIN20_CONFIG_V 0x00000003U -#define GPIO_PIN20_CONFIG_S 11 -/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN20_INT_ENA 0x0000001FU -#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) -#define GPIO_PIN20_INT_ENA_V 0x0000001FU -#define GPIO_PIN20_INT_ENA_S 13 - -/** GPIO_PIN21_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) -/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) -#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN21_SYNC2_BYPASS_S 0 -/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN21_PAD_DRIVER (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) -#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN21_PAD_DRIVER_S 2 -/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) -#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN21_SYNC1_BYPASS_S 3 -/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN21_INT_TYPE 0x00000007U -#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) -#define GPIO_PIN21_INT_TYPE_V 0x00000007U -#define GPIO_PIN21_INT_TYPE_S 7 -/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) -#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN21_WAKEUP_ENABLE_S 10 -/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN21_CONFIG 0x00000003U -#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) -#define GPIO_PIN21_CONFIG_V 0x00000003U -#define GPIO_PIN21_CONFIG_S 11 -/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN21_INT_ENA 0x0000001FU -#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) -#define GPIO_PIN21_INT_ENA_V 0x0000001FU -#define GPIO_PIN21_INT_ENA_S 13 - -/** GPIO_PIN22_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) -/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) -#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN22_SYNC2_BYPASS_S 0 -/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN22_PAD_DRIVER (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) -#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN22_PAD_DRIVER_S 2 -/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) -#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN22_SYNC1_BYPASS_S 3 -/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN22_INT_TYPE 0x00000007U -#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) -#define GPIO_PIN22_INT_TYPE_V 0x00000007U -#define GPIO_PIN22_INT_TYPE_S 7 -/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) -#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN22_WAKEUP_ENABLE_S 10 -/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN22_CONFIG 0x00000003U -#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) -#define GPIO_PIN22_CONFIG_V 0x00000003U -#define GPIO_PIN22_CONFIG_S 11 -/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN22_INT_ENA 0x0000001FU -#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) -#define GPIO_PIN22_INT_ENA_V 0x0000001FU -#define GPIO_PIN22_INT_ENA_S 13 - -/** GPIO_PIN23_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) -/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) -#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN23_SYNC2_BYPASS_S 0 -/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN23_PAD_DRIVER (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) -#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN23_PAD_DRIVER_S 2 -/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) -#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN23_SYNC1_BYPASS_S 3 -/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN23_INT_TYPE 0x00000007U -#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) -#define GPIO_PIN23_INT_TYPE_V 0x00000007U -#define GPIO_PIN23_INT_TYPE_S 7 -/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) -#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN23_WAKEUP_ENABLE_S 10 -/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN23_CONFIG 0x00000003U -#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) -#define GPIO_PIN23_CONFIG_V 0x00000003U -#define GPIO_PIN23_CONFIG_S 11 -/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN23_INT_ENA 0x0000001FU -#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) -#define GPIO_PIN23_INT_ENA_V 0x0000001FU -#define GPIO_PIN23_INT_ENA_S 13 - -/** GPIO_PIN24_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) -/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) -#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN24_SYNC2_BYPASS_S 0 -/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN24_PAD_DRIVER (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) -#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN24_PAD_DRIVER_S 2 -/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) -#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN24_SYNC1_BYPASS_S 3 -/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN24_INT_TYPE 0x00000007U -#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) -#define GPIO_PIN24_INT_TYPE_V 0x00000007U -#define GPIO_PIN24_INT_TYPE_S 7 -/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) -#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN24_WAKEUP_ENABLE_S 10 -/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN24_CONFIG 0x00000003U -#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) -#define GPIO_PIN24_CONFIG_V 0x00000003U -#define GPIO_PIN24_CONFIG_S 11 -/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN24_INT_ENA 0x0000001FU -#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) -#define GPIO_PIN24_INT_ENA_V 0x0000001FU -#define GPIO_PIN24_INT_ENA_S 13 - -/** GPIO_PIN25_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) -/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) -#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN25_SYNC2_BYPASS_S 0 -/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN25_PAD_DRIVER (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) -#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN25_PAD_DRIVER_S 2 -/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) -#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN25_SYNC1_BYPASS_S 3 -/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN25_INT_TYPE 0x00000007U -#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) -#define GPIO_PIN25_INT_TYPE_V 0x00000007U -#define GPIO_PIN25_INT_TYPE_S 7 -/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) -#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN25_WAKEUP_ENABLE_S 10 -/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN25_CONFIG 0x00000003U -#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) -#define GPIO_PIN25_CONFIG_V 0x00000003U -#define GPIO_PIN25_CONFIG_S 11 -/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN25_INT_ENA 0x0000001FU -#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) -#define GPIO_PIN25_INT_ENA_V 0x0000001FU -#define GPIO_PIN25_INT_ENA_S 13 - -/** GPIO_PIN26_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) -/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) -#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN26_SYNC2_BYPASS_S 0 -/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN26_PAD_DRIVER (BIT(2)) -#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) -#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN26_PAD_DRIVER_S 2 -/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) -#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN26_SYNC1_BYPASS_S 3 -/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN26_INT_TYPE 0x00000007U -#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) -#define GPIO_PIN26_INT_TYPE_V 0x00000007U -#define GPIO_PIN26_INT_TYPE_S 7 -/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) -#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN26_WAKEUP_ENABLE_S 10 -/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN26_CONFIG 0x00000003U -#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) -#define GPIO_PIN26_CONFIG_V 0x00000003U -#define GPIO_PIN26_CONFIG_S 11 -/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN26_INT_ENA 0x0000001FU -#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) -#define GPIO_PIN26_INT_ENA_V 0x0000001FU -#define GPIO_PIN26_INT_ENA_S 13 - -/** GPIO_PIN27_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) -/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) -#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN27_SYNC2_BYPASS_S 0 -/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN27_PAD_DRIVER (BIT(2)) -#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) -#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN27_PAD_DRIVER_S 2 -/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) -#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN27_SYNC1_BYPASS_S 3 -/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN27_INT_TYPE 0x00000007U -#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) -#define GPIO_PIN27_INT_TYPE_V 0x00000007U -#define GPIO_PIN27_INT_TYPE_S 7 -/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) -#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN27_WAKEUP_ENABLE_S 10 -/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN27_CONFIG 0x00000003U -#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) -#define GPIO_PIN27_CONFIG_V 0x00000003U -#define GPIO_PIN27_CONFIG_S 11 -/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN27_INT_ENA 0x0000001FU -#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) -#define GPIO_PIN27_INT_ENA_V 0x0000001FU -#define GPIO_PIN27_INT_ENA_S 13 - -/** GPIO_PIN28_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) -/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) -#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN28_SYNC2_BYPASS_S 0 -/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN28_PAD_DRIVER (BIT(2)) -#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) -#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN28_PAD_DRIVER_S 2 -/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) -#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN28_SYNC1_BYPASS_S 3 -/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN28_INT_TYPE 0x00000007U -#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) -#define GPIO_PIN28_INT_TYPE_V 0x00000007U -#define GPIO_PIN28_INT_TYPE_S 7 -/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) -#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN28_WAKEUP_ENABLE_S 10 -/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN28_CONFIG 0x00000003U -#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) -#define GPIO_PIN28_CONFIG_V 0x00000003U -#define GPIO_PIN28_CONFIG_S 11 -/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN28_INT_ENA 0x0000001FU -#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) -#define GPIO_PIN28_INT_ENA_V 0x0000001FU -#define GPIO_PIN28_INT_ENA_S 13 - -/** GPIO_PIN29_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) -/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) -#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN29_SYNC2_BYPASS_S 0 -/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN29_PAD_DRIVER (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) -#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN29_PAD_DRIVER_S 2 -/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) -#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN29_SYNC1_BYPASS_S 3 -/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN29_INT_TYPE 0x00000007U -#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) -#define GPIO_PIN29_INT_TYPE_V 0x00000007U -#define GPIO_PIN29_INT_TYPE_S 7 -/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) -#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN29_WAKEUP_ENABLE_S 10 -/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN29_CONFIG 0x00000003U -#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) -#define GPIO_PIN29_CONFIG_V 0x00000003U -#define GPIO_PIN29_CONFIG_S 11 -/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN29_INT_ENA 0x0000001FU -#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) -#define GPIO_PIN29_INT_ENA_V 0x0000001FU -#define GPIO_PIN29_INT_ENA_S 13 - -/** GPIO_PIN30_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) -/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) -#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN30_SYNC2_BYPASS_S 0 -/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN30_PAD_DRIVER (BIT(2)) -#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) -#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN30_PAD_DRIVER_S 2 -/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) -#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN30_SYNC1_BYPASS_S 3 -/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN30_INT_TYPE 0x00000007U -#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) -#define GPIO_PIN30_INT_TYPE_V 0x00000007U -#define GPIO_PIN30_INT_TYPE_S 7 -/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) -#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN30_WAKEUP_ENABLE_S 10 -/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN30_CONFIG 0x00000003U -#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) -#define GPIO_PIN30_CONFIG_V 0x00000003U -#define GPIO_PIN30_CONFIG_S 11 -/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN30_INT_ENA 0x0000001FU -#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) -#define GPIO_PIN30_INT_ENA_V 0x0000001FU -#define GPIO_PIN30_INT_ENA_S 13 - -/** GPIO_PIN31_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) -/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) -#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN31_SYNC2_BYPASS_S 0 -/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN31_PAD_DRIVER (BIT(2)) -#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) -#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN31_PAD_DRIVER_S 2 -/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) -#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN31_SYNC1_BYPASS_S 3 -/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN31_INT_TYPE 0x00000007U -#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) -#define GPIO_PIN31_INT_TYPE_V 0x00000007U -#define GPIO_PIN31_INT_TYPE_S 7 -/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) -#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN31_WAKEUP_ENABLE_S 10 -/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN31_CONFIG 0x00000003U -#define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) -#define GPIO_PIN31_CONFIG_V 0x00000003U -#define GPIO_PIN31_CONFIG_S 11 -/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN31_INT_ENA 0x0000001FU -#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) -#define GPIO_PIN31_INT_ENA_V 0x0000001FU -#define GPIO_PIN31_INT_ENA_S 13 - -/** GPIO_PIN32_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4) -/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN32_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) -#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN32_SYNC2_BYPASS_S 0 -/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN32_PAD_DRIVER (BIT(2)) -#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) -#define GPIO_PIN32_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN32_PAD_DRIVER_S 2 -/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN32_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) -#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN32_SYNC1_BYPASS_S 3 -/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN32_INT_TYPE 0x00000007U -#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) -#define GPIO_PIN32_INT_TYPE_V 0x00000007U -#define GPIO_PIN32_INT_TYPE_S 7 -/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) -#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN32_WAKEUP_ENABLE_S 10 -/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN32_CONFIG 0x00000003U -#define GPIO_PIN32_CONFIG_M (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S) -#define GPIO_PIN32_CONFIG_V 0x00000003U -#define GPIO_PIN32_CONFIG_S 11 -/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN32_INT_ENA 0x0000001FU -#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) -#define GPIO_PIN32_INT_ENA_V 0x0000001FU -#define GPIO_PIN32_INT_ENA_S 13 - -/** GPIO_PIN33_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8) -/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN33_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) -#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN33_SYNC2_BYPASS_S 0 -/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN33_PAD_DRIVER (BIT(2)) -#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) -#define GPIO_PIN33_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN33_PAD_DRIVER_S 2 -/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN33_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) -#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN33_SYNC1_BYPASS_S 3 -/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN33_INT_TYPE 0x00000007U -#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) -#define GPIO_PIN33_INT_TYPE_V 0x00000007U -#define GPIO_PIN33_INT_TYPE_S 7 -/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) -#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN33_WAKEUP_ENABLE_S 10 -/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN33_CONFIG 0x00000003U -#define GPIO_PIN33_CONFIG_M (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S) -#define GPIO_PIN33_CONFIG_V 0x00000003U -#define GPIO_PIN33_CONFIG_S 11 -/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN33_INT_ENA 0x0000001FU -#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) -#define GPIO_PIN33_INT_ENA_V 0x0000001FU -#define GPIO_PIN33_INT_ENA_S 13 - -/** GPIO_PIN34_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc) -/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN34_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN34_SYNC2_BYPASS_M (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S) -#define GPIO_PIN34_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN34_SYNC2_BYPASS_S 0 -/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN34_PAD_DRIVER (BIT(2)) -#define GPIO_PIN34_PAD_DRIVER_M (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S) -#define GPIO_PIN34_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN34_PAD_DRIVER_S 2 -/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN34_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN34_SYNC1_BYPASS_M (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S) -#define GPIO_PIN34_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN34_SYNC1_BYPASS_S 3 -/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN34_INT_TYPE 0x00000007U -#define GPIO_PIN34_INT_TYPE_M (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S) -#define GPIO_PIN34_INT_TYPE_V 0x00000007U -#define GPIO_PIN34_INT_TYPE_S 7 -/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN34_WAKEUP_ENABLE_M (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S) -#define GPIO_PIN34_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN34_WAKEUP_ENABLE_S 10 -/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN34_CONFIG 0x00000003U -#define GPIO_PIN34_CONFIG_M (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S) -#define GPIO_PIN34_CONFIG_V 0x00000003U -#define GPIO_PIN34_CONFIG_S 11 -/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN34_INT_ENA 0x0000001FU -#define GPIO_PIN34_INT_ENA_M (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S) -#define GPIO_PIN34_INT_ENA_V 0x0000001FU -#define GPIO_PIN34_INT_ENA_S 13 - -/** GPIO_PIN35_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) -/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN35_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN35_SYNC2_BYPASS_M (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S) -#define GPIO_PIN35_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN35_SYNC2_BYPASS_S 0 -/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN35_PAD_DRIVER (BIT(2)) -#define GPIO_PIN35_PAD_DRIVER_M (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S) -#define GPIO_PIN35_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN35_PAD_DRIVER_S 2 -/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN35_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN35_SYNC1_BYPASS_M (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S) -#define GPIO_PIN35_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN35_SYNC1_BYPASS_S 3 -/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN35_INT_TYPE 0x00000007U -#define GPIO_PIN35_INT_TYPE_M (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S) -#define GPIO_PIN35_INT_TYPE_V 0x00000007U -#define GPIO_PIN35_INT_TYPE_S 7 -/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN35_WAKEUP_ENABLE_M (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S) -#define GPIO_PIN35_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN35_WAKEUP_ENABLE_S 10 -/** GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN35_CONFIG 0x00000003U -#define GPIO_PIN35_CONFIG_M (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S) -#define GPIO_PIN35_CONFIG_V 0x00000003U -#define GPIO_PIN35_CONFIG_S 11 -/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN35_INT_ENA 0x0000001FU -#define GPIO_PIN35_INT_ENA_M (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S) -#define GPIO_PIN35_INT_ENA_V 0x0000001FU -#define GPIO_PIN35_INT_ENA_S 13 - -/** GPIO_PIN36_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) -/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN36_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN36_SYNC2_BYPASS_M (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S) -#define GPIO_PIN36_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN36_SYNC2_BYPASS_S 0 -/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN36_PAD_DRIVER (BIT(2)) -#define GPIO_PIN36_PAD_DRIVER_M (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S) -#define GPIO_PIN36_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN36_PAD_DRIVER_S 2 -/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN36_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN36_SYNC1_BYPASS_M (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S) -#define GPIO_PIN36_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN36_SYNC1_BYPASS_S 3 -/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN36_INT_TYPE 0x00000007U -#define GPIO_PIN36_INT_TYPE_M (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S) -#define GPIO_PIN36_INT_TYPE_V 0x00000007U -#define GPIO_PIN36_INT_TYPE_S 7 -/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN36_WAKEUP_ENABLE_M (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S) -#define GPIO_PIN36_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN36_WAKEUP_ENABLE_S 10 -/** GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN36_CONFIG 0x00000003U -#define GPIO_PIN36_CONFIG_M (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S) -#define GPIO_PIN36_CONFIG_V 0x00000003U -#define GPIO_PIN36_CONFIG_S 11 -/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN36_INT_ENA 0x0000001FU -#define GPIO_PIN36_INT_ENA_M (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S) -#define GPIO_PIN36_INT_ENA_V 0x0000001FU -#define GPIO_PIN36_INT_ENA_S 13 - -/** GPIO_PIN37_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) -/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN37_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN37_SYNC2_BYPASS_M (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S) -#define GPIO_PIN37_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN37_SYNC2_BYPASS_S 0 -/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN37_PAD_DRIVER (BIT(2)) -#define GPIO_PIN37_PAD_DRIVER_M (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S) -#define GPIO_PIN37_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN37_PAD_DRIVER_S 2 -/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN37_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN37_SYNC1_BYPASS_M (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S) -#define GPIO_PIN37_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN37_SYNC1_BYPASS_S 3 -/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN37_INT_TYPE 0x00000007U -#define GPIO_PIN37_INT_TYPE_M (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S) -#define GPIO_PIN37_INT_TYPE_V 0x00000007U -#define GPIO_PIN37_INT_TYPE_S 7 -/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN37_WAKEUP_ENABLE_M (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S) -#define GPIO_PIN37_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN37_WAKEUP_ENABLE_S 10 -/** GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN37_CONFIG 0x00000003U -#define GPIO_PIN37_CONFIG_M (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S) -#define GPIO_PIN37_CONFIG_V 0x00000003U -#define GPIO_PIN37_CONFIG_S 11 -/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN37_INT_ENA 0x0000001FU -#define GPIO_PIN37_INT_ENA_M (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S) -#define GPIO_PIN37_INT_ENA_V 0x0000001FU -#define GPIO_PIN37_INT_ENA_S 13 - -/** GPIO_PIN38_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c) -/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN38_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN38_SYNC2_BYPASS_M (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S) -#define GPIO_PIN38_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN38_SYNC2_BYPASS_S 0 -/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN38_PAD_DRIVER (BIT(2)) -#define GPIO_PIN38_PAD_DRIVER_M (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S) -#define GPIO_PIN38_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN38_PAD_DRIVER_S 2 -/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN38_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN38_SYNC1_BYPASS_M (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S) -#define GPIO_PIN38_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN38_SYNC1_BYPASS_S 3 -/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN38_INT_TYPE 0x00000007U -#define GPIO_PIN38_INT_TYPE_M (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S) -#define GPIO_PIN38_INT_TYPE_V 0x00000007U -#define GPIO_PIN38_INT_TYPE_S 7 -/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN38_WAKEUP_ENABLE_M (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S) -#define GPIO_PIN38_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN38_WAKEUP_ENABLE_S 10 -/** GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN38_CONFIG 0x00000003U -#define GPIO_PIN38_CONFIG_M (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S) -#define GPIO_PIN38_CONFIG_V 0x00000003U -#define GPIO_PIN38_CONFIG_S 11 -/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN38_INT_ENA 0x0000001FU -#define GPIO_PIN38_INT_ENA_M (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S) -#define GPIO_PIN38_INT_ENA_V 0x0000001FU -#define GPIO_PIN38_INT_ENA_S 13 - -/** GPIO_PIN39_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) -/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN39_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN39_SYNC2_BYPASS_M (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S) -#define GPIO_PIN39_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN39_SYNC2_BYPASS_S 0 -/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN39_PAD_DRIVER (BIT(2)) -#define GPIO_PIN39_PAD_DRIVER_M (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S) -#define GPIO_PIN39_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN39_PAD_DRIVER_S 2 -/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN39_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN39_SYNC1_BYPASS_M (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S) -#define GPIO_PIN39_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN39_SYNC1_BYPASS_S 3 -/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN39_INT_TYPE 0x00000007U -#define GPIO_PIN39_INT_TYPE_M (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S) -#define GPIO_PIN39_INT_TYPE_V 0x00000007U -#define GPIO_PIN39_INT_TYPE_S 7 -/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN39_WAKEUP_ENABLE_M (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S) -#define GPIO_PIN39_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN39_WAKEUP_ENABLE_S 10 -/** GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN39_CONFIG 0x00000003U -#define GPIO_PIN39_CONFIG_M (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S) -#define GPIO_PIN39_CONFIG_V 0x00000003U -#define GPIO_PIN39_CONFIG_S 11 -/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN39_INT_ENA 0x0000001FU -#define GPIO_PIN39_INT_ENA_M (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S) -#define GPIO_PIN39_INT_ENA_V 0x0000001FU -#define GPIO_PIN39_INT_ENA_S 13 - -/** GPIO_PIN40_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) -/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN40_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN40_SYNC2_BYPASS_M (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S) -#define GPIO_PIN40_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN40_SYNC2_BYPASS_S 0 -/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN40_PAD_DRIVER (BIT(2)) -#define GPIO_PIN40_PAD_DRIVER_M (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S) -#define GPIO_PIN40_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN40_PAD_DRIVER_S 2 -/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN40_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN40_SYNC1_BYPASS_M (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S) -#define GPIO_PIN40_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN40_SYNC1_BYPASS_S 3 -/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN40_INT_TYPE 0x00000007U -#define GPIO_PIN40_INT_TYPE_M (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S) -#define GPIO_PIN40_INT_TYPE_V 0x00000007U -#define GPIO_PIN40_INT_TYPE_S 7 -/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN40_WAKEUP_ENABLE_M (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S) -#define GPIO_PIN40_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN40_WAKEUP_ENABLE_S 10 -/** GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN40_CONFIG 0x00000003U -#define GPIO_PIN40_CONFIG_M (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S) -#define GPIO_PIN40_CONFIG_V 0x00000003U -#define GPIO_PIN40_CONFIG_S 11 -/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN40_INT_ENA 0x0000001FU -#define GPIO_PIN40_INT_ENA_M (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S) -#define GPIO_PIN40_INT_ENA_V 0x0000001FU -#define GPIO_PIN40_INT_ENA_S 13 - -/** GPIO_PIN41_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) -/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN41_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN41_SYNC2_BYPASS_M (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S) -#define GPIO_PIN41_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN41_SYNC2_BYPASS_S 0 -/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN41_PAD_DRIVER (BIT(2)) -#define GPIO_PIN41_PAD_DRIVER_M (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S) -#define GPIO_PIN41_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN41_PAD_DRIVER_S 2 -/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN41_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN41_SYNC1_BYPASS_M (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S) -#define GPIO_PIN41_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN41_SYNC1_BYPASS_S 3 -/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN41_INT_TYPE 0x00000007U -#define GPIO_PIN41_INT_TYPE_M (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S) -#define GPIO_PIN41_INT_TYPE_V 0x00000007U -#define GPIO_PIN41_INT_TYPE_S 7 -/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN41_WAKEUP_ENABLE_M (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S) -#define GPIO_PIN41_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN41_WAKEUP_ENABLE_S 10 -/** GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN41_CONFIG 0x00000003U -#define GPIO_PIN41_CONFIG_M (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S) -#define GPIO_PIN41_CONFIG_V 0x00000003U -#define GPIO_PIN41_CONFIG_S 11 -/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN41_INT_ENA 0x0000001FU -#define GPIO_PIN41_INT_ENA_M (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S) -#define GPIO_PIN41_INT_ENA_V 0x0000001FU -#define GPIO_PIN41_INT_ENA_S 13 - -/** GPIO_PIN42_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c) -/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN42_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN42_SYNC2_BYPASS_M (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S) -#define GPIO_PIN42_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN42_SYNC2_BYPASS_S 0 -/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN42_PAD_DRIVER (BIT(2)) -#define GPIO_PIN42_PAD_DRIVER_M (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S) -#define GPIO_PIN42_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN42_PAD_DRIVER_S 2 -/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN42_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN42_SYNC1_BYPASS_M (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S) -#define GPIO_PIN42_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN42_SYNC1_BYPASS_S 3 -/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN42_INT_TYPE 0x00000007U -#define GPIO_PIN42_INT_TYPE_M (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S) -#define GPIO_PIN42_INT_TYPE_V 0x00000007U -#define GPIO_PIN42_INT_TYPE_S 7 -/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN42_WAKEUP_ENABLE_M (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S) -#define GPIO_PIN42_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN42_WAKEUP_ENABLE_S 10 -/** GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN42_CONFIG 0x00000003U -#define GPIO_PIN42_CONFIG_M (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S) -#define GPIO_PIN42_CONFIG_V 0x00000003U -#define GPIO_PIN42_CONFIG_S 11 -/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN42_INT_ENA 0x0000001FU -#define GPIO_PIN42_INT_ENA_M (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S) -#define GPIO_PIN42_INT_ENA_V 0x0000001FU -#define GPIO_PIN42_INT_ENA_S 13 - -/** GPIO_PIN43_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) -/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN43_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN43_SYNC2_BYPASS_M (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S) -#define GPIO_PIN43_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN43_SYNC2_BYPASS_S 0 -/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN43_PAD_DRIVER (BIT(2)) -#define GPIO_PIN43_PAD_DRIVER_M (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S) -#define GPIO_PIN43_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN43_PAD_DRIVER_S 2 -/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN43_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN43_SYNC1_BYPASS_M (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S) -#define GPIO_PIN43_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN43_SYNC1_BYPASS_S 3 -/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN43_INT_TYPE 0x00000007U -#define GPIO_PIN43_INT_TYPE_M (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S) -#define GPIO_PIN43_INT_TYPE_V 0x00000007U -#define GPIO_PIN43_INT_TYPE_S 7 -/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN43_WAKEUP_ENABLE_M (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S) -#define GPIO_PIN43_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN43_WAKEUP_ENABLE_S 10 -/** GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN43_CONFIG 0x00000003U -#define GPIO_PIN43_CONFIG_M (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S) -#define GPIO_PIN43_CONFIG_V 0x00000003U -#define GPIO_PIN43_CONFIG_S 11 -/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN43_INT_ENA 0x0000001FU -#define GPIO_PIN43_INT_ENA_M (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S) -#define GPIO_PIN43_INT_ENA_V 0x0000001FU -#define GPIO_PIN43_INT_ENA_S 13 - -/** GPIO_PIN44_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) -/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN44_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN44_SYNC2_BYPASS_M (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S) -#define GPIO_PIN44_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN44_SYNC2_BYPASS_S 0 -/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN44_PAD_DRIVER (BIT(2)) -#define GPIO_PIN44_PAD_DRIVER_M (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S) -#define GPIO_PIN44_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN44_PAD_DRIVER_S 2 -/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN44_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN44_SYNC1_BYPASS_M (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S) -#define GPIO_PIN44_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN44_SYNC1_BYPASS_S 3 -/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN44_INT_TYPE 0x00000007U -#define GPIO_PIN44_INT_TYPE_M (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S) -#define GPIO_PIN44_INT_TYPE_V 0x00000007U -#define GPIO_PIN44_INT_TYPE_S 7 -/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN44_WAKEUP_ENABLE_M (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S) -#define GPIO_PIN44_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN44_WAKEUP_ENABLE_S 10 -/** GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN44_CONFIG 0x00000003U -#define GPIO_PIN44_CONFIG_M (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S) -#define GPIO_PIN44_CONFIG_V 0x00000003U -#define GPIO_PIN44_CONFIG_S 11 -/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN44_INT_ENA 0x0000001FU -#define GPIO_PIN44_INT_ENA_M (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S) -#define GPIO_PIN44_INT_ENA_V 0x0000001FU -#define GPIO_PIN44_INT_ENA_S 13 - -/** GPIO_STATUS_NEXT_REG register - * GPIO interrupt source register for GPIO0-31 - */ -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) -/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; - * GPIO interrupt source register for GPIO0-31 - */ -#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU -#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU -#define GPIO_STATUS_INTERRUPT_NEXT_S 0 - -/** GPIO_STATUS_NEXT1_REG register - * GPIO interrupt source register for GPIO32-44 - */ -#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) -/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [12:0]; default: 0; - * GPIO interrupt source register for GPIO32-44 - */ -#define GPIO_STATUS_INTERRUPT_NEXT1 0x00001FFFU -#define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) -#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x00001FFFU -#define GPIO_STATUS_INTERRUPT_NEXT1_S 0 - -/** GPIO_FUNC0_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) -/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC0_IN_SEL 0x0000003FU -#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) -#define GPIO_FUNC0_IN_SEL_V 0x0000003FU -#define GPIO_FUNC0_IN_SEL_S 0 -/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) -#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_IN_INV_SEL_S 6 -/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG0_IN_SEL (BIT(7)) -#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) -#define GPIO_SIG0_IN_SEL_V 0x00000001U -#define GPIO_SIG0_IN_SEL_S 7 - -/** GPIO_FUNC1_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) -/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC1_IN_SEL 0x0000003FU -#define GPIO_FUNC1_IN_SEL_M (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S) -#define GPIO_FUNC1_IN_SEL_V 0x0000003FU -#define GPIO_FUNC1_IN_SEL_S 0 -/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC1_IN_INV_SEL_M (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S) -#define GPIO_FUNC1_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC1_IN_INV_SEL_S 6 -/** GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG1_IN_SEL (BIT(7)) -#define GPIO_SIG1_IN_SEL_M (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S) -#define GPIO_SIG1_IN_SEL_V 0x00000001U -#define GPIO_SIG1_IN_SEL_S 7 - -/** GPIO_FUNC2_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) -/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC2_IN_SEL 0x0000003FU -#define GPIO_FUNC2_IN_SEL_M (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S) -#define GPIO_FUNC2_IN_SEL_V 0x0000003FU -#define GPIO_FUNC2_IN_SEL_S 0 -/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC2_IN_INV_SEL_M (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S) -#define GPIO_FUNC2_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC2_IN_INV_SEL_S 6 -/** GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG2_IN_SEL (BIT(7)) -#define GPIO_SIG2_IN_SEL_M (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S) -#define GPIO_SIG2_IN_SEL_V 0x00000001U -#define GPIO_SIG2_IN_SEL_S 7 - -/** GPIO_FUNC3_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) -/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC3_IN_SEL 0x0000003FU -#define GPIO_FUNC3_IN_SEL_M (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S) -#define GPIO_FUNC3_IN_SEL_V 0x0000003FU -#define GPIO_FUNC3_IN_SEL_S 0 -/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC3_IN_INV_SEL_M (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S) -#define GPIO_FUNC3_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC3_IN_INV_SEL_S 6 -/** GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG3_IN_SEL (BIT(7)) -#define GPIO_SIG3_IN_SEL_M (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S) -#define GPIO_SIG3_IN_SEL_V 0x00000001U -#define GPIO_SIG3_IN_SEL_S 7 - -/** GPIO_FUNC4_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) -/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC4_IN_SEL 0x0000003FU -#define GPIO_FUNC4_IN_SEL_M (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S) -#define GPIO_FUNC4_IN_SEL_V 0x0000003FU -#define GPIO_FUNC4_IN_SEL_S 0 -/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC4_IN_INV_SEL_M (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S) -#define GPIO_FUNC4_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC4_IN_INV_SEL_S 6 -/** GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG4_IN_SEL (BIT(7)) -#define GPIO_SIG4_IN_SEL_M (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S) -#define GPIO_SIG4_IN_SEL_V 0x00000001U -#define GPIO_SIG4_IN_SEL_S 7 - -/** GPIO_FUNC5_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) -/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC5_IN_SEL 0x0000003FU -#define GPIO_FUNC5_IN_SEL_M (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S) -#define GPIO_FUNC5_IN_SEL_V 0x0000003FU -#define GPIO_FUNC5_IN_SEL_S 0 -/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC5_IN_INV_SEL_M (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S) -#define GPIO_FUNC5_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC5_IN_INV_SEL_S 6 -/** GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG5_IN_SEL (BIT(7)) -#define GPIO_SIG5_IN_SEL_M (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S) -#define GPIO_SIG5_IN_SEL_V 0x00000001U -#define GPIO_SIG5_IN_SEL_S 7 - -/** GPIO_FUNC6_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) -/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC6_IN_SEL 0x0000003FU -#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) -#define GPIO_FUNC6_IN_SEL_V 0x0000003FU -#define GPIO_FUNC6_IN_SEL_S 0 -/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) -#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_IN_INV_SEL_S 6 -/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG6_IN_SEL (BIT(7)) -#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) -#define GPIO_SIG6_IN_SEL_V 0x00000001U -#define GPIO_SIG6_IN_SEL_S 7 - -/** GPIO_FUNC7_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) -/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC7_IN_SEL 0x0000003FU -#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) -#define GPIO_FUNC7_IN_SEL_V 0x0000003FU -#define GPIO_FUNC7_IN_SEL_S 0 -/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) -#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_IN_INV_SEL_S 6 -/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG7_IN_SEL (BIT(7)) -#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) -#define GPIO_SIG7_IN_SEL_V 0x00000001U -#define GPIO_SIG7_IN_SEL_S 7 - -/** GPIO_FUNC8_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) -/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC8_IN_SEL 0x0000003FU -#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) -#define GPIO_FUNC8_IN_SEL_V 0x0000003FU -#define GPIO_FUNC8_IN_SEL_S 0 -/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) -#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_IN_INV_SEL_S 6 -/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG8_IN_SEL (BIT(7)) -#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) -#define GPIO_SIG8_IN_SEL_V 0x00000001U -#define GPIO_SIG8_IN_SEL_S 7 - -/** GPIO_FUNC9_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) -/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC9_IN_SEL 0x0000003FU -#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) -#define GPIO_FUNC9_IN_SEL_V 0x0000003FU -#define GPIO_FUNC9_IN_SEL_S 0 -/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) -#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_IN_INV_SEL_S 6 -/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG9_IN_SEL (BIT(7)) -#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) -#define GPIO_SIG9_IN_SEL_V 0x00000001U -#define GPIO_SIG9_IN_SEL_S 7 - -/** GPIO_FUNC10_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) -/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC10_IN_SEL 0x0000003FU -#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) -#define GPIO_FUNC10_IN_SEL_V 0x0000003FU -#define GPIO_FUNC10_IN_SEL_S 0 -/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) -#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_IN_INV_SEL_S 6 -/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG10_IN_SEL (BIT(7)) -#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) -#define GPIO_SIG10_IN_SEL_V 0x00000001U -#define GPIO_SIG10_IN_SEL_S 7 - -/** GPIO_FUNC11_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) -/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC11_IN_SEL 0x0000003FU -#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) -#define GPIO_FUNC11_IN_SEL_V 0x0000003FU -#define GPIO_FUNC11_IN_SEL_S 0 -/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) -#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_IN_INV_SEL_S 6 -/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG11_IN_SEL (BIT(7)) -#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) -#define GPIO_SIG11_IN_SEL_V 0x00000001U -#define GPIO_SIG11_IN_SEL_S 7 - -/** GPIO_FUNC12_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) -/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC12_IN_SEL 0x0000003FU -#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) -#define GPIO_FUNC12_IN_SEL_V 0x0000003FU -#define GPIO_FUNC12_IN_SEL_S 0 -/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) -#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_IN_INV_SEL_S 6 -/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG12_IN_SEL (BIT(7)) -#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) -#define GPIO_SIG12_IN_SEL_V 0x00000001U -#define GPIO_SIG12_IN_SEL_S 7 - -/** GPIO_FUNC13_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) -/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC13_IN_SEL 0x0000003FU -#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) -#define GPIO_FUNC13_IN_SEL_V 0x0000003FU -#define GPIO_FUNC13_IN_SEL_S 0 -/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) -#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_IN_INV_SEL_S 6 -/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG13_IN_SEL (BIT(7)) -#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) -#define GPIO_SIG13_IN_SEL_V 0x00000001U -#define GPIO_SIG13_IN_SEL_S 7 - -/** GPIO_FUNC14_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) -/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC14_IN_SEL 0x0000003FU -#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) -#define GPIO_FUNC14_IN_SEL_V 0x0000003FU -#define GPIO_FUNC14_IN_SEL_S 0 -/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) -#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_IN_INV_SEL_S 6 -/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG14_IN_SEL (BIT(7)) -#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) -#define GPIO_SIG14_IN_SEL_V 0x00000001U -#define GPIO_SIG14_IN_SEL_S 7 - -/** GPIO_FUNC15_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) -/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC15_IN_SEL 0x0000003FU -#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) -#define GPIO_FUNC15_IN_SEL_V 0x0000003FU -#define GPIO_FUNC15_IN_SEL_S 0 -/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) -#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_IN_INV_SEL_S 6 -/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG15_IN_SEL (BIT(7)) -#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) -#define GPIO_SIG15_IN_SEL_V 0x00000001U -#define GPIO_SIG15_IN_SEL_S 7 - -/** GPIO_FUNC16_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) -/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC16_IN_SEL 0x0000003FU -#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) -#define GPIO_FUNC16_IN_SEL_V 0x0000003FU -#define GPIO_FUNC16_IN_SEL_S 0 -/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) -#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_IN_INV_SEL_S 6 -/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG16_IN_SEL (BIT(7)) -#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) -#define GPIO_SIG16_IN_SEL_V 0x00000001U -#define GPIO_SIG16_IN_SEL_S 7 - -/** GPIO_FUNC17_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) -/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC17_IN_SEL 0x0000003FU -#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) -#define GPIO_FUNC17_IN_SEL_V 0x0000003FU -#define GPIO_FUNC17_IN_SEL_S 0 -/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) -#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_IN_INV_SEL_S 6 -/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG17_IN_SEL (BIT(7)) -#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) -#define GPIO_SIG17_IN_SEL_V 0x00000001U -#define GPIO_SIG17_IN_SEL_S 7 - -/** GPIO_FUNC18_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) -/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC18_IN_SEL 0x0000003FU -#define GPIO_FUNC18_IN_SEL_M (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S) -#define GPIO_FUNC18_IN_SEL_V 0x0000003FU -#define GPIO_FUNC18_IN_SEL_S 0 -/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC18_IN_INV_SEL_M (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S) -#define GPIO_FUNC18_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC18_IN_INV_SEL_S 6 -/** GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG18_IN_SEL (BIT(7)) -#define GPIO_SIG18_IN_SEL_M (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S) -#define GPIO_SIG18_IN_SEL_V 0x00000001U -#define GPIO_SIG18_IN_SEL_S 7 - -/** GPIO_FUNC19_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) -/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC19_IN_SEL 0x0000003FU -#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) -#define GPIO_FUNC19_IN_SEL_V 0x0000003FU -#define GPIO_FUNC19_IN_SEL_S 0 -/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) -#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC19_IN_INV_SEL_S 6 -/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG19_IN_SEL (BIT(7)) -#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) -#define GPIO_SIG19_IN_SEL_V 0x00000001U -#define GPIO_SIG19_IN_SEL_S 7 - -/** GPIO_FUNC20_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) -/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC20_IN_SEL 0x0000003FU -#define GPIO_FUNC20_IN_SEL_M (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S) -#define GPIO_FUNC20_IN_SEL_V 0x0000003FU -#define GPIO_FUNC20_IN_SEL_S 0 -/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC20_IN_INV_SEL_M (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S) -#define GPIO_FUNC20_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC20_IN_INV_SEL_S 6 -/** GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG20_IN_SEL (BIT(7)) -#define GPIO_SIG20_IN_SEL_M (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S) -#define GPIO_SIG20_IN_SEL_V 0x00000001U -#define GPIO_SIG20_IN_SEL_S 7 - -/** GPIO_FUNC21_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) -/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC21_IN_SEL 0x0000003FU -#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) -#define GPIO_FUNC21_IN_SEL_V 0x0000003FU -#define GPIO_FUNC21_IN_SEL_S 0 -/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) -#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC21_IN_INV_SEL_S 6 -/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG21_IN_SEL (BIT(7)) -#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) -#define GPIO_SIG21_IN_SEL_V 0x00000001U -#define GPIO_SIG21_IN_SEL_S 7 - -/** GPIO_FUNC22_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) -/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC22_IN_SEL 0x0000003FU -#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) -#define GPIO_FUNC22_IN_SEL_V 0x0000003FU -#define GPIO_FUNC22_IN_SEL_S 0 -/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) -#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC22_IN_INV_SEL_S 6 -/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG22_IN_SEL (BIT(7)) -#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) -#define GPIO_SIG22_IN_SEL_V 0x00000001U -#define GPIO_SIG22_IN_SEL_S 7 - -/** GPIO_FUNC23_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) -/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC23_IN_SEL 0x0000003FU -#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) -#define GPIO_FUNC23_IN_SEL_V 0x0000003FU -#define GPIO_FUNC23_IN_SEL_S 0 -/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) -#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC23_IN_INV_SEL_S 6 -/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG23_IN_SEL (BIT(7)) -#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) -#define GPIO_SIG23_IN_SEL_V 0x00000001U -#define GPIO_SIG23_IN_SEL_S 7 - -/** GPIO_FUNC24_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) -/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC24_IN_SEL 0x0000003FU -#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) -#define GPIO_FUNC24_IN_SEL_V 0x0000003FU -#define GPIO_FUNC24_IN_SEL_S 0 -/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) -#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC24_IN_INV_SEL_S 6 -/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG24_IN_SEL (BIT(7)) -#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) -#define GPIO_SIG24_IN_SEL_V 0x00000001U -#define GPIO_SIG24_IN_SEL_S 7 - -/** GPIO_FUNC25_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) -/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC25_IN_SEL 0x0000003FU -#define GPIO_FUNC25_IN_SEL_M (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S) -#define GPIO_FUNC25_IN_SEL_V 0x0000003FU -#define GPIO_FUNC25_IN_SEL_S 0 -/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC25_IN_INV_SEL_M (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S) -#define GPIO_FUNC25_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC25_IN_INV_SEL_S 6 -/** GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG25_IN_SEL (BIT(7)) -#define GPIO_SIG25_IN_SEL_M (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S) -#define GPIO_SIG25_IN_SEL_V 0x00000001U -#define GPIO_SIG25_IN_SEL_S 7 - -/** GPIO_FUNC26_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) -/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC26_IN_SEL 0x0000003FU -#define GPIO_FUNC26_IN_SEL_M (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S) -#define GPIO_FUNC26_IN_SEL_V 0x0000003FU -#define GPIO_FUNC26_IN_SEL_S 0 -/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC26_IN_INV_SEL_M (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S) -#define GPIO_FUNC26_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC26_IN_INV_SEL_S 6 -/** GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG26_IN_SEL (BIT(7)) -#define GPIO_SIG26_IN_SEL_M (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S) -#define GPIO_SIG26_IN_SEL_V 0x00000001U -#define GPIO_SIG26_IN_SEL_S 7 - -/** GPIO_FUNC27_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) -/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC27_IN_SEL 0x0000003FU -#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) -#define GPIO_FUNC27_IN_SEL_V 0x0000003FU -#define GPIO_FUNC27_IN_SEL_S 0 -/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) -#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_IN_INV_SEL_S 6 -/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG27_IN_SEL (BIT(7)) -#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) -#define GPIO_SIG27_IN_SEL_V 0x00000001U -#define GPIO_SIG27_IN_SEL_S 7 - -/** GPIO_FUNC28_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) -/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC28_IN_SEL 0x0000003FU -#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) -#define GPIO_FUNC28_IN_SEL_V 0x0000003FU -#define GPIO_FUNC28_IN_SEL_S 0 -/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) -#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_IN_INV_SEL_S 6 -/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG28_IN_SEL (BIT(7)) -#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) -#define GPIO_SIG28_IN_SEL_V 0x00000001U -#define GPIO_SIG28_IN_SEL_S 7 - -/** GPIO_FUNC29_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) -/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC29_IN_SEL 0x0000003FU -#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) -#define GPIO_FUNC29_IN_SEL_V 0x0000003FU -#define GPIO_FUNC29_IN_SEL_S 0 -/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) -#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_IN_INV_SEL_S 6 -/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG29_IN_SEL (BIT(7)) -#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) -#define GPIO_SIG29_IN_SEL_V 0x00000001U -#define GPIO_SIG29_IN_SEL_S 7 - -/** GPIO_FUNC30_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) -/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC30_IN_SEL 0x0000003FU -#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) -#define GPIO_FUNC30_IN_SEL_V 0x0000003FU -#define GPIO_FUNC30_IN_SEL_S 0 -/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) -#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_IN_INV_SEL_S 6 -/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG30_IN_SEL (BIT(7)) -#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) -#define GPIO_SIG30_IN_SEL_V 0x00000001U -#define GPIO_SIG30_IN_SEL_S 7 - -/** GPIO_FUNC31_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) -/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC31_IN_SEL 0x0000003FU -#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) -#define GPIO_FUNC31_IN_SEL_V 0x0000003FU -#define GPIO_FUNC31_IN_SEL_S 0 -/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) -#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_IN_INV_SEL_S 6 -/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG31_IN_SEL (BIT(7)) -#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) -#define GPIO_SIG31_IN_SEL_V 0x00000001U -#define GPIO_SIG31_IN_SEL_S 7 - -/** GPIO_FUNC32_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) -/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC32_IN_SEL 0x0000003FU -#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) -#define GPIO_FUNC32_IN_SEL_V 0x0000003FU -#define GPIO_FUNC32_IN_SEL_S 0 -/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) -#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_IN_INV_SEL_S 6 -/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG32_IN_SEL (BIT(7)) -#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) -#define GPIO_SIG32_IN_SEL_V 0x00000001U -#define GPIO_SIG32_IN_SEL_S 7 - -/** GPIO_FUNC33_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) -/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC33_IN_SEL 0x0000003FU -#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) -#define GPIO_FUNC33_IN_SEL_V 0x0000003FU -#define GPIO_FUNC33_IN_SEL_S 0 -/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) -#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC33_IN_INV_SEL_S 6 -/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG33_IN_SEL (BIT(7)) -#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) -#define GPIO_SIG33_IN_SEL_V 0x00000001U -#define GPIO_SIG33_IN_SEL_S 7 - -/** GPIO_FUNC34_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) -/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC34_IN_SEL 0x0000003FU -#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) -#define GPIO_FUNC34_IN_SEL_V 0x0000003FU -#define GPIO_FUNC34_IN_SEL_S 0 -/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) -#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC34_IN_INV_SEL_S 6 -/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG34_IN_SEL (BIT(7)) -#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) -#define GPIO_SIG34_IN_SEL_V 0x00000001U -#define GPIO_SIG34_IN_SEL_S 7 - -/** GPIO_FUNC35_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) -/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC35_IN_SEL 0x0000003FU -#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) -#define GPIO_FUNC35_IN_SEL_V 0x0000003FU -#define GPIO_FUNC35_IN_SEL_S 0 -/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) -#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC35_IN_INV_SEL_S 6 -/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG35_IN_SEL (BIT(7)) -#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) -#define GPIO_SIG35_IN_SEL_V 0x00000001U -#define GPIO_SIG35_IN_SEL_S 7 - -/** GPIO_FUNC36_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) -/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC36_IN_SEL 0x0000003FU -#define GPIO_FUNC36_IN_SEL_M (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S) -#define GPIO_FUNC36_IN_SEL_V 0x0000003FU -#define GPIO_FUNC36_IN_SEL_S 0 -/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC36_IN_INV_SEL_M (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S) -#define GPIO_FUNC36_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC36_IN_INV_SEL_S 6 -/** GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG36_IN_SEL (BIT(7)) -#define GPIO_SIG36_IN_SEL_M (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S) -#define GPIO_SIG36_IN_SEL_V 0x00000001U -#define GPIO_SIG36_IN_SEL_S 7 - -/** GPIO_FUNC37_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) -/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC37_IN_SEL 0x0000003FU -#define GPIO_FUNC37_IN_SEL_M (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S) -#define GPIO_FUNC37_IN_SEL_V 0x0000003FU -#define GPIO_FUNC37_IN_SEL_S 0 -/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC37_IN_INV_SEL_M (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S) -#define GPIO_FUNC37_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC37_IN_INV_SEL_S 6 -/** GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG37_IN_SEL (BIT(7)) -#define GPIO_SIG37_IN_SEL_M (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S) -#define GPIO_SIG37_IN_SEL_V 0x00000001U -#define GPIO_SIG37_IN_SEL_S 7 - -/** GPIO_FUNC38_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) -/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC38_IN_SEL 0x0000003FU -#define GPIO_FUNC38_IN_SEL_M (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S) -#define GPIO_FUNC38_IN_SEL_V 0x0000003FU -#define GPIO_FUNC38_IN_SEL_S 0 -/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC38_IN_INV_SEL_M (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S) -#define GPIO_FUNC38_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC38_IN_INV_SEL_S 6 -/** GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG38_IN_SEL (BIT(7)) -#define GPIO_SIG38_IN_SEL_M (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S) -#define GPIO_SIG38_IN_SEL_V 0x00000001U -#define GPIO_SIG38_IN_SEL_S 7 - -/** GPIO_FUNC39_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) -/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC39_IN_SEL 0x0000003FU -#define GPIO_FUNC39_IN_SEL_M (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S) -#define GPIO_FUNC39_IN_SEL_V 0x0000003FU -#define GPIO_FUNC39_IN_SEL_S 0 -/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC39_IN_INV_SEL_M (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S) -#define GPIO_FUNC39_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC39_IN_INV_SEL_S 6 -/** GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG39_IN_SEL (BIT(7)) -#define GPIO_SIG39_IN_SEL_M (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S) -#define GPIO_SIG39_IN_SEL_V 0x00000001U -#define GPIO_SIG39_IN_SEL_S 7 - -/** GPIO_FUNC40_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) -/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC40_IN_SEL 0x0000003FU -#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) -#define GPIO_FUNC40_IN_SEL_V 0x0000003FU -#define GPIO_FUNC40_IN_SEL_S 0 -/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) -#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC40_IN_INV_SEL_S 6 -/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG40_IN_SEL (BIT(7)) -#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) -#define GPIO_SIG40_IN_SEL_V 0x00000001U -#define GPIO_SIG40_IN_SEL_S 7 - -/** GPIO_FUNC41_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) -/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC41_IN_SEL 0x0000003FU -#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) -#define GPIO_FUNC41_IN_SEL_V 0x0000003FU -#define GPIO_FUNC41_IN_SEL_S 0 -/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) -#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC41_IN_INV_SEL_S 6 -/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG41_IN_SEL (BIT(7)) -#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) -#define GPIO_SIG41_IN_SEL_V 0x00000001U -#define GPIO_SIG41_IN_SEL_S 7 - -/** GPIO_FUNC42_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) -/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC42_IN_SEL 0x0000003FU -#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) -#define GPIO_FUNC42_IN_SEL_V 0x0000003FU -#define GPIO_FUNC42_IN_SEL_S 0 -/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) -#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC42_IN_INV_SEL_S 6 -/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG42_IN_SEL (BIT(7)) -#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) -#define GPIO_SIG42_IN_SEL_V 0x00000001U -#define GPIO_SIG42_IN_SEL_S 7 - -/** GPIO_FUNC43_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) -/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC43_IN_SEL 0x0000003FU -#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) -#define GPIO_FUNC43_IN_SEL_V 0x0000003FU -#define GPIO_FUNC43_IN_SEL_S 0 -/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) -#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC43_IN_INV_SEL_S 6 -/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG43_IN_SEL (BIT(7)) -#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) -#define GPIO_SIG43_IN_SEL_V 0x00000001U -#define GPIO_SIG43_IN_SEL_S 7 - -/** GPIO_FUNC44_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) -/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC44_IN_SEL 0x0000003FU -#define GPIO_FUNC44_IN_SEL_M (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S) -#define GPIO_FUNC44_IN_SEL_V 0x0000003FU -#define GPIO_FUNC44_IN_SEL_S 0 -/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC44_IN_INV_SEL_M (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S) -#define GPIO_FUNC44_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC44_IN_INV_SEL_S 6 -/** GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG44_IN_SEL (BIT(7)) -#define GPIO_SIG44_IN_SEL_M (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S) -#define GPIO_SIG44_IN_SEL_V 0x00000001U -#define GPIO_SIG44_IN_SEL_S 7 - -/** GPIO_FUNC45_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) -/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC45_IN_SEL 0x0000003FU -#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) -#define GPIO_FUNC45_IN_SEL_V 0x0000003FU -#define GPIO_FUNC45_IN_SEL_S 0 -/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) -#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC45_IN_INV_SEL_S 6 -/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG45_IN_SEL (BIT(7)) -#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) -#define GPIO_SIG45_IN_SEL_V 0x00000001U -#define GPIO_SIG45_IN_SEL_S 7 - -/** GPIO_FUNC46_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) -/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC46_IN_SEL 0x0000003FU -#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) -#define GPIO_FUNC46_IN_SEL_V 0x0000003FU -#define GPIO_FUNC46_IN_SEL_S 0 -/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) -#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC46_IN_INV_SEL_S 6 -/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG46_IN_SEL (BIT(7)) -#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) -#define GPIO_SIG46_IN_SEL_V 0x00000001U -#define GPIO_SIG46_IN_SEL_S 7 - -/** GPIO_FUNC47_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) -/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC47_IN_SEL 0x0000003FU -#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) -#define GPIO_FUNC47_IN_SEL_V 0x0000003FU -#define GPIO_FUNC47_IN_SEL_S 0 -/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) -#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC47_IN_INV_SEL_S 6 -/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG47_IN_SEL (BIT(7)) -#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) -#define GPIO_SIG47_IN_SEL_V 0x00000001U -#define GPIO_SIG47_IN_SEL_S 7 - -/** GPIO_FUNC48_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) -/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC48_IN_SEL 0x0000003FU -#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) -#define GPIO_FUNC48_IN_SEL_V 0x0000003FU -#define GPIO_FUNC48_IN_SEL_S 0 -/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) -#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC48_IN_INV_SEL_S 6 -/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG48_IN_SEL (BIT(7)) -#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) -#define GPIO_SIG48_IN_SEL_V 0x00000001U -#define GPIO_SIG48_IN_SEL_S 7 - -/** GPIO_FUNC49_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) -/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC49_IN_SEL 0x0000003FU -#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) -#define GPIO_FUNC49_IN_SEL_V 0x0000003FU -#define GPIO_FUNC49_IN_SEL_S 0 -/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) -#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC49_IN_INV_SEL_S 6 -/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG49_IN_SEL (BIT(7)) -#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) -#define GPIO_SIG49_IN_SEL_V 0x00000001U -#define GPIO_SIG49_IN_SEL_S 7 - -/** GPIO_FUNC50_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) -/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC50_IN_SEL 0x0000003FU -#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) -#define GPIO_FUNC50_IN_SEL_V 0x0000003FU -#define GPIO_FUNC50_IN_SEL_S 0 -/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) -#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC50_IN_INV_SEL_S 6 -/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG50_IN_SEL (BIT(7)) -#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) -#define GPIO_SIG50_IN_SEL_V 0x00000001U -#define GPIO_SIG50_IN_SEL_S 7 - -/** GPIO_FUNC51_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) -/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC51_IN_SEL 0x0000003FU -#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) -#define GPIO_FUNC51_IN_SEL_V 0x0000003FU -#define GPIO_FUNC51_IN_SEL_S 0 -/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) -#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC51_IN_INV_SEL_S 6 -/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG51_IN_SEL (BIT(7)) -#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) -#define GPIO_SIG51_IN_SEL_V 0x00000001U -#define GPIO_SIG51_IN_SEL_S 7 - -/** GPIO_FUNC52_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) -/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC52_IN_SEL 0x0000003FU -#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) -#define GPIO_FUNC52_IN_SEL_V 0x0000003FU -#define GPIO_FUNC52_IN_SEL_S 0 -/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) -#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC52_IN_INV_SEL_S 6 -/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG52_IN_SEL (BIT(7)) -#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) -#define GPIO_SIG52_IN_SEL_V 0x00000001U -#define GPIO_SIG52_IN_SEL_S 7 - -/** GPIO_FUNC53_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) -/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC53_IN_SEL 0x0000003FU -#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) -#define GPIO_FUNC53_IN_SEL_V 0x0000003FU -#define GPIO_FUNC53_IN_SEL_S 0 -/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) -#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC53_IN_INV_SEL_S 6 -/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG53_IN_SEL (BIT(7)) -#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) -#define GPIO_SIG53_IN_SEL_V 0x00000001U -#define GPIO_SIG53_IN_SEL_S 7 - -/** GPIO_FUNC54_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) -/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC54_IN_SEL 0x0000003FU -#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) -#define GPIO_FUNC54_IN_SEL_V 0x0000003FU -#define GPIO_FUNC54_IN_SEL_S 0 -/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) -#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC54_IN_INV_SEL_S 6 -/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG54_IN_SEL (BIT(7)) -#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) -#define GPIO_SIG54_IN_SEL_V 0x00000001U -#define GPIO_SIG54_IN_SEL_S 7 - -/** GPIO_FUNC55_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) -/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC55_IN_SEL 0x0000003FU -#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) -#define GPIO_FUNC55_IN_SEL_V 0x0000003FU -#define GPIO_FUNC55_IN_SEL_S 0 -/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) -#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC55_IN_INV_SEL_S 6 -/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG55_IN_SEL (BIT(7)) -#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) -#define GPIO_SIG55_IN_SEL_V 0x00000001U -#define GPIO_SIG55_IN_SEL_S 7 - -/** GPIO_FUNC56_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) -/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC56_IN_SEL 0x0000003FU -#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) -#define GPIO_FUNC56_IN_SEL_V 0x0000003FU -#define GPIO_FUNC56_IN_SEL_S 0 -/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) -#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC56_IN_INV_SEL_S 6 -/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG56_IN_SEL (BIT(7)) -#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) -#define GPIO_SIG56_IN_SEL_V 0x00000001U -#define GPIO_SIG56_IN_SEL_S 7 - -/** GPIO_FUNC57_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) -/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC57_IN_SEL 0x0000003FU -#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) -#define GPIO_FUNC57_IN_SEL_V 0x0000003FU -#define GPIO_FUNC57_IN_SEL_S 0 -/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) -#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC57_IN_INV_SEL_S 6 -/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG57_IN_SEL (BIT(7)) -#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) -#define GPIO_SIG57_IN_SEL_V 0x00000001U -#define GPIO_SIG57_IN_SEL_S 7 - -/** GPIO_FUNC58_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) -/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC58_IN_SEL 0x0000003FU -#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) -#define GPIO_FUNC58_IN_SEL_V 0x0000003FU -#define GPIO_FUNC58_IN_SEL_S 0 -/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) -#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC58_IN_INV_SEL_S 6 -/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG58_IN_SEL (BIT(7)) -#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) -#define GPIO_SIG58_IN_SEL_V 0x00000001U -#define GPIO_SIG58_IN_SEL_S 7 - -/** GPIO_FUNC59_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) -/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC59_IN_SEL 0x0000003FU -#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) -#define GPIO_FUNC59_IN_SEL_V 0x0000003FU -#define GPIO_FUNC59_IN_SEL_S 0 -/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) -#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC59_IN_INV_SEL_S 6 -/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG59_IN_SEL (BIT(7)) -#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) -#define GPIO_SIG59_IN_SEL_V 0x00000001U -#define GPIO_SIG59_IN_SEL_S 7 - -/** GPIO_FUNC60_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) -/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC60_IN_SEL 0x0000003FU -#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) -#define GPIO_FUNC60_IN_SEL_V 0x0000003FU -#define GPIO_FUNC60_IN_SEL_S 0 -/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) -#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC60_IN_INV_SEL_S 6 -/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG60_IN_SEL (BIT(7)) -#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) -#define GPIO_SIG60_IN_SEL_V 0x00000001U -#define GPIO_SIG60_IN_SEL_S 7 - -/** GPIO_FUNC61_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) -/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC61_IN_SEL 0x0000003FU -#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) -#define GPIO_FUNC61_IN_SEL_V 0x0000003FU -#define GPIO_FUNC61_IN_SEL_S 0 -/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) -#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC61_IN_INV_SEL_S 6 -/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG61_IN_SEL (BIT(7)) -#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) -#define GPIO_SIG61_IN_SEL_V 0x00000001U -#define GPIO_SIG61_IN_SEL_S 7 - -/** GPIO_FUNC62_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) -/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC62_IN_SEL 0x0000003FU -#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) -#define GPIO_FUNC62_IN_SEL_V 0x0000003FU -#define GPIO_FUNC62_IN_SEL_S 0 -/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) -#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC62_IN_INV_SEL_S 6 -/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG62_IN_SEL (BIT(7)) -#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) -#define GPIO_SIG62_IN_SEL_V 0x00000001U -#define GPIO_SIG62_IN_SEL_S 7 - -/** GPIO_FUNC63_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) -/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC63_IN_SEL 0x0000003FU -#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) -#define GPIO_FUNC63_IN_SEL_V 0x0000003FU -#define GPIO_FUNC63_IN_SEL_S 0 -/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) -#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC63_IN_INV_SEL_S 6 -/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG63_IN_SEL (BIT(7)) -#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) -#define GPIO_SIG63_IN_SEL_V 0x00000001U -#define GPIO_SIG63_IN_SEL_S 7 - -/** GPIO_FUNC64_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) -/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC64_IN_SEL 0x0000003FU -#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) -#define GPIO_FUNC64_IN_SEL_V 0x0000003FU -#define GPIO_FUNC64_IN_SEL_S 0 -/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) -#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC64_IN_INV_SEL_S 6 -/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG64_IN_SEL (BIT(7)) -#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) -#define GPIO_SIG64_IN_SEL_V 0x00000001U -#define GPIO_SIG64_IN_SEL_S 7 - -/** GPIO_FUNC65_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) -/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC65_IN_SEL 0x0000003FU -#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) -#define GPIO_FUNC65_IN_SEL_V 0x0000003FU -#define GPIO_FUNC65_IN_SEL_S 0 -/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) -#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC65_IN_INV_SEL_S 6 -/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG65_IN_SEL (BIT(7)) -#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) -#define GPIO_SIG65_IN_SEL_V 0x00000001U -#define GPIO_SIG65_IN_SEL_S 7 - -/** GPIO_FUNC66_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) -/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC66_IN_SEL 0x0000003FU -#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) -#define GPIO_FUNC66_IN_SEL_V 0x0000003FU -#define GPIO_FUNC66_IN_SEL_S 0 -/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) -#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC66_IN_INV_SEL_S 6 -/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG66_IN_SEL (BIT(7)) -#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) -#define GPIO_SIG66_IN_SEL_V 0x00000001U -#define GPIO_SIG66_IN_SEL_S 7 - -/** GPIO_FUNC67_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) -/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC67_IN_SEL 0x0000003FU -#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) -#define GPIO_FUNC67_IN_SEL_V 0x0000003FU -#define GPIO_FUNC67_IN_SEL_S 0 -/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) -#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC67_IN_INV_SEL_S 6 -/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG67_IN_SEL (BIT(7)) -#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) -#define GPIO_SIG67_IN_SEL_V 0x00000001U -#define GPIO_SIG67_IN_SEL_S 7 - -/** GPIO_FUNC68_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) -/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC68_IN_SEL 0x0000003FU -#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) -#define GPIO_FUNC68_IN_SEL_V 0x0000003FU -#define GPIO_FUNC68_IN_SEL_S 0 -/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) -#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC68_IN_INV_SEL_S 6 -/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG68_IN_SEL (BIT(7)) -#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) -#define GPIO_SIG68_IN_SEL_V 0x00000001U -#define GPIO_SIG68_IN_SEL_S 7 - -/** GPIO_FUNC69_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) -/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC69_IN_SEL 0x0000003FU -#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) -#define GPIO_FUNC69_IN_SEL_V 0x0000003FU -#define GPIO_FUNC69_IN_SEL_S 0 -/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) -#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC69_IN_INV_SEL_S 6 -/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG69_IN_SEL (BIT(7)) -#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) -#define GPIO_SIG69_IN_SEL_V 0x00000001U -#define GPIO_SIG69_IN_SEL_S 7 - -/** GPIO_FUNC70_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) -/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC70_IN_SEL 0x0000003FU -#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) -#define GPIO_FUNC70_IN_SEL_V 0x0000003FU -#define GPIO_FUNC70_IN_SEL_S 0 -/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) -#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC70_IN_INV_SEL_S 6 -/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG70_IN_SEL (BIT(7)) -#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) -#define GPIO_SIG70_IN_SEL_V 0x00000001U -#define GPIO_SIG70_IN_SEL_S 7 - -/** GPIO_FUNC71_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) -/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC71_IN_SEL 0x0000003FU -#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) -#define GPIO_FUNC71_IN_SEL_V 0x0000003FU -#define GPIO_FUNC71_IN_SEL_S 0 -/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) -#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC71_IN_INV_SEL_S 6 -/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG71_IN_SEL (BIT(7)) -#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) -#define GPIO_SIG71_IN_SEL_V 0x00000001U -#define GPIO_SIG71_IN_SEL_S 7 - -/** GPIO_FUNC72_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) -/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC72_IN_SEL 0x0000003FU -#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) -#define GPIO_FUNC72_IN_SEL_V 0x0000003FU -#define GPIO_FUNC72_IN_SEL_S 0 -/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) -#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC72_IN_INV_SEL_S 6 -/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG72_IN_SEL (BIT(7)) -#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) -#define GPIO_SIG72_IN_SEL_V 0x00000001U -#define GPIO_SIG72_IN_SEL_S 7 - -/** GPIO_FUNC73_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) -/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC73_IN_SEL 0x0000003FU -#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) -#define GPIO_FUNC73_IN_SEL_V 0x0000003FU -#define GPIO_FUNC73_IN_SEL_S 0 -/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) -#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC73_IN_INV_SEL_S 6 -/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG73_IN_SEL (BIT(7)) -#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) -#define GPIO_SIG73_IN_SEL_V 0x00000001U -#define GPIO_SIG73_IN_SEL_S 7 - -/** GPIO_FUNC74_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) -/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC74_IN_SEL 0x0000003FU -#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) -#define GPIO_FUNC74_IN_SEL_V 0x0000003FU -#define GPIO_FUNC74_IN_SEL_S 0 -/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) -#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC74_IN_INV_SEL_S 6 -/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG74_IN_SEL (BIT(7)) -#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) -#define GPIO_SIG74_IN_SEL_V 0x00000001U -#define GPIO_SIG74_IN_SEL_S 7 - -/** GPIO_FUNC75_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) -/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC75_IN_SEL 0x0000003FU -#define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) -#define GPIO_FUNC75_IN_SEL_V 0x0000003FU -#define GPIO_FUNC75_IN_SEL_S 0 -/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) -#define GPIO_FUNC75_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC75_IN_INV_SEL_S 6 -/** GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG75_IN_SEL (BIT(7)) -#define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) -#define GPIO_SIG75_IN_SEL_V 0x00000001U -#define GPIO_SIG75_IN_SEL_S 7 - -/** GPIO_FUNC76_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) -/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC76_IN_SEL 0x0000003FU -#define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) -#define GPIO_FUNC76_IN_SEL_V 0x0000003FU -#define GPIO_FUNC76_IN_SEL_S 0 -/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) -#define GPIO_FUNC76_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC76_IN_INV_SEL_S 6 -/** GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG76_IN_SEL (BIT(7)) -#define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) -#define GPIO_SIG76_IN_SEL_V 0x00000001U -#define GPIO_SIG76_IN_SEL_S 7 - -/** GPIO_FUNC77_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) -/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC77_IN_SEL 0x0000003FU -#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) -#define GPIO_FUNC77_IN_SEL_V 0x0000003FU -#define GPIO_FUNC77_IN_SEL_S 0 -/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) -#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC77_IN_INV_SEL_S 6 -/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG77_IN_SEL (BIT(7)) -#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) -#define GPIO_SIG77_IN_SEL_V 0x00000001U -#define GPIO_SIG77_IN_SEL_S 7 - -/** GPIO_FUNC78_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) -/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC78_IN_SEL 0x0000003FU -#define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) -#define GPIO_FUNC78_IN_SEL_V 0x0000003FU -#define GPIO_FUNC78_IN_SEL_S 0 -/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) -#define GPIO_FUNC78_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC78_IN_INV_SEL_S 6 -/** GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG78_IN_SEL (BIT(7)) -#define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) -#define GPIO_SIG78_IN_SEL_V 0x00000001U -#define GPIO_SIG78_IN_SEL_S 7 - -/** GPIO_FUNC79_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) -/** GPIO_FUNC79_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC79_IN_SEL 0x0000003FU -#define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) -#define GPIO_FUNC79_IN_SEL_V 0x0000003FU -#define GPIO_FUNC79_IN_SEL_S 0 -/** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) -#define GPIO_FUNC79_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC79_IN_INV_SEL_S 6 -/** GPIO_SIG79_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG79_IN_SEL (BIT(7)) -#define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) -#define GPIO_SIG79_IN_SEL_V 0x00000001U -#define GPIO_SIG79_IN_SEL_S 7 - -/** GPIO_FUNC80_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) -/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC80_IN_SEL 0x0000003FU -#define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) -#define GPIO_FUNC80_IN_SEL_V 0x0000003FU -#define GPIO_FUNC80_IN_SEL_S 0 -/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) -#define GPIO_FUNC80_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC80_IN_INV_SEL_S 6 -/** GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG80_IN_SEL (BIT(7)) -#define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) -#define GPIO_SIG80_IN_SEL_V 0x00000001U -#define GPIO_SIG80_IN_SEL_S 7 - -/** GPIO_FUNC81_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) -/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC81_IN_SEL 0x0000003FU -#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) -#define GPIO_FUNC81_IN_SEL_V 0x0000003FU -#define GPIO_FUNC81_IN_SEL_S 0 -/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) -#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC81_IN_INV_SEL_S 6 -/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG81_IN_SEL (BIT(7)) -#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) -#define GPIO_SIG81_IN_SEL_V 0x00000001U -#define GPIO_SIG81_IN_SEL_S 7 - -/** GPIO_FUNC82_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) -/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC82_IN_SEL 0x0000003FU -#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) -#define GPIO_FUNC82_IN_SEL_V 0x0000003FU -#define GPIO_FUNC82_IN_SEL_S 0 -/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) -#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC82_IN_INV_SEL_S 6 -/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG82_IN_SEL (BIT(7)) -#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) -#define GPIO_SIG82_IN_SEL_V 0x00000001U -#define GPIO_SIG82_IN_SEL_S 7 - -/** GPIO_FUNC83_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) -/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC83_IN_SEL 0x0000003FU -#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) -#define GPIO_FUNC83_IN_SEL_V 0x0000003FU -#define GPIO_FUNC83_IN_SEL_S 0 -/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) -#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC83_IN_INV_SEL_S 6 -/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG83_IN_SEL (BIT(7)) -#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) -#define GPIO_SIG83_IN_SEL_V 0x00000001U -#define GPIO_SIG83_IN_SEL_S 7 - -/** GPIO_FUNC84_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) -/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC84_IN_SEL 0x0000003FU -#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) -#define GPIO_FUNC84_IN_SEL_V 0x0000003FU -#define GPIO_FUNC84_IN_SEL_S 0 -/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) -#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC84_IN_INV_SEL_S 6 -/** GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG84_IN_SEL (BIT(7)) -#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) -#define GPIO_SIG84_IN_SEL_V 0x00000001U -#define GPIO_SIG84_IN_SEL_S 7 - -/** GPIO_FUNC85_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) -/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC85_IN_SEL 0x0000003FU -#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) -#define GPIO_FUNC85_IN_SEL_V 0x0000003FU -#define GPIO_FUNC85_IN_SEL_S 0 -/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) -#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC85_IN_INV_SEL_S 6 -/** GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG85_IN_SEL (BIT(7)) -#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) -#define GPIO_SIG85_IN_SEL_V 0x00000001U -#define GPIO_SIG85_IN_SEL_S 7 - -/** GPIO_FUNC86_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) -/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC86_IN_SEL 0x0000003FU -#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) -#define GPIO_FUNC86_IN_SEL_V 0x0000003FU -#define GPIO_FUNC86_IN_SEL_S 0 -/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) -#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC86_IN_INV_SEL_S 6 -/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG86_IN_SEL (BIT(7)) -#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) -#define GPIO_SIG86_IN_SEL_V 0x00000001U -#define GPIO_SIG86_IN_SEL_S 7 - -/** GPIO_FUNC87_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) -/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC87_IN_SEL 0x0000003FU -#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) -#define GPIO_FUNC87_IN_SEL_V 0x0000003FU -#define GPIO_FUNC87_IN_SEL_S 0 -/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) -#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC87_IN_INV_SEL_S 6 -/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG87_IN_SEL (BIT(7)) -#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) -#define GPIO_SIG87_IN_SEL_V 0x00000001U -#define GPIO_SIG87_IN_SEL_S 7 - -/** GPIO_FUNC88_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) -/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC88_IN_SEL 0x0000003FU -#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) -#define GPIO_FUNC88_IN_SEL_V 0x0000003FU -#define GPIO_FUNC88_IN_SEL_S 0 -/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) -#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC88_IN_INV_SEL_S 6 -/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG88_IN_SEL (BIT(7)) -#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) -#define GPIO_SIG88_IN_SEL_V 0x00000001U -#define GPIO_SIG88_IN_SEL_S 7 - -/** GPIO_FUNC89_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) -/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC89_IN_SEL 0x0000003FU -#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) -#define GPIO_FUNC89_IN_SEL_V 0x0000003FU -#define GPIO_FUNC89_IN_SEL_S 0 -/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) -#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC89_IN_INV_SEL_S 6 -/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG89_IN_SEL (BIT(7)) -#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) -#define GPIO_SIG89_IN_SEL_V 0x00000001U -#define GPIO_SIG89_IN_SEL_S 7 - -/** GPIO_FUNC90_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) -/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC90_IN_SEL 0x0000003FU -#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) -#define GPIO_FUNC90_IN_SEL_V 0x0000003FU -#define GPIO_FUNC90_IN_SEL_S 0 -/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) -#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC90_IN_INV_SEL_S 6 -/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG90_IN_SEL (BIT(7)) -#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) -#define GPIO_SIG90_IN_SEL_V 0x00000001U -#define GPIO_SIG90_IN_SEL_S 7 - -/** GPIO_FUNC91_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) -/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC91_IN_SEL 0x0000003FU -#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) -#define GPIO_FUNC91_IN_SEL_V 0x0000003FU -#define GPIO_FUNC91_IN_SEL_S 0 -/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) -#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC91_IN_INV_SEL_S 6 -/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG91_IN_SEL (BIT(7)) -#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) -#define GPIO_SIG91_IN_SEL_V 0x00000001U -#define GPIO_SIG91_IN_SEL_S 7 - -/** GPIO_FUNC92_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) -/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC92_IN_SEL 0x0000003FU -#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) -#define GPIO_FUNC92_IN_SEL_V 0x0000003FU -#define GPIO_FUNC92_IN_SEL_S 0 -/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) -#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC92_IN_INV_SEL_S 6 -/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG92_IN_SEL (BIT(7)) -#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) -#define GPIO_SIG92_IN_SEL_V 0x00000001U -#define GPIO_SIG92_IN_SEL_S 7 - -/** GPIO_FUNC93_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) -/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC93_IN_SEL 0x0000003FU -#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) -#define GPIO_FUNC93_IN_SEL_V 0x0000003FU -#define GPIO_FUNC93_IN_SEL_S 0 -/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) -#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC93_IN_INV_SEL_S 6 -/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG93_IN_SEL (BIT(7)) -#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) -#define GPIO_SIG93_IN_SEL_V 0x00000001U -#define GPIO_SIG93_IN_SEL_S 7 - -/** GPIO_FUNC94_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) -/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC94_IN_SEL 0x0000003FU -#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) -#define GPIO_FUNC94_IN_SEL_V 0x0000003FU -#define GPIO_FUNC94_IN_SEL_S 0 -/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) -#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC94_IN_INV_SEL_S 6 -/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG94_IN_SEL (BIT(7)) -#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) -#define GPIO_SIG94_IN_SEL_V 0x00000001U -#define GPIO_SIG94_IN_SEL_S 7 - -/** GPIO_FUNC95_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) -/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC95_IN_SEL 0x0000003FU -#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) -#define GPIO_FUNC95_IN_SEL_V 0x0000003FU -#define GPIO_FUNC95_IN_SEL_S 0 -/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) -#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC95_IN_INV_SEL_S 6 -/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG95_IN_SEL (BIT(7)) -#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) -#define GPIO_SIG95_IN_SEL_V 0x00000001U -#define GPIO_SIG95_IN_SEL_S 7 - -/** GPIO_FUNC96_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) -/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC96_IN_SEL 0x0000003FU -#define GPIO_FUNC96_IN_SEL_M (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S) -#define GPIO_FUNC96_IN_SEL_V 0x0000003FU -#define GPIO_FUNC96_IN_SEL_S 0 -/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC96_IN_INV_SEL_M (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S) -#define GPIO_FUNC96_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC96_IN_INV_SEL_S 6 -/** GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG96_IN_SEL (BIT(7)) -#define GPIO_SIG96_IN_SEL_M (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S) -#define GPIO_SIG96_IN_SEL_V 0x00000001U -#define GPIO_SIG96_IN_SEL_S 7 - -/** GPIO_FUNC97_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) -/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC97_IN_SEL 0x0000003FU -#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) -#define GPIO_FUNC97_IN_SEL_V 0x0000003FU -#define GPIO_FUNC97_IN_SEL_S 0 -/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) -#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC97_IN_INV_SEL_S 6 -/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG97_IN_SEL (BIT(7)) -#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) -#define GPIO_SIG97_IN_SEL_V 0x00000001U -#define GPIO_SIG97_IN_SEL_S 7 - -/** GPIO_FUNC98_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) -/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC98_IN_SEL 0x0000003FU -#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) -#define GPIO_FUNC98_IN_SEL_V 0x0000003FU -#define GPIO_FUNC98_IN_SEL_S 0 -/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) -#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC98_IN_INV_SEL_S 6 -/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG98_IN_SEL (BIT(7)) -#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) -#define GPIO_SIG98_IN_SEL_V 0x00000001U -#define GPIO_SIG98_IN_SEL_S 7 - -/** GPIO_FUNC99_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) -/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC99_IN_SEL 0x0000003FU -#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) -#define GPIO_FUNC99_IN_SEL_V 0x0000003FU -#define GPIO_FUNC99_IN_SEL_S 0 -/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) -#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC99_IN_INV_SEL_S 6 -/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG99_IN_SEL (BIT(7)) -#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) -#define GPIO_SIG99_IN_SEL_V 0x00000001U -#define GPIO_SIG99_IN_SEL_S 7 - -/** GPIO_FUNC100_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) -/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC100_IN_SEL 0x0000003FU -#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) -#define GPIO_FUNC100_IN_SEL_V 0x0000003FU -#define GPIO_FUNC100_IN_SEL_S 0 -/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) -#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC100_IN_INV_SEL_S 6 -/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG100_IN_SEL (BIT(7)) -#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) -#define GPIO_SIG100_IN_SEL_V 0x00000001U -#define GPIO_SIG100_IN_SEL_S 7 - -/** GPIO_FUNC101_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) -/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC101_IN_SEL 0x0000003FU -#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) -#define GPIO_FUNC101_IN_SEL_V 0x0000003FU -#define GPIO_FUNC101_IN_SEL_S 0 -/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) -#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC101_IN_INV_SEL_S 6 -/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG101_IN_SEL (BIT(7)) -#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) -#define GPIO_SIG101_IN_SEL_V 0x00000001U -#define GPIO_SIG101_IN_SEL_S 7 - -/** GPIO_FUNC102_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) -/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC102_IN_SEL 0x0000003FU -#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) -#define GPIO_FUNC102_IN_SEL_V 0x0000003FU -#define GPIO_FUNC102_IN_SEL_S 0 -/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) -#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC102_IN_INV_SEL_S 6 -/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG102_IN_SEL (BIT(7)) -#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) -#define GPIO_SIG102_IN_SEL_V 0x00000001U -#define GPIO_SIG102_IN_SEL_S 7 - -/** GPIO_FUNC103_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) -/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC103_IN_SEL 0x0000003FU -#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) -#define GPIO_FUNC103_IN_SEL_V 0x0000003FU -#define GPIO_FUNC103_IN_SEL_S 0 -/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) -#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC103_IN_INV_SEL_S 6 -/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG103_IN_SEL (BIT(7)) -#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) -#define GPIO_SIG103_IN_SEL_V 0x00000001U -#define GPIO_SIG103_IN_SEL_S 7 - -/** GPIO_FUNC104_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) -/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC104_IN_SEL 0x0000003FU -#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) -#define GPIO_FUNC104_IN_SEL_V 0x0000003FU -#define GPIO_FUNC104_IN_SEL_S 0 -/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) -#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC104_IN_INV_SEL_S 6 -/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG104_IN_SEL (BIT(7)) -#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) -#define GPIO_SIG104_IN_SEL_V 0x00000001U -#define GPIO_SIG104_IN_SEL_S 7 - -/** GPIO_FUNC105_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) -/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC105_IN_SEL 0x0000003FU -#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) -#define GPIO_FUNC105_IN_SEL_V 0x0000003FU -#define GPIO_FUNC105_IN_SEL_S 0 -/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) -#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC105_IN_INV_SEL_S 6 -/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG105_IN_SEL (BIT(7)) -#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) -#define GPIO_SIG105_IN_SEL_V 0x00000001U -#define GPIO_SIG105_IN_SEL_S 7 - -/** GPIO_FUNC106_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) -/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC106_IN_SEL 0x0000003FU -#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) -#define GPIO_FUNC106_IN_SEL_V 0x0000003FU -#define GPIO_FUNC106_IN_SEL_S 0 -/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) -#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC106_IN_INV_SEL_S 6 -/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG106_IN_SEL (BIT(7)) -#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) -#define GPIO_SIG106_IN_SEL_V 0x00000001U -#define GPIO_SIG106_IN_SEL_S 7 - -/** GPIO_FUNC107_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC107_IN_SEL 0x0000003FU -#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) -#define GPIO_FUNC107_IN_SEL_V 0x0000003FU -#define GPIO_FUNC107_IN_SEL_S 0 -/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) -#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC107_IN_INV_SEL_S 6 -/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG107_IN_SEL (BIT(7)) -#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) -#define GPIO_SIG107_IN_SEL_V 0x00000001U -#define GPIO_SIG107_IN_SEL_S 7 - -/** GPIO_FUNC108_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC108_IN_SEL 0x0000003FU -#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) -#define GPIO_FUNC108_IN_SEL_V 0x0000003FU -#define GPIO_FUNC108_IN_SEL_S 0 -/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) -#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC108_IN_INV_SEL_S 6 -/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG108_IN_SEL (BIT(7)) -#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) -#define GPIO_SIG108_IN_SEL_V 0x00000001U -#define GPIO_SIG108_IN_SEL_S 7 - -/** GPIO_FUNC109_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC109_IN_SEL 0x0000003FU -#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) -#define GPIO_FUNC109_IN_SEL_V 0x0000003FU -#define GPIO_FUNC109_IN_SEL_S 0 -/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) -#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC109_IN_INV_SEL_S 6 -/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG109_IN_SEL (BIT(7)) -#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) -#define GPIO_SIG109_IN_SEL_V 0x00000001U -#define GPIO_SIG109_IN_SEL_S 7 - -/** GPIO_FUNC110_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) -/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC110_IN_SEL 0x0000003FU -#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) -#define GPIO_FUNC110_IN_SEL_V 0x0000003FU -#define GPIO_FUNC110_IN_SEL_S 0 -/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) -#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC110_IN_INV_SEL_S 6 -/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG110_IN_SEL (BIT(7)) -#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) -#define GPIO_SIG110_IN_SEL_V 0x00000001U -#define GPIO_SIG110_IN_SEL_S 7 - -/** GPIO_FUNC111_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) -/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC111_IN_SEL 0x0000003FU -#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) -#define GPIO_FUNC111_IN_SEL_V 0x0000003FU -#define GPIO_FUNC111_IN_SEL_S 0 -/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) -#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC111_IN_INV_SEL_S 6 -/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG111_IN_SEL (BIT(7)) -#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) -#define GPIO_SIG111_IN_SEL_V 0x00000001U -#define GPIO_SIG111_IN_SEL_S 7 - -/** GPIO_FUNC112_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) -/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC112_IN_SEL 0x0000003FU -#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) -#define GPIO_FUNC112_IN_SEL_V 0x0000003FU -#define GPIO_FUNC112_IN_SEL_S 0 -/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) -#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC112_IN_INV_SEL_S 6 -/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG112_IN_SEL (BIT(7)) -#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) -#define GPIO_SIG112_IN_SEL_V 0x00000001U -#define GPIO_SIG112_IN_SEL_S 7 - -/** GPIO_FUNC113_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) -/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC113_IN_SEL 0x0000003FU -#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) -#define GPIO_FUNC113_IN_SEL_V 0x0000003FU -#define GPIO_FUNC113_IN_SEL_S 0 -/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) -#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC113_IN_INV_SEL_S 6 -/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG113_IN_SEL (BIT(7)) -#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) -#define GPIO_SIG113_IN_SEL_V 0x00000001U -#define GPIO_SIG113_IN_SEL_S 7 - -/** GPIO_FUNC114_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) -/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC114_IN_SEL 0x0000003FU -#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) -#define GPIO_FUNC114_IN_SEL_V 0x0000003FU -#define GPIO_FUNC114_IN_SEL_S 0 -/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) -#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC114_IN_INV_SEL_S 6 -/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG114_IN_SEL (BIT(7)) -#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) -#define GPIO_SIG114_IN_SEL_V 0x00000001U -#define GPIO_SIG114_IN_SEL_S 7 - -/** GPIO_FUNC115_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) -/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC115_IN_SEL 0x0000003FU -#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) -#define GPIO_FUNC115_IN_SEL_V 0x0000003FU -#define GPIO_FUNC115_IN_SEL_S 0 -/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) -#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC115_IN_INV_SEL_S 6 -/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG115_IN_SEL (BIT(7)) -#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) -#define GPIO_SIG115_IN_SEL_V 0x00000001U -#define GPIO_SIG115_IN_SEL_S 7 - -/** GPIO_FUNC116_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) -/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC116_IN_SEL 0x0000003FU -#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) -#define GPIO_FUNC116_IN_SEL_V 0x0000003FU -#define GPIO_FUNC116_IN_SEL_S 0 -/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) -#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC116_IN_INV_SEL_S 6 -/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG116_IN_SEL (BIT(7)) -#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) -#define GPIO_SIG116_IN_SEL_V 0x00000001U -#define GPIO_SIG116_IN_SEL_S 7 - -/** GPIO_FUNC117_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) -/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC117_IN_SEL 0x0000003FU -#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) -#define GPIO_FUNC117_IN_SEL_V 0x0000003FU -#define GPIO_FUNC117_IN_SEL_S 0 -/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) -#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC117_IN_INV_SEL_S 6 -/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG117_IN_SEL (BIT(7)) -#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) -#define GPIO_SIG117_IN_SEL_V 0x00000001U -#define GPIO_SIG117_IN_SEL_S 7 - -/** GPIO_FUNC118_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) -/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC118_IN_SEL 0x0000003FU -#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) -#define GPIO_FUNC118_IN_SEL_V 0x0000003FU -#define GPIO_FUNC118_IN_SEL_S 0 -/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) -#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC118_IN_INV_SEL_S 6 -/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG118_IN_SEL (BIT(7)) -#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) -#define GPIO_SIG118_IN_SEL_V 0x00000001U -#define GPIO_SIG118_IN_SEL_S 7 - -/** GPIO_FUNC119_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC119_IN_SEL 0x0000003FU -#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) -#define GPIO_FUNC119_IN_SEL_V 0x0000003FU -#define GPIO_FUNC119_IN_SEL_S 0 -/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) -#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC119_IN_INV_SEL_S 6 -/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG119_IN_SEL (BIT(7)) -#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) -#define GPIO_SIG119_IN_SEL_V 0x00000001U -#define GPIO_SIG119_IN_SEL_S 7 - -/** GPIO_FUNC120_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC120_IN_SEL 0x0000003FU -#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) -#define GPIO_FUNC120_IN_SEL_V 0x0000003FU -#define GPIO_FUNC120_IN_SEL_S 0 -/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) -#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC120_IN_INV_SEL_S 6 -/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG120_IN_SEL (BIT(7)) -#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) -#define GPIO_SIG120_IN_SEL_V 0x00000001U -#define GPIO_SIG120_IN_SEL_S 7 - -/** GPIO_FUNC121_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC121_IN_SEL 0x0000003FU -#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) -#define GPIO_FUNC121_IN_SEL_V 0x0000003FU -#define GPIO_FUNC121_IN_SEL_S 0 -/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) -#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC121_IN_INV_SEL_S 6 -/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG121_IN_SEL (BIT(7)) -#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) -#define GPIO_SIG121_IN_SEL_V 0x00000001U -#define GPIO_SIG121_IN_SEL_S 7 - -/** GPIO_FUNC122_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) -/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC122_IN_SEL 0x0000003FU -#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) -#define GPIO_FUNC122_IN_SEL_V 0x0000003FU -#define GPIO_FUNC122_IN_SEL_S 0 -/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) -#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC122_IN_INV_SEL_S 6 -/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG122_IN_SEL (BIT(7)) -#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) -#define GPIO_SIG122_IN_SEL_V 0x00000001U -#define GPIO_SIG122_IN_SEL_S 7 - -/** GPIO_FUNC123_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC123_IN_SEL 0x0000003FU -#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) -#define GPIO_FUNC123_IN_SEL_V 0x0000003FU -#define GPIO_FUNC123_IN_SEL_S 0 -/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) -#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC123_IN_INV_SEL_S 6 -/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG123_IN_SEL (BIT(7)) -#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) -#define GPIO_SIG123_IN_SEL_V 0x00000001U -#define GPIO_SIG123_IN_SEL_S 7 - -/** GPIO_FUNC124_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC124_IN_SEL 0x0000003FU -#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) -#define GPIO_FUNC124_IN_SEL_V 0x0000003FU -#define GPIO_FUNC124_IN_SEL_S 0 -/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) -#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC124_IN_INV_SEL_S 6 -/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG124_IN_SEL (BIT(7)) -#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) -#define GPIO_SIG124_IN_SEL_V 0x00000001U -#define GPIO_SIG124_IN_SEL_S 7 - -/** GPIO_FUNC125_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/** GPIO_FUNC125_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC125_IN_SEL 0x0000003FU -#define GPIO_FUNC125_IN_SEL_M (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S) -#define GPIO_FUNC125_IN_SEL_V 0x0000003FU -#define GPIO_FUNC125_IN_SEL_S 0 -/** GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC125_IN_INV_SEL_M (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S) -#define GPIO_FUNC125_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC125_IN_INV_SEL_S 6 -/** GPIO_SIG125_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG125_IN_SEL (BIT(7)) -#define GPIO_SIG125_IN_SEL_M (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S) -#define GPIO_SIG125_IN_SEL_V 0x00000001U -#define GPIO_SIG125_IN_SEL_S 7 - -/** GPIO_FUNC126_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) -/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC126_IN_SEL 0x0000003FU -#define GPIO_FUNC126_IN_SEL_M (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S) -#define GPIO_FUNC126_IN_SEL_V 0x0000003FU -#define GPIO_FUNC126_IN_SEL_S 0 -/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC126_IN_INV_SEL_M (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S) -#define GPIO_FUNC126_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC126_IN_INV_SEL_S 6 -/** GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG126_IN_SEL (BIT(7)) -#define GPIO_SIG126_IN_SEL_M (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S) -#define GPIO_SIG126_IN_SEL_V 0x00000001U -#define GPIO_SIG126_IN_SEL_S 7 - -/** GPIO_FUNC127_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC127_IN_SEL 0x0000003FU -#define GPIO_FUNC127_IN_SEL_M (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S) -#define GPIO_FUNC127_IN_SEL_V 0x0000003FU -#define GPIO_FUNC127_IN_SEL_S 0 -/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC127_IN_INV_SEL_M (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S) -#define GPIO_FUNC127_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC127_IN_INV_SEL_S 6 -/** GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG127_IN_SEL (BIT(7)) -#define GPIO_SIG127_IN_SEL_M (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S) -#define GPIO_SIG127_IN_SEL_V 0x00000001U -#define GPIO_SIG127_IN_SEL_S 7 - -/** GPIO_FUNC0_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) -/** GPIO_FUNC0_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC0_OUT_SEL 0x000000FFU -#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) -#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC0_OUT_SEL_S 0 -/** GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) -#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_OUT_INV_SEL_S 8 -/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC0_OEN_SEL (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) -#define GPIO_FUNC0_OEN_SEL_V 0x00000001U -#define GPIO_FUNC0_OEN_SEL_S 9 -/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) -#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_OEN_INV_SEL_S 10 - -/** GPIO_FUNC1_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) -/** GPIO_FUNC1_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC1_OUT_SEL 0x000000FFU -#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) -#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC1_OUT_SEL_S 0 -/** GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) -#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC1_OUT_INV_SEL_S 8 -/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC1_OEN_SEL (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) -#define GPIO_FUNC1_OEN_SEL_V 0x00000001U -#define GPIO_FUNC1_OEN_SEL_S 9 -/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) -#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC1_OEN_INV_SEL_S 10 - -/** GPIO_FUNC2_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) -/** GPIO_FUNC2_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC2_OUT_SEL 0x000000FFU -#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) -#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC2_OUT_SEL_S 0 -/** GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) -#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC2_OUT_INV_SEL_S 8 -/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC2_OEN_SEL (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) -#define GPIO_FUNC2_OEN_SEL_V 0x00000001U -#define GPIO_FUNC2_OEN_SEL_S 9 -/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) -#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC2_OEN_INV_SEL_S 10 - -/** GPIO_FUNC3_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) -/** GPIO_FUNC3_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC3_OUT_SEL 0x000000FFU -#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) -#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC3_OUT_SEL_S 0 -/** GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) -#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC3_OUT_INV_SEL_S 8 -/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC3_OEN_SEL (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) -#define GPIO_FUNC3_OEN_SEL_V 0x00000001U -#define GPIO_FUNC3_OEN_SEL_S 9 -/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) -#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC3_OEN_INV_SEL_S 10 - -/** GPIO_FUNC4_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) -/** GPIO_FUNC4_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC4_OUT_SEL 0x000000FFU -#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) -#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC4_OUT_SEL_S 0 -/** GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) -#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC4_OUT_INV_SEL_S 8 -/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC4_OEN_SEL (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) -#define GPIO_FUNC4_OEN_SEL_V 0x00000001U -#define GPIO_FUNC4_OEN_SEL_S 9 -/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) -#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC4_OEN_INV_SEL_S 10 - -/** GPIO_FUNC5_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) -/** GPIO_FUNC5_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC5_OUT_SEL 0x000000FFU -#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) -#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC5_OUT_SEL_S 0 -/** GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) -#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC5_OUT_INV_SEL_S 8 -/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC5_OEN_SEL (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) -#define GPIO_FUNC5_OEN_SEL_V 0x00000001U -#define GPIO_FUNC5_OEN_SEL_S 9 -/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) -#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC5_OEN_INV_SEL_S 10 - -/** GPIO_FUNC6_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) -/** GPIO_FUNC6_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC6_OUT_SEL 0x000000FFU -#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) -#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC6_OUT_SEL_S 0 -/** GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) -#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_OUT_INV_SEL_S 8 -/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC6_OEN_SEL (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) -#define GPIO_FUNC6_OEN_SEL_V 0x00000001U -#define GPIO_FUNC6_OEN_SEL_S 9 -/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) -#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_OEN_INV_SEL_S 10 - -/** GPIO_FUNC7_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) -/** GPIO_FUNC7_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC7_OUT_SEL 0x000000FFU -#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) -#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC7_OUT_SEL_S 0 -/** GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) -#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_OUT_INV_SEL_S 8 -/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC7_OEN_SEL (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) -#define GPIO_FUNC7_OEN_SEL_V 0x00000001U -#define GPIO_FUNC7_OEN_SEL_S 9 -/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) -#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_OEN_INV_SEL_S 10 - -/** GPIO_FUNC8_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) -/** GPIO_FUNC8_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC8_OUT_SEL 0x000000FFU -#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) -#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC8_OUT_SEL_S 0 -/** GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) -#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_OUT_INV_SEL_S 8 -/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC8_OEN_SEL (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) -#define GPIO_FUNC8_OEN_SEL_V 0x00000001U -#define GPIO_FUNC8_OEN_SEL_S 9 -/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) -#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_OEN_INV_SEL_S 10 - -/** GPIO_FUNC9_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) -/** GPIO_FUNC9_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC9_OUT_SEL 0x000000FFU -#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) -#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC9_OUT_SEL_S 0 -/** GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) -#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_OUT_INV_SEL_S 8 -/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC9_OEN_SEL (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) -#define GPIO_FUNC9_OEN_SEL_V 0x00000001U -#define GPIO_FUNC9_OEN_SEL_S 9 -/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) -#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_OEN_INV_SEL_S 10 - -/** GPIO_FUNC10_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) -/** GPIO_FUNC10_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC10_OUT_SEL 0x000000FFU -#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) -#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC10_OUT_SEL_S 0 -/** GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) -#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_OUT_INV_SEL_S 8 -/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC10_OEN_SEL (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) -#define GPIO_FUNC10_OEN_SEL_V 0x00000001U -#define GPIO_FUNC10_OEN_SEL_S 9 -/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) -#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_OEN_INV_SEL_S 10 - -/** GPIO_FUNC11_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) -/** GPIO_FUNC11_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC11_OUT_SEL 0x000000FFU -#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) -#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC11_OUT_SEL_S 0 -/** GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) -#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_OUT_INV_SEL_S 8 -/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC11_OEN_SEL (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) -#define GPIO_FUNC11_OEN_SEL_V 0x00000001U -#define GPIO_FUNC11_OEN_SEL_S 9 -/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) -#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_OEN_INV_SEL_S 10 - -/** GPIO_FUNC12_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) -/** GPIO_FUNC12_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC12_OUT_SEL 0x000000FFU -#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) -#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC12_OUT_SEL_S 0 -/** GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) -#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_OUT_INV_SEL_S 8 -/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC12_OEN_SEL (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) -#define GPIO_FUNC12_OEN_SEL_V 0x00000001U -#define GPIO_FUNC12_OEN_SEL_S 9 -/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) -#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_OEN_INV_SEL_S 10 - -/** GPIO_FUNC13_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) -/** GPIO_FUNC13_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC13_OUT_SEL 0x000000FFU -#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) -#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC13_OUT_SEL_S 0 -/** GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) -#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_OUT_INV_SEL_S 8 -/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC13_OEN_SEL (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) -#define GPIO_FUNC13_OEN_SEL_V 0x00000001U -#define GPIO_FUNC13_OEN_SEL_S 9 -/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) -#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_OEN_INV_SEL_S 10 - -/** GPIO_FUNC14_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) -/** GPIO_FUNC14_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC14_OUT_SEL 0x000000FFU -#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) -#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC14_OUT_SEL_S 0 -/** GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) -#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_OUT_INV_SEL_S 8 -/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC14_OEN_SEL (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) -#define GPIO_FUNC14_OEN_SEL_V 0x00000001U -#define GPIO_FUNC14_OEN_SEL_S 9 -/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) -#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_OEN_INV_SEL_S 10 - -/** GPIO_FUNC15_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) -/** GPIO_FUNC15_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC15_OUT_SEL 0x000000FFU -#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) -#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC15_OUT_SEL_S 0 -/** GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) -#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_OUT_INV_SEL_S 8 -/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC15_OEN_SEL (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) -#define GPIO_FUNC15_OEN_SEL_V 0x00000001U -#define GPIO_FUNC15_OEN_SEL_S 9 -/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) -#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_OEN_INV_SEL_S 10 - -/** GPIO_FUNC16_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) -/** GPIO_FUNC16_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC16_OUT_SEL 0x000000FFU -#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) -#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC16_OUT_SEL_S 0 -/** GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) -#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_OUT_INV_SEL_S 8 -/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC16_OEN_SEL (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) -#define GPIO_FUNC16_OEN_SEL_V 0x00000001U -#define GPIO_FUNC16_OEN_SEL_S 9 -/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) -#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_OEN_INV_SEL_S 10 - -/** GPIO_FUNC17_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) -/** GPIO_FUNC17_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC17_OUT_SEL 0x000000FFU -#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) -#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC17_OUT_SEL_S 0 -/** GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) -#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_OUT_INV_SEL_S 8 -/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC17_OEN_SEL (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) -#define GPIO_FUNC17_OEN_SEL_V 0x00000001U -#define GPIO_FUNC17_OEN_SEL_S 9 -/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) -#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_OEN_INV_SEL_S 10 - -/** GPIO_FUNC18_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) -/** GPIO_FUNC18_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC18_OUT_SEL 0x000000FFU -#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) -#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC18_OUT_SEL_S 0 -/** GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) -#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC18_OUT_INV_SEL_S 8 -/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC18_OEN_SEL (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) -#define GPIO_FUNC18_OEN_SEL_V 0x00000001U -#define GPIO_FUNC18_OEN_SEL_S 9 -/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) -#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC18_OEN_INV_SEL_S 10 - -/** GPIO_FUNC19_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) -/** GPIO_FUNC19_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC19_OUT_SEL 0x000000FFU -#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) -#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC19_OUT_SEL_S 0 -/** GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) -#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC19_OUT_INV_SEL_S 8 -/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC19_OEN_SEL (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) -#define GPIO_FUNC19_OEN_SEL_V 0x00000001U -#define GPIO_FUNC19_OEN_SEL_S 9 -/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) -#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC19_OEN_INV_SEL_S 10 - -/** GPIO_FUNC20_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) -/** GPIO_FUNC20_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC20_OUT_SEL 0x000000FFU -#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) -#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC20_OUT_SEL_S 0 -/** GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) -#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC20_OUT_INV_SEL_S 8 -/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC20_OEN_SEL (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) -#define GPIO_FUNC20_OEN_SEL_V 0x00000001U -#define GPIO_FUNC20_OEN_SEL_S 9 -/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) -#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC20_OEN_INV_SEL_S 10 - -/** GPIO_FUNC21_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) -/** GPIO_FUNC21_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC21_OUT_SEL 0x000000FFU -#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) -#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC21_OUT_SEL_S 0 -/** GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) -#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC21_OUT_INV_SEL_S 8 -/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC21_OEN_SEL (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) -#define GPIO_FUNC21_OEN_SEL_V 0x00000001U -#define GPIO_FUNC21_OEN_SEL_S 9 -/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) -#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC21_OEN_INV_SEL_S 10 - -/** GPIO_FUNC22_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) -/** GPIO_FUNC22_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC22_OUT_SEL 0x000000FFU -#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) -#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC22_OUT_SEL_S 0 -/** GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) -#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC22_OUT_INV_SEL_S 8 -/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC22_OEN_SEL (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) -#define GPIO_FUNC22_OEN_SEL_V 0x00000001U -#define GPIO_FUNC22_OEN_SEL_S 9 -/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) -#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC22_OEN_INV_SEL_S 10 - -/** GPIO_FUNC23_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) -/** GPIO_FUNC23_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC23_OUT_SEL 0x000000FFU -#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) -#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC23_OUT_SEL_S 0 -/** GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) -#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC23_OUT_INV_SEL_S 8 -/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC23_OEN_SEL (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) -#define GPIO_FUNC23_OEN_SEL_V 0x00000001U -#define GPIO_FUNC23_OEN_SEL_S 9 -/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) -#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC23_OEN_INV_SEL_S 10 - -/** GPIO_FUNC24_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) -/** GPIO_FUNC24_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC24_OUT_SEL 0x000000FFU -#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) -#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC24_OUT_SEL_S 0 -/** GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) -#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC24_OUT_INV_SEL_S 8 -/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC24_OEN_SEL (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) -#define GPIO_FUNC24_OEN_SEL_V 0x00000001U -#define GPIO_FUNC24_OEN_SEL_S 9 -/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) -#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC24_OEN_INV_SEL_S 10 - -/** GPIO_FUNC25_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) -/** GPIO_FUNC25_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC25_OUT_SEL 0x000000FFU -#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) -#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC25_OUT_SEL_S 0 -/** GPIO_FUNC25_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) -#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC25_OUT_INV_SEL_S 8 -/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC25_OEN_SEL (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) -#define GPIO_FUNC25_OEN_SEL_V 0x00000001U -#define GPIO_FUNC25_OEN_SEL_S 9 -/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) -#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC25_OEN_INV_SEL_S 10 - -/** GPIO_FUNC26_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) -/** GPIO_FUNC26_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC26_OUT_SEL 0x000000FFU -#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) -#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC26_OUT_SEL_S 0 -/** GPIO_FUNC26_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) -#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC26_OUT_INV_SEL_S 8 -/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC26_OEN_SEL (BIT(9)) -#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) -#define GPIO_FUNC26_OEN_SEL_V 0x00000001U -#define GPIO_FUNC26_OEN_SEL_S 9 -/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) -#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC26_OEN_INV_SEL_S 10 - -/** GPIO_FUNC27_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) -/** GPIO_FUNC27_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC27_OUT_SEL 0x000000FFU -#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) -#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC27_OUT_SEL_S 0 -/** GPIO_FUNC27_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) -#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_OUT_INV_SEL_S 8 -/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC27_OEN_SEL (BIT(9)) -#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) -#define GPIO_FUNC27_OEN_SEL_V 0x00000001U -#define GPIO_FUNC27_OEN_SEL_S 9 -/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) -#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_OEN_INV_SEL_S 10 - -/** GPIO_FUNC28_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) -/** GPIO_FUNC28_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC28_OUT_SEL 0x000000FFU -#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) -#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC28_OUT_SEL_S 0 -/** GPIO_FUNC28_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) -#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_OUT_INV_SEL_S 8 -/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC28_OEN_SEL (BIT(9)) -#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) -#define GPIO_FUNC28_OEN_SEL_V 0x00000001U -#define GPIO_FUNC28_OEN_SEL_S 9 -/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) -#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_OEN_INV_SEL_S 10 - -/** GPIO_FUNC29_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) -/** GPIO_FUNC29_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC29_OUT_SEL 0x000000FFU -#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) -#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC29_OUT_SEL_S 0 -/** GPIO_FUNC29_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) -#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_OUT_INV_SEL_S 8 -/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC29_OEN_SEL (BIT(9)) -#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) -#define GPIO_FUNC29_OEN_SEL_V 0x00000001U -#define GPIO_FUNC29_OEN_SEL_S 9 -/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) -#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_OEN_INV_SEL_S 10 - -/** GPIO_FUNC30_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) -/** GPIO_FUNC30_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC30_OUT_SEL 0x000000FFU -#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) -#define GPIO_FUNC30_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC30_OUT_SEL_S 0 -/** GPIO_FUNC30_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC30_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) -#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_OUT_INV_SEL_S 8 -/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC30_OEN_SEL (BIT(9)) -#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) -#define GPIO_FUNC30_OEN_SEL_V 0x00000001U -#define GPIO_FUNC30_OEN_SEL_S 9 -/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC30_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) -#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_OEN_INV_SEL_S 10 - -/** GPIO_FUNC31_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) -/** GPIO_FUNC31_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC31_OUT_SEL 0x000000FFU -#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) -#define GPIO_FUNC31_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC31_OUT_SEL_S 0 -/** GPIO_FUNC31_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC31_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) -#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_OUT_INV_SEL_S 8 -/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC31_OEN_SEL (BIT(9)) -#define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) -#define GPIO_FUNC31_OEN_SEL_V 0x00000001U -#define GPIO_FUNC31_OEN_SEL_S 9 -/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC31_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) -#define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_OEN_INV_SEL_S 10 - -/** GPIO_FUNC32_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4) -/** GPIO_FUNC32_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC32_OUT_SEL 0x000000FFU -#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) -#define GPIO_FUNC32_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC32_OUT_SEL_S 0 -/** GPIO_FUNC32_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC32_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) -#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_OUT_INV_SEL_S 8 -/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC32_OEN_SEL (BIT(9)) -#define GPIO_FUNC32_OEN_SEL_M (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S) -#define GPIO_FUNC32_OEN_SEL_V 0x00000001U -#define GPIO_FUNC32_OEN_SEL_S 9 -/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC32_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC32_OEN_INV_SEL_M (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S) -#define GPIO_FUNC32_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_OEN_INV_SEL_S 10 - -/** GPIO_FUNC33_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8) -/** GPIO_FUNC33_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC33_OUT_SEL 0x000000FFU -#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) -#define GPIO_FUNC33_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC33_OUT_SEL_S 0 -/** GPIO_FUNC33_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC33_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) -#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC33_OUT_INV_SEL_S 8 -/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC33_OEN_SEL (BIT(9)) -#define GPIO_FUNC33_OEN_SEL_M (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S) -#define GPIO_FUNC33_OEN_SEL_V 0x00000001U -#define GPIO_FUNC33_OEN_SEL_S 9 -/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC33_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC33_OEN_INV_SEL_M (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S) -#define GPIO_FUNC33_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC33_OEN_INV_SEL_S 10 - -/** GPIO_FUNC34_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc) -/** GPIO_FUNC34_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC34_OUT_SEL 0x000000FFU -#define GPIO_FUNC34_OUT_SEL_M (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S) -#define GPIO_FUNC34_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC34_OUT_SEL_S 0 -/** GPIO_FUNC34_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC34_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC34_OUT_INV_SEL_M (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S) -#define GPIO_FUNC34_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC34_OUT_INV_SEL_S 8 -/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC34_OEN_SEL (BIT(9)) -#define GPIO_FUNC34_OEN_SEL_M (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S) -#define GPIO_FUNC34_OEN_SEL_V 0x00000001U -#define GPIO_FUNC34_OEN_SEL_S 9 -/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC34_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC34_OEN_INV_SEL_M (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S) -#define GPIO_FUNC34_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC34_OEN_INV_SEL_S 10 - -/** GPIO_FUNC35_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0) -/** GPIO_FUNC35_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC35_OUT_SEL 0x000000FFU -#define GPIO_FUNC35_OUT_SEL_M (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S) -#define GPIO_FUNC35_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC35_OUT_SEL_S 0 -/** GPIO_FUNC35_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC35_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC35_OUT_INV_SEL_M (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S) -#define GPIO_FUNC35_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC35_OUT_INV_SEL_S 8 -/** GPIO_FUNC35_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC35_OEN_SEL (BIT(9)) -#define GPIO_FUNC35_OEN_SEL_M (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S) -#define GPIO_FUNC35_OEN_SEL_V 0x00000001U -#define GPIO_FUNC35_OEN_SEL_S 9 -/** GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC35_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC35_OEN_INV_SEL_M (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S) -#define GPIO_FUNC35_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC35_OEN_INV_SEL_S 10 - -/** GPIO_FUNC36_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4) -/** GPIO_FUNC36_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC36_OUT_SEL 0x000000FFU -#define GPIO_FUNC36_OUT_SEL_M (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S) -#define GPIO_FUNC36_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC36_OUT_SEL_S 0 -/** GPIO_FUNC36_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC36_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC36_OUT_INV_SEL_M (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S) -#define GPIO_FUNC36_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC36_OUT_INV_SEL_S 8 -/** GPIO_FUNC36_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC36_OEN_SEL (BIT(9)) -#define GPIO_FUNC36_OEN_SEL_M (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S) -#define GPIO_FUNC36_OEN_SEL_V 0x00000001U -#define GPIO_FUNC36_OEN_SEL_S 9 -/** GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC36_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC36_OEN_INV_SEL_M (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S) -#define GPIO_FUNC36_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC36_OEN_INV_SEL_S 10 - -/** GPIO_FUNC37_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8) -/** GPIO_FUNC37_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC37_OUT_SEL 0x000000FFU -#define GPIO_FUNC37_OUT_SEL_M (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S) -#define GPIO_FUNC37_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC37_OUT_SEL_S 0 -/** GPIO_FUNC37_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC37_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC37_OUT_INV_SEL_M (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S) -#define GPIO_FUNC37_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC37_OUT_INV_SEL_S 8 -/** GPIO_FUNC37_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC37_OEN_SEL (BIT(9)) -#define GPIO_FUNC37_OEN_SEL_M (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S) -#define GPIO_FUNC37_OEN_SEL_V 0x00000001U -#define GPIO_FUNC37_OEN_SEL_S 9 -/** GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC37_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC37_OEN_INV_SEL_M (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S) -#define GPIO_FUNC37_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC37_OEN_INV_SEL_S 10 - -/** GPIO_FUNC38_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec) -/** GPIO_FUNC38_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC38_OUT_SEL 0x000000FFU -#define GPIO_FUNC38_OUT_SEL_M (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S) -#define GPIO_FUNC38_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC38_OUT_SEL_S 0 -/** GPIO_FUNC38_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC38_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC38_OUT_INV_SEL_M (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S) -#define GPIO_FUNC38_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC38_OUT_INV_SEL_S 8 -/** GPIO_FUNC38_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC38_OEN_SEL (BIT(9)) -#define GPIO_FUNC38_OEN_SEL_M (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S) -#define GPIO_FUNC38_OEN_SEL_V 0x00000001U -#define GPIO_FUNC38_OEN_SEL_S 9 -/** GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC38_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC38_OEN_INV_SEL_M (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S) -#define GPIO_FUNC38_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC38_OEN_INV_SEL_S 10 - -/** GPIO_FUNC39_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0) -/** GPIO_FUNC39_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC39_OUT_SEL 0x000000FFU -#define GPIO_FUNC39_OUT_SEL_M (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S) -#define GPIO_FUNC39_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC39_OUT_SEL_S 0 -/** GPIO_FUNC39_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC39_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC39_OUT_INV_SEL_M (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S) -#define GPIO_FUNC39_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC39_OUT_INV_SEL_S 8 -/** GPIO_FUNC39_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC39_OEN_SEL (BIT(9)) -#define GPIO_FUNC39_OEN_SEL_M (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S) -#define GPIO_FUNC39_OEN_SEL_V 0x00000001U -#define GPIO_FUNC39_OEN_SEL_S 9 -/** GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC39_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC39_OEN_INV_SEL_M (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S) -#define GPIO_FUNC39_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC39_OEN_INV_SEL_S 10 - -/** GPIO_FUNC40_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4) -/** GPIO_FUNC40_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC40_OUT_SEL 0x000000FFU -#define GPIO_FUNC40_OUT_SEL_M (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S) -#define GPIO_FUNC40_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC40_OUT_SEL_S 0 -/** GPIO_FUNC40_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC40_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC40_OUT_INV_SEL_M (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S) -#define GPIO_FUNC40_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC40_OUT_INV_SEL_S 8 -/** GPIO_FUNC40_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC40_OEN_SEL (BIT(9)) -#define GPIO_FUNC40_OEN_SEL_M (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S) -#define GPIO_FUNC40_OEN_SEL_V 0x00000001U -#define GPIO_FUNC40_OEN_SEL_S 9 -/** GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC40_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC40_OEN_INV_SEL_M (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S) -#define GPIO_FUNC40_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC40_OEN_INV_SEL_S 10 - -/** GPIO_FUNC41_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8) -/** GPIO_FUNC41_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC41_OUT_SEL 0x000000FFU -#define GPIO_FUNC41_OUT_SEL_M (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S) -#define GPIO_FUNC41_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC41_OUT_SEL_S 0 -/** GPIO_FUNC41_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC41_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC41_OUT_INV_SEL_M (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S) -#define GPIO_FUNC41_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC41_OUT_INV_SEL_S 8 -/** GPIO_FUNC41_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC41_OEN_SEL (BIT(9)) -#define GPIO_FUNC41_OEN_SEL_M (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S) -#define GPIO_FUNC41_OEN_SEL_V 0x00000001U -#define GPIO_FUNC41_OEN_SEL_S 9 -/** GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC41_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC41_OEN_INV_SEL_M (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S) -#define GPIO_FUNC41_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC41_OEN_INV_SEL_S 10 - -/** GPIO_FUNC42_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc) -/** GPIO_FUNC42_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC42_OUT_SEL 0x000000FFU -#define GPIO_FUNC42_OUT_SEL_M (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S) -#define GPIO_FUNC42_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC42_OUT_SEL_S 0 -/** GPIO_FUNC42_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC42_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC42_OUT_INV_SEL_M (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S) -#define GPIO_FUNC42_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC42_OUT_INV_SEL_S 8 -/** GPIO_FUNC42_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC42_OEN_SEL (BIT(9)) -#define GPIO_FUNC42_OEN_SEL_M (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S) -#define GPIO_FUNC42_OEN_SEL_V 0x00000001U -#define GPIO_FUNC42_OEN_SEL_S 9 -/** GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC42_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC42_OEN_INV_SEL_M (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S) -#define GPIO_FUNC42_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC42_OEN_INV_SEL_S 10 - -/** GPIO_FUNC43_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) -/** GPIO_FUNC43_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC43_OUT_SEL 0x000000FFU -#define GPIO_FUNC43_OUT_SEL_M (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S) -#define GPIO_FUNC43_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC43_OUT_SEL_S 0 -/** GPIO_FUNC43_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC43_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC43_OUT_INV_SEL_M (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S) -#define GPIO_FUNC43_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC43_OUT_INV_SEL_S 8 -/** GPIO_FUNC43_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC43_OEN_SEL (BIT(9)) -#define GPIO_FUNC43_OEN_SEL_M (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S) -#define GPIO_FUNC43_OEN_SEL_V 0x00000001U -#define GPIO_FUNC43_OEN_SEL_S 9 -/** GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC43_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC43_OEN_INV_SEL_M (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S) -#define GPIO_FUNC43_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC43_OEN_INV_SEL_S 10 - -/** GPIO_FUNC44_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) -/** GPIO_FUNC44_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC44_OUT_SEL 0x000000FFU -#define GPIO_FUNC44_OUT_SEL_M (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S) -#define GPIO_FUNC44_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC44_OUT_SEL_S 0 -/** GPIO_FUNC44_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC44_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC44_OUT_INV_SEL_M (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S) -#define GPIO_FUNC44_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC44_OUT_INV_SEL_S 8 -/** GPIO_FUNC44_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC44_OEN_SEL (BIT(9)) -#define GPIO_FUNC44_OEN_SEL_M (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S) -#define GPIO_FUNC44_OEN_SEL_V 0x00000001U -#define GPIO_FUNC44_OEN_SEL_S 9 -/** GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC44_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC44_OEN_INV_SEL_M (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S) -#define GPIO_FUNC44_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC44_OEN_INV_SEL_S 10 - -/** GPIO_CLOCK_GATE_REG register - * GPIO clock gate register - */ -#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) -/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; - * set this bit to enable GPIO clock gate - */ -#define GPIO_CLK_EN (BIT(0)) -#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) -#define GPIO_CLK_EN_V 0x00000001U -#define GPIO_CLK_EN_S 0 - -/** GPIO_REG_DATE_REG register - * GPIO version register - */ -#define GPIO_REG_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) -/** GPIO_REG_DATE : R/W; bitpos: [27:0]; default: 33628944; - * version register - */ -#define GPIO_REG_DATE 0x0FFFFFFFU -#define GPIO_REG_DATE_M (GPIO_REG_DATE_V << GPIO_REG_DATE_S) -#define GPIO_REG_DATE_V 0x0FFFFFFFU -#define GPIO_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif - -#endif /*_SOC_GPIO_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/gpio_sd_reg.h b/components/soc/esp32h4/include/rev1/soc/gpio_sd_reg.h deleted file mode 100644 index 1afd32b5dc..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/gpio_sd_reg.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) -/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD0_PRESCALE 0x000000FF -#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S)) -#define GPIO_SD0_PRESCALE_V 0xFF -#define GPIO_SD0_PRESCALE_S 8 -/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD0_IN 0x000000FF -#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S)) -#define GPIO_SD0_IN_V 0xFF -#define GPIO_SD0_IN_S 0 - -#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004) -/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD1_PRESCALE 0x000000FF -#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S)) -#define GPIO_SD1_PRESCALE_V 0xFF -#define GPIO_SD1_PRESCALE_S 8 -/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD1_IN 0x000000FF -#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S)) -#define GPIO_SD1_IN_V 0xFF -#define GPIO_SD1_IN_S 0 - -#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008) -/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD2_PRESCALE 0x000000FF -#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S)) -#define GPIO_SD2_PRESCALE_V 0xFF -#define GPIO_SD2_PRESCALE_S 8 -/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD2_IN 0x000000FF -#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S)) -#define GPIO_SD2_IN_V 0xFF -#define GPIO_SD2_IN_S 0 - -#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c) -/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ -/*description: */ -#define GPIO_SD3_PRESCALE 0x000000FF -#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S)) -#define GPIO_SD3_PRESCALE_V 0xFF -#define GPIO_SD3_PRESCALE_S 8 -/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define GPIO_SD3_IN 0x000000FF -#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S)) -#define GPIO_SD3_IN_V 0xFF -#define GPIO_SD3_IN_S 0 - -#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020) -/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SD_CLK_EN (BIT(31)) -#define GPIO_SD_CLK_EN_M (BIT(31)) -#define GPIO_SD_CLK_EN_V 0x1 -#define GPIO_SD_CLK_EN_S 31 - -#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024) -/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define GPIO_SPI_SWAP (BIT(31)) -#define GPIO_SPI_SWAP_M (BIT(31)) -#define GPIO_SPI_SWAP_V 0x1 -#define GPIO_SPI_SWAP_S 31 -/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: */ -#define GPIO_FUNCTION_CLK_EN (BIT(30)) -#define GPIO_FUNCTION_CLK_EN_M (BIT(30)) -#define GPIO_FUNCTION_CLK_EN_V 0x1 -#define GPIO_FUNCTION_CLK_EN_S 30 - -#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028) -/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006230 ; */ -/*description: */ -#define GPIO_SD_DATE 0x0FFFFFFF -#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S)) -#define GPIO_SD_DATE_V 0xFFFFFFF -#define GPIO_SD_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev1/soc/gpio_sig_map.h b/components/soc/esp32h4/include/rev1/soc/gpio_sig_map.h deleted file mode 100644 index 16ac67a469..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/gpio_sig_map.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_GPIO_SIG_MAP_H_ -#define _SOC_GPIO_SIG_MAP_H_ - -#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX -#define SPIQ_IN_IDX 0 -#define SPIQ_OUT_IDX 0 -#define SPID_IN_IDX 1 -#define SPID_OUT_IDX 1 -#define SPIHD_IN_IDX 2 -#define SPIHD_OUT_IDX 2 -#define SPIWP_IN_IDX 3 -#define SPIWP_OUT_IDX 3 -#define SPICLK_OUT_IDX 4 -#define SPICS0_OUT_IDX 5 -#define U0RXD_IN_IDX 6 -#define U0TXD_OUT_IDX 6 -#define U0CTS_IN_IDX 7 -#define U0RTS_OUT_IDX 7 -#define U0DSR_IN_IDX 8 -#define U0DTR_OUT_IDX 8 -#define U1RXD_IN_IDX 9 -#define U1TXD_OUT_IDX 9 -#define U1CTS_IN_IDX 10 -#define U1RTS_OUT_IDX 10 -#define U1DSR_IN_IDX 11 -#define U1DTR_OUT_IDX 11 -#define I2S_MCLK_IN_IDX 12 -#define I2S_MCLK_OUT_IDX 12 -#define I2SO_BCK_IN_IDX 13 -#define I2SO_BCK_OUT_IDX 13 -#define I2SO_WS_IN_IDX 14 -#define I2SO_WS_OUT_IDX 14 -#define I2SI_SD_IN_IDX 15 -#define I2SO_SD_OUT_IDX 15 -#define I2SI_BCK_IN_IDX 16 -#define I2SI_BCK_OUT_IDX 16 -#define I2SI_WS_IN_IDX 17 -#define I2SI_WS_OUT_IDX 17 -#define CO_EXT_PRIORITY_IN_IDX 18 -#define I2SO_SD1_OUT_IDX 18 -#define CO_EXT_ACTIVE_IN_IDX 19 -#define CO_EXT_ACTIVE_OUT_IDX 19 -#define CPU_TESTBUS0_IDX 20 -#define CPU_TESTBUS1_IDX 21 -#define CPU_TESTBUS2_IDX 22 -#define CPU_TESTBUS3_IDX 23 -#define CPU_TESTBUS4_IDX 24 -#define CPU_TESTBUS5_IDX 25 -#define CPU_TESTBUS6_IDX 26 -#define CPU_TESTBUS7_IDX 27 -#define CPU_GPIO_IN0_IDX 28 -#define CPU_GPIO_OUT0_IDX 28 -#define CPU_GPIO_IN1_IDX 29 -#define CPU_GPIO_OUT1_IDX 29 -#define CPU_GPIO_IN2_IDX 30 -#define CPU_GPIO_OUT2_IDX 30 -#define CPU_GPIO_IN3_IDX 31 -#define CPU_GPIO_OUT3_IDX 31 -#define CPU_GPIO_IN4_IDX 32 -#define CPU_GPIO_OUT4_IDX 32 -#define CPU_GPIO_IN5_IDX 33 -#define CPU_GPIO_OUT5_IDX 33 -#define CPU_GPIO_IN6_IDX 34 -#define CPU_GPIO_OUT6_IDX 34 -#define CPU_GPIO_IN7_IDX 35 -#define CPU_GPIO_OUT7_IDX 35 -#define USB_JTAG_TCK_IDX 36 -#define USB_JTAG_TMS_IDX 37 -#define USB_JTAG_TDI_IDX 38 -#define USB_JTAG_TDO_IDX 39 -#define USB_EXTPHY_VP_IDX 40 -#define USB_EXTPHY_OEN_IDX 40 -#define USB_EXTPHY_VM_IDX 41 -#define USB_EXTPHY_SPEED_IDX 41 -#define USB_EXTPHY_RCV_IDX 42 -#define USB_EXTPHY_VPO_IDX 42 -#define USB_EXTPHY_VMO_IDX 43 -#define USB_EXTPHY_SUSPND_IDX 44 -#define EXT_ADC_START_IDX 45 -#define LEDC_LS_SIG_OUT0_IDX 45 -#define LEDC_LS_SIG_OUT1_IDX 46 -#define LEDC_LS_SIG_OUT2_IDX 47 -#define LEDC_LS_SIG_OUT3_IDX 48 -#define LEDC_LS_SIG_OUT4_IDX 49 -#define LEDC_LS_SIG_OUT5_IDX 50 -#define RMT_SIG_IN0_IDX 51 -#define RMT_SIG_OUT0_IDX 51 -#define RMT_SIG_IN1_IDX 52 -#define RMT_SIG_OUT1_IDX 52 -#define I2CEXT0_SCL_IN_IDX 53 -#define I2CEXT0_SCL_OUT_IDX 53 -#define I2CEXT0_SDA_IN_IDX 54 -#define I2CEXT0_SDA_OUT_IDX 54 -#define GPIO_SD0_OUT_IDX 55 -#define GPIO_SD1_OUT_IDX 56 -#define GPIO_SD2_OUT_IDX 57 -#define GPIO_SD3_OUT_IDX 58 -#define EVENT_MATRIX_IN0_IDX 59 -#define TASK_MATRIX_OUT0_IDX 59 -#define EVENT_MATRIX_IN1_IDX 60 -#define TASK_MATRIX_OUT1_IDX 60 -#define EVENT_MATRIX_IN2_IDX 61 -#define TASK_MATRIX_OUT2_IDX 61 -#define EVENT_MATRIX_IN3_IDX 62 -#define TASK_MATRIX_OUT3_IDX 62 -#define FSPICLK_IN_IDX 63 -#define FSPICLK_OUT_IDX 63 -#define FSPIQ_IN_IDX 64 -#define FSPIQ_OUT_IDX 64 -#define FSPID_IN_IDX 65 -#define FSPID_OUT_IDX 65 -#define FSPIHD_IN_IDX 66 -#define FSPIHD_OUT_IDX 66 -#define FSPIWP_IN_IDX 67 -#define FSPIWP_OUT_IDX 67 -#define FSPICS0_IN_IDX 68 -#define FSPICS0_OUT_IDX 68 -#define FSPICS1_OUT_IDX 69 -#define FSPICS2_OUT_IDX 70 -#define FSPICS3_OUT_IDX 71 -#define FSPICS4_OUT_IDX 72 -#define FSPICS5_OUT_IDX 73 -#define TWAI_RX_IDX 74 -#define TWAI_TX_IDX 74 -#define TWAI_BUS_OFF_ON_IDX 75 -#define TWAI_CLKOUT_IDX 76 -#define PCMFSYNC_IN_IDX 77 -#define BT_AUDIO0_IRQ_IDX 77 -#define PCMCLK_IN_IDX 78 -#define BT_AUDIO1_IRQ_IDX 78 -#define PCMDIN_IDX 79 -#define BT_AUDIO2_IRQ_IDX 79 -#define RW_WAKEUP_REQ_IDX 80 -#define BLE_AUDIO0_IRQ_IDX 80 -#define BLE_AUDIO1_IRQ_IDX 81 -#define BLE_AUDIO2_IRQ_IDX 82 -#define PCMFSYNC_OUT_IDX 83 -#define PCMCLK_OUT_IDX 84 -#define PCMDOUT_IDX 85 -#define BLE_AUDIO_SYNC0_P_IDX 86 -#define BLE_AUDIO_SYNC1_P_IDX 87 -#define BLE_AUDIO_SYNC2_P_IDX 88 -#define ANT_SEL0_IDX 89 -#define ANT_SEL1_IDX 90 -#define ANT_SEL2_IDX 91 -#define ANT_SEL3_IDX 92 -#define ANT_SEL4_IDX 93 -#define ANT_SEL5_IDX 94 -#define ANT_SEL6_IDX 95 -#define ANT_SEL7_IDX 96 -#define SIG_IN_FUNC_97_IDX 97 -#define SIG_IN_FUNC97_IDX 97 -#define SIG_IN_FUNC_98_IDX 98 -#define SIG_IN_FUNC98_IDX 98 -#define SIG_IN_FUNC_99_IDX 99 -#define SIG_IN_FUNC99_IDX 99 -#define SIG_IN_FUNC_100_IDX 100 -#define SIG_IN_FUNC100_IDX 100 -#define SYNCERR_IDX 101 -#define SYNCFOUND_FLAG_IDX 102 -#define CH_IDX_IDX 103 -#define RX_WINDOW_IDX 104 -#define DATA_EN_IDX 105 -#define DATA_IDX 106 -#define PKT_TX_ON_IDX 107 -#define PKT_RX_ON_IDX 108 -#define TXRU_ON_IDX 109 -#define RXRU_ON_IDX 110 -#define LELC_ST3_IDX 111 -#define LELC_ST2_IDX 112 -#define LELC_ST1_IDX 113 -#define LELC_ST0_IDX 114 -#define CRCOK_IDX 115 -#define CLK_GPIO_IDX 116 -#define RADIO_START_IDX 117 -#define CLK_OUT_OUT1_IDX 123 -#define CLK_OUT_OUT2_IDX 124 -#define CLK_OUT_OUT3_IDX 125 -#define SPICS1_OUT_IDX 126 -#define USB_JTAG_TRST_IDX 127 -#define SIG_GPIO_OUT_IDX 128 -#define GPIO_MAP_DATE_IDX 0x2006130 -#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/gpio_struct.h b/components/soc/esp32h4/include/rev1/soc/gpio_struct.h deleted file mode 100644 index 87cd70a6c3..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/gpio_struct.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configuration register */ -/** Type of bt_select register - * GPIO bit select register - */ -typedef union { - struct { - /** bt_sel : R/W; bitpos: [31:0]; default: 0; - * GPIO bit select register - */ - uint32_t bt_sel:32; - }; - uint32_t val; -} gpio_bt_select_reg_t; - -/** Type of out register - * GPIO output register for GPIO0-31 - */ -typedef union { - struct { - /** out_data_orig : R/W/WS/WC; bitpos: [31:0]; default: 0; - * GPIO output register for GPIO0-31 - */ - uint32_t out_data_orig:32; - }; - uint32_t val; -} gpio_out_reg_t; - -/** Type of out_w1ts register - * GPIO output set register for GPIO0-31 - */ -typedef union { - struct { - /** out_w1ts : WT; bitpos: [31:0]; default: 0; - * GPIO output set register for GPIO0-31 - */ - uint32_t out_w1ts:32; - }; - uint32_t val; -} gpio_out_w1ts_reg_t; - -/** Type of out_w1tc register - * GPIO output clear register for GPIO0-31 - */ -typedef union { - struct { - /** out_w1tc : WT; bitpos: [31:0]; default: 0; - * GPIO output clear register for GPIO0-31 - */ - uint32_t out_w1tc:32; - }; - uint32_t val; -} gpio_out_w1tc_reg_t; - -/** Type of out1 register - * GPIO output register for GPIO32-44 - */ -typedef union { - struct { - /** out1_data_orig : R/W/WS/WC; bitpos: [12:0]; default: 0; - * GPIO output register for GPIO32-44 - */ - uint32_t out1_data_orig:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_out1_reg_t; - -/** Type of out1_w1ts register - * GPIO output set register for GPIO32-44 - */ -typedef union { - struct { - /** out1_w1ts : WT; bitpos: [12:0]; default: 0; - * GPIO output set register for GPIO32-44 - */ - uint32_t out1_w1ts:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_out1_w1ts_reg_t; - -/** Type of out1_w1tc register - * GPIO output clear register for GPIO32-44 - */ -typedef union { - struct { - /** out1_w1tc : WT; bitpos: [12:0]; default: 0; - * GPIO output clear register for GPIO32-44 - */ - uint32_t out1_w1tc:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_out1_w1tc_reg_t; - -/** Type of sdio_select register - * GPIO sdio select register - */ -typedef union { - struct { - /** sdio_sel : R/W; bitpos: [7:0]; default: 0; - * GPIO sdio select register - */ - uint32_t sdio_sel:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_sdio_select_reg_t; - -/** Type of enable register - * GPIO output enable register for GPIO0-31 - */ -typedef union { - struct { - /** enable_data : R/W/SS; bitpos: [31:0]; default: 0; - * GPIO output enable register for GPIO0-31 - */ - uint32_t enable_data:32; - }; - uint32_t val; -} gpio_enable_reg_t; - -/** Type of enable_w1ts register - * GPIO output enable set register for GPIO0-31 - */ -typedef union { - struct { - /** enable_w1ts : WT; bitpos: [31:0]; default: 0; - * GPIO output enable set register for GPIO0-31 - */ - uint32_t enable_w1ts:32; - }; - uint32_t val; -} gpio_enable_w1ts_reg_t; - -/** Type of enable_w1tc register - * GPIO output enable clear register for GPIO0-31 - */ -typedef union { - struct { - /** enable_w1tc : WT; bitpos: [31:0]; default: 0; - * GPIO output enable clear register for GPIO0-31 - */ - uint32_t enable_w1tc:32; - }; - uint32_t val; -} gpio_enable_w1tc_reg_t; - -/** Type of enable1 register - * GPIO output enable register for GPIO32-44 - */ -typedef union { - struct { - /** enable1_data : R/W/SS; bitpos: [12:0]; default: 0; - * GPIO output enable register for GPIO32-44 - */ - uint32_t enable1_data:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_enable1_reg_t; - -/** Type of enable1_w1ts register - * GPIO output enable set register for GPIO32-44 - */ -typedef union { - struct { - /** enable1_w1ts : WT; bitpos: [12:0]; default: 0; - * GPIO output enable set register for GPIO32-44 - */ - uint32_t enable1_w1ts:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_enable1_w1ts_reg_t; - -/** Type of enable1_w1tc register - * GPIO output enable clear register for GPIO32-44 - */ -typedef union { - struct { - /** enable1_w1tc : WT; bitpos: [12:0]; default: 0; - * GPIO output enable clear register for GPIO32-44 - */ - uint32_t enable1_w1tc:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_enable1_w1tc_reg_t; - -/** Type of strap register - * pad strapping register - */ -typedef union { - struct { - /** strapping : RO; bitpos: [15:0]; default: 0; - * pad strapping register - */ - uint32_t strapping:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} gpio_strap_reg_t; - -/** Type of in register - * GPIO input register for GPIO0-31 - */ -typedef union { - struct { - /** in_data_next : RO; bitpos: [31:0]; default: 0; - * GPIO input register for GPIO0-31 - */ - uint32_t in_data_next:32; - }; - uint32_t val; -} gpio_in_reg_t; - -/** Type of in1 register - * GPIO input register for GPIO32-44 - */ -typedef union { - struct { - /** in1_data_next : RO; bitpos: [12:0]; default: 0; - * GPIO input register for GPIO32-44 - */ - uint32_t in1_data_next:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_in1_reg_t; - -/** Type of status register - * GPIO interrupt status register for GPIO0-31 - */ -typedef union { - struct { - /** status_interrupt : R/W/SS; bitpos: [31:0]; default: 0; - * GPIO interrupt status register for GPIO0-31 - */ - uint32_t status_interrupt:32; - }; - uint32_t val; -} gpio_status_reg_t; - -/** Type of status_w1ts register - * GPIO interrupt status set register for GPIO0-31 - */ -typedef union { - struct { - /** status_w1ts : WT; bitpos: [31:0]; default: 0; - * GPIO interrupt status set register for GPIO0-31 - */ - uint32_t status_w1ts:32; - }; - uint32_t val; -} gpio_status_w1ts_reg_t; - -/** Type of status_w1tc register - * GPIO interrupt status clear register for GPIO0-31 - */ -typedef union { - struct { - /** status_w1tc : WT; bitpos: [31:0]; default: 0; - * GPIO interrupt status clear register for GPIO0-31 - */ - uint32_t status_w1tc:32; - }; - uint32_t val; -} gpio_status_w1tc_reg_t; - -/** Type of status1 register - * GPIO interrupt status register for GPIO32-44 - */ -typedef union { - struct { - /** status1_interrupt : R/W/SS; bitpos: [12:0]; default: 0; - * GPIO interrupt status register for GPIO32-44 - */ - uint32_t status1_interrupt:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_status1_reg_t; - -/** Type of status1_w1ts register - * GPIO interrupt status set register for GPIO32-44 - */ -typedef union { - struct { - /** status1_w1ts : WT; bitpos: [12:0]; default: 0; - * GPIO interrupt status set register for GPIO32-44 - */ - uint32_t status1_w1ts:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_status1_w1ts_reg_t; - -/** Type of status1_w1tc register - * GPIO interrupt status clear register for GPIO32-44 - */ -typedef union { - struct { - /** status1_w1tc : WT; bitpos: [12:0]; default: 0; - * GPIO interrupt status clear register for GPIO32-44 - */ - uint32_t status1_w1tc:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_status1_w1tc_reg_t; - -/** Type of pcpu_int register - * GPIO PRO_CPU interrupt status register for GPIO0-31 - */ -typedef union { - struct { - /** procpu_int : RO; bitpos: [31:0]; default: 0; - * GPIO PRO_CPU interrupt status register for GPIO0-31 - */ - uint32_t procpu_int:32; - }; - uint32_t val; -} gpio_pcpu_int_reg_t; - -/** Type of pcpu_nmi_int register - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 - */ -typedef union { - struct { - /** procpu_nmi_int : RO; bitpos: [31:0]; default: 0; - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 - */ - uint32_t procpu_nmi_int:32; - }; - uint32_t val; -} gpio_pcpu_nmi_int_reg_t; - -/** Type of cpusdio_int register - * GPIO CPUSDIO interrupt status register for GPIO0-31 - */ -typedef union { - struct { - /** sdio_int : RO; bitpos: [31:0]; default: 0; - * GPIO CPUSDIO interrupt status register for GPIO0-31 - */ - uint32_t sdio_int:32; - }; - uint32_t val; -} gpio_cpusdio_int_reg_t; - -/** Type of pcpu_int1 register - * GPIO PRO_CPU interrupt status register for GPIO32-44 - */ -typedef union { - struct { - /** procpu_int1 : RO; bitpos: [12:0]; default: 0; - * GPIO PRO_CPU interrupt status register for GPIO32-44 - */ - uint32_t procpu_int1:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_pcpu_int1_reg_t; - -/** Type of pcpu_nmi_int1 register - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 - */ -typedef union { - struct { - /** procpu_nmi_int1 : RO; bitpos: [12:0]; default: 0; - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44 - */ - uint32_t procpu_nmi_int1:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_pcpu_nmi_int1_reg_t; - -/** Type of cpusdio_int1 register - * GPIO CPUSDIO interrupt status register for GPIO32-44 - */ -typedef union { - struct { - /** sdio_int1 : RO; bitpos: [12:0]; default: 0; - * GPIO CPUSDIO interrupt status register for GPIO32-44 - */ - uint32_t sdio_int1:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_cpusdio_int1_reg_t; - -/** Type of pin register - * GPIO pin configuration register - */ -typedef union { - struct { - /** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ - uint32_t pin_sync2_bypass:2; - /** pin_pad_driver : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ - uint32_t pin_pad_driver:1; - /** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ - uint32_t pin_sync1_bypass:2; - uint32_t reserved_5:2; - /** pin_int_type : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ - uint32_t pin_int_type:3; - /** pin_wakeup_enable : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ - uint32_t pin_wakeup_enable:1; - /** pin_config : R/W; bitpos: [12:11]; default: 0; - * reserved - */ - uint32_t pin_config:2; - /** pin_int_ena : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ - uint32_t pin_int_ena:5; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_pin_reg_t; - -/** Type of status_next register - * GPIO interrupt source register for GPIO0-31 - */ -typedef union { - struct { - /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; - * GPIO interrupt source register for GPIO0-31 - */ - uint32_t status_interrupt_next:32; - }; - uint32_t val; -} gpio_status_next_reg_t; - -/** Type of status_next1 register - * GPIO interrupt source register for GPIO32-44 - */ -typedef union { - struct { - /** status_interrupt_next1 : RO; bitpos: [12:0]; default: 0; - * GPIO interrupt source register for GPIO32-44 - */ - uint32_t status_interrupt_next1:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} gpio_status_next1_reg_t; - -/** Type of func_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func_in_sel : R/W; bitpos: [5:0]; default: 0; - * set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func_in_sel:6; - /** func_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func_in_inv_sel:1; - /** sig_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func_in_sel_cfg_reg_t; - -/** Type of func_out_sel_cfg register - * GPIO output function select register - */ -typedef union { - struct { - /** func_out_sel : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ - uint32_t func_out_sel:8; - /** func_out_inv_sel : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ - uint32_t func_out_inv_sel:1; - /** func_oen_sel : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ - uint32_t func_oen_sel:1; - /** func_oen_inv_sel : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ - uint32_t func_oen_inv_sel:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} gpio_func_out_sel_cfg_reg_t; - -/** Type of clock_gate register - * GPIO clock gate register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * set this bit to enable GPIO clock gate - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_clock_gate_reg_t; - -/** Type of reg_date register - * GPIO version register - */ -typedef union { - struct { - /** reg_date : R/W; bitpos: [27:0]; default: 33628944; - * version register - */ - uint32_t reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_reg_date_reg_t; - - -typedef struct { - volatile gpio_bt_select_reg_t bt_select; - volatile gpio_out_reg_t out; - volatile gpio_out_w1ts_reg_t out_w1ts; - volatile gpio_out_w1tc_reg_t out_w1tc; - volatile gpio_out1_reg_t out1; - volatile gpio_out1_w1ts_reg_t out1_w1ts; - volatile gpio_out1_w1tc_reg_t out1_w1tc; - volatile gpio_sdio_select_reg_t sdio_select; - volatile gpio_enable_reg_t enable; - volatile gpio_enable_w1ts_reg_t enable_w1ts; - volatile gpio_enable_w1tc_reg_t enable_w1tc; - volatile gpio_enable1_reg_t enable1; - volatile gpio_enable1_w1ts_reg_t enable1_w1ts; - volatile gpio_enable1_w1tc_reg_t enable1_w1tc; - volatile gpio_strap_reg_t strap; - volatile gpio_in_reg_t in; - volatile gpio_in1_reg_t in1; - volatile gpio_status_reg_t status; - volatile gpio_status_w1ts_reg_t status_w1ts; - volatile gpio_status_w1tc_reg_t status_w1tc; - volatile gpio_status1_reg_t status1; - volatile gpio_status1_w1ts_reg_t status1_w1ts; - volatile gpio_status1_w1tc_reg_t status1_w1tc; - volatile gpio_pcpu_int_reg_t pcpu_int; - volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; - volatile gpio_cpusdio_int_reg_t cpusdio_int; - volatile gpio_pcpu_int1_reg_t pcpu_int1; - volatile gpio_pcpu_nmi_int1_reg_t pcpu_nmi_int1; - volatile gpio_cpusdio_int1_reg_t cpusdio_int1; - volatile gpio_pin_reg_t pin[45]; - uint32_t reserved_128[9]; - volatile gpio_status_next_reg_t status_next; - volatile gpio_status_next1_reg_t status_next1; - volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; - uint32_t reserved_354[128]; - volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[45]; - uint32_t reserved_608[9]; - volatile gpio_clock_gate_reg_t clock_gate; - uint32_t reserved_630[51]; - volatile gpio_reg_date_reg_t reg_date; -} gpio_dev_t; - -extern gpio_dev_t GPIO; - -#ifndef __cplusplus -_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev1/soc/interrupt_core0_reg.h b/components/soc/esp32h4/include/rev1/soc/interrupt_core0_reg.h deleted file mode 100644 index f449ec2a9c..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/interrupt_core0_reg.h +++ /dev/null @@ -1,913 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_INTERRUPT_CORE0_REG_H_ -#define _SOC_INTERRUPT_CORE0_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE - -#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000) -/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S)) -#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004) -/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S)) -#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 - -#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008) -/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S)) -#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C) -/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S)) -#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BB_INT_MAP_S 0 - -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010) -/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 - -#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014) -/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S)) -#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 - -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018) -/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 - -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C) -/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S)) -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 - -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020) -/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)) -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 - -#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024) -/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S)) -#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 - -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028) -/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S)) -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 - -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C) -/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 - -#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030) -/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S)) -#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034) -/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S)) -#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038) -/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S)) -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C) -/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S)) -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040) -/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 - -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044) -/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 - -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048) -/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 - -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C) -/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 - -#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050) -/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S)) -#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 - -#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054) -/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058) -/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S)) -#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C) -/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S)) -#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 - -#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060) -/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S)) -#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 - -#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064) -/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TWAI_INT_MAP_M ((INTERRUPT_CORE0_TWAI_INT_MAP_V)<<(INTERRUPT_CORE0_TWAI_INT_MAP_S)) -#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0 - -#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) -/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S)) -#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C) -/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070) -/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S)) -#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074) -/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078) -/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F -#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S)) -#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F -#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 - -#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C) -/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F -#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S)) -#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F -#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 - -#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080) -/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 - -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084) -/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 - -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088) -/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 - -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C) -/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 - -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090) -/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 - -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094) -/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 - -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) -/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 - -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C) -/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 - -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0) -/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4) -/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 - -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8) -/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 - -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC) -/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 - -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0) -/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 - -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4) -/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0 - -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8) -/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S)) -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0 - -#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC) -/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S)) -#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 - -#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0) -/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S)) -#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_AES_INT_MAP_S 0 - -#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4) -/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S)) -#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4) -/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 - -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8) -/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC) -/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0) -/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4) -/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8) -/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC) -/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0) -/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S)) -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 - -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4) -/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 - -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) -/* INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TG3_T0_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M ((INTERRUPT_CORE0_TG3_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_T0_INT_MAP_S)) -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_S 0 - -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) -/* INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG3_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_WDT_INT_MAP_S)) -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S 0 - -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) -/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S)) -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0 - -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) -/* INTERRUPT_CORE0_IEEE802154MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_M ((INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V)<<(INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S)) -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S 0 - -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) -/* INTERRUPT_CORE0_IEEE802154BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_M ((INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V)<<(INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S)) -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S 0 - -#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) -/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S)) -#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_COEX_INT_MAP_S 0 - -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) -/* INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP 0x0000001F -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M ((INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V)<<(INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S)) -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V 0x1F -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S 0 - -#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) -/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S)) -#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 - -#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) -/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S)) -#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 - -#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) -/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S)) -#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF -#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 - -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) -/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define INTERRUPT_CORE0_CLK_EN (BIT(0)) -#define INTERRUPT_CORE0_CLK_EN_M (BIT(0)) -#define INTERRUPT_CORE0_CLK_EN_V 0x1 -#define INTERRUPT_CORE0_CLK_EN_S 0 - -#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) -/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S)) -#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0 - -#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) -/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S)) -#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0 - -#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) -/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S)) -#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0 - -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) -/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S)) -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) -/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) -/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) -/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) -/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) -/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) -/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) -/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) -/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) -/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) -/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) -/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) -/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) -/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) -/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) -/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) -/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) -/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) -/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C) -/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) -/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) -/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) -/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C) -/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) -/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) -/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) -/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19C) -/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0) -/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4) -/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8) -/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC) -/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0 - -#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0) -/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S)) -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0 -#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) - -#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4) -/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F -#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S)) -#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF -#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0 - -#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) -/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2011090 ; */ -/*description: */ -#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S)) -#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF -#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 - -#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/io_mux_reg.h b/components/soc/esp32h4/include/rev1/soc/io_mux_reg.h deleted file mode 100644 index 45aad3cdb8..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/io_mux_reg.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_IO_MUX_REG_H_ -#define _SOC_IO_MUX_REG_H_ - -#include "soc/soc.h" - -/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ -/* Output enable in sleep mode */ -#define SLP_OE (BIT(0)) -#define SLP_OE_M (BIT(0)) -#define SLP_OE_V 1 -#define SLP_OE_S 0 -/* Pin used for wakeup from sleep */ -#define SLP_SEL (BIT(1)) -#define SLP_SEL_M (BIT(1)) -#define SLP_SEL_V 1 -#define SLP_SEL_S 1 -/* Pulldown enable in sleep mode */ -#define SLP_PD (BIT(2)) -#define SLP_PD_M (BIT(2)) -#define SLP_PD_V 1 -#define SLP_PD_S 2 -/* Pullup enable in sleep mode */ -#define SLP_PU (BIT(3)) -#define SLP_PU_M (BIT(3)) -#define SLP_PU_V 1 -#define SLP_PU_S 3 -/* Input enable in sleep mode */ -#define SLP_IE (BIT(4)) -#define SLP_IE_M (BIT(4)) -#define SLP_IE_V 1 -#define SLP_IE_S 4 -/* Drive strength in sleep mode */ -#define SLP_DRV 0x3 -#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) -#define SLP_DRV_V 0x3 -#define SLP_DRV_S 5 -/* Pulldown enable */ -#define FUN_PD (BIT(7)) -#define FUN_PD_M (BIT(7)) -#define FUN_PD_V 1 -#define FUN_PD_S 7 -/* Pullup enable */ -#define FUN_PU (BIT(8)) -#define FUN_PU_M (BIT(8)) -#define FUN_PU_V 1 -#define FUN_PU_S 8 -/* Input enable */ -#define FUN_IE (BIT(9)) -#define FUN_IE_M (FUN_IE_V << FUN_IE_S) -#define FUN_IE_V 1 -#define FUN_IE_S 9 -/* Drive strength */ -#define FUN_DRV 0x3 -#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) -#define FUN_DRV_V 0x3 -#define FUN_DRV_S 10 -/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ -#define MCU_SEL 0x7 -#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) -#define MCU_SEL_V 0x7 -#define MCU_SEL_S 12 -/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ -#define FILTER_EN (BIT(15)) -#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) -#define FILTER_EN_V 1 -#define FILTER_EN_S 15 - -#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) -#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) - - -#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); -#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) -#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) -#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) -#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) - -#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U -#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U -#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U -#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U -#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U -#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U -#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U -#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U -#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U -#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U -#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U -#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U -#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U -#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U -#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U -#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U -#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U -#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U -#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U -#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U -#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U -#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U -#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U -#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U -#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U -#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U -#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U -#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U -#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_GPIO28_U -#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U -#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_GPIO30_U -#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_GPIO31_U -#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U -#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U -#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U -#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U -#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U -#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U -#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U -#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U -#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_GPIO40_U - -/* Value to set in IO Mux to use a pin as GPIO. */ -#define PIN_FUNC_GPIO 1 - -#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) - -#define SPI_HD_GPIO_NUM 12 -#define SPI_WP_GPIO_NUM 13 -#define SPI_CS0_GPIO_NUM 14 -#define SPI_CLK_GPIO_NUM 15 -#define SPI_D_GPIO_NUM 16 -#define SPI_Q_GPIO_NUM 17 - -#define SD_CLK_GPIO_NUM 12 -#define SD_CMD_GPIO_NUM 11 -#define SD_DATA0_GPIO_NUM 13 -#define SD_DATA1_GPIO_NUM 14 -#define SD_DATA2_GPIO_NUM 9 -#define SD_DATA3_GPIO_NUM 10 - -#define USB_DM_GPIO_NUM 18 -#define USB_DP_GPIO_NUM 19 - -#define XTAL32K_P_GPIO_NUM 0 -#define XTAL32K_N_GPIO_NUM 1 - -#define MAX_RTC_GPIO_NUM 5 -#define MAX_PAD_GPIO_NUM 40 -#define MAX_GPIO_NUM 44 - -#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE -#define PIN_CTRL (REG_IO_MUX_BASE +0x00) -#define PAD_POWER_SEL BIT(15) -#define PAD_POWER_SEL_V 0x1 -#define PAD_POWER_SEL_M BIT(15) -#define PAD_POWER_SEL_S 15 - - -#define PAD_POWER_SWITCH_DELAY 0x7 -#define PAD_POWER_SWITCH_DELAY_V 0x7 -#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) -#define PAD_POWER_SWITCH_DELAY_S 12 - - -#define CLK_OUT3 0xf -#define CLK_OUT3_V CLK_OUT3 -#define CLK_OUT3_S 8 -#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) -#define CLK_OUT2 0xf -#define CLK_OUT2_V CLK_OUT2 -#define CLK_OUT2_S 4 -#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) -#define CLK_OUT1 0xf -#define CLK_OUT1_V CLK_OUT1 -#define CLK_OUT1_S 0 -#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) - -#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x04) -#define FUNC_XTAL_32K_P_GPIO0 1 -#define FUNC_XTAL_32K_P_GPIO0_0 0 - -#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x08) -#define FUNC_XTAL_32K_N_GPIO1 1 -#define FUNC_XTAL_32K_N_GPIO1_0 0 - -#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c) -#define FUNC_GPIO2_FSPIQ 2 -#define FUNC_GPIO2_GPIO2 1 -#define FUNC_GPIO2_GPIO2_0 0 - -#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10) -#define FUNC_GPIO3_GPIO3 1 -#define FUNC_GPIO3_GPIO3_0 0 - -#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0x14) -#define FUNC_MTMS_FSPIHD 2 -#define FUNC_MTMS_GPIO4 1 -#define FUNC_MTMS_MTMS 0 - -#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0x18) -#define FUNC_MTDI_FSPIWP 2 -#define FUNC_MTDI_GPIO5 1 -#define FUNC_MTDI_MTDI 0 - -#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0x1c) -#define FUNC_MTCK_FSPICLK 2 -#define FUNC_MTCK_GPIO6 1 -#define FUNC_MTCK_MTCK 0 - -#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0x20) -#define FUNC_MTDO_FSPID 2 -#define FUNC_MTDO_GPIO7 1 -#define FUNC_MTDO_MTDO 0 - -#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24) -#define FUNC_GPIO8_GPIO8 1 -#define FUNC_GPIO8_GPIO8_0 0 - -#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) -#define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_GPIO9_0 0 - -#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) -#define FUNC_GPIO10_FSPICS0 2 -#define FUNC_GPIO10_GPIO10 1 -#define FUNC_GPIO10_GPIO10_0 0 - -#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE +0x30) -#define FUNC_VDD_SPI_GPIO11 1 -#define FUNC_VDD_SPI_GPIO11_0 0 - -#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x34) -#define FUNC_SPIHD_GPIO12 1 -#define FUNC_SPIHD_SPIHD 0 - -#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x38) -#define FUNC_SPIWP_GPIO13 1 -#define FUNC_SPIWP_SPIWP 0 - -#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x3c) -#define FUNC_SPICS0_GPIO14 1 -#define FUNC_SPICS0_SPICS0 0 - -#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x40) -#define FUNC_SPICLK_GPIO15 1 -#define FUNC_SPICLK_SPICLK 0 - -#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x44) -#define FUNC_SPID_GPIO16 1 -#define FUNC_SPID_SPID 0 - -#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x48) -#define FUNC_SPIQ_GPIO17 1 -#define FUNC_SPIQ_SPIQ 0 - -#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE +0x4c) -#define FUNC_GPIO18_GPIO18 1 -#define FUNC_GPIO18_GPIO18_0 0 - -#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50) -#define FUNC_GPIO19_GPIO19 1 -#define FUNC_GPIO19_GPIO19_0 0 - -#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0x54) -#define FUNC_U0RXD_GPIO20 1 -#define FUNC_U0RXD_U0RXD 0 - -#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0x58) -#define FUNC_U0TXD_GPIO21 1 -#define FUNC_U0TXD_U0TXD 0 - -#define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE +0x5c) -#define FUNC_GPIO22_GPIO22 1 -#define FUNC_GPIO22_GPIO22_0 0 - -#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE +0x60) -#define FUNC_GPIO23_GPIO23 1 -#define FUNC_GPIO23_GPIO23_0 0 - -#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE +0x64) -#define FUNC_GPIO24_GPIO24 1 -#define FUNC_GPIO24_GPIO24_0 0 - -#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE +0x68) -#define FUNC_GPIO25_GPIO25 1 -#define FUNC_GPIO25_GPIO25_0 0 - -#define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE +0x6c) -#define FUNC_GPIO26_GPIO26 1 -#define FUNC_GPIO26_GPIO26_0 0 - -#define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE +0x70) -#define FUNC_GPIO27_GPIO27 1 -#define FUNC_GPIO27_GPIO27_0 0 - -#define PERIPHS_IO_MUX_GPIO28_U (REG_IO_MUX_BASE +0x74) -#define FUNC_GPIO28_GPIO28 1 -#define FUNC_GPIO28_GPIO28_0 0 - -#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE +0x78) -#define FUNC_GPIO29_GPIO29 1 -#define FUNC_GPIO29_GPIO29_0 0 - -#define PERIPHS_IO_MUX_GPIO30_U (REG_IO_MUX_BASE +0x7c) -#define FUNC_GPIO30_GPIO30 1 -#define FUNC_GPIO30_GPIO30_0 0 - -#define PERIPHS_IO_MUX_GPIO31_U (REG_IO_MUX_BASE +0x80) -#define FUNC_GPIO31_GPIO31 1 -#define FUNC_GPIO31_GPIO31_0 0 - -#define PERIPHS_IO_MUX_GPIO32_U (REG_IO_MUX_BASE +0x84) -#define FUNC_GPIO32_GPIO32 1 -#define FUNC_GPIO32_GPIO32_0 0 - -#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) -#define FUNC_GPIO33_GPIO33 1 -#define FUNC_GPIO33_GPIO33_0 0 - -#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) -#define FUNC_GPIO34_GPIO34 1 -#define FUNC_GPIO34_GPIO34_0 0 - -#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) -#define FUNC_GPIO35_GPIO35 1 -#define FUNC_GPIO35_GPIO35_0 0 - -#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) -#define FUNC_GPIO36_GPIO36 1 -#define FUNC_GPIO36_GPIO36_0 0 - -#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) -#define FUNC_GPIO37_GPIO37 1 -#define FUNC_GPIO37_GPIO37_0 0 - -#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) -#define FUNC_GPIO38_GPIO38 1 -#define FUNC_GPIO38_GPIO38_0 0 - -#define PERIPHS_IO_MUX_GPIO39_U (REG_IO_MUX_BASE +0xa0) -#define FUNC_GPIO39_GPIO39 1 -#define FUNC_GPIO39_GPIO39_0 0 - -#define PERIPHS_IO_MUX_GPIO40_U (REG_IO_MUX_BASE +0xa4) -#define FUNC_GPIO40_GPIO40 1 -#define FUNC_GPIO40_GPIO40_0 0 - -/** IO_MUX_DATE_REG register - * IO MUX Version Control Register - */ -#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc) -/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 33628944; - * Version control register - */ -#define IO_MUX_REG_DATE 0x0FFFFFFFU -#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) -#define IO_MUX_REG_DATE_V 0x0FFFFFFFU -#define IO_MUX_REG_DATE_S 0 -#define IO_MUX_DATE_VERSION 0x2012310 - -#endif diff --git a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h b/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h deleted file mode 100644 index f079d1240c..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_reg.h +++ /dev/null @@ -1,3173 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_RTC_CNTL_REG_H_ -#define _SOC_RTC_CNTL_REG_H_ - -/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ -#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 -/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ -#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A - -/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ -#define RTC_WDT_RESET_LENGTH_100_NS 0 -#define RTC_WDT_RESET_LENGTH_200_NS 1 -#define RTC_WDT_RESET_LENGTH_300_NS 2 -#define RTC_WDT_RESET_LENGTH_400_NS 3 -#define RTC_WDT_RESET_LENGTH_500_NS 4 -#define RTC_WDT_RESET_LENGTH_800_NS 5 -#define RTC_WDT_RESET_LENGTH_1600_NS 6 -#define RTC_WDT_RESET_LENGTH_3200_NS 7 - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG -#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG - -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) -/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: SW system reset*/ -#define RTC_CNTL_SW_SYS_RST (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_V 0x1 -#define RTC_CNTL_SW_SYS_RST_S 31 -/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force no reset in deep sleep*/ -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 -/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: digital wrap force reset in deep sleep*/ -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 -/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 -#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 -/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_PLL_FORCE_NOISO_S 27 -/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_XTL_FORCE_NOISO_S 26 -/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 -#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 -/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 -#define RTC_CNTL_PLL_FORCE_ISO_S 24 -/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 -#define RTC_CNTL_XTL_FORCE_ISO_S 23 -/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 -#define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) -#define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 -#define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 -/* RTC_CNTL_XPD_RFPLL_FORCE : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XPD_RFPLL_FORCE (BIT(19)) -#define RTC_CNTL_XPD_RFPLL_FORCE_M (BIT(19)) -#define RTC_CNTL_XPD_RFPLL_FORCE_V 0x1 -#define RTC_CNTL_XPD_RFPLL_FORCE_S 19 -/* RTC_CNTL_XPD_RFPLL : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XPD_RFPLL (BIT(18)) -#define RTC_CNTL_XPD_RFPLL_M (BIT(18)) -#define RTC_CNTL_XPD_RFPLL_V 0x1 -#define RTC_CNTL_XPD_RFPLL_S 18 -/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ -/*description: wait bias_sleep and current source wakeup*/ -#define RTC_CNTL_XTL_EN_WAIT 0x0000000F -#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) -#define RTC_CNTL_XTL_EN_WAIT_V 0xF -#define RTC_CNTL_XTL_EN_WAIT_S 14 -/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ -/*description: crystall force power up*/ -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_V 0x1 -#define RTC_CNTL_XTL_FORCE_PU_S 13 -/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: crystall force power down*/ -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_V 0x1 -#define RTC_CNTL_XTL_FORCE_PD_S 12 -/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: BB_PLL force power up*/ -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 -#define RTC_CNTL_BBPLL_FORCE_PU_S 11 -/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: BB_PLL force power down*/ -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 -#define RTC_CNTL_BBPLL_FORCE_PD_S 10 -/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: BB_PLL_I2C force power up*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 -/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: BB_PLL _I2C force power down*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 -/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: BB_I2C force power up*/ -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 -/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: BB_I2C force power down*/ -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 -/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: PRO CPU SW reset*/ -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_V 0x1 -#define RTC_CNTL_SW_PROCPU_RST_S 5 -/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: APP CPU SW reset*/ -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_V 0x1 -#define RTC_CNTL_SW_APPCPU_RST_S 4 -/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == - 0x86 will stall PRO CPU*/ -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) -#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 -#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 -/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == - 0x86 will stall APP CPU*/ -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) -#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 -#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 - -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) -/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) -#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_S 0 - -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) -/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: timer alarm enable bit*/ -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 -/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC sleep timer high 16 bits*/ -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF -#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) -#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF -#define RTC_CNTL_SLP_VAL_HI_S 0 - -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) -/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set 1: to update register with RTC timer*/ -#define RTC_CNTL_TIME_UPDATE (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_V 0x1 -#define RTC_CNTL_TIME_UPDATE_S 31 -/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: enable to record system reset time*/ -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_V 0x1 -#define RTC_CNTL_TIMER_SYS_RST_S 29 -/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Enable to record 40M XTAL OFF time*/ -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 -#define RTC_CNTL_TIMER_XTL_OFF_S 28 -/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Enable to record system stall time*/ -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 -#define RTC_CNTL_TIMER_SYS_STALL_S 27 - -#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) -/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits*/ -#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) -#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 - -#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) -/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits*/ -#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) -#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF -#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 - -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) -/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: sleep enable bit*/ -#define RTC_CNTL_SLEEP_EN (BIT(31)) -#define RTC_CNTL_SLEEP_EN_M (BIT(31)) -#define RTC_CNTL_SLEEP_EN_V 0x1 -#define RTC_CNTL_SLEEP_EN_S 31 -/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: leep reject bit*/ -#define RTC_CNTL_SLP_REJECT (BIT(30)) -#define RTC_CNTL_SLP_REJECT_M (BIT(30)) -#define RTC_CNTL_SLP_REJECT_V 0x1 -#define RTC_CNTL_SLP_REJECT_S 30 -/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: leep wakeup bit*/ -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_S 29 -/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: SDIO active indication*/ -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 -#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 -/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: APB to RTC using bridge*/ -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 -/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear rtc sleep reject cause*/ -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 -/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rtc software interrupt to main cpu*/ -#define RTC_CNTL_SW_CPU_INT (BIT(0)) -#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) -#define RTC_CNTL_SW_CPU_INT_V 0x1 -#define RTC_CNTL_SW_CPU_INT_S 0 - -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) -/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ -/*description: PLL wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF -#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) -#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF -#define RTC_CNTL_PLL_BUF_WAIT_S 24 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 -/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ -/*description: XTAL wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF -#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) -#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF -#define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 -/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ -/*description: CK8M wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_CK8M_WAIT 0x000000FF -#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) -#define RTC_CNTL_CK8M_WAIT_V 0xFF -#define RTC_CNTL_CK8M_WAIT_S 6 -/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ -/*description: CPU stall wait cycles in fast_clk_rtc*/ -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F -#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) -#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F -#define RTC_CNTL_CPU_STALL_WAIT_S 1 -/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: CPU stall enable bit*/ -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_V 0x1 -#define RTC_CNTL_CPU_STALL_EN_S 0 - -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) -/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ -/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) -#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 - -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) -/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) -#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_BT_POWERUP_TIMER_S 25 -/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF -#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) -#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_BT_WAIT_TIMER_S 16 -/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) -#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 -/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) -#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 - -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) -/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 -/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 -/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 -/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 - -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) -/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ -/*description: minimal sleep cycles in slow_clk_rtc*/ -#define RTC_CNTL_MIN_SLP_VAL 0x000000FF -#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) -#define RTC_CNTL_MIN_SLP_VAL_V 0xFF -#define RTC_CNTL_MIN_SLP_VAL_S 8 - -#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) -/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 -/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) -#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 - -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) -/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_V 0x1 -#define RTC_CNTL_PLL_I2C_PU_S 31 -/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: CKGEN_I2C power up*/ -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 -#define RTC_CNTL_CKGEN_I2C_PU_S 30 -/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: 1: RFRX_PBUS power up*/ -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 -#define RTC_CNTL_RFRX_PBUS_PU_S 28 -/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: 1: TXRF_I2C power up*/ -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_V 0x1 -#define RTC_CNTL_TXRF_I2C_PU_S 27 -/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: PVTMON power up*/ -#define RTC_CNTL_PVTMON_PU (BIT(26)) -#define RTC_CNTL_PVTMON_PU_M (BIT(26)) -#define RTC_CNTL_PVTMON_PU_V 0x1 -#define RTC_CNTL_PVTMON_PU_S 26 -/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: start BBPLL calibration during sleep*/ -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 -#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 -/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: PLLA force power up*/ -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PU_S 24 -/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: PLLA force power down*/ -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PD_S 23 -/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: PLLA force power up*/ -#define RTC_CNTL_SAR_I2C_PU (BIT(22)) -#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) -#define RTC_CNTL_SAR_I2C_PU_V 0x1 -#define RTC_CNTL_SAR_I2C_PU_S 22 -/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_V 0x1 -#define RTC_CNTL_GLITCH_RST_EN_S 20 -/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 -/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 -/* RTC_CNTL_XPD_TRX_FORCE_PU : R/W ;bitpos:[17] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_XPD_TRX_FORCE_PU (BIT(17)) -#define RTC_CNTL_XPD_TRX_FORCE_PU_M (BIT(17)) -#define RTC_CNTL_XPD_TRX_FORCE_PU_V 0x1 -#define RTC_CNTL_XPD_TRX_FORCE_PU_S 17 -/* RTC_CNTL_XPD_TRX_FORCE_PD : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XPD_TRX_FORCE_PD (BIT(16)) -#define RTC_CNTL_XPD_TRX_FORCE_PD_M (BIT(16)) -#define RTC_CNTL_XPD_TRX_FORCE_PD_V 0x1 -#define RTC_CNTL_XPD_TRX_FORCE_PD_S 16 - -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) -/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) -#define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) -#define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 -#define RTC_CNTL_DRESET_MASK_PROCPU_S 25 -/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) -#define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) -#define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 -#define RTC_CNTL_DRESET_MASK_APPCPU_S 24 -/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 -/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 -/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 -/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 -/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: PROCPU OcdHaltOnReset*/ -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 -/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: APPCPU OcdHaltOnReset*/ -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 -/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: clear APP CPU reset flag*/ -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 -/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: clear PRO CPU reset_flag*/ -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 -/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: APP CPU reset flag*/ -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 -/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: PRO CPU reset_flag*/ -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 -/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: PRO CPU state vector sel*/ -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 -/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: APP CPU state vector sel*/ -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 -/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ -/*description: reset cause of APP CPU*/ -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) -#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F -#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 -/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ -/*description: reset cause of PRO CPU*/ -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) -#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F -#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 - -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) -/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:13] ;default: 18'b1100 ; */ -/*description: wakeup enable bitmap*/ -#define RTC_CNTL_WAKEUP_ENA 0x0007FFFF -#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) -#define RTC_CNTL_WAKEUP_ENA_V 0x7FFFF -#define RTC_CNTL_WAKEUP_ENA_S 13 - -#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) -/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_M (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_V 0x1 -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_S 22 -/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA : ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_M (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_V 0x1 -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_S 21 -/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 -#define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 -/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 -/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 -/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_V 0x1 -#define RTC_CNTL_SWD_INT_ENA_S 15 -/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 -/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 -/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_S 3 -/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 -/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 - -#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) -/* RTC_CNTL_VSET_DCDC_DONE_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_M (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_V 0x1 -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_S 22 -/* RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_M (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_V 0x1 -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_S 21 -/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 -#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 -/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt_raw*/ -#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 -/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt raw*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 -/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt raw*/ -#define RTC_CNTL_SWD_INT_RAW (BIT(15)) -#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) -#define RTC_CNTL_SWD_INT_RAW_V 0x1 -#define RTC_CNTL_SWD_INT_RAW_S 15 -/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt raw*/ -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 -/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt raw*/ -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 -/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt raw*/ -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_V 0x1 -#define RTC_CNTL_WDT_INT_RAW_S 3 -/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt raw*/ -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 -/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt raw*/ -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 - -#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) -/* RTC_CNTL_VSET_DCDC_DONE_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_M (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_V 0x1 -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_S 22 -/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_M (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_V 0x1 -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_S 21 -/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 -#define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 -/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt state*/ -#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 -/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt state*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 -/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt state*/ -#define RTC_CNTL_SWD_INT_ST (BIT(15)) -#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ST_V 0x1 -#define RTC_CNTL_SWD_INT_ST_S 15 -/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt state*/ -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 -/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt state*/ -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 -/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt state*/ -#define RTC_CNTL_WDT_INT_ST (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_V 0x1 -#define RTC_CNTL_WDT_INT_ST_S 3 -/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt state*/ -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 -/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt state*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 - -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) -/* RTC_CNTL_VSET_DCDC_DONE_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_M (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_V 0x1 -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_S 22 -/* RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_M (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_V 0x1 -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_S 21 -/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 -#define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 -/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Clear glitch det interrupt state*/ -#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 -/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 -/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Clear super watch dog interrupt state*/ -#define RTC_CNTL_SWD_INT_CLR (BIT(15)) -#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) -#define RTC_CNTL_SWD_INT_CLR_V 0x1 -#define RTC_CNTL_SWD_INT_CLR_S 15 -/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Clear RTC main timer interrupt state*/ -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 -/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Clear brown out interrupt state*/ -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 -/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state*/ -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_V 0x1 -#define RTC_CNTL_WDT_INT_CLR_S 3 -/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Clear sleep reject interrupt state*/ -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 -/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Clear sleep wakeup interrupt state*/ -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 - -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) -/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH0 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) -#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_S 0 - -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) -/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH1 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) -#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_S 0 - -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) -/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH2 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) -#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_S 0 - -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) -/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH3 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) -#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_S 0 - -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) -/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 -#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 -/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: power down XTAL at high level*/ -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 -#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 -/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: XTAL_32K sel. 0: external XTAL_32K*/ -#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) -#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) -#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 -#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 -/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: state of 32k_wdt*/ -#define RTC_CNTL_WDT_STATE 0x00000007 -#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) -#define RTC_CNTL_WDT_STATE_V 0x7 -#define RTC_CNTL_WDT_STATE_S 20 -/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ -/*description: DAC_XTAL_32K*/ -#define RTC_CNTL_DAC_XTAL_32K 0x00000007 -#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) -#define RTC_CNTL_DAC_XTAL_32K_V 0x7 -#define RTC_CNTL_DAC_XTAL_32K_S 17 -/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: XPD_XTAL_32K*/ -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_V 0x1 -#define RTC_CNTL_XPD_XTAL_32K_S 16 -/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ -/*description: DRES_XTAL_32K*/ -#define RTC_CNTL_DRES_XTAL_32K 0x00000007 -#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) -#define RTC_CNTL_DRES_XTAL_32K_V 0x7 -#define RTC_CNTL_DRES_XTAL_32K_S 13 -/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: xtal_32k gm control*/ -#define RTC_CNTL_DGM_XTAL_32K 0x00000007 -#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) -#define RTC_CNTL_DGM_XTAL_32K_V 0x7 -#define RTC_CNTL_DGM_XTAL_32K_S 10 -/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 0: single-end buffer 1: differential buffer*/ -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 -#define RTC_CNTL_DBUF_XTAL_32K_S 9 -/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: apply an internal clock to help xtal 32k to start*/ -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 -#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 -/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: Xtal 32k xpd control by sw or fsm*/ -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 -#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 -/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: xtal 32k switch back xtal when xtal is restarted*/ -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 -#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 -/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: xtal 32k restart xtal when xtal is dead*/ -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 -#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 -/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: xtal 32k switch to back up clock when xtal is dead*/ -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 -/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: xtal 32k external xtal clock force on*/ -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 -/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog sw reset*/ -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 -#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 -/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog clock force on*/ -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 -/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog enable*/ -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 -#define RTC_CNTL_XTAL32K_WDT_EN_S 0 - -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) -/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable filter for gpio wakeup event*/ -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 - -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) -/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable reject for deep sleep*/ -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 -#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 -/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: enable reject for light sleep*/ -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 -/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:11] ;default: 18'd0 ; */ -/*description: sleep reject enable*/ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0007FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) -#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x7FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_S 11 - -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) -/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ -/*description: */ -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 -#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) -#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 -#define RTC_CNTL_CPUPERIOD_SEL_S 30 -/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: CPU sel option*/ -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_V 0x1 -#define RTC_CNTL_CPUSEL_CONF_S 29 - -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) -/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) -#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 -#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 -/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: fast_clk_rtc sel. 0: XTAL div 2*/ -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 -#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 -/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 -/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 -/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: CK8M force power up*/ -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 -#define RTC_CNTL_CK8M_FORCE_PU_S 26 -/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: CK8M force power down*/ -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 -#define RTC_CNTL_CK8M_FORCE_PD_S 25 -/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:15] ;default: 10'd600 ; */ -/*description: CK8M_DFREQ*/ -#define RTC_CNTL_CK8M_DFREQ 0x000003FF -#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) -#define RTC_CNTL_CK8M_DFREQ_V 0x3FF -#define RTC_CNTL_CK8M_DFREQ_S 15 -/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: CK8M force no gating during sleep*/ -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(14)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(14)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 14 -/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: XTAL force no gating during sleep*/ -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(13)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(13)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 13 -/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: divider = reg_ck8m_div_sel + 1*/ -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) -#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 -#define RTC_CNTL_CK8M_DIV_SEL_S 10 -/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: enable CK8M for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_EN (BIT(6)) -#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(6)) -#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_EN_S 6 -/* RTC_CNTL_DIG_RC32K_EN : R/W ;bitpos:[5] ;default: 1'd1 ; */ -/*description: enable RC32K for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_RC32K_EN (BIT(5)) -#define RTC_CNTL_DIG_RC32K_EN_M (BIT(5)) -#define RTC_CNTL_DIG_RC32K_EN_V 0x1 -#define RTC_CNTL_DIG_RC32K_EN_S 5 -/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(4)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(4)) -#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 -#define RTC_CNTL_DIG_XTAL32K_EN_S 4 -/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 -#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 -/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 -/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 -/* RTC_CNTL_BLE_TMR_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_TMR_RST (BIT(0)) -#define RTC_CNTL_BLE_TMR_RST_M (BIT(0)) -#define RTC_CNTL_BLE_TMR_RST_V 0x1 -#define RTC_CNTL_BLE_TMR_RST_S 0 - -#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) -/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 -/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_DIV 0x000000FF -#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) -#define RTC_CNTL_ANA_CLK_DIV_V 0xFF -#define RTC_CNTL_ANA_CLK_DIV_S 23 -/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ -#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) -#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) -#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 -#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 -/* RTC_CNTL_ANA_CLK_PD_IDLE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_PD_IDLE (BIT(21)) -#define RTC_CNTL_ANA_CLK_PD_IDLE_M (BIT(21)) -#define RTC_CNTL_ANA_CLK_PD_IDLE_V 0x1 -#define RTC_CNTL_ANA_CLK_PD_IDLE_S 21 -/* RTC_CNTL_ANA_CLK_PD_MONITOR : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_PD_MONITOR (BIT(20)) -#define RTC_CNTL_ANA_CLK_PD_MONITOR_M (BIT(20)) -#define RTC_CNTL_ANA_CLK_PD_MONITOR_V 0x1 -#define RTC_CNTL_ANA_CLK_PD_MONITOR_S 20 -/* RTC_CNTL_ANA_CLK_PD_SLP : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_PD_SLP (BIT(19)) -#define RTC_CNTL_ANA_CLK_PD_SLP_M (BIT(19)) -#define RTC_CNTL_ANA_CLK_PD_SLP_V 0x1 -#define RTC_CNTL_ANA_CLK_PD_SLP_S 19 - -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) -/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_V 0x1 -#define RTC_CNTL_XPD_SDIO_REG_S 31 -/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ -/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFH_SDIO 0x00000003 -#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) -#define RTC_CNTL_DREFH_SDIO_V 0x3 -#define RTC_CNTL_DREFH_SDIO_S 29 -/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ -/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFM_SDIO 0x00000003 -#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) -#define RTC_CNTL_DREFM_SDIO_V 0x3 -#define RTC_CNTL_DREFM_SDIO_S 27 -/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ -/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFL_SDIO 0x00000003 -#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) -#define RTC_CNTL_DREFL_SDIO_V 0x3 -#define RTC_CNTL_DREFL_SDIO_S 25 -/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: read only register for REG1P8_READY*/ -#define RTC_CNTL_REG1P8_READY (BIT(24)) -#define RTC_CNTL_REG1P8_READY_M (BIT(24)) -#define RTC_CNTL_REG1P8_READY_V 0x1 -#define RTC_CNTL_REG1P8_READY_S 24 -/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_SDIO_TIEH (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_V 0x1 -#define RTC_CNTL_SDIO_TIEH_S 23 -/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: use SW option to control SDIO_REG*/ -#define RTC_CNTL_SDIO_FORCE (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_V 0x1 -#define RTC_CNTL_SDIO_FORCE_S 22 -/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ -/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ -#define RTC_CNTL_SDIO_PD_EN (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_V 0x1 -#define RTC_CNTL_SDIO_PD_EN_S 21 -/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: enable current limit*/ -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 -#define RTC_CNTL_SDIO_ENCURLIM_S 20 -/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: select current limit mode*/ -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 -#define RTC_CNTL_SDIO_MODECURLIM_S 19 -/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ -/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ -#define RTC_CNTL_SDIO_DCURLIM 0x00000007 -#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) -#define RTC_CNTL_SDIO_DCURLIM_V 0x7 -#define RTC_CNTL_SDIO_DCURLIM_S 16 -/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: 0 to set init[1:0]=0*/ -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_V 0x1 -#define RTC_CNTL_SDIO_EN_INITI_S 15 -/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ -/*description: add resistor from ldo output to ground. 0: no res*/ -#define RTC_CNTL_SDIO_INITI 0x00000003 -#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) -#define RTC_CNTL_SDIO_INITI_V 0x3 -#define RTC_CNTL_SDIO_INITI_S 13 -/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ -/*description: ability to prevent LDO from overshoot*/ -#define RTC_CNTL_SDIO_DCAP 0x00000003 -#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) -#define RTC_CNTL_SDIO_DCAP_V 0x3 -#define RTC_CNTL_SDIO_DCAP_S 11 -/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ -/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ -#define RTC_CNTL_SDIO_DTHDRV 0x00000003 -#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) -#define RTC_CNTL_SDIO_DTHDRV_V 0x3 -#define RTC_CNTL_SDIO_DTHDRV_S 9 -/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ -/*description: timer count to apply reg_sdio_dcap after sdio power on*/ -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF -#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) -#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF -#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 - -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) -/* RTC_CNTL_XPD_DCDC_IDLE : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_XPD_DCDC_IDLE (BIT(28)) -#define RTC_CNTL_XPD_DCDC_IDLE_M (BIT(28)) -#define RTC_CNTL_XPD_DCDC_IDLE_V 0x1 -#define RTC_CNTL_XPD_DCDC_IDLE_S 28 -/* RTC_CNTL_XPD_DCDC_MONITOR : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_XPD_DCDC_MONITOR (BIT(27)) -#define RTC_CNTL_XPD_DCDC_MONITOR_M (BIT(27)) -#define RTC_CNTL_XPD_DCDC_MONITOR_V 0x1 -#define RTC_CNTL_XPD_DCDC_MONITOR_S 27 -/* RTC_CNTL_XPD_DCDC_SLP : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_XPD_DCDC_SLP (BIT(26)) -#define RTC_CNTL_XPD_DCDC_SLP_M (BIT(26)) -#define RTC_CNTL_XPD_DCDC_SLP_V 0x1 -#define RTC_CNTL_XPD_DCDC_SLP_S 26 -/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in monitor state*/ -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F -#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) -#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF -#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 -/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in sleep state*/ -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 -/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: bias_sleep when rtc in monitor state*/ -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 -#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 -/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: bias_sleep when rtc in sleep_state*/ -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 -/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in monitor state*/ -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 -#define RTC_CNTL_PD_CUR_MONITOR_S 15 -/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in sleep_state*/ -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 -#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 -/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 -#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 -/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 -/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 -#define RTC_CNTL_BIAS_BUF_WAKE_S 11 -/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 -#define RTC_CNTL_BIAS_BUF_IDLE_S 10 - -#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) -/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) -#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 -#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 -/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: RTC_REG force power down (for RTC_REG power down means decrease - the voltage to 0.8v or lower )*/ -#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) -#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 -#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 -/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: RTC_DBOOST force power up*/ -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 -#define RTC_CNTL_DBOOST_FORCE_PU_S 29 -/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RTC_DBOOST force power down*/ -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 -#define RTC_CNTL_DBOOST_FORCE_PD_S 28 -/* RTC_CNTL_VDD_DRV_B_SLP_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VDD_DRV_B_SLP_EN (BIT(27)) -#define RTC_CNTL_VDD_DRV_B_SLP_EN_M (BIT(27)) -#define RTC_CNTL_VDD_DRV_B_SLP_EN_V 0x1 -#define RTC_CNTL_VDD_DRV_B_SLP_EN_S 27 -/* RTC_CNTL_VDD_DRV_B_SLP : R/W ;bitpos:[26:21] ;default: 6'd0 ; */ -/*description: */ -#define RTC_CNTL_VDD_DRV_B_SLP 0x0000003F -#define RTC_CNTL_VDD_DRV_B_SLP_M ((RTC_CNTL_VDD_DRV_B_SLP_V)<<(RTC_CNTL_VDD_DRV_B_SLP_S)) -#define RTC_CNTL_VDD_DRV_B_SLP_V 0x3F -#define RTC_CNTL_VDD_DRV_B_SLP_S 21 -/* RTC_CNTL_VDD_DRV_B_ACTIVE : R/W ;bitpos:[20:15] ;default: 6'd0 ; */ -/*description: SCK_DCAP*/ -#define RTC_CNTL_VDD_DRV_B_ACTIVE 0x0000003F -#define RTC_CNTL_VDD_DRV_B_ACTIVE_M ((RTC_CNTL_VDD_DRV_B_ACTIVE_V)<<(RTC_CNTL_VDD_DRV_B_ACTIVE_S)) -#define RTC_CNTL_VDD_DRV_B_ACTIVE_V 0x3F -#define RTC_CNTL_VDD_DRV_B_ACTIVE_S 15 -/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[11:4] ;default: 8'd0 ; */ -/*description: */ -#define RTC_CNTL_SCK_DCAP 0x000000FF -#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) -#define RTC_CNTL_SCK_DCAP_V 0xFF -#define RTC_CNTL_SCK_DCAP_S 4 -/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_CAL_EN (BIT(3)) -#define RTC_CNTL_DIG_CAL_EN_M (BIT(3)) -#define RTC_CNTL_DIG_CAL_EN_V 0x1 -#define RTC_CNTL_DIG_CAL_EN_S 3 -/* RTC_CNTL_DBIAS_SWITCH_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DBIAS_SWITCH_IDLE (BIT(2)) -#define RTC_CNTL_DBIAS_SWITCH_IDLE_M (BIT(2)) -#define RTC_CNTL_DBIAS_SWITCH_IDLE_V 0x1 -#define RTC_CNTL_DBIAS_SWITCH_IDLE_S 2 -/* RTC_CNTL_DBIAS_SWITCH_MONITOR : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DBIAS_SWITCH_MONITOR (BIT(1)) -#define RTC_CNTL_DBIAS_SWITCH_MONITOR_M (BIT(1)) -#define RTC_CNTL_DBIAS_SWITCH_MONITOR_V 0x1 -#define RTC_CNTL_DBIAS_SWITCH_MONITOR_S 1 -/* RTC_CNTL_DBIAS_SWITCH_SLP : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DBIAS_SWITCH_SLP (BIT(0)) -#define RTC_CNTL_DBIAS_SWITCH_SLP_M (BIT(0)) -#define RTC_CNTL_DBIAS_SWITCH_SLP_V 0x1 -#define RTC_CNTL_DBIAS_SWITCH_SLP_S 0 - -#define RTC_CNTL_RTCULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0084) -/* RTC_CNTL_REGULATOR0_DBIAS_SEL : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: 1: select sw dbias_active 0: select pvt value*/ -#define RTC_CNTL_REGULATOR0_DBIAS_SEL (BIT(31)) -#define RTC_CNTL_REGULATOR0_DBIAS_SEL_M (BIT(31)) -#define RTC_CNTL_REGULATOR0_DBIAS_SEL_V 0x1 -#define RTC_CNTL_REGULATOR0_DBIAS_SEL_S 31 -/* RTC_CNTL_REGULATOR0_DBIAS_ACTIVE : R/W ;bitpos:[29:25] ;default: 5'b10100 ; */ -/*description: the rtc regulator0 dbias when chip in active state*/ -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE 0x0000001F -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_M ((RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V)<<(RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S)) -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V 0x1F -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S 25 -/* RTC_CNTL_REGULATOR0_DBIAS_SLP : R/W ;bitpos:[24:20] ;default: 5'b10100 ; */ -/*description: the rtc regulator0 dbias when chip in sleep state*/ -#define RTC_CNTL_REGULATOR0_DBIAS_SLP 0x0000001F -#define RTC_CNTL_REGULATOR0_DBIAS_SLP_M ((RTC_CNTL_REGULATOR0_DBIAS_SLP_V)<<(RTC_CNTL_REGULATOR0_DBIAS_SLP_S)) -#define RTC_CNTL_REGULATOR0_DBIAS_SLP_V 0x1F -#define RTC_CNTL_REGULATOR0_DBIAS_SLP_S 20 -/* RTC_CNTL_PVT_RTC_DBIAS : RO ;bitpos:[19:15] ;default: 5'b10100 ; */ -/*description: get pvt dbias value*/ -#define RTC_CNTL_PVT_RTC_DBIAS 0x0000001F -#define RTC_CNTL_PVT_RTC_DBIAS_M ((RTC_CNTL_PVT_RTC_DBIAS_V)<<(RTC_CNTL_PVT_RTC_DBIAS_S)) -#define RTC_CNTL_PVT_RTC_DBIAS_V 0x1F -#define RTC_CNTL_PVT_RTC_DBIAS_S 15 - -#define RTC_CNTL_RTCULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0088) -/* RTC_CNTL_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[28:25] ;default: 4'b1000 ; */ -/*description: the rtc regulator1 dbias when chip in active state*/ -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE 0x0000000F -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S)) -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V 0xF -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S 25 -/* RTC_CNTL_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[23:20] ;default: 4'b1000 ; */ -/*description: the rtc regulator1 dbias when chip in sleep state*/ -#define RTC_CNTL_REGULATOR1_DBIAS_SLP 0x0000000F -#define RTC_CNTL_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_REGULATOR1_DBIAS_SLP_S)) -#define RTC_CNTL_REGULATOR1_DBIAS_SLP_V 0xF -#define RTC_CNTL_REGULATOR1_DBIAS_SLP_S 20 - -#define RTC_CNTL_DIGULATOR_REG (DR_REG_RTCCNTL_BASE + 0x008C) -/* RTC_CNTL_DG_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_DG_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_DG_REGULATOR_FORCE_PU_M (BIT(31)) -#define RTC_CNTL_DG_REGULATOR_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_REGULATOR_FORCE_PU_S 31 -/* RTC_CNTL_DG_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_DG_REGULATOR_FORCE_PD_M (BIT(30)) -#define RTC_CNTL_DG_REGULATOR_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_REGULATOR_FORCE_PD_S 30 -/* RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU (BIT(29)) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_M (BIT(29)) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_S 29 -/* RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD (BIT(28)) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_M (BIT(28)) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_S 28 -/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(27)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(27)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 27 -/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[26:3] ;default: 24'd0 ; */ -/*description: */ -#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x00FFFFFF -#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFFFFFF -#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 3 - -#define RTC_CNTL_DIGULATOR_DRVB_REG (DR_REG_RTCCNTL_BASE + 0x0090) -/* RTC_CNTL_DG_VDD_DRV_B_ACTIVE : R/W ;bitpos:[23:0] ;default: 24'd0 ; */ -/*description: */ -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE 0x00FFFFFF -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_M ((RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V)<<(RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S)) -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V 0xFFFFFF -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S 0 - -#define RTC_CNTL_DIGULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0094) -/* RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: 1: select sw dbias_active 0: select pvt value*/ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL (BIT(31)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_M (BIT(31)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_V 0x1 -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_S 31 -/* RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: initial pvt dbias value*/ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT (BIT(30)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_M (BIT(30)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_V 0x1 -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_S 30 -/* RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE : R/W ;bitpos:[29:25] ;default: 5'b10100 ; */ -/*description: the dig regulator0 dbias when chip in active state*/ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE 0x0000001F -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_M ((RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V)<<(RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V 0x1F -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S 25 -/* RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP : R/W ;bitpos:[24:20] ;default: 5'b10100 ; */ -/*description: the dig regulator0 dbias when chip in sleep state*/ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP 0x0000001F -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_M ((RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V)<<(RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V 0x1F -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S 20 -/* RTC_CNTL_PVT_DIG_DBIAS : RO ;bitpos:[19:15] ;default: 5'b10100 ; */ -/*description: get pvt dbias value*/ -#define RTC_CNTL_PVT_DIG_DBIAS 0x0000001F -#define RTC_CNTL_PVT_DIG_DBIAS_M ((RTC_CNTL_PVT_DIG_DBIAS_V)<<(RTC_CNTL_PVT_DIG_DBIAS_S)) -#define RTC_CNTL_PVT_DIG_DBIAS_V 0x1F -#define RTC_CNTL_PVT_DIG_DBIAS_S 15 - -#define RTC_CNTL_DIGULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x0098) -/* RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE : R/W ;bitpos:[28:25] ;default: 4'b1000 ; */ -/*description: the dig regulator1 dbias when chip in active state*/ -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE 0x0000000F -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_M ((RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V)<<(RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S)) -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V 0xF -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S 25 -/* RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP : R/W ;bitpos:[23:20] ;default: 4'b1000 ; */ -/*description: the dig regulator1 dbias when chip in sleep state*/ -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP 0x0000000F -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_M ((RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V)<<(RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S)) -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V 0xF -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S 20 - -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x009C) -/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: rtc pad force hold*/ -#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) -#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) -#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 -#define RTC_CNTL_PAD_FORCE_HOLD_S 21 - -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x00A0) -/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 -#define RTC_CNTL_DG_WRAP_PD_EN_S 31 -/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: enable power down wifi in sleep*/ -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_V 0x1 -#define RTC_CNTL_WIFI_PD_EN_S 30 -/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) -#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) -#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 -#define RTC_CNTL_CPU_TOP_PD_EN_S 29 -/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) -#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) -#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 -#define RTC_CNTL_DG_PERI_PD_EN_S 28 -/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BT_PD_EN (BIT(27)) -#define RTC_CNTL_BT_PD_EN_M (BIT(27)) -#define RTC_CNTL_BT_PD_EN_V 0x1 -#define RTC_CNTL_BT_PD_EN_S 27 -/* RTC_CNTL_DG_WRAP_RET_PD_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_RET_PD_EN (BIT(26)) -#define RTC_CNTL_DG_WRAP_RET_PD_EN_M (BIT(26)) -#define RTC_CNTL_DG_WRAP_RET_PD_EN_V 0x1 -#define RTC_CNTL_DG_WRAP_RET_PD_EN_S 26 -/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) -#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) -#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 -#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 -/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) -#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) -#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 -#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 -/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ -/*description: wifi force power up*/ -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 -#define RTC_CNTL_WIFI_FORCE_PU_S 18 -/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: wifi force power down*/ -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 -#define RTC_CNTL_WIFI_FORCE_PD_S 17 -/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 -/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 -/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) -#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) -#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 -/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) -#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) -#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 -/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_BT_FORCE_PU (BIT(12)) -#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) -#define RTC_CNTL_BT_FORCE_PU_V 0x1 -#define RTC_CNTL_BT_FORCE_PU_S 12 -/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BT_FORCE_PD (BIT(11)) -#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) -#define RTC_CNTL_BT_FORCE_PD_V 0x1 -#define RTC_CNTL_BT_FORCE_PD_S 11 -/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(10)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(10)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 10 -/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(9)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(9)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 9 -/* RTC_CNTL_DG_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_DG_MEM_FORCE_PU (BIT(8)) -#define RTC_CNTL_DG_MEM_FORCE_PU_M (BIT(8)) -#define RTC_CNTL_DG_MEM_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_MEM_FORCE_PU_S 8 -/* RTC_CNTL_DG_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_MEM_FORCE_PD (BIT(7)) -#define RTC_CNTL_DG_MEM_FORCE_PD_M (BIT(7)) -#define RTC_CNTL_DG_MEM_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_MEM_FORCE_PD_S 7 -/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: memories in digital core force no PD in sleep*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 -#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 -/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: memories in digital core force PD in sleep*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 -#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 -/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) -#define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) -#define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 -#define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 -/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 -#define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) -#define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 -#define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 - -#define RTC_CNTL_DIG_POWER_SWITCH0_REG (DR_REG_RTCCNTL_BASE + 0x00A4) -/* RTC_CNTL_XPD_MEM_SWITCH_MASK : R/W ;bitpos:[31:12] ;default: ~20'h0 ; */ -/*description: */ -#define RTC_CNTL_XPD_MEM_SWITCH_MASK 0x000FFFFF -#define RTC_CNTL_XPD_MEM_SWITCH_MASK_M ((RTC_CNTL_XPD_MEM_SWITCH_MASK_V)<<(RTC_CNTL_XPD_MEM_SWITCH_MASK_S)) -#define RTC_CNTL_XPD_MEM_SWITCH_MASK_V 0xFFFFF -#define RTC_CNTL_XPD_MEM_SWITCH_MASK_S 12 -/* RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK : R/W ;bitpos:[11:7] ;default: ~5'h0 ; */ -/*description: */ -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK 0x0000001F -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_M ((RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V)<<(RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S)) -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V 0x1F -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S 7 -/* RTC_CNTL_XPD_DG_PERI_SWITCH_MASK : R/W ;bitpos:[6:2] ;default: ~5'h0 ; */ -/*description: */ -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK 0x0000001F -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_M ((RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V)<<(RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S)) -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V 0x1F -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S 2 - -#define RTC_CNTL_DIG_POWER_SWITCH1_REG (DR_REG_RTCCNTL_BASE + 0x00A8) -/* RTC_CNTL_XPD_CPU_SWITCH_MASK : R/W ;bitpos:[31:27] ;default: ~5'h0 ; */ -/*description: */ -#define RTC_CNTL_XPD_CPU_SWITCH_MASK 0x0000001F -#define RTC_CNTL_XPD_CPU_SWITCH_MASK_M ((RTC_CNTL_XPD_CPU_SWITCH_MASK_V)<<(RTC_CNTL_XPD_CPU_SWITCH_MASK_S)) -#define RTC_CNTL_XPD_CPU_SWITCH_MASK_V 0x1F -#define RTC_CNTL_XPD_CPU_SWITCH_MASK_S 27 -/* RTC_CNTL_XPD_WIFI_SWITCH_MASK : R/W ;bitpos:[26:22] ;default: ~5'h0 ; */ -/*description: */ -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK 0x0000001F -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_M ((RTC_CNTL_XPD_WIFI_SWITCH_MASK_V)<<(RTC_CNTL_XPD_WIFI_SWITCH_MASK_S)) -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_V 0x1F -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_S 22 - -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x00AC) -/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 -/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force ISO*/ -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 -/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: wifi force no ISO*/ -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 -#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 -/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: wifi force ISO*/ -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 -#define RTC_CNTL_WIFI_FORCE_ISO_S 28 -/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: cpu force no ISO*/ -#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 -/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: cpu force ISO*/ -#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) -#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) -#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 -#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 -/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) -#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 -/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) -#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 -/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) -#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 -#define RTC_CNTL_BT_FORCE_NOISO_S 23 -/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) -#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) -#define RTC_CNTL_BT_FORCE_ISO_V 0x1 -#define RTC_CNTL_BT_FORCE_ISO_S 22 -/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: digital pad force hold*/ -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 -/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: digital pad force un-hold*/ -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 -/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: digital pad force ISO*/ -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 -/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: digital pad force no ISO*/ -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 -/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: digital pad enable auto-hold*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 -/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: wtite only register to clear digital pad auto-hold*/ -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 -/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: read only register to indicate digital pad auto-hold status*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 -#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 -/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 -#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 -/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 -#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 -/* RTC_CNTL_DG_MEM_FORCE_ISO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DG_MEM_FORCE_ISO (BIT(6)) -#define RTC_CNTL_DG_MEM_FORCE_ISO_M (BIT(6)) -#define RTC_CNTL_DG_MEM_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_MEM_FORCE_ISO_S 6 -/* RTC_CNTL_DG_MEM_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_DG_MEM_FORCE_NOISO (BIT(5)) -#define RTC_CNTL_DG_MEM_FORCE_NOISO_M (BIT(5)) -#define RTC_CNTL_DG_MEM_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_MEM_FORCE_NOISO_S 5 - -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x00B0) -/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RTC_CNTL_WDT_EN (BIT(31)) -#define RTC_CNTL_WDT_EN_M (BIT(31)) -#define RTC_CNTL_WDT_EN_V 0x1 -#define RTC_CNTL_WDT_EN_S 31 -/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG0 0x00000007 -#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) -#define RTC_CNTL_WDT_STG0_V 0x7 -#define RTC_CNTL_WDT_STG0_S 28 -/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG1 0x00000007 -#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) -#define RTC_CNTL_WDT_STG1_V 0x7 -#define RTC_CNTL_WDT_STG1_S 25 -/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG2 0x00000007 -#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) -#define RTC_CNTL_WDT_STG2_V 0x7 -#define RTC_CNTL_WDT_STG2_S 22 -/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG3 0x00000007 -#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) -#define RTC_CNTL_WDT_STG3_V 0x7 -#define RTC_CNTL_WDT_STG3_S 19 -/* RTC_CNTL_WDT_STGX : */ -/*description: stage action selection values */ -#define RTC_WDT_STG_SEL_OFF 0 -#define RTC_WDT_STG_SEL_INT 1 -#define RTC_WDT_STG_SEL_RESET_CPU 2 -#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 -#define RTC_WDT_STG_SEL_RESET_RTC 4 - -/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ -/*description: CPU reset counter length*/ -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 -/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ -/*description: system reset counter length*/ -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 -/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: enable WDT in flash boot*/ -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 -/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: enable WDT reset PRO CPU*/ -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 -/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable WDT reset APP CPU*/ -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 -/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: pause WDT in sleep*/ -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 -#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 -/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: wdt reset whole chip enable*/ -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 -/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ -/*description: chip reset siginal pulse width*/ -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 - -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x00B4) -/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ -/*description: */ -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) -#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_S 0 - -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x00B8) -/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ -/*description: */ -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) -#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_S 0 - -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00BC) -/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: */ -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) -#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_S 0 - -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00C0) -/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: */ -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) -#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_S 0 - -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00C4) -/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_WDT_FEED (BIT(31)) -#define RTC_CNTL_WDT_FEED_M (BIT(31)) -#define RTC_CNTL_WDT_FEED_V 0x1 -#define RTC_CNTL_WDT_FEED_S 31 - -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00C8) -/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) -#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_S 0 - -#define RTC_CNTL_WDTRESET_CHIP_REG (DR_REG_RTCCNTL_BASE + 0x00CC) -/* RTC_CNTL_RESET_CHIP_KEY : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ -/*description: */ -#define RTC_CNTL_RESET_CHIP_KEY 0x000000FF -#define RTC_CNTL_RESET_CHIP_KEY_M ((RTC_CNTL_RESET_CHIP_KEY_V)<<(RTC_CNTL_RESET_CHIP_KEY_S)) -#define RTC_CNTL_RESET_CHIP_KEY_V 0xFF -#define RTC_CNTL_RESET_CHIP_KEY_S 24 -/* RTC_CNTL_RESET_CHIP_TARGET : R/W ;bitpos:[23:16] ;default: 8'ha5 ; */ -/*description: */ -#define RTC_CNTL_RESET_CHIP_TARGET 0x000000FF -#define RTC_CNTL_RESET_CHIP_TARGET_M ((RTC_CNTL_RESET_CHIP_TARGET_V)<<(RTC_CNTL_RESET_CHIP_TARGET_S)) -#define RTC_CNTL_RESET_CHIP_TARGET_V 0xFF -#define RTC_CNTL_RESET_CHIP_TARGET_S 16 - -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00D0) -/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: automatically feed swd when int comes*/ -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 -#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 -/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD*/ -#define RTC_CNTL_SWD_DISABLE (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_V 0x1 -#define RTC_CNTL_SWD_DISABLE_S 30 -/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Sw feed swd*/ -#define RTC_CNTL_SWD_FEED (BIT(29)) -#define RTC_CNTL_SWD_FEED_M (BIT(29)) -#define RTC_CNTL_SWD_FEED_V 0x1 -#define RTC_CNTL_SWD_FEED_S 29 -/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: reset swd reset flag*/ -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 -#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 -/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ -/*description: adjust signal width send to swd*/ -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF -#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) -#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF -#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 -/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) -#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) -#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 -#define RTC_CNTL_SWD_BYPASS_RST_S 17 -/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: swd interrupt for feeding*/ -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_V 0x1 -#define RTC_CNTL_SWD_FEED_INT_S 1 -/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: swd reset flag*/ -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 -#define RTC_CNTL_SWD_RESET_FLAG_S 0 - -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00D4) -/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF -#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) -#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_SWD_WKEY_S 0 - -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00D8) -/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ -/*description: */ -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) -#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F -#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 -/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0]*/ -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) -#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F -#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 - -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00DC) -/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH4 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) -#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_S 0 - -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00E0) -/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH5 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) -#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_S 0 - -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00E4) -/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH6 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) -#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_S 0 - -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00E8) -/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH7 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) -#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_S 0 - -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00EC) -/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ -/*description: rtc main state machine status*/ -#define RTC_CNTL_MAIN_STATE 0x0000000F -#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) -#define RTC_CNTL_MAIN_STATE_V 0xF -#define RTC_CNTL_MAIN_STATE_S 28 -/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: rtc main state machine is in idle state*/ -#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 -/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: rtc main state machine is in sleep state*/ -#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) -#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) -#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 -/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait xtal state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 -/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait pll state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 -/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait 8m state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 -/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of low power*/ -#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) -#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) -#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 -#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 -/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of wakeup process*/ -#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) -#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) -#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 -#define RTC_CNTL_IN_WAKEUP_STATE_S 21 -/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: rtc main state machine has been waited for some cycles*/ -#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) -#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) -#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 -#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 -/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: rtc is ready to receive wake up trigger from wake up source*/ -#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) -#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) -#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 -#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 -/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc main state machine is in states that pll should be running*/ -#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) -#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) -#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 -#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 -/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: no use any more*/ -#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 -/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: ulp/cocpu is done*/ -#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) -#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) -#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 -#define RTC_CNTL_COCPU_STATE_DONE_S 16 -/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: ulp/cocpu is in sleep state*/ -#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) -#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) -#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 -#define RTC_CNTL_COCPU_STATE_SLP_S 15 -/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: ulp/cocpu is about to working. Switch rtc main state*/ -#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) -#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) -#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 -#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 -/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: ulp/cocpu should start to work*/ -#define RTC_CNTL_COCPU_STATE_START (BIT(13)) -#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) -#define RTC_CNTL_COCPU_STATE_START_V 0x1 -#define RTC_CNTL_COCPU_STATE_START_S 13 -/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: touch is done*/ -#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) -#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) -#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 -#define RTC_CNTL_TOUCH_STATE_DONE_S 12 -/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: touch is in sleep state*/ -#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) -#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) -#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 -#define RTC_CNTL_TOUCH_STATE_SLP_S 11 -/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: touch is about to working. Switch rtc main state*/ -#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) -#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) -#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 -#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 -/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch should start to work*/ -#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) -#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) -#define RTC_CNTL_TOUCH_STATE_START_V 0x1 -#define RTC_CNTL_TOUCH_STATE_START_S 9 -/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: digital wrap power down*/ -#define RTC_CNTL_XPD_DIG (BIT(8)) -#define RTC_CNTL_XPD_DIG_M (BIT(8)) -#define RTC_CNTL_XPD_DIG_V 0x1 -#define RTC_CNTL_XPD_DIG_S 8 -/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: digital wrap iso*/ -#define RTC_CNTL_DIG_ISO (BIT(7)) -#define RTC_CNTL_DIG_ISO_M (BIT(7)) -#define RTC_CNTL_DIG_ISO_V 0x1 -#define RTC_CNTL_DIG_ISO_S 7 -/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: wifi wrap power down*/ -#define RTC_CNTL_XPD_WIFI (BIT(6)) -#define RTC_CNTL_XPD_WIFI_M (BIT(6)) -#define RTC_CNTL_XPD_WIFI_V 0x1 -#define RTC_CNTL_XPD_WIFI_S 6 -/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: wifi iso*/ -#define RTC_CNTL_WIFI_ISO (BIT(5)) -#define RTC_CNTL_WIFI_ISO_M (BIT(5)) -#define RTC_CNTL_WIFI_ISO_V 0x1 -#define RTC_CNTL_WIFI_ISO_S 5 -/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: rtc peripheral power down*/ -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_V 0x1 -#define RTC_CNTL_XPD_RTC_PERI_S 4 -/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: rtc peripheral iso*/ -#define RTC_CNTL_PERI_ISO (BIT(3)) -#define RTC_CNTL_PERI_ISO_M (BIT(3)) -#define RTC_CNTL_PERI_ISO_V 0x1 -#define RTC_CNTL_PERI_ISO_S 3 -/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: External DCDC power down*/ -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 -#define RTC_CNTL_XPD_DIG_DCDC_S 2 -/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rom0 power down*/ -#define RTC_CNTL_XPD_ROM0 (BIT(0)) -#define RTC_CNTL_XPD_ROM0_M (BIT(0)) -#define RTC_CNTL_XPD_ROM0_V 0x1 -#define RTC_CNTL_XPD_ROM0_S 0 - -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00F0) -/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) -#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_S 0 - -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00F4) -/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) -#define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) -#define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 -#define RTC_CNTL_GPIO_PIN5_HOLD_S 5 -/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) -#define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) -#define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 -#define RTC_CNTL_GPIO_PIN4_HOLD_S 4 -/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) -#define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) -#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 -#define RTC_CNTL_GPIO_PIN3_HOLD_S 3 -/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) -#define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) -#define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 -#define RTC_CNTL_GPIO_PIN2_HOLD_S 2 -/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) -#define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) -#define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 -#define RTC_CNTL_GPIO_PIN1_HOLD_S 1 -/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) -#define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) -#define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 -#define RTC_CNTL_GPIO_PIN0_HOLD_S 0 - -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00F8) -/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF -#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) -#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_DIG_PAD_HOLD_S 0 - -#define RTC_CNTL_DIG_PAD_HOLD1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) -/* RTC_CNTL_DIG_PAD_HOLD1 : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_PAD_HOLD1 0x000001FF -#define RTC_CNTL_DIG_PAD_HOLD1_M ((RTC_CNTL_DIG_PAD_HOLD1_V)<<(RTC_CNTL_DIG_PAD_HOLD1_S)) -#define RTC_CNTL_DIG_PAD_HOLD1_V 0x1FF -#define RTC_CNTL_DIG_PAD_HOLD1_S 0 - -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x0100) -/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_V 0x1 -#define RTC_CNTL_BROWN_OUT_DET_S 31 -/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: enable brown out*/ -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_ENA_S 30 -/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: clear brown out counter*/ -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 -#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 -/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 -/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: 4-pos reset*/ -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 -#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 -/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: enable brown out reset*/ -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 -/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ -/*description: brown out reset wait cycles*/ -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) -#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 -/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable power down RF when brown out happens*/ -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 -/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable close flash when brown out happens*/ -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 -/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ -/*description: brown out interrupt wait cycles*/ -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) -#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF -#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 - -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x0104) -/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits*/ -#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) -#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 - -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x0108) -/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits*/ -#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) -#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF -#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 - -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x010C) -/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: xtal 32k watch dog backup clock factor*/ -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF -#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) -#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF -#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 - -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0110) -/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: if restarted xtal32k period is smaller than this*/ -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F -#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) -#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF -#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 -/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ -/*description: If no clock detected for this amount of time*/ -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 -/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ -/*description: cycles to wait to repower on xtal 32k*/ -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF -#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) -#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF -#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 -/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: cycles to wait to return noral xtal 32k*/ -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F -#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) -#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF -#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 - -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0114) -/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 -#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 - -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0118) -/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[18:0] ;default: 19'd0 ; */ -/*description: sleep reject cause*/ -#define RTC_CNTL_REJECT_CAUSE 0x0007FFFF -#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) -#define RTC_CNTL_REJECT_CAUSE_V 0x7FFFF -#define RTC_CNTL_REJECT_CAUSE_S 0 - -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x011C) -/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 - -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0120) -/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[18:0] ;default: 19'd0 ; */ -/*description: sleep wakeup cause*/ -#define RTC_CNTL_WAKEUP_CAUSE 0x0007FFFF -#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FFFF -#define RTC_CNTL_WAKEUP_CAUSE_S 0 - -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0124) -/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ -/*description: sleep cycles for ULP-coprocessor timer*/ -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 - -#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0128) -/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_M (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_S 22 -/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_M (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_S 21 -/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 -/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 -/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 -/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 -/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 -/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 -/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 -/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 -/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 - -#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x012C) -/* RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_M (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_S 22 -/* RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_M (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_S 21 -/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 -/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 -/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 -/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 -/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 -/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 -/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 -/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 -/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 - -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0130) -/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ -/*description: wait cycles for rention operation*/ -#define RTC_CNTL_RETENTION_WAIT 0x0000001F -#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) -#define RTC_CNTL_RETENTION_WAIT_V 0x1F -#define RTC_CNTL_RETENTION_WAIT_S 27 -/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_EN (BIT(26)) -#define RTC_CNTL_RETENTION_EN_M (BIT(26)) -#define RTC_CNTL_RETENTION_EN_V 0x1 -#define RTC_CNTL_RETENTION_EN_S 26 -/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 -/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 -#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) -#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 -#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 -/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) -#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) -#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 -#define RTC_CNTL_RETENTION_CLK_SEL_S 18 -/* RTC_CNTL_CNTL_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_CNTL_CLK_EN (BIT(17)) -#define RTC_CNTL_CNTL_CLK_EN_M (BIT(17)) -#define RTC_CNTL_CNTL_CLK_EN_V 0x1 -#define RTC_CNTL_CNTL_CLK_EN_S 17 - -#define RTC_CNTL_RETENTION_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0134) -/* RTC_CNTL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_LINK_ADDR 0x07FFFFFF -#define RTC_CNTL_RETENTION_LINK_ADDR_M ((RTC_CNTL_RETENTION_LINK_ADDR_V)<<(RTC_CNTL_RETENTION_LINK_ADDR_S)) -#define RTC_CNTL_RETENTION_LINK_ADDR_V 0x7FFFFFF -#define RTC_CNTL_RETENTION_LINK_ADDR_S 0 - -#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0138) -/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: select use analog fib signal*/ -#define RTC_CNTL_FIB_SEL 0x00000007 -#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) -#define RTC_CNTL_FIB_SEL_V 0x7 -#define RTC_CNTL_FIB_SEL_S 0 - -#define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOD_RST BIT(1) -#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) - -#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x013C) -/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 -/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 -/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 -/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 -/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 -/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 -/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 -#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) -#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 -#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 -/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 -#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) -#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 -#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 -/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 -#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) -#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 -#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 -/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 -#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) -#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 -#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 -/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 -#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) -#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 -#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 -/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 -#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) -#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 -#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 -/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) -#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) -#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 -#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 -/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 -/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F -#define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) -#define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F -#define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 - -#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140) -/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_SEL4 0x0000001F -#define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) -#define RTC_CNTL_DEBUG_SEL4_V 0x1F -#define RTC_CNTL_DEBUG_SEL4_S 27 -/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_SEL3 0x0000001F -#define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) -#define RTC_CNTL_DEBUG_SEL3_V 0x1F -#define RTC_CNTL_DEBUG_SEL3_S 22 -/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_SEL2 0x0000001F -#define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) -#define RTC_CNTL_DEBUG_SEL2_V 0x1F -#define RTC_CNTL_DEBUG_SEL2_S 17 -/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_SEL1 0x0000001F -#define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) -#define RTC_CNTL_DEBUG_SEL1_V 0x1F -#define RTC_CNTL_DEBUG_SEL1_S 12 -/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_SEL0 0x0000001F -#define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) -#define RTC_CNTL_DEBUG_SEL0_V 0x1F -#define RTC_CNTL_DEBUG_SEL0_S 7 -/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F -#define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) -#define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F -#define RTC_CNTL_DEBUG_BIT_SEL_S 2 -/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) -#define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) -#define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 -#define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 -/* RTC_CNTL_MTDI_ENAMUX : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_MTDI_ENAMUX (BIT(0)) -#define RTC_CNTL_MTDI_ENAMUX_M (BIT(0)) -#define RTC_CNTL_MTDI_ENAMUX_V 0x1 -#define RTC_CNTL_MTDI_ENAMUX_S 0 - -#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0144) -/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F -#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) -#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF -#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 -/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F -#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) -#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF -#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 -/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F -#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) -#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF -#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 -/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F -#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) -#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF -#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 -/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F -#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) -#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF -#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 -/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F -#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) -#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF -#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 -/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) -#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) -#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 -#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 -/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) -#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) -#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 -#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 -/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) -#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) -#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 -#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 -/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) -#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) -#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 -#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 -/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) -#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) -#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 -#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 -/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) -#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) -#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 -#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 -/* RTC_CNTL_VDD_DIG_TEST : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define RTC_CNTL_VDD_DIG_TEST 0x00000003 -#define RTC_CNTL_VDD_DIG_TEST_M ((RTC_CNTL_VDD_DIG_TEST_V)<<(RTC_CNTL_VDD_DIG_TEST_S)) -#define RTC_CNTL_VDD_DIG_TEST_V 0x3 -#define RTC_CNTL_VDD_DIG_TEST_S 0 - -#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0148) -/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F -#define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) -#define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F -#define RTC_CNTL_SAR_DEBUG_SEL_S 27 - -#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x014C) -/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) -#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) -#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 -#define RTC_CNTL_POWER_GLITCH_EN_S 31 -/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 -/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 -/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 -/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ -/*description: */ -#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 -#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) -#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 -#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 - -#define RTC_CNTL_DCDC_CTRL0_REG (DR_REG_RTCCNTL_BASE + 0x0150) -/* RTC_CNTL_POCPENB_DCDC : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_POCPENB_DCDC (BIT(31)) -#define RTC_CNTL_POCPENB_DCDC_M (BIT(31)) -#define RTC_CNTL_POCPENB_DCDC_V 0x1 -#define RTC_CNTL_POCPENB_DCDC_S 31 -/* RTC_CNTL_SSTIME_DCDC : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SSTIME_DCDC (BIT(30)) -#define RTC_CNTL_SSTIME_DCDC_M (BIT(30)) -#define RTC_CNTL_SSTIME_DCDC_V 0x1 -#define RTC_CNTL_SSTIME_DCDC_S 30 -/* RTC_CNTL_CCM_DCDC : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_CCM_DCDC (BIT(29)) -#define RTC_CNTL_CCM_DCDC_M (BIT(29)) -#define RTC_CNTL_CCM_DCDC_V 0x1 -#define RTC_CNTL_CCM_DCDC_S 29 -/* RTC_CNTL_FSW_DCDC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ -/*description: */ -#define RTC_CNTL_FSW_DCDC 0x00000007 -#define RTC_CNTL_FSW_DCDC_M ((RTC_CNTL_FSW_DCDC_V)<<(RTC_CNTL_FSW_DCDC_S)) -#define RTC_CNTL_FSW_DCDC_V 0x7 -#define RTC_CNTL_FSW_DCDC_S 26 -/* RTC_CNTL_DCMLEVEL_DCDC : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ -/*description: */ -#define RTC_CNTL_DCMLEVEL_DCDC 0x00000003 -#define RTC_CNTL_DCMLEVEL_DCDC_M ((RTC_CNTL_DCMLEVEL_DCDC_V)<<(RTC_CNTL_DCMLEVEL_DCDC_S)) -#define RTC_CNTL_DCMLEVEL_DCDC_V 0x3 -#define RTC_CNTL_DCMLEVEL_DCDC_S 24 -/* RTC_CNTL_DCM2ENB_DCDC : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DCM2ENB_DCDC (BIT(23)) -#define RTC_CNTL_DCM2ENB_DCDC_M (BIT(23)) -#define RTC_CNTL_DCM2ENB_DCDC_V 0x1 -#define RTC_CNTL_DCM2ENB_DCDC_S 23 -/* RTC_CNTL_RAMP_DCDC : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RAMP_DCDC (BIT(22)) -#define RTC_CNTL_RAMP_DCDC_M (BIT(22)) -#define RTC_CNTL_RAMP_DCDC_V 0x1 -#define RTC_CNTL_RAMP_DCDC_S 22 -/* RTC_CNTL_RAMPLEVEL_DCDC : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RAMPLEVEL_DCDC (BIT(21)) -#define RTC_CNTL_RAMPLEVEL_DCDC_M (BIT(21)) -#define RTC_CNTL_RAMPLEVEL_DCDC_V 0x1 -#define RTC_CNTL_RAMPLEVEL_DCDC_S 21 -/* RTC_CNTL_POWER_GOOD_DCDC : RO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_POWER_GOOD_DCDC (BIT(5)) -#define RTC_CNTL_POWER_GOOD_DCDC_M (BIT(5)) -#define RTC_CNTL_POWER_GOOD_DCDC_V 0x1 -#define RTC_CNTL_POWER_GOOD_DCDC_S 5 -/* RTC_CNTL_VSET_DCDC_VALUE : RO ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_VALUE 0x0000001F -#define RTC_CNTL_VSET_DCDC_VALUE_M ((RTC_CNTL_VSET_DCDC_VALUE_V)<<(RTC_CNTL_VSET_DCDC_VALUE_S)) -#define RTC_CNTL_VSET_DCDC_VALUE_V 0x1F -#define RTC_CNTL_VSET_DCDC_VALUE_S 0 - -#define RTC_CNTL_DCDC_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0154) -/* RTC_CNTL_DCDC_MODE_IDLE : R/W ;bitpos:[31:29] ;default: 3'b100 ; */ -/*description: */ -#define RTC_CNTL_DCDC_MODE_IDLE 0x00000007 -#define RTC_CNTL_DCDC_MODE_IDLE_M ((RTC_CNTL_DCDC_MODE_IDLE_V)<<(RTC_CNTL_DCDC_MODE_IDLE_S)) -#define RTC_CNTL_DCDC_MODE_IDLE_V 0x7 -#define RTC_CNTL_DCDC_MODE_IDLE_S 29 -/* RTC_CNTL_DCDC_MODE_MONITOR : R/W ;bitpos:[28:26] ;default: 3'b100 ; */ -/*description: */ -#define RTC_CNTL_DCDC_MODE_MONITOR 0x00000007 -#define RTC_CNTL_DCDC_MODE_MONITOR_M ((RTC_CNTL_DCDC_MODE_MONITOR_V)<<(RTC_CNTL_DCDC_MODE_MONITOR_S)) -#define RTC_CNTL_DCDC_MODE_MONITOR_V 0x7 -#define RTC_CNTL_DCDC_MODE_MONITOR_S 26 -/* RTC_CNTL_DCDC_MODE_SLP : R/W ;bitpos:[25:23] ;default: 3'b100 ; */ -/*description: */ -#define RTC_CNTL_DCDC_MODE_SLP 0x00000007 -#define RTC_CNTL_DCDC_MODE_SLP_M ((RTC_CNTL_DCDC_MODE_SLP_V)<<(RTC_CNTL_DCDC_MODE_SLP_S)) -#define RTC_CNTL_DCDC_MODE_SLP_V 0x7 -#define RTC_CNTL_DCDC_MODE_SLP_S 23 - -#define RTC_CNTL_DCDC_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0158) -/* RTC_CNTL_VSET_DCDC_SW_SEL : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_SW_SEL (BIT(28)) -#define RTC_CNTL_VSET_DCDC_SW_SEL_M (BIT(28)) -#define RTC_CNTL_VSET_DCDC_SW_SEL_V 0x1 -#define RTC_CNTL_VSET_DCDC_SW_SEL_S 28 -/* RTC_CNTL_VSET_DCDC_SEL_HW_SW : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW (BIT(27)) -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_M (BIT(27)) -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_V 0x1 -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_S 27 -/* RTC_CNTL_VSET_DCDC_GAP : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_GAP 0x0000001F -#define RTC_CNTL_VSET_DCDC_GAP_M ((RTC_CNTL_VSET_DCDC_GAP_V)<<(RTC_CNTL_VSET_DCDC_GAP_S)) -#define RTC_CNTL_VSET_DCDC_GAP_V 0x1F -#define RTC_CNTL_VSET_DCDC_GAP_S 22 -/* RTC_CNTL_VSET_DCDC_STEP : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_STEP 0x0000001F -#define RTC_CNTL_VSET_DCDC_STEP_M ((RTC_CNTL_VSET_DCDC_STEP_V)<<(RTC_CNTL_VSET_DCDC_STEP_S)) -#define RTC_CNTL_VSET_DCDC_STEP_V 0x1F -#define RTC_CNTL_VSET_DCDC_STEP_S 17 -/* RTC_CNTL_VSET_DCDC_FIX : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_FIX (BIT(16)) -#define RTC_CNTL_VSET_DCDC_FIX_M (BIT(16)) -#define RTC_CNTL_VSET_DCDC_FIX_V 0x1 -#define RTC_CNTL_VSET_DCDC_FIX_S 16 -/* RTC_CNTL_VSET_DCDC_INIT : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_INIT (BIT(15)) -#define RTC_CNTL_VSET_DCDC_INIT_M (BIT(15)) -#define RTC_CNTL_VSET_DCDC_INIT_V 0x1 -#define RTC_CNTL_VSET_DCDC_INIT_S 15 -/* RTC_CNTL_VSET_DCDC_INIT_VALUE : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_INIT_VALUE 0x0000001F -#define RTC_CNTL_VSET_DCDC_INIT_VALUE_M ((RTC_CNTL_VSET_DCDC_INIT_VALUE_V)<<(RTC_CNTL_VSET_DCDC_INIT_VALUE_S)) -#define RTC_CNTL_VSET_DCDC_INIT_VALUE_V 0x1F -#define RTC_CNTL_VSET_DCDC_INIT_VALUE_S 10 -/* RTC_CNTL_VSET_DCDC_TARGET_VALUE0 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0 0x0000001F -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_M ((RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V)<<(RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S)) -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V 0x1F -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S 5 -/* RTC_CNTL_VSET_DCDC_TARGET_VALUE1 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1 0x0000001F -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_M ((RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V)<<(RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S)) -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V 0x1F -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S 0 - -#define RTC_CNTL_RC32K_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x015C) -/* RTC_CNTL_RC32K_XPD : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RC32K_XPD (BIT(31)) -#define RTC_CNTL_RC32K_XPD_M (BIT(31)) -#define RTC_CNTL_RC32K_XPD_V 0x1 -#define RTC_CNTL_RC32K_XPD_S 31 -/* RTC_CNTL_RC32K_DFREQ : R/W ;bitpos:[30:21] ;default: 10'h1ff ; */ -/*description: */ -#define RTC_CNTL_RC32K_DFREQ 0x000003FF -#define RTC_CNTL_RC32K_DFREQ_M ((RTC_CNTL_RC32K_DFREQ_V)<<(RTC_CNTL_RC32K_DFREQ_S)) -#define RTC_CNTL_RC32K_DFREQ_V 0x3FF -#define RTC_CNTL_RC32K_DFREQ_S 21 - -#define RTC_CNTL_PLL8M_REG (DR_REG_RTCCNTL_BASE + 0x0160) -/* RTC_CNTL_XPD_PLL8M : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XPD_PLL8M (BIT(31)) -#define RTC_CNTL_XPD_PLL8M_M (BIT(31)) -#define RTC_CNTL_XPD_PLL8M_V 0x1 -#define RTC_CNTL_XPD_PLL8M_S 31 -/* RTC_CNTL_CKREF_PLL8M_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_CKREF_PLL8M_SEL (BIT(30)) -#define RTC_CNTL_CKREF_PLL8M_SEL_M (BIT(30)) -#define RTC_CNTL_CKREF_PLL8M_SEL_V 0x1 -#define RTC_CNTL_CKREF_PLL8M_SEL_S 30 - -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) -/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103250 ; */ -/*description: */ -#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF -#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) -#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF -#define RTC_CNTL_CNTL_DATE_S 0 - -#ifdef __cplusplus -} -#endif - -#endif /*_SOC_RTC_CNTL_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_struct.h b/components/soc/esp32h4/include/rev1/soc/rtc_cntl_struct.h deleted file mode 100644 index 8fa92bc3b3..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/rtc_cntl_struct.h +++ /dev/null @@ -1,996 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_RTC_CNTL_STRUCT_H_ -#define _SOC_RTC_CNTL_STRUCT_H_ -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct rtc_cntl_dev_s { - union { - struct { - uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ - uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ - uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ - uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ - uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ - uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ - uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ - uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ - uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ - uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ - uint32_t xtl_force_pd: 1; /*crystall force power down*/ - uint32_t xtl_force_pu: 1; /*crystall force power up*/ - uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ - uint32_t xpd_rfpll: 1; - uint32_t xpd_rfpll_force: 1; - uint32_t ctr_sel: 3; - uint32_t xtl_force_iso: 1; - uint32_t pll_force_iso: 1; - uint32_t analog_force_iso: 1; - uint32_t xtl_force_noiso: 1; - uint32_t pll_force_noiso: 1; - uint32_t analog_force_noiso: 1; - uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ - uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ - uint32_t sw_sys_rst: 1; /*SW system reset*/ - }; - uint32_t val; - } options0; - uint32_t slp_timer0; /**/ - union { - struct { - uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ - uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ - uint32_t reserved17: 15; - }; - uint32_t val; - } slp_timer1; - union { - struct { - uint32_t reserved0: 27; - uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ - uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ - uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ - uint32_t reserved30: 1; - uint32_t update: 1; /*Set 1: to update register with RTC timer*/ - }; - uint32_t val; - } time_update; - uint32_t time_low0; /*RTC timer low 32 bits*/ - union { - struct { - uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/ - uint32_t reserved16: 16; - }; - uint32_t val; - } time_high0; - union { - struct { - uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ - uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ - uint32_t reserved2: 20; - uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ - uint32_t reserved23: 5; - uint32_t sdio_active_ind: 1; /*SDIO active indication*/ - uint32_t slp_wakeup: 1; /*leep wakeup bit*/ - uint32_t slp_reject: 1; /*leep reject bit*/ - uint32_t sleep_en: 1; /*sleep enable bit*/ - }; - uint32_t val; - } state0; - union { - struct { - uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ - uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ - uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ - uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ - uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ - }; - uint32_t val; - } timer1; - union { - struct { - uint32_t reserved0: 24; - uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ - }; - uint32_t val; - } timer2; - union { - struct { - uint32_t wifi_wait_timer: 9; - uint32_t wifi_powerup_timer: 7; - uint32_t bt_wait_timer: 9; - uint32_t bt_powerup_timer: 7; - }; - uint32_t val; - } timer3; - union { - struct { - uint32_t cpu_top_wait_timer: 9; - uint32_t cpu_top_powerup_timer: 7; - uint32_t dg_wrap_wait_timer: 9; - uint32_t dg_wrap_powerup_timer: 7; - }; - uint32_t val; - } timer4; - union { - struct { - uint32_t reserved0: 8; - uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ - uint32_t reserved16: 16; - }; - uint32_t val; - } timer5; - union { - struct { - uint32_t reserved0: 16; - uint32_t dg_peri_wait_timer: 9; - uint32_t dg_peri_powerup_timer: 7; - }; - uint32_t val; - } timer6; - union { - struct { - uint32_t reserved0: 16; - uint32_t xpd_trx_force_pd: 1; - uint32_t xpd_trx_force_pu: 1; - uint32_t i2c_reset_por_force_pd: 1; - uint32_t i2c_reset_por_force_pu: 1; - uint32_t glitch_rst_en: 1; - uint32_t reserved21: 1; /*PLLA force power down*/ - uint32_t peri_i2c_pu: 1; /*PLLA force power up*/ - uint32_t plla_force_pd: 1; /*PLLA force power down*/ - uint32_t plla_force_pu: 1; /*PLLA force power up*/ - uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ - uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ - uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ - uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ - uint32_t reserved29: 1; - uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ - uint32_t pll_i2c_pu: 1; - }; - uint32_t val; - } ana_conf; - union { - struct { - uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ - uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ - uint32_t stat_vector_sel_appcpu: 1; /*APP CPU state vector sel*/ - uint32_t stat_vector_sel_procpu: 1; /*PRO CPU state vector sel*/ - uint32_t all_reset_flag_procpu: 1; /*PRO CPU reset_flag*/ - uint32_t all_reset_flag_appcpu: 1; /*APP CPU reset flag*/ - uint32_t all_reset_flag_clr_procpu: 1; /*clear PRO CPU reset_flag*/ - uint32_t all_reset_flag_clr_appcpu: 1; /*clear APP CPU reset flag*/ - uint32_t ocd_halt_on_reset_appcpu: 1; /*APPCPU OcdHaltOnReset*/ - uint32_t ocd_halt_on_reset_procpu: 1; /*PROCPU OcdHaltOnReset*/ - uint32_t jtag_reset_flag_procpu: 1; - uint32_t jtag_reset_flag_appcpu: 1; - uint32_t jtag_reset_flag_clr_procpu: 1; - uint32_t jtag_reset_flag_clr_appcpu: 1; - uint32_t rtc_dreset_mask_appcpu: 1; - uint32_t rtc_dreset_mask_procpu: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } reset_state; - union { - struct { - uint32_t reserved0: 13; - uint32_t rtc_wakeup_ena:19; /*wakeup enable bitmap*/ - }; - uint32_t val; - } wakeup_state; - union { - struct { - uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ - uint32_t reserved2: 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ - uint32_t reserved4: 5; - uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ - uint32_t reserved11: 4; /*enable saradc2 interrupt*/ - uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ - uint32_t reserved17: 2; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t rtc_ble_compare_wake: 1; - uint32_t vset_dcdc_done: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ - uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ - uint32_t reserved2: 1; /*SDIO idle interrupt raw*/ - uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ - uint32_t reserved4: 5; /*touch inactive interrupt raw*/ - uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ - uint32_t reserved11: 4; /*saradc2 interrupt raw*/ - uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ - uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ - uint32_t reserved17: 2; /*touch timeout interrupt raw*/ - uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t rtc_ble_compare_wake: 1; - uint32_t vset_dcdc_done: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*sleep reject interrupt state*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ - uint32_t reserved4: 5; - uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ - uint32_t reserved11: 4; - uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t rtc_ble_compare_wake: 1; - uint32_t vset_dcdc_done: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ - uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ - uint32_t reserved4: 5; - uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ - uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ - uint32_t reserved11: 4; - uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ - uint32_t rtc_bbpll_cal: 1; - uint32_t rtc_ble_compare_wake: 1; - uint32_t vset_dcdc_done: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } int_clr; - uint32_t store[4]; /**/ - union { - struct { - uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ - uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ - uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ - uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ - uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ - uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ - uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ - uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ - uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ - uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ - uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ - uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ - uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ - uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ - uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ - uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ - uint32_t reserved24: 6; - uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ - uint32_t ctr_en: 1; - }; - uint32_t val; - } ext_xtl_conf; - union { - struct { - uint32_t reserved0: 31; - uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ - }; - uint32_t val; - } ext_wakeup_conf; - union { - struct { - uint32_t reserved0: 11; - uint32_t rtc_sleep_reject_ena:19; /*sleep reject enable*/ - uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ - uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ - }; - uint32_t val; - } slp_reject_conf; - union { - struct { - uint32_t reserved0: 29; - uint32_t cpusel_conf: 1; /*CPU sel option*/ - uint32_t cpuperiod_sel: 2; - }; - uint32_t val; - } cpu_period_conf; - union { - struct { - uint32_t rtc_ble_tmr_rst: 1; - uint32_t efuse_clk_force_gating: 1; - uint32_t efuse_clk_force_nogating: 1; - uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ - uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ - uint32_t dig_rc32k_en: 1; /*enable RC32K for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ - uint32_t reserved7: 3; - uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ - uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ - uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ - uint32_t ck8m_dfreq: 10; /*CK8M_DFREQ*/ - uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ - uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ - uint32_t xtal_global_force_gating: 1; - uint32_t xtal_global_force_nogating: 1; - uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 2*/ - uint32_t ana_clk_rtc_sel: 2; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t reserved0: 19; - uint32_t rtc_ana_clk_pd_slp: 1; - uint32_t rtc_ana_clk_pd_monitor: 1; - uint32_t rtc_ana_clk_pd_idle: 1; - uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ - uint32_t rtc_ana_clk_div: 8; - uint32_t slow_clk_next_edge: 1; - }; - uint32_t val; - } slow_clk_conf; - union { - struct { - uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ - uint32_t reserved8: 1; - uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ - uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ - uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ - uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ - uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ - uint32_t sdio_modecurlim: 1; /*select current limit mode*/ - uint32_t sdio_encurlim: 1; /*enable current limit*/ - uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ - uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ - uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ - uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ - uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t xpd_sdio: 1; - }; - uint32_t val; - } sdio_conf; - union { - struct { - uint32_t reserved0: 10; - uint32_t bias_buf_idle: 1; - uint32_t bias_buf_wake: 1; - uint32_t bias_buf_deep_slp: 1; - uint32_t bias_buf_monitor: 1; - uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ - uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ - uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ - uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ - uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ - uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ - uint32_t xpd_dcdc_slp: 1; - uint32_t xpd_dcdc_monitor: 1; - uint32_t xpd_dcdc_idle: 1; - uint32_t reserved29: 3; - }; - uint32_t val; - } bias_conf; - union { - struct { - uint32_t dbias_switch_slp: 1; - uint32_t dbias_switch_monitor: 1; - uint32_t dbias_switch_idle: 1; - uint32_t dig_cal_en: 1; - uint32_t sck_dcap: 8; - uint32_t reserved12: 3; - uint32_t rtc_vdd_drv_b_active: 6; /*SCK_DCAP*/ - uint32_t rtc_vdd_drv_b_slp: 6; - uint32_t rtc_vdd_drv_b_slp_en: 1; - uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ - uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ - uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ - uint32_t rtculator_force_pu: 1; - }; - uint32_t val; - } rtculator; - union { - struct { - uint32_t reserved0: 15; - uint32_t pvt_rtc_dbias: 5; /*get pvt dbias value*/ - uint32_t rtculator0_dbias_slp: 5; /*the rtc regulator0 dbias when chip in sleep state*/ - uint32_t rtculator0_dbias_active: 5; /*the rtc regulator0 dbias when chip in active state*/ - uint32_t reserved30: 1; - uint32_t rtculator0_dbias_sel: 1; /*1: select sw dbias_active 0: select pvt value*/ - }; - uint32_t val; - } rtculator0_dbias; - union { - struct { - uint32_t reserved0: 20; - uint32_t rtculator1_dbias_slp: 4; /*the rtc regulator1 dbias when chip in sleep state*/ - uint32_t reserved24: 1; - uint32_t rtculator1_dbias_active: 4; /*the rtc regulator1 dbias when chip in active state*/ - uint32_t reserved29: 3; - }; - uint32_t val; - } rtculator1_dbias; - union { - struct { - uint32_t reserved0: 3; - uint32_t dg_vdd_drv_b_slp: 24; - uint32_t dg_vdd_drv_b_slp_en: 1; - uint32_t dgulator_slp_force_pd: 1; - uint32_t dgulator_slp_force_pu: 1; - uint32_t dgulator_force_pd: 1; - uint32_t dgulator_force_pu: 1; - }; - uint32_t val; - } digulator; - union { - struct { - uint32_t dg_vdd_drv_b_active:24; - uint32_t reserved24: 8; - }; - uint32_t val; - } digulator_drvb; - union { - struct { - uint32_t reserved0: 15; - uint32_t pvt_dig_dbias: 5; /*get pvt dbias value*/ - uint32_t digulator0_dbias_slp: 5; /*the dig regulator0 dbias when chip in sleep state*/ - uint32_t digulator0_dbias_active: 5; /*the dig regulator0 dbias when chip in active state*/ - uint32_t digulator0_dbias_init: 1; /*initial pvt dbias value*/ - uint32_t digulator0_dbias_sel: 1; /*1: select sw dbias_active 0: select pvt value*/ - }; - uint32_t val; - } digulator0_dbias; - union { - struct { - uint32_t reserved0: 20; - uint32_t digulator1_dbias_slp: 4; /*the dig regulator1 dbias when chip in sleep state*/ - uint32_t reserved24: 1; - uint32_t digulator1_dbias_active: 4; /*the dig regulator1 dbias when chip in active state*/ - uint32_t reserved29: 3; - }; - uint32_t val; - } digulator1_dbias; - union { - struct { - uint32_t reserved0: 21; - uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ - uint32_t reserved22: 10; - }; - uint32_t val; - } rtc_pwc; - union { - struct { - uint32_t vdd_spi_pwr_drv: 2; - uint32_t vdd_spi_pwr_force: 1; - uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ - uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ - uint32_t reserved5: 2; - uint32_t dg_mem_force_pd: 1; - uint32_t dg_mem_force_pu: 1; - uint32_t dg_wrap_force_pd: 1; - uint32_t dg_wrap_force_pu: 1; - uint32_t bt_force_pd: 1; - uint32_t bt_force_pu: 1; - uint32_t dg_peri_force_pd: 1; - uint32_t dg_peri_force_pu: 1; - uint32_t fastmem_force_lpd: 1; - uint32_t fastmem_force_lpu: 1; - uint32_t wifi_force_pd: 1; /*wifi force power down*/ - uint32_t wifi_force_pu: 1; /*wifi force power up*/ - uint32_t reserved19: 2; /*digital core force power down*/ - uint32_t cpu_top_force_pd: 1; - uint32_t cpu_top_force_pu: 1; - uint32_t reserved23: 3; - uint32_t dg_wrap_ret_pd_en: 1; - uint32_t bt_pd_en: 1; - uint32_t dg_peri_pd_en: 1; - uint32_t cpu_top_pd_en: 1; - uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ - uint32_t dg_wrap_pd_en: 1; - }; - uint32_t val; - } dig_pwc; - union { - struct { - uint32_t reserved0: 2; - uint32_t xpd_dg_peri_switch_mask: 5; - uint32_t xpd_dg_wrap_switch_mask: 5; - uint32_t xpd_mem_switch_mask: 20; - }; - uint32_t val; - } dig_power_switch0; - union { - struct { - uint32_t reserved0: 22; - uint32_t xpd_wifi_switch_mask: 5; - uint32_t xpd_cpu_switch_mask: 5; - }; - uint32_t val; - } dig_power_switch1; - union { - struct { - uint32_t reserved0: 5; - uint32_t dg_mem_force_noiso: 1; - uint32_t dg_mem_force_iso: 1; - uint32_t dig_iso_force_off: 1; - uint32_t dig_iso_force_on: 1; - uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ - uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ - uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ - uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ - uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ - uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ - uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ - uint32_t reserved16: 6; - uint32_t bt_force_iso: 1; - uint32_t bt_force_noiso: 1; - uint32_t dg_peri_force_iso: 1; - uint32_t dg_peri_force_noiso: 1; - uint32_t cpu_top_force_iso: 1; /*cpu force ISO*/ - uint32_t cpu_top_force_noiso: 1; /*cpu force no ISO*/ - uint32_t wifi_force_iso: 1; /*wifi force ISO*/ - uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ - uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ - uint32_t dg_wrap_force_noiso: 1; - }; - uint32_t val; - } dig_iso; - union { - struct { - uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ - uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ - uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ - uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ - uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ - uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ - uint32_t sys_reset_length: 3; /*system reset counter length*/ - uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ - uint32_t stg3: 3; /*1: interrupt stage en*/ - uint32_t stg2: 3; /*1: interrupt stage en*/ - uint32_t stg1: 3; /*1: interrupt stage en*/ - uint32_t stg0: 3; /*1: interrupt stage en*/ - uint32_t en: 1; - }; - uint32_t val; - } wdt_config0; - uint32_t wdt_config1; /**/ - uint32_t wdt_config2; /**/ - uint32_t wdt_config3; /**/ - uint32_t wdt_config4; /**/ - union { - struct { - uint32_t reserved0: 31; - uint32_t feed: 1; - }; - uint32_t val; - } wdt_feed; - uint32_t wdt_wprotect; /**/ - union { - struct { - uint32_t reserved0: 16; - uint32_t reset_chip_target: 8; - uint32_t reset_chip_key: 8; - }; - uint32_t val; - } wdtreset_chip; - union { - struct { - uint32_t swd_reset_flag: 1; /*swd reset flag*/ - uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ - uint32_t reserved2: 15; - uint32_t swd_bypass_rst: 1; - uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ - uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ - uint32_t swd_feed: 1; /*Sw feed swd*/ - uint32_t swd_disable: 1; /*disabel SWD*/ - uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ - }; - uint32_t val; - } swd_conf; - uint32_t swd_wprotect; /**/ - union { - struct { - uint32_t reserved0: 20; - uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ - uint32_t procpu_c1: 6; - }; - uint32_t val; - } sw_cpu_stall; - uint32_t store4; /**/ - uint32_t store5; /**/ - uint32_t store6; /**/ - uint32_t store7; /**/ - union { - struct { - uint32_t xpd_rom0: 1; /*rom0 power down*/ - uint32_t reserved1: 1; - uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ - uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ - uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ - uint32_t wifi_iso: 1; /*wifi iso*/ - uint32_t xpd_wifi: 1; /*wifi wrap power down*/ - uint32_t dig_iso: 1; /*digital wrap iso*/ - uint32_t xpd_dig: 1; /*digital wrap power down*/ - uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ - uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ - uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ - uint32_t rtc_touch_state_done: 1; /*touch is done*/ - uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ - uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ - uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ - uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ - uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ - uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ - uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ - uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ - uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ - uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ - uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ - uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ - uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ - uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ - uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ - uint32_t rtc_main_state: 4; /*rtc main state machine status*/ - }; - uint32_t val; - } low_power_st; - uint32_t diag0; /**/ - union { - struct { - uint32_t rtc_gpio_pin0_hold: 1; - uint32_t rtc_gpio_pin1_hold: 1; - uint32_t rtc_gpio_pin2_hold: 1; - uint32_t rtc_gpio_pin3_hold: 1; - uint32_t rtc_gpio_pin4_hold: 1; - uint32_t rtc_gpio_pin5_hold: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } pad_hold; - uint32_t dig_pad_hold; /**/ - union { - struct { - uint32_t dig_pad_hold1: 9; - uint32_t reserved9: 23; - }; - uint32_t val; - } dig_pad_hold1; - union { - struct { - uint32_t reserved0: 4; - uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ - uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ - uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ - uint32_t rst_wait: 10; /*brown out reset wait cycles*/ - uint32_t rst_ena: 1; /*enable brown out reset*/ - uint32_t rst_sel: 1; /*1: 4-pos reset*/ - uint32_t ana_rst_en: 1; - uint32_t cnt_clr: 1; /*clear brown out counter*/ - uint32_t ena: 1; /*enable brown out*/ - uint32_t det: 1; - }; - uint32_t val; - } brown_out; - uint32_t time_low1; /*RTC timer low 32 bits*/ - union { - struct { - uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/ - uint32_t reserved16: 16; - }; - uint32_t val; - } time_high1; - uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ - union { - struct { - uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ - uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ - uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ - uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ - }; - uint32_t val; - } xtal32k_conf; - union { - struct { - uint32_t reserved0: 18; - uint32_t io_mux_reset_disable: 1; - uint32_t reserved19: 13; - }; - uint32_t val; - } usb_conf; - union { - struct { - uint32_t reject_cause:19; /*sleep reject cause*/ - uint32_t reserved19: 13; - }; - uint32_t val; - } slp_reject_cause; - union { - struct { - uint32_t force_download_boot: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } option1; - union { - struct { - uint32_t wakeup_cause:19; /*sleep wakeup cause*/ - uint32_t reserved19: 13; - }; - uint32_t val; - } slp_wakeup_cause; - union { - struct { - uint32_t reserved0: 8; - uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/ - }; - uint32_t val; - } ulp_cp_timer_1; - union { - struct { - uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ - uint32_t reserved4: 5; - uint32_t w1ts: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ - uint32_t reserved11: 4; - uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_bbpll_cal_w1ts: 1; - uint32_t rtc_ble_compare_wake_w1ts: 1; - uint32_t vset_dcdc_done_w1ts: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } int_ena_w1ts; - union { - struct { - uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ - uint32_t reserved2: 1; - uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ - uint32_t reserved4: 5; - uint32_t w1tc: 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ - uint32_t reserved11: 4; - uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ - uint32_t reserved17: 2; - uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ - uint32_t rtc_bbpll_cal_w1tc: 1; - uint32_t rtc_ble_compare_wake_w1tc: 1; - uint32_t vset_dcdc_done_w1tc: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } int_ena_w1tc; - union { - struct { - uint32_t reserved0: 17; - uint32_t clk_en: 1; - uint32_t retention_clk_sel: 1; - uint32_t retention_done_wait: 3; - uint32_t retention_clkoff_wait: 4; - uint32_t retention_en: 1; - uint32_t retention_wait: 5; /*wait cycles for rention operation*/ - }; - uint32_t val; - } retention_ctrl; - union { - struct { - uint32_t retention_link_addr:27; - uint32_t reserved27: 5; - }; - uint32_t val; - } retention_ctrl1; - union { - struct { - uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } fib_sel; - union { - struct { - uint32_t rtc_gpio_wakeup_status: 6; - uint32_t rtc_gpio_wakeup_status_clr: 1; - uint32_t rtc_gpio_pin_clk_gate: 1; - uint32_t rtc_gpio_pin5_int_type: 3; - uint32_t rtc_gpio_pin4_int_type: 3; - uint32_t rtc_gpio_pin3_int_type: 3; - uint32_t rtc_gpio_pin2_int_type: 3; - uint32_t rtc_gpio_pin1_int_type: 3; - uint32_t rtc_gpio_pin0_int_type: 3; - uint32_t rtc_gpio_pin5_wakeup_enable: 1; - uint32_t rtc_gpio_pin4_wakeup_enable: 1; - uint32_t rtc_gpio_pin3_wakeup_enable: 1; - uint32_t rtc_gpio_pin2_wakeup_enable: 1; - uint32_t rtc_gpio_pin1_wakeup_enable: 1; - uint32_t rtc_gpio_pin0_wakeup_enable: 1; - }; - uint32_t val; - } gpio_wakeup; - union { - struct { - uint32_t rtc_mtdi_enamux: 1; - uint32_t rtc_debug_12m_no_gating: 1; - uint32_t rtc_debug_bit_sel: 5; - uint32_t rtc_debug_sel0: 5; - uint32_t rtc_debug_sel1: 5; - uint32_t rtc_debug_sel2: 5; - uint32_t rtc_debug_sel3: 5; - uint32_t rtc_debug_sel4: 5; - }; - uint32_t val; - } dbg_sel; - union { - struct { - uint32_t vdd_dig_test: 2; - uint32_t rtc_gpio_pin5_mux_sel: 1; - uint32_t rtc_gpio_pin4_mux_sel: 1; - uint32_t rtc_gpio_pin3_mux_sel: 1; - uint32_t rtc_gpio_pin2_mux_sel: 1; - uint32_t rtc_gpio_pin1_mux_sel: 1; - uint32_t rtc_gpio_pin0_mux_sel: 1; - uint32_t rtc_gpio_pin5_fun_sel: 4; - uint32_t rtc_gpio_pin4_fun_sel: 4; - uint32_t rtc_gpio_pin3_fun_sel: 4; - uint32_t rtc_gpio_pin2_fun_sel: 4; - uint32_t rtc_gpio_pin1_fun_sel: 4; - uint32_t rtc_gpio_pin0_fun_sel: 4; - }; - uint32_t val; - } dbg_map; - union { - struct { - uint32_t reserved0: 27; - uint32_t sar_debug_sel: 5; - }; - uint32_t val; - } dbg_sar_sel; - union { - struct { - uint32_t reserved0: 26; - uint32_t power_glitch_dsense: 2; - uint32_t power_glitch_force_pd: 1; - uint32_t power_glitch_force_pu: 1; - uint32_t power_glitch_efuse_sel: 1; - uint32_t power_glitch_en: 1; - }; - uint32_t val; - } pg_ctrl; - union { - struct { - uint32_t vset_dcdc_value: 5; - uint32_t power_good_dcdc: 1; - uint32_t reserved6: 15; - uint32_t ramplevel_dcdc: 1; - uint32_t ramp_dcdc: 1; - uint32_t dcm2enb_dcdc: 1; - uint32_t dcmlevel_dcdc: 2; - uint32_t fsw_dcdc: 3; - uint32_t ccm_dcdc: 1; - uint32_t sstime_dcdc: 1; - uint32_t pocpenb_dcdc: 1; - }; - uint32_t val; - } dcdc_ctrl0; - union { - struct { - uint32_t reserved0: 23; - uint32_t dcdc_mode_slp: 3; - uint32_t dcdc_mode_monitor: 3; - uint32_t dcdc_mode_idle: 3; - }; - uint32_t val; - } dcdc_ctrl1; - union { - struct { - uint32_t vset_dcdc_target_value1: 5; - uint32_t vset_dcdc_target_value0: 5; - uint32_t vset_dcdc_init_value: 5; - uint32_t vset_dcdc_init: 1; - uint32_t vset_dcdc_fix: 1; - uint32_t vset_dcdc_step: 5; - uint32_t vset_dcdc_gap: 5; - uint32_t vset_dcdc_sel_hw_sw: 1; - uint32_t vset_dcdc_sw_sel: 1; - uint32_t reserved29: 3; - }; - uint32_t val; - } dcdc_ctrl2; - union { - struct { - uint32_t reserved0: 21; - uint32_t rc32k_dfreq:10; - uint32_t rc32k_xpd: 1; - }; - uint32_t val; - } rc32k_ctrl; - union { - struct { - uint32_t reserved0: 30; - uint32_t ckref_pll8m_sel: 1; - uint32_t xpd_pll8m: 1; - }; - uint32_t val; - } pll8m; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - union { - struct { - uint32_t date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } date; -} rtc_cntl_dev_t; -extern rtc_cntl_dev_t RTCCNTL; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/sensitive_reg.h b/components/soc/esp32h4/include/rev1/soc/sensitive_reg.h deleted file mode 100644 index 4dcaef7903..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/sensitive_reg.h +++ /dev/null @@ -1,2512 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SENSITIVE_REG_H_ -#define _SOC_SENSITIVE_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) -/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_ROM_TABLE_LOCK (BIT(0)) -#define SENSITIVE_ROM_TABLE_LOCK_M (BIT(0)) -#define SENSITIVE_ROM_TABLE_LOCK_V 0x1 -#define SENSITIVE_ROM_TABLE_LOCK_S 0 - -#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x004) -/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_ROM_TABLE 0xFFFFFFFF -#define SENSITIVE_ROM_TABLE_M ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S)) -#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFF -#define SENSITIVE_ROM_TABLE_S 0 - -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x008) -/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK (BIT(0)) -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M (BIT(0)) -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V 0x1 -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S 0 - -#define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0x00C) -/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_PRIVILEGE_MODE_SEL (BIT(0)) -#define SENSITIVE_PRIVILEGE_MODE_SEL_M (BIT(0)) -#define SENSITIVE_PRIVILEGE_MODE_SEL_V 0x1 -#define SENSITIVE_PRIVILEGE_MODE_SEL_S 0 - -#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x010) -/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 - -#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x014) -/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 - -#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x018) -/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 - -#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x01C) -/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: ~3'h0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007 -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x7 -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 -/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: ~1'h0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x1 -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0 - -#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x020) -/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (BIT(3)) -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x1 -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 -/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007 -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x7 -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0 - -#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x024) -/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V 0x1 -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S 0 - -#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x028) -/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 - -#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x02C) -/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 -#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 -/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 -#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 -/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 -#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 -/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 -#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 - -#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x030) -/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 - -#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x034) -/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 -#define SENSITIVE_PRO_MMU_WR_ACS_S 1 -/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 -#define SENSITIVE_PRO_MMU_RD_ACS_S 0 - -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x038) -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x03C) -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x040) -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x044) -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x048) -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x04C) -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x050) -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x054) -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x058) -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x05C) -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x060) -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x064) -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x068) -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x06C) -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x070) -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x074) -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x078) -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x07C) -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x080) -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x084) -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x088) -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x08C) -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x090) -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x094) -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x098) -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 - -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x09C) -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 - -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0A0) -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 - -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0A4) -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xF -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 -/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 - -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0A8) -/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0AC) -/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000FF -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0xFF -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 -/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 -/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 -/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 - -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0B0) -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000FF -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0xFF -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 - -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0B4) -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000FF -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0xFF -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 -/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 - -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0B8) -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000FF -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0xFF -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 - -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0BC) -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000FF -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0xFF -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 -/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 - -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0C0) -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0C4) -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 - -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0C8) -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 -/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0CC) -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 - -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0D0) -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 - -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0D4) -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 -/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 - -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0D8) -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0DC) -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 - -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0E0) -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 - -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0E4) -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 - -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0E8) -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 - -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0EC) -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000F -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xF -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 -/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0F0) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0F4) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0F8) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0FC) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x100) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x104) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 12 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 8 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x108) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x10C) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x110) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x114) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S 30 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S 28 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S 26 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S 22 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S 20 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S 18 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x118) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 16 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 14 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 12 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 10 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 8 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 4 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x11C) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x120) -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 -/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124) -/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128) -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12C) -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 -/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x3 -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13C) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S 0 - -#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14C) -/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */ -/*description: */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFF -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x150) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x154) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x158) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x15C) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x160) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x164) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 - -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x168) -/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x16C) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x1 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x170) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S 30 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S 26 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S 24 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S 18 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S 16 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S 6 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S 4 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S 2 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x174) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S 30 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S 28 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S 18 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S 6 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S 4 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x178) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S 10 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S 4 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x17C) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S 30 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S 28 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S 26 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S 22 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S 20 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S 18 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S 16 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 14 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S 8 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S 6 -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 - -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x180) -/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x184) -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x1 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x188) -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V 0x1 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S 1 -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x1 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x18C) -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(6)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 6 -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 3 -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V 0x3 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S 1 -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x1 -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 - -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x190) -/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xFFFFFFFF -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xFFFFFFFF -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 - -#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x194) -/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SENSITIVE_CLK_EN (BIT(0)) -#define SENSITIVE_CLK_EN_M (BIT(0)) -#define SENSITIVE_CLK_EN_V 0x1 -#define SENSITIVE_CLK_EN_S 0 - -#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) -/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101190 ; */ -/*description: */ -#define SENSITIVE_DATE 0x0FFFFFFF -#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) -#define SENSITIVE_DATE_V 0xFFFFFFF -#define SENSITIVE_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SENSITIVE_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/sensitive_struct.h b/components/soc/esp32h4/include/rev1/soc/sensitive_struct.h deleted file mode 100644 index 5541ecca6e..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/sensitive_struct.h +++ /dev/null @@ -1,2017 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SENSITIVE_STRUCT_H_ -#define _SOC_SENSITIVE_STRUCT_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct sensitive_dev_s { - union { - struct { - uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } rom_table_lock; - uint32_t rom_table; - union { - struct { - uint32_t reg_privilege_mode_sel_lock : 1; /*privilege_mode_sel_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } privilege_mode_sel_lock; - union { - struct { - uint32_t reg_privilege_mode_sel : 1; /*privilege_mode_sel*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } privilege_mode_sel; - union { - struct { - uint32_t reg_apb_peripheral_access_lock: 1; /*apb_peripheral_access_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } apb_peripheral_access_0; - union { - struct { - uint32_t reg_apb_peripheral_access_split_burst: 1; /*apb_peripheral_access_split_burst*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } apb_peripheral_access_1; - union { - struct { - uint32_t reg_internal_sram_usage_lock : 1; /*internal_sram_usage_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } internal_sram_usage_0; - union { - struct { - uint32_t reg_internal_sram_usage_cpu_cache: 1; /*internal_sram_usage_cpu_cache*/ - uint32_t reg_internal_sram_usage_cpu_sram: 3; /*internal_sram_usage_cpu_sram*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } internal_sram_usage_1; - union { - struct { - uint32_t reg_internal_sram_usage_mac_dump_sram: 3; /*internal_sram_usage_mac_dump_sram*/ - uint32_t reg_internal_sram_alloc_mac_dump: 1; /*internal_sram_alloc_mac_dump*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } internal_sram_usage_3; - union { - struct { - uint32_t reg_internal_sram_usage_log_sram: 1; /*internal_sram_usage_log_sram*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } internal_sram_usage_4; - union { - struct { - uint32_t reg_cache_tag_access_lock : 1; /*cache_tag_access_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } cache_tag_access_0; - union { - struct { - uint32_t reg_pro_i_tag_rd_acs : 1; /*pro_i_tag_rd_acs*/ - uint32_t reg_pro_i_tag_wr_acs : 1; /*pro_i_tag_wr_acs*/ - uint32_t reg_pro_d_tag_rd_acs : 1; /*pro_d_tag_rd_acs*/ - uint32_t reg_pro_d_tag_wr_acs : 1; /*pro_d_tag_wr_acs*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } cache_tag_access_1; - union { - struct { - uint32_t reg_cache_mmu_access_lock : 1; /*cache_mmu_access_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } cache_mmu_access_0; - union { - struct { - uint32_t reg_pro_mmu_rd_acs : 1; /*pro_mmu_rd_acs*/ - uint32_t reg_pro_mmu_wr_acs : 1; /*pro_mmu_wr_acs*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } cache_mmu_access_1; - union { - struct { - uint32_t reg_dma_apbperi_spi2_pms_constrain_lock: 1; /*dma_apbperi_spi2_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_spi2_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_spi2_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_uchi0_pms_constrain_lock: 1; /*dma_apbperi_uchi0_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_uchi0_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_uchi0_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_i2s0_pms_constrain_lock: 1; /*dma_apbperi_i2s0_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_i2s0_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_i2s0_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_mac_pms_constrain_lock: 1; /*dma_apbperi_mac_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_mac_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_mac_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_backup_pms_constrain_lock: 1; /*dma_apbperi_backup_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_backup_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_backup_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_lc_pms_constrain_lock: 1; /*dma_apbperi_lc_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_lc_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_lc_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_aes_pms_constrain_lock: 1; /*dma_apbperi_aes_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_aes_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_aes_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_sha_pms_constrain_lock: 1; /*dma_apbperi_sha_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_sha_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_sha_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_lock: 1; /*dma_apbperi_adc_dac_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } dma_apbperi_adc_dac_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3: 2; /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reserved24 : 8; - }; - uint32_t val; - } dma_apbperi_adc_dac_pms_constrain_1; - union { - struct { - uint32_t dma_apbperi_ble_sec_pms_constrain_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } dma_apbperi_ble_sec_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0: 2; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1: 2; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2: 2; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3: 2; - uint32_t reserved8: 4; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0: 2; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1: 2; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2: 2; - uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3: 2; - uint32_t reserved20: 4; - uint32_t reserved24: 8; - }; - uint32_t val; - } dma_apbperi_ble_sec_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_white_list_pms_constrain_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } dma_apbperi_white_list_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0: 2; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1: 2; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2: 2; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3: 2; - uint32_t reserved8: 4; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0: 2; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1: 2; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2: 2; - uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3: 2; - uint32_t reserved20: 4; - uint32_t reserved24: 8; - }; - uint32_t val; - } dma_apbperi_white_list_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } dma_apbperi_sdio_host_pms_constrain_0; - union { - struct { - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0: 2; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1: 2; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2: 2; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3: 2; - uint32_t reserved8: 4; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0: 2; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1: 2; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2: 2; - uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3: 2; - uint32_t reserved20: 4; - uint32_t reserved24: 8; - }; - uint32_t val; - } dma_apbperi_sdio_host_pms_constrain_1; - union { - struct { - uint32_t reg_dma_apbperi_pms_monitor_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } dma_apbperi_pms_monitor_0; - union { - struct { - uint32_t reg_dma_apbperi_pms_monitor_violate_clr: 1; /*dma_apbperi_pms_monitor_violate_clr*/ - uint32_t reg_dma_apbperi_pms_monitor_violate_en: 1; /*dma_apbperi_pms_monitor_violate_en*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } dma_apbperi_pms_monitor_1; - union { - struct { - uint32_t reg_dma_apbperi_pms_monitor_violate_intr: 1; /*dma_apbperi_pms_monitor_violate_intr*/ - uint32_t reg_dma_apbperi_pms_monitor_violate_status_world: 2; /*dma_apbperi_pms_monitor_violate_status_world*/ - uint32_t reg_dma_apbperi_pms_monitor_violate_status_addr: 24; /*dma_apbperi_pms_monitor_violate_status_addr*/ - uint32_t reserved27 : 5; - }; - uint32_t val; - } dma_apbperi_pms_monitor_2; - union { - struct { - uint32_t reg_dma_apbperi_pms_monitor_violate_status_wr: 1; /*dma_apbperi_pms_monitor_violate_status_wr*/ - uint32_t reg_dma_apbperi_pms_monitor_violate_status_byteen: 4; /*dma_apbperi_pms_monitor_violate_status_byteen*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } dma_apbperi_pms_monitor_3; - union { - struct { - uint32_t reg_core_x_iram0_dram0_dma_split_line_constrain_lock: 1; /*core_x_iram0_dram0_dma_split_line_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_x_iram0_dram0_dma_split_line_constrain_0; - union { - struct { - uint32_t reg_core_x_iram0_dram0_dma_sram_category_0: 2; /*core_x_iram0_dram0_dma_sram_category_0*/ - uint32_t reg_core_x_iram0_dram0_dma_sram_category_1: 2; /*core_x_iram0_dram0_dma_sram_category_1*/ - uint32_t reg_core_x_iram0_dram0_dma_sram_category_2: 2; /*core_x_iram0_dram0_dma_sram_category_2*/ - uint32_t reserved6 : 8; - uint32_t reg_core_x_iram0_dram0_dma_sram_splitaddr: 8; /*core_x_iram0_dram0_dma_sram_splitaddr*/ - uint32_t reserved22 : 10; - }; - uint32_t val; - } core_x_iram0_dram0_dma_split_line_constrain_1; - union { - struct { - uint32_t reg_core_x_iram0_sram_line_0_category_0: 2; /*core_x_iram0_sram_line_0_category_0*/ - uint32_t reg_core_x_iram0_sram_line_0_category_1: 2; /*core_x_iram0_sram_line_0_category_1*/ - uint32_t reg_core_x_iram0_sram_line_0_category_2: 2; /*core_x_iram0_sram_line_0_category_2*/ - uint32_t reserved6 : 8; - uint32_t reg_core_x_iram0_sram_line_0_splitaddr: 8; /*core_x_iram0_sram_line_0_splitaddr*/ - uint32_t reserved22 : 10; - }; - uint32_t val; - } core_x_iram0_dram0_dma_split_line_constrain_2; - union { - struct { - uint32_t reg_core_x_iram0_sram_line_1_category_0: 2; /*core_x_iram0_sram_line_1_category_0*/ - uint32_t reg_core_x_iram0_sram_line_1_category_1: 2; /*core_x_iram0_sram_line_1_category_1*/ - uint32_t reg_core_x_iram0_sram_line_1_category_2: 2; /*core_x_iram0_sram_line_1_category_2*/ - uint32_t reserved6 : 8; - uint32_t reg_core_x_iram0_sram_line_1_splitaddr: 8; /*core_x_iram0_sram_line_1_splitaddr*/ - uint32_t reserved22 : 10; - }; - uint32_t val; - } core_x_iram0_dram0_dma_split_line_constrain_3; - union { - struct { - uint32_t reg_core_x_dram0_dma_sram_line_0_category_0: 2; /*core_x_dram0_dma_sram_line_0_category_0*/ - uint32_t reg_core_x_dram0_dma_sram_line_0_category_1: 2; /*core_x_dram0_dma_sram_line_0_category_1*/ - uint32_t reg_core_x_dram0_dma_sram_line_0_category_2: 2; /*core_x_dram0_dma_sram_line_0_category_2*/ - uint32_t reserved6 : 8; - uint32_t reg_core_x_dram0_dma_sram_line_0_splitaddr: 8; /*core_x_dram0_dma_sram_line_0_splitaddr*/ - uint32_t reserved22 : 10; - }; - uint32_t val; - } core_x_iram0_dram0_dma_split_line_constrain_4; - union { - struct { - uint32_t reg_core_x_dram0_dma_sram_line_1_category_0: 2; /*core_x_dram0_dma_sram_line_1_category_0*/ - uint32_t reg_core_x_dram0_dma_sram_line_1_category_1: 2; /*core_x_dram0_dma_sram_line_1_category_1*/ - uint32_t reg_core_x_dram0_dma_sram_line_1_category_2: 2; /*core_x_dram0_dma_sram_line_1_category_2*/ - uint32_t reserved6 : 8; - uint32_t reg_core_x_dram0_dma_sram_line_1_splitaddr: 8; /*core_x_dram0_dma_sram_line_1_splitaddr*/ - uint32_t reserved22 : 10; - }; - uint32_t val; - } core_x_iram0_dram0_dma_split_line_constrain_5; - union { - struct { - uint32_t reg_core_x_iram0_pms_constrain_lock: 1; /*core_x_iram0_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_x_iram0_pms_constrain_0; - union { - struct { - uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_1: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_2: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_3: 3; /*core_x_iram0_pms_constrain_sram_world_1_pms_3*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0*/ - uint32_t reserved15 : 3; - uint32_t reg_core_x_iram0_pms_constrain_rom_world_1_pms: 3; /*core_x_iram0_pms_constrain_rom_world_1_pms*/ - uint32_t reserved21 : 11; - }; - uint32_t val; - } core_x_iram0_pms_constrain_1; - union { - struct { - uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_1: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_2: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_3: 3; /*core_x_iram0_pms_constrain_sram_world_0_pms_3*/ - uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 3; /*core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0*/ - uint32_t reserved15 : 3; - uint32_t reg_core_x_iram0_pms_constrain_rom_world_0_pms: 3; /*core_x_iram0_pms_constrain_rom_world_0_pms*/ - uint32_t reserved21 : 11; - }; - uint32_t val; - } core_x_iram0_pms_constrain_2; - union { - struct { - uint32_t reg_core_0_iram0_pms_monitor_lock: 1; /*core_0_iram0_pms_monitor_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_0_iram0_pms_monitor_0; - union { - struct { - uint32_t reg_core_0_iram0_pms_monitor_violate_clr: 1; /*core_0_iram0_pms_monitor_violate_clr*/ - uint32_t reg_core_0_iram0_pms_monitor_violate_en: 1; /*core_0_iram0_pms_monitor_violate_en*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } core_0_iram0_pms_monitor_1; - union { - struct { - uint32_t reg_core_0_iram0_pms_monitor_violate_intr: 1; /*core_0_iram0_pms_monitor_violate_intr*/ - uint32_t reg_core_0_iram0_pms_monitor_violate_status_wr: 1; /*core_0_iram0_pms_monitor_violate_status_wr*/ - uint32_t reg_core_0_iram0_pms_monitor_violate_status_loadstore: 1; /*core_0_iram0_pms_monitor_violate_status_loadstore*/ - uint32_t reg_core_0_iram0_pms_monitor_violate_status_world: 2; /*core_0_iram0_pms_monitor_violate_status_world*/ - uint32_t reg_core_0_iram0_pms_monitor_violate_status_addr: 24; /*core_0_iram0_pms_monitor_violate_status_addr*/ - uint32_t reserved29 : 3; - }; - uint32_t val; - } core_0_iram0_pms_monitor_2; - union { - struct { - uint32_t reg_core_x_dram0_pms_constrain_lock: 1; /*core_x_dram0_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_x_dram0_pms_constrain_0; - union { - struct { - uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_0: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_0*/ - uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_1: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_1*/ - uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_2: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_2*/ - uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_3: 2; /*core_x_dram0_pms_constrain_sram_world_0_pms_3*/ - uint32_t reserved8 : 4; - uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_0: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_0*/ - uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_1: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_1*/ - uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_2: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_2*/ - uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_3: 2; /*core_x_dram0_pms_constrain_sram_world_1_pms_3*/ - uint32_t reserved20 : 4; - uint32_t reg_core_x_dram0_pms_constrain_rom_world_0_pms: 2; /*core_x_dram0_pms_constrain_rom_world_0_pms*/ - uint32_t reg_core_x_dram0_pms_constrain_rom_world_1_pms: 2; /*core_x_dram0_pms_constrain_rom_world_1_pms*/ - uint32_t reserved28 : 4; - }; - uint32_t val; - } core_x_dram0_pms_constrain_1; - union { - struct { - uint32_t reg_core_0_dram0_pms_monitor_lock: 1; /*core_0_dram0_pms_monitor_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_0_dram0_pms_monitor_0; - union { - struct { - uint32_t reg_core_0_dram0_pms_monitor_violate_clr: 1; /*core_0_dram0_pms_monitor_violate_clr*/ - uint32_t reg_core_0_dram0_pms_monitor_violate_en: 1; /*core_0_dram0_pms_monitor_violate_en*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } core_0_dram0_pms_monitor_1; - union { - struct { - uint32_t reg_core_0_dram0_pms_monitor_violate_intr: 1; /*core_0_dram0_pms_monitor_violate_intr*/ - uint32_t reg_core_0_dram0_pms_monitor_violate_status_lock: 1; /*core_0_dram0_pms_monitor_violate_status_lock*/ - uint32_t reg_core_0_dram0_pms_monitor_violate_status_world: 2; /*core_0_dram0_pms_monitor_violate_status_world*/ - uint32_t reg_core_0_dram0_pms_monitor_violate_status_addr: 24; /*core_0_dram0_pms_monitor_violate_status_addr*/ - uint32_t reserved28 : 4; - }; - uint32_t val; - } core_0_dram0_pms_monitor_2; - union { - struct { - uint32_t reg_core_0_dram0_pms_monitor_violate_status_wr: 1; /*core_0_dram0_pms_monitor_violate_status_wr*/ - uint32_t reg_core_0_dram0_pms_monitor_violate_status_byteen: 4; /*core_0_dram0_pms_monitor_violate_status_byteen*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } core_0_dram0_pms_monitor_3; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_lock: 1; /*core_0_pif_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_0_pif_pms_constrain_0; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_0_uart: 2; /*core_0_pif_pms_constrain_world_0_uart*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1: 2; /*core_0_pif_pms_constrain_world_0_g0spi_1*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0: 2; /*core_0_pif_pms_constrain_world_0_g0spi_0*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_gpio: 2; /*core_0_pif_pms_constrain_world_0_gpio*/ - uint32_t reserved8: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_fe: 2; /*core_0_pif_pms_constrain_world_0_fe*/ - uint32_t reserved12: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_rtc: 2; /*core_0_pif_pms_constrain_world_0_rtc*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux: 2; /*core_0_pif_pms_constrain_world_0_io_mux*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_wdg: 2; /*core_0_pif_pms_constrain_world_0_wdg*/ - uint32_t reserved20 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_0_misc: 2; /*core_0_pif_pms_constrain_world_0_misc*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_i2c: 2; /*core_0_pif_pms_constrain_world_0_i2c*/ - uint32_t reserved28 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_uart1: 2; /*core_0_pif_pms_constrain_world_0_uart1*/ - }; - uint32_t val; - } core_0_pif_pms_constrain_1; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_0_bt: 2; /*core_0_pif_pms_constrain_world_0_bt*/ - uint32_t reserved2 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_i2c_ext0: 2; /*core_0_pif_pms_constrain_world_0_i2c_ext0*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_uhci0: 2; /*core_0_pif_pms_constrain_world_0_uhci0*/ - uint32_t reserved8 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_rmt: 2; /*core_0_pif_pms_constrain_world_0_rmt*/ - uint32_t reserved12 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_0_ledc: 2; /*core_0_pif_pms_constrain_world_0_ledc*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_efuse: 2; - uint32_t reserved20: 2; - uint32_t reserved22: 2; - uint32_t reserved24: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_systimer: 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_2; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_0_spi_2: 2; /*core_0_pif_pms_constrain_world_0_spi_2*/ - uint32_t reserved2 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl: 2; /*core_0_pif_pms_constrain_world_0_apb_ctrl*/ - uint32_t reserved6 : 4; - uint32_t reg_core_0_pif_pms_constrain_world_0_twai: 2; /*core_0_pif_pms_constrain_world_0_twai*/ - uint32_t reserved12 : 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1: 2; /*core_0_pif_pms_constrain_world_0_i2s1*/ - uint32_t reserved16 : 6; - uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt: 2; /*core_0_pif_pms_constrain_world_0_rwbt*/ - uint32_t reserved24 : 2; - uint32_t reserved26: 2; - uint32_t reserved28: 2; - uint32_t reserved30 : 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_3; - union { - struct { - uint32_t reserved0 : 2; - uint32_t reserved2: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri: 2; /*core_0_pif_pms_constrain_world_0_crypto_peri*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma: 2; /*core_0_pif_pms_constrain_world_0_crypto_dma*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc: 2; /*core_0_pif_pms_constrain_world_0_apb_adc*/ - uint32_t reserved10 : 2; - uint32_t reserved12: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device: 2; /*core_0_pif_pms_constrain_world_0_usb_device*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_etm: 2; /*core_0_pif_pms_constrain_world_0_system*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup3: 2; /*core_0_pif_pms_constrain_world_0_sensitive*/ - uint32_t reg_core_0_pif_pms_constrain_world_0_ble_sec: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_ieee802154mac: 2; - uint32_t reserved24: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_coex: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_rtc_ble_tmr: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_clkrst: 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_4; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_0_pvt: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_system: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_ad: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_dio: 2; - uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller: 2; - uint32_t reserved18: 14; - }; - uint32_t val; - } core_0_pif_pms_constrain_5; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_uart: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_gpio: 2; - uint32_t reserved8: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_fe: 2; - uint32_t reserved12: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_rtc: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_wdg: 2; - uint32_t reserved20: 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_misc: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_i2c: 2; - uint32_t reserved28: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_uart1: 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_6; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_bt: 2; - uint32_t reserved2: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0: 2; - uint32_t reserved8: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_rmt: 2; - uint32_t reserved12: 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_ledc: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_efuse: 2; - uint32_t reserved20: 2; - uint32_t reserved22: 2; - uint32_t reserved24: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_systimer: 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_7; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2: 2; - uint32_t reserved2: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2; - uint32_t reserved6: 4; - uint32_t reg_core_0_pif_pms_constrain_world_1_twai: 2; - uint32_t reserved12: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; - uint32_t reserved16: 6; - uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; - uint32_t reserved24: 2; - uint32_t reserved26: 2; - uint32_t reserved28: 2; - uint32_t reserved30: 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_8; - union { - struct { - uint32_t reserved0: 2; - uint32_t reserved2: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc: 2; - uint32_t reserved10: 2; - uint32_t reserved12: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_etm: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup3: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_ble_sec: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_ieee802154mac: 2; - uint32_t reserved24: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_coex: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_rtc_ble_tmr: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_clkrst: 2; - }; - uint32_t val; - } core_0_pif_pms_constrain_9; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_world_1_pvt: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_system: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_ad: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_dio: 2; - uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller: 2; - uint32_t reserved18: 14; - }; - uint32_t val; - } core_0_pif_pms_constrain_10; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:11; - uint32_t reg_ore_0_pif_pms_constrain_rtcfast_spltaddr_world_1:11; - uint32_t reserved22: 10; - }; - uint32_t val; - } core_0_pif_pms_constrain_11; - union { - struct { - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l: 3; - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h: 3; - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l: 3; - uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h: 3; - uint32_t reserved12: 20; - }; - uint32_t val; - } core_0_pif_pms_constrain_12; - union { - struct { - uint32_t region_pms_constrain_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } sensitiveion_pms_constrain_0; - union { - struct { - uint32_t reg_region_pms_constrain_world_0_area_0: 2; /*region_pms_constrain_world_0_area_0*/ - uint32_t reg_region_pms_constrain_world_0_area_1: 2; /*region_pms_constrain_world_0_area_1*/ - uint32_t reg_region_pms_constrain_world_0_area_2: 2; /*region_pms_constrain_world_0_area_2*/ - uint32_t reg_region_pms_constrain_world_0_area_3: 2; /*region_pms_constrain_world_0_area_3*/ - uint32_t reg_region_pms_constrain_world_0_area_4: 2; /*region_pms_constrain_world_0_area_4*/ - uint32_t reg_region_pms_constrain_world_0_area_5: 2; /*region_pms_constrain_world_0_area_5*/ - uint32_t reg_region_pms_constrain_world_0_area_6: 2; /*region_pms_constrain_world_0_area_6*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } sensitiveion_pms_constrain_1; - union { - struct { - uint32_t reg_region_pms_constrain_world_1_area_0: 2; /*region_pms_constrain_world_1_area_0*/ - uint32_t reg_region_pms_constrain_world_1_area_1: 2; /*region_pms_constrain_world_1_area_1*/ - uint32_t reg_region_pms_constrain_world_1_area_2: 2; /*region_pms_constrain_world_1_area_2*/ - uint32_t reg_region_pms_constrain_world_1_area_3: 2; /*region_pms_constrain_world_1_area_3*/ - uint32_t reg_region_pms_constrain_world_1_area_4: 2; /*region_pms_constrain_world_1_area_4*/ - uint32_t reg_region_pms_constrain_world_1_area_5: 2; /*region_pms_constrain_world_1_area_5*/ - uint32_t reg_region_pms_constrain_world_1_area_6: 2; /*region_pms_constrain_world_1_area_6*/ - uint32_t reserved14 : 18; - }; - uint32_t val; - } sensitiveion_pms_constrain_2; - union { - struct { - uint32_t reg_region_pms_constrain_addr_0: 30; /*region_pms_constrain_addr_0*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_3; - union { - struct { - uint32_t reg_region_pms_constrain_addr_1: 30; /*region_pms_constrain_addr_1*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_4; - union { - struct { - uint32_t reg_region_pms_constrain_addr_2: 30; /*region_pms_constrain_addr_2*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_5; - union { - struct { - uint32_t reg_region_pms_constrain_addr_3: 30; /*region_pms_constrain_addr_3*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_6; - union { - struct { - uint32_t reg_region_pms_constrain_addr_4: 30; /*region_pms_constrain_addr_4*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_7; - union { - struct { - uint32_t reg_region_pms_constrain_addr_5: 30; /*region_pms_constrain_addr_5*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_8; - union { - struct { - uint32_t reg_region_pms_constrain_addr_6: 30; /*region_pms_constrain_addr_6*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_9; - union { - struct { - uint32_t reg_region_pms_constrain_addr_7: 30; /*region_pms_constrain_addr_7*/ - uint32_t reserved30 : 2; - }; - uint32_t val; - } sensitiveion_pms_constrain_10; - union { - struct { - uint32_t reg_core_0_pif_pms_monitor_lock: 1; /*core_0_pif_pms_monitor_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } core_0_pif_pms_monitor_0; - union { - struct { - uint32_t reg_core_0_pif_pms_monitor_violate_clr: 1; /*core_0_pif_pms_monitor_violate_clr*/ - uint32_t reg_core_0_pif_pms_monitor_violate_en: 1; /*core_0_pif_pms_monitor_violate_en*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } core_0_pif_pms_monitor_1; - union { - struct { - uint32_t reg_core_0_pif_pms_monitor_violate_intr: 1; /*core_0_pif_pms_monitor_violate_intr*/ - uint32_t reg_core_0_pif_pms_monitor_violate_status_hport_0: 1; /*core_0_pif_pms_monitor_violate_status_hport_0*/ - uint32_t reg_core_0_pif_pms_monitor_violate_status_hsize: 3; /*core_0_pif_pms_monitor_violate_status_hsize*/ - uint32_t reg_core_0_pif_pms_monitor_violate_status_hwrite: 1; /*core_0_pif_pms_monitor_violate_status_hwrite*/ - uint32_t reg_core_0_pif_pms_monitor_violate_status_hworld: 2; /*core_0_pif_pms_monitor_violate_status_hworld*/ - uint32_t reserved8 : 24; - }; - uint32_t val; - } core_0_pif_pms_monitor_2; - uint32_t core_0_pif_pms_monitor_3; - union { - struct { - uint32_t reg_core_0_pif_pms_monitor_nonword_violate_clr: 1; /*core_0_pif_pms_monitor_nonword_violate_clr*/ - uint32_t reg_core_0_pif_pms_monitor_nonword_violate_en: 1; /*core_0_pif_pms_monitor_nonword_violate_en*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } core_0_pif_pms_monitor_4; - union { - struct { - uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr: 1; /*core_0_pif_pms_monitor_nonword_violate_intr*/ - uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/ - uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/ - uint32_t reserved5: 27; - }; - uint32_t val; - } core_0_pif_pms_monitor_5; - uint32_t core_0_pif_pms_monitor_6; - union { - struct { - uint32_t reg_backup_bus_pms_constrain_lock: 1; /*backup_bus_pms_constrain_lock*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } backup_bus_pms_constrain_0; - union { - struct { - uint32_t reg_backup_bus_pms_constrain_uart: 2; /*backup_bus_pms_constrain_uart*/ - uint32_t reg_backup_bus_pms_constrain_g0spi_1: 2; /*backup_bus_pms_constrain_g0spi_1*/ - uint32_t reg_backup_bus_pms_constrain_g0spi_0: 2; /*backup_bus_pms_constrain_g0spi_0*/ - uint32_t reg_backup_bus_pms_constrain_gpio: 2; /*backup_bus_pms_constrain_gpio*/ - uint32_t reserved8: 2; - uint32_t reg_backup_bus_pms_constrain_fe: 2; /*backup_bus_pms_constrain_fe*/ - uint32_t reserved12: 2; - uint32_t reg_backup_bus_pms_constrain_rtc: 2; /*backup_bus_pms_constrain_rtc*/ - uint32_t reg_backup_bus_pms_constrain_io_mux: 2; /*backup_bus_pms_constrain_io_mux*/ - uint32_t reg_backup_bus_pms_constrain_wdg: 2; /*backup_bus_pms_constrain_wdg*/ - uint32_t reserved20 : 4; - uint32_t reg_backup_bus_pms_constrain_misc: 2; /*backup_bus_pms_constrain_misc*/ - uint32_t reg_backup_bus_pms_constrain_i2c: 2; /*backup_bus_pms_constrain_i2c*/ - uint32_t reserved28 : 2; - uint32_t reg_backup_bus_pms_constrain_uart1: 2; /*backup_bus_pms_constrain_uart1*/ - }; - uint32_t val; - } backup_bus_pms_constrain_1; - union { - struct { - uint32_t reg_backup_bus_pms_constrain_bt: 2; /*backup_bus_pms_constrain_bt*/ - uint32_t reserved2 : 2; - uint32_t reg_backup_bus_pms_constrain_i2c_ext0: 2; /*backup_bus_pms_constrain_i2c_ext0*/ - uint32_t reg_backup_bus_pms_constrain_uhci0: 2; /*backup_bus_pms_constrain_uhci0*/ - uint32_t reserved8 : 2; - uint32_t reg_backup_bus_pms_constrain_rmt: 2; /*backup_bus_pms_constrain_rmt*/ - uint32_t reserved12 : 4; - uint32_t reg_backup_bus_pms_constrain_ledc: 2; /*backup_bus_pms_constrain_ledc*/ - uint32_t reg_backup_bus_pms_constrain_efuse: 2; - uint32_t reserved20 : 2; - uint32_t reserved22 : 2; - uint32_t reserved24 : 2; - uint32_t reg_backup_bus_pms_constrain_timergroup: 2; /*backup_bus_pms_constrain_timergroup*/ - uint32_t reg_backup_bus_pms_constrain_timergroup1: 2; /*backup_bus_pms_constrain_timergroup1*/ - uint32_t reg_backup_bus_pms_constrain_systimer: 2; /*backup_bus_pms_constrain_systimer*/ - }; - uint32_t val; - } backup_bus_pms_constrain_2; - union { - struct { - uint32_t reg_backup_bus_pms_constrain_spi_2: 2; /*backup_bus_pms_constrain_spi_2*/ - uint32_t reserved2 : 2; - uint32_t reg_backup_bus_pms_constrain_apb_ctrl: 2; /*backup_bus_pms_constrain_apb_ctrl*/ - uint32_t reserved6 : 4; - uint32_t reg_backup_bus_pms_constrain_twai: 2; /*backup_bus_pms_constrain_twai*/ - uint32_t reserved12 : 2; - uint32_t reg_backup_bus_pms_constrain_i2s1: 2; /*backup_bus_pms_constrain_i2s1*/ - uint32_t reserved16 : 6; - uint32_t reg_backup_bus_pms_constrain_rwbt: 2; /*backup_bus_pms_constrain_rwbt*/ - uint32_t reserved24 : 2; - uint32_t reserved26 : 2; - uint32_t reserved28 : 2; - uint32_t reserved30 : 2; - }; - uint32_t val; - } backup_bus_pms_constrain_3; - union { - struct { - uint32_t reserved0: 2; - uint32_t reserved2: 2; - uint32_t reg_backup_bus_pms_constrain_crypto_peri: 2; - uint32_t reg_backup_bus_pms_constrain_crypto_dma: 2; - uint32_t reg_backup_bus_pms_constrain_apb_adc: 2; - uint32_t reserved10: 2; - uint32_t reserved12: 2; - uint32_t reg_backup_bus_pms_constrain_usb_device: 2; - uint32_t reg_backup_bus_pms_constrain_etm: 2; - uint32_t reg_backup_bus_pms_constrain_timergroup3: 2; - uint32_t reg_backup_bus_pms_constrain_ble_sec: 2; - uint32_t backup_bus_pms_constrain_ieee802154mac: 2; - uint32_t reserved24: 2; - uint32_t reg_backup_bus_pms_constrain_coex: 2; - uint32_t reg_backup_bus_pms_constrain_rtc_ble_tmr: 2; - uint32_t reg_backup_bus_pms_constrain_clkrst: 2; - }; - uint32_t val; - } backup_bus_pms_constrain_4; - union { - struct { - uint32_t backup_bus_pms_constrain_pvt: 2; - uint32_t reserved2: 30; - }; - uint32_t val; - } backup_bus_pms_constrain_5; - union { - struct { - uint32_t backup_bus_pms_monitor_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } backup_bus_pms_monitor_0; - union { - struct { - uint32_t reg_backup_bus_pms_monitor_violate_clr: 1; /*backup_bus_pms_monitor_violate_clr*/ - uint32_t reg_backup_bus_pms_monitor_violate_en: 1; /*backup_bus_pms_monitor_violate_en*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } backup_bus_pms_monitor_1; - union { - struct { - uint32_t reg_backup_bus_pms_monitor_violate_intr: 1; /*backup_bus_pms_monitor_violate_intr*/ - uint32_t reg_backup_bus_pms_monitor_violate_status_htrans: 2; /*backup_bus_pms_monitor_violate_status_htrans*/ - uint32_t reg_backup_bus_pms_monitor_violate_status_hsize: 3; /*backup_bus_pms_monitor_violate_status_hsize*/ - uint32_t reg_backup_bus_pms_monitor_violate_status_hwrite: 1; /*backup_bus_pms_monitor_violate_status_hwrite*/ - uint32_t reserved7 : 25; - }; - uint32_t val; - } backup_bus_pms_monitor_2; - uint32_t backup_bus_pms_monitor_3; - union { - struct { - uint32_t reg_clk_en: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } clock_gate; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t reserved_400; - uint32_t reserved_404; - uint32_t reserved_408; - uint32_t reserved_40c; - uint32_t reserved_410; - uint32_t reserved_414; - uint32_t reserved_418; - uint32_t reserved_41c; - uint32_t reserved_420; - uint32_t reserved_424; - uint32_t reserved_428; - uint32_t reserved_42c; - uint32_t reserved_430; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - uint32_t reserved_47c; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t reserved_500; - uint32_t reserved_504; - uint32_t reserved_508; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t reserved_540; - uint32_t reserved_544; - uint32_t reserved_548; - uint32_t reserved_54c; - uint32_t reserved_550; - uint32_t reserved_554; - uint32_t reserved_558; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t reserved_580; - uint32_t reserved_584; - uint32_t reserved_588; - uint32_t reserved_58c; - uint32_t reserved_590; - uint32_t reserved_594; - uint32_t reserved_598; - uint32_t reserved_59c; - uint32_t reserved_5a0; - uint32_t reserved_5a4; - uint32_t reserved_5a8; - uint32_t reserved_5ac; - uint32_t reserved_5b0; - uint32_t reserved_5b4; - uint32_t reserved_5b8; - uint32_t reserved_5bc; - uint32_t reserved_5c0; - uint32_t reserved_5c4; - uint32_t reserved_5c8; - uint32_t reserved_5cc; - uint32_t reserved_5d0; - uint32_t reserved_5d4; - uint32_t reserved_5d8; - uint32_t reserved_5dc; - uint32_t reserved_5e0; - uint32_t reserved_5e4; - uint32_t reserved_5e8; - uint32_t reserved_5ec; - uint32_t reserved_5f0; - uint32_t reserved_5f4; - uint32_t reserved_5f8; - uint32_t reserved_5fc; - uint32_t reserved_600; - uint32_t reserved_604; - uint32_t reserved_608; - uint32_t reserved_60c; - uint32_t reserved_610; - uint32_t reserved_614; - uint32_t reserved_618; - uint32_t reserved_61c; - uint32_t reserved_620; - uint32_t reserved_624; - uint32_t reserved_628; - uint32_t reserved_62c; - uint32_t reserved_630; - uint32_t reserved_634; - uint32_t reserved_638; - uint32_t reserved_63c; - uint32_t reserved_640; - uint32_t reserved_644; - uint32_t reserved_648; - uint32_t reserved_64c; - uint32_t reserved_650; - uint32_t reserved_654; - uint32_t reserved_658; - uint32_t reserved_65c; - uint32_t reserved_660; - uint32_t reserved_664; - uint32_t reserved_668; - uint32_t reserved_66c; - uint32_t reserved_670; - uint32_t reserved_674; - uint32_t reserved_678; - uint32_t reserved_67c; - uint32_t reserved_680; - uint32_t reserved_684; - uint32_t reserved_688; - uint32_t reserved_68c; - uint32_t reserved_690; - uint32_t reserved_694; - uint32_t reserved_698; - uint32_t reserved_69c; - uint32_t reserved_6a0; - uint32_t reserved_6a4; - uint32_t reserved_6a8; - uint32_t reserved_6ac; - uint32_t reserved_6b0; - uint32_t reserved_6b4; - uint32_t reserved_6b8; - uint32_t reserved_6bc; - uint32_t reserved_6c0; - uint32_t reserved_6c4; - uint32_t reserved_6c8; - uint32_t reserved_6cc; - uint32_t reserved_6d0; - uint32_t reserved_6d4; - uint32_t reserved_6d8; - uint32_t reserved_6dc; - uint32_t reserved_6e0; - uint32_t reserved_6e4; - uint32_t reserved_6e8; - uint32_t reserved_6ec; - uint32_t reserved_6f0; - uint32_t reserved_6f4; - uint32_t reserved_6f8; - uint32_t reserved_6fc; - uint32_t reserved_700; - uint32_t reserved_704; - uint32_t reserved_708; - uint32_t reserved_70c; - uint32_t reserved_710; - uint32_t reserved_714; - uint32_t reserved_718; - uint32_t reserved_71c; - uint32_t reserved_720; - uint32_t reserved_724; - uint32_t reserved_728; - uint32_t reserved_72c; - uint32_t reserved_730; - uint32_t reserved_734; - uint32_t reserved_738; - uint32_t reserved_73c; - uint32_t reserved_740; - uint32_t reserved_744; - uint32_t reserved_748; - uint32_t reserved_74c; - uint32_t reserved_750; - uint32_t reserved_754; - uint32_t reserved_758; - uint32_t reserved_75c; - uint32_t reserved_760; - uint32_t reserved_764; - uint32_t reserved_768; - uint32_t reserved_76c; - uint32_t reserved_770; - uint32_t reserved_774; - uint32_t reserved_778; - uint32_t reserved_77c; - uint32_t reserved_780; - uint32_t reserved_784; - uint32_t reserved_788; - uint32_t reserved_78c; - uint32_t reserved_790; - uint32_t reserved_794; - uint32_t reserved_798; - uint32_t reserved_79c; - uint32_t reserved_7a0; - uint32_t reserved_7a4; - uint32_t reserved_7a8; - uint32_t reserved_7ac; - uint32_t reserved_7b0; - uint32_t reserved_7b4; - uint32_t reserved_7b8; - uint32_t reserved_7bc; - uint32_t reserved_7c0; - uint32_t reserved_7c4; - uint32_t reserved_7c8; - uint32_t reserved_7cc; - uint32_t reserved_7d0; - uint32_t reserved_7d4; - uint32_t reserved_7d8; - uint32_t reserved_7dc; - uint32_t reserved_7e0; - uint32_t reserved_7e4; - uint32_t reserved_7e8; - uint32_t reserved_7ec; - uint32_t reserved_7f0; - uint32_t reserved_7f4; - uint32_t reserved_7f8; - uint32_t reserved_7fc; - uint32_t reserved_800; - uint32_t reserved_804; - uint32_t reserved_808; - uint32_t reserved_80c; - uint32_t reserved_810; - uint32_t reserved_814; - uint32_t reserved_818; - uint32_t reserved_81c; - uint32_t reserved_820; - uint32_t reserved_824; - uint32_t reserved_828; - uint32_t reserved_82c; - uint32_t reserved_830; - uint32_t reserved_834; - uint32_t reserved_838; - uint32_t reserved_83c; - uint32_t reserved_840; - uint32_t reserved_844; - uint32_t reserved_848; - uint32_t reserved_84c; - uint32_t reserved_850; - uint32_t reserved_854; - uint32_t reserved_858; - uint32_t reserved_85c; - uint32_t reserved_860; - uint32_t reserved_864; - uint32_t reserved_868; - uint32_t reserved_86c; - uint32_t reserved_870; - uint32_t reserved_874; - uint32_t reserved_878; - uint32_t reserved_87c; - uint32_t reserved_880; - uint32_t reserved_884; - uint32_t reserved_888; - uint32_t reserved_88c; - uint32_t reserved_890; - uint32_t reserved_894; - uint32_t reserved_898; - uint32_t reserved_89c; - uint32_t reserved_8a0; - uint32_t reserved_8a4; - uint32_t reserved_8a8; - uint32_t reserved_8ac; - uint32_t reserved_8b0; - uint32_t reserved_8b4; - uint32_t reserved_8b8; - uint32_t reserved_8bc; - uint32_t reserved_8c0; - uint32_t reserved_8c4; - uint32_t reserved_8c8; - uint32_t reserved_8cc; - uint32_t reserved_8d0; - uint32_t reserved_8d4; - uint32_t reserved_8d8; - uint32_t reserved_8dc; - uint32_t reserved_8e0; - uint32_t reserved_8e4; - uint32_t reserved_8e8; - uint32_t reserved_8ec; - uint32_t reserved_8f0; - uint32_t reserved_8f4; - uint32_t reserved_8f8; - uint32_t reserved_8fc; - uint32_t reserved_900; - uint32_t reserved_904; - uint32_t reserved_908; - uint32_t reserved_90c; - uint32_t reserved_910; - uint32_t reserved_914; - uint32_t reserved_918; - uint32_t reserved_91c; - uint32_t reserved_920; - uint32_t reserved_924; - uint32_t reserved_928; - uint32_t reserved_92c; - uint32_t reserved_930; - uint32_t reserved_934; - uint32_t reserved_938; - uint32_t reserved_93c; - uint32_t reserved_940; - uint32_t reserved_944; - uint32_t reserved_948; - uint32_t reserved_94c; - uint32_t reserved_950; - uint32_t reserved_954; - uint32_t reserved_958; - uint32_t reserved_95c; - uint32_t reserved_960; - uint32_t reserved_964; - uint32_t reserved_968; - uint32_t reserved_96c; - uint32_t reserved_970; - uint32_t reserved_974; - uint32_t reserved_978; - uint32_t reserved_97c; - uint32_t reserved_980; - uint32_t reserved_984; - uint32_t reserved_988; - uint32_t reserved_98c; - uint32_t reserved_990; - uint32_t reserved_994; - uint32_t reserved_998; - uint32_t reserved_99c; - uint32_t reserved_9a0; - uint32_t reserved_9a4; - uint32_t reserved_9a8; - uint32_t reserved_9ac; - uint32_t reserved_9b0; - uint32_t reserved_9b4; - uint32_t reserved_9b8; - uint32_t reserved_9bc; - uint32_t reserved_9c0; - uint32_t reserved_9c4; - uint32_t reserved_9c8; - uint32_t reserved_9cc; - uint32_t reserved_9d0; - uint32_t reserved_9d4; - uint32_t reserved_9d8; - uint32_t reserved_9dc; - uint32_t reserved_9e0; - uint32_t reserved_9e4; - uint32_t reserved_9e8; - uint32_t reserved_9ec; - uint32_t reserved_9f0; - uint32_t reserved_9f4; - uint32_t reserved_9f8; - uint32_t reserved_9fc; - uint32_t reserved_a00; - uint32_t reserved_a04; - uint32_t reserved_a08; - uint32_t reserved_a0c; - uint32_t reserved_a10; - uint32_t reserved_a14; - uint32_t reserved_a18; - uint32_t reserved_a1c; - uint32_t reserved_a20; - uint32_t reserved_a24; - uint32_t reserved_a28; - uint32_t reserved_a2c; - uint32_t reserved_a30; - uint32_t reserved_a34; - uint32_t reserved_a38; - uint32_t reserved_a3c; - uint32_t reserved_a40; - uint32_t reserved_a44; - uint32_t reserved_a48; - uint32_t reserved_a4c; - uint32_t reserved_a50; - uint32_t reserved_a54; - uint32_t reserved_a58; - uint32_t reserved_a5c; - uint32_t reserved_a60; - uint32_t reserved_a64; - uint32_t reserved_a68; - uint32_t reserved_a6c; - uint32_t reserved_a70; - uint32_t reserved_a74; - uint32_t reserved_a78; - uint32_t reserved_a7c; - uint32_t reserved_a80; - uint32_t reserved_a84; - uint32_t reserved_a88; - uint32_t reserved_a8c; - uint32_t reserved_a90; - uint32_t reserved_a94; - uint32_t reserved_a98; - uint32_t reserved_a9c; - uint32_t reserved_aa0; - uint32_t reserved_aa4; - uint32_t reserved_aa8; - uint32_t reserved_aac; - uint32_t reserved_ab0; - uint32_t reserved_ab4; - uint32_t reserved_ab8; - uint32_t reserved_abc; - uint32_t reserved_ac0; - uint32_t reserved_ac4; - uint32_t reserved_ac8; - uint32_t reserved_acc; - uint32_t reserved_ad0; - uint32_t reserved_ad4; - uint32_t reserved_ad8; - uint32_t reserved_adc; - uint32_t reserved_ae0; - uint32_t reserved_ae4; - uint32_t reserved_ae8; - uint32_t reserved_aec; - uint32_t reserved_af0; - uint32_t reserved_af4; - uint32_t reserved_af8; - uint32_t reserved_afc; - uint32_t reserved_b00; - uint32_t reserved_b04; - uint32_t reserved_b08; - uint32_t reserved_b0c; - uint32_t reserved_b10; - uint32_t reserved_b14; - uint32_t reserved_b18; - uint32_t reserved_b1c; - uint32_t reserved_b20; - uint32_t reserved_b24; - uint32_t reserved_b28; - uint32_t reserved_b2c; - uint32_t reserved_b30; - uint32_t reserved_b34; - uint32_t reserved_b38; - uint32_t reserved_b3c; - uint32_t reserved_b40; - uint32_t reserved_b44; - uint32_t reserved_b48; - uint32_t reserved_b4c; - uint32_t reserved_b50; - uint32_t reserved_b54; - uint32_t reserved_b58; - uint32_t reserved_b5c; - uint32_t reserved_b60; - uint32_t reserved_b64; - uint32_t reserved_b68; - uint32_t reserved_b6c; - uint32_t reserved_b70; - uint32_t reserved_b74; - uint32_t reserved_b78; - uint32_t reserved_b7c; - uint32_t reserved_b80; - uint32_t reserved_b84; - uint32_t reserved_b88; - uint32_t reserved_b8c; - uint32_t reserved_b90; - uint32_t reserved_b94; - uint32_t reserved_b98; - uint32_t reserved_b9c; - uint32_t reserved_ba0; - uint32_t reserved_ba4; - uint32_t reserved_ba8; - uint32_t reserved_bac; - uint32_t reserved_bb0; - uint32_t reserved_bb4; - uint32_t reserved_bb8; - uint32_t reserved_bbc; - uint32_t reserved_bc0; - uint32_t reserved_bc4; - uint32_t reserved_bc8; - uint32_t reserved_bcc; - uint32_t reserved_bd0; - uint32_t reserved_bd4; - uint32_t reserved_bd8; - uint32_t reserved_bdc; - uint32_t reserved_be0; - uint32_t reserved_be4; - uint32_t reserved_be8; - uint32_t reserved_bec; - uint32_t reserved_bf0; - uint32_t reserved_bf4; - uint32_t reserved_bf8; - uint32_t reserved_bfc; - uint32_t reserved_c00; - uint32_t reserved_c04; - uint32_t reserved_c08; - uint32_t reserved_c0c; - uint32_t reserved_c10; - uint32_t reserved_c14; - uint32_t reserved_c18; - uint32_t reserved_c1c; - uint32_t reserved_c20; - uint32_t reserved_c24; - uint32_t reserved_c28; - uint32_t reserved_c2c; - uint32_t reserved_c30; - uint32_t reserved_c34; - uint32_t reserved_c38; - uint32_t reserved_c3c; - uint32_t reserved_c40; - uint32_t reserved_c44; - uint32_t reserved_c48; - uint32_t reserved_c4c; - uint32_t reserved_c50; - uint32_t reserved_c54; - uint32_t reserved_c58; - uint32_t reserved_c5c; - uint32_t reserved_c60; - uint32_t reserved_c64; - uint32_t reserved_c68; - uint32_t reserved_c6c; - uint32_t reserved_c70; - uint32_t reserved_c74; - uint32_t reserved_c78; - uint32_t reserved_c7c; - uint32_t reserved_c80; - uint32_t reserved_c84; - uint32_t reserved_c88; - uint32_t reserved_c8c; - uint32_t reserved_c90; - uint32_t reserved_c94; - uint32_t reserved_c98; - uint32_t reserved_c9c; - uint32_t reserved_ca0; - uint32_t reserved_ca4; - uint32_t reserved_ca8; - uint32_t reserved_cac; - uint32_t reserved_cb0; - uint32_t reserved_cb4; - uint32_t reserved_cb8; - uint32_t reserved_cbc; - uint32_t reserved_cc0; - uint32_t reserved_cc4; - uint32_t reserved_cc8; - uint32_t reserved_ccc; - uint32_t reserved_cd0; - uint32_t reserved_cd4; - uint32_t reserved_cd8; - uint32_t reserved_cdc; - uint32_t reserved_ce0; - uint32_t reserved_ce4; - uint32_t reserved_ce8; - uint32_t reserved_cec; - uint32_t reserved_cf0; - uint32_t reserved_cf4; - uint32_t reserved_cf8; - uint32_t reserved_cfc; - uint32_t reserved_d00; - uint32_t reserved_d04; - uint32_t reserved_d08; - uint32_t reserved_d0c; - uint32_t reserved_d10; - uint32_t reserved_d14; - uint32_t reserved_d18; - uint32_t reserved_d1c; - uint32_t reserved_d20; - uint32_t reserved_d24; - uint32_t reserved_d28; - uint32_t reserved_d2c; - uint32_t reserved_d30; - uint32_t reserved_d34; - uint32_t reserved_d38; - uint32_t reserved_d3c; - uint32_t reserved_d40; - uint32_t reserved_d44; - uint32_t reserved_d48; - uint32_t reserved_d4c; - uint32_t reserved_d50; - uint32_t reserved_d54; - uint32_t reserved_d58; - uint32_t reserved_d5c; - uint32_t reserved_d60; - uint32_t reserved_d64; - uint32_t reserved_d68; - uint32_t reserved_d6c; - uint32_t reserved_d70; - uint32_t reserved_d74; - uint32_t reserved_d78; - uint32_t reserved_d7c; - uint32_t reserved_d80; - uint32_t reserved_d84; - uint32_t reserved_d88; - uint32_t reserved_d8c; - uint32_t reserved_d90; - uint32_t reserved_d94; - uint32_t reserved_d98; - uint32_t reserved_d9c; - uint32_t reserved_da0; - uint32_t reserved_da4; - uint32_t reserved_da8; - uint32_t reserved_dac; - uint32_t reserved_db0; - uint32_t reserved_db4; - uint32_t reserved_db8; - uint32_t reserved_dbc; - uint32_t reserved_dc0; - uint32_t reserved_dc4; - uint32_t reserved_dc8; - uint32_t reserved_dcc; - uint32_t reserved_dd0; - uint32_t reserved_dd4; - uint32_t reserved_dd8; - uint32_t reserved_ddc; - uint32_t reserved_de0; - uint32_t reserved_de4; - uint32_t reserved_de8; - uint32_t reserved_dec; - uint32_t reserved_df0; - uint32_t reserved_df4; - uint32_t reserved_df8; - uint32_t reserved_dfc; - uint32_t reserved_e00; - uint32_t reserved_e04; - uint32_t reserved_e08; - uint32_t reserved_e0c; - uint32_t reserved_e10; - uint32_t reserved_e14; - uint32_t reserved_e18; - uint32_t reserved_e1c; - uint32_t reserved_e20; - uint32_t reserved_e24; - uint32_t reserved_e28; - uint32_t reserved_e2c; - uint32_t reserved_e30; - uint32_t reserved_e34; - uint32_t reserved_e38; - uint32_t reserved_e3c; - uint32_t reserved_e40; - uint32_t reserved_e44; - uint32_t reserved_e48; - uint32_t reserved_e4c; - uint32_t reserved_e50; - uint32_t reserved_e54; - uint32_t reserved_e58; - uint32_t reserved_e5c; - uint32_t reserved_e60; - uint32_t reserved_e64; - uint32_t reserved_e68; - uint32_t reserved_e6c; - uint32_t reserved_e70; - uint32_t reserved_e74; - uint32_t reserved_e78; - uint32_t reserved_e7c; - uint32_t reserved_e80; - uint32_t reserved_e84; - uint32_t reserved_e88; - uint32_t reserved_e8c; - uint32_t reserved_e90; - uint32_t reserved_e94; - uint32_t reserved_e98; - uint32_t reserved_e9c; - uint32_t reserved_ea0; - uint32_t reserved_ea4; - uint32_t reserved_ea8; - uint32_t reserved_eac; - uint32_t reserved_eb0; - uint32_t reserved_eb4; - uint32_t reserved_eb8; - uint32_t reserved_ebc; - uint32_t reserved_ec0; - uint32_t reserved_ec4; - uint32_t reserved_ec8; - uint32_t reserved_ecc; - uint32_t reserved_ed0; - uint32_t reserved_ed4; - uint32_t reserved_ed8; - uint32_t reserved_edc; - uint32_t reserved_ee0; - uint32_t reserved_ee4; - uint32_t reserved_ee8; - uint32_t reserved_eec; - uint32_t reserved_ef0; - uint32_t reserved_ef4; - uint32_t reserved_ef8; - uint32_t reserved_efc; - uint32_t reserved_f00; - uint32_t reserved_f04; - uint32_t reserved_f08; - uint32_t reserved_f0c; - uint32_t reserved_f10; - uint32_t reserved_f14; - uint32_t reserved_f18; - uint32_t reserved_f1c; - uint32_t reserved_f20; - uint32_t reserved_f24; - uint32_t reserved_f28; - uint32_t reserved_f2c; - uint32_t reserved_f30; - uint32_t reserved_f34; - uint32_t reserved_f38; - uint32_t reserved_f3c; - uint32_t reserved_f40; - uint32_t reserved_f44; - uint32_t reserved_f48; - uint32_t reserved_f4c; - uint32_t reserved_f50; - uint32_t reserved_f54; - uint32_t reserved_f58; - uint32_t reserved_f5c; - uint32_t reserved_f60; - uint32_t reserved_f64; - uint32_t reserved_f68; - uint32_t reserved_f6c; - uint32_t reserved_f70; - uint32_t reserved_f74; - uint32_t reserved_f78; - uint32_t reserved_f7c; - uint32_t reserved_f80; - uint32_t reserved_f84; - uint32_t reserved_f88; - uint32_t reserved_f8c; - uint32_t reserved_f90; - uint32_t reserved_f94; - uint32_t reserved_f98; - uint32_t reserved_f9c; - uint32_t reserved_fa0; - uint32_t reserved_fa4; - uint32_t reserved_fa8; - uint32_t reserved_fac; - uint32_t reserved_fb0; - uint32_t reserved_fb4; - uint32_t reserved_fb8; - uint32_t reserved_fbc; - uint32_t reserved_fc0; - uint32_t reserved_fc4; - uint32_t reserved_fc8; - uint32_t reserved_fcc; - uint32_t reserved_fd0; - uint32_t reserved_fd4; - uint32_t reserved_fd8; - uint32_t reserved_fdc; - uint32_t reserved_fe0; - uint32_t reserved_fe4; - uint32_t reserved_fe8; - uint32_t reserved_fec; - uint32_t reserved_ff0; - uint32_t reserved_ff4; - uint32_t reserved_ff8; - union { - struct { - uint32_t reg_date : 28; /*reg_date*/ - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; -} sensitive_dev_t; -extern sensitive_dev_t SENSITIVE; -#ifdef __cplusplus -} -#endif - -#endif /*_SOC_SENSITIVE_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/syscon_reg.h b/components/soc/esp32h4/include/rev1/soc/syscon_reg.h deleted file mode 100644 index 68eaea2e83..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/syscon_reg.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SYSCON_REG_H_ -#define _SOC_SYSCON_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) -/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) -#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_S 0 - -#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) -/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) -#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF -#define SYSCON_WIFI_BB_CFG_2_S 0 - -#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) -/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SYSCON_PERI_IO_SWAP 0x000000FF -#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) -#define SYSCON_PERI_IO_SWAP_V 0xFF -#define SYSCON_PERI_IO_SWAP_S 0 - -#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) -/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) -#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) -#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 -#define SYSCON_EXT_MEM_PMS_LOCK_S 0 - -#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) -/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: */ -#define SYSCON_FLASH_ACE0_ATTR 0x00000003 -#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) -#define SYSCON_FLASH_ACE0_ATTR_V 0x3 -#define SYSCON_FLASH_ACE0_ATTR_S 0 - -#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) -/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: */ -#define SYSCON_FLASH_ACE1_ATTR 0x00000003 -#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) -#define SYSCON_FLASH_ACE1_ATTR_V 0x3 -#define SYSCON_FLASH_ACE1_ATTR_S 0 - -#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) -/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: */ -#define SYSCON_FLASH_ACE2_ATTR 0x00000003 -#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) -#define SYSCON_FLASH_ACE2_ATTR_V 0x3 -#define SYSCON_FLASH_ACE2_ATTR_S 0 - -#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034) -/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ -/*description: */ -#define SYSCON_FLASH_ACE3_ATTR 0x00000003 -#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) -#define SYSCON_FLASH_ACE3_ATTR_V 0x3 -#define SYSCON_FLASH_ACE3_ATTR_S 0 - -#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) -/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) -#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE0_ADDR_S_S 0 - -#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) -/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ -/*description: */ -#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) -#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE1_ADDR_S_S 0 - -#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) -/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ -/*description: */ -#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) -#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE2_ADDR_S_S 0 - -#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044) -/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */ -/*description: */ -#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF -#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) -#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF -#define SYSCON_FLASH_ACE3_ADDR_S_S 0 - -#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) -/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: */ -#define SYSCON_FLASH_ACE0_SIZE 0x00001FFF -#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) -#define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF -#define SYSCON_FLASH_ACE0_SIZE_S 0 - -#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) -/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: */ -#define SYSCON_FLASH_ACE1_SIZE 0x00001FFF -#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) -#define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF -#define SYSCON_FLASH_ACE1_SIZE_S 0 - -#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) -/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: */ -#define SYSCON_FLASH_ACE2_SIZE 0x00001FFF -#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) -#define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF -#define SYSCON_FLASH_ACE2_SIZE_S 0 - -#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054) -/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ -/*description: */ -#define SYSCON_FLASH_ACE3_SIZE 0x00001FFF -#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) -#define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF -#define SYSCON_FLASH_ACE3_SIZE_S 0 - -#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088) -/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ -/*description: */ -#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F -#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) -#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F -#define SYSCON_SPI_MEM_REJECT_CDE_S 2 -/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) -#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) -#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 -#define SYSCON_SPI_MEM_REJECT_CLR_S 1 -/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) -#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) -#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 -#define SYSCON_SPI_MEM_REJECT_INT_S 0 - -#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C) -/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF -#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) -#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF -#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 - -#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090) -/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) -#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) -#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 -#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 - -#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094) -/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SYSCON_REDCY_ANDOR (BIT(31)) -#define SYSCON_REDCY_ANDOR_M (BIT(31)) -#define SYSCON_REDCY_ANDOR_V 0x1 -#define SYSCON_REDCY_ANDOR_S 31 -/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ -/*description: */ -#define SYSCON_REDCY_SIG0 0x7FFFFFFF -#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) -#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF -#define SYSCON_REDCY_SIG0_S 0 - -#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098) -/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SYSCON_REDCY_NANDOR (BIT(31)) -#define SYSCON_REDCY_NANDOR_M (BIT(31)) -#define SYSCON_REDCY_NANDOR_V 0x1 -#define SYSCON_REDCY_NANDOR_S 31 -/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ -/*description: */ -#define SYSCON_REDCY_SIG1 0x7FFFFFFF -#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) -#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF -#define SYSCON_REDCY_SIG1_S 0 - -#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C) -/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) -#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) -#define SYSCON_DC_MEM_FORCE_PD_V 0x1 -#define SYSCON_DC_MEM_FORCE_PD_S 5 -/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) -#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) -#define SYSCON_DC_MEM_FORCE_PU_V 0x1 -#define SYSCON_DC_MEM_FORCE_PU_S 4 -/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) -#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) -#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 -#define SYSCON_PBUS_MEM_FORCE_PD_S 3 -/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) -#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) -#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 -#define SYSCON_PBUS_MEM_FORCE_PU_S 2 -/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) -#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) -#define SYSCON_AGC_MEM_FORCE_PD_V 0x1 -#define SYSCON_AGC_MEM_FORCE_PD_S 1 -/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) -#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) -#define SYSCON_AGC_MEM_FORCE_PU_V 0x1 -#define SYSCON_AGC_MEM_FORCE_PU_S 0 - -#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0) -/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) -#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) -#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 -#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 - -#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4) -/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ -/*description: */ -#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F -#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) -#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF -#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2 -/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003 -#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) -#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x3 -#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 - -#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0A8) -/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */ -/*description: */ -#define SYSCON_SRAM_POWER_DOWN 0x0000000F -#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) -#define SYSCON_SRAM_POWER_DOWN_V 0xF -#define SYSCON_SRAM_POWER_DOWN_S 2 -/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define SYSCON_ROM_POWER_DOWN 0x00000003 -#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) -#define SYSCON_ROM_POWER_DOWN_V 0x3 -#define SYSCON_ROM_POWER_DOWN_S 0 - -#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0AC) -/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ -/*description: */ -#define SYSCON_SRAM_POWER_UP 0x0000000F -#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) -#define SYSCON_SRAM_POWER_UP_V 0xF -#define SYSCON_SRAM_POWER_UP_S 2 -/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ -/*description: */ -#define SYSCON_ROM_POWER_UP 0x00000003 -#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) -#define SYSCON_ROM_POWER_UP_V 0x3 -#define SYSCON_ROM_POWER_UP_S 0 - -#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0x0B0) -/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSCON_RND_DATA 0xFFFFFFFF -#define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S)) -#define SYSCON_RND_DATA_V 0xFFFFFFFF -#define SYSCON_RND_DATA_S 0 - -#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0x0B4) -/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_ENA (BIT(31)) -#define SYSCON_PERI_BACKUP_ENA_M (BIT(31)) -#define SYSCON_PERI_BACKUP_ENA_V 0x1 -#define SYSCON_PERI_BACKUP_ENA_S 31 -/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_TO_MEM (BIT(30)) -#define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30)) -#define SYSCON_PERI_BACKUP_TO_MEM_V 0x1 -#define SYSCON_PERI_BACKUP_TO_MEM_S 30 -/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_START (BIT(29)) -#define SYSCON_PERI_BACKUP_START_M (BIT(29)) -#define SYSCON_PERI_BACKUP_START_V 0x1 -#define SYSCON_PERI_BACKUP_START_S 29 -/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_SIZE 0x000003FF -#define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S)) -#define SYSCON_PERI_BACKUP_SIZE_V 0x3FF -#define SYSCON_PERI_BACKUP_SIZE_S 19 -/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF -#define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S)) -#define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF -#define SYSCON_PERI_BACKUP_TOUT_THRES_S 9 -/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F -#define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S)) -#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F -#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 -/* SYSCON_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE (BIT(3)) -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3)) -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V 0x1 -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S 3 -/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000007 -#define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S)) -#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x7 -#define SYSCON_PERI_BACKUP_FLOW_ERR_S 0 - -#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8) -/* SYSCON_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_APB_START_ADDR_M ((SYSCON_PERI_BACKUP_APB_START_ADDR_V)<<(SYSCON_PERI_BACKUP_APB_START_ADDR_S)) -#define SYSCON_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_APB_START_ADDR_S 0 - -#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC) -/* SYSCON_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MEM_START_ADDR_M ((SYSCON_PERI_BACKUP_MEM_START_ADDR_V)<<(SYSCON_PERI_BACKUP_MEM_START_ADDR_S)) -#define SYSCON_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MEM_START_ADDR_S 0 - -#define SYSCON_PERI_BACKUP_MAP0_REG (DR_REG_SYSCON_BASE + 0x0C0) -/* SYSCON_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_MAP0 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP0_M ((SYSCON_PERI_BACKUP_MAP0_V)<<(SYSCON_PERI_BACKUP_MAP0_S)) -#define SYSCON_PERI_BACKUP_MAP0_V 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP0_S 0 - -#define SYSCON_PERI_BACKUP_MAP1_REG (DR_REG_SYSCON_BASE + 0x0C4) -/* SYSCON_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_MAP1 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP1_M ((SYSCON_PERI_BACKUP_MAP1_V)<<(SYSCON_PERI_BACKUP_MAP1_S)) -#define SYSCON_PERI_BACKUP_MAP1_V 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP1_S 0 - -#define SYSCON_PERI_BACKUP_MAP2_REG (DR_REG_SYSCON_BASE + 0x0C8) -/* SYSCON_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_MAP2 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP2_M ((SYSCON_PERI_BACKUP_MAP2_V)<<(SYSCON_PERI_BACKUP_MAP2_S)) -#define SYSCON_PERI_BACKUP_MAP2_V 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP2_S 0 - -#define SYSCON_PERI_BACKUP_MAP3_REG (DR_REG_SYSCON_BASE + 0x0CC) -/* SYSCON_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_MAP3 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP3_M ((SYSCON_PERI_BACKUP_MAP3_V)<<(SYSCON_PERI_BACKUP_MAP3_S)) -#define SYSCON_PERI_BACKUP_MAP3_V 0xFFFFFFFF -#define SYSCON_PERI_BACKUP_MAP3_S 0 - -#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0D0) -/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1 -#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1 -/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1 -#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 - -#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0D4) -/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1 -#define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1 -/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1 -#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 - -#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0D8) -/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1 -#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1 -/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1 -#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 - -#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0DC) -/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1 -#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1 -/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1 -#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 - -#define SYSCON_CLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0E0) -/* SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_CLK_EN (BIT(0)) -#define SYSCON_CLK_EN_M (BIT(0)) -#define SYSCON_CLK_EN_V 0x1 -#define SYSCON_CLK_EN_S 0 - -#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) -/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */ -/*description: Version control*/ -#define SYSCON_DATE 0xFFFFFFFF -#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) -#define SYSCON_DATE_V 0xFFFFFFFF -#define SYSCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SYSCON_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/syscon_struct.h b/components/soc/esp32h4/include/rev1/soc/syscon_struct.h deleted file mode 100644 index a7c1849d3f..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/syscon_struct.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SYSCON_STRUCT_H_ -#define _SOC_SYSCON_STRUCT_H_ -#include -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct syscon_dev_s { - uint32_t reserved_0; - uint32_t reserved_4; - uint32_t reserved_8; - uint32_t wifi_bb_cfg; /**/ - uint32_t wifi_bb_cfg_2; /**/ - uint32_t reserved_14; - uint32_t reserved_18; - union { - struct { - uint32_t peri_io_swap: 8; - uint32_t reserved8: 24; - }; - uint32_t val; - } host_inf_sel; - union { - struct { - uint32_t ext_mem_pms_lock: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } ext_mem_pms_lock; - uint32_t reserved_24; - union { - struct { - uint32_t flash_ace0_attr: 2; - uint32_t reserved2: 30; - }; - uint32_t val; - } flash_ace0_attr; - union { - struct { - uint32_t flash_ace1_attr: 2; - uint32_t reserved2: 30; - }; - uint32_t val; - } flash_ace1_attr; - union { - struct { - uint32_t flash_ace2_attr: 2; - uint32_t reserved2: 30; - }; - uint32_t val; - } flash_ace2_attr; - union { - struct { - uint32_t flash_ace3_attr: 2; - uint32_t reserved2: 30; - }; - uint32_t val; - } flash_ace3_attr; - uint32_t flash_ace0_addr; /**/ - uint32_t flash_ace1_addr; /**/ - uint32_t flash_ace2_addr; /**/ - uint32_t flash_ace3_addr; /**/ - union { - struct { - uint32_t flash_ace0_size:13; - uint32_t reserved13: 19; - }; - uint32_t val; - } flash_ace0_size; - union { - struct { - uint32_t flash_ace1_size:13; - uint32_t reserved13: 19; - }; - uint32_t val; - } flash_ace1_size; - union { - struct { - uint32_t flash_ace2_size:13; - uint32_t reserved13: 19; - }; - uint32_t val; - } flash_ace2_size; - union { - struct { - uint32_t flash_ace3_size:13; - uint32_t reserved13: 19; - }; - uint32_t val; - } flash_ace3_size; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - union { - struct { - uint32_t spi_mem_reject_int: 1; - uint32_t spi_mem_reject_clr: 1; - uint32_t spi_mem_reject_cde: 5; - uint32_t reserved7: 25; - }; - uint32_t val; - } spi_mem_pms_ctrl; - uint32_t spi_mem_reject_addr; /**/ - union { - struct { - uint32_t sdio_win_access_en: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } sdio_ctrl; - union { - struct { - uint32_t redcy_sig0: 31; - uint32_t redcy_andor: 1; - }; - uint32_t val; - } redcy_sig0; - union { - struct { - uint32_t redcy_sig1: 31; - uint32_t redcy_nandor: 1; - }; - uint32_t val; - } redcy_sig1; - union { - struct { - uint32_t agc_mem_force_pu: 1; - uint32_t agc_mem_force_pd: 1; - uint32_t pbus_mem_force_pu: 1; - uint32_t pbus_mem_force_pd: 1; - uint32_t dc_mem_force_pu: 1; - uint32_t dc_mem_force_pd: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } front_end_mem_pd; - union { - struct { - uint32_t retention_link_addr: 27; - uint32_t nobypass_cpu_iso_rst: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } retention_ctrl; - union { - struct { - uint32_t rom_clkgate_force_on: 2; - uint32_t sram_clkgate_force_on: 4; - uint32_t reserved6: 26; - }; - uint32_t val; - } clkgate_force_on; - union { - struct { - uint32_t rom_power_down: 2; - uint32_t sram_power_down: 4; - uint32_t reserved6: 26; - }; - uint32_t val; - } mem_power_down; - union { - struct { - uint32_t rom_power_up: 2; - uint32_t sram_power_up: 4; - uint32_t reserved6: 26; - }; - uint32_t val; - } mem_power_up; - uint32_t rnd_data; /**/ - union { - struct { - uint32_t peri_backup_flow_err: 3; - uint32_t peri_backup_addr_map_mode: 1; - uint32_t peri_backup_burst_limit: 5; - uint32_t peri_backup_tout_thres: 10; - uint32_t peri_backup_size: 10; - uint32_t peri_backup_start: 1; - uint32_t peri_backup_to_mem: 1; - uint32_t peri_backup_ena: 1; - }; - uint32_t val; - } peri_backup_config; - uint32_t peri_backup_apb_addr; /**/ - uint32_t peri_backup_mem_addr; /**/ - uint32_t peri_backup_map0; /**/ - uint32_t peri_backup_map1; /**/ - uint32_t peri_backup_map2; /**/ - uint32_t peri_backup_map3; /**/ - union { - struct { - uint32_t peri_backup_done: 1; - uint32_t peri_backup_err: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } peri_backup_int_raw; - union { - struct { - uint32_t peri_backup_done: 1; - uint32_t peri_backup_err: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } peri_backup_int_st; - union { - struct { - uint32_t peri_backup_done: 1; - uint32_t peri_backup_err: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } peri_backup_int_ena; - union { - struct { - uint32_t peri_backup_done: 1; - uint32_t peri_backup_err: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } peri_backup_int_clr; - union { - struct { - uint32_t clk_en: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } clk_conf; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t date; /*Version control*/ -} syscon_dev_t; -extern syscon_dev_t SYSCON; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_SYSCON_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/system_reg.h b/components/soc/esp32h4/include/rev1/soc/system_reg.h deleted file mode 100644 index 0d8095361f..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/system_reg.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SYSTEM_REG_H_ -#define _SOC_SYSTEM_REG_H_ - -#include "soc/soc.h" -#include "soc/clkrst_reg.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000) -/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 -#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 -/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 -#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 - -#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004) -/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 -#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 -/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 -#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 - -#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008) -/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: */ -#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F -#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) -#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF -#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 -/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 - -#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C) -/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 -#define SYSTEM_LSLP_MEM_PD_MASK_S 0 - -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x010) -/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 - -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x014) -/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 - -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x018) -/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 - -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x01C) -/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 -#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 - -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x020) -/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 -#define SYSTEM_RSA_MEM_FORCE_PD_S 2 -/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 -#define SYSTEM_RSA_MEM_FORCE_PU_S 1 -/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_RSA_MEM_PD (BIT(0)) -#define SYSTEM_RSA_MEM_PD_M (BIT(0)) -#define SYSTEM_RSA_MEM_PD_V 0x1 -#define SYSTEM_RSA_MEM_PD_S 0 - -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x024) -/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_EDMA_RESET (BIT(1)) -#define SYSTEM_EDMA_RESET_M (BIT(1)) -#define SYSTEM_EDMA_RESET_V 0x1 -#define SYSTEM_EDMA_RESET_S 1 -/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_EDMA_CLK_ON (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_V 0x1 -#define SYSTEM_EDMA_CLK_ON_S 0 - -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x028) -/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_DCACHE_RESET (BIT(3)) -#define SYSTEM_DCACHE_RESET_M (BIT(3)) -#define SYSTEM_DCACHE_RESET_V 0x1 -#define SYSTEM_DCACHE_RESET_S 3 -/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_DCACHE_CLK_ON (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_V 0x1 -#define SYSTEM_DCACHE_CLK_ON_S 2 -/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ICACHE_RESET (BIT(1)) -#define SYSTEM_ICACHE_RESET_M (BIT(1)) -#define SYSTEM_ICACHE_RESET_V 0x1 -#define SYSTEM_ICACHE_RESET_S 1 -/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_ICACHE_CLK_ON (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_V 0x1 -#define SYSTEM_ICACHE_CLK_ON_S 0 - -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x02C) -/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 -/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 -/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 -/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 - -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x030) -/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 -#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 -/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF -#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) -#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF -#define SYSTEM_RTC_MEM_CRC_LEN_S 20 -/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF -#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) -#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF -#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 -/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_V 0x1 -#define SYSTEM_RTC_MEM_CRC_START_S 8 - -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x034) -/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF -#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) -#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF -#define SYSTEM_RTC_MEM_CRC_RES_S 0 - -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038) -/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 -#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 -/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 -#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 - -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x03C) -/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (BIT(0)) -#define SYSTEM_CLK_EN_V 0x1 -#define SYSTEM_CLK_EN_S 0 - -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x040) -/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: */ -#define SYSTEM_MEM_VT_SEL 0x00000003 -#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) -#define SYSTEM_MEM_VT_SEL_V 0x3 -#define SYSTEM_MEM_VT_SEL_S 22 -/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ -/*description: */ -#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF -#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) -#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF -#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 -/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 -#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 -/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 -#define SYSTEM_MEM_ERR_CNT_CLR_S 4 -/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ -/*description: */ -#define SYSTEM_MEM_PATH_LEN 0x0000000F -#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) -#define SYSTEM_MEM_PATH_LEN_V 0xF -#define SYSTEM_MEM_PATH_LEN_S 0 - -#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103240 ; */ -/*description: */ -#define SYSTEM_DATE 0x0FFFFFFF -#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) -#define SYSTEM_DATE_V 0xFFFFFFF -#define SYSTEM_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SYSTEM_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/system_struct.h b/components/soc/esp32h4/include/rev1/soc/system_struct.h deleted file mode 100644 index a3d2433b50..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/system_struct.h +++ /dev/null @@ -1,1175 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_SYSTEM_STRUCT_H_ -#define _SOC_SYSTEM_STRUCT_H_ - -#include -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct system_dev_s { - union { - struct { - uint32_t reserved0 : 6; /*reserved*/ - uint32_t reg_clk_en_assist_debug : 1; /*reg_clk_en_assist_debug*/ - uint32_t reg_clk_en_dedicated_gpio : 1; /*reg_clk_en_dedicated_gpio*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } cpu_peri_clk_en; - union { - struct { - uint32_t reserved0 : 6; /*reserved*/ - uint32_t reg_rst_en_assist_debug : 1; /*reg_rst_en_assist_debug*/ - uint32_t reg_rst_en_dedicated_gpio : 1; /*reg_rst_en_dedicated_gpio*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } cpu_peri_rst_en; - union { - struct { - uint32_t reg_cpuperiod_sel : 2; /*reg_cpuperiod_sel*/ - uint32_t reg_pll_freq_sel : 1; /*reg_pll_freq_sel*/ - uint32_t reg_cpu_wait_mode_force_on : 1; /*reg_cpu_wait_mode_force_on*/ - uint32_t reg_cpu_waiti_delay_num : 4; /*reg_cpu_waiti_delay_num*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } cpu_per_conf; - union { - struct { - uint32_t reg_lslp_mem_pd_mask : 1; /*reg_lslp_mem_pd_mask*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } mem_pd_mask; - union { - struct { - uint32_t reg_cpu_intr_from_cpu_0 : 1; /*reg_cpu_intr_from_cpu_0*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_0; - union { - struct { - uint32_t reg_cpu_intr_from_cpu_1 : 1; /*reg_cpu_intr_from_cpu_1*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_1; - union { - struct { - uint32_t reg_cpu_intr_from_cpu_2 : 1; /*reg_cpu_intr_from_cpu_2*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_2; - union { - struct { - uint32_t reg_cpu_intr_from_cpu_3 : 1; /*reg_cpu_intr_from_cpu_3*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } cpu_intr_from_cpu_3; - union { - struct { - uint32_t reg_rsa_mem_pd : 1; /*reg_rsa_mem_pd*/ - uint32_t reg_rsa_mem_force_pu : 1; /*reg_rsa_mem_force_pu*/ - uint32_t reg_rsa_mem_force_pd : 1; /*reg_rsa_mem_force_pd*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } rsa_pd_ctrl; - union { - struct { - uint32_t reg_edma_clk_on : 1; /*reg_edma_clk_on*/ - uint32_t reg_edma_reset : 1; /*reg_edma_reset*/ - uint32_t reserved2 : 30; /*reserved*/ - }; - uint32_t val; - } edma_ctrl; - union { - struct { - uint32_t reg_icache_clk_on : 1; /*reg_icache_clk_on*/ - uint32_t reg_icache_reset : 1; /*reg_icache_reset*/ - uint32_t reg_dcache_clk_on : 1; /*reg_dcache_clk_on*/ - uint32_t reg_dcache_reset : 1; /*reg_dcache_reset*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } cache_control; - union { - struct { - uint32_t reg_enable_spi_manual_encrypt : 1; /*reg_enable_spi_manual_encrypt*/ - uint32_t reg_enable_download_db_encrypt: 1; /*reg_enable_download_db_encrypt*/ - uint32_t reg_enable_download_g0cb_decrypt: 1; /*reg_enable_download_g0cb_decrypt*/ - uint32_t reg_enable_download_manual_encrypt: 1; /*reg_enable_download_manual_encrypt*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } external_device_encrypt_decrypt_control; - union { - struct { - uint32_t reserved0 : 8; /*fast memory crc register*/ - uint32_t reg_rtc_mem_crc_start : 1; /*reg_rtc_mem_crc_start*/ - uint32_t reg_rtc_mem_crc_addr : 11; /*reg_rtc_mem_crc_addr*/ - uint32_t reg_rtc_mem_crc_len : 11; /*reg_rtc_mem_crc_len*/ - uint32_t reg_rtc_mem_crc_finish : 1; /*reg_rtc_mem_crc_finish*/ - }; - uint32_t val; - } rtc_fastmem_config; - uint32_t rtc_fastmem_crc; - union { - struct { - uint32_t reg_redundant_eco_drive : 1; /*reg_redundant_eco_drive*/ - uint32_t reg_redundant_eco_result : 1; /*reg_redundant_eco_result*/ - uint32_t reserved2 : 30; /*reserved*/ - }; - uint32_t val; - } redundant_eco_ctrl; - union { - struct { - uint32_t reg_clk_en : 1; /*reg_clk_en*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } clock_gate; - union { - struct { - uint32_t reg_mem_path_len : 4; /*reg_mem_path_len*/ - uint32_t reg_mem_err_cnt_clr : 1; /*reg_mem_err_cnt_clr*/ - uint32_t reg_mem_pvt_monitor_en : 1; /*reg_mem_pvt_monitor_en*/ - uint32_t reg_mem_timing_err_cnt : 16; /*reg_mem_timing_err_cnt*/ - uint32_t reg_mem_vt_sel : 2; /*reg_mem_vt_sel*/ - uint32_t reserved24 : 8; /*reserved*/ - }; - uint32_t val; - } mem_pvt; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t reserved_3fc; - uint32_t reserved_400; - uint32_t reserved_404; - uint32_t reserved_408; - uint32_t reserved_40c; - uint32_t reserved_410; - uint32_t reserved_414; - uint32_t reserved_418; - uint32_t reserved_41c; - uint32_t reserved_420; - uint32_t reserved_424; - uint32_t reserved_428; - uint32_t reserved_42c; - uint32_t reserved_430; - uint32_t reserved_434; - uint32_t reserved_438; - uint32_t reserved_43c; - uint32_t reserved_440; - uint32_t reserved_444; - uint32_t reserved_448; - uint32_t reserved_44c; - uint32_t reserved_450; - uint32_t reserved_454; - uint32_t reserved_458; - uint32_t reserved_45c; - uint32_t reserved_460; - uint32_t reserved_464; - uint32_t reserved_468; - uint32_t reserved_46c; - uint32_t reserved_470; - uint32_t reserved_474; - uint32_t reserved_478; - uint32_t reserved_47c; - uint32_t reserved_480; - uint32_t reserved_484; - uint32_t reserved_488; - uint32_t reserved_48c; - uint32_t reserved_490; - uint32_t reserved_494; - uint32_t reserved_498; - uint32_t reserved_49c; - uint32_t reserved_4a0; - uint32_t reserved_4a4; - uint32_t reserved_4a8; - uint32_t reserved_4ac; - uint32_t reserved_4b0; - uint32_t reserved_4b4; - uint32_t reserved_4b8; - uint32_t reserved_4bc; - uint32_t reserved_4c0; - uint32_t reserved_4c4; - uint32_t reserved_4c8; - uint32_t reserved_4cc; - uint32_t reserved_4d0; - uint32_t reserved_4d4; - uint32_t reserved_4d8; - uint32_t reserved_4dc; - uint32_t reserved_4e0; - uint32_t reserved_4e4; - uint32_t reserved_4e8; - uint32_t reserved_4ec; - uint32_t reserved_4f0; - uint32_t reserved_4f4; - uint32_t reserved_4f8; - uint32_t reserved_4fc; - uint32_t reserved_500; - uint32_t reserved_504; - uint32_t reserved_508; - uint32_t reserved_50c; - uint32_t reserved_510; - uint32_t reserved_514; - uint32_t reserved_518; - uint32_t reserved_51c; - uint32_t reserved_520; - uint32_t reserved_524; - uint32_t reserved_528; - uint32_t reserved_52c; - uint32_t reserved_530; - uint32_t reserved_534; - uint32_t reserved_538; - uint32_t reserved_53c; - uint32_t reserved_540; - uint32_t reserved_544; - uint32_t reserved_548; - uint32_t reserved_54c; - uint32_t reserved_550; - uint32_t reserved_554; - uint32_t reserved_558; - uint32_t reserved_55c; - uint32_t reserved_560; - uint32_t reserved_564; - uint32_t reserved_568; - uint32_t reserved_56c; - uint32_t reserved_570; - uint32_t reserved_574; - uint32_t reserved_578; - uint32_t reserved_57c; - uint32_t reserved_580; - uint32_t reserved_584; - uint32_t reserved_588; - uint32_t reserved_58c; - uint32_t reserved_590; - uint32_t reserved_594; - uint32_t reserved_598; - uint32_t reserved_59c; - uint32_t reserved_5a0; - uint32_t reserved_5a4; - uint32_t reserved_5a8; - uint32_t reserved_5ac; - uint32_t reserved_5b0; - uint32_t reserved_5b4; - uint32_t reserved_5b8; - uint32_t reserved_5bc; - uint32_t reserved_5c0; - uint32_t reserved_5c4; - uint32_t reserved_5c8; - uint32_t reserved_5cc; - uint32_t reserved_5d0; - uint32_t reserved_5d4; - uint32_t reserved_5d8; - uint32_t reserved_5dc; - uint32_t reserved_5e0; - uint32_t reserved_5e4; - uint32_t reserved_5e8; - uint32_t reserved_5ec; - uint32_t reserved_5f0; - uint32_t reserved_5f4; - uint32_t reserved_5f8; - uint32_t reserved_5fc; - uint32_t reserved_600; - uint32_t reserved_604; - uint32_t reserved_608; - uint32_t reserved_60c; - uint32_t reserved_610; - uint32_t reserved_614; - uint32_t reserved_618; - uint32_t reserved_61c; - uint32_t reserved_620; - uint32_t reserved_624; - uint32_t reserved_628; - uint32_t reserved_62c; - uint32_t reserved_630; - uint32_t reserved_634; - uint32_t reserved_638; - uint32_t reserved_63c; - uint32_t reserved_640; - uint32_t reserved_644; - uint32_t reserved_648; - uint32_t reserved_64c; - uint32_t reserved_650; - uint32_t reserved_654; - uint32_t reserved_658; - uint32_t reserved_65c; - uint32_t reserved_660; - uint32_t reserved_664; - uint32_t reserved_668; - uint32_t reserved_66c; - uint32_t reserved_670; - uint32_t reserved_674; - uint32_t reserved_678; - uint32_t reserved_67c; - uint32_t reserved_680; - uint32_t reserved_684; - uint32_t reserved_688; - uint32_t reserved_68c; - uint32_t reserved_690; - uint32_t reserved_694; - uint32_t reserved_698; - uint32_t reserved_69c; - uint32_t reserved_6a0; - uint32_t reserved_6a4; - uint32_t reserved_6a8; - uint32_t reserved_6ac; - uint32_t reserved_6b0; - uint32_t reserved_6b4; - uint32_t reserved_6b8; - uint32_t reserved_6bc; - uint32_t reserved_6c0; - uint32_t reserved_6c4; - uint32_t reserved_6c8; - uint32_t reserved_6cc; - uint32_t reserved_6d0; - uint32_t reserved_6d4; - uint32_t reserved_6d8; - uint32_t reserved_6dc; - uint32_t reserved_6e0; - uint32_t reserved_6e4; - uint32_t reserved_6e8; - uint32_t reserved_6ec; - uint32_t reserved_6f0; - uint32_t reserved_6f4; - uint32_t reserved_6f8; - uint32_t reserved_6fc; - uint32_t reserved_700; - uint32_t reserved_704; - uint32_t reserved_708; - uint32_t reserved_70c; - uint32_t reserved_710; - uint32_t reserved_714; - uint32_t reserved_718; - uint32_t reserved_71c; - uint32_t reserved_720; - uint32_t reserved_724; - uint32_t reserved_728; - uint32_t reserved_72c; - uint32_t reserved_730; - uint32_t reserved_734; - uint32_t reserved_738; - uint32_t reserved_73c; - uint32_t reserved_740; - uint32_t reserved_744; - uint32_t reserved_748; - uint32_t reserved_74c; - uint32_t reserved_750; - uint32_t reserved_754; - uint32_t reserved_758; - uint32_t reserved_75c; - uint32_t reserved_760; - uint32_t reserved_764; - uint32_t reserved_768; - uint32_t reserved_76c; - uint32_t reserved_770; - uint32_t reserved_774; - uint32_t reserved_778; - uint32_t reserved_77c; - uint32_t reserved_780; - uint32_t reserved_784; - uint32_t reserved_788; - uint32_t reserved_78c; - uint32_t reserved_790; - uint32_t reserved_794; - uint32_t reserved_798; - uint32_t reserved_79c; - uint32_t reserved_7a0; - uint32_t reserved_7a4; - uint32_t reserved_7a8; - uint32_t reserved_7ac; - uint32_t reserved_7b0; - uint32_t reserved_7b4; - uint32_t reserved_7b8; - uint32_t reserved_7bc; - uint32_t reserved_7c0; - uint32_t reserved_7c4; - uint32_t reserved_7c8; - uint32_t reserved_7cc; - uint32_t reserved_7d0; - uint32_t reserved_7d4; - uint32_t reserved_7d8; - uint32_t reserved_7dc; - uint32_t reserved_7e0; - uint32_t reserved_7e4; - uint32_t reserved_7e8; - uint32_t reserved_7ec; - uint32_t reserved_7f0; - uint32_t reserved_7f4; - uint32_t reserved_7f8; - uint32_t reserved_7fc; - uint32_t reserved_800; - uint32_t reserved_804; - uint32_t reserved_808; - uint32_t reserved_80c; - uint32_t reserved_810; - uint32_t reserved_814; - uint32_t reserved_818; - uint32_t reserved_81c; - uint32_t reserved_820; - uint32_t reserved_824; - uint32_t reserved_828; - uint32_t reserved_82c; - uint32_t reserved_830; - uint32_t reserved_834; - uint32_t reserved_838; - uint32_t reserved_83c; - uint32_t reserved_840; - uint32_t reserved_844; - uint32_t reserved_848; - uint32_t reserved_84c; - uint32_t reserved_850; - uint32_t reserved_854; - uint32_t reserved_858; - uint32_t reserved_85c; - uint32_t reserved_860; - uint32_t reserved_864; - uint32_t reserved_868; - uint32_t reserved_86c; - uint32_t reserved_870; - uint32_t reserved_874; - uint32_t reserved_878; - uint32_t reserved_87c; - uint32_t reserved_880; - uint32_t reserved_884; - uint32_t reserved_888; - uint32_t reserved_88c; - uint32_t reserved_890; - uint32_t reserved_894; - uint32_t reserved_898; - uint32_t reserved_89c; - uint32_t reserved_8a0; - uint32_t reserved_8a4; - uint32_t reserved_8a8; - uint32_t reserved_8ac; - uint32_t reserved_8b0; - uint32_t reserved_8b4; - uint32_t reserved_8b8; - uint32_t reserved_8bc; - uint32_t reserved_8c0; - uint32_t reserved_8c4; - uint32_t reserved_8c8; - uint32_t reserved_8cc; - uint32_t reserved_8d0; - uint32_t reserved_8d4; - uint32_t reserved_8d8; - uint32_t reserved_8dc; - uint32_t reserved_8e0; - uint32_t reserved_8e4; - uint32_t reserved_8e8; - uint32_t reserved_8ec; - uint32_t reserved_8f0; - uint32_t reserved_8f4; - uint32_t reserved_8f8; - uint32_t reserved_8fc; - uint32_t reserved_900; - uint32_t reserved_904; - uint32_t reserved_908; - uint32_t reserved_90c; - uint32_t reserved_910; - uint32_t reserved_914; - uint32_t reserved_918; - uint32_t reserved_91c; - uint32_t reserved_920; - uint32_t reserved_924; - uint32_t reserved_928; - uint32_t reserved_92c; - uint32_t reserved_930; - uint32_t reserved_934; - uint32_t reserved_938; - uint32_t reserved_93c; - uint32_t reserved_940; - uint32_t reserved_944; - uint32_t reserved_948; - uint32_t reserved_94c; - uint32_t reserved_950; - uint32_t reserved_954; - uint32_t reserved_958; - uint32_t reserved_95c; - uint32_t reserved_960; - uint32_t reserved_964; - uint32_t reserved_968; - uint32_t reserved_96c; - uint32_t reserved_970; - uint32_t reserved_974; - uint32_t reserved_978; - uint32_t reserved_97c; - uint32_t reserved_980; - uint32_t reserved_984; - uint32_t reserved_988; - uint32_t reserved_98c; - uint32_t reserved_990; - uint32_t reserved_994; - uint32_t reserved_998; - uint32_t reserved_99c; - uint32_t reserved_9a0; - uint32_t reserved_9a4; - uint32_t reserved_9a8; - uint32_t reserved_9ac; - uint32_t reserved_9b0; - uint32_t reserved_9b4; - uint32_t reserved_9b8; - uint32_t reserved_9bc; - uint32_t reserved_9c0; - uint32_t reserved_9c4; - uint32_t reserved_9c8; - uint32_t reserved_9cc; - uint32_t reserved_9d0; - uint32_t reserved_9d4; - uint32_t reserved_9d8; - uint32_t reserved_9dc; - uint32_t reserved_9e0; - uint32_t reserved_9e4; - uint32_t reserved_9e8; - uint32_t reserved_9ec; - uint32_t reserved_9f0; - uint32_t reserved_9f4; - uint32_t reserved_9f8; - uint32_t reserved_9fc; - uint32_t reserved_a00; - uint32_t reserved_a04; - uint32_t reserved_a08; - uint32_t reserved_a0c; - uint32_t reserved_a10; - uint32_t reserved_a14; - uint32_t reserved_a18; - uint32_t reserved_a1c; - uint32_t reserved_a20; - uint32_t reserved_a24; - uint32_t reserved_a28; - uint32_t reserved_a2c; - uint32_t reserved_a30; - uint32_t reserved_a34; - uint32_t reserved_a38; - uint32_t reserved_a3c; - uint32_t reserved_a40; - uint32_t reserved_a44; - uint32_t reserved_a48; - uint32_t reserved_a4c; - uint32_t reserved_a50; - uint32_t reserved_a54; - uint32_t reserved_a58; - uint32_t reserved_a5c; - uint32_t reserved_a60; - uint32_t reserved_a64; - uint32_t reserved_a68; - uint32_t reserved_a6c; - uint32_t reserved_a70; - uint32_t reserved_a74; - uint32_t reserved_a78; - uint32_t reserved_a7c; - uint32_t reserved_a80; - uint32_t reserved_a84; - uint32_t reserved_a88; - uint32_t reserved_a8c; - uint32_t reserved_a90; - uint32_t reserved_a94; - uint32_t reserved_a98; - uint32_t reserved_a9c; - uint32_t reserved_aa0; - uint32_t reserved_aa4; - uint32_t reserved_aa8; - uint32_t reserved_aac; - uint32_t reserved_ab0; - uint32_t reserved_ab4; - uint32_t reserved_ab8; - uint32_t reserved_abc; - uint32_t reserved_ac0; - uint32_t reserved_ac4; - uint32_t reserved_ac8; - uint32_t reserved_acc; - uint32_t reserved_ad0; - uint32_t reserved_ad4; - uint32_t reserved_ad8; - uint32_t reserved_adc; - uint32_t reserved_ae0; - uint32_t reserved_ae4; - uint32_t reserved_ae8; - uint32_t reserved_aec; - uint32_t reserved_af0; - uint32_t reserved_af4; - uint32_t reserved_af8; - uint32_t reserved_afc; - uint32_t reserved_b00; - uint32_t reserved_b04; - uint32_t reserved_b08; - uint32_t reserved_b0c; - uint32_t reserved_b10; - uint32_t reserved_b14; - uint32_t reserved_b18; - uint32_t reserved_b1c; - uint32_t reserved_b20; - uint32_t reserved_b24; - uint32_t reserved_b28; - uint32_t reserved_b2c; - uint32_t reserved_b30; - uint32_t reserved_b34; - uint32_t reserved_b38; - uint32_t reserved_b3c; - uint32_t reserved_b40; - uint32_t reserved_b44; - uint32_t reserved_b48; - uint32_t reserved_b4c; - uint32_t reserved_b50; - uint32_t reserved_b54; - uint32_t reserved_b58; - uint32_t reserved_b5c; - uint32_t reserved_b60; - uint32_t reserved_b64; - uint32_t reserved_b68; - uint32_t reserved_b6c; - uint32_t reserved_b70; - uint32_t reserved_b74; - uint32_t reserved_b78; - uint32_t reserved_b7c; - uint32_t reserved_b80; - uint32_t reserved_b84; - uint32_t reserved_b88; - uint32_t reserved_b8c; - uint32_t reserved_b90; - uint32_t reserved_b94; - uint32_t reserved_b98; - uint32_t reserved_b9c; - uint32_t reserved_ba0; - uint32_t reserved_ba4; - uint32_t reserved_ba8; - uint32_t reserved_bac; - uint32_t reserved_bb0; - uint32_t reserved_bb4; - uint32_t reserved_bb8; - uint32_t reserved_bbc; - uint32_t reserved_bc0; - uint32_t reserved_bc4; - uint32_t reserved_bc8; - uint32_t reserved_bcc; - uint32_t reserved_bd0; - uint32_t reserved_bd4; - uint32_t reserved_bd8; - uint32_t reserved_bdc; - uint32_t reserved_be0; - uint32_t reserved_be4; - uint32_t reserved_be8; - uint32_t reserved_bec; - uint32_t reserved_bf0; - uint32_t reserved_bf4; - uint32_t reserved_bf8; - uint32_t reserved_bfc; - uint32_t reserved_c00; - uint32_t reserved_c04; - uint32_t reserved_c08; - uint32_t reserved_c0c; - uint32_t reserved_c10; - uint32_t reserved_c14; - uint32_t reserved_c18; - uint32_t reserved_c1c; - uint32_t reserved_c20; - uint32_t reserved_c24; - uint32_t reserved_c28; - uint32_t reserved_c2c; - uint32_t reserved_c30; - uint32_t reserved_c34; - uint32_t reserved_c38; - uint32_t reserved_c3c; - uint32_t reserved_c40; - uint32_t reserved_c44; - uint32_t reserved_c48; - uint32_t reserved_c4c; - uint32_t reserved_c50; - uint32_t reserved_c54; - uint32_t reserved_c58; - uint32_t reserved_c5c; - uint32_t reserved_c60; - uint32_t reserved_c64; - uint32_t reserved_c68; - uint32_t reserved_c6c; - uint32_t reserved_c70; - uint32_t reserved_c74; - uint32_t reserved_c78; - uint32_t reserved_c7c; - uint32_t reserved_c80; - uint32_t reserved_c84; - uint32_t reserved_c88; - uint32_t reserved_c8c; - uint32_t reserved_c90; - uint32_t reserved_c94; - uint32_t reserved_c98; - uint32_t reserved_c9c; - uint32_t reserved_ca0; - uint32_t reserved_ca4; - uint32_t reserved_ca8; - uint32_t reserved_cac; - uint32_t reserved_cb0; - uint32_t reserved_cb4; - uint32_t reserved_cb8; - uint32_t reserved_cbc; - uint32_t reserved_cc0; - uint32_t reserved_cc4; - uint32_t reserved_cc8; - uint32_t reserved_ccc; - uint32_t reserved_cd0; - uint32_t reserved_cd4; - uint32_t reserved_cd8; - uint32_t reserved_cdc; - uint32_t reserved_ce0; - uint32_t reserved_ce4; - uint32_t reserved_ce8; - uint32_t reserved_cec; - uint32_t reserved_cf0; - uint32_t reserved_cf4; - uint32_t reserved_cf8; - uint32_t reserved_cfc; - uint32_t reserved_d00; - uint32_t reserved_d04; - uint32_t reserved_d08; - uint32_t reserved_d0c; - uint32_t reserved_d10; - uint32_t reserved_d14; - uint32_t reserved_d18; - uint32_t reserved_d1c; - uint32_t reserved_d20; - uint32_t reserved_d24; - uint32_t reserved_d28; - uint32_t reserved_d2c; - uint32_t reserved_d30; - uint32_t reserved_d34; - uint32_t reserved_d38; - uint32_t reserved_d3c; - uint32_t reserved_d40; - uint32_t reserved_d44; - uint32_t reserved_d48; - uint32_t reserved_d4c; - uint32_t reserved_d50; - uint32_t reserved_d54; - uint32_t reserved_d58; - uint32_t reserved_d5c; - uint32_t reserved_d60; - uint32_t reserved_d64; - uint32_t reserved_d68; - uint32_t reserved_d6c; - uint32_t reserved_d70; - uint32_t reserved_d74; - uint32_t reserved_d78; - uint32_t reserved_d7c; - uint32_t reserved_d80; - uint32_t reserved_d84; - uint32_t reserved_d88; - uint32_t reserved_d8c; - uint32_t reserved_d90; - uint32_t reserved_d94; - uint32_t reserved_d98; - uint32_t reserved_d9c; - uint32_t reserved_da0; - uint32_t reserved_da4; - uint32_t reserved_da8; - uint32_t reserved_dac; - uint32_t reserved_db0; - uint32_t reserved_db4; - uint32_t reserved_db8; - uint32_t reserved_dbc; - uint32_t reserved_dc0; - uint32_t reserved_dc4; - uint32_t reserved_dc8; - uint32_t reserved_dcc; - uint32_t reserved_dd0; - uint32_t reserved_dd4; - uint32_t reserved_dd8; - uint32_t reserved_ddc; - uint32_t reserved_de0; - uint32_t reserved_de4; - uint32_t reserved_de8; - uint32_t reserved_dec; - uint32_t reserved_df0; - uint32_t reserved_df4; - uint32_t reserved_df8; - uint32_t reserved_dfc; - uint32_t reserved_e00; - uint32_t reserved_e04; - uint32_t reserved_e08; - uint32_t reserved_e0c; - uint32_t reserved_e10; - uint32_t reserved_e14; - uint32_t reserved_e18; - uint32_t reserved_e1c; - uint32_t reserved_e20; - uint32_t reserved_e24; - uint32_t reserved_e28; - uint32_t reserved_e2c; - uint32_t reserved_e30; - uint32_t reserved_e34; - uint32_t reserved_e38; - uint32_t reserved_e3c; - uint32_t reserved_e40; - uint32_t reserved_e44; - uint32_t reserved_e48; - uint32_t reserved_e4c; - uint32_t reserved_e50; - uint32_t reserved_e54; - uint32_t reserved_e58; - uint32_t reserved_e5c; - uint32_t reserved_e60; - uint32_t reserved_e64; - uint32_t reserved_e68; - uint32_t reserved_e6c; - uint32_t reserved_e70; - uint32_t reserved_e74; - uint32_t reserved_e78; - uint32_t reserved_e7c; - uint32_t reserved_e80; - uint32_t reserved_e84; - uint32_t reserved_e88; - uint32_t reserved_e8c; - uint32_t reserved_e90; - uint32_t reserved_e94; - uint32_t reserved_e98; - uint32_t reserved_e9c; - uint32_t reserved_ea0; - uint32_t reserved_ea4; - uint32_t reserved_ea8; - uint32_t reserved_eac; - uint32_t reserved_eb0; - uint32_t reserved_eb4; - uint32_t reserved_eb8; - uint32_t reserved_ebc; - uint32_t reserved_ec0; - uint32_t reserved_ec4; - uint32_t reserved_ec8; - uint32_t reserved_ecc; - uint32_t reserved_ed0; - uint32_t reserved_ed4; - uint32_t reserved_ed8; - uint32_t reserved_edc; - uint32_t reserved_ee0; - uint32_t reserved_ee4; - uint32_t reserved_ee8; - uint32_t reserved_eec; - uint32_t reserved_ef0; - uint32_t reserved_ef4; - uint32_t reserved_ef8; - uint32_t reserved_efc; - uint32_t reserved_f00; - uint32_t reserved_f04; - uint32_t reserved_f08; - uint32_t reserved_f0c; - uint32_t reserved_f10; - uint32_t reserved_f14; - uint32_t reserved_f18; - uint32_t reserved_f1c; - uint32_t reserved_f20; - uint32_t reserved_f24; - uint32_t reserved_f28; - uint32_t reserved_f2c; - uint32_t reserved_f30; - uint32_t reserved_f34; - uint32_t reserved_f38; - uint32_t reserved_f3c; - uint32_t reserved_f40; - uint32_t reserved_f44; - uint32_t reserved_f48; - uint32_t reserved_f4c; - uint32_t reserved_f50; - uint32_t reserved_f54; - uint32_t reserved_f58; - uint32_t reserved_f5c; - uint32_t reserved_f60; - uint32_t reserved_f64; - uint32_t reserved_f68; - uint32_t reserved_f6c; - uint32_t reserved_f70; - uint32_t reserved_f74; - uint32_t reserved_f78; - uint32_t reserved_f7c; - uint32_t reserved_f80; - uint32_t reserved_f84; - uint32_t reserved_f88; - uint32_t reserved_f8c; - uint32_t reserved_f90; - uint32_t reserved_f94; - uint32_t reserved_f98; - uint32_t reserved_f9c; - uint32_t reserved_fa0; - uint32_t reserved_fa4; - uint32_t reserved_fa8; - uint32_t reserved_fac; - uint32_t reserved_fb0; - uint32_t reserved_fb4; - uint32_t reserved_fb8; - uint32_t reserved_fbc; - uint32_t reserved_fc0; - uint32_t reserved_fc4; - uint32_t reserved_fc8; - uint32_t reserved_fcc; - uint32_t reserved_fd0; - uint32_t reserved_fd4; - uint32_t reserved_fd8; - uint32_t reserved_fdc; - uint32_t reserved_fe0; - uint32_t reserved_fe4; - uint32_t reserved_fe8; - uint32_t reserved_fec; - uint32_t reserved_ff0; - uint32_t reserved_ff4; - uint32_t reserved_ff8; - union { - struct { - uint32_t reg_system_reg_date : 28; /*reg_system_reg_date*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; -} system_dev_t; -extern system_dev_t SYSTEM; -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SYSTEM_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/rev1/soc/usb_serial_jtag_reg.h b/components/soc/esp32h4/include/rev1/soc/usb_serial_jtag_reg.h deleted file mode 100644 index d4f7ad7c12..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/usb_serial_jtag_reg.h +++ /dev/null @@ -1,994 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -#include -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -/** Configuration Registers */ - -/** USB_SERIAL_JTAG_EP1_REG register - * USB_SERIAL_JTAG_EP1_REG. - */ -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) -/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0; - * Write and read byte data to/from UART Tx/Rx FIFO through this field. - * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write - * data (up to 64 bytes) into UART Tx FIFO. When - * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check - * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to - * know how many data is received, then read that amount of data from UART - * Rx - * FIFO. - */ -#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF -#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) -#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FF -#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 - -/** USB_SERIAL_JTAG_CONF0_REG register - * USB_SERIAL_JTAG_CONF0_REG. - */ -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) -/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external - * PHY - */ -#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) -#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001 -#define USB_SERIAL_JTAG_PHY_SEL_S 0 -/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; - * Enable software control USB D+ D- - * exchange - */ -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001 -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 -/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; - * USB D+ D- - * exchange - */ -#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) -#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) -#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001 -#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 -/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0; - * Control single-end input high threshold. 1.76V to 2V, step - * 80mV - */ -#define USB_SERIAL_JTAG_VREFL 0x00000003 -#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) -#define USB_SERIAL_JTAG_VREFL_V 0x00000003 -#define USB_SERIAL_JTAG_VREFL_S 3 -/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0; - * Control single-end input low threshold. 0.8V to 1.04V, step - * 80mV - */ -#define USB_SERIAL_JTAG_VREFH 0x00000003 -#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) -#define USB_SERIAL_JTAG_VREFH_V 0x00000003 -#define USB_SERIAL_JTAG_VREFH_S 5 -/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; - * Enable software control input - * threshold - */ -#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) -#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) -#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001 -#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 -/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; - * Enable software control USB D+ D- pullup - * pulldown - */ -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001 -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 -/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; - * Control USB D+ pull - * up. - */ -#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) -#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) -#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001 -#define USB_SERIAL_JTAG_DP_PULLUP_S 9 -/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; - * Control USB D+ pull - * down. - */ -#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) -#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) -#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001 -#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 -/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; - * Control USB D- pull - * up. - */ -#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) -#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) -#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001 -#define USB_SERIAL_JTAG_DM_PULLUP_S 11 -/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; - * Control USB D- pull - * down. - */ -#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) -#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) -#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001 -#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 -/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; - * Control pull up - * value. - */ -#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) -#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) -#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001 -#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 -/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; - * Enable USB pad - * function. - */ -#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001 -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 - -/** USB_SERIAL_JTAG_TEST_REG register - * USB_SERIAL_JTAG_TEST_REG. - */ -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) -/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; - * Enable test of the USB - * pad - */ -#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) -#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) -#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001 -#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 -/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; - * USB pad oen in - * test - */ -#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) -#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) -#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001 -#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 -/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; - * USB D+ tx value in - * test - */ -#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) -#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) -#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001 -#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 -/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; - * USB D- tx value in - * test - */ -#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) -#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) -#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001 -#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 - -/** USB_SERIAL_JTAG_MISC_CONF_REG register - * USB_SERIAL_JTAG_MISC_CONF_REG. - */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) -/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when - * application writes - * registers. - */ -#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) -#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) -#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001 -#define USB_SERIAL_JTAG_CLK_EN_S 0 - -/** USB_SERIAL_JTAG_MEM_CONF_REG register - * USB_SERIAL_JTAG_MEM_CONF_REG. - */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) -/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; - * 1: power down usb - * memory. - */ -#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) -#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) -#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001 -#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 -/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; - * 1: Force clock on for usb - * memory. - */ -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001 -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 - - -/** Status Registers */ - -/** USB_SERIAL_JTAG_EP1_CONF_REG register - * USB_SERIAL_JTAG_EP1_CONF_REG. - */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) -/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; - * Set this bit to indicate writing byte data to UART Tx FIFO is done. - * This bit then stays 0 until data in UART Tx FIFO is read by the USB - * Host. - */ -#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) -#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) -#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001 -#define USB_SERIAL_JTAG_WR_DONE_S 0 -/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; - * 1'b1: Indicate UART Tx FIFO is not full and data can be written into - * in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the - * data is sent to the USB - * Host. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 -/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; - * 1'b1: Indicate there is data in UART Rx - * FIFO. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 - -/** USB_SERIAL_JTAG_JFIFO_ST_REG register - * USB_SERIAL_JTAG_JFIFO_ST_REG. - */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) -/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0; - * JTAG in fifo - * counter. - */ -#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003 -#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) -#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003 -#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 -/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; - * 1: JTAG in fifo is - * empty. - */ -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001 -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 -/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; - * 1: JTAG in fifo is - * full. - */ -#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) -#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) -#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001 -#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 -/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0; - * JTAT out fifo - * counter. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003 -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003 -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 -/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; - * 1: JTAG out fifo is - * empty. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 -/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; - * 1: JTAG out fifo is - * full. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 -/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; - * Write 1 to reset JTAG in - * fifo. - */ -#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) -#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) -#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001 -#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 -/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; - * Write 1 to reset JTAG out - * fifo. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 - -/** USB_SERIAL_JTAG_FRAM_NUM_REG register - * USB_SERIAL_JTAG_FRAM_NUM_REG. - */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) -/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0; - * Frame index of received SOF - * frame. - */ -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FF -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 - -/** USB_SERIAL_JTAG_IN_EP0_ST_REG register - * USB_SERIAL_JTAG_IN_EP0_ST_REG. - */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) -/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1; - * State of IN Endpoint - * 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003 -#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) -#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 -/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of IN endpoint - * 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of IN endpoint - * 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP1_ST_REG register - * USB_SERIAL_JTAG_IN_EP1_ST_REG. - */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) -/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1; - * State of IN Endpoint - * 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003 -#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) -#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 -/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of IN endpoint - * 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of IN endpoint - * 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP2_ST_REG register - * USB_SERIAL_JTAG_IN_EP2_ST_REG. - */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) -/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1; - * State of IN Endpoint - * 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003 -#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) -#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 -/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of IN endpoint - * 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of IN endpoint - * 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP3_ST_REG register - * USB_SERIAL_JTAG_IN_EP3_ST_REG. - */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) -/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1; - * State of IN Endpoint - * 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003 -#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) -#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 -/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of IN endpoint - * 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of IN endpoint - * 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register - * USB_SERIAL_JTAG_OUT_EP0_ST_REG. - */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) -/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0; - * State of OUT Endpoint - * 0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003 -#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 -/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of OUT endpoint 0. When - * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are - * USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT - * EP0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of OUT endpoint - * 0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register - * USB_SERIAL_JTAG_OUT_EP1_ST_REG. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) -/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0; - * State of OUT Endpoint - * 1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003 -#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 -/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of OUT endpoint 1. When - * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are - * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT - * EP1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of OUT endpoint - * 1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 -/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0; - * Data count in OUT endpoint 1 when one packet is - * received. - */ -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 - -/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register - * USB_SERIAL_JTAG_OUT_EP2_ST_REG. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) -/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0; - * State of OUT Endpoint - * 2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003 -#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003 -#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 -/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0; - * Write data address of OUT endpoint 2. When - * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are - * USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT - * EP2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 -/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0; - * Read data address of OUT endpoint - * 2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007F -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 - - -/** Interrupt Registers */ - -/** USB_SERIAL_JTAG_INT_RAW_REG register - * USB_SERIAL_JTAG_INT_RAW_REG. - */ -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) -/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when a flush command is - * received for IN endpoint 2 of - * JTAG. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when a SOF frame is - * received. - */ -#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) -#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 -/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the Serial Port OUT - * Endpoint received one - * packet. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; - * The raw interrupt bit turns to high level when the Serial Port IN - * Endpoint is - * empty. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 -/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when a PID error is - * detected. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 -/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when a CRC5 error is - * detected. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 -/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when a CRC16 error is - * detected. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 -/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when a bit stuffing error is - * detected. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 -/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when an IN token for IN - * endpoint 1 is - * received. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when a USB bus reset is - * detected. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 -/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 1 received - * packet with zero - * payload. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 2 received - * packet with zero - * payload. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 - -/** USB_SERIAL_JTAG_INT_ST_REG register - * USB_SERIAL_JTAG_INT_ST_REG. - */ -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) -/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) -#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 -/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the - * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the - * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 -/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 -/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 -/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 -/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 -/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the - * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 -/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the - * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the - * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 - -/** USB_SERIAL_JTAG_INT_ENA_REG register - * USB_SERIAL_JTAG_INT_ENA_REG. - */ -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) -/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) -#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 -/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the - * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 -/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 -/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 -/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 -/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 -/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the - * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 -/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the - * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the - * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 - -/** USB_SERIAL_JTAG_INT_CLR_REG register - * USB_SERIAL_JTAG_INT_CLR_REG. - */ -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) -/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) -#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 -/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 -/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 -/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 -/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 -/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 -/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 -/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001 -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 - - -/** Version Registers */ - -/** USB_SERIAL_JTAG_DATE_REG register - * USB_SERIAL_JTAG_DATE_REG. - */ -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) -/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872; - * register - * version. - */ -#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF -#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) -#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF -#define USB_SERIAL_JTAG_DATE_S 0 - - - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev1/soc/usb_serial_jtag_struct.h b/components/soc/esp32h4/include/rev1/soc/usb_serial_jtag_struct.h deleted file mode 100644 index 01771c8373..0000000000 --- a/components/soc/esp32h4/include/rev1/soc/usb_serial_jtag_struct.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_ -#define _SOC_USB_SERIAL_JTAG_STRUCT_H_ - -#include -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct usb_serial_jtag_dev_s { - union { - struct { - uint32_t rdwr_byte : 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } ep1; - union { - struct { - uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done. This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/ - uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/ - uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } ep1_conf; - union { - struct { - uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/ - uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when a SOF frame is received.*/ - uint32_t serial_out_recv_pkt_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/ - uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/ - uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when a PID error is detected.*/ - uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/ - uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/ - uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/ - uint32_t in_token_rec_in_ep1_int_raw : 1; /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/ - uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/ - uint32_t out_ep1_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/ - uint32_t out_ep2_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/ - uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/ - uint32_t serial_out_recv_pkt_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/ - uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/ - uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/ - uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/ - uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/ - uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/ - uint32_t in_token_rec_in_ep1_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ - uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/ - uint32_t out_ep1_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t out_ep2_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/ - uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/ - uint32_t serial_out_recv_pkt_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/ - uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/ - uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/ - uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/ - uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/ - uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/ - uint32_t in_token_rec_in_ep1_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/ - uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/ - uint32_t out_ep1_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t out_ep2_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/ - uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/ - uint32_t serial_out_recv_pkt_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/ - uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/ - uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/ - uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/ - uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/ - uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/ - uint32_t in_token_rec_in_ep1_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/ - uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/ - uint32_t out_ep1_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t out_ep2_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t phy_sel : 1; /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/ - uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/ - uint32_t exchg_pins : 1; /*USB D+ D- exchange*/ - uint32_t vrefh : 2; /*Control single-end input high threshold. 1.76V to 2V, step 80mV */ - uint32_t vrefl : 2; /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/ - uint32_t vref_override : 1; /*Enable software control input threshold*/ - uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/ - uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/ - uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/ - uint32_t dm_pullup : 1; /*Control USB D- pull up.*/ - uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/ - uint32_t pullup_value : 1; /*Control pull up value.*/ - uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/ - uint32_t reserved15 : 17; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t test_enable : 1; /*Enable test of the USB pad*/ - uint32_t test_usb_oe : 1; /*USB pad oen in test*/ - uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/ - uint32_t test_tx_dm : 1; /*USB D- tx value in test*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } test; - union { - struct { - uint32_t in_fifo_cnt : 2; /*JTAG in fifo counter.*/ - uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/ - uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/ - uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/ - uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/ - uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/ - uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/ - uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/ - uint32_t reserved10 : 22; - }; - uint32_t val; - } jfifo_st; - union { - struct { - uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/ - uint32_t reserved11 : 21; - }; - uint32_t val; - } fram_num; - union { - struct { - uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/ - uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/ - uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } in_ep0_st; - union { - struct { - uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/ - uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/ - uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } in_ep1_st; - union { - struct { - uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/ - uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/ - uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } in_ep2_st; - union { - struct { - uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/ - uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/ - uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } in_ep3_st; - union { - struct { - uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/ - uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ - uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } out_ep0_st; - union { - struct { - uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/ - uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/ - uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/ - uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/ - uint32_t reserved23 : 9; /*reserved*/ - }; - uint32_t val; - } out_ep1_st; - union { - struct { - uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/ - uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/ - uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } out_ep2_st; - union { - struct { - uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } misc_conf; - union { - struct { - uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/ - uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/ - uint32_t reserved2 : 30; - }; - uint32_t val; - } mem_conf; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t date; -} usb_serial_jtag_dev_t; -extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/rev2/soc/assist_debug_reg.h b/components/soc/esp32h4/include/rev2/soc/assist_debug_reg.h deleted file mode 100644 index 10b8e335cb..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/assist_debug_reg.h +++ /dev/null @@ -1,896 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 - -/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 -/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) -/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) -/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) -/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) -#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 - -/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) -/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) -#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 - -/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) -/** ASSIST_DEBUG_CORE_0_SP_MIN : RW; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) -#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 - -/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) -/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) -#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 - -/** ASSIST_DEBUG_CORE_0_SP_PC_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) -/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) -#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 - -/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) -/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW; bitpos: [0]; default: 0; - * enable recording function, if enable, assist_debug will update PdebugPC, so you can - * read it - */ -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW; bitpos: [1]; default: 0; - * enable CPU Pdebug function, if enable, CPU will update PdebugPC - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 - -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 - -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) -/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 - -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 - -/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 -/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24)) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24 -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25 - -/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) -/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 - -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 - -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) -/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU -#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 - -/** ASSIST_DEBUG_LOG_SETTING_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) -/** ASSIST_DEBUG_LOG_ENA : R/W; bitpos: [2:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_ENA 0x00000007U -#define ASSIST_DEBUG_LOG_ENA_M (ASSIST_DEBUG_LOG_ENA_V << ASSIST_DEBUG_LOG_ENA_S) -#define ASSIST_DEBUG_LOG_ENA_V 0x00000007U -#define ASSIST_DEBUG_LOG_ENA_S 0 -/** ASSIST_DEBUG_LOG_MODE : R/W; bitpos: [6:3]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MODE 0x0000000FU -#define ASSIST_DEBUG_LOG_MODE_M (ASSIST_DEBUG_LOG_MODE_V << ASSIST_DEBUG_LOG_MODE_S) -#define ASSIST_DEBUG_LOG_MODE_V 0x0000000FU -#define ASSIST_DEBUG_LOG_MODE_S 3 -/** ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7)) -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V << ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S) -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x00000001U -#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7 - -/** ASSIST_DEBUG_LOG_DATA_0_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) -/** ASSIST_DEBUG_LOG_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_DATA_0_M (ASSIST_DEBUG_LOG_DATA_0_V << ASSIST_DEBUG_LOG_DATA_0_S) -#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_DATA_0_S 0 - -/** ASSIST_DEBUG_LOG_DATA_MASK_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78) -/** ASSIST_DEBUG_LOG_DATA_SIZE : R/W; bitpos: [15:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFFU -#define ASSIST_DEBUG_LOG_DATA_SIZE_M (ASSIST_DEBUG_LOG_DATA_SIZE_V << ASSIST_DEBUG_LOG_DATA_SIZE_S) -#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0x0000FFFFU -#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0 - -/** ASSIST_DEBUG_LOG_MIN_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c) -/** ASSIST_DEBUG_LOG_MIN : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MIN_M (ASSIST_DEBUG_LOG_MIN_V << ASSIST_DEBUG_LOG_MIN_S) -#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MIN_S 0 - -/** ASSIST_DEBUG_LOG_MAX_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80) -/** ASSIST_DEBUG_LOG_MAX : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MAX_M (ASSIST_DEBUG_LOG_MAX_V << ASSIST_DEBUG_LOG_MAX_S) -#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MAX_S 0 - -/** ASSIST_DEBUG_LOG_MEM_START_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84) -/** ASSIST_DEBUG_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MEM_START_M (ASSIST_DEBUG_LOG_MEM_START_V << ASSIST_DEBUG_LOG_MEM_START_S) -#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MEM_START_S 0 - -/** ASSIST_DEBUG_LOG_MEM_END_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88) -/** ASSIST_DEBUG_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MEM_END_M (ASSIST_DEBUG_LOG_MEM_END_V << ASSIST_DEBUG_LOG_MEM_END_S) -#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MEM_END_S 0 - -/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c) -/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M (ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V << ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S) -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFFU -#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0 - -/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG register - * register description - */ -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90) -/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0)) -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S) -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x00000001U -#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0 -/** ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1)) -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S) -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U -#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1 - -/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94) -/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU -#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 - -/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register - * register description - */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98) -/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 -/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; - * Need add description - */ -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U -#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 - -/** ASSIST_DEBUG_DATE_REG register - * register description - */ -#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc) -/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 33587216; - * Need add description - */ -#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU -#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S) -#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU -#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/clkrst_reg.h b/components/soc/esp32h4/include/rev2/soc/clkrst_reg.h deleted file mode 100644 index 66da37e850..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/clkrst_reg.h +++ /dev/null @@ -1,1295 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SYSTEM_SYSCLK_CONF_REG register - * register description - */ -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0) -/** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [7:0]; default: 0; - * Need add description - */ -#define SYSTEM_CLK_XTAL_FREQ 0x000000FFU -#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) -#define SYSTEM_CLK_XTAL_FREQ_V 0x000000FFU -#define SYSTEM_CLK_XTAL_FREQ_S 0 -/** SYSTEM_SPLL_FREQ : RO; bitpos: [15:8]; default: 0; - * Need add description - */ -#define SYSTEM_SPLL_FREQ 0x000000FFU -#define SYSTEM_SPLL_FREQ_M (SYSTEM_SPLL_FREQ_V << SYSTEM_SPLL_FREQ_S) -#define SYSTEM_SPLL_FREQ_V 0x000000FFU -#define SYSTEM_SPLL_FREQ_S 8 -/** SYSTEM_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SYSTEM_SOC_CLK_SEL 0x00000003U -#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) -#define SYSTEM_SOC_CLK_SEL_V 0x00000003U -#define SYSTEM_SOC_CLK_SEL_S 16 - -/** SYSTEM_CPUCLK_CONF_REG register - * register description - */ -#define SYSTEM_CPUCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x4) -/** SYSTEM_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_DIV_NUM 0x000000FFU -#define SYSTEM_CPU_DIV_NUM_M (SYSTEM_CPU_DIV_NUM_V << SYSTEM_CPU_DIV_NUM_S) -#define SYSTEM_CPU_DIV_NUM_V 0x000000FFU -#define SYSTEM_CPU_DIV_NUM_S 0 - -#define SYSTEM_PRE_DIV_CNT SYSTEM_CPU_DIV_NUM -#define SYSTEM_PRE_DIV_CNT_M SYSTEM_CPU_DIV_NUM_M -#define SYSTEM_PRE_DIV_CNT_V SYSTEM_CPU_DIV_NUM_V -#define SYSTEM_PRE_DIV_CNT_S SYSTEM_CPU_DIV_NUM_S - -/** SYSTEM_CPU_DIV_NUMERATOR : R/W; bitpos: [13:8]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_DIV_NUMERATOR 0x0000003FU -#define SYSTEM_CPU_DIV_NUMERATOR_M (SYSTEM_CPU_DIV_NUMERATOR_V << SYSTEM_CPU_DIV_NUMERATOR_S) -#define SYSTEM_CPU_DIV_NUMERATOR_V 0x0000003FU -#define SYSTEM_CPU_DIV_NUMERATOR_S 8 -/** SYSTEM_CPU_DIV_DENOMINATOR : R/W; bitpos: [21:16]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_DIV_DENOMINATOR 0x0000003FU -#define SYSTEM_CPU_DIV_DENOMINATOR_M (SYSTEM_CPU_DIV_DENOMINATOR_V << SYSTEM_CPU_DIV_DENOMINATOR_S) -#define SYSTEM_CPU_DIV_DENOMINATOR_V 0x0000003FU -#define SYSTEM_CPU_DIV_DENOMINATOR_S 16 - -/** SYSTEM_BUSCLK_CONF_REG register - * register description - */ -#define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x8) -/** SYSTEM_APB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Need add description - */ -#define SYSTEM_APB_DIV_NUM 0x000000FFU -#define SYSTEM_APB_DIV_NUM_M (SYSTEM_APB_DIV_NUM_V << SYSTEM_APB_DIV_NUM_S) -#define SYSTEM_APB_DIV_NUM_V 0x000000FFU -#define SYSTEM_APB_DIV_NUM_S 0 -/** SYSTEM_AHB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Need add description - */ -#define SYSTEM_AHB_DIV_NUM 0x000000FFU -#define SYSTEM_AHB_DIV_NUM_M (SYSTEM_AHB_DIV_NUM_V << SYSTEM_AHB_DIV_NUM_S) -#define SYSTEM_AHB_DIV_NUM_V 0x000000FFU -#define SYSTEM_AHB_DIV_NUM_S 8 - -/** SYSTEM_MODCLK_CONF_REG register - * register description - */ -#define SYSTEM_MODCLK_CONF_REG (DR_REG_CLKRST_BASE + 0xc) -/** SYSTEM_MODEM_CLK_SEL : R/W; bitpos: [1:0]; default: 1; - * Need add description - */ -#define SYSTEM_MODEM_CLK_SEL 0x00000003U -#define SYSTEM_MODEM_CLK_SEL_M (SYSTEM_MODEM_CLK_SEL_V << SYSTEM_MODEM_CLK_SEL_S) -#define SYSTEM_MODEM_CLK_SEL_V 0x00000003U -#define SYSTEM_MODEM_CLK_SEL_S 0 -/** SYSTEM_ETM_CLK_SEL : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_ETM_CLK_SEL (BIT(2)) -#define SYSTEM_ETM_CLK_SEL_M (SYSTEM_ETM_CLK_SEL_V << SYSTEM_ETM_CLK_SEL_S) -#define SYSTEM_ETM_CLK_SEL_V 0x00000001U -#define SYSTEM_ETM_CLK_SEL_S 2 -/** SYSTEM_ETM_CLK_ACTIVE : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_ETM_CLK_ACTIVE (BIT(3)) -#define SYSTEM_ETM_CLK_ACTIVE_M (SYSTEM_ETM_CLK_ACTIVE_V << SYSTEM_ETM_CLK_ACTIVE_S) -#define SYSTEM_ETM_CLK_ACTIVE_V 0x00000001U -#define SYSTEM_ETM_CLK_ACTIVE_S 3 -/** SYSTEM_COEX_LPCLK_SEL : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ -#define SYSTEM_COEX_LPCLK_SEL 0x00000003U -#define SYSTEM_COEX_LPCLK_SEL_M (SYSTEM_COEX_LPCLK_SEL_V << SYSTEM_COEX_LPCLK_SEL_S) -#define SYSTEM_COEX_LPCLK_SEL_V 0x00000003U -#define SYSTEM_COEX_LPCLK_SEL_S 4 -/** SYSTEM_COEX_LPCLK_DIV : R/W; bitpos: [15:6]; default: 999; - * Need add description - */ -#define SYSTEM_COEX_LPCLK_DIV 0x000003FFU -#define SYSTEM_COEX_LPCLK_DIV_M (SYSTEM_COEX_LPCLK_DIV_V << SYSTEM_COEX_LPCLK_DIV_S) -#define SYSTEM_COEX_LPCLK_DIV_V 0x000003FFU -#define SYSTEM_COEX_LPCLK_DIV_S 6 -/** SYSTEM_BT_DFM_CLK_INV_PHASE : R/W; bitpos: [17:16]; default: 0; - * Need add description - */ -#define SYSTEM_BT_DFM_CLK_INV_PHASE 0x00000003U -#define SYSTEM_BT_DFM_CLK_INV_PHASE_M (SYSTEM_BT_DFM_CLK_INV_PHASE_V << SYSTEM_BT_DFM_CLK_INV_PHASE_S) -#define SYSTEM_BT_DFM_CLK_INV_PHASE_V 0x00000003U -#define SYSTEM_BT_DFM_CLK_INV_PHASE_S 16 - -/** SYSTEM_CLK_OUT_EN_REG register - * register description - */ -#define SYSTEM_CLK_OUT_EN_REG (DR_REG_CLKRST_BASE + 0x10) -/** SYSTEM_CLK_8M_BT_OEN : R/W; bitpos: [3]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_8M_BT_OEN (BIT(3)) -#define SYSTEM_CLK_8M_BT_OEN_M (SYSTEM_CLK_8M_BT_OEN_V << SYSTEM_CLK_8M_BT_OEN_S) -#define SYSTEM_CLK_8M_BT_OEN_V 0x00000001U -#define SYSTEM_CLK_8M_BT_OEN_S 3 -/** SYSTEM_CLK_16M_BT_OEN : R/W; bitpos: [4]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_16M_BT_OEN (BIT(4)) -#define SYSTEM_CLK_16M_BT_OEN_M (SYSTEM_CLK_16M_BT_OEN_V << SYSTEM_CLK_16M_BT_OEN_S) -#define SYSTEM_CLK_16M_BT_OEN_V 0x00000001U -#define SYSTEM_CLK_16M_BT_OEN_S 4 -/** SYSTEM_CLK_32M_BT_OEN : R/W; bitpos: [5]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_32M_BT_OEN (BIT(5)) -#define SYSTEM_CLK_32M_BT_OEN_M (SYSTEM_CLK_32M_BT_OEN_V << SYSTEM_CLK_32M_BT_OEN_S) -#define SYSTEM_CLK_32M_BT_OEN_V 0x00000001U -#define SYSTEM_CLK_32M_BT_OEN_S 5 -/** SYSTEM_CLK_APB_OEN : R/W; bitpos: [6]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_APB_OEN (BIT(6)) -#define SYSTEM_CLK_APB_OEN_M (SYSTEM_CLK_APB_OEN_V << SYSTEM_CLK_APB_OEN_S) -#define SYSTEM_CLK_APB_OEN_V 0x00000001U -#define SYSTEM_CLK_APB_OEN_S 6 -/** SYSTEM_CLK_AHB_OEN : R/W; bitpos: [7]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_AHB_OEN (BIT(7)) -#define SYSTEM_CLK_AHB_OEN_M (SYSTEM_CLK_AHB_OEN_V << SYSTEM_CLK_AHB_OEN_S) -#define SYSTEM_CLK_AHB_OEN_V 0x00000001U -#define SYSTEM_CLK_AHB_OEN_S 7 -/** SYSTEM_CLK_CPU_OEN : R/W; bitpos: [8]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_CPU_OEN (BIT(8)) -#define SYSTEM_CLK_CPU_OEN_M (SYSTEM_CLK_CPU_OEN_V << SYSTEM_CLK_CPU_OEN_S) -#define SYSTEM_CLK_CPU_OEN_V 0x00000001U -#define SYSTEM_CLK_CPU_OEN_S 8 -/** SYSTEM_CLK_SPLL_OEN : R/W; bitpos: [9]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_SPLL_OEN (BIT(9)) -#define SYSTEM_CLK_SPLL_OEN_M (SYSTEM_CLK_SPLL_OEN_V << SYSTEM_CLK_SPLL_OEN_S) -#define SYSTEM_CLK_SPLL_OEN_V 0x00000001U -#define SYSTEM_CLK_SPLL_OEN_S 9 -/** SYSTEM_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_XTAL_OEN (BIT(10)) -#define SYSTEM_CLK_XTAL_OEN_M (SYSTEM_CLK_XTAL_OEN_V << SYSTEM_CLK_XTAL_OEN_S) -#define SYSTEM_CLK_XTAL_OEN_V 0x00000001U -#define SYSTEM_CLK_XTAL_OEN_S 10 -/** SYSTEM_CLK_RFDAC_OEN : R/W; bitpos: [11]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_RFDAC_OEN (BIT(11)) -#define SYSTEM_CLK_RFDAC_OEN_M (SYSTEM_CLK_RFDAC_OEN_V << SYSTEM_CLK_RFDAC_OEN_S) -#define SYSTEM_CLK_RFDAC_OEN_V 0x00000001U -#define SYSTEM_CLK_RFDAC_OEN_S 11 -/** SYSTEM_CLK_RFADC_OEN : R/W; bitpos: [12]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_RFADC_OEN (BIT(12)) -#define SYSTEM_CLK_RFADC_OEN_M (SYSTEM_CLK_RFADC_OEN_V << SYSTEM_CLK_RFADC_OEN_S) -#define SYSTEM_CLK_RFADC_OEN_V 0x00000001U -#define SYSTEM_CLK_RFADC_OEN_S 12 - -/** SYSTEM_MODEM_CLK_EN_REG register - * register description - */ -#define SYSTEM_MODEM_CLK_EN_REG (DR_REG_CLKRST_BASE + 0x14) -/** SYSTEM_FE_CAL_CLK_EN : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_FE_CAL_CLK_EN (BIT(0)) -#define SYSTEM_FE_CAL_CLK_EN_M (SYSTEM_FE_CAL_CLK_EN_V << SYSTEM_FE_CAL_CLK_EN_S) -#define SYSTEM_FE_CAL_CLK_EN_V 0x00000001U -#define SYSTEM_FE_CAL_CLK_EN_S 0 -/** SYSTEM_FE_CLK_EN : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_FE_CLK_EN (BIT(1)) -#define SYSTEM_FE_CLK_EN_M (SYSTEM_FE_CLK_EN_V << SYSTEM_FE_CLK_EN_S) -#define SYSTEM_FE_CLK_EN_V 0x00000001U -#define SYSTEM_FE_CLK_EN_S 1 -/** SYSTEM_MAC_CLK_EN : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_MAC_CLK_EN (BIT(2)) -#define SYSTEM_MAC_CLK_EN_M (SYSTEM_MAC_CLK_EN_V << SYSTEM_MAC_CLK_EN_S) -#define SYSTEM_MAC_CLK_EN_V 0x00000001U -#define SYSTEM_MAC_CLK_EN_S 2 -/** SYSTEM_BT_CLK_EN : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_BT_CLK_EN (BIT(3)) -#define SYSTEM_BT_CLK_EN_M (SYSTEM_BT_CLK_EN_V << SYSTEM_BT_CLK_EN_S) -#define SYSTEM_BT_CLK_EN_V 0x00000001U -#define SYSTEM_BT_CLK_EN_S 3 -/** SYSTEM_BTMAC_CLK_EN : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define SYSTEM_BTMAC_CLK_EN (BIT(4)) -#define SYSTEM_BTMAC_CLK_EN_M (SYSTEM_BTMAC_CLK_EN_V << SYSTEM_BTMAC_CLK_EN_S) -#define SYSTEM_BTMAC_CLK_EN_V 0x00000001U -#define SYSTEM_BTMAC_CLK_EN_S 4 -/** SYSTEM_SDIO_CLK_EN : R/W; bitpos: [5]; default: 1; - * Need add description - */ -#define SYSTEM_SDIO_CLK_EN (BIT(5)) -#define SYSTEM_SDIO_CLK_EN_M (SYSTEM_SDIO_CLK_EN_V << SYSTEM_SDIO_CLK_EN_S) -#define SYSTEM_SDIO_CLK_EN_V 0x00000001U -#define SYSTEM_SDIO_CLK_EN_S 5 -/** SYSTEM_EMAC_CLK_EN : R/W; bitpos: [6]; default: 1; - * Need add description - */ -#define SYSTEM_EMAC_CLK_EN (BIT(6)) -#define SYSTEM_EMAC_CLK_EN_M (SYSTEM_EMAC_CLK_EN_V << SYSTEM_EMAC_CLK_EN_S) -#define SYSTEM_EMAC_CLK_EN_V 0x00000001U -#define SYSTEM_EMAC_CLK_EN_S 6 -/** SYSTEM_MACPWR_CLK_EN : R/W; bitpos: [7]; default: 1; - * Need add description - */ -#define SYSTEM_MACPWR_CLK_EN (BIT(7)) -#define SYSTEM_MACPWR_CLK_EN_M (SYSTEM_MACPWR_CLK_EN_V << SYSTEM_MACPWR_CLK_EN_S) -#define SYSTEM_MACPWR_CLK_EN_V 0x00000001U -#define SYSTEM_MACPWR_CLK_EN_S 7 -/** SYSTEM_RW_BTMAC_CLK_EN : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define SYSTEM_RW_BTMAC_CLK_EN (BIT(8)) -#define SYSTEM_RW_BTMAC_CLK_EN_M (SYSTEM_RW_BTMAC_CLK_EN_V << SYSTEM_RW_BTMAC_CLK_EN_S) -#define SYSTEM_RW_BTMAC_CLK_EN_V 0x00000001U -#define SYSTEM_RW_BTMAC_CLK_EN_S 8 -/** SYSTEM_I2C_CLK_EN : R/W; bitpos: [9]; default: 1; - * Need add description - */ -#define SYSTEM_I2C_CLK_EN (BIT(9)) -#define SYSTEM_I2C_CLK_EN_M (SYSTEM_I2C_CLK_EN_V << SYSTEM_I2C_CLK_EN_S) -#define SYSTEM_I2C_CLK_EN_V 0x00000001U -#define SYSTEM_I2C_CLK_EN_S 9 -/** SYSTEM_I2CMST_CLK_EN : R/W; bitpos: [10]; default: 1; - * Need add description - */ -#define SYSTEM_I2CMST_CLK_EN (BIT(10)) -#define SYSTEM_I2CMST_CLK_EN_M (SYSTEM_I2CMST_CLK_EN_V << SYSTEM_I2CMST_CLK_EN_S) -#define SYSTEM_I2CMST_CLK_EN_V 0x00000001U -#define SYSTEM_I2CMST_CLK_EN_S 10 -/** SYSTEM_COEX_CLK_EN : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define SYSTEM_COEX_CLK_EN (BIT(11)) -#define SYSTEM_COEX_CLK_EN_M (SYSTEM_COEX_CLK_EN_V << SYSTEM_COEX_CLK_EN_S) -#define SYSTEM_COEX_CLK_EN_V 0x00000001U -#define SYSTEM_COEX_CLK_EN_S 11 -/** SYSTEM_IEEE802154BB_CLK_EN : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define SYSTEM_IEEE802154BB_CLK_EN (BIT(12)) -#define SYSTEM_IEEE802154BB_CLK_EN_M (SYSTEM_IEEE802154BB_CLK_EN_V << SYSTEM_IEEE802154BB_CLK_EN_S) -#define SYSTEM_IEEE802154BB_CLK_EN_V 0x00000001U -#define SYSTEM_IEEE802154BB_CLK_EN_S 12 -/** SYSTEM_IEEE802154MAC_CLK_EN : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define SYSTEM_IEEE802154MAC_CLK_EN (BIT(13)) -#define SYSTEM_IEEE802154MAC_CLK_EN_M (SYSTEM_IEEE802154MAC_CLK_EN_V << SYSTEM_IEEE802154MAC_CLK_EN_S) -#define SYSTEM_IEEE802154MAC_CLK_EN_V 0x00000001U -#define SYSTEM_IEEE802154MAC_CLK_EN_S 13 -/** SYSTEM_BLE_SEC_ECB_CLK_EN : R/W; bitpos: [14]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_ECB_CLK_EN (BIT(14)) -#define SYSTEM_BLE_SEC_ECB_CLK_EN_M (SYSTEM_BLE_SEC_ECB_CLK_EN_V << SYSTEM_BLE_SEC_ECB_CLK_EN_S) -#define SYSTEM_BLE_SEC_ECB_CLK_EN_V 0x00000001U -#define SYSTEM_BLE_SEC_ECB_CLK_EN_S 14 -/** SYSTEM_BLE_SEC_CCM_CLK_EN : R/W; bitpos: [15]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_CCM_CLK_EN (BIT(15)) -#define SYSTEM_BLE_SEC_CCM_CLK_EN_M (SYSTEM_BLE_SEC_CCM_CLK_EN_V << SYSTEM_BLE_SEC_CCM_CLK_EN_S) -#define SYSTEM_BLE_SEC_CCM_CLK_EN_V 0x00000001U -#define SYSTEM_BLE_SEC_CCM_CLK_EN_S 15 -/** SYSTEM_BLE_SEC_BAH_CLK_EN : R/W; bitpos: [16]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_BAH_CLK_EN (BIT(16)) -#define SYSTEM_BLE_SEC_BAH_CLK_EN_M (SYSTEM_BLE_SEC_BAH_CLK_EN_V << SYSTEM_BLE_SEC_BAH_CLK_EN_S) -#define SYSTEM_BLE_SEC_BAH_CLK_EN_V 0x00000001U -#define SYSTEM_BLE_SEC_BAH_CLK_EN_S 16 -/** SYSTEM_BLE_SEC_CLK_EN : R/W; bitpos: [17]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_CLK_EN (BIT(17)) -#define SYSTEM_BLE_SEC_CLK_EN_M (SYSTEM_BLE_SEC_CLK_EN_V << SYSTEM_BLE_SEC_CLK_EN_S) -#define SYSTEM_BLE_SEC_CLK_EN_V 0x00000001U -#define SYSTEM_BLE_SEC_CLK_EN_S 17 -/** SYSTEM_BTLC_CLK_EN : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define SYSTEM_BTLC_CLK_EN (BIT(18)) -#define SYSTEM_BTLC_CLK_EN_M (SYSTEM_BTLC_CLK_EN_V << SYSTEM_BTLC_CLK_EN_S) -#define SYSTEM_BTLC_CLK_EN_V 0x00000001U -#define SYSTEM_BTLC_CLK_EN_S 18 -/** SYSTEM_RFDAC_CLK_EN : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define SYSTEM_RFDAC_CLK_EN (BIT(19)) -#define SYSTEM_RFDAC_CLK_EN_M (SYSTEM_RFDAC_CLK_EN_V << SYSTEM_RFDAC_CLK_EN_S) -#define SYSTEM_RFDAC_CLK_EN_V 0x00000001U -#define SYSTEM_RFDAC_CLK_EN_S 19 -/** SYSTEM_RFADC_CLK_EN : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define SYSTEM_RFADC_CLK_EN (BIT(20)) -#define SYSTEM_RFADC_CLK_EN_M (SYSTEM_RFADC_CLK_EN_V << SYSTEM_RFADC_CLK_EN_S) -#define SYSTEM_RFADC_CLK_EN_V 0x00000001U -#define SYSTEM_RFADC_CLK_EN_S 20 -/** SYSTEM_DATA_DUMP_CLK_EN : R/W; bitpos: [21]; default: 0; - * Need add description - */ -#define SYSTEM_DATA_DUMP_CLK_EN (BIT(21)) -#define SYSTEM_DATA_DUMP_CLK_EN_M (SYSTEM_DATA_DUMP_CLK_EN_V << SYSTEM_DATA_DUMP_CLK_EN_S) -#define SYSTEM_DATA_DUMP_CLK_EN_V 0x00000001U -#define SYSTEM_DATA_DUMP_CLK_EN_S 21 -/** SYSTEM_BT_DFM_CLK_EN : R/W; bitpos: [22]; default: 0; - * Need add description - */ -#define SYSTEM_BT_DFM_CLK_EN (BIT(22)) -#define SYSTEM_BT_DFM_CLK_EN_M (SYSTEM_BT_DFM_CLK_EN_V << SYSTEM_BT_DFM_CLK_EN_S) -#define SYSTEM_BT_DFM_CLK_EN_V 0x00000001U -#define SYSTEM_BT_DFM_CLK_EN_S 22 - -/** SYSTEM_MODEM_RST_EN_REG register - * register description - */ -#define SYSTEM_MODEM_RST_EN_REG (DR_REG_CLKRST_BASE + 0x18) -/** SYSTEM_FE_RST : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_FE_RST (BIT(0)) -#define SYSTEM_FE_RST_M (SYSTEM_FE_RST_V << SYSTEM_FE_RST_S) -#define SYSTEM_FE_RST_V 0x00000001U -#define SYSTEM_FE_RST_S 0 -/** SYSTEM_MAC_RST : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_MAC_RST (BIT(1)) -#define SYSTEM_MAC_RST_M (SYSTEM_MAC_RST_V << SYSTEM_MAC_RST_S) -#define SYSTEM_MAC_RST_V 0x00000001U -#define SYSTEM_MAC_RST_S 1 -/** SYSTEM_BT_RST : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_BT_RST (BIT(2)) -#define SYSTEM_BT_RST_M (SYSTEM_BT_RST_V << SYSTEM_BT_RST_S) -#define SYSTEM_BT_RST_V 0x00000001U -#define SYSTEM_BT_RST_S 2 -/** SYSTEM_BTMAC_RST : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_BTMAC_RST (BIT(3)) -#define SYSTEM_BTMAC_RST_M (SYSTEM_BTMAC_RST_V << SYSTEM_BTMAC_RST_S) -#define SYSTEM_BTMAC_RST_V 0x00000001U -#define SYSTEM_BTMAC_RST_S 3 -/** SYSTEM_SDIO_RST : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define SYSTEM_SDIO_RST (BIT(4)) -#define SYSTEM_SDIO_RST_M (SYSTEM_SDIO_RST_V << SYSTEM_SDIO_RST_S) -#define SYSTEM_SDIO_RST_V 0x00000001U -#define SYSTEM_SDIO_RST_S 4 -/** SYSTEM_EMAC_RST : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define SYSTEM_EMAC_RST (BIT(5)) -#define SYSTEM_EMAC_RST_M (SYSTEM_EMAC_RST_V << SYSTEM_EMAC_RST_S) -#define SYSTEM_EMAC_RST_V 0x00000001U -#define SYSTEM_EMAC_RST_S 5 -/** SYSTEM_MACPWR_RST : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define SYSTEM_MACPWR_RST (BIT(6)) -#define SYSTEM_MACPWR_RST_M (SYSTEM_MACPWR_RST_V << SYSTEM_MACPWR_RST_S) -#define SYSTEM_MACPWR_RST_V 0x00000001U -#define SYSTEM_MACPWR_RST_S 6 -/** SYSTEM_RW_BTMAC_RST : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define SYSTEM_RW_BTMAC_RST (BIT(7)) -#define SYSTEM_RW_BTMAC_RST_M (SYSTEM_RW_BTMAC_RST_V << SYSTEM_RW_BTMAC_RST_S) -#define SYSTEM_RW_BTMAC_RST_V 0x00000001U -#define SYSTEM_RW_BTMAC_RST_S 7 -/** SYSTEM_RW_BTLP_RST : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define SYSTEM_RW_BTLP_RST (BIT(8)) -#define SYSTEM_RW_BTLP_RST_M (SYSTEM_RW_BTLP_RST_V << SYSTEM_RW_BTLP_RST_S) -#define SYSTEM_RW_BTLP_RST_V 0x00000001U -#define SYSTEM_RW_BTLP_RST_S 8 -/** SYSTEM_RW_BTREG_RST : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define SYSTEM_RW_BTREG_RST (BIT(9)) -#define SYSTEM_RW_BTREG_RST_M (SYSTEM_RW_BTREG_RST_V << SYSTEM_RW_BTREG_RST_S) -#define SYSTEM_RW_BTREG_RST_V 0x00000001U -#define SYSTEM_RW_BTREG_RST_S 9 -/** SYSTEM_RW_BTLPREG_RST : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define SYSTEM_RW_BTLPREG_RST (BIT(10)) -#define SYSTEM_RW_BTLPREG_RST_M (SYSTEM_RW_BTLPREG_RST_V << SYSTEM_RW_BTLPREG_RST_S) -#define SYSTEM_RW_BTLPREG_RST_V 0x00000001U -#define SYSTEM_RW_BTLPREG_RST_S 10 -/** SYSTEM_BT_REG_RST : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define SYSTEM_BT_REG_RST (BIT(11)) -#define SYSTEM_BT_REG_RST_M (SYSTEM_BT_REG_RST_V << SYSTEM_BT_REG_RST_S) -#define SYSTEM_BT_REG_RST_V 0x00000001U -#define SYSTEM_BT_REG_RST_S 11 -/** SYSTEM_COEX_RST : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define SYSTEM_COEX_RST (BIT(12)) -#define SYSTEM_COEX_RST_M (SYSTEM_COEX_RST_V << SYSTEM_COEX_RST_S) -#define SYSTEM_COEX_RST_V 0x00000001U -#define SYSTEM_COEX_RST_S 12 -/** SYSTEM_IEEE802154BB_RST : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define SYSTEM_IEEE802154BB_RST (BIT(13)) -#define SYSTEM_IEEE802154BB_RST_M (SYSTEM_IEEE802154BB_RST_V << SYSTEM_IEEE802154BB_RST_S) -#define SYSTEM_IEEE802154BB_RST_V 0x00000001U -#define SYSTEM_IEEE802154BB_RST_S 13 -/** SYSTEM_IEEE802154MAC_RST : R/W; bitpos: [14]; default: 0; - * Need add description - */ -#define SYSTEM_IEEE802154MAC_RST (BIT(14)) -#define SYSTEM_IEEE802154MAC_RST_M (SYSTEM_IEEE802154MAC_RST_V << SYSTEM_IEEE802154MAC_RST_S) -#define SYSTEM_IEEE802154MAC_RST_V 0x00000001U -#define SYSTEM_IEEE802154MAC_RST_S 14 -/** SYSTEM_BLE_SEC_ECB_RST : R/W; bitpos: [15]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_ECB_RST (BIT(15)) -#define SYSTEM_BLE_SEC_ECB_RST_M (SYSTEM_BLE_SEC_ECB_RST_V << SYSTEM_BLE_SEC_ECB_RST_S) -#define SYSTEM_BLE_SEC_ECB_RST_V 0x00000001U -#define SYSTEM_BLE_SEC_ECB_RST_S 15 -/** SYSTEM_BLE_SEC_CCM_RST : R/W; bitpos: [16]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_CCM_RST (BIT(16)) -#define SYSTEM_BLE_SEC_CCM_RST_M (SYSTEM_BLE_SEC_CCM_RST_V << SYSTEM_BLE_SEC_CCM_RST_S) -#define SYSTEM_BLE_SEC_CCM_RST_V 0x00000001U -#define SYSTEM_BLE_SEC_CCM_RST_S 16 -/** SYSTEM_BLE_SEC_BAH_RST : R/W; bitpos: [17]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_BAH_RST (BIT(17)) -#define SYSTEM_BLE_SEC_BAH_RST_M (SYSTEM_BLE_SEC_BAH_RST_V << SYSTEM_BLE_SEC_BAH_RST_S) -#define SYSTEM_BLE_SEC_BAH_RST_V 0x00000001U -#define SYSTEM_BLE_SEC_BAH_RST_S 17 -/** SYSTEM_BLE_SEC_RST : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define SYSTEM_BLE_SEC_RST (BIT(18)) -#define SYSTEM_BLE_SEC_RST_M (SYSTEM_BLE_SEC_RST_V << SYSTEM_BLE_SEC_RST_S) -#define SYSTEM_BLE_SEC_RST_V 0x00000001U -#define SYSTEM_BLE_SEC_RST_S 18 -/** SYSTEM_APB_RET_RST : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define SYSTEM_APB_RET_RST (BIT(19)) -#define SYSTEM_APB_RET_RST_M (SYSTEM_APB_RET_RST_V << SYSTEM_APB_RET_RST_S) -#define SYSTEM_APB_RET_RST_V 0x00000001U -#define SYSTEM_APB_RET_RST_S 19 -/** SYSTEM_DATA_DUMP_RST : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define SYSTEM_DATA_DUMP_RST (BIT(20)) -#define SYSTEM_DATA_DUMP_RST_M (SYSTEM_DATA_DUMP_RST_V << SYSTEM_DATA_DUMP_RST_S) -#define SYSTEM_DATA_DUMP_RST_V 0x00000001U -#define SYSTEM_DATA_DUMP_RST_S 20 - -/** SYSTEM_PERIP_CLK_CONF_REG register - * register description - */ -#define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_CLKRST_BASE + 0x1c) -/** SYSTEM_SEC_DIV_NUM : R/W; bitpos: [7:0]; default: 1; - * Need add description - */ -#define SYSTEM_SEC_DIV_NUM 0x000000FFU -#define SYSTEM_SEC_DIV_NUM_M (SYSTEM_SEC_DIV_NUM_V << SYSTEM_SEC_DIV_NUM_S) -#define SYSTEM_SEC_DIV_NUM_V 0x000000FFU -#define SYSTEM_SEC_DIV_NUM_S 0 -/** SYSTEM_USB_DEVICE_DIV_NUM : R/W; bitpos: [15:8]; default: 1; - * Need add description - */ -#define SYSTEM_USB_DEVICE_DIV_NUM 0x000000FFU -#define SYSTEM_USB_DEVICE_DIV_NUM_M (SYSTEM_USB_DEVICE_DIV_NUM_V << SYSTEM_USB_DEVICE_DIV_NUM_S) -#define SYSTEM_USB_DEVICE_DIV_NUM_V 0x000000FFU -#define SYSTEM_USB_DEVICE_DIV_NUM_S 8 -/** SYSTEM_TWAI_DIV_NUM : R/W; bitpos: [23:16]; default: 1; - * Need add description - */ -#define SYSTEM_TWAI_DIV_NUM 0x000000FFU -#define SYSTEM_TWAI_DIV_NUM_M (SYSTEM_TWAI_DIV_NUM_V << SYSTEM_TWAI_DIV_NUM_S) -#define SYSTEM_TWAI_DIV_NUM_V 0x000000FFU -#define SYSTEM_TWAI_DIV_NUM_S 16 -/** SYSTEM_MSPI_DIV_NUM : R/W; bitpos: [31:24]; default: 1; - * Need add description - */ -#define SYSTEM_MSPI_DIV_NUM 0x000000FFU -#define SYSTEM_MSPI_DIV_NUM_M (SYSTEM_MSPI_DIV_NUM_V << SYSTEM_MSPI_DIV_NUM_S) -#define SYSTEM_MSPI_DIV_NUM_V 0x000000FFU -#define SYSTEM_MSPI_DIV_NUM_S 24 - -/** SYSTEM_PERIP_CLK_EN0_REG register - * register description - */ -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_CLKRST_BASE + 0x20) -/** SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_TIMERS_CLK_EN (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_M (SYSTEM_TIMERS_CLK_EN_V << SYSTEM_TIMERS_CLK_EN_S) -#define SYSTEM_TIMERS_CLK_EN_V 0x00000001U -#define SYSTEM_TIMERS_CLK_EN_S 0 -/** SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SYSTEM_SPI01_CLK_EN (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_M (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S) -#define SYSTEM_SPI01_CLK_EN_V 0x00000001U -#define SYSTEM_SPI01_CLK_EN_S 1 -/** SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1; - * Need add description - */ -#define SYSTEM_UART_CLK_EN (BIT(2)) -#define SYSTEM_UART_CLK_EN_M (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S) -#define SYSTEM_UART_CLK_EN_V 0x00000001U -#define SYSTEM_UART_CLK_EN_S 2 -/** SYSTEM_WDG_CLK_EN : R/W; bitpos: [3]; default: 1; - * Need add description - */ -#define SYSTEM_WDG_CLK_EN (BIT(3)) -#define SYSTEM_WDG_CLK_EN_M (SYSTEM_WDG_CLK_EN_V << SYSTEM_WDG_CLK_EN_S) -#define SYSTEM_WDG_CLK_EN_V 0x00000001U -#define SYSTEM_WDG_CLK_EN_S 3 -/** SYSTEM_I2S0_CLK_EN : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define SYSTEM_I2S0_CLK_EN (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_M (SYSTEM_I2S0_CLK_EN_V << SYSTEM_I2S0_CLK_EN_S) -#define SYSTEM_I2S0_CLK_EN_V 0x00000001U -#define SYSTEM_I2S0_CLK_EN_S 4 -/** SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1; - * Need add description - */ -#define SYSTEM_UART1_CLK_EN (BIT(5)) -#define SYSTEM_UART1_CLK_EN_M (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S) -#define SYSTEM_UART1_CLK_EN_V 0x00000001U -#define SYSTEM_UART1_CLK_EN_S 5 -/** SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1; - * Need add description - */ -#define SYSTEM_SPI2_CLK_EN (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_M (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S) -#define SYSTEM_SPI2_CLK_EN_V 0x00000001U -#define SYSTEM_SPI2_CLK_EN_S 6 -/** SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_M (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S) -#define SYSTEM_I2C_EXT0_CLK_EN_V 0x00000001U -#define SYSTEM_I2C_EXT0_CLK_EN_S 7 -/** SYSTEM_UHCI0_CLK_EN : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define SYSTEM_UHCI0_CLK_EN (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_M (SYSTEM_UHCI0_CLK_EN_V << SYSTEM_UHCI0_CLK_EN_S) -#define SYSTEM_UHCI0_CLK_EN_V 0x00000001U -#define SYSTEM_UHCI0_CLK_EN_S 8 -/** SYSTEM_RMT_CLK_EN : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define SYSTEM_RMT_CLK_EN (BIT(9)) -#define SYSTEM_RMT_CLK_EN_M (SYSTEM_RMT_CLK_EN_V << SYSTEM_RMT_CLK_EN_S) -#define SYSTEM_RMT_CLK_EN_V 0x00000001U -#define SYSTEM_RMT_CLK_EN_S 9 -/** SYSTEM_PCNT_CLK_EN : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define SYSTEM_PCNT_CLK_EN (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_M (SYSTEM_PCNT_CLK_EN_V << SYSTEM_PCNT_CLK_EN_S) -#define SYSTEM_PCNT_CLK_EN_V 0x00000001U -#define SYSTEM_PCNT_CLK_EN_S 10 -/** SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define SYSTEM_LEDC_CLK_EN (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_M (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S) -#define SYSTEM_LEDC_CLK_EN_V 0x00000001U -#define SYSTEM_LEDC_CLK_EN_S 11 -/** SYSTEM_UHCI1_CLK_EN : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define SYSTEM_UHCI1_CLK_EN (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_M (SYSTEM_UHCI1_CLK_EN_V << SYSTEM_UHCI1_CLK_EN_S) -#define SYSTEM_UHCI1_CLK_EN_V 0x00000001U -#define SYSTEM_UHCI1_CLK_EN_S 12 -/** SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1; - * Need add description - */ -#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_M (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S) -#define SYSTEM_TIMERGROUP_CLK_EN_V 0x00000001U -#define SYSTEM_TIMERGROUP_CLK_EN_S 13 -/** SYSTEM_EFUSE_CLK_EN : R/W; bitpos: [14]; default: 1; - * Need add description - */ -#define SYSTEM_EFUSE_CLK_EN (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_M (SYSTEM_EFUSE_CLK_EN_V << SYSTEM_EFUSE_CLK_EN_S) -#define SYSTEM_EFUSE_CLK_EN_V 0x00000001U -#define SYSTEM_EFUSE_CLK_EN_S 14 -/** SYSTEM_TIMERGROUP1_CLK_EN : R/W; bitpos: [15]; default: 1; - * Need add description - */ -#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_M (SYSTEM_TIMERGROUP1_CLK_EN_V << SYSTEM_TIMERGROUP1_CLK_EN_S) -#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x00000001U -#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 -/** SYSTEM_SPI3_CLK_EN : R/W; bitpos: [16]; default: 1; - * Need add description - */ -#define SYSTEM_SPI3_CLK_EN (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_M (SYSTEM_SPI3_CLK_EN_V << SYSTEM_SPI3_CLK_EN_S) -#define SYSTEM_SPI3_CLK_EN_V 0x00000001U -#define SYSTEM_SPI3_CLK_EN_S 16 -/** SYSTEM_PWM0_CLK_EN : R/W; bitpos: [17]; default: 0; - * Need add description - */ -#define SYSTEM_PWM0_CLK_EN (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_M (SYSTEM_PWM0_CLK_EN_V << SYSTEM_PWM0_CLK_EN_S) -#define SYSTEM_PWM0_CLK_EN_V 0x00000001U -#define SYSTEM_PWM0_CLK_EN_S 17 -/** SYSTEM_I2C_EXT1_CLK_EN : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_M (SYSTEM_I2C_EXT1_CLK_EN_V << SYSTEM_I2C_EXT1_CLK_EN_S) -#define SYSTEM_I2C_EXT1_CLK_EN_V 0x00000001U -#define SYSTEM_I2C_EXT1_CLK_EN_S 18 -/** SYSTEM_TWAI_CLK_EN : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define SYSTEM_TWAI_CLK_EN (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_M (SYSTEM_TWAI_CLK_EN_V << SYSTEM_TWAI_CLK_EN_S) -#define SYSTEM_TWAI_CLK_EN_V 0x00000001U -#define SYSTEM_TWAI_CLK_EN_S 19 -/** SYSTEM_PWM1_CLK_EN : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define SYSTEM_PWM1_CLK_EN (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_M (SYSTEM_PWM1_CLK_EN_V << SYSTEM_PWM1_CLK_EN_S) -#define SYSTEM_PWM1_CLK_EN_V 0x00000001U -#define SYSTEM_PWM1_CLK_EN_S 20 -/** SYSTEM_I2S1_CLK_EN : R/W; bitpos: [21]; default: 0; - * Need add description - */ -#define SYSTEM_I2S1_CLK_EN (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_M (SYSTEM_I2S1_CLK_EN_V << SYSTEM_I2S1_CLK_EN_S) -#define SYSTEM_I2S1_CLK_EN_V 0x00000001U -#define SYSTEM_I2S1_CLK_EN_S 21 -/** SYSTEM_SPI2_DMA_CLK_EN : R/W; bitpos: [22]; default: 1; - * Need add description - */ -#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_M (SYSTEM_SPI2_DMA_CLK_EN_V << SYSTEM_SPI2_DMA_CLK_EN_S) -#define SYSTEM_SPI2_DMA_CLK_EN_V 0x00000001U -#define SYSTEM_SPI2_DMA_CLK_EN_S 22 -/** SYSTEM_USB_DEVICE_CLK_EN : R/W; bitpos: [23]; default: 1; - * Need add description - */ -#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) -#define SYSTEM_USB_DEVICE_CLK_EN_M (SYSTEM_USB_DEVICE_CLK_EN_V << SYSTEM_USB_DEVICE_CLK_EN_S) -#define SYSTEM_USB_DEVICE_CLK_EN_V 0x00000001U -#define SYSTEM_USB_DEVICE_CLK_EN_S 23 -/** SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1; - * Need add description - */ -#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_M (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S) -#define SYSTEM_UART_MEM_CLK_EN_V 0x00000001U -#define SYSTEM_UART_MEM_CLK_EN_S 24 -/** SYSTEM_PWM2_CLK_EN : R/W; bitpos: [25]; default: 0; - * Need add description - */ -#define SYSTEM_PWM2_CLK_EN (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_M (SYSTEM_PWM2_CLK_EN_V << SYSTEM_PWM2_CLK_EN_S) -#define SYSTEM_PWM2_CLK_EN_V 0x00000001U -#define SYSTEM_PWM2_CLK_EN_S 25 -/** SYSTEM_PWM3_CLK_EN : R/W; bitpos: [26]; default: 0; - * Need add description - */ -#define SYSTEM_PWM3_CLK_EN (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_M (SYSTEM_PWM3_CLK_EN_V << SYSTEM_PWM3_CLK_EN_S) -#define SYSTEM_PWM3_CLK_EN_V 0x00000001U -#define SYSTEM_PWM3_CLK_EN_S 26 -/** SYSTEM_SPI3_DMA_CLK_EN : R/W; bitpos: [27]; default: 1; - * Need add description - */ -#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_M (SYSTEM_SPI3_DMA_CLK_EN_V << SYSTEM_SPI3_DMA_CLK_EN_S) -#define SYSTEM_SPI3_DMA_CLK_EN_V 0x00000001U -#define SYSTEM_SPI3_DMA_CLK_EN_S 27 -/** SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1; - * Need add description - */ -#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_M (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S) -#define SYSTEM_APB_SARADC_CLK_EN_V 0x00000001U -#define SYSTEM_APB_SARADC_CLK_EN_S 28 -/** SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1; - * Need add description - */ -#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_M (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S) -#define SYSTEM_SYSTIMER_CLK_EN_V 0x00000001U -#define SYSTEM_SYSTIMER_CLK_EN_S 29 -/** SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; - * Need add description - */ -#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_M (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S) -#define SYSTEM_ADC2_ARB_CLK_EN_V 0x00000001U -#define SYSTEM_ADC2_ARB_CLK_EN_S 30 -/** SYSTEM_SPI4_CLK_EN : R/W; bitpos: [31]; default: 1; - * Need add description - */ -#define SYSTEM_SPI4_CLK_EN (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_M (SYSTEM_SPI4_CLK_EN_V << SYSTEM_SPI4_CLK_EN_S) -#define SYSTEM_SPI4_CLK_EN_V 0x00000001U -#define SYSTEM_SPI4_CLK_EN_S 31 - -/** SYSTEM_PERIP_CLK_EN1_REG register - * register description - */ -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_CLKRST_BASE + 0x24) -/** SYSTEM_RETENTION_TOP_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_RETENTION_TOP_CLK_EN (BIT(0)) -#define SYSTEM_RETENTION_TOP_CLK_EN_M (SYSTEM_RETENTION_TOP_CLK_EN_V << SYSTEM_RETENTION_TOP_CLK_EN_S) -#define SYSTEM_RETENTION_TOP_CLK_EN_V 0x00000001U -#define SYSTEM_RETENTION_TOP_CLK_EN_S 0 -/** SYSTEM_CRYPTO_AES_CLK_EN : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_M (SYSTEM_CRYPTO_AES_CLK_EN_V << SYSTEM_CRYPTO_AES_CLK_EN_S) -#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x00000001U -#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 -/** SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_M (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S) -#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x00000001U -#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 -/** SYSTEM_CRYPTO_RSA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_M (SYSTEM_CRYPTO_RSA_CLK_EN_V << SYSTEM_CRYPTO_RSA_CLK_EN_S) -#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x00000001U -#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 -/** SYSTEM_CRYPTO_DS_CLK_EN : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_M (SYSTEM_CRYPTO_DS_CLK_EN_V << SYSTEM_CRYPTO_DS_CLK_EN_S) -#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x00000001U -#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 -/** SYSTEM_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (SYSTEM_CRYPTO_HMAC_CLK_EN_V << SYSTEM_CRYPTO_HMAC_CLK_EN_S) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x00000001U -#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 -/** SYSTEM_CRYPTO_ECC_CLK_EN : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(6)) -#define SYSTEM_CRYPTO_ECC_CLK_EN_M (SYSTEM_CRYPTO_ECC_CLK_EN_V << SYSTEM_CRYPTO_ECC_CLK_EN_S) -#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x00000001U -#define SYSTEM_CRYPTO_ECC_CLK_EN_S 6 -/** SYSTEM_DMA_CLK_EN : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define SYSTEM_DMA_CLK_EN (BIT(7)) -#define SYSTEM_DMA_CLK_EN_M (SYSTEM_DMA_CLK_EN_V << SYSTEM_DMA_CLK_EN_S) -#define SYSTEM_DMA_CLK_EN_V 0x00000001U -#define SYSTEM_DMA_CLK_EN_S 7 -/** SYSTEM_SDIO_HOST_CLK_EN : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define SYSTEM_SDIO_HOST_CLK_EN (BIT(8)) -#define SYSTEM_SDIO_HOST_CLK_EN_M (SYSTEM_SDIO_HOST_CLK_EN_V << SYSTEM_SDIO_HOST_CLK_EN_S) -#define SYSTEM_SDIO_HOST_CLK_EN_V 0x00000001U -#define SYSTEM_SDIO_HOST_CLK_EN_S 8 -/** SYSTEM_LCD_CAM_CLK_EN : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define SYSTEM_LCD_CAM_CLK_EN (BIT(9)) -#define SYSTEM_LCD_CAM_CLK_EN_M (SYSTEM_LCD_CAM_CLK_EN_V << SYSTEM_LCD_CAM_CLK_EN_S) -#define SYSTEM_LCD_CAM_CLK_EN_V 0x00000001U -#define SYSTEM_LCD_CAM_CLK_EN_S 9 -/** SYSTEM_UART2_CLK_EN : R/W; bitpos: [10]; default: 1; - * Need add description - */ -#define SYSTEM_UART2_CLK_EN (BIT(10)) -#define SYSTEM_UART2_CLK_EN_M (SYSTEM_UART2_CLK_EN_V << SYSTEM_UART2_CLK_EN_S) -#define SYSTEM_UART2_CLK_EN_V 0x00000001U -#define SYSTEM_UART2_CLK_EN_S 10 -/** SYSTEM_TSENS_CLK_EN : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define SYSTEM_TSENS_CLK_EN (BIT(11)) -#define SYSTEM_TSENS_CLK_EN_M (SYSTEM_TSENS_CLK_EN_V << SYSTEM_TSENS_CLK_EN_S) -#define SYSTEM_TSENS_CLK_EN_V 0x00000001U -#define SYSTEM_TSENS_CLK_EN_S 11 -/** SYSTEM_ETM_CLK_EN : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define SYSTEM_ETM_CLK_EN (BIT(12)) -#define SYSTEM_ETM_CLK_EN_M (SYSTEM_ETM_CLK_EN_V << SYSTEM_ETM_CLK_EN_S) -#define SYSTEM_ETM_CLK_EN_V 0x00000001U -#define SYSTEM_ETM_CLK_EN_S 12 -/** SYSTEM_TIMERGROUP3_CLK_EN : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define SYSTEM_TIMERGROUP3_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP3_CLK_EN_M (SYSTEM_TIMERGROUP3_CLK_EN_V << SYSTEM_TIMERGROUP3_CLK_EN_S) -#define SYSTEM_TIMERGROUP3_CLK_EN_V 0x00000001U -#define SYSTEM_TIMERGROUP3_CLK_EN_S 13 -/** SYSTEM_REGRET_CLK_EN : R/W; bitpos: [14]; default: 0; - * Need add description - */ -#define SYSTEM_REGRET_CLK_EN (BIT(14)) -#define SYSTEM_REGRET_CLK_EN_M (SYSTEM_REGRET_CLK_EN_V << SYSTEM_REGRET_CLK_EN_S) -#define SYSTEM_REGRET_CLK_EN_V 0x00000001U -#define SYSTEM_REGRET_CLK_EN_S 14 -/** SYSTEM_PVT_CLK_EN : R/W; bitpos: [15]; default: 1; - * Need add description - */ -#define SYSTEM_PVT_CLK_EN (BIT(15)) -#define SYSTEM_PVT_CLK_EN_M (SYSTEM_PVT_CLK_EN_V << SYSTEM_PVT_CLK_EN_S) -#define SYSTEM_PVT_CLK_EN_V 0x00000001U -#define SYSTEM_PVT_CLK_EN_S 15 - -/** SYSTEM_PERIP_RST_EN0_REG register - * register description - */ -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_CLKRST_BASE + 0x28) -/** SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_TIMERS_RST (BIT(0)) -#define SYSTEM_TIMERS_RST_M (SYSTEM_TIMERS_RST_V << SYSTEM_TIMERS_RST_S) -#define SYSTEM_TIMERS_RST_V 0x00000001U -#define SYSTEM_TIMERS_RST_S 0 -/** SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_SPI01_RST (BIT(1)) -#define SYSTEM_SPI01_RST_M (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S) -#define SYSTEM_SPI01_RST_V 0x00000001U -#define SYSTEM_SPI01_RST_S 1 -/** SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_UART_RST (BIT(2)) -#define SYSTEM_UART_RST_M (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S) -#define SYSTEM_UART_RST_V 0x00000001U -#define SYSTEM_UART_RST_S 2 -/** SYSTEM_WDG_RST : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_WDG_RST (BIT(3)) -#define SYSTEM_WDG_RST_M (SYSTEM_WDG_RST_V << SYSTEM_WDG_RST_S) -#define SYSTEM_WDG_RST_V 0x00000001U -#define SYSTEM_WDG_RST_S 3 -/** SYSTEM_I2S0_RST : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define SYSTEM_I2S0_RST (BIT(4)) -#define SYSTEM_I2S0_RST_M (SYSTEM_I2S0_RST_V << SYSTEM_I2S0_RST_S) -#define SYSTEM_I2S0_RST_V 0x00000001U -#define SYSTEM_I2S0_RST_S 4 -/** SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define SYSTEM_UART1_RST (BIT(5)) -#define SYSTEM_UART1_RST_M (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S) -#define SYSTEM_UART1_RST_V 0x00000001U -#define SYSTEM_UART1_RST_S 5 -/** SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define SYSTEM_SPI2_RST (BIT(6)) -#define SYSTEM_SPI2_RST_M (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S) -#define SYSTEM_SPI2_RST_V 0x00000001U -#define SYSTEM_SPI2_RST_S 6 -/** SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define SYSTEM_I2C_EXT0_RST (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_M (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S) -#define SYSTEM_I2C_EXT0_RST_V 0x00000001U -#define SYSTEM_I2C_EXT0_RST_S 7 -/** SYSTEM_UHCI0_RST : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define SYSTEM_UHCI0_RST (BIT(8)) -#define SYSTEM_UHCI0_RST_M (SYSTEM_UHCI0_RST_V << SYSTEM_UHCI0_RST_S) -#define SYSTEM_UHCI0_RST_V 0x00000001U -#define SYSTEM_UHCI0_RST_S 8 -/** SYSTEM_RMT_RST : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define SYSTEM_RMT_RST (BIT(9)) -#define SYSTEM_RMT_RST_M (SYSTEM_RMT_RST_V << SYSTEM_RMT_RST_S) -#define SYSTEM_RMT_RST_V 0x00000001U -#define SYSTEM_RMT_RST_S 9 -/** SYSTEM_PCNT_RST : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define SYSTEM_PCNT_RST (BIT(10)) -#define SYSTEM_PCNT_RST_M (SYSTEM_PCNT_RST_V << SYSTEM_PCNT_RST_S) -#define SYSTEM_PCNT_RST_V 0x00000001U -#define SYSTEM_PCNT_RST_S 10 -/** SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define SYSTEM_LEDC_RST (BIT(11)) -#define SYSTEM_LEDC_RST_M (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S) -#define SYSTEM_LEDC_RST_V 0x00000001U -#define SYSTEM_LEDC_RST_S 11 -/** SYSTEM_UHCI1_RST : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define SYSTEM_UHCI1_RST (BIT(12)) -#define SYSTEM_UHCI1_RST_M (SYSTEM_UHCI1_RST_V << SYSTEM_UHCI1_RST_S) -#define SYSTEM_UHCI1_RST_V 0x00000001U -#define SYSTEM_UHCI1_RST_S 12 -/** SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define SYSTEM_TIMERGROUP_RST (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_M (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S) -#define SYSTEM_TIMERGROUP_RST_V 0x00000001U -#define SYSTEM_TIMERGROUP_RST_S 13 -/** SYSTEM_EFUSE_RST : R/W; bitpos: [14]; default: 0; - * Need add description - */ -#define SYSTEM_EFUSE_RST (BIT(14)) -#define SYSTEM_EFUSE_RST_M (SYSTEM_EFUSE_RST_V << SYSTEM_EFUSE_RST_S) -#define SYSTEM_EFUSE_RST_V 0x00000001U -#define SYSTEM_EFUSE_RST_S 14 -/** SYSTEM_TIMERGROUP1_RST : R/W; bitpos: [15]; default: 0; - * Need add description - */ -#define SYSTEM_TIMERGROUP1_RST (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_M (SYSTEM_TIMERGROUP1_RST_V << SYSTEM_TIMERGROUP1_RST_S) -#define SYSTEM_TIMERGROUP1_RST_V 0x00000001U -#define SYSTEM_TIMERGROUP1_RST_S 15 -/** SYSTEM_SPI3_RST : R/W; bitpos: [16]; default: 0; - * Need add description - */ -#define SYSTEM_SPI3_RST (BIT(16)) -#define SYSTEM_SPI3_RST_M (SYSTEM_SPI3_RST_V << SYSTEM_SPI3_RST_S) -#define SYSTEM_SPI3_RST_V 0x00000001U -#define SYSTEM_SPI3_RST_S 16 -/** SYSTEM_PWM0_RST : R/W; bitpos: [17]; default: 0; - * Need add description - */ -#define SYSTEM_PWM0_RST (BIT(17)) -#define SYSTEM_PWM0_RST_M (SYSTEM_PWM0_RST_V << SYSTEM_PWM0_RST_S) -#define SYSTEM_PWM0_RST_V 0x00000001U -#define SYSTEM_PWM0_RST_S 17 -/** SYSTEM_I2C_EXT1_RST : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define SYSTEM_I2C_EXT1_RST (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_M (SYSTEM_I2C_EXT1_RST_V << SYSTEM_I2C_EXT1_RST_S) -#define SYSTEM_I2C_EXT1_RST_V 0x00000001U -#define SYSTEM_I2C_EXT1_RST_S 18 -/** SYSTEM_TWAI_RST : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define SYSTEM_TWAI_RST (BIT(19)) -#define SYSTEM_TWAI_RST_M (SYSTEM_TWAI_RST_V << SYSTEM_TWAI_RST_S) -#define SYSTEM_TWAI_RST_V 0x00000001U -#define SYSTEM_TWAI_RST_S 19 -/** SYSTEM_PWM1_RST : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define SYSTEM_PWM1_RST (BIT(20)) -#define SYSTEM_PWM1_RST_M (SYSTEM_PWM1_RST_V << SYSTEM_PWM1_RST_S) -#define SYSTEM_PWM1_RST_V 0x00000001U -#define SYSTEM_PWM1_RST_S 20 -/** SYSTEM_I2S1_RST : R/W; bitpos: [21]; default: 0; - * Need add description - */ -#define SYSTEM_I2S1_RST (BIT(21)) -#define SYSTEM_I2S1_RST_M (SYSTEM_I2S1_RST_V << SYSTEM_I2S1_RST_S) -#define SYSTEM_I2S1_RST_V 0x00000001U -#define SYSTEM_I2S1_RST_S 21 -/** SYSTEM_SPI2_DMA_RST : R/W; bitpos: [22]; default: 0; - * Need add description - */ -#define SYSTEM_SPI2_DMA_RST (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_M (SYSTEM_SPI2_DMA_RST_V << SYSTEM_SPI2_DMA_RST_S) -#define SYSTEM_SPI2_DMA_RST_V 0x00000001U -#define SYSTEM_SPI2_DMA_RST_S 22 -/** SYSTEM_USB_DEVICE_RST : R/W; bitpos: [23]; default: 0; - * Need add description - */ -#define SYSTEM_USB_DEVICE_RST (BIT(23)) -#define SYSTEM_USB_DEVICE_RST_M (SYSTEM_USB_DEVICE_RST_V << SYSTEM_USB_DEVICE_RST_S) -#define SYSTEM_USB_DEVICE_RST_V 0x00000001U -#define SYSTEM_USB_DEVICE_RST_S 23 -/** SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0; - * Need add description - */ -#define SYSTEM_UART_MEM_RST (BIT(24)) -#define SYSTEM_UART_MEM_RST_M (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S) -#define SYSTEM_UART_MEM_RST_V 0x00000001U -#define SYSTEM_UART_MEM_RST_S 24 -/** SYSTEM_PWM2_RST : R/W; bitpos: [25]; default: 0; - * Need add description - */ -#define SYSTEM_PWM2_RST (BIT(25)) -#define SYSTEM_PWM2_RST_M (SYSTEM_PWM2_RST_V << SYSTEM_PWM2_RST_S) -#define SYSTEM_PWM2_RST_V 0x00000001U -#define SYSTEM_PWM2_RST_S 25 -/** SYSTEM_PWM3_RST : R/W; bitpos: [26]; default: 0; - * Need add description - */ -#define SYSTEM_PWM3_RST (BIT(26)) -#define SYSTEM_PWM3_RST_M (SYSTEM_PWM3_RST_V << SYSTEM_PWM3_RST_S) -#define SYSTEM_PWM3_RST_V 0x00000001U -#define SYSTEM_PWM3_RST_S 26 -/** SYSTEM_SPI3_DMA_RST : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define SYSTEM_SPI3_DMA_RST (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_M (SYSTEM_SPI3_DMA_RST_V << SYSTEM_SPI3_DMA_RST_S) -#define SYSTEM_SPI3_DMA_RST_V 0x00000001U -#define SYSTEM_SPI3_DMA_RST_S 27 -/** SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define SYSTEM_APB_SARADC_RST (BIT(28)) -#define SYSTEM_APB_SARADC_RST_M (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S) -#define SYSTEM_APB_SARADC_RST_V 0x00000001U -#define SYSTEM_APB_SARADC_RST_S 28 -/** SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0; - * Need add description - */ -#define SYSTEM_SYSTIMER_RST (BIT(29)) -#define SYSTEM_SYSTIMER_RST_M (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S) -#define SYSTEM_SYSTIMER_RST_V 0x00000001U -#define SYSTEM_SYSTIMER_RST_S 29 -/** SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define SYSTEM_ADC2_ARB_RST (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_M (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S) -#define SYSTEM_ADC2_ARB_RST_V 0x00000001U -#define SYSTEM_ADC2_ARB_RST_S 30 -/** SYSTEM_SPI4_RST : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define SYSTEM_SPI4_RST (BIT(31)) -#define SYSTEM_SPI4_RST_M (SYSTEM_SPI4_RST_V << SYSTEM_SPI4_RST_S) -#define SYSTEM_SPI4_RST_V 0x00000001U -#define SYSTEM_SPI4_RST_S 31 - -/** SYSTEM_PERIP_RST_EN1_REG register - * register description - */ -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_CLKRST_BASE + 0x2c) -/** SYSTEM_RETENTION_TOP_RST : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_RETENTION_TOP_RST (BIT(0)) -#define SYSTEM_RETENTION_TOP_RST_M (SYSTEM_RETENTION_TOP_RST_V << SYSTEM_RETENTION_TOP_RST_S) -#define SYSTEM_RETENTION_TOP_RST_V 0x00000001U -#define SYSTEM_RETENTION_TOP_RST_S 0 -/** SYSTEM_CRYPTO_AES_RST : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SYSTEM_CRYPTO_AES_RST (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_M (SYSTEM_CRYPTO_AES_RST_V << SYSTEM_CRYPTO_AES_RST_S) -#define SYSTEM_CRYPTO_AES_RST_V 0x00000001U -#define SYSTEM_CRYPTO_AES_RST_S 1 -/** SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1; - * Need add description - */ -#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_M (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S) -#define SYSTEM_CRYPTO_SHA_RST_V 0x00000001U -#define SYSTEM_CRYPTO_SHA_RST_S 2 -/** SYSTEM_CRYPTO_RSA_RST : R/W; bitpos: [3]; default: 1; - * Need add description - */ -#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_M (SYSTEM_CRYPTO_RSA_RST_V << SYSTEM_CRYPTO_RSA_RST_S) -#define SYSTEM_CRYPTO_RSA_RST_V 0x00000001U -#define SYSTEM_CRYPTO_RSA_RST_S 3 -/** SYSTEM_CRYPTO_DS_RST : R/W; bitpos: [4]; default: 1; - * Need add description - */ -#define SYSTEM_CRYPTO_DS_RST (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_M (SYSTEM_CRYPTO_DS_RST_V << SYSTEM_CRYPTO_DS_RST_S) -#define SYSTEM_CRYPTO_DS_RST_V 0x00000001U -#define SYSTEM_CRYPTO_DS_RST_S 4 -/** SYSTEM_CRYPTO_HMAC_RST : R/W; bitpos: [5]; default: 1; - * Need add description - */ -#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_M (SYSTEM_CRYPTO_HMAC_RST_V << SYSTEM_CRYPTO_HMAC_RST_S) -#define SYSTEM_CRYPTO_HMAC_RST_V 0x00000001U -#define SYSTEM_CRYPTO_HMAC_RST_S 5 -/** SYSTEM_CRYPTO_ECC_RST : R/W; bitpos: [6]; default: 1; - * Need add description - */ -#define SYSTEM_CRYPTO_ECC_RST (BIT(6)) -#define SYSTEM_CRYPTO_ECC_RST_M (SYSTEM_CRYPTO_ECC_RST_V << SYSTEM_CRYPTO_ECC_RST_S) -#define SYSTEM_CRYPTO_ECC_RST_V 0x00000001U -#define SYSTEM_CRYPTO_ECC_RST_S 6 -/** SYSTEM_DMA_RST : R/W; bitpos: [7]; default: 1; - * Need add description - */ -#define SYSTEM_DMA_RST (BIT(7)) -#define SYSTEM_DMA_RST_M (SYSTEM_DMA_RST_V << SYSTEM_DMA_RST_S) -#define SYSTEM_DMA_RST_V 0x00000001U -#define SYSTEM_DMA_RST_S 7 -/** SYSTEM_SDIO_HOST_RST : R/W; bitpos: [8]; default: 1; - * Need add description - */ -#define SYSTEM_SDIO_HOST_RST (BIT(8)) -#define SYSTEM_SDIO_HOST_RST_M (SYSTEM_SDIO_HOST_RST_V << SYSTEM_SDIO_HOST_RST_S) -#define SYSTEM_SDIO_HOST_RST_V 0x00000001U -#define SYSTEM_SDIO_HOST_RST_S 8 -/** SYSTEM_LCD_CAM_RST : R/W; bitpos: [9]; default: 1; - * Need add description - */ -#define SYSTEM_LCD_CAM_RST (BIT(9)) -#define SYSTEM_LCD_CAM_RST_M (SYSTEM_LCD_CAM_RST_V << SYSTEM_LCD_CAM_RST_S) -#define SYSTEM_LCD_CAM_RST_V 0x00000001U -#define SYSTEM_LCD_CAM_RST_S 9 -/** SYSTEM_UART2_RST : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define SYSTEM_UART2_RST (BIT(10)) -#define SYSTEM_UART2_RST_M (SYSTEM_UART2_RST_V << SYSTEM_UART2_RST_S) -#define SYSTEM_UART2_RST_V 0x00000001U -#define SYSTEM_UART2_RST_S 10 -/** SYSTEM_TSENS_RST : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define SYSTEM_TSENS_RST (BIT(11)) -#define SYSTEM_TSENS_RST_M (SYSTEM_TSENS_RST_V << SYSTEM_TSENS_RST_S) -#define SYSTEM_TSENS_RST_V 0x00000001U -#define SYSTEM_TSENS_RST_S 11 -/** SYSTEM_ETM_RST : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define SYSTEM_ETM_RST (BIT(12)) -#define SYSTEM_ETM_RST_M (SYSTEM_ETM_RST_V << SYSTEM_ETM_RST_S) -#define SYSTEM_ETM_RST_V 0x00000001U -#define SYSTEM_ETM_RST_S 12 -/** SYSTEM_TIMERGROUP3_RST : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define SYSTEM_TIMERGROUP3_RST (BIT(13)) -#define SYSTEM_TIMERGROUP3_RST_M (SYSTEM_TIMERGROUP3_RST_V << SYSTEM_TIMERGROUP3_RST_S) -#define SYSTEM_TIMERGROUP3_RST_V 0x00000001U -#define SYSTEM_TIMERGROUP3_RST_S 13 -/** SYSTEM_REGRET_RST : R/W; bitpos: [14]; default: 0; - * Need add description - */ -#define SYSTEM_REGRET_RST (BIT(14)) -#define SYSTEM_REGRET_RST_M (SYSTEM_REGRET_RST_V << SYSTEM_REGRET_RST_S) -#define SYSTEM_REGRET_RST_V 0x00000001U -#define SYSTEM_REGRET_RST_S 14 -/** SYSTEM_PVT_RST : R/W; bitpos: [15]; default: 0; - * Need add description - */ -#define SYSTEM_PVT_RST (BIT(15)) -#define SYSTEM_PVT_RST_M (SYSTEM_PVT_RST_V << SYSTEM_PVT_RST_S) -#define SYSTEM_PVT_RST_V 0x00000001U -#define SYSTEM_PVT_RST_S 15 - -/** SYSTEM_FPGA_DBG_REG register - * register description - */ -#define SYSTEM_FPGA_DBG_REG (DR_REG_CLKRST_BASE + 0x30) -/** SYSTEM_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; - * Need add description - */ -#define SYSTEM_FPGA_DEBUG 0xFFFFFFFFU -#define SYSTEM_FPGA_DEBUG_M (SYSTEM_FPGA_DEBUG_V << SYSTEM_FPGA_DEBUG_S) -#define SYSTEM_FPGA_DEBUG_V 0xFFFFFFFFU -#define SYSTEM_FPGA_DEBUG_S 0 - -/** SYSTEM_REGCLK_CONF_REG register - * register description - */ -#define SYSTEM_REGCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x34) -/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) -#define SYSTEM_CLK_EN_V 0x00000001U -#define SYSTEM_CLK_EN_S 0 - -/** SYSTEM_CLKRST_DATE_REG register - * register description - */ -#define SYSTEM_CLKRST_DATE_REG (DR_REG_SYSTEM_BASE + 0x38) -/** CLKRST_DATE : R/W; bitpos: [27:0]; default: 34672962; - * Need add description - */ -#define CLKRST_DATE 0x0FFFFFFFU -#define CLKRST_DATE_M (CLKRST_DATE_V << CLKRST_DATE_S) -#define CLKRST_DATE_V 0x0FFFFFFFU -#define CLKRST_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/ecc_mult_reg.h b/components/soc/esp32h4/include/rev2/soc/ecc_mult_reg.h deleted file mode 100644 index 3cc3f815d2..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/ecc_mult_reg.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xC) -/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the ecc calculate done interrupt.*/ -#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_RAW_M (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_RAW_V 0x1 -#define ECC_MULT_CALC_DONE_INT_RAW_S 0 - -#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) -/* ECC_MULT_CALC_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the ecc calculate done interrupt.*/ -#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_ST_M (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_ST_V 0x1 -#define ECC_MULT_CALC_DONE_INT_ST_S 0 - -#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) -/* ECC_MULT_CALC_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the ecc calculate done interrupt.*/ -#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_ENA_M (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_ENA_V 0x1 -#define ECC_MULT_CALC_DONE_INT_ENA_S 0 - -#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) -/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the ecc calculate done interrupt.*/ -#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_CLR_M (BIT(0)) -#define ECC_MULT_CALC_DONE_INT_CLR_V 0x1 -#define ECC_MULT_CALC_DONE_INT_CLR_S 0 - -#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1C) -/* ECC_MULT_VERIFICATION_RESULT : RO/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: ECC verification result register..*/ -#define ECC_MULT_VERIFICATION_RESULT (BIT(8)) -#define ECC_MULT_VERIFICATION_RESULT_M (BIT(8)) -#define ECC_MULT_VERIFICATION_RESULT_V 0x1 -#define ECC_MULT_VERIFICATION_RESULT_S 8 -/* ECC_MULT_WORK_MODE : R/W ;bitpos:[7:5] ;default: 3'b0 ; */ -/*description: ECC operation mode register..*/ -#define ECC_MULT_WORK_MODE 0x00000007 -#define ECC_MULT_WORK_MODE_M ((ECC_MULT_WORK_MODE_V)<<(ECC_MULT_WORK_MODE_S)) -#define ECC_MULT_WORK_MODE_V 0x7 -#define ECC_MULT_WORK_MODE_S 5 -/* ECC_MULT_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: clk gate.*/ -#define ECC_MULT_CLK_EN (BIT(4)) -#define ECC_MULT_CLK_EN_M (BIT(4)) -#define ECC_MULT_CLK_EN_V 0x1 -#define ECC_MULT_CLK_EN_S 4 -/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define ECC_MULT_SECURITY_MODE (BIT(3)) -#define ECC_MULT_SECURITY_MODE_M (BIT(3)) -#define ECC_MULT_SECURITY_MODE_V 0x1 -#define ECC_MULT_SECURITY_MODE_S 3 -/* ECC_MULT_KEY_LENGTH : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 0:192bit key length mode. 1:256bit key length mode.*/ -#define ECC_MULT_KEY_LENGTH (BIT(2)) -#define ECC_MULT_KEY_LENGTH_M (BIT(2)) -#define ECC_MULT_KEY_LENGTH_V 0x1 -#define ECC_MULT_KEY_LENGTH_S 2 -/* ECC_MULT_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset ECC.*/ -#define ECC_MULT_RESET (BIT(1)) -#define ECC_MULT_RESET_M (BIT(1)) -#define ECC_MULT_RESET_V 0x1 -#define ECC_MULT_RESET_S 1 -/* ECC_MULT_START : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to start a ECC operation..*/ -#define ECC_MULT_START (BIT(0)) -#define ECC_MULT_START_M (BIT(0)) -#define ECC_MULT_START_V 0x1 -#define ECC_MULT_START_S 0 - -#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xFC) -/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */ -/*description: ECC mult version control register.*/ -#define ECC_MULT_DATE 0x0FFFFFFF -#define ECC_MULT_DATE_M ((ECC_MULT_DATE_V)<<(ECC_MULT_DATE_S)) -#define ECC_MULT_DATE_V 0xFFFFFFF -#define ECC_MULT_DATE_S 0 - -#define ECC_MULT_K_1_REG (DR_REG_ECC_MULT_BASE + 0x0100) -/* ECC_MULT_MEM_K_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_1 0xFFFFFFFF -#define ECC_MULT_MEM_K_1_M ((ECC_MULT_MEM_K_1_V)<<(ECC_MULT_MEM_K_1_S)) -#define ECC_MULT_MEM_K_1_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_1_S 0 - -#define ECC_MULT_K_2_REG (DR_REG_ECC_MULT_BASE + 0x0104) -/* ECC_MULT_MEM_K_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_2 0xFFFFFFFF -#define ECC_MULT_MEM_K_2_M ((ECC_MULT_MEM_K_2_V)<<(ECC_MULT_MEM_K_2_S)) -#define ECC_MULT_MEM_K_2_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_2_S 0 - -#define ECC_MULT_K_3_REG (DR_REG_ECC_MULT_BASE + 0x0108) -/* ECC_MULT_MEM_K_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_3 0xFFFFFFFF -#define ECC_MULT_MEM_K_3_M ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S)) -#define ECC_MULT_MEM_K_3_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_3_S 0 - -#define ECC_MULT_K_4_REG (DR_REG_ECC_MULT_BASE + 0x010c) -/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_4 0xFFFFFFFF -#define ECC_MULT_MEM_K_4_M ((ECC_MULT_MEM_K_4_V)<<(ECC_MULT_MEM_K_4_S)) -#define ECC_MULT_MEM_K_4_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_4_S 0 - -#define ECC_MULT_K_5_REG (DR_REG_ECC_MULT_BASE + 0x0110) -/* ECC_MULT_MEM_K_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_5 0xFFFFFFFF -#define ECC_MULT_MEM_K_5_M ((ECC_MULT_MEM_K_5_V)<<(ECC_MULT_MEM_K_5_S)) -#define ECC_MULT_MEM_K_5_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_5_S 0 - -#define ECC_MULT_K_6_REG (DR_REG_ECC_MULT_BASE + 0x0114) -/* ECC_MULT_MEM_K_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_6 0xFFFFFFFF -#define ECC_MULT_MEM_K_6_M ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S)) -#define ECC_MULT_MEM_K_6_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_6_S 0 - -#define ECC_MULT_K_7_REG (DR_REG_ECC_MULT_BASE + 0x0118) -/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_7 0xFFFFFFFF -#define ECC_MULT_MEM_K_7_M ((ECC_MULT_MEM_K_7_V)<<(ECC_MULT_MEM_K_7_S)) -#define ECC_MULT_MEM_K_7_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_7_S 0 - -#define ECC_MULT_K_8_REG (DR_REG_ECC_MULT_BASE + 0x011c) -/* ECC_MULT_MEM_K_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter k.*/ -#define ECC_MULT_MEM_K_8 0xFFFFFFFF -#define ECC_MULT_MEM_K_8_M ((ECC_MULT_MEM_K_8_V)<<(ECC_MULT_MEM_K_8_S)) -#define ECC_MULT_MEM_K_8_V 0xFFFFFFFF -#define ECC_MULT_MEM_K_8_S 0 - -#define ECC_MULT_PX_1_REG (DR_REG_ECC_MULT_BASE + 0x0120) -/* ECC_MULT_MEM_PX_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_1 0xFFFFFFFF -#define ECC_MULT_MEM_PX_1_M ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S)) -#define ECC_MULT_MEM_PX_1_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_1_S 0 - -#define ECC_MULT_PX_2_REG (DR_REG_ECC_MULT_BASE + 0x0124) -/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_2 0xFFFFFFFF -#define ECC_MULT_MEM_PX_2_M ((ECC_MULT_MEM_PX_2_V)<<(ECC_MULT_MEM_PX_2_S)) -#define ECC_MULT_MEM_PX_2_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_2_S 0 - -#define ECC_MULT_PX_3_REG (DR_REG_ECC_MULT_BASE + 0x0128) -/* ECC_MULT_MEM_PX_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_3 0xFFFFFFFF -#define ECC_MULT_MEM_PX_3_M ((ECC_MULT_MEM_PX_3_V)<<(ECC_MULT_MEM_PX_3_S)) -#define ECC_MULT_MEM_PX_3_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_3_S 0 - -#define ECC_MULT_PX_4_REG (DR_REG_ECC_MULT_BASE + 0x012c) -/* ECC_MULT_MEM_PX_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_4 0xFFFFFFFF -#define ECC_MULT_MEM_PX_4_M ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S)) -#define ECC_MULT_MEM_PX_4_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_4_S 0 - -#define ECC_MULT_PX_5_REG (DR_REG_ECC_MULT_BASE + 0x0130) -/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_5 0xFFFFFFFF -#define ECC_MULT_MEM_PX_5_M ((ECC_MULT_MEM_PX_5_V)<<(ECC_MULT_MEM_PX_5_S)) -#define ECC_MULT_MEM_PX_5_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_5_S 0 - -#define ECC_MULT_PX_6_REG (DR_REG_ECC_MULT_BASE + 0x0134) -/* ECC_MULT_MEM_PX_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_6 0xFFFFFFFF -#define ECC_MULT_MEM_PX_6_M ((ECC_MULT_MEM_PX_6_V)<<(ECC_MULT_MEM_PX_6_S)) -#define ECC_MULT_MEM_PX_6_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_6_S 0 - -#define ECC_MULT_PX_7_REG (DR_REG_ECC_MULT_BASE + 0x0138) -/* ECC_MULT_MEM_PX_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_7 0xFFFFFFFF -#define ECC_MULT_MEM_PX_7_M ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S)) -#define ECC_MULT_MEM_PX_7_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_7_S 0 - -#define ECC_MULT_PX_8_REG (DR_REG_ECC_MULT_BASE + 0x013c) -/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Px.*/ -#define ECC_MULT_MEM_PX_8 0xFFFFFFFF -#define ECC_MULT_MEM_PX_8_M ((ECC_MULT_MEM_PX_8_V)<<(ECC_MULT_MEM_PX_8_S)) -#define ECC_MULT_MEM_PX_8_V 0xFFFFFFFF -#define ECC_MULT_MEM_PX_8_S 0 - -#define ECC_MULT_PY_1_REG (DR_REG_ECC_MULT_BASE + 0x0140) -/* ECC_MULT_MEM_PY_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_1 0xFFFFFFFF -#define ECC_MULT_MEM_PY_1_M ((ECC_MULT_MEM_PY_1_V)<<(ECC_MULT_MEM_PY_1_S)) -#define ECC_MULT_MEM_PY_1_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_1_S 0 - -#define ECC_MULT_PY_2_REG (DR_REG_ECC_MULT_BASE + 0x0144) -/* ECC_MULT_MEM_PY_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_2 0xFFFFFFFF -#define ECC_MULT_MEM_PY_2_M ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S)) -#define ECC_MULT_MEM_PY_2_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_2_S 0 - -#define ECC_MULT_PY_3_REG (DR_REG_ECC_MULT_BASE + 0x0148) -/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_3 0xFFFFFFFF -#define ECC_MULT_MEM_PY_3_M ((ECC_MULT_MEM_PY_3_V)<<(ECC_MULT_MEM_PY_3_S)) -#define ECC_MULT_MEM_PY_3_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_3_S 0 - -#define ECC_MULT_PY_4_REG (DR_REG_ECC_MULT_BASE + 0x014c) -/* ECC_MULT_MEM_PY_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_4 0xFFFFFFFF -#define ECC_MULT_MEM_PY_4_M ((ECC_MULT_MEM_PY_4_V)<<(ECC_MULT_MEM_PY_4_S)) -#define ECC_MULT_MEM_PY_4_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_4_S 0 - -#define ECC_MULT_PY_5_REG (DR_REG_ECC_MULT_BASE + 0x0150) -/* ECC_MULT_MEM_PY_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_5 0xFFFFFFFF -#define ECC_MULT_MEM_PY_5_M ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S)) -#define ECC_MULT_MEM_PY_5_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_5_S 0 - -#define ECC_MULT_PY_6_REG (DR_REG_ECC_MULT_BASE + 0x0154) -/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_6 0xFFFFFFFF -#define ECC_MULT_MEM_PY_6_M ((ECC_MULT_MEM_PY_6_V)<<(ECC_MULT_MEM_PY_6_S)) -#define ECC_MULT_MEM_PY_6_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_6_S 0 - -#define ECC_MULT_PY_7_REG (DR_REG_ECC_MULT_BASE + 0x0158) -/* ECC_MULT_MEM_PY_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_7 0xFFFFFFFF -#define ECC_MULT_MEM_PY_7_M ((ECC_MULT_MEM_PY_7_V)<<(ECC_MULT_MEM_PY_7_S)) -#define ECC_MULT_MEM_PY_7_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_7_S 0 - -#define ECC_MULT_PY_8_REG (DR_REG_ECC_MULT_BASE + 0x015c) -/* ECC_MULT_MEM_PY_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: ECC Mem Parameter Py.*/ -#define ECC_MULT_MEM_PY_8 0xFFFFFFFF -#define ECC_MULT_MEM_PY_8_M ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S)) -#define ECC_MULT_MEM_PY_8_V 0xFFFFFFFF -#define ECC_MULT_MEM_PY_8_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/ecc_mult_struct.h b/components/soc/esp32h4/include/rev2/soc/ecc_mult_struct.h deleted file mode 100644 index 365f47ba00..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/ecc_mult_struct.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Interrupt registers */ -/** Type of int_raw register - * ECC interrupt raw register, valid in level. - */ -typedef union { - struct { - /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecc calculate done interrupt - */ - uint32_t calc_done_int_raw:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecc_mult_int_raw_reg_t; - -/** Type of int_st register - * ECC interrupt status register. - */ -typedef union { - struct { - /** calc_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecc calculate done interrupt - */ - uint32_t calc_done_int_st:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecc_mult_int_st_reg_t; - -/** Type of int_ena register - * ECC interrupt enable register. - */ -typedef union { - struct { - /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecc calculate done interrupt - */ - uint32_t calc_done_int_ena:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecc_mult_int_ena_reg_t; - -/** Type of int_clr register - * ECC interrupt clear register. - */ -typedef union { - struct { - /** calc_done_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecc calculate done interrupt - */ - uint32_t calc_done_int_clr:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecc_mult_int_clr_reg_t; - - -/** Group: Configuration registers */ -/** Type of conf register - * ECC configure register - */ -typedef union { - struct { - /** start : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to start a ECC operation. - */ - uint32_t start:1; - /** reset : WT; bitpos: [1]; default: 0; - * Set this bit to reset ECC - */ - uint32_t reset:1; - /** key_length : R/W; bitpos: [2]; default: 0; - * 0:192bit key length mode. 1:256bit key length mode - */ - uint32_t key_length:1; - /** security_mode : R/W; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t security_mode:1; - /** clk_en : R/W; bitpos: [4]; default: 0; - * clk gate - */ - uint32_t clk_en:1; - /** work_mode : R/W; bitpos: [7:5]; default: 0; - * ECC operation mode register. - */ - uint32_t work_mode:3; - /** verification_result : RO/SS; bitpos: [8]; default: 0; - * ECC verification result register. - */ - uint32_t verification_result:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} ecc_mult_conf_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 34636176; - * ECC mult version control register - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} ecc_mult_date_reg_t; - - -typedef struct { - uint32_t reserved_000[3]; - volatile ecc_mult_int_raw_reg_t int_raw; - volatile ecc_mult_int_st_reg_t int_st; - volatile ecc_mult_int_ena_reg_t int_ena; - volatile ecc_mult_int_clr_reg_t int_clr; - volatile ecc_mult_conf_reg_t conf; - uint32_t reserved_020[55]; - volatile ecc_mult_date_reg_t date; -} ecc_mult_dev_t; - - -#ifndef __cplusplus -_Static_assert(sizeof(ecc_mult_dev_t) == 0x100, "Invalid size of ecc_mult_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/efuse_reg.h b/components/soc/esp32h4/include/rev2/soc/efuse_reg.h deleted file mode 100644 index 9be65687c0..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/efuse_reg.h +++ /dev/null @@ -1,2309 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_0 0xFFFFFFFFU -#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_0_S 0 - -/** EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_1 0xFFFFFFFFU -#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_1_S 0 - -/** EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_2 0xFFFFFFFFU -#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_2_S 0 - -/** EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) -/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * The content of the 3rd 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_3 0xFFFFFFFFU -#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_3_S 0 - -/** EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * The content of the 4th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_4 0xFFFFFFFFU -#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_4_S 0 - -/** EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * The content of the 5th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_5 0xFFFFFFFFU -#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_5_S 0 - -/** EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * The content of the 6th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_6 0xFFFFFFFFU -#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_6_S 0 - -/** EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. - */ -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) -/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * The content of the 7th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_7 0xFFFFFFFFU -#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_7_S 0 - -/** EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. - */ -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_0_S 0 - -/** EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. - */ -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_1_S 0 - -/** EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. - */ -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_2_S 0 - -/** EFUSE_RD_WR_DIS_REG register - * BLOCK0 data register $n. - */ -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) -/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * The value of WR_DIS. - */ -#define EFUSE_WR_DIS 0xFFFFFFFFU -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xFFFFFFFFU -#define EFUSE_WR_DIS_S 0 - -/** EFUSE_RD_REPEAT_DATA0_REG register - * BLOCK0 data register $n. - */ -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * The value of RD_DIS. - */ -#define EFUSE_RD_DIS 0x0000007FU -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007FU -#define EFUSE_RD_DIS_S 0 -/** EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED5 (BIT(7)) -#define EFUSE_RPT4_RESERVED5_M (BIT(7)) -#define EFUSE_RPT4_RESERVED5_V 0x1 -#define EFUSE_RPT4_RESERVED5_S 7 -/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * The value of DIS_ICACHE. - */ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) -#define EFUSE_DIS_ICACHE_V 0x00000001U -#define EFUSE_DIS_ICACHE_S 8 -/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * The value of DIS_USB_JTAG. - */ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) -#define EFUSE_DIS_USB_JTAG_V 0x00000001U -#define EFUSE_DIS_USB_JTAG_S 9 -/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; - * The value of DIS_DOWNLOAD_ICACHE. - */ -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/** EFUSE_DIS_USB_DEVICE : RO; bitpos: [11]; default: 0; - * The value of DIS_USB_DEVICE. - */ -#define EFUSE_DIS_USB_DEVICE (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_M (EFUSE_DIS_USB_DEVICE_V << EFUSE_DIS_USB_DEVICE_S) -#define EFUSE_DIS_USB_DEVICE_V 0x00000001U -#define EFUSE_DIS_USB_DEVICE_S 11 -/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * The value of DIS_FORCE_DOWNLOAD. - */ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/** EFUSE_RPT4_RESERVED6 : RO ;bitpos:[13] ;default: 1'b0 ; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED6 (BIT(13)) -#define EFUSE_RPT4_RESERVED6_M (BIT(13)) -#define EFUSE_RPT4_RESERVED6_V 0x1 -#define EFUSE_RPT4_RESERVED6_S 13 -/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * The value of DIS_TWAI. - */ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) -#define EFUSE_DIS_TWAI_V 0x00000001U -#define EFUSE_DIS_TWAI_S 14 -/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * The value of JTAG_SEL_ENABLE. - */ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) -#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * The value of SOFT_DIS_JTAG. - */ -#define EFUSE_SOFT_DIS_JTAG 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) -#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_S 16 -/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * The value of DIS_PAD_JTAG. - */ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) -#define EFUSE_DIS_PAD_JTAG_V 0x00000001U -#define EFUSE_DIS_PAD_JTAG_S 19 -/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * The value of DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * The value of USB_DREFH. - */ -#define EFUSE_USB_DREFH 0x00000003U -#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) -#define EFUSE_USB_DREFH_V 0x00000003U -#define EFUSE_USB_DREFH_S 21 -/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * The value of USB_DREFL. - */ -#define EFUSE_USB_DREFL 0x00000003U -#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) -#define EFUSE_USB_DREFL_V 0x00000003U -#define EFUSE_USB_DREFL_S 23 -/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * The value of USB_EXCHG_PINS. - */ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) -#define EFUSE_USB_EXCHG_PINS_V 0x00000001U -#define EFUSE_USB_EXCHG_PINS_S 25 -/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * The value of VDD_SPI_AS_GPIO. - */ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; - * The value of BTLC_GPIO_ENABLE. - */ -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003U -#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003U -#define EFUSE_BTLC_GPIO_ENABLE_S 27 -/** EFUSE_POWERGLITCH_EN : RO; bitpos: [29]; default: 0; - * The value of POWERGLITCH_EN. - */ -#define EFUSE_POWERGLITCH_EN (BIT(29)) -#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) -#define EFUSE_POWERGLITCH_EN_V 0x00000001U -#define EFUSE_POWERGLITCH_EN_S 29 -/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [31:30]; default: 0; - * The value of POWER_GLITCH_DSENSE. - */ -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003U -#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003U -#define EFUSE_POWER_GLITCH_DSENSE_S 30 - -/** EFUSE_RD_REPEAT_DATA1_REG register - * BLOCK0 data register $n. - */ -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [15:0]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED2 0x0000FFFFU -#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) -#define EFUSE_RPT4_RESERVED2_V 0x0000FFFFU -#define EFUSE_RPT4_RESERVED2_S 0 -/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * The value of WDT_DELAY_SEL. - */ -#define EFUSE_WDT_DELAY_SEL 0x00000003U -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_S 16 -/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * The value of SPI_BOOT_CRYPT_CNT. - */ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE0. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE1. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE2. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * The value of KEY_PURPOSE_0. - */ -#define EFUSE_KEY_PURPOSE_0 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_S 24 -/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * The value of KEY_PURPOSE_1. - */ -#define EFUSE_KEY_PURPOSE_1 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_S 28 - -/** EFUSE_RD_REPEAT_DATA2_REG register - * BLOCK0 data register $n. - */ -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * The value of KEY_PURPOSE_2. - */ -#define EFUSE_KEY_PURPOSE_2 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_S 0 -/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * The value of KEY_PURPOSE_3. - */ -#define EFUSE_KEY_PURPOSE_3 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_S 4 -/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * The value of KEY_PURPOSE_4. - */ -#define EFUSE_KEY_PURPOSE_4 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_S 8 -/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * The value of KEY_PURPOSE_5. - */ -#define EFUSE_KEY_PURPOSE_5 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_S 12 -/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [19:16]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED3 0x0000000FU -#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) -#define EFUSE_RPT4_RESERVED3_V 0x0000000FU -#define EFUSE_RPT4_RESERVED3_S 16 -/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * The value of SECURE_BOOT_EN. - */ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) -#define EFUSE_SECURE_BOOT_EN_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_S 20 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * The value of SECURE_BOOT_AGGRESSIVE_REVOKE. - */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [27:22]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED0 0x0000003FU -#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) -#define EFUSE_RPT4_RESERVED0_V 0x0000003FU -#define EFUSE_RPT4_RESERVED0_S 22 -/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * The value of FLASH_TPUW. - */ -#define EFUSE_FLASH_TPUW 0x0000000FU -#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) -#define EFUSE_FLASH_TPUW_V 0x0000000FU -#define EFUSE_FLASH_TPUW_S 28 - -/** EFUSE_RD_REPEAT_DATA3_REG register - * BLOCK0 data register $n. - */ -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) -/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * The value of DIS_DOWNLOAD_MODE. - */ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 -/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * The value of DIS_DIRECT_BOOT. - */ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) -#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * The value of DIS_USB_SERIAL_JTAG_ROM_PRINT. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/** EFUSE_RPT4_RESERVED8 : RO; bitpos: [3]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED8 (BIT(3)) -#define EFUSE_RPT4_RESERVED8_M (EFUSE_RPT4_RESERVED8_V << EFUSE_RPT4_RESERVED8_S) -#define EFUSE_RPT4_RESERVED8_V 0x00000001U -#define EFUSE_RPT4_RESERVED8_S 3 -/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * The value of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * The value of ENABLE_SECURITY_DOWNLOAD. - */ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * The value of UART_PRINT_CONTROL. - */ -#define EFUSE_UART_PRINT_CONTROL 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) -#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_S 6 -/** EFUSE_RPT4_RESERVED7 : RO; bitpos: [12:8]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED7 0x0000001FU -#define EFUSE_RPT4_RESERVED7_M (EFUSE_RPT4_RESERVED7_V << EFUSE_RPT4_RESERVED7_S) -#define EFUSE_RPT4_RESERVED7_V 0x0000001FU -#define EFUSE_RPT4_RESERVED7_S 8 -/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; - * The value of FORCE_SEND_RESUME. - */ -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) -#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U -#define EFUSE_FORCE_SEND_RESUME_S 13 -/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; - * The value of SECURE_VERSION. - */ -#define EFUSE_SECURE_VERSION 0x0000FFFFU -#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x0000FFFFU -#define EFUSE_SECURE_VERSION_S 14 -/** EFUSE_RPT4_RESERVED1 : RO; bitpos: [31:30]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED1 0x00000003U -#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) -#define EFUSE_RPT4_RESERVED1_V 0x00000003U -#define EFUSE_RPT4_RESERVED1_S 30 - -/** EFUSE_RD_REPEAT_DATA4_REG register - * BLOCK0 data register $n. - */ -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/** EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED4 0x00FFFFFFU -#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) -#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFFU -#define EFUSE_RPT4_RESERVED4_S 0 - -/** EFUSE_RD_MAC_SPI_SYS_0_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) -/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ -#define EFUSE_MAC_0 0xFFFFFFFFU -#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) -#define EFUSE_MAC_0_V 0xFFFFFFFFU -#define EFUSE_MAC_0_S 0 - -/** EFUSE_RD_MAC_SPI_SYS_1_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) -/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ -#define EFUSE_MAC_1 0x0000FFFFU -#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) -#define EFUSE_MAC_1_V 0x0000FFFFU -#define EFUSE_MAC_1_S 0 -/** EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; - * Stores the zeroth part of SPI_PAD_CONF. - */ -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFFU -#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) -#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFFU -#define EFUSE_SPI_PAD_CONF_0_S 16 - -/** EFUSE_RD_MAC_SPI_SYS_2_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first part of SPI_PAD_CONF. - */ -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFFU -#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFFU -#define EFUSE_SPI_PAD_CONF_1_S 0 - -/** EFUSE_RD_MAC_SPI_SYS_3_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Stores the fist 8 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_0 0x000000FF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0xFF -#define EFUSE_SYS_DATA_PART0_0_S 25 -/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: Package version 0:ESP32-H4 */ -#define EFUSE_PKG_VERSION 0x00000007 -#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) -#define EFUSE_PKG_VERSION_V 0x7 -#define EFUSE_PKG_VERSION_S 21 -/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: WAFER version 0:A */ -#define EFUSE_WAFER_VERSION 0x00000007 -#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) -#define EFUSE_WAFER_VERSION_V 0x7 -#define EFUSE_WAFER_VERSION_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF.*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -/** EFUSE_RD_MAC_SPI_SYS_4_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the fist 32 bits of the zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_S 0 - -/** EFUSE_RD_MAC_SPI_SYS_5_REG register - * BLOCK1 data register $n. - */ -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 0 - -/** EFUSE_RD_SYS_PART1_DATA0_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 - -/** EFUSE_RD_SYS_PART1_DATA1_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 - -/** EFUSE_RD_SYS_PART1_DATA2_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 - -/** EFUSE_RD_SYS_PART1_DATA3_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 - -/** EFUSE_RD_SYS_PART1_DATA4_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 - -/** EFUSE_RD_SYS_PART1_DATA5_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_S 0 - -/** EFUSE_RD_SYS_PART1_DATA6_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_S 0 - -/** EFUSE_RD_SYS_PART1_DATA7_REG register - * Register $n of BLOCK2 (system). - */ -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_S 0 - -/** EFUSE_RD_USR_DATA0_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) -/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA0 0xFFFFFFFFU -#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) -#define EFUSE_USR_DATA0_V 0xFFFFFFFFU -#define EFUSE_USR_DATA0_S 0 - -/** EFUSE_RD_USR_DATA1_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) -/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA1 0xFFFFFFFFU -#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) -#define EFUSE_USR_DATA1_V 0xFFFFFFFFU -#define EFUSE_USR_DATA1_S 0 - -/** EFUSE_RD_USR_DATA2_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) -/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA2 0xFFFFFFFFU -#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) -#define EFUSE_USR_DATA2_V 0xFFFFFFFFU -#define EFUSE_USR_DATA2_S 0 - -/** EFUSE_RD_USR_DATA3_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) -/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA3 0xFFFFFFFFU -#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) -#define EFUSE_USR_DATA3_V 0xFFFFFFFFU -#define EFUSE_USR_DATA3_S 0 - -/** EFUSE_RD_USR_DATA4_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) -/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA4 0xFFFFFFFFU -#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) -#define EFUSE_USR_DATA4_V 0xFFFFFFFFU -#define EFUSE_USR_DATA4_S 0 - -/** EFUSE_RD_USR_DATA5_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) -/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA5 0xFFFFFFFFU -#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) -#define EFUSE_USR_DATA5_V 0xFFFFFFFFU -#define EFUSE_USR_DATA5_S 0 - -/** EFUSE_RD_USR_DATA6_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 - -/** EFUSE_RD_USR_DATA7_REG register - * Register $n of BLOCK3 (user). - */ -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). - */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 - -/** EFUSE_RD_KEY0_DATA0_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) -/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA0 0xFFFFFFFFU -#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA0_S 0 - -/** EFUSE_RD_KEY0_DATA1_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) -/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA1 0xFFFFFFFFU -#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA1_S 0 - -/** EFUSE_RD_KEY0_DATA2_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) -/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA2 0xFFFFFFFFU -#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA2_S 0 - -/** EFUSE_RD_KEY0_DATA3_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) -/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA3 0xFFFFFFFFU -#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA3_S 0 - -/** EFUSE_RD_KEY0_DATA4_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) -/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA4 0xFFFFFFFFU -#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA4_S 0 - -/** EFUSE_RD_KEY0_DATA5_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) -/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA5 0xFFFFFFFFU -#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA5_S 0 - -/** EFUSE_RD_KEY0_DATA6_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) -/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA6 0xFFFFFFFFU -#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA6_S 0 - -/** EFUSE_RD_KEY0_DATA7_REG register - * Register $n of BLOCK4 (KEY0). - */ -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) -/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ -#define EFUSE_KEY0_DATA7 0xFFFFFFFFU -#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA7_S 0 - -/** EFUSE_RD_KEY1_DATA0_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) -/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA0 0xFFFFFFFFU -#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA0_S 0 - -/** EFUSE_RD_KEY1_DATA1_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) -/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA1 0xFFFFFFFFU -#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA1_S 0 - -/** EFUSE_RD_KEY1_DATA2_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) -/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA2 0xFFFFFFFFU -#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA2_S 0 - -/** EFUSE_RD_KEY1_DATA3_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) -/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA3 0xFFFFFFFFU -#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA3_S 0 - -/** EFUSE_RD_KEY1_DATA4_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) -/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA4 0xFFFFFFFFU -#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA4_S 0 - -/** EFUSE_RD_KEY1_DATA5_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) -/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA5 0xFFFFFFFFU -#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA5_S 0 - -/** EFUSE_RD_KEY1_DATA6_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) -/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA6 0xFFFFFFFFU -#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA6_S 0 - -/** EFUSE_RD_KEY1_DATA7_REG register - * Register $n of BLOCK5 (KEY1). - */ -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) -/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ -#define EFUSE_KEY1_DATA7 0xFFFFFFFFU -#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA7_S 0 - -/** EFUSE_RD_KEY2_DATA0_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) -/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA0 0xFFFFFFFFU -#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA0_S 0 - -/** EFUSE_RD_KEY2_DATA1_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) -/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA1 0xFFFFFFFFU -#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA1_S 0 - -/** EFUSE_RD_KEY2_DATA2_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) -/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA2 0xFFFFFFFFU -#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA2_S 0 - -/** EFUSE_RD_KEY2_DATA3_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) -/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA3 0xFFFFFFFFU -#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA3_S 0 - -/** EFUSE_RD_KEY2_DATA4_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) -/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA4 0xFFFFFFFFU -#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA4_S 0 - -/** EFUSE_RD_KEY2_DATA5_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) -/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA5 0xFFFFFFFFU -#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA5_S 0 - -/** EFUSE_RD_KEY2_DATA6_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) -/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA6 0xFFFFFFFFU -#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA6_S 0 - -/** EFUSE_RD_KEY2_DATA7_REG register - * Register $n of BLOCK6 (KEY2). - */ -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) -/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ -#define EFUSE_KEY2_DATA7 0xFFFFFFFFU -#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA7_S 0 - -/** EFUSE_RD_KEY3_DATA0_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) -/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA0 0xFFFFFFFFU -#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA0_S 0 - -/** EFUSE_RD_KEY3_DATA1_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA1 0xFFFFFFFFU -#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA1_S 0 - -/** EFUSE_RD_KEY3_DATA2_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA2 0xFFFFFFFFU -#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA2_S 0 - -/** EFUSE_RD_KEY3_DATA3_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA3 0xFFFFFFFFU -#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA3_S 0 - -/** EFUSE_RD_KEY3_DATA4_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) -/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA4 0xFFFFFFFFU -#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA4_S 0 - -/** EFUSE_RD_KEY3_DATA5_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA5 0xFFFFFFFFU -#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA5_S 0 - -/** EFUSE_RD_KEY3_DATA6_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA6 0xFFFFFFFFU -#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA6_S 0 - -/** EFUSE_RD_KEY3_DATA7_REG register - * Register $n of BLOCK7 (KEY3). - */ -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ -#define EFUSE_KEY3_DATA7 0xFFFFFFFFU -#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA7_S 0 - -/** EFUSE_RD_KEY4_DATA0_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) -/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA0 0xFFFFFFFFU -#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA0_S 0 - -/** EFUSE_RD_KEY4_DATA1_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA1 0xFFFFFFFFU -#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA1_S 0 - -/** EFUSE_RD_KEY4_DATA2_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA2 0xFFFFFFFFU -#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA2_S 0 - -/** EFUSE_RD_KEY4_DATA3_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA3 0xFFFFFFFFU -#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA3_S 0 - -/** EFUSE_RD_KEY4_DATA4_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) -/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA4 0xFFFFFFFFU -#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA4_S 0 - -/** EFUSE_RD_KEY4_DATA5_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA5 0xFFFFFFFFU -#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA5_S 0 - -/** EFUSE_RD_KEY4_DATA6_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA6 0xFFFFFFFFU -#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA6_S 0 - -/** EFUSE_RD_KEY4_DATA7_REG register - * Register $n of BLOCK8 (KEY4). - */ -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ -#define EFUSE_KEY4_DATA7 0xFFFFFFFFU -#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA7_S 0 - -/** EFUSE_RD_KEY5_DATA0_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) -/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA0 0xFFFFFFFFU -#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA0_S 0 - -/** EFUSE_RD_KEY5_DATA1_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA1 0xFFFFFFFFU -#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA1_S 0 - -/** EFUSE_RD_KEY5_DATA2_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA2 0xFFFFFFFFU -#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA2_S 0 - -/** EFUSE_RD_KEY5_DATA3_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA3 0xFFFFFFFFU -#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA3_S 0 - -/** EFUSE_RD_KEY5_DATA4_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) -/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA4 0xFFFFFFFFU -#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA4_S 0 - -/** EFUSE_RD_KEY5_DATA5_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA5 0xFFFFFFFFU -#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA5_S 0 - -/** EFUSE_RD_KEY5_DATA6_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA6 0xFFFFFFFFU -#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA6_S 0 - -/** EFUSE_RD_KEY5_DATA7_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ -#define EFUSE_KEY5_DATA7 0xFFFFFFFFU -#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA7_S 0 - -/** EFUSE_RD_SYS_PART2_DATA0_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_S 0 - -/** EFUSE_RD_SYS_PART2_DATA1_REG register - * Register $n of BLOCK9 (KEY5). - */ -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_S 0 - -/** EFUSE_RD_SYS_PART2_DATA2_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_S 0 - -/** EFUSE_RD_SYS_PART2_DATA3_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_S 0 - -/** EFUSE_RD_SYS_PART2_DATA4_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) -/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_4_S 0 - -/** EFUSE_RD_SYS_PART2_DATA5_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_5_S 0 - -/** EFUSE_RD_SYS_PART2_DATA6_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_S 0 - -/** EFUSE_RD_SYS_PART2_DATA7_REG register - * Register $n of BLOCK10 (system). - */ -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_S 0 - -/** EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) -/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * If any bit in RD_DIS is 1, then it indicates a programming error. - */ -#define EFUSE_RD_DIS_ERR 0x0000007FU -#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) -#define EFUSE_RD_DIS_ERR_V 0x0000007FU -#define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_RPT4_RESERVED5_ERR : RO; bitpos: [7]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED5_ERR (BIT(7)) -#define EFUSE_RPT4_RESERVED5_ERR_M (EFUSE_RPT4_RESERVED5_ERR_V << EFUSE_RPT4_RESERVED5_ERR_S) -#define EFUSE_RPT4_RESERVED5_ERR_V 0x00000001U -#define EFUSE_RPT4_RESERVED5_ERR_S 7 -/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * If DIS_ICACHE is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) -#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U -#define EFUSE_DIS_ICACHE_ERR_S 8 -/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * If DIS_USB_JTAG is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; - * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [11]; default: 0; - * If DIS_USB_DEVICE is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(11)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001U -#define EFUSE_DIS_USB_DEVICE_ERR_S 11 -/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/** EFUSE_RPT4_RESERVED6_ERR : RO; bitpos: [13]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED6_ERR (BIT(13)) -#define EFUSE_RPT4_RESERVED6_ERR_M (EFUSE_RPT4_RESERVED6_ERR_V << EFUSE_RPT4_RESERVED6_ERR_S) -#define EFUSE_RPT4_RESERVED6_ERR_V 0x00000001U -#define EFUSE_RPT4_RESERVED6_ERR_S 13 -/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * If DIS_TWAI is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) -#define EFUSE_DIS_TWAI_ERR_V 0x00000001U -#define EFUSE_DIS_TWAI_ERR_S 14 -/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. - */ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * If SOFT_DIS_JTAG is 1, then it indicates a programming error. - */ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * If DIS_PAD_JTAG is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; - * If any bit in USB_DREFH is 1, then it indicates a programming error. - */ -#define EFUSE_USB_DREFH_ERR 0x00000003U -#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) -#define EFUSE_USB_DREFH_ERR_V 0x00000003U -#define EFUSE_USB_DREFH_ERR_S 21 -/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; - * If any bit in USB_DREFL is 1, then it indicates a programming error. - */ -#define EFUSE_USB_DREFL_ERR 0x00000003U -#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) -#define EFUSE_USB_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_DREFL_ERR_S 23 -/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * If USB_EXCHG_PINS is 1, then it indicates a programming error. - */ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; - * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. - */ -#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U -#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; - * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. - */ -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003U -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003U -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 -/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [29]; default: 0; - * If POWERGLITCH_EN is 1, then it indicates a programming error. - */ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(29)) -#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U -#define EFUSE_POWERGLITCH_EN_ERR_S 29 -/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [31:30]; default: 0; - * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. - */ -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003U -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003U -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 30 - -/** EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [15:0]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED2_ERR 0x0000FFFFU -#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) -#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000FFFFU -#define EFUSE_RPT4_RESERVED2_ERR_S 0 -/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. - */ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. - */ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. - */ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. - */ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 - -/** EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. - */ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 -/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. - */ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. - */ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. - */ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [19:16]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED3_ERR 0x0000000FU -#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) -#define EFUSE_RPT4_RESERVED3_ERR_V 0x0000000FU -#define EFUSE_RPT4_RESERVED3_ERR_S 16 -/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * If SECURE_BOOT_EN is 1, then it indicates a programming error. - */ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. - */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [27:22]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED0_ERR 0x0000003FU -#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000003FU -#define EFUSE_RPT4_RESERVED0_ERR_S 22 -/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * If any bit in FLASH_TPUM is 1, then it indicates a programming error. - */ -#define EFUSE_FLASH_TPUW_ERR 0x0000000FU -#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) -#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU -#define EFUSE_FLASH_TPUW_ERR_S 28 - -/** EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 -/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * If DIS_DIRECT_BOOT is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * If DIS_USB_SERIAL_JTAG_ROM_PRINT is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/** EFUSE_RPT4_RESERVED8_ERR : RO; bitpos: [3]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED8_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED8_ERR_M (EFUSE_RPT4_RESERVED8_ERR_V << EFUSE_RPT4_RESERVED8_ERR_S) -#define EFUSE_RPT4_RESERVED8_ERR_V 0x00000001U -#define EFUSE_RPT4_RESERVED8_ERR_S 3 -/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * If DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE is 1, then it indicates a programming error. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. - */ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. - */ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/** EFUSE_RPT4_RESERVED7_ERR : RO; bitpos: [12:8]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED7_ERR 0x0000001FU -#define EFUSE_RPT4_RESERVED7_ERR_M (EFUSE_RPT4_RESERVED7_ERR_V << EFUSE_RPT4_RESERVED7_ERR_S) -#define EFUSE_RPT4_RESERVED7_ERR_V 0x0000001FU -#define EFUSE_RPT4_RESERVED7_ERR_S 8 -/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; - * If FORCE_SEND_RESUME is 1, then it indicates a programming error. - */ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 -/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; - * If any bit in SECURE_VERSION is 1, then it indicates a programming error. - */ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU -#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU -#define EFUSE_SECURE_VERSION_ERR_S 14 -/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31:30]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED1_ERR 0x00000003U -#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000003U -#define EFUSE_RPT4_RESERVED1_ERR_S 30 - -/** EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. - */ -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) -/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; - * Reserved. - */ -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFFU -#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) -#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFFU -#define EFUSE_RPT4_RESERVED4_ERR_S 0 - -/** EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. - */ -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U -#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 -/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U -#define EFUSE_MAC_SPI_8M_FAIL_S 3 -/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_SYS_PART1_NUM 0x00000007U -#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) -#define EFUSE_SYS_PART1_NUM_V 0x00000007U -#define EFUSE_SYS_PART1_NUM_S 4 -/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001U -#define EFUSE_SYS_PART1_FAIL_S 7 -/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_USR_DATA_FAIL_S 11 -/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY0_ERR_NUM 0x00000007U -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007U -#define EFUSE_KEY0_ERR_NUM_S 12 -/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001U -#define EFUSE_KEY0_FAIL_S 15 -/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY1_ERR_NUM 0x00000007U -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007U -#define EFUSE_KEY1_ERR_NUM_S 16 -/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001U -#define EFUSE_KEY1_FAIL_S 19 -/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY2_ERR_NUM 0x00000007U -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007U -#define EFUSE_KEY2_ERR_NUM_S 20 -/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001U -#define EFUSE_KEY2_FAIL_S 23 -/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY3_ERR_NUM 0x00000007U -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007U -#define EFUSE_KEY3_ERR_NUM_S 24 -/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001U -#define EFUSE_KEY3_FAIL_S 27 -/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY4_ERR_NUM 0x00000007U -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007U -#define EFUSE_KEY4_ERR_NUM_S 28 -/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001U -#define EFUSE_KEY4_FAIL_S 31 - -/** EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. - */ -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY5_ERR_NUM 0x00000007U -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007U -#define EFUSE_KEY5_ERR_NUM_S 0 -/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001U -#define EFUSE_KEY5_FAIL_S 3 -/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001U -#define EFUSE_SYS_PART2_FAIL_S 7 - -/** EFUSE_CLK_REG register - * eFuse clcok configuration register. - */ -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) -/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) -#define EFUSE_MEM_FORCE_PD_V 0x00000001U -#define EFUSE_MEM_FORCE_PD_S 0 -/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U -#define EFUSE_MEM_CLK_FORCE_ON_S 1 -/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) -#define EFUSE_MEM_FORCE_PU_V 0x00000001U -#define EFUSE_MEM_FORCE_PU_S 2 -/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Set this bit and force to enable clock signal of eFuse memory. - */ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) -#define EFUSE_CLK_EN_V 0x00000001U -#define EFUSE_CLK_EN_S 16 - -#define EFUSE_WRITE_OP_CODE 0x5a5a -#define EFUSE_READ_OP_CODE 0x5aa5 - -/** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register - */ -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) -/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: Operate programming command 0x5AA5: Operate read command. - */ -#define EFUSE_OP_CODE 0x0000FFFFU -#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) -#define EFUSE_OP_CODE_V 0x0000FFFFU -#define EFUSE_OP_CODE_S 0 - -/** EFUSE_STATUS_REG register - * eFuse status register. - */ -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) -/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ -#define EFUSE_STATE 0x0000000FU -#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) -#define EFUSE_STATE_V 0x0000000FU -#define EFUSE_STATE_S 0 -/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) -#define EFUSE_OTP_LOAD_SW_V 0x00000001U -#define EFUSE_OTP_LOAD_SW_S 4 -/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) -#define EFUSE_OTP_STROBE_SW_V 0x00000001U -#define EFUSE_OTP_STROBE_SW_S 6 -/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) -#define EFUSE_OTP_CSB_SW_V 0x00000001U -#define EFUSE_OTP_CSB_SW_S 7 -/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) -#define EFUSE_OTP_PGENB_SW_V 0x00000001U -#define EFUSE_OTP_PGENB_SW_S 8 -/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; - * Indicates the number of error bits during programming BLOCK0. - */ -#define EFUSE_REPEAT_ERR_CNT 0x000000FFU -#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) -#define EFUSE_REPEAT_ERR_CNT_V 0x000000FFU -#define EFUSE_REPEAT_ERR_CNT_S 10 - -/** EFUSE_CMD_REG register - * eFuse command register. - */ -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) -/** EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) -#define EFUSE_READ_CMD_V 0x00000001U -#define EFUSE_READ_CMD_S 0 -/** EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) -#define EFUSE_PGM_CMD_V 0x00000001U -#define EFUSE_PGM_CMD_S 1 -/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ -#define EFUSE_BLK_NUM 0x0000000FU -#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) -#define EFUSE_BLK_NUM_V 0x0000000FU -#define EFUSE_BLK_NUM_S 2 - -/** EFUSE_INT_RAW_REG register - * eFuse raw interrupt register. - */ -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) -/** EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) -#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U -#define EFUSE_READ_DONE_INT_RAW_S 0 -/** EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) -#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/** EFUSE_INT_ST_REG register - * eFuse interrupt status register. - */ -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) -/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) -#define EFUSE_READ_DONE_INT_ST_V 0x00000001U -#define EFUSE_READ_DONE_INT_ST_S 0 -/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) -#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/** EFUSE_INT_ENA_REG register - * eFuse interrupt enable register. - */ -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) -/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) -#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U -#define EFUSE_READ_DONE_INT_ENA_S 0 -/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) -#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/** EFUSE_INT_CLR_REG register - * eFuse interrupt clear register. - */ -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) -/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) -#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U -#define EFUSE_READ_DONE_INT_CLR_S 0 -/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) -#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/** EFUSE_DAC_CONF_REG register - * Controls the eFuse programming voltage. - */ -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; - * Controls the division factor of the rising clock of the programming voltage. - */ -#define EFUSE_DAC_CLK_DIV 0x000000FFU -#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) -#define EFUSE_DAC_CLK_DIV_V 0x000000FFU -#define EFUSE_DAC_CLK_DIV_S 0 -/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; - * Don't care. - */ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ -#define EFUSE_DAC_NUM 0x000000FFU -#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) -#define EFUSE_DAC_NUM_V 0x000000FFU -#define EFUSE_DAC_NUM_S 9 -/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) -#define EFUSE_OE_CLR_V 0x00000001U -#define EFUSE_OE_CLR_S 17 - -/** EFUSE_RD_TIM_CONF_REG register - * Configures read timing parameters. - */ -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the initial read time of eFuse. - */ -#define EFUSE_READ_INIT_NUM 0x000000FFU -#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) -#define EFUSE_READ_INIT_NUM_V 0x000000FFU -#define EFUSE_READ_INIT_NUM_S 24 - -/** EFUSE_WR_TIM_CONF1_REG register - * Configurarion register 1 of eFuse programming timing parameters. - */ -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) -/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; - * Configures the power up time for VDDQ. - */ -#define EFUSE_PWR_ON_NUM 0x0000FFFFU -#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) -#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU -#define EFUSE_PWR_ON_NUM_S 8 - -/** EFUSE_WR_TIM_CONF2_REG register - * Configurarion register 2 of eFuse programming timing parameters. - */ -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) -/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ -#define EFUSE_PWR_OFF_NUM 0x0000FFFFU -#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) -#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU -#define EFUSE_PWR_OFF_NUM_S 0 - -/** EFUSE_DATE_REG register - * eFuse version register. - */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 33583616; - * Stores eFuse version. - */ -#define EFUSE_DATE 0x0FFFFFFFU -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0FFFFFFFU -#define EFUSE_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/efuse_struct.h b/components/soc/esp32h4/include/rev2/soc/efuse_struct.h deleted file mode 100644 index a01c154314..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/efuse_struct.h +++ /dev/null @@ -1,2177 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: PGM Data Register */ -/** Type of pgm_data0 register - * Register 0 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_0:32; - }; - uint32_t val; -} efuse_pgm_data0_reg_t; - -/** Type of pgm_data1 register - * Register 1 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit data to be programmed. - */ - uint32_t pgm_data_1:32; - }; - uint32_t val; -} efuse_pgm_data1_reg_t; - -/** Type of pgm_data2 register - * Register 2 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit data to be programmed. - */ - uint32_t pgm_data_2:32; - }; - uint32_t val; -} efuse_pgm_data2_reg_t; - -/** Type of pgm_data3 register - * Register 3 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * The content of the 3rd 32-bit data to be programmed. - */ - uint32_t pgm_data_3:32; - }; - uint32_t val; -} efuse_pgm_data3_reg_t; - -/** Type of pgm_data4 register - * Register 4 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * The content of the 4th 32-bit data to be programmed. - */ - uint32_t pgm_data_4:32; - }; - uint32_t val; -} efuse_pgm_data4_reg_t; - -/** Type of pgm_data5 register - * Register 5 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * The content of the 5th 32-bit data to be programmed. - */ - uint32_t pgm_data_5:32; - }; - uint32_t val; -} efuse_pgm_data5_reg_t; - -/** Type of pgm_data6 register - * Register 6 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * The content of the 6th 32-bit data to be programmed. - */ - uint32_t pgm_data_6:32; - }; - uint32_t val; -} efuse_pgm_data6_reg_t; - -/** Type of pgm_data7 register - * Register 7 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * The content of the 7th 32-bit data to be programmed. - */ - uint32_t pgm_data_7:32; - }; - uint32_t val; -} efuse_pgm_data7_reg_t; - -/** Type of pgm_check_value0 register - * Register 0 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_0:32; - }; - uint32_t val; -} efuse_pgm_check_value0_reg_t; - -/** Type of pgm_check_value1 register - * Register 1 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_1:32; - }; - uint32_t val; -} efuse_pgm_check_value1_reg_t; - -/** Type of pgm_check_value2 register - * Register 2 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_2:32; - }; - uint32_t val; -} efuse_pgm_check_value2_reg_t; - - -/** Group: ******** Registers */ -/** Type of rd_wr_dis register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** wr_dis : RO; bitpos: [31:0]; default: 0; - * The value of WR_DIS. - */ - uint32_t wr_dis:32; - }; - uint32_t val; -} efuse_rd_wr_dis_reg_t; - -/** Type of rd_repeat_data0 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** rd_dis : RO; bitpos: [6:0]; default: 0; - * The value of RD_DIS. - */ - uint32_t rd_dis:7; - /** rpt4_reserved5 : RO; bitpos: [7]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved5:1; - /** dis_icache : RO; bitpos: [8]; default: 0; - * The value of DIS_ICACHE. - */ - uint32_t dis_icache:1; - /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * The value of DIS_USB_JTAG. - */ - uint32_t dis_usb_jtag:1; - /** dis_download_icache : RO; bitpos: [10]; default: 0; - * The value of DIS_DOWNLOAD_ICACHE. - */ - uint32_t dis_download_icache:1; - /** dis_usb_device : RO; bitpos: [11]; default: 0; - * The value of DIS_USB_DEVICE. - */ - uint32_t dis_usb_device:1; - /** dis_force_download : RO; bitpos: [12]; default: 0; - * The value of DIS_FORCE_DOWNLOAD. - */ - uint32_t dis_force_download:1; - /** rpt4_reserved6 : RO; bitpos: [13]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved6:1; - /** dis_twai : RO; bitpos: [14]; default: 0; - * The value of DIS_TWAI. - */ - uint32_t dis_twai:1; - /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * The value of JTAG_SEL_ENABLE. - */ - uint32_t jtag_sel_enable:1; - /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * The value of SOFT_DIS_JTAG. - */ - uint32_t soft_dis_jtag:3; - /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * The value of DIS_PAD_JTAG. - */ - uint32_t dis_pad_jtag:1; - /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * The value of DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ - uint32_t dis_download_manual_encrypt:1; - /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * The value of USB_DREFH. - */ - uint32_t usb_drefh:2; - /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * The value of USB_DREFL. - */ - uint32_t usb_drefl:2; - /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * The value of USB_EXCHG_PINS. - */ - uint32_t usb_exchg_pins:1; - /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * The value of VDD_SPI_AS_GPIO. - */ - uint32_t vdd_spi_as_gpio:1; - /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; - * The value of BTLC_GPIO_ENABLE. - */ - uint32_t btlc_gpio_enable:2; - /** powerglitch_en : RO; bitpos: [29]; default: 0; - * The value of POWERGLITCH_EN. - */ - uint32_t powerglitch_en:1; - /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0; - * The value of POWER_GLITCH_DSENSE. - */ - uint32_t power_glitch_dsense:2; - }; - uint32_t val; -} efuse_rd_repeat_data0_reg_t; - -/** Type of rd_repeat_data1 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved2:16; - /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * The value of WDT_DELAY_SEL. - */ - uint32_t wdt_delay_sel:2; - /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * The value of SPI_BOOT_CRYPT_CNT. - */ - uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE0. - */ - uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE1. - */ - uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * The value of SECURE_BOOT_KEY_REVOKE2. - */ - uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * The value of KEY_PURPOSE_0. - */ - uint32_t key_purpose_0:4; - /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * The value of KEY_PURPOSE_1. - */ - uint32_t key_purpose_1:4; - }; - uint32_t val; -} efuse_rd_repeat_data1_reg_t; - -/** Type of rd_repeat_data2 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * The value of KEY_PURPOSE_2. - */ - uint32_t key_purpose_2:4; - /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * The value of KEY_PURPOSE_3. - */ - uint32_t key_purpose_3:4; - /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * The value of KEY_PURPOSE_4. - */ - uint32_t key_purpose_4:4; - /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * The value of KEY_PURPOSE_5. - */ - uint32_t key_purpose_5:4; - /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved3:4; - /** secure_boot_en : RO; bitpos: [20]; default: 0; - * The value of SECURE_BOOT_EN. - */ - uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * The value of SECURE_BOOT_AGGRESSIVE_REVOKE. - */ - uint32_t secure_boot_aggressive_revoke:1; - /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved0:6; - /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * The value of FLASH_TPUW. - */ - uint32_t flash_tpuw:4; - }; - uint32_t val; -} efuse_rd_repeat_data2_reg_t; - -/** Type of rd_repeat_data3 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** dis_download_mode : RO; bitpos: [0]; default: 0; - * The value of DIS_DOWNLOAD_MODE. - */ - uint32_t dis_download_mode:1; - /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * The value of DIS_DIRECT_BOOT. - */ - uint32_t dis_direct_boot:1; - /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * The value of DIS_USB_SERIAL_JTAG_ROM_PRINT. - */ - uint32_t dis_usb_serial_jtag_rom_print:1; - /** rpt4_reserved8 : RO; bitpos: [3]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved8:1; - /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * The value of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. - */ - uint32_t dis_usb_serial_jtag_download_mode:1; - /** enable_security_download : RO; bitpos: [5]; default: 0; - * The value of ENABLE_SECURITY_DOWNLOAD. - */ - uint32_t enable_security_download:1; - /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * The value of UART_PRINT_CONTROL. - */ - uint32_t uart_print_control:2; - /** rpt4_reserved7 : RO; bitpos: [12:8]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved7:5; - /** force_send_resume : RO; bitpos: [13]; default: 0; - * The value of FORCE_SEND_RESUME. - */ - uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [29:14]; default: 0; - * The value of SECURE_VERSION. - */ - uint32_t secure_version:16; - /** rpt4_reserved1 : RO; bitpos: [31:30]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved1:2; - }; - uint32_t val; -} efuse_rd_repeat_data3_reg_t; - -/** Type of rd_repeat_data4 register - * BLOCK0 data register $n. - */ -typedef union { - struct { - /** rpt4_reserved4 : RO; bitpos: [23:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved4:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_rd_repeat_data4_reg_t; - -/** Type of rd_mac_spi_sys_0 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ - uint32_t mac_0:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_0_reg_t; - -/** Type of rd_mac_spi_sys_1 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ - uint32_t mac_1:16; - /** spi_pad_conf_0 : RO; bitpos: [31:16]; default: 0; - * Stores the zeroth part of SPI_PAD_CONF. - */ - uint32_t spi_pad_conf_0:16; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_1_reg_t; - -/** Type of rd_mac_spi_sys_2 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** spi_pad_conf_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first part of SPI_PAD_CONF. - */ - uint32_t spi_pad_conf_1:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_2_reg_t; - -/** Type of rd_mac_spi_sys_3 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0; - * Stores the second part of SPI_PAD_CONF. - */ - uint32_t spi_pad_conf_2:18; - uint32_t wafer_version:3; - uint32_t pkg_version:3; - uint32_t sys_data_part0_0:8; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_3_reg_t; - -/** Type of rd_mac_spi_sys_4 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the fist 32 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_1:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_4_reg_t; - -/** Type of rd_mac_spi_sys_5 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. - */ - uint32_t sys_data_part0_2:32; - }; - uint32_t val; -} efuse_rd_mac_spi_sys_5_reg_t; - -/** Type of rd_sys_part1_data0 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_0:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data0_reg_t; - -/** Type of rd_sys_part1_data1 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_1:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data1_reg_t; - -/** Type of rd_sys_part1_data2 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_2:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data2_reg_t; - -/** Type of rd_sys_part1_data3 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_3:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data3_reg_t; - -/** Type of rd_sys_part1_data4 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_4:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data4_reg_t; - -/** Type of rd_sys_part1_data5 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_5:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data5_reg_t; - -/** Type of rd_sys_part1_data6 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_6:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data6_reg_t; - -/** Type of rd_sys_part1_data7 register - * Register $n of BLOCK2 (system). - */ -typedef union { - struct { - /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. - */ - uint32_t sys_data_part1_7:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data7_reg_t; - -/** Type of rd_usr_data0 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data0:32; - }; - uint32_t val; -} efuse_rd_usr_data0_reg_t; - -/** Type of rd_usr_data1 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ - uint32_t usr_data1:32; - }; - uint32_t val; -} efuse_rd_usr_data1_reg_t; - -/** Type of rd_usr_data2 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ - uint32_t usr_data2:32; - }; - uint32_t val; -} efuse_rd_usr_data2_reg_t; - -/** Type of rd_usr_data3 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ - uint32_t usr_data3:32; - }; - uint32_t val; -} efuse_rd_usr_data3_reg_t; - -/** Type of rd_usr_data4 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data4:32; - }; - uint32_t val; -} efuse_rd_usr_data4_reg_t; - -/** Type of rd_usr_data5 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data5:32; - }; - uint32_t val; -} efuse_rd_usr_data5_reg_t; - -/** Type of rd_usr_data6 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). - */ - uint32_t usr_data6:32; - }; - uint32_t val; -} efuse_rd_usr_data6_reg_t; - -/** Type of rd_usr_data7 register - * Register $n of BLOCK3 (user). - */ -typedef union { - struct { - /** usr_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). - */ - uint32_t usr_data7:32; - }; - uint32_t val; -} efuse_rd_usr_data7_reg_t; - -/** Type of rd_key0_data0 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ - uint32_t key0_data0:32; - }; - uint32_t val; -} efuse_rd_key0_data0_reg_t; - -/** Type of rd_key0_data1 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. - */ - uint32_t key0_data1:32; - }; - uint32_t val; -} efuse_rd_key0_data1_reg_t; - -/** Type of rd_key0_data2 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ - uint32_t key0_data2:32; - }; - uint32_t val; -} efuse_rd_key0_data2_reg_t; - -/** Type of rd_key0_data3 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. - */ - uint32_t key0_data3:32; - }; - uint32_t val; -} efuse_rd_key0_data3_reg_t; - -/** Type of rd_key0_data4 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ - uint32_t key0_data4:32; - }; - uint32_t val; -} efuse_rd_key0_data4_reg_t; - -/** Type of rd_key0_data5 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. - */ - uint32_t key0_data5:32; - }; - uint32_t val; -} efuse_rd_key0_data5_reg_t; - -/** Type of rd_key0_data6 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ - uint32_t key0_data6:32; - }; - uint32_t val; -} efuse_rd_key0_data6_reg_t; - -/** Type of rd_key0_data7 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ - uint32_t key0_data7:32; - }; - uint32_t val; -} efuse_rd_key0_data7_reg_t; - -/** Type of rd_key1_data0 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ - uint32_t key1_data0:32; - }; - uint32_t val; -} efuse_rd_key1_data0_reg_t; - -/** Type of rd_key1_data1 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ - uint32_t key1_data1:32; - }; - uint32_t val; -} efuse_rd_key1_data1_reg_t; - -/** Type of rd_key1_data2 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ - uint32_t key1_data2:32; - }; - uint32_t val; -} efuse_rd_key1_data2_reg_t; - -/** Type of rd_key1_data3 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ - uint32_t key1_data3:32; - }; - uint32_t val; -} efuse_rd_key1_data3_reg_t; - -/** Type of rd_key1_data4 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ - uint32_t key1_data4:32; - }; - uint32_t val; -} efuse_rd_key1_data4_reg_t; - -/** Type of rd_key1_data5 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ - uint32_t key1_data5:32; - }; - uint32_t val; -} efuse_rd_key1_data5_reg_t; - -/** Type of rd_key1_data6 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ - uint32_t key1_data6:32; - }; - uint32_t val; -} efuse_rd_key1_data6_reg_t; - -/** Type of rd_key1_data7 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ - uint32_t key1_data7:32; - }; - uint32_t val; -} efuse_rd_key1_data7_reg_t; - -/** Type of rd_key2_data0 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ - uint32_t key2_data0:32; - }; - uint32_t val; -} efuse_rd_key2_data0_reg_t; - -/** Type of rd_key2_data1 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ - uint32_t key2_data1:32; - }; - uint32_t val; -} efuse_rd_key2_data1_reg_t; - -/** Type of rd_key2_data2 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ - uint32_t key2_data2:32; - }; - uint32_t val; -} efuse_rd_key2_data2_reg_t; - -/** Type of rd_key2_data3 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ - uint32_t key2_data3:32; - }; - uint32_t val; -} efuse_rd_key2_data3_reg_t; - -/** Type of rd_key2_data4 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ - uint32_t key2_data4:32; - }; - uint32_t val; -} efuse_rd_key2_data4_reg_t; - -/** Type of rd_key2_data5 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ - uint32_t key2_data5:32; - }; - uint32_t val; -} efuse_rd_key2_data5_reg_t; - -/** Type of rd_key2_data6 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ - uint32_t key2_data6:32; - }; - uint32_t val; -} efuse_rd_key2_data6_reg_t; - -/** Type of rd_key2_data7 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ - uint32_t key2_data7:32; - }; - uint32_t val; -} efuse_rd_key2_data7_reg_t; - -/** Type of rd_key3_data0 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ - uint32_t key3_data0:32; - }; - uint32_t val; -} efuse_rd_key3_data0_reg_t; - -/** Type of rd_key3_data1 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ - uint32_t key3_data1:32; - }; - uint32_t val; -} efuse_rd_key3_data1_reg_t; - -/** Type of rd_key3_data2 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ - uint32_t key3_data2:32; - }; - uint32_t val; -} efuse_rd_key3_data2_reg_t; - -/** Type of rd_key3_data3 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ - uint32_t key3_data3:32; - }; - uint32_t val; -} efuse_rd_key3_data3_reg_t; - -/** Type of rd_key3_data4 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ - uint32_t key3_data4:32; - }; - uint32_t val; -} efuse_rd_key3_data4_reg_t; - -/** Type of rd_key3_data5 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ - uint32_t key3_data5:32; - }; - uint32_t val; -} efuse_rd_key3_data5_reg_t; - -/** Type of rd_key3_data6 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ - uint32_t key3_data6:32; - }; - uint32_t val; -} efuse_rd_key3_data6_reg_t; - -/** Type of rd_key3_data7 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ - uint32_t key3_data7:32; - }; - uint32_t val; -} efuse_rd_key3_data7_reg_t; - -/** Type of rd_key4_data0 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ - uint32_t key4_data0:32; - }; - uint32_t val; -} efuse_rd_key4_data0_reg_t; - -/** Type of rd_key4_data1 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ - uint32_t key4_data1:32; - }; - uint32_t val; -} efuse_rd_key4_data1_reg_t; - -/** Type of rd_key4_data2 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ - uint32_t key4_data2:32; - }; - uint32_t val; -} efuse_rd_key4_data2_reg_t; - -/** Type of rd_key4_data3 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ - uint32_t key4_data3:32; - }; - uint32_t val; -} efuse_rd_key4_data3_reg_t; - -/** Type of rd_key4_data4 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ - uint32_t key4_data4:32; - }; - uint32_t val; -} efuse_rd_key4_data4_reg_t; - -/** Type of rd_key4_data5 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ - uint32_t key4_data5:32; - }; - uint32_t val; -} efuse_rd_key4_data5_reg_t; - -/** Type of rd_key4_data6 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ - uint32_t key4_data6:32; - }; - uint32_t val; -} efuse_rd_key4_data6_reg_t; - -/** Type of rd_key4_data7 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ - uint32_t key4_data7:32; - }; - uint32_t val; -} efuse_rd_key4_data7_reg_t; - -/** Type of rd_key5_data0 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ - uint32_t key5_data0:32; - }; - uint32_t val; -} efuse_rd_key5_data0_reg_t; - -/** Type of rd_key5_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ - uint32_t key5_data1:32; - }; - uint32_t val; -} efuse_rd_key5_data1_reg_t; - -/** Type of rd_key5_data2 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ - uint32_t key5_data2:32; - }; - uint32_t val; -} efuse_rd_key5_data2_reg_t; - -/** Type of rd_key5_data3 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ - uint32_t key5_data3:32; - }; - uint32_t val; -} efuse_rd_key5_data3_reg_t; - -/** Type of rd_key5_data4 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ - uint32_t key5_data4:32; - }; - uint32_t val; -} efuse_rd_key5_data4_reg_t; - -/** Type of rd_key5_data5 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ - uint32_t key5_data5:32; - }; - uint32_t val; -} efuse_rd_key5_data5_reg_t; - -/** Type of rd_key5_data6 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ - uint32_t key5_data6:32; - }; - uint32_t val; -} efuse_rd_key5_data6_reg_t; - -/** Type of rd_key5_data7 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ - uint32_t key5_data7:32; - }; - uint32_t val; -} efuse_rd_key5_data7_reg_t; - -/** Type of rd_sys_part2_data0 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_0:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data0_reg_t; - -/** Type of rd_sys_part2_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_1:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data1_reg_t; - -/** Type of rd_sys_part2_data2 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_2:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data2_reg_t; - -/** Type of rd_sys_part2_data3 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_3:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data3_reg_t; - -/** Type of rd_sys_part2_data4 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_4:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data4_reg_t; - -/** Type of rd_sys_part2_data5 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_5:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data5_reg_t; - -/** Type of rd_sys_part2_data6 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_6:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data6_reg_t; - -/** Type of rd_sys_part2_data7 register - * Register $n of BLOCK10 (system). - */ -typedef union { - struct { - /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. - */ - uint32_t sys_data_part2_7:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data7_reg_t; - -/** Type of rd_repeat_err0 register - * Programming error record register 0 of BLOCK0. - */ -typedef union { - struct { - /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * If any bit in RD_DIS is 1, then it indicates a programming error. - */ - uint32_t rd_dis_err:7; - /** rpt4_reserved5_err : RO; bitpos: [7]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved5_err:1; - /** dis_icache_err : RO; bitpos: [8]; default: 0; - * If DIS_ICACHE is 1, then it indicates a programming error. - */ - uint32_t dis_icache_err:1; - /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * If DIS_USB_JTAG is 1, then it indicates a programming error. - */ - uint32_t dis_usb_jtag_err:1; - /** dis_download_icache_err : RO; bitpos: [10]; default: 0; - * If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. - */ - uint32_t dis_download_icache_err:1; - /** dis_usb_device_err : RO; bitpos: [11]; default: 0; - * If DIS_USB_DEVICE is 1, then it indicates a programming error. - */ - uint32_t dis_usb_device_err:1; - /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. - */ - uint32_t dis_force_download_err:1; - /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved6_err:1; - /** dis_twai_err : RO; bitpos: [14]; default: 0; - * If DIS_TWAI is 1, then it indicates a programming error. - */ - uint32_t dis_twai_err:1; - /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * If JTAG_SEL_ENABLE is 1, then it indicates a programming error. - */ - uint32_t jtag_sel_enable_err:1; - /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * If SOFT_DIS_JTAG is 1, then it indicates a programming error. - */ - uint32_t soft_dis_jtag_err:3; - /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * If DIS_PAD_JTAG is 1, then it indicates a programming error. - */ - uint32_t dis_pad_jtag_err:1; - /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. - */ - uint32_t dis_download_manual_encrypt_err:1; - /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; - * If any bit in USB_DREFH is 1, then it indicates a programming error. - */ - uint32_t usb_drefh_err:2; - /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; - * If any bit in USB_DREFL is 1, then it indicates a programming error. - */ - uint32_t usb_drefl_err:2; - /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * If USB_EXCHG_PINS is 1, then it indicates a programming error. - */ - uint32_t usb_exchg_pins_err:1; - /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. - */ - uint32_t vdd_spi_as_gpio_err:1; - /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; - * If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. - */ - uint32_t btlc_gpio_enable_err:2; - /** powerglitch_en_err : RO; bitpos: [29]; default: 0; - * If POWERGLITCH_EN is 1, then it indicates a programming error. - */ - uint32_t powerglitch_en_err:1; - /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0; - * If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. - */ - uint32_t power_glitch_dsense_err:2; - }; - uint32_t val; -} efuse_rd_repeat_err0_reg_t; - -/** Type of rd_repeat_err1 register - * Programming error record register 1 of BLOCK0. - */ -typedef union { - struct { - /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved2_err:16; - /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. - */ - uint32_t wdt_delay_sel_err:2; - /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. - */ - uint32_t spi_boot_crypt_cnt_err:3; - /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. - */ - uint32_t secure_boot_key_revoke0_err:1; - /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. - */ - uint32_t secure_boot_key_revoke1_err:1; - /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. - */ - uint32_t secure_boot_key_revoke2_err:1; - /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_0_err:4; - /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_1_err:4; - }; - uint32_t val; -} efuse_rd_repeat_err1_reg_t; - -/** Type of rd_repeat_err2 register - * Programming error record register 2 of BLOCK0. - */ -typedef union { - struct { - /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_2_err:4; - /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_3_err:4; - /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_4_err:4; - /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. - */ - uint32_t key_purpose_5_err:4; - /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved3_err:4; - /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * If SECURE_BOOT_EN is 1, then it indicates a programming error. - */ - uint32_t secure_boot_en_err:1; - /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. - */ - uint32_t secure_boot_aggressive_revoke_err:1; - /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved0_err:6; - /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * If any bit in FLASH_TPUM is 1, then it indicates a programming error. - */ - uint32_t flash_tpuw_err:4; - }; - uint32_t val; -} efuse_rd_repeat_err2_reg_t; - -/** Type of rd_repeat_err3 register - * Programming error record register 3 of BLOCK0. - */ -typedef union { - struct { - /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. - */ - uint32_t dis_download_mode_err:1; - /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * If DIS_DIRECT_BOOT is 1, then it indicates a programming error. - */ - uint32_t dis_direct_boot_err:1; - /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * If DIS_USB_SERIAL_JTAG_ROM_PRINT is 1, then it indicates a programming error. - */ - uint32_t dis_usb_serial_jtag_rom_print_err:1; - /** rpt4_reserved8_err : RO; bitpos: [3]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved8_err:1; - /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * If DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE is 1, then it indicates a programming error. - */ - uint32_t dis_usb_serial_jtag_download_mode_err:1; - /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. - */ - uint32_t enable_security_download_err:1; - /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. - */ - uint32_t uart_print_control_err:2; - /** rpt4_reserved7 : RO; bitpos: [12:8]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved7:5; - /** force_send_resume_err : RO; bitpos: [13]; default: 0; - * If FORCE_SEND_RESUME is 1, then it indicates a programming error. - */ - uint32_t force_send_resume_err:1; - /** secure_version_err : RO; bitpos: [29:14]; default: 0; - * If any bit in SECURE_VERSION is 1, then it indicates a programming error. - */ - uint32_t secure_version_err:16; - /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved1_err:2; - }; - uint32_t val; -} efuse_rd_repeat_err3_reg_t; - -/** Type of rd_repeat_err4 register - * Programming error record register 4 of BLOCK0. - */ -typedef union { - struct { - /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; - * Reserved. - */ - uint32_t rpt4_reserved4_err:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_rd_repeat_err4_reg_t; - -/** Type of rd_rs_err0 register - * Programming error record register 0 of BLOCK1-10. - */ -typedef union { - struct { - /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t mac_spi_8m_err_num:3; - /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t mac_spi_8m_fail:1; - /** sys_part1_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t sys_part1_num:3; - /** sys_part1_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t sys_part1_fail:1; - /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t usr_data_err_num:3; - /** usr_data_fail : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ - uint32_t usr_data_fail:1; - /** key0_err_num : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key0_err_num:3; - /** key0_fail : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key0_fail:1; - /** key1_err_num : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key1_err_num:3; - /** key1_fail : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key1_fail:1; - /** key2_err_num : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key2_err_num:3; - /** key2_fail : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key2_fail:1; - /** key3_err_num : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key3_err_num:3; - /** key3_fail : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key3_fail:1; - /** key4_err_num : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key4_err_num:3; - /** key4_fail : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key$n is reliable 1: Means that - * programming key$n failed and the number of error bytes is over 6. - */ - uint32_t key4_fail:1; - }; - uint32_t val; -} efuse_rd_rs_err0_reg_t; - -/** Type of rd_rs_err1 register - * Programming error record register 1 of BLOCK1-10. - */ -typedef union { - struct { - /** key5_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key5_err_num:3; - /** key5_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ - uint32_t key5_fail:1; - /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t sys_part2_err_num:3; - /** sys_part2_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - uint32_t sys_part2_fail:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} efuse_rd_rs_err1_reg_t; - -/** Type of clk register - * eFuse clcok configuration register. - */ -typedef union { - struct { - /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ - uint32_t mem_force_pd:1; - /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ - uint32_t mem_clk_force_on:1; - /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ - uint32_t mem_force_pu:1; - uint32_t reserved_3:13; - /** clk_en : R/W; bitpos: [16]; default: 0; - * Set this bit and force to enable clock signal of eFuse memory. - */ - uint32_t clk_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} efuse_clk_reg_t; - -/** Type of conf register - * eFuse operation mode configuraiton register - */ -typedef union { - struct { - /** op_code : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: Operate programming command 0x5AA5: Operate read command. - */ - uint32_t op_code:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_conf_reg_t; - -/** Type of status register - * eFuse status register. - */ -typedef union { - struct { - /** state : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - uint32_t state:4; - /** otp_load_sw : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ - uint32_t otp_load_sw:1; - /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ - uint32_t otp_vddq_c_sync2:1; - /** otp_strobe_sw : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ - uint32_t otp_strobe_sw:1; - /** otp_csb_sw : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ - uint32_t otp_csb_sw:1; - /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ - uint32_t otp_pgenb_sw:1; - /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ - uint32_t otp_vddq_is_sw:1; - /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; - * Indicates the number of error bits during programming BLOCK0. - */ - uint32_t repeat_err_cnt:8; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_status_reg_t; - -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - -/** Type of int_raw register - * eFuse raw interrupt register. - */ -typedef union { - struct { - /** read_done_int_raw : RO; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - uint32_t read_done_int_raw:1; - /** pgm_done_int_raw : RO; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_raw_reg_t; - -/** Type of int_st register - * eFuse interrupt status register. - */ -typedef union { - struct { - /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - uint32_t read_done_int_st:1; - /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_st_reg_t; - -/** Type of int_ena register - * eFuse interrupt enable register. - */ -typedef union { - struct { - /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - uint32_t read_done_int_ena:1; - /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_ena_reg_t; - -/** Type of int_clr register - * eFuse interrupt clear register. - */ -typedef union { - struct { - /** read_done_int_clr : WO; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - uint32_t read_done_int_clr:1; - /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_clr_reg_t; - -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the initial read time of eFuse. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 33583616; - * Stores eFuse version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - -typedef struct { - volatile efuse_pgm_data0_reg_t pgm_data0; - volatile efuse_pgm_data1_reg_t pgm_data1; - volatile efuse_pgm_data2_reg_t pgm_data2; - volatile efuse_pgm_data3_reg_t pgm_data3; - volatile efuse_pgm_data4_reg_t pgm_data4; - volatile efuse_pgm_data5_reg_t pgm_data5; - volatile efuse_pgm_data6_reg_t pgm_data6; - volatile efuse_pgm_data7_reg_t pgm_data7; - volatile efuse_pgm_check_value0_reg_t pgm_check_value0; - volatile efuse_pgm_check_value1_reg_t pgm_check_value1; - volatile efuse_pgm_check_value2_reg_t pgm_check_value2; - volatile efuse_rd_wr_dis_reg_t rd_wr_dis; - volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; - volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; - volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; - volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; - volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; - volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; - volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; - volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; - volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; - volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; - volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; - volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; - volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; - volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; - volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; - volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; - volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; - volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; - volatile efuse_rd_usr_data0_reg_t rd_usr_data0; - volatile efuse_rd_usr_data1_reg_t rd_usr_data1; - volatile efuse_rd_usr_data2_reg_t rd_usr_data2; - volatile efuse_rd_usr_data3_reg_t rd_usr_data3; - volatile efuse_rd_usr_data4_reg_t rd_usr_data4; - volatile efuse_rd_usr_data5_reg_t rd_usr_data5; - volatile efuse_rd_usr_data6_reg_t rd_usr_data6; - volatile efuse_rd_usr_data7_reg_t rd_usr_data7; - volatile efuse_rd_key0_data0_reg_t rd_key0_data0; - volatile efuse_rd_key0_data1_reg_t rd_key0_data1; - volatile efuse_rd_key0_data2_reg_t rd_key0_data2; - volatile efuse_rd_key0_data3_reg_t rd_key0_data3; - volatile efuse_rd_key0_data4_reg_t rd_key0_data4; - volatile efuse_rd_key0_data5_reg_t rd_key0_data5; - volatile efuse_rd_key0_data6_reg_t rd_key0_data6; - volatile efuse_rd_key0_data7_reg_t rd_key0_data7; - volatile efuse_rd_key1_data0_reg_t rd_key1_data0; - volatile efuse_rd_key1_data1_reg_t rd_key1_data1; - volatile efuse_rd_key1_data2_reg_t rd_key1_data2; - volatile efuse_rd_key1_data3_reg_t rd_key1_data3; - volatile efuse_rd_key1_data4_reg_t rd_key1_data4; - volatile efuse_rd_key1_data5_reg_t rd_key1_data5; - volatile efuse_rd_key1_data6_reg_t rd_key1_data6; - volatile efuse_rd_key1_data7_reg_t rd_key1_data7; - volatile efuse_rd_key2_data0_reg_t rd_key2_data0; - volatile efuse_rd_key2_data1_reg_t rd_key2_data1; - volatile efuse_rd_key2_data2_reg_t rd_key2_data2; - volatile efuse_rd_key2_data3_reg_t rd_key2_data3; - volatile efuse_rd_key2_data4_reg_t rd_key2_data4; - volatile efuse_rd_key2_data5_reg_t rd_key2_data5; - volatile efuse_rd_key2_data6_reg_t rd_key2_data6; - volatile efuse_rd_key2_data7_reg_t rd_key2_data7; - volatile efuse_rd_key3_data0_reg_t rd_key3_data0; - volatile efuse_rd_key3_data1_reg_t rd_key3_data1; - volatile efuse_rd_key3_data2_reg_t rd_key3_data2; - volatile efuse_rd_key3_data3_reg_t rd_key3_data3; - volatile efuse_rd_key3_data4_reg_t rd_key3_data4; - volatile efuse_rd_key3_data5_reg_t rd_key3_data5; - volatile efuse_rd_key3_data6_reg_t rd_key3_data6; - volatile efuse_rd_key3_data7_reg_t rd_key3_data7; - volatile efuse_rd_key4_data0_reg_t rd_key4_data0; - volatile efuse_rd_key4_data1_reg_t rd_key4_data1; - volatile efuse_rd_key4_data2_reg_t rd_key4_data2; - volatile efuse_rd_key4_data3_reg_t rd_key4_data3; - volatile efuse_rd_key4_data4_reg_t rd_key4_data4; - volatile efuse_rd_key4_data5_reg_t rd_key4_data5; - volatile efuse_rd_key4_data6_reg_t rd_key4_data6; - volatile efuse_rd_key4_data7_reg_t rd_key4_data7; - volatile efuse_rd_key5_data0_reg_t rd_key5_data0; - volatile efuse_rd_key5_data1_reg_t rd_key5_data1; - volatile efuse_rd_key5_data2_reg_t rd_key5_data2; - volatile efuse_rd_key5_data3_reg_t rd_key5_data3; - volatile efuse_rd_key5_data4_reg_t rd_key5_data4; - volatile efuse_rd_key5_data5_reg_t rd_key5_data5; - volatile efuse_rd_key5_data6_reg_t rd_key5_data6; - volatile efuse_rd_key5_data7_reg_t rd_key5_data7; - volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; - volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; - volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; - volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; - volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; - volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; - volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; - volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; - volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; - volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; - volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; - uint32_t reserved_18c; - volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; - uint32_t reserved_194[11]; - volatile efuse_rd_rs_err0_reg_t rd_rs_err0; - volatile efuse_rd_rs_err1_reg_t rd_rs_err1; - volatile efuse_clk_reg_t clk; - volatile efuse_conf_reg_t conf; - volatile efuse_status_reg_t status; - volatile efuse_cmd_reg_t cmd; - volatile efuse_int_raw_reg_t int_raw; - volatile efuse_int_st_reg_t int_st; - volatile efuse_int_ena_reg_t int_ena; - volatile efuse_int_clr_reg_t int_clr; - volatile efuse_dac_conf_reg_t dac_conf; - volatile efuse_rd_tim_conf_reg_t rd_tim_conf; - volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; - volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; - uint32_t reserved_1f8; - volatile efuse_date_reg_t date; -} efuse_dev_t; - -extern efuse_dev_t EFUSE; - -#ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/gpio_reg.h b/components/soc/esp32h4/include/rev2/soc/gpio_reg.h deleted file mode 100644 index b49e876545..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/gpio_reg.h +++ /dev/null @@ -1,6583 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_GPIO_REG_H_ -#define _SOC_GPIO_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define GPIO_PIN_CONFIG_MSB 12 -#define GPIO_PIN_CONFIG_LSB 11 -#define GPIO_PIN_CONFIG_MASK 0x00001800 -#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) -#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) - -#define GPIO_WAKEUP_ENABLE 1 -#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) -#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 -#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) -#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) - -#define GPIO_PIN_INT_TYPE_MASK 0x380 -#define GPIO_PIN_INT_TYPE_MSB 9 -#define GPIO_PIN_INT_TYPE_LSB 7 -#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) - -#define GPIO_PAD_DRIVER_ENABLE 1 -#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) -#define GPIO_PIN_PAD_DRIVER_MSB 2 -#define GPIO_PIN_PAD_DRIVER_LSB 2 -#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 -#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) -#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) - -/** GPIO_BT_SELECT_REG register - * GPIO bit select register - */ -#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) -/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; - * GPIO bit select register - */ -#define GPIO_BT_SEL 0xFFFFFFFFU -#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) -#define GPIO_BT_SEL_V 0xFFFFFFFFU -#define GPIO_BT_SEL_S 0 - -/** GPIO_OUT_REG register - * GPIO output register for GPIO0-29 - */ -#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/** GPIO_OUT_DATA_ORIG : R/W/WS/WC; bitpos: [29:0]; default: 0; - * GPIO output register for GPIO0-29 - */ -#define GPIO_OUT_DATA_ORIG 0x3FFFFFFFU -#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) -#define GPIO_OUT_DATA_ORIG_V 0x3FFFFFFFU -#define GPIO_OUT_DATA_ORIG_S 0 - -/** GPIO_OUT_W1TS_REG register - * GPIO output set register for GPIO0-29 - */ -#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/** GPIO_OUT_W1TS : WT; bitpos: [29:0]; default: 0; - * GPIO output set register for GPIO0-29 - */ -#define GPIO_OUT_W1TS 0x3FFFFFFFU -#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) -#define GPIO_OUT_W1TS_V 0x3FFFFFFFU -#define GPIO_OUT_W1TS_S 0 - -/** GPIO_OUT_W1TC_REG register - * GPIO output clear register for GPIO0-29 - */ -#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) -/** GPIO_OUT_W1TC : WT; bitpos: [29:0]; default: 0; - * GPIO output clear register for GPIO0-29 - */ -#define GPIO_OUT_W1TC 0x3FFFFFFFU -#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) -#define GPIO_OUT_W1TC_V 0x3FFFFFFFU -#define GPIO_OUT_W1TC_S 0 - -/** GPIO_SDIO_SELECT_REG register - * GPIO sdio select register - */ -#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) -/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; - * GPIO sdio select register - */ -#define GPIO_SDIO_SEL 0x000000FFU -#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) -#define GPIO_SDIO_SEL_V 0x000000FFU -#define GPIO_SDIO_SEL_S 0 - -/** GPIO_ENABLE_REG register - * GPIO output enable register for GPIO0-29 - */ -#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) -/** GPIO_ENABLE_DATA : R/W/SS; bitpos: [29:0]; default: 0; - * GPIO output enable register for GPIO0-29 - */ -#define GPIO_ENABLE_DATA 0x3FFFFFFFU -#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) -#define GPIO_ENABLE_DATA_V 0x3FFFFFFFU -#define GPIO_ENABLE_DATA_S 0 - -/** GPIO_ENABLE_W1TS_REG register - * GPIO output enable set register for GPIO0-29 - */ -#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) -/** GPIO_ENABLE_W1TS : WT; bitpos: [29:0]; default: 0; - * GPIO output enable set register for GPIO0-29 - */ -#define GPIO_ENABLE_W1TS 0x3FFFFFFFU -#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) -#define GPIO_ENABLE_W1TS_V 0x3FFFFFFFU -#define GPIO_ENABLE_W1TS_S 0 - -/** GPIO_ENABLE_W1TC_REG register - * GPIO output enable clear register for GPIO0-29 - */ -#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) -/** GPIO_ENABLE_W1TC : WT; bitpos: [29:0]; default: 0; - * GPIO output enable clear register for GPIO0-29 - */ -#define GPIO_ENABLE_W1TC 0x3FFFFFFFU -#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) -#define GPIO_ENABLE_W1TC_V 0x3FFFFFFFU -#define GPIO_ENABLE_W1TC_S 0 - -/** GPIO_STRAP_REG register - * pad strapping register - */ -#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) -/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; - * pad strapping register - */ -#define GPIO_STRAPPING 0x0000FFFFU -#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) -#define GPIO_STRAPPING_V 0x0000FFFFU -#define GPIO_STRAPPING_S 0 - -/** GPIO_IN_REG register - * GPIO input register for GPIO0-29 - */ -#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) -/** GPIO_IN_DATA_NEXT : RO; bitpos: [29:0]; default: 0; - * GPIO input register for GPIO0-29 - */ -#define GPIO_IN_DATA_NEXT 0x3FFFFFFFU -#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) -#define GPIO_IN_DATA_NEXT_V 0x3FFFFFFFU -#define GPIO_IN_DATA_NEXT_S 0 - -/** GPIO_STATUS_REG register - * GPIO interrupt status register for GPIO0-29 - */ -#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) -/** GPIO_STATUS_INTERRUPT : R/W/SS; bitpos: [29:0]; default: 0; - * GPIO interrupt status register for GPIO0-29 - */ -#define GPIO_STATUS_INTERRUPT 0x3FFFFFFFU -#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) -#define GPIO_STATUS_INTERRUPT_V 0x3FFFFFFFU -#define GPIO_STATUS_INTERRUPT_S 0 - -/** GPIO_STATUS_W1TS_REG register - * GPIO interrupt status set register for GPIO0-29 - */ -#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) -/** GPIO_STATUS_W1TS : WT; bitpos: [29:0]; default: 0; - * GPIO interrupt status set register for GPIO0-29 - */ -#define GPIO_STATUS_W1TS 0x3FFFFFFFU -#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) -#define GPIO_STATUS_W1TS_V 0x3FFFFFFFU -#define GPIO_STATUS_W1TS_S 0 - -/** GPIO_STATUS_W1TC_REG register - * GPIO interrupt status clear register for GPIO0-29 - */ -#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) -/** GPIO_STATUS_W1TC : WT; bitpos: [29:0]; default: 0; - * GPIO interrupt status clear register for GPIO0-29 - */ -#define GPIO_STATUS_W1TC 0x3FFFFFFFU -#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) -#define GPIO_STATUS_W1TC_V 0x3FFFFFFFU -#define GPIO_STATUS_W1TC_S 0 - -/** GPIO_PCPU_INT_REG register - * GPIO PRO_CPU interrupt status register for GPIO0-29 - */ -#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) -/** GPIO_PROCPU_INT : RO; bitpos: [29:0]; default: 0; - * GPIO PRO_CPU interrupt status register for GPIO0-29 - */ -#define GPIO_PROCPU_INT 0x3FFFFFFFU -#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) -#define GPIO_PROCPU_INT_V 0x3FFFFFFFU -#define GPIO_PROCPU_INT_S 0 - -/** GPIO_PCPU_NMI_INT_REG register - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 - */ -#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) -/** GPIO_PROCPU_NMI_INT : RO; bitpos: [29:0]; default: 0; - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 - */ -#define GPIO_PROCPU_NMI_INT 0x3FFFFFFFU -#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) -#define GPIO_PROCPU_NMI_INT_V 0x3FFFFFFFU -#define GPIO_PROCPU_NMI_INT_S 0 - -/** GPIO_CPUSDIO_INT_REG register - * GPIO CPUSDIO interrupt status register for GPIO0-29 - */ -#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) -/** GPIO_SDIO_INT : RO; bitpos: [29:0]; default: 0; - * GPIO CPUSDIO interrupt status register for GPIO0-29 - */ -#define GPIO_SDIO_INT 0x3FFFFFFFU -#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) -#define GPIO_SDIO_INT_V 0x3FFFFFFFU -#define GPIO_SDIO_INT_S 0 - -/** GPIO_PIN0_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) -/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN0_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) -#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN0_SYNC2_BYPASS_S 0 -/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) -#define GPIO_PIN0_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN0_PAD_DRIVER_S 2 -/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN0_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) -#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN0_SYNC1_BYPASS_S 3 -/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN0_INT_TYPE 0x00000007U -#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) -#define GPIO_PIN0_INT_TYPE_V 0x00000007U -#define GPIO_PIN0_INT_TYPE_S 7 -/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) -#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN0_WAKEUP_ENABLE_S 10 -/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN0_CONFIG 0x00000003U -#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) -#define GPIO_PIN0_CONFIG_V 0x00000003U -#define GPIO_PIN0_CONFIG_S 11 -/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN0_INT_ENA 0x0000001FU -#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) -#define GPIO_PIN0_INT_ENA_V 0x0000001FU -#define GPIO_PIN0_INT_ENA_S 13 - -/** GPIO_PIN1_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) -/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN1_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) -#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN1_SYNC2_BYPASS_S 0 -/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) -#define GPIO_PIN1_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN1_PAD_DRIVER_S 2 -/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN1_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) -#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN1_SYNC1_BYPASS_S 3 -/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN1_INT_TYPE 0x00000007U -#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) -#define GPIO_PIN1_INT_TYPE_V 0x00000007U -#define GPIO_PIN1_INT_TYPE_S 7 -/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) -#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN1_WAKEUP_ENABLE_S 10 -/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN1_CONFIG 0x00000003U -#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) -#define GPIO_PIN1_CONFIG_V 0x00000003U -#define GPIO_PIN1_CONFIG_S 11 -/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN1_INT_ENA 0x0000001FU -#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) -#define GPIO_PIN1_INT_ENA_V 0x0000001FU -#define GPIO_PIN1_INT_ENA_S 13 - -/** GPIO_PIN2_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) -/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN2_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) -#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN2_SYNC2_BYPASS_S 0 -/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) -#define GPIO_PIN2_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN2_PAD_DRIVER_S 2 -/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN2_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) -#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN2_SYNC1_BYPASS_S 3 -/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN2_INT_TYPE 0x00000007U -#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) -#define GPIO_PIN2_INT_TYPE_V 0x00000007U -#define GPIO_PIN2_INT_TYPE_S 7 -/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) -#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN2_WAKEUP_ENABLE_S 10 -/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN2_CONFIG 0x00000003U -#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) -#define GPIO_PIN2_CONFIG_V 0x00000003U -#define GPIO_PIN2_CONFIG_S 11 -/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN2_INT_ENA 0x0000001FU -#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) -#define GPIO_PIN2_INT_ENA_V 0x0000001FU -#define GPIO_PIN2_INT_ENA_S 13 - -/** GPIO_PIN3_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) -/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN3_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) -#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN3_SYNC2_BYPASS_S 0 -/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) -#define GPIO_PIN3_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN3_PAD_DRIVER_S 2 -/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN3_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) -#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN3_SYNC1_BYPASS_S 3 -/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN3_INT_TYPE 0x00000007U -#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) -#define GPIO_PIN3_INT_TYPE_V 0x00000007U -#define GPIO_PIN3_INT_TYPE_S 7 -/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) -#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN3_WAKEUP_ENABLE_S 10 -/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN3_CONFIG 0x00000003U -#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) -#define GPIO_PIN3_CONFIG_V 0x00000003U -#define GPIO_PIN3_CONFIG_S 11 -/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN3_INT_ENA 0x0000001FU -#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) -#define GPIO_PIN3_INT_ENA_V 0x0000001FU -#define GPIO_PIN3_INT_ENA_S 13 - -/** GPIO_PIN4_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) -/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN4_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) -#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN4_SYNC2_BYPASS_S 0 -/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) -#define GPIO_PIN4_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN4_PAD_DRIVER_S 2 -/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN4_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) -#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN4_SYNC1_BYPASS_S 3 -/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN4_INT_TYPE 0x00000007U -#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) -#define GPIO_PIN4_INT_TYPE_V 0x00000007U -#define GPIO_PIN4_INT_TYPE_S 7 -/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) -#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN4_WAKEUP_ENABLE_S 10 -/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN4_CONFIG 0x00000003U -#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) -#define GPIO_PIN4_CONFIG_V 0x00000003U -#define GPIO_PIN4_CONFIG_S 11 -/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN4_INT_ENA 0x0000001FU -#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) -#define GPIO_PIN4_INT_ENA_V 0x0000001FU -#define GPIO_PIN4_INT_ENA_S 13 - -/** GPIO_PIN5_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) -/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN5_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) -#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN5_SYNC2_BYPASS_S 0 -/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) -#define GPIO_PIN5_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN5_PAD_DRIVER_S 2 -/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN5_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) -#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN5_SYNC1_BYPASS_S 3 -/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN5_INT_TYPE 0x00000007U -#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) -#define GPIO_PIN5_INT_TYPE_V 0x00000007U -#define GPIO_PIN5_INT_TYPE_S 7 -/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) -#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN5_WAKEUP_ENABLE_S 10 -/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN5_CONFIG 0x00000003U -#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) -#define GPIO_PIN5_CONFIG_V 0x00000003U -#define GPIO_PIN5_CONFIG_S 11 -/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN5_INT_ENA 0x0000001FU -#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) -#define GPIO_PIN5_INT_ENA_V 0x0000001FU -#define GPIO_PIN5_INT_ENA_S 13 - -/** GPIO_PIN6_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) -/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN6_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) -#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN6_SYNC2_BYPASS_S 0 -/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) -#define GPIO_PIN6_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN6_PAD_DRIVER_S 2 -/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN6_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) -#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN6_SYNC1_BYPASS_S 3 -/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN6_INT_TYPE 0x00000007U -#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) -#define GPIO_PIN6_INT_TYPE_V 0x00000007U -#define GPIO_PIN6_INT_TYPE_S 7 -/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) -#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN6_WAKEUP_ENABLE_S 10 -/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN6_CONFIG 0x00000003U -#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) -#define GPIO_PIN6_CONFIG_V 0x00000003U -#define GPIO_PIN6_CONFIG_S 11 -/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN6_INT_ENA 0x0000001FU -#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) -#define GPIO_PIN6_INT_ENA_V 0x0000001FU -#define GPIO_PIN6_INT_ENA_S 13 - -/** GPIO_PIN7_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) -/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN7_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) -#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN7_SYNC2_BYPASS_S 0 -/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) -#define GPIO_PIN7_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN7_PAD_DRIVER_S 2 -/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN7_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) -#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN7_SYNC1_BYPASS_S 3 -/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN7_INT_TYPE 0x00000007U -#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) -#define GPIO_PIN7_INT_TYPE_V 0x00000007U -#define GPIO_PIN7_INT_TYPE_S 7 -/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) -#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN7_WAKEUP_ENABLE_S 10 -/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN7_CONFIG 0x00000003U -#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) -#define GPIO_PIN7_CONFIG_V 0x00000003U -#define GPIO_PIN7_CONFIG_S 11 -/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN7_INT_ENA 0x0000001FU -#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) -#define GPIO_PIN7_INT_ENA_V 0x0000001FU -#define GPIO_PIN7_INT_ENA_S 13 - -/** GPIO_PIN8_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) -/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN8_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) -#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN8_SYNC2_BYPASS_S 0 -/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) -#define GPIO_PIN8_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN8_PAD_DRIVER_S 2 -/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN8_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) -#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN8_SYNC1_BYPASS_S 3 -/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN8_INT_TYPE 0x00000007U -#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) -#define GPIO_PIN8_INT_TYPE_V 0x00000007U -#define GPIO_PIN8_INT_TYPE_S 7 -/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) -#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN8_WAKEUP_ENABLE_S 10 -/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN8_CONFIG 0x00000003U -#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) -#define GPIO_PIN8_CONFIG_V 0x00000003U -#define GPIO_PIN8_CONFIG_S 11 -/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN8_INT_ENA 0x0000001FU -#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) -#define GPIO_PIN8_INT_ENA_V 0x0000001FU -#define GPIO_PIN8_INT_ENA_S 13 - -/** GPIO_PIN9_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) -/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN9_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) -#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN9_SYNC2_BYPASS_S 0 -/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) -#define GPIO_PIN9_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN9_PAD_DRIVER_S 2 -/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN9_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) -#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN9_SYNC1_BYPASS_S 3 -/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN9_INT_TYPE 0x00000007U -#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) -#define GPIO_PIN9_INT_TYPE_V 0x00000007U -#define GPIO_PIN9_INT_TYPE_S 7 -/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) -#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN9_WAKEUP_ENABLE_S 10 -/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN9_CONFIG 0x00000003U -#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) -#define GPIO_PIN9_CONFIG_V 0x00000003U -#define GPIO_PIN9_CONFIG_S 11 -/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN9_INT_ENA 0x0000001FU -#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) -#define GPIO_PIN9_INT_ENA_V 0x0000001FU -#define GPIO_PIN9_INT_ENA_S 13 - -/** GPIO_PIN10_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) -/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN10_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) -#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN10_SYNC2_BYPASS_S 0 -/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) -#define GPIO_PIN10_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN10_PAD_DRIVER_S 2 -/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN10_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) -#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN10_SYNC1_BYPASS_S 3 -/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN10_INT_TYPE 0x00000007U -#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) -#define GPIO_PIN10_INT_TYPE_V 0x00000007U -#define GPIO_PIN10_INT_TYPE_S 7 -/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) -#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN10_WAKEUP_ENABLE_S 10 -/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN10_CONFIG 0x00000003U -#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) -#define GPIO_PIN10_CONFIG_V 0x00000003U -#define GPIO_PIN10_CONFIG_S 11 -/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN10_INT_ENA 0x0000001FU -#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) -#define GPIO_PIN10_INT_ENA_V 0x0000001FU -#define GPIO_PIN10_INT_ENA_S 13 - -/** GPIO_PIN11_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) -/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN11_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) -#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN11_SYNC2_BYPASS_S 0 -/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) -#define GPIO_PIN11_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN11_PAD_DRIVER_S 2 -/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN11_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) -#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN11_SYNC1_BYPASS_S 3 -/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN11_INT_TYPE 0x00000007U -#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) -#define GPIO_PIN11_INT_TYPE_V 0x00000007U -#define GPIO_PIN11_INT_TYPE_S 7 -/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) -#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN11_WAKEUP_ENABLE_S 10 -/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN11_CONFIG 0x00000003U -#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) -#define GPIO_PIN11_CONFIG_V 0x00000003U -#define GPIO_PIN11_CONFIG_S 11 -/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN11_INT_ENA 0x0000001FU -#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) -#define GPIO_PIN11_INT_ENA_V 0x0000001FU -#define GPIO_PIN11_INT_ENA_S 13 - -/** GPIO_PIN12_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) -/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN12_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) -#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN12_SYNC2_BYPASS_S 0 -/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) -#define GPIO_PIN12_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN12_PAD_DRIVER_S 2 -/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN12_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) -#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN12_SYNC1_BYPASS_S 3 -/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN12_INT_TYPE 0x00000007U -#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) -#define GPIO_PIN12_INT_TYPE_V 0x00000007U -#define GPIO_PIN12_INT_TYPE_S 7 -/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) -#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN12_WAKEUP_ENABLE_S 10 -/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN12_CONFIG 0x00000003U -#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) -#define GPIO_PIN12_CONFIG_V 0x00000003U -#define GPIO_PIN12_CONFIG_S 11 -/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN12_INT_ENA 0x0000001FU -#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) -#define GPIO_PIN12_INT_ENA_V 0x0000001FU -#define GPIO_PIN12_INT_ENA_S 13 - -/** GPIO_PIN13_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) -/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN13_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) -#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN13_SYNC2_BYPASS_S 0 -/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) -#define GPIO_PIN13_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN13_PAD_DRIVER_S 2 -/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN13_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) -#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN13_SYNC1_BYPASS_S 3 -/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN13_INT_TYPE 0x00000007U -#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) -#define GPIO_PIN13_INT_TYPE_V 0x00000007U -#define GPIO_PIN13_INT_TYPE_S 7 -/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) -#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN13_WAKEUP_ENABLE_S 10 -/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN13_CONFIG 0x00000003U -#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) -#define GPIO_PIN13_CONFIG_V 0x00000003U -#define GPIO_PIN13_CONFIG_S 11 -/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN13_INT_ENA 0x0000001FU -#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) -#define GPIO_PIN13_INT_ENA_V 0x0000001FU -#define GPIO_PIN13_INT_ENA_S 13 - -/** GPIO_PIN14_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) -/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN14_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) -#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN14_SYNC2_BYPASS_S 0 -/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) -#define GPIO_PIN14_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN14_PAD_DRIVER_S 2 -/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN14_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) -#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN14_SYNC1_BYPASS_S 3 -/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN14_INT_TYPE 0x00000007U -#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) -#define GPIO_PIN14_INT_TYPE_V 0x00000007U -#define GPIO_PIN14_INT_TYPE_S 7 -/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) -#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN14_WAKEUP_ENABLE_S 10 -/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN14_CONFIG 0x00000003U -#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) -#define GPIO_PIN14_CONFIG_V 0x00000003U -#define GPIO_PIN14_CONFIG_S 11 -/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN14_INT_ENA 0x0000001FU -#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) -#define GPIO_PIN14_INT_ENA_V 0x0000001FU -#define GPIO_PIN14_INT_ENA_S 13 - -/** GPIO_PIN15_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) -/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN15_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) -#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN15_SYNC2_BYPASS_S 0 -/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) -#define GPIO_PIN15_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN15_PAD_DRIVER_S 2 -/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN15_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) -#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN15_SYNC1_BYPASS_S 3 -/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN15_INT_TYPE 0x00000007U -#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) -#define GPIO_PIN15_INT_TYPE_V 0x00000007U -#define GPIO_PIN15_INT_TYPE_S 7 -/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) -#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN15_WAKEUP_ENABLE_S 10 -/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN15_CONFIG 0x00000003U -#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) -#define GPIO_PIN15_CONFIG_V 0x00000003U -#define GPIO_PIN15_CONFIG_S 11 -/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN15_INT_ENA 0x0000001FU -#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) -#define GPIO_PIN15_INT_ENA_V 0x0000001FU -#define GPIO_PIN15_INT_ENA_S 13 - -/** GPIO_PIN16_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) -/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN16_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) -#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN16_SYNC2_BYPASS_S 0 -/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) -#define GPIO_PIN16_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN16_PAD_DRIVER_S 2 -/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN16_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) -#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN16_SYNC1_BYPASS_S 3 -/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN16_INT_TYPE 0x00000007U -#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) -#define GPIO_PIN16_INT_TYPE_V 0x00000007U -#define GPIO_PIN16_INT_TYPE_S 7 -/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) -#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN16_WAKEUP_ENABLE_S 10 -/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN16_CONFIG 0x00000003U -#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) -#define GPIO_PIN16_CONFIG_V 0x00000003U -#define GPIO_PIN16_CONFIG_S 11 -/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN16_INT_ENA 0x0000001FU -#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) -#define GPIO_PIN16_INT_ENA_V 0x0000001FU -#define GPIO_PIN16_INT_ENA_S 13 - -/** GPIO_PIN17_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) -/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN17_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) -#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN17_SYNC2_BYPASS_S 0 -/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) -#define GPIO_PIN17_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN17_PAD_DRIVER_S 2 -/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN17_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) -#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN17_SYNC1_BYPASS_S 3 -/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN17_INT_TYPE 0x00000007U -#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) -#define GPIO_PIN17_INT_TYPE_V 0x00000007U -#define GPIO_PIN17_INT_TYPE_S 7 -/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) -#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN17_WAKEUP_ENABLE_S 10 -/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN17_CONFIG 0x00000003U -#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) -#define GPIO_PIN17_CONFIG_V 0x00000003U -#define GPIO_PIN17_CONFIG_S 11 -/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN17_INT_ENA 0x0000001FU -#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) -#define GPIO_PIN17_INT_ENA_V 0x0000001FU -#define GPIO_PIN17_INT_ENA_S 13 - -/** GPIO_PIN18_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) -/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN18_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) -#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN18_SYNC2_BYPASS_S 0 -/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN18_PAD_DRIVER (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) -#define GPIO_PIN18_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN18_PAD_DRIVER_S 2 -/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN18_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) -#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN18_SYNC1_BYPASS_S 3 -/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN18_INT_TYPE 0x00000007U -#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) -#define GPIO_PIN18_INT_TYPE_V 0x00000007U -#define GPIO_PIN18_INT_TYPE_S 7 -/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) -#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN18_WAKEUP_ENABLE_S 10 -/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN18_CONFIG 0x00000003U -#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) -#define GPIO_PIN18_CONFIG_V 0x00000003U -#define GPIO_PIN18_CONFIG_S 11 -/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN18_INT_ENA 0x0000001FU -#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) -#define GPIO_PIN18_INT_ENA_V 0x0000001FU -#define GPIO_PIN18_INT_ENA_S 13 - -/** GPIO_PIN19_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) -/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN19_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) -#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN19_SYNC2_BYPASS_S 0 -/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN19_PAD_DRIVER (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) -#define GPIO_PIN19_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN19_PAD_DRIVER_S 2 -/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN19_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) -#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN19_SYNC1_BYPASS_S 3 -/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN19_INT_TYPE 0x00000007U -#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) -#define GPIO_PIN19_INT_TYPE_V 0x00000007U -#define GPIO_PIN19_INT_TYPE_S 7 -/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) -#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN19_WAKEUP_ENABLE_S 10 -/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN19_CONFIG 0x00000003U -#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) -#define GPIO_PIN19_CONFIG_V 0x00000003U -#define GPIO_PIN19_CONFIG_S 11 -/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN19_INT_ENA 0x0000001FU -#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) -#define GPIO_PIN19_INT_ENA_V 0x0000001FU -#define GPIO_PIN19_INT_ENA_S 13 - -/** GPIO_PIN20_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) -/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN20_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) -#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN20_SYNC2_BYPASS_S 0 -/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN20_PAD_DRIVER (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) -#define GPIO_PIN20_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN20_PAD_DRIVER_S 2 -/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN20_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) -#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN20_SYNC1_BYPASS_S 3 -/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN20_INT_TYPE 0x00000007U -#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) -#define GPIO_PIN20_INT_TYPE_V 0x00000007U -#define GPIO_PIN20_INT_TYPE_S 7 -/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) -#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN20_WAKEUP_ENABLE_S 10 -/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN20_CONFIG 0x00000003U -#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) -#define GPIO_PIN20_CONFIG_V 0x00000003U -#define GPIO_PIN20_CONFIG_S 11 -/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN20_INT_ENA 0x0000001FU -#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) -#define GPIO_PIN20_INT_ENA_V 0x0000001FU -#define GPIO_PIN20_INT_ENA_S 13 - -/** GPIO_PIN21_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) -/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN21_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) -#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN21_SYNC2_BYPASS_S 0 -/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN21_PAD_DRIVER (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) -#define GPIO_PIN21_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN21_PAD_DRIVER_S 2 -/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN21_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) -#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN21_SYNC1_BYPASS_S 3 -/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN21_INT_TYPE 0x00000007U -#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) -#define GPIO_PIN21_INT_TYPE_V 0x00000007U -#define GPIO_PIN21_INT_TYPE_S 7 -/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) -#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN21_WAKEUP_ENABLE_S 10 -/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN21_CONFIG 0x00000003U -#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) -#define GPIO_PIN21_CONFIG_V 0x00000003U -#define GPIO_PIN21_CONFIG_S 11 -/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN21_INT_ENA 0x0000001FU -#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) -#define GPIO_PIN21_INT_ENA_V 0x0000001FU -#define GPIO_PIN21_INT_ENA_S 13 - -/** GPIO_PIN22_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) -/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) -#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN22_SYNC2_BYPASS_S 0 -/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN22_PAD_DRIVER (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) -#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN22_PAD_DRIVER_S 2 -/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) -#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN22_SYNC1_BYPASS_S 3 -/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN22_INT_TYPE 0x00000007U -#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) -#define GPIO_PIN22_INT_TYPE_V 0x00000007U -#define GPIO_PIN22_INT_TYPE_S 7 -/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) -#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN22_WAKEUP_ENABLE_S 10 -/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN22_CONFIG 0x00000003U -#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) -#define GPIO_PIN22_CONFIG_V 0x00000003U -#define GPIO_PIN22_CONFIG_S 11 -/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN22_INT_ENA 0x0000001FU -#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) -#define GPIO_PIN22_INT_ENA_V 0x0000001FU -#define GPIO_PIN22_INT_ENA_S 13 - -/** GPIO_PIN23_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) -/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) -#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN23_SYNC2_BYPASS_S 0 -/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN23_PAD_DRIVER (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) -#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN23_PAD_DRIVER_S 2 -/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) -#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN23_SYNC1_BYPASS_S 3 -/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN23_INT_TYPE 0x00000007U -#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) -#define GPIO_PIN23_INT_TYPE_V 0x00000007U -#define GPIO_PIN23_INT_TYPE_S 7 -/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) -#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN23_WAKEUP_ENABLE_S 10 -/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN23_CONFIG 0x00000003U -#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) -#define GPIO_PIN23_CONFIG_V 0x00000003U -#define GPIO_PIN23_CONFIG_S 11 -/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN23_INT_ENA 0x0000001FU -#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) -#define GPIO_PIN23_INT_ENA_V 0x0000001FU -#define GPIO_PIN23_INT_ENA_S 13 - -/** GPIO_PIN24_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) -/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) -#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN24_SYNC2_BYPASS_S 0 -/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN24_PAD_DRIVER (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) -#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN24_PAD_DRIVER_S 2 -/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) -#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN24_SYNC1_BYPASS_S 3 -/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN24_INT_TYPE 0x00000007U -#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) -#define GPIO_PIN24_INT_TYPE_V 0x00000007U -#define GPIO_PIN24_INT_TYPE_S 7 -/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) -#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN24_WAKEUP_ENABLE_S 10 -/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN24_CONFIG 0x00000003U -#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) -#define GPIO_PIN24_CONFIG_V 0x00000003U -#define GPIO_PIN24_CONFIG_S 11 -/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN24_INT_ENA 0x0000001FU -#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) -#define GPIO_PIN24_INT_ENA_V 0x0000001FU -#define GPIO_PIN24_INT_ENA_S 13 - -/** GPIO_PIN25_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) -/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) -#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN25_SYNC2_BYPASS_S 0 -/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN25_PAD_DRIVER (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) -#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN25_PAD_DRIVER_S 2 -/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) -#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN25_SYNC1_BYPASS_S 3 -/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN25_INT_TYPE 0x00000007U -#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) -#define GPIO_PIN25_INT_TYPE_V 0x00000007U -#define GPIO_PIN25_INT_TYPE_S 7 -/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) -#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN25_WAKEUP_ENABLE_S 10 -/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN25_CONFIG 0x00000003U -#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) -#define GPIO_PIN25_CONFIG_V 0x00000003U -#define GPIO_PIN25_CONFIG_S 11 -/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN25_INT_ENA 0x0000001FU -#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) -#define GPIO_PIN25_INT_ENA_V 0x0000001FU -#define GPIO_PIN25_INT_ENA_S 13 - -/** GPIO_PIN26_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) -/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) -#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN26_SYNC2_BYPASS_S 0 -/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN26_PAD_DRIVER (BIT(2)) -#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) -#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN26_PAD_DRIVER_S 2 -/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) -#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN26_SYNC1_BYPASS_S 3 -/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN26_INT_TYPE 0x00000007U -#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) -#define GPIO_PIN26_INT_TYPE_V 0x00000007U -#define GPIO_PIN26_INT_TYPE_S 7 -/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) -#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN26_WAKEUP_ENABLE_S 10 -/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN26_CONFIG 0x00000003U -#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) -#define GPIO_PIN26_CONFIG_V 0x00000003U -#define GPIO_PIN26_CONFIG_S 11 -/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN26_INT_ENA 0x0000001FU -#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) -#define GPIO_PIN26_INT_ENA_V 0x0000001FU -#define GPIO_PIN26_INT_ENA_S 13 - -/** GPIO_PIN27_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) -/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) -#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN27_SYNC2_BYPASS_S 0 -/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN27_PAD_DRIVER (BIT(2)) -#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) -#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN27_PAD_DRIVER_S 2 -/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) -#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN27_SYNC1_BYPASS_S 3 -/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN27_INT_TYPE 0x00000007U -#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) -#define GPIO_PIN27_INT_TYPE_V 0x00000007U -#define GPIO_PIN27_INT_TYPE_S 7 -/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) -#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN27_WAKEUP_ENABLE_S 10 -/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN27_CONFIG 0x00000003U -#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) -#define GPIO_PIN27_CONFIG_V 0x00000003U -#define GPIO_PIN27_CONFIG_S 11 -/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN27_INT_ENA 0x0000001FU -#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) -#define GPIO_PIN27_INT_ENA_V 0x0000001FU -#define GPIO_PIN27_INT_ENA_S 13 - -/** GPIO_PIN28_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) -/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) -#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN28_SYNC2_BYPASS_S 0 -/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN28_PAD_DRIVER (BIT(2)) -#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) -#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN28_PAD_DRIVER_S 2 -/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) -#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN28_SYNC1_BYPASS_S 3 -/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN28_INT_TYPE 0x00000007U -#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) -#define GPIO_PIN28_INT_TYPE_V 0x00000007U -#define GPIO_PIN28_INT_TYPE_S 7 -/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) -#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN28_WAKEUP_ENABLE_S 10 -/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN28_CONFIG 0x00000003U -#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) -#define GPIO_PIN28_CONFIG_V 0x00000003U -#define GPIO_PIN28_CONFIG_S 11 -/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN28_INT_ENA 0x0000001FU -#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) -#define GPIO_PIN28_INT_ENA_V 0x0000001FU -#define GPIO_PIN28_INT_ENA_S 13 - -/** GPIO_PIN29_REG register - * GPIO pin configuration register - */ -#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) -/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U -#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) -#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U -#define GPIO_PIN29_SYNC2_BYPASS_S 0 -/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ -#define GPIO_PIN29_PAD_DRIVER (BIT(2)) -#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) -#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U -#define GPIO_PIN29_PAD_DRIVER_S 2 -/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ -#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U -#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) -#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U -#define GPIO_PIN29_SYNC1_BYPASS_S 3 -/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ -#define GPIO_PIN29_INT_TYPE 0x00000007U -#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) -#define GPIO_PIN29_INT_TYPE_V 0x00000007U -#define GPIO_PIN29_INT_TYPE_S 7 -/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ -#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) -#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U -#define GPIO_PIN29_WAKEUP_ENABLE_S 10 -/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; - * reserved - */ -#define GPIO_PIN29_CONFIG 0x00000003U -#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) -#define GPIO_PIN29_CONFIG_V 0x00000003U -#define GPIO_PIN29_CONFIG_S 11 -/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ -#define GPIO_PIN29_INT_ENA 0x0000001FU -#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) -#define GPIO_PIN29_INT_ENA_V 0x0000001FU -#define GPIO_PIN29_INT_ENA_S 13 - -/** GPIO_STATUS_NEXT_REG register - * GPIO interrupt source register for GPIO0-29 - */ -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) -/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; - * GPIO interrupt source register for GPIO0-29 - */ -#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU -#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU -#define GPIO_STATUS_INTERRUPT_NEXT_S 0 - -/** GPIO_FUNC0_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) -/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC0_IN_SEL 0x0000001FU -#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) -#define GPIO_FUNC0_IN_SEL_V 0x0000001FU -#define GPIO_FUNC0_IN_SEL_S 0 -/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) -#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_IN_INV_SEL_S 5 -/** GPIO_SIG0_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG0_IN_SEL (BIT(6)) -#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) -#define GPIO_SIG0_IN_SEL_V 0x00000001U -#define GPIO_SIG0_IN_SEL_S 6 - -/** GPIO_FUNC1_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) -/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC1_IN_SEL 0x0000001FU -#define GPIO_FUNC1_IN_SEL_M (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S) -#define GPIO_FUNC1_IN_SEL_V 0x0000001FU -#define GPIO_FUNC1_IN_SEL_S 0 -/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC1_IN_INV_SEL_M (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S) -#define GPIO_FUNC1_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC1_IN_INV_SEL_S 5 -/** GPIO_SIG1_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG1_IN_SEL (BIT(6)) -#define GPIO_SIG1_IN_SEL_M (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S) -#define GPIO_SIG1_IN_SEL_V 0x00000001U -#define GPIO_SIG1_IN_SEL_S 6 - -/** GPIO_FUNC2_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) -/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC2_IN_SEL 0x0000001FU -#define GPIO_FUNC2_IN_SEL_M (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S) -#define GPIO_FUNC2_IN_SEL_V 0x0000001FU -#define GPIO_FUNC2_IN_SEL_S 0 -/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC2_IN_INV_SEL_M (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S) -#define GPIO_FUNC2_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC2_IN_INV_SEL_S 5 -/** GPIO_SIG2_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG2_IN_SEL (BIT(6)) -#define GPIO_SIG2_IN_SEL_M (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S) -#define GPIO_SIG2_IN_SEL_V 0x00000001U -#define GPIO_SIG2_IN_SEL_S 6 - -/** GPIO_FUNC3_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) -/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC3_IN_SEL 0x0000001FU -#define GPIO_FUNC3_IN_SEL_M (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S) -#define GPIO_FUNC3_IN_SEL_V 0x0000001FU -#define GPIO_FUNC3_IN_SEL_S 0 -/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC3_IN_INV_SEL_M (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S) -#define GPIO_FUNC3_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC3_IN_INV_SEL_S 5 -/** GPIO_SIG3_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG3_IN_SEL (BIT(6)) -#define GPIO_SIG3_IN_SEL_M (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S) -#define GPIO_SIG3_IN_SEL_V 0x00000001U -#define GPIO_SIG3_IN_SEL_S 6 - -/** GPIO_FUNC4_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) -/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC4_IN_SEL 0x0000001FU -#define GPIO_FUNC4_IN_SEL_M (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S) -#define GPIO_FUNC4_IN_SEL_V 0x0000001FU -#define GPIO_FUNC4_IN_SEL_S 0 -/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC4_IN_INV_SEL_M (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S) -#define GPIO_FUNC4_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC4_IN_INV_SEL_S 5 -/** GPIO_SIG4_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG4_IN_SEL (BIT(6)) -#define GPIO_SIG4_IN_SEL_M (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S) -#define GPIO_SIG4_IN_SEL_V 0x00000001U -#define GPIO_SIG4_IN_SEL_S 6 - -/** GPIO_FUNC5_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) -/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC5_IN_SEL 0x0000001FU -#define GPIO_FUNC5_IN_SEL_M (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S) -#define GPIO_FUNC5_IN_SEL_V 0x0000001FU -#define GPIO_FUNC5_IN_SEL_S 0 -/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC5_IN_INV_SEL_M (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S) -#define GPIO_FUNC5_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC5_IN_INV_SEL_S 5 -/** GPIO_SIG5_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG5_IN_SEL (BIT(6)) -#define GPIO_SIG5_IN_SEL_M (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S) -#define GPIO_SIG5_IN_SEL_V 0x00000001U -#define GPIO_SIG5_IN_SEL_S 6 - -/** GPIO_FUNC6_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) -/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC6_IN_SEL 0x0000001FU -#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) -#define GPIO_FUNC6_IN_SEL_V 0x0000001FU -#define GPIO_FUNC6_IN_SEL_S 0 -/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) -#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_IN_INV_SEL_S 5 -/** GPIO_SIG6_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG6_IN_SEL (BIT(6)) -#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) -#define GPIO_SIG6_IN_SEL_V 0x00000001U -#define GPIO_SIG6_IN_SEL_S 6 - -/** GPIO_FUNC7_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) -/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC7_IN_SEL 0x0000001FU -#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) -#define GPIO_FUNC7_IN_SEL_V 0x0000001FU -#define GPIO_FUNC7_IN_SEL_S 0 -/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) -#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_IN_INV_SEL_S 5 -/** GPIO_SIG7_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG7_IN_SEL (BIT(6)) -#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) -#define GPIO_SIG7_IN_SEL_V 0x00000001U -#define GPIO_SIG7_IN_SEL_S 6 - -/** GPIO_FUNC8_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) -/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC8_IN_SEL 0x0000001FU -#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) -#define GPIO_FUNC8_IN_SEL_V 0x0000001FU -#define GPIO_FUNC8_IN_SEL_S 0 -/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) -#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_IN_INV_SEL_S 5 -/** GPIO_SIG8_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG8_IN_SEL (BIT(6)) -#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) -#define GPIO_SIG8_IN_SEL_V 0x00000001U -#define GPIO_SIG8_IN_SEL_S 6 - -/** GPIO_FUNC9_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) -/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC9_IN_SEL 0x0000001FU -#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) -#define GPIO_FUNC9_IN_SEL_V 0x0000001FU -#define GPIO_FUNC9_IN_SEL_S 0 -/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) -#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_IN_INV_SEL_S 5 -/** GPIO_SIG9_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG9_IN_SEL (BIT(6)) -#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) -#define GPIO_SIG9_IN_SEL_V 0x00000001U -#define GPIO_SIG9_IN_SEL_S 6 - -/** GPIO_FUNC10_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) -/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC10_IN_SEL 0x0000001FU -#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) -#define GPIO_FUNC10_IN_SEL_V 0x0000001FU -#define GPIO_FUNC10_IN_SEL_S 0 -/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) -#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_IN_INV_SEL_S 5 -/** GPIO_SIG10_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG10_IN_SEL (BIT(6)) -#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) -#define GPIO_SIG10_IN_SEL_V 0x00000001U -#define GPIO_SIG10_IN_SEL_S 6 - -/** GPIO_FUNC11_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) -/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC11_IN_SEL 0x0000001FU -#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) -#define GPIO_FUNC11_IN_SEL_V 0x0000001FU -#define GPIO_FUNC11_IN_SEL_S 0 -/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) -#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_IN_INV_SEL_S 5 -/** GPIO_SIG11_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG11_IN_SEL (BIT(6)) -#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) -#define GPIO_SIG11_IN_SEL_V 0x00000001U -#define GPIO_SIG11_IN_SEL_S 6 - -/** GPIO_FUNC12_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) -/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC12_IN_SEL 0x0000001FU -#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) -#define GPIO_FUNC12_IN_SEL_V 0x0000001FU -#define GPIO_FUNC12_IN_SEL_S 0 -/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) -#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_IN_INV_SEL_S 5 -/** GPIO_SIG12_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG12_IN_SEL (BIT(6)) -#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) -#define GPIO_SIG12_IN_SEL_V 0x00000001U -#define GPIO_SIG12_IN_SEL_S 6 - -/** GPIO_FUNC13_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) -/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC13_IN_SEL 0x0000001FU -#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) -#define GPIO_FUNC13_IN_SEL_V 0x0000001FU -#define GPIO_FUNC13_IN_SEL_S 0 -/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) -#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_IN_INV_SEL_S 5 -/** GPIO_SIG13_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG13_IN_SEL (BIT(6)) -#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) -#define GPIO_SIG13_IN_SEL_V 0x00000001U -#define GPIO_SIG13_IN_SEL_S 6 - -/** GPIO_FUNC14_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) -/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC14_IN_SEL 0x0000001FU -#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) -#define GPIO_FUNC14_IN_SEL_V 0x0000001FU -#define GPIO_FUNC14_IN_SEL_S 0 -/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) -#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_IN_INV_SEL_S 5 -/** GPIO_SIG14_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG14_IN_SEL (BIT(6)) -#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) -#define GPIO_SIG14_IN_SEL_V 0x00000001U -#define GPIO_SIG14_IN_SEL_S 6 - -/** GPIO_FUNC15_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) -/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC15_IN_SEL 0x0000001FU -#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) -#define GPIO_FUNC15_IN_SEL_V 0x0000001FU -#define GPIO_FUNC15_IN_SEL_S 0 -/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) -#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_IN_INV_SEL_S 5 -/** GPIO_SIG15_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG15_IN_SEL (BIT(6)) -#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) -#define GPIO_SIG15_IN_SEL_V 0x00000001U -#define GPIO_SIG15_IN_SEL_S 6 - -/** GPIO_FUNC16_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) -/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC16_IN_SEL 0x0000001FU -#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) -#define GPIO_FUNC16_IN_SEL_V 0x0000001FU -#define GPIO_FUNC16_IN_SEL_S 0 -/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) -#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_IN_INV_SEL_S 5 -/** GPIO_SIG16_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG16_IN_SEL (BIT(6)) -#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) -#define GPIO_SIG16_IN_SEL_V 0x00000001U -#define GPIO_SIG16_IN_SEL_S 6 - -/** GPIO_FUNC17_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) -/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC17_IN_SEL 0x0000001FU -#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) -#define GPIO_FUNC17_IN_SEL_V 0x0000001FU -#define GPIO_FUNC17_IN_SEL_S 0 -/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) -#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_IN_INV_SEL_S 5 -/** GPIO_SIG17_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG17_IN_SEL (BIT(6)) -#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) -#define GPIO_SIG17_IN_SEL_V 0x00000001U -#define GPIO_SIG17_IN_SEL_S 6 - -/** GPIO_FUNC18_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) -/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC18_IN_SEL 0x0000001FU -#define GPIO_FUNC18_IN_SEL_M (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S) -#define GPIO_FUNC18_IN_SEL_V 0x0000001FU -#define GPIO_FUNC18_IN_SEL_S 0 -/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC18_IN_INV_SEL_M (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S) -#define GPIO_FUNC18_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC18_IN_INV_SEL_S 5 -/** GPIO_SIG18_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG18_IN_SEL (BIT(6)) -#define GPIO_SIG18_IN_SEL_M (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S) -#define GPIO_SIG18_IN_SEL_V 0x00000001U -#define GPIO_SIG18_IN_SEL_S 6 - -/** GPIO_FUNC19_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) -/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC19_IN_SEL 0x0000001FU -#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) -#define GPIO_FUNC19_IN_SEL_V 0x0000001FU -#define GPIO_FUNC19_IN_SEL_S 0 -/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) -#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC19_IN_INV_SEL_S 5 -/** GPIO_SIG19_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG19_IN_SEL (BIT(6)) -#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) -#define GPIO_SIG19_IN_SEL_V 0x00000001U -#define GPIO_SIG19_IN_SEL_S 6 - -/** GPIO_FUNC20_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) -/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC20_IN_SEL 0x0000001FU -#define GPIO_FUNC20_IN_SEL_M (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S) -#define GPIO_FUNC20_IN_SEL_V 0x0000001FU -#define GPIO_FUNC20_IN_SEL_S 0 -/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC20_IN_INV_SEL_M (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S) -#define GPIO_FUNC20_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC20_IN_INV_SEL_S 5 -/** GPIO_SIG20_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG20_IN_SEL (BIT(6)) -#define GPIO_SIG20_IN_SEL_M (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S) -#define GPIO_SIG20_IN_SEL_V 0x00000001U -#define GPIO_SIG20_IN_SEL_S 6 - -/** GPIO_FUNC21_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) -/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC21_IN_SEL 0x0000001FU -#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) -#define GPIO_FUNC21_IN_SEL_V 0x0000001FU -#define GPIO_FUNC21_IN_SEL_S 0 -/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) -#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC21_IN_INV_SEL_S 5 -/** GPIO_SIG21_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG21_IN_SEL (BIT(6)) -#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) -#define GPIO_SIG21_IN_SEL_V 0x00000001U -#define GPIO_SIG21_IN_SEL_S 6 - -/** GPIO_FUNC22_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) -/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC22_IN_SEL 0x0000001FU -#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) -#define GPIO_FUNC22_IN_SEL_V 0x0000001FU -#define GPIO_FUNC22_IN_SEL_S 0 -/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) -#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC22_IN_INV_SEL_S 5 -/** GPIO_SIG22_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG22_IN_SEL (BIT(6)) -#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) -#define GPIO_SIG22_IN_SEL_V 0x00000001U -#define GPIO_SIG22_IN_SEL_S 6 - -/** GPIO_FUNC23_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) -/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC23_IN_SEL 0x0000001FU -#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) -#define GPIO_FUNC23_IN_SEL_V 0x0000001FU -#define GPIO_FUNC23_IN_SEL_S 0 -/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) -#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC23_IN_INV_SEL_S 5 -/** GPIO_SIG23_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG23_IN_SEL (BIT(6)) -#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) -#define GPIO_SIG23_IN_SEL_V 0x00000001U -#define GPIO_SIG23_IN_SEL_S 6 - -/** GPIO_FUNC24_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) -/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC24_IN_SEL 0x0000001FU -#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) -#define GPIO_FUNC24_IN_SEL_V 0x0000001FU -#define GPIO_FUNC24_IN_SEL_S 0 -/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) -#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC24_IN_INV_SEL_S 5 -/** GPIO_SIG24_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG24_IN_SEL (BIT(6)) -#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) -#define GPIO_SIG24_IN_SEL_V 0x00000001U -#define GPIO_SIG24_IN_SEL_S 6 - -/** GPIO_FUNC25_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) -/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC25_IN_SEL 0x0000001FU -#define GPIO_FUNC25_IN_SEL_M (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S) -#define GPIO_FUNC25_IN_SEL_V 0x0000001FU -#define GPIO_FUNC25_IN_SEL_S 0 -/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC25_IN_INV_SEL_M (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S) -#define GPIO_FUNC25_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC25_IN_INV_SEL_S 5 -/** GPIO_SIG25_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG25_IN_SEL (BIT(6)) -#define GPIO_SIG25_IN_SEL_M (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S) -#define GPIO_SIG25_IN_SEL_V 0x00000001U -#define GPIO_SIG25_IN_SEL_S 6 - -/** GPIO_FUNC26_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) -/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC26_IN_SEL 0x0000001FU -#define GPIO_FUNC26_IN_SEL_M (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S) -#define GPIO_FUNC26_IN_SEL_V 0x0000001FU -#define GPIO_FUNC26_IN_SEL_S 0 -/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC26_IN_INV_SEL_M (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S) -#define GPIO_FUNC26_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC26_IN_INV_SEL_S 5 -/** GPIO_SIG26_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG26_IN_SEL (BIT(6)) -#define GPIO_SIG26_IN_SEL_M (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S) -#define GPIO_SIG26_IN_SEL_V 0x00000001U -#define GPIO_SIG26_IN_SEL_S 6 - -/** GPIO_FUNC27_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) -/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC27_IN_SEL 0x0000001FU -#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) -#define GPIO_FUNC27_IN_SEL_V 0x0000001FU -#define GPIO_FUNC27_IN_SEL_S 0 -/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) -#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_IN_INV_SEL_S 5 -/** GPIO_SIG27_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG27_IN_SEL (BIT(6)) -#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) -#define GPIO_SIG27_IN_SEL_V 0x00000001U -#define GPIO_SIG27_IN_SEL_S 6 - -/** GPIO_FUNC28_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) -/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC28_IN_SEL 0x0000001FU -#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) -#define GPIO_FUNC28_IN_SEL_V 0x0000001FU -#define GPIO_FUNC28_IN_SEL_S 0 -/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) -#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_IN_INV_SEL_S 5 -/** GPIO_SIG28_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG28_IN_SEL (BIT(6)) -#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) -#define GPIO_SIG28_IN_SEL_V 0x00000001U -#define GPIO_SIG28_IN_SEL_S 6 - -/** GPIO_FUNC29_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) -/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC29_IN_SEL 0x0000001FU -#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) -#define GPIO_FUNC29_IN_SEL_V 0x0000001FU -#define GPIO_FUNC29_IN_SEL_S 0 -/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) -#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_IN_INV_SEL_S 5 -/** GPIO_SIG29_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG29_IN_SEL (BIT(6)) -#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) -#define GPIO_SIG29_IN_SEL_V 0x00000001U -#define GPIO_SIG29_IN_SEL_S 6 - -/** GPIO_FUNC30_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) -/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC30_IN_SEL 0x0000001FU -#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) -#define GPIO_FUNC30_IN_SEL_V 0x0000001FU -#define GPIO_FUNC30_IN_SEL_S 0 -/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) -#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_IN_INV_SEL_S 5 -/** GPIO_SIG30_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG30_IN_SEL (BIT(6)) -#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) -#define GPIO_SIG30_IN_SEL_V 0x00000001U -#define GPIO_SIG30_IN_SEL_S 6 - -/** GPIO_FUNC31_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) -/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC31_IN_SEL 0x0000001FU -#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) -#define GPIO_FUNC31_IN_SEL_V 0x0000001FU -#define GPIO_FUNC31_IN_SEL_S 0 -/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) -#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_IN_INV_SEL_S 5 -/** GPIO_SIG31_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG31_IN_SEL (BIT(6)) -#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) -#define GPIO_SIG31_IN_SEL_V 0x00000001U -#define GPIO_SIG31_IN_SEL_S 6 - -/** GPIO_FUNC32_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) -/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC32_IN_SEL 0x0000001FU -#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) -#define GPIO_FUNC32_IN_SEL_V 0x0000001FU -#define GPIO_FUNC32_IN_SEL_S 0 -/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) -#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_IN_INV_SEL_S 5 -/** GPIO_SIG32_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG32_IN_SEL (BIT(6)) -#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) -#define GPIO_SIG32_IN_SEL_V 0x00000001U -#define GPIO_SIG32_IN_SEL_S 6 - -/** GPIO_FUNC33_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) -/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC33_IN_SEL 0x0000001FU -#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) -#define GPIO_FUNC33_IN_SEL_V 0x0000001FU -#define GPIO_FUNC33_IN_SEL_S 0 -/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) -#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC33_IN_INV_SEL_S 5 -/** GPIO_SIG33_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG33_IN_SEL (BIT(6)) -#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) -#define GPIO_SIG33_IN_SEL_V 0x00000001U -#define GPIO_SIG33_IN_SEL_S 6 - -/** GPIO_FUNC34_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) -/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC34_IN_SEL 0x0000001FU -#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) -#define GPIO_FUNC34_IN_SEL_V 0x0000001FU -#define GPIO_FUNC34_IN_SEL_S 0 -/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) -#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC34_IN_INV_SEL_S 5 -/** GPIO_SIG34_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG34_IN_SEL (BIT(6)) -#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) -#define GPIO_SIG34_IN_SEL_V 0x00000001U -#define GPIO_SIG34_IN_SEL_S 6 - -/** GPIO_FUNC35_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) -/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC35_IN_SEL 0x0000001FU -#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) -#define GPIO_FUNC35_IN_SEL_V 0x0000001FU -#define GPIO_FUNC35_IN_SEL_S 0 -/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) -#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC35_IN_INV_SEL_S 5 -/** GPIO_SIG35_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG35_IN_SEL (BIT(6)) -#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) -#define GPIO_SIG35_IN_SEL_V 0x00000001U -#define GPIO_SIG35_IN_SEL_S 6 - -/** GPIO_FUNC36_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) -/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC36_IN_SEL 0x0000001FU -#define GPIO_FUNC36_IN_SEL_M (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S) -#define GPIO_FUNC36_IN_SEL_V 0x0000001FU -#define GPIO_FUNC36_IN_SEL_S 0 -/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC36_IN_INV_SEL_M (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S) -#define GPIO_FUNC36_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC36_IN_INV_SEL_S 5 -/** GPIO_SIG36_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG36_IN_SEL (BIT(6)) -#define GPIO_SIG36_IN_SEL_M (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S) -#define GPIO_SIG36_IN_SEL_V 0x00000001U -#define GPIO_SIG36_IN_SEL_S 6 - -/** GPIO_FUNC37_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) -/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC37_IN_SEL 0x0000001FU -#define GPIO_FUNC37_IN_SEL_M (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S) -#define GPIO_FUNC37_IN_SEL_V 0x0000001FU -#define GPIO_FUNC37_IN_SEL_S 0 -/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC37_IN_INV_SEL_M (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S) -#define GPIO_FUNC37_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC37_IN_INV_SEL_S 5 -/** GPIO_SIG37_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG37_IN_SEL (BIT(6)) -#define GPIO_SIG37_IN_SEL_M (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S) -#define GPIO_SIG37_IN_SEL_V 0x00000001U -#define GPIO_SIG37_IN_SEL_S 6 - -/** GPIO_FUNC38_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) -/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC38_IN_SEL 0x0000001FU -#define GPIO_FUNC38_IN_SEL_M (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S) -#define GPIO_FUNC38_IN_SEL_V 0x0000001FU -#define GPIO_FUNC38_IN_SEL_S 0 -/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC38_IN_INV_SEL_M (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S) -#define GPIO_FUNC38_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC38_IN_INV_SEL_S 5 -/** GPIO_SIG38_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG38_IN_SEL (BIT(6)) -#define GPIO_SIG38_IN_SEL_M (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S) -#define GPIO_SIG38_IN_SEL_V 0x00000001U -#define GPIO_SIG38_IN_SEL_S 6 - -/** GPIO_FUNC39_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) -/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC39_IN_SEL 0x0000001FU -#define GPIO_FUNC39_IN_SEL_M (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S) -#define GPIO_FUNC39_IN_SEL_V 0x0000001FU -#define GPIO_FUNC39_IN_SEL_S 0 -/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC39_IN_INV_SEL_M (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S) -#define GPIO_FUNC39_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC39_IN_INV_SEL_S 5 -/** GPIO_SIG39_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG39_IN_SEL (BIT(6)) -#define GPIO_SIG39_IN_SEL_M (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S) -#define GPIO_SIG39_IN_SEL_V 0x00000001U -#define GPIO_SIG39_IN_SEL_S 6 - -/** GPIO_FUNC40_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) -/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC40_IN_SEL 0x0000001FU -#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) -#define GPIO_FUNC40_IN_SEL_V 0x0000001FU -#define GPIO_FUNC40_IN_SEL_S 0 -/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) -#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC40_IN_INV_SEL_S 5 -/** GPIO_SIG40_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG40_IN_SEL (BIT(6)) -#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) -#define GPIO_SIG40_IN_SEL_V 0x00000001U -#define GPIO_SIG40_IN_SEL_S 6 - -/** GPIO_FUNC41_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) -/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC41_IN_SEL 0x0000001FU -#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) -#define GPIO_FUNC41_IN_SEL_V 0x0000001FU -#define GPIO_FUNC41_IN_SEL_S 0 -/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) -#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC41_IN_INV_SEL_S 5 -/** GPIO_SIG41_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG41_IN_SEL (BIT(6)) -#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) -#define GPIO_SIG41_IN_SEL_V 0x00000001U -#define GPIO_SIG41_IN_SEL_S 6 - -/** GPIO_FUNC42_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) -/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC42_IN_SEL 0x0000001FU -#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) -#define GPIO_FUNC42_IN_SEL_V 0x0000001FU -#define GPIO_FUNC42_IN_SEL_S 0 -/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) -#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC42_IN_INV_SEL_S 5 -/** GPIO_SIG42_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG42_IN_SEL (BIT(6)) -#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) -#define GPIO_SIG42_IN_SEL_V 0x00000001U -#define GPIO_SIG42_IN_SEL_S 6 - -/** GPIO_FUNC43_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) -/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC43_IN_SEL 0x0000001FU -#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) -#define GPIO_FUNC43_IN_SEL_V 0x0000001FU -#define GPIO_FUNC43_IN_SEL_S 0 -/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) -#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC43_IN_INV_SEL_S 5 -/** GPIO_SIG43_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG43_IN_SEL (BIT(6)) -#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) -#define GPIO_SIG43_IN_SEL_V 0x00000001U -#define GPIO_SIG43_IN_SEL_S 6 - -/** GPIO_FUNC44_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) -/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC44_IN_SEL 0x0000001FU -#define GPIO_FUNC44_IN_SEL_M (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S) -#define GPIO_FUNC44_IN_SEL_V 0x0000001FU -#define GPIO_FUNC44_IN_SEL_S 0 -/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC44_IN_INV_SEL_M (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S) -#define GPIO_FUNC44_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC44_IN_INV_SEL_S 5 -/** GPIO_SIG44_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG44_IN_SEL (BIT(6)) -#define GPIO_SIG44_IN_SEL_M (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S) -#define GPIO_SIG44_IN_SEL_V 0x00000001U -#define GPIO_SIG44_IN_SEL_S 6 - -/** GPIO_FUNC45_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) -/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC45_IN_SEL 0x0000001FU -#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) -#define GPIO_FUNC45_IN_SEL_V 0x0000001FU -#define GPIO_FUNC45_IN_SEL_S 0 -/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) -#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC45_IN_INV_SEL_S 5 -/** GPIO_SIG45_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG45_IN_SEL (BIT(6)) -#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) -#define GPIO_SIG45_IN_SEL_V 0x00000001U -#define GPIO_SIG45_IN_SEL_S 6 - -/** GPIO_FUNC46_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) -/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC46_IN_SEL 0x0000001FU -#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) -#define GPIO_FUNC46_IN_SEL_V 0x0000001FU -#define GPIO_FUNC46_IN_SEL_S 0 -/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) -#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC46_IN_INV_SEL_S 5 -/** GPIO_SIG46_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG46_IN_SEL (BIT(6)) -#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) -#define GPIO_SIG46_IN_SEL_V 0x00000001U -#define GPIO_SIG46_IN_SEL_S 6 - -/** GPIO_FUNC47_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) -/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC47_IN_SEL 0x0000001FU -#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) -#define GPIO_FUNC47_IN_SEL_V 0x0000001FU -#define GPIO_FUNC47_IN_SEL_S 0 -/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) -#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC47_IN_INV_SEL_S 5 -/** GPIO_SIG47_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG47_IN_SEL (BIT(6)) -#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) -#define GPIO_SIG47_IN_SEL_V 0x00000001U -#define GPIO_SIG47_IN_SEL_S 6 - -/** GPIO_FUNC48_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) -/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC48_IN_SEL 0x0000001FU -#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) -#define GPIO_FUNC48_IN_SEL_V 0x0000001FU -#define GPIO_FUNC48_IN_SEL_S 0 -/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) -#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC48_IN_INV_SEL_S 5 -/** GPIO_SIG48_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG48_IN_SEL (BIT(6)) -#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) -#define GPIO_SIG48_IN_SEL_V 0x00000001U -#define GPIO_SIG48_IN_SEL_S 6 - -/** GPIO_FUNC49_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) -/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC49_IN_SEL 0x0000001FU -#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) -#define GPIO_FUNC49_IN_SEL_V 0x0000001FU -#define GPIO_FUNC49_IN_SEL_S 0 -/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) -#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC49_IN_INV_SEL_S 5 -/** GPIO_SIG49_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG49_IN_SEL (BIT(6)) -#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) -#define GPIO_SIG49_IN_SEL_V 0x00000001U -#define GPIO_SIG49_IN_SEL_S 6 - -/** GPIO_FUNC50_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) -/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC50_IN_SEL 0x0000001FU -#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) -#define GPIO_FUNC50_IN_SEL_V 0x0000001FU -#define GPIO_FUNC50_IN_SEL_S 0 -/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) -#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC50_IN_INV_SEL_S 5 -/** GPIO_SIG50_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG50_IN_SEL (BIT(6)) -#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) -#define GPIO_SIG50_IN_SEL_V 0x00000001U -#define GPIO_SIG50_IN_SEL_S 6 - -/** GPIO_FUNC51_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) -/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC51_IN_SEL 0x0000001FU -#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) -#define GPIO_FUNC51_IN_SEL_V 0x0000001FU -#define GPIO_FUNC51_IN_SEL_S 0 -/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) -#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC51_IN_INV_SEL_S 5 -/** GPIO_SIG51_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG51_IN_SEL (BIT(6)) -#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) -#define GPIO_SIG51_IN_SEL_V 0x00000001U -#define GPIO_SIG51_IN_SEL_S 6 - -/** GPIO_FUNC52_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) -/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC52_IN_SEL 0x0000001FU -#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) -#define GPIO_FUNC52_IN_SEL_V 0x0000001FU -#define GPIO_FUNC52_IN_SEL_S 0 -/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) -#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC52_IN_INV_SEL_S 5 -/** GPIO_SIG52_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG52_IN_SEL (BIT(6)) -#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) -#define GPIO_SIG52_IN_SEL_V 0x00000001U -#define GPIO_SIG52_IN_SEL_S 6 - -/** GPIO_FUNC53_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) -/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC53_IN_SEL 0x0000001FU -#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) -#define GPIO_FUNC53_IN_SEL_V 0x0000001FU -#define GPIO_FUNC53_IN_SEL_S 0 -/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) -#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC53_IN_INV_SEL_S 5 -/** GPIO_SIG53_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG53_IN_SEL (BIT(6)) -#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) -#define GPIO_SIG53_IN_SEL_V 0x00000001U -#define GPIO_SIG53_IN_SEL_S 6 - -/** GPIO_FUNC54_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) -/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC54_IN_SEL 0x0000001FU -#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) -#define GPIO_FUNC54_IN_SEL_V 0x0000001FU -#define GPIO_FUNC54_IN_SEL_S 0 -/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) -#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC54_IN_INV_SEL_S 5 -/** GPIO_SIG54_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG54_IN_SEL (BIT(6)) -#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) -#define GPIO_SIG54_IN_SEL_V 0x00000001U -#define GPIO_SIG54_IN_SEL_S 6 - -/** GPIO_FUNC55_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) -/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC55_IN_SEL 0x0000001FU -#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) -#define GPIO_FUNC55_IN_SEL_V 0x0000001FU -#define GPIO_FUNC55_IN_SEL_S 0 -/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) -#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC55_IN_INV_SEL_S 5 -/** GPIO_SIG55_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG55_IN_SEL (BIT(6)) -#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) -#define GPIO_SIG55_IN_SEL_V 0x00000001U -#define GPIO_SIG55_IN_SEL_S 6 - -/** GPIO_FUNC56_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) -/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC56_IN_SEL 0x0000001FU -#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) -#define GPIO_FUNC56_IN_SEL_V 0x0000001FU -#define GPIO_FUNC56_IN_SEL_S 0 -/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) -#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC56_IN_INV_SEL_S 5 -/** GPIO_SIG56_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG56_IN_SEL (BIT(6)) -#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) -#define GPIO_SIG56_IN_SEL_V 0x00000001U -#define GPIO_SIG56_IN_SEL_S 6 - -/** GPIO_FUNC57_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) -/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC57_IN_SEL 0x0000001FU -#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) -#define GPIO_FUNC57_IN_SEL_V 0x0000001FU -#define GPIO_FUNC57_IN_SEL_S 0 -/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) -#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC57_IN_INV_SEL_S 5 -/** GPIO_SIG57_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG57_IN_SEL (BIT(6)) -#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) -#define GPIO_SIG57_IN_SEL_V 0x00000001U -#define GPIO_SIG57_IN_SEL_S 6 - -/** GPIO_FUNC58_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) -/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC58_IN_SEL 0x0000001FU -#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) -#define GPIO_FUNC58_IN_SEL_V 0x0000001FU -#define GPIO_FUNC58_IN_SEL_S 0 -/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) -#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC58_IN_INV_SEL_S 5 -/** GPIO_SIG58_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG58_IN_SEL (BIT(6)) -#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) -#define GPIO_SIG58_IN_SEL_V 0x00000001U -#define GPIO_SIG58_IN_SEL_S 6 - -/** GPIO_FUNC59_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) -/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC59_IN_SEL 0x0000001FU -#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) -#define GPIO_FUNC59_IN_SEL_V 0x0000001FU -#define GPIO_FUNC59_IN_SEL_S 0 -/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) -#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC59_IN_INV_SEL_S 5 -/** GPIO_SIG59_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG59_IN_SEL (BIT(6)) -#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) -#define GPIO_SIG59_IN_SEL_V 0x00000001U -#define GPIO_SIG59_IN_SEL_S 6 - -/** GPIO_FUNC60_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) -/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC60_IN_SEL 0x0000001FU -#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) -#define GPIO_FUNC60_IN_SEL_V 0x0000001FU -#define GPIO_FUNC60_IN_SEL_S 0 -/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) -#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC60_IN_INV_SEL_S 5 -/** GPIO_SIG60_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG60_IN_SEL (BIT(6)) -#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) -#define GPIO_SIG60_IN_SEL_V 0x00000001U -#define GPIO_SIG60_IN_SEL_S 6 - -/** GPIO_FUNC61_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) -/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC61_IN_SEL 0x0000001FU -#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) -#define GPIO_FUNC61_IN_SEL_V 0x0000001FU -#define GPIO_FUNC61_IN_SEL_S 0 -/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) -#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC61_IN_INV_SEL_S 5 -/** GPIO_SIG61_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG61_IN_SEL (BIT(6)) -#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) -#define GPIO_SIG61_IN_SEL_V 0x00000001U -#define GPIO_SIG61_IN_SEL_S 6 - -/** GPIO_FUNC62_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) -/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC62_IN_SEL 0x0000001FU -#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) -#define GPIO_FUNC62_IN_SEL_V 0x0000001FU -#define GPIO_FUNC62_IN_SEL_S 0 -/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) -#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC62_IN_INV_SEL_S 5 -/** GPIO_SIG62_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG62_IN_SEL (BIT(6)) -#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) -#define GPIO_SIG62_IN_SEL_V 0x00000001U -#define GPIO_SIG62_IN_SEL_S 6 - -/** GPIO_FUNC63_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) -/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC63_IN_SEL 0x0000001FU -#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) -#define GPIO_FUNC63_IN_SEL_V 0x0000001FU -#define GPIO_FUNC63_IN_SEL_S 0 -/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) -#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC63_IN_INV_SEL_S 5 -/** GPIO_SIG63_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG63_IN_SEL (BIT(6)) -#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) -#define GPIO_SIG63_IN_SEL_V 0x00000001U -#define GPIO_SIG63_IN_SEL_S 6 - -/** GPIO_FUNC64_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) -/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC64_IN_SEL 0x0000001FU -#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) -#define GPIO_FUNC64_IN_SEL_V 0x0000001FU -#define GPIO_FUNC64_IN_SEL_S 0 -/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) -#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC64_IN_INV_SEL_S 5 -/** GPIO_SIG64_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG64_IN_SEL (BIT(6)) -#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) -#define GPIO_SIG64_IN_SEL_V 0x00000001U -#define GPIO_SIG64_IN_SEL_S 6 - -/** GPIO_FUNC65_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) -/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC65_IN_SEL 0x0000001FU -#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) -#define GPIO_FUNC65_IN_SEL_V 0x0000001FU -#define GPIO_FUNC65_IN_SEL_S 0 -/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) -#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC65_IN_INV_SEL_S 5 -/** GPIO_SIG65_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG65_IN_SEL (BIT(6)) -#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) -#define GPIO_SIG65_IN_SEL_V 0x00000001U -#define GPIO_SIG65_IN_SEL_S 6 - -/** GPIO_FUNC66_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) -/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC66_IN_SEL 0x0000001FU -#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) -#define GPIO_FUNC66_IN_SEL_V 0x0000001FU -#define GPIO_FUNC66_IN_SEL_S 0 -/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) -#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC66_IN_INV_SEL_S 5 -/** GPIO_SIG66_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG66_IN_SEL (BIT(6)) -#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) -#define GPIO_SIG66_IN_SEL_V 0x00000001U -#define GPIO_SIG66_IN_SEL_S 6 - -/** GPIO_FUNC67_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) -/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC67_IN_SEL 0x0000001FU -#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) -#define GPIO_FUNC67_IN_SEL_V 0x0000001FU -#define GPIO_FUNC67_IN_SEL_S 0 -/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) -#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC67_IN_INV_SEL_S 5 -/** GPIO_SIG67_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG67_IN_SEL (BIT(6)) -#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) -#define GPIO_SIG67_IN_SEL_V 0x00000001U -#define GPIO_SIG67_IN_SEL_S 6 - -/** GPIO_FUNC68_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) -/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC68_IN_SEL 0x0000001FU -#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) -#define GPIO_FUNC68_IN_SEL_V 0x0000001FU -#define GPIO_FUNC68_IN_SEL_S 0 -/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) -#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC68_IN_INV_SEL_S 5 -/** GPIO_SIG68_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG68_IN_SEL (BIT(6)) -#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) -#define GPIO_SIG68_IN_SEL_V 0x00000001U -#define GPIO_SIG68_IN_SEL_S 6 - -/** GPIO_FUNC69_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) -/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC69_IN_SEL 0x0000001FU -#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) -#define GPIO_FUNC69_IN_SEL_V 0x0000001FU -#define GPIO_FUNC69_IN_SEL_S 0 -/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) -#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC69_IN_INV_SEL_S 5 -/** GPIO_SIG69_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG69_IN_SEL (BIT(6)) -#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) -#define GPIO_SIG69_IN_SEL_V 0x00000001U -#define GPIO_SIG69_IN_SEL_S 6 - -/** GPIO_FUNC70_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) -/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC70_IN_SEL 0x0000001FU -#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) -#define GPIO_FUNC70_IN_SEL_V 0x0000001FU -#define GPIO_FUNC70_IN_SEL_S 0 -/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) -#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC70_IN_INV_SEL_S 5 -/** GPIO_SIG70_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG70_IN_SEL (BIT(6)) -#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) -#define GPIO_SIG70_IN_SEL_V 0x00000001U -#define GPIO_SIG70_IN_SEL_S 6 - -/** GPIO_FUNC71_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) -/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC71_IN_SEL 0x0000001FU -#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) -#define GPIO_FUNC71_IN_SEL_V 0x0000001FU -#define GPIO_FUNC71_IN_SEL_S 0 -/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) -#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC71_IN_INV_SEL_S 5 -/** GPIO_SIG71_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG71_IN_SEL (BIT(6)) -#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) -#define GPIO_SIG71_IN_SEL_V 0x00000001U -#define GPIO_SIG71_IN_SEL_S 6 - -/** GPIO_FUNC72_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) -/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC72_IN_SEL 0x0000001FU -#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) -#define GPIO_FUNC72_IN_SEL_V 0x0000001FU -#define GPIO_FUNC72_IN_SEL_S 0 -/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) -#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC72_IN_INV_SEL_S 5 -/** GPIO_SIG72_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG72_IN_SEL (BIT(6)) -#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) -#define GPIO_SIG72_IN_SEL_V 0x00000001U -#define GPIO_SIG72_IN_SEL_S 6 - -/** GPIO_FUNC73_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) -/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC73_IN_SEL 0x0000001FU -#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) -#define GPIO_FUNC73_IN_SEL_V 0x0000001FU -#define GPIO_FUNC73_IN_SEL_S 0 -/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) -#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC73_IN_INV_SEL_S 5 -/** GPIO_SIG73_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG73_IN_SEL (BIT(6)) -#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) -#define GPIO_SIG73_IN_SEL_V 0x00000001U -#define GPIO_SIG73_IN_SEL_S 6 - -/** GPIO_FUNC74_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) -/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC74_IN_SEL 0x0000001FU -#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) -#define GPIO_FUNC74_IN_SEL_V 0x0000001FU -#define GPIO_FUNC74_IN_SEL_S 0 -/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) -#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC74_IN_INV_SEL_S 5 -/** GPIO_SIG74_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG74_IN_SEL (BIT(6)) -#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) -#define GPIO_SIG74_IN_SEL_V 0x00000001U -#define GPIO_SIG74_IN_SEL_S 6 - -/** GPIO_FUNC75_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) -/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC75_IN_SEL 0x0000001FU -#define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) -#define GPIO_FUNC75_IN_SEL_V 0x0000001FU -#define GPIO_FUNC75_IN_SEL_S 0 -/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) -#define GPIO_FUNC75_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC75_IN_INV_SEL_S 5 -/** GPIO_SIG75_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG75_IN_SEL (BIT(6)) -#define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) -#define GPIO_SIG75_IN_SEL_V 0x00000001U -#define GPIO_SIG75_IN_SEL_S 6 - -/** GPIO_FUNC76_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) -/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC76_IN_SEL 0x0000001FU -#define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) -#define GPIO_FUNC76_IN_SEL_V 0x0000001FU -#define GPIO_FUNC76_IN_SEL_S 0 -/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) -#define GPIO_FUNC76_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC76_IN_INV_SEL_S 5 -/** GPIO_SIG76_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG76_IN_SEL (BIT(6)) -#define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) -#define GPIO_SIG76_IN_SEL_V 0x00000001U -#define GPIO_SIG76_IN_SEL_S 6 - -/** GPIO_FUNC77_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) -/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC77_IN_SEL 0x0000001FU -#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) -#define GPIO_FUNC77_IN_SEL_V 0x0000001FU -#define GPIO_FUNC77_IN_SEL_S 0 -/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) -#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC77_IN_INV_SEL_S 5 -/** GPIO_SIG77_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG77_IN_SEL (BIT(6)) -#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) -#define GPIO_SIG77_IN_SEL_V 0x00000001U -#define GPIO_SIG77_IN_SEL_S 6 - -/** GPIO_FUNC78_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) -/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC78_IN_SEL 0x0000001FU -#define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) -#define GPIO_FUNC78_IN_SEL_V 0x0000001FU -#define GPIO_FUNC78_IN_SEL_S 0 -/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) -#define GPIO_FUNC78_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC78_IN_INV_SEL_S 5 -/** GPIO_SIG78_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG78_IN_SEL (BIT(6)) -#define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) -#define GPIO_SIG78_IN_SEL_V 0x00000001U -#define GPIO_SIG78_IN_SEL_S 6 - -/** GPIO_FUNC79_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) -/** GPIO_FUNC79_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC79_IN_SEL 0x0000001FU -#define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) -#define GPIO_FUNC79_IN_SEL_V 0x0000001FU -#define GPIO_FUNC79_IN_SEL_S 0 -/** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) -#define GPIO_FUNC79_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC79_IN_INV_SEL_S 5 -/** GPIO_SIG79_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG79_IN_SEL (BIT(6)) -#define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) -#define GPIO_SIG79_IN_SEL_V 0x00000001U -#define GPIO_SIG79_IN_SEL_S 6 - -/** GPIO_FUNC80_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) -/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC80_IN_SEL 0x0000001FU -#define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) -#define GPIO_FUNC80_IN_SEL_V 0x0000001FU -#define GPIO_FUNC80_IN_SEL_S 0 -/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) -#define GPIO_FUNC80_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC80_IN_INV_SEL_S 5 -/** GPIO_SIG80_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG80_IN_SEL (BIT(6)) -#define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) -#define GPIO_SIG80_IN_SEL_V 0x00000001U -#define GPIO_SIG80_IN_SEL_S 6 - -/** GPIO_FUNC81_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) -/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC81_IN_SEL 0x0000001FU -#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) -#define GPIO_FUNC81_IN_SEL_V 0x0000001FU -#define GPIO_FUNC81_IN_SEL_S 0 -/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) -#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC81_IN_INV_SEL_S 5 -/** GPIO_SIG81_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG81_IN_SEL (BIT(6)) -#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) -#define GPIO_SIG81_IN_SEL_V 0x00000001U -#define GPIO_SIG81_IN_SEL_S 6 - -/** GPIO_FUNC82_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) -/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC82_IN_SEL 0x0000001FU -#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) -#define GPIO_FUNC82_IN_SEL_V 0x0000001FU -#define GPIO_FUNC82_IN_SEL_S 0 -/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) -#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC82_IN_INV_SEL_S 5 -/** GPIO_SIG82_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG82_IN_SEL (BIT(6)) -#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) -#define GPIO_SIG82_IN_SEL_V 0x00000001U -#define GPIO_SIG82_IN_SEL_S 6 - -/** GPIO_FUNC83_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) -/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC83_IN_SEL 0x0000001FU -#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) -#define GPIO_FUNC83_IN_SEL_V 0x0000001FU -#define GPIO_FUNC83_IN_SEL_S 0 -/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) -#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC83_IN_INV_SEL_S 5 -/** GPIO_SIG83_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG83_IN_SEL (BIT(6)) -#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) -#define GPIO_SIG83_IN_SEL_V 0x00000001U -#define GPIO_SIG83_IN_SEL_S 6 - -/** GPIO_FUNC84_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) -/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC84_IN_SEL 0x0000001FU -#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) -#define GPIO_FUNC84_IN_SEL_V 0x0000001FU -#define GPIO_FUNC84_IN_SEL_S 0 -/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) -#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC84_IN_INV_SEL_S 5 -/** GPIO_SIG84_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG84_IN_SEL (BIT(6)) -#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) -#define GPIO_SIG84_IN_SEL_V 0x00000001U -#define GPIO_SIG84_IN_SEL_S 6 - -/** GPIO_FUNC85_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) -/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC85_IN_SEL 0x0000001FU -#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) -#define GPIO_FUNC85_IN_SEL_V 0x0000001FU -#define GPIO_FUNC85_IN_SEL_S 0 -/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) -#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC85_IN_INV_SEL_S 5 -/** GPIO_SIG85_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG85_IN_SEL (BIT(6)) -#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) -#define GPIO_SIG85_IN_SEL_V 0x00000001U -#define GPIO_SIG85_IN_SEL_S 6 - -/** GPIO_FUNC86_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) -/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC86_IN_SEL 0x0000001FU -#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) -#define GPIO_FUNC86_IN_SEL_V 0x0000001FU -#define GPIO_FUNC86_IN_SEL_S 0 -/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) -#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC86_IN_INV_SEL_S 5 -/** GPIO_SIG86_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG86_IN_SEL (BIT(6)) -#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) -#define GPIO_SIG86_IN_SEL_V 0x00000001U -#define GPIO_SIG86_IN_SEL_S 6 - -/** GPIO_FUNC87_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) -/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC87_IN_SEL 0x0000001FU -#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) -#define GPIO_FUNC87_IN_SEL_V 0x0000001FU -#define GPIO_FUNC87_IN_SEL_S 0 -/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) -#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC87_IN_INV_SEL_S 5 -/** GPIO_SIG87_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG87_IN_SEL (BIT(6)) -#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) -#define GPIO_SIG87_IN_SEL_V 0x00000001U -#define GPIO_SIG87_IN_SEL_S 6 - -/** GPIO_FUNC88_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) -/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC88_IN_SEL 0x0000001FU -#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) -#define GPIO_FUNC88_IN_SEL_V 0x0000001FU -#define GPIO_FUNC88_IN_SEL_S 0 -/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) -#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC88_IN_INV_SEL_S 5 -/** GPIO_SIG88_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG88_IN_SEL (BIT(6)) -#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) -#define GPIO_SIG88_IN_SEL_V 0x00000001U -#define GPIO_SIG88_IN_SEL_S 6 - -/** GPIO_FUNC89_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) -/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC89_IN_SEL 0x0000001FU -#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) -#define GPIO_FUNC89_IN_SEL_V 0x0000001FU -#define GPIO_FUNC89_IN_SEL_S 0 -/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) -#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC89_IN_INV_SEL_S 5 -/** GPIO_SIG89_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG89_IN_SEL (BIT(6)) -#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) -#define GPIO_SIG89_IN_SEL_V 0x00000001U -#define GPIO_SIG89_IN_SEL_S 6 - -/** GPIO_FUNC90_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) -/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC90_IN_SEL 0x0000001FU -#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) -#define GPIO_FUNC90_IN_SEL_V 0x0000001FU -#define GPIO_FUNC90_IN_SEL_S 0 -/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) -#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC90_IN_INV_SEL_S 5 -/** GPIO_SIG90_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG90_IN_SEL (BIT(6)) -#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) -#define GPIO_SIG90_IN_SEL_V 0x00000001U -#define GPIO_SIG90_IN_SEL_S 6 - -/** GPIO_FUNC91_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) -/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC91_IN_SEL 0x0000001FU -#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) -#define GPIO_FUNC91_IN_SEL_V 0x0000001FU -#define GPIO_FUNC91_IN_SEL_S 0 -/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) -#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC91_IN_INV_SEL_S 5 -/** GPIO_SIG91_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG91_IN_SEL (BIT(6)) -#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) -#define GPIO_SIG91_IN_SEL_V 0x00000001U -#define GPIO_SIG91_IN_SEL_S 6 - -/** GPIO_FUNC92_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) -/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC92_IN_SEL 0x0000001FU -#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) -#define GPIO_FUNC92_IN_SEL_V 0x0000001FU -#define GPIO_FUNC92_IN_SEL_S 0 -/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) -#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC92_IN_INV_SEL_S 5 -/** GPIO_SIG92_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG92_IN_SEL (BIT(6)) -#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) -#define GPIO_SIG92_IN_SEL_V 0x00000001U -#define GPIO_SIG92_IN_SEL_S 6 - -/** GPIO_FUNC93_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) -/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC93_IN_SEL 0x0000001FU -#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) -#define GPIO_FUNC93_IN_SEL_V 0x0000001FU -#define GPIO_FUNC93_IN_SEL_S 0 -/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) -#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC93_IN_INV_SEL_S 5 -/** GPIO_SIG93_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG93_IN_SEL (BIT(6)) -#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) -#define GPIO_SIG93_IN_SEL_V 0x00000001U -#define GPIO_SIG93_IN_SEL_S 6 - -/** GPIO_FUNC94_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) -/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC94_IN_SEL 0x0000001FU -#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) -#define GPIO_FUNC94_IN_SEL_V 0x0000001FU -#define GPIO_FUNC94_IN_SEL_S 0 -/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) -#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC94_IN_INV_SEL_S 5 -/** GPIO_SIG94_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG94_IN_SEL (BIT(6)) -#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) -#define GPIO_SIG94_IN_SEL_V 0x00000001U -#define GPIO_SIG94_IN_SEL_S 6 - -/** GPIO_FUNC95_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) -/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC95_IN_SEL 0x0000001FU -#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) -#define GPIO_FUNC95_IN_SEL_V 0x0000001FU -#define GPIO_FUNC95_IN_SEL_S 0 -/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) -#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC95_IN_INV_SEL_S 5 -/** GPIO_SIG95_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG95_IN_SEL (BIT(6)) -#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) -#define GPIO_SIG95_IN_SEL_V 0x00000001U -#define GPIO_SIG95_IN_SEL_S 6 - -/** GPIO_FUNC96_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) -/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC96_IN_SEL 0x0000001FU -#define GPIO_FUNC96_IN_SEL_M (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S) -#define GPIO_FUNC96_IN_SEL_V 0x0000001FU -#define GPIO_FUNC96_IN_SEL_S 0 -/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC96_IN_INV_SEL_M (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S) -#define GPIO_FUNC96_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC96_IN_INV_SEL_S 5 -/** GPIO_SIG96_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG96_IN_SEL (BIT(6)) -#define GPIO_SIG96_IN_SEL_M (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S) -#define GPIO_SIG96_IN_SEL_V 0x00000001U -#define GPIO_SIG96_IN_SEL_S 6 - -/** GPIO_FUNC97_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) -/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC97_IN_SEL 0x0000001FU -#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) -#define GPIO_FUNC97_IN_SEL_V 0x0000001FU -#define GPIO_FUNC97_IN_SEL_S 0 -/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) -#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC97_IN_INV_SEL_S 5 -/** GPIO_SIG97_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG97_IN_SEL (BIT(6)) -#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) -#define GPIO_SIG97_IN_SEL_V 0x00000001U -#define GPIO_SIG97_IN_SEL_S 6 - -/** GPIO_FUNC98_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) -/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC98_IN_SEL 0x0000001FU -#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) -#define GPIO_FUNC98_IN_SEL_V 0x0000001FU -#define GPIO_FUNC98_IN_SEL_S 0 -/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) -#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC98_IN_INV_SEL_S 5 -/** GPIO_SIG98_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG98_IN_SEL (BIT(6)) -#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) -#define GPIO_SIG98_IN_SEL_V 0x00000001U -#define GPIO_SIG98_IN_SEL_S 6 - -/** GPIO_FUNC99_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) -/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC99_IN_SEL 0x0000001FU -#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) -#define GPIO_FUNC99_IN_SEL_V 0x0000001FU -#define GPIO_FUNC99_IN_SEL_S 0 -/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) -#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC99_IN_INV_SEL_S 5 -/** GPIO_SIG99_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG99_IN_SEL (BIT(6)) -#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) -#define GPIO_SIG99_IN_SEL_V 0x00000001U -#define GPIO_SIG99_IN_SEL_S 6 - -/** GPIO_FUNC100_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) -/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC100_IN_SEL 0x0000001FU -#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) -#define GPIO_FUNC100_IN_SEL_V 0x0000001FU -#define GPIO_FUNC100_IN_SEL_S 0 -/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) -#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC100_IN_INV_SEL_S 5 -/** GPIO_SIG100_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG100_IN_SEL (BIT(6)) -#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) -#define GPIO_SIG100_IN_SEL_V 0x00000001U -#define GPIO_SIG100_IN_SEL_S 6 - -/** GPIO_FUNC101_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) -/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC101_IN_SEL 0x0000001FU -#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) -#define GPIO_FUNC101_IN_SEL_V 0x0000001FU -#define GPIO_FUNC101_IN_SEL_S 0 -/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) -#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC101_IN_INV_SEL_S 5 -/** GPIO_SIG101_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG101_IN_SEL (BIT(6)) -#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) -#define GPIO_SIG101_IN_SEL_V 0x00000001U -#define GPIO_SIG101_IN_SEL_S 6 - -/** GPIO_FUNC102_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) -/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC102_IN_SEL 0x0000001FU -#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) -#define GPIO_FUNC102_IN_SEL_V 0x0000001FU -#define GPIO_FUNC102_IN_SEL_S 0 -/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) -#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC102_IN_INV_SEL_S 5 -/** GPIO_SIG102_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG102_IN_SEL (BIT(6)) -#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) -#define GPIO_SIG102_IN_SEL_V 0x00000001U -#define GPIO_SIG102_IN_SEL_S 6 - -/** GPIO_FUNC103_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) -/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC103_IN_SEL 0x0000001FU -#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) -#define GPIO_FUNC103_IN_SEL_V 0x0000001FU -#define GPIO_FUNC103_IN_SEL_S 0 -/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) -#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC103_IN_INV_SEL_S 5 -/** GPIO_SIG103_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG103_IN_SEL (BIT(6)) -#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) -#define GPIO_SIG103_IN_SEL_V 0x00000001U -#define GPIO_SIG103_IN_SEL_S 6 - -/** GPIO_FUNC104_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) -/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC104_IN_SEL 0x0000001FU -#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) -#define GPIO_FUNC104_IN_SEL_V 0x0000001FU -#define GPIO_FUNC104_IN_SEL_S 0 -/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) -#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC104_IN_INV_SEL_S 5 -/** GPIO_SIG104_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG104_IN_SEL (BIT(6)) -#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) -#define GPIO_SIG104_IN_SEL_V 0x00000001U -#define GPIO_SIG104_IN_SEL_S 6 - -/** GPIO_FUNC105_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) -/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC105_IN_SEL 0x0000001FU -#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) -#define GPIO_FUNC105_IN_SEL_V 0x0000001FU -#define GPIO_FUNC105_IN_SEL_S 0 -/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) -#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC105_IN_INV_SEL_S 5 -/** GPIO_SIG105_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG105_IN_SEL (BIT(6)) -#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) -#define GPIO_SIG105_IN_SEL_V 0x00000001U -#define GPIO_SIG105_IN_SEL_S 6 - -/** GPIO_FUNC106_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) -/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC106_IN_SEL 0x0000001FU -#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) -#define GPIO_FUNC106_IN_SEL_V 0x0000001FU -#define GPIO_FUNC106_IN_SEL_S 0 -/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) -#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC106_IN_INV_SEL_S 5 -/** GPIO_SIG106_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG106_IN_SEL (BIT(6)) -#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) -#define GPIO_SIG106_IN_SEL_V 0x00000001U -#define GPIO_SIG106_IN_SEL_S 6 - -/** GPIO_FUNC107_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC107_IN_SEL 0x0000001FU -#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) -#define GPIO_FUNC107_IN_SEL_V 0x0000001FU -#define GPIO_FUNC107_IN_SEL_S 0 -/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) -#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC107_IN_INV_SEL_S 5 -/** GPIO_SIG107_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG107_IN_SEL (BIT(6)) -#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) -#define GPIO_SIG107_IN_SEL_V 0x00000001U -#define GPIO_SIG107_IN_SEL_S 6 - -/** GPIO_FUNC108_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC108_IN_SEL 0x0000001FU -#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) -#define GPIO_FUNC108_IN_SEL_V 0x0000001FU -#define GPIO_FUNC108_IN_SEL_S 0 -/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) -#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC108_IN_INV_SEL_S 5 -/** GPIO_SIG108_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG108_IN_SEL (BIT(6)) -#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) -#define GPIO_SIG108_IN_SEL_V 0x00000001U -#define GPIO_SIG108_IN_SEL_S 6 - -/** GPIO_FUNC109_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC109_IN_SEL 0x0000001FU -#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) -#define GPIO_FUNC109_IN_SEL_V 0x0000001FU -#define GPIO_FUNC109_IN_SEL_S 0 -/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) -#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC109_IN_INV_SEL_S 5 -/** GPIO_SIG109_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG109_IN_SEL (BIT(6)) -#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) -#define GPIO_SIG109_IN_SEL_V 0x00000001U -#define GPIO_SIG109_IN_SEL_S 6 - -/** GPIO_FUNC110_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) -/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC110_IN_SEL 0x0000001FU -#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) -#define GPIO_FUNC110_IN_SEL_V 0x0000001FU -#define GPIO_FUNC110_IN_SEL_S 0 -/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) -#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC110_IN_INV_SEL_S 5 -/** GPIO_SIG110_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG110_IN_SEL (BIT(6)) -#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) -#define GPIO_SIG110_IN_SEL_V 0x00000001U -#define GPIO_SIG110_IN_SEL_S 6 - -/** GPIO_FUNC111_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) -/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC111_IN_SEL 0x0000001FU -#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) -#define GPIO_FUNC111_IN_SEL_V 0x0000001FU -#define GPIO_FUNC111_IN_SEL_S 0 -/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) -#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC111_IN_INV_SEL_S 5 -/** GPIO_SIG111_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG111_IN_SEL (BIT(6)) -#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) -#define GPIO_SIG111_IN_SEL_V 0x00000001U -#define GPIO_SIG111_IN_SEL_S 6 - -/** GPIO_FUNC112_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) -/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC112_IN_SEL 0x0000001FU -#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) -#define GPIO_FUNC112_IN_SEL_V 0x0000001FU -#define GPIO_FUNC112_IN_SEL_S 0 -/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) -#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC112_IN_INV_SEL_S 5 -/** GPIO_SIG112_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG112_IN_SEL (BIT(6)) -#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) -#define GPIO_SIG112_IN_SEL_V 0x00000001U -#define GPIO_SIG112_IN_SEL_S 6 - -/** GPIO_FUNC113_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) -/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC113_IN_SEL 0x0000001FU -#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) -#define GPIO_FUNC113_IN_SEL_V 0x0000001FU -#define GPIO_FUNC113_IN_SEL_S 0 -/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) -#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC113_IN_INV_SEL_S 5 -/** GPIO_SIG113_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG113_IN_SEL (BIT(6)) -#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) -#define GPIO_SIG113_IN_SEL_V 0x00000001U -#define GPIO_SIG113_IN_SEL_S 6 - -/** GPIO_FUNC114_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) -/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC114_IN_SEL 0x0000001FU -#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) -#define GPIO_FUNC114_IN_SEL_V 0x0000001FU -#define GPIO_FUNC114_IN_SEL_S 0 -/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) -#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC114_IN_INV_SEL_S 5 -/** GPIO_SIG114_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG114_IN_SEL (BIT(6)) -#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) -#define GPIO_SIG114_IN_SEL_V 0x00000001U -#define GPIO_SIG114_IN_SEL_S 6 - -/** GPIO_FUNC115_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) -/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC115_IN_SEL 0x0000001FU -#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) -#define GPIO_FUNC115_IN_SEL_V 0x0000001FU -#define GPIO_FUNC115_IN_SEL_S 0 -/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) -#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC115_IN_INV_SEL_S 5 -/** GPIO_SIG115_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG115_IN_SEL (BIT(6)) -#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) -#define GPIO_SIG115_IN_SEL_V 0x00000001U -#define GPIO_SIG115_IN_SEL_S 6 - -/** GPIO_FUNC116_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) -/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC116_IN_SEL 0x0000001FU -#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) -#define GPIO_FUNC116_IN_SEL_V 0x0000001FU -#define GPIO_FUNC116_IN_SEL_S 0 -/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) -#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC116_IN_INV_SEL_S 5 -/** GPIO_SIG116_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG116_IN_SEL (BIT(6)) -#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) -#define GPIO_SIG116_IN_SEL_V 0x00000001U -#define GPIO_SIG116_IN_SEL_S 6 - -/** GPIO_FUNC117_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) -/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC117_IN_SEL 0x0000001FU -#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) -#define GPIO_FUNC117_IN_SEL_V 0x0000001FU -#define GPIO_FUNC117_IN_SEL_S 0 -/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) -#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC117_IN_INV_SEL_S 5 -/** GPIO_SIG117_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG117_IN_SEL (BIT(6)) -#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) -#define GPIO_SIG117_IN_SEL_V 0x00000001U -#define GPIO_SIG117_IN_SEL_S 6 - -/** GPIO_FUNC118_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) -/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC118_IN_SEL 0x0000001FU -#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) -#define GPIO_FUNC118_IN_SEL_V 0x0000001FU -#define GPIO_FUNC118_IN_SEL_S 0 -/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) -#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC118_IN_INV_SEL_S 5 -/** GPIO_SIG118_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG118_IN_SEL (BIT(6)) -#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) -#define GPIO_SIG118_IN_SEL_V 0x00000001U -#define GPIO_SIG118_IN_SEL_S 6 - -/** GPIO_FUNC119_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC119_IN_SEL 0x0000001FU -#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) -#define GPIO_FUNC119_IN_SEL_V 0x0000001FU -#define GPIO_FUNC119_IN_SEL_S 0 -/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) -#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC119_IN_INV_SEL_S 5 -/** GPIO_SIG119_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG119_IN_SEL (BIT(6)) -#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) -#define GPIO_SIG119_IN_SEL_V 0x00000001U -#define GPIO_SIG119_IN_SEL_S 6 - -/** GPIO_FUNC120_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC120_IN_SEL 0x0000001FU -#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) -#define GPIO_FUNC120_IN_SEL_V 0x0000001FU -#define GPIO_FUNC120_IN_SEL_S 0 -/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) -#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC120_IN_INV_SEL_S 5 -/** GPIO_SIG120_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG120_IN_SEL (BIT(6)) -#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) -#define GPIO_SIG120_IN_SEL_V 0x00000001U -#define GPIO_SIG120_IN_SEL_S 6 - -/** GPIO_FUNC121_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC121_IN_SEL 0x0000001FU -#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) -#define GPIO_FUNC121_IN_SEL_V 0x0000001FU -#define GPIO_FUNC121_IN_SEL_S 0 -/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) -#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC121_IN_INV_SEL_S 5 -/** GPIO_SIG121_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG121_IN_SEL (BIT(6)) -#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) -#define GPIO_SIG121_IN_SEL_V 0x00000001U -#define GPIO_SIG121_IN_SEL_S 6 - -/** GPIO_FUNC122_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) -/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC122_IN_SEL 0x0000001FU -#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) -#define GPIO_FUNC122_IN_SEL_V 0x0000001FU -#define GPIO_FUNC122_IN_SEL_S 0 -/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) -#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC122_IN_INV_SEL_S 5 -/** GPIO_SIG122_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG122_IN_SEL (BIT(6)) -#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) -#define GPIO_SIG122_IN_SEL_V 0x00000001U -#define GPIO_SIG122_IN_SEL_S 6 - -/** GPIO_FUNC123_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC123_IN_SEL 0x0000001FU -#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) -#define GPIO_FUNC123_IN_SEL_V 0x0000001FU -#define GPIO_FUNC123_IN_SEL_S 0 -/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) -#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC123_IN_INV_SEL_S 5 -/** GPIO_SIG123_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG123_IN_SEL (BIT(6)) -#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) -#define GPIO_SIG123_IN_SEL_V 0x00000001U -#define GPIO_SIG123_IN_SEL_S 6 - -/** GPIO_FUNC124_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC124_IN_SEL 0x0000001FU -#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) -#define GPIO_FUNC124_IN_SEL_V 0x0000001FU -#define GPIO_FUNC124_IN_SEL_S 0 -/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) -#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC124_IN_INV_SEL_S 5 -/** GPIO_SIG124_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG124_IN_SEL (BIT(6)) -#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) -#define GPIO_SIG124_IN_SEL_V 0x00000001U -#define GPIO_SIG124_IN_SEL_S 6 - -/** GPIO_FUNC125_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/** GPIO_FUNC125_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC125_IN_SEL 0x0000001FU -#define GPIO_FUNC125_IN_SEL_M (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S) -#define GPIO_FUNC125_IN_SEL_V 0x0000001FU -#define GPIO_FUNC125_IN_SEL_S 0 -/** GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC125_IN_INV_SEL_M (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S) -#define GPIO_FUNC125_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC125_IN_INV_SEL_S 5 -/** GPIO_SIG125_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG125_IN_SEL (BIT(6)) -#define GPIO_SIG125_IN_SEL_M (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S) -#define GPIO_SIG125_IN_SEL_V 0x00000001U -#define GPIO_SIG125_IN_SEL_S 6 - -/** GPIO_FUNC126_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) -/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC126_IN_SEL 0x0000001FU -#define GPIO_FUNC126_IN_SEL_M (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S) -#define GPIO_FUNC126_IN_SEL_V 0x0000001FU -#define GPIO_FUNC126_IN_SEL_S 0 -/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC126_IN_INV_SEL_M (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S) -#define GPIO_FUNC126_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC126_IN_INV_SEL_S 5 -/** GPIO_SIG126_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG126_IN_SEL (BIT(6)) -#define GPIO_SIG126_IN_SEL_M (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S) -#define GPIO_SIG126_IN_SEL_V 0x00000001U -#define GPIO_SIG126_IN_SEL_S 6 - -/** GPIO_FUNC127_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ -#define GPIO_FUNC127_IN_SEL 0x0000001FU -#define GPIO_FUNC127_IN_SEL_M (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S) -#define GPIO_FUNC127_IN_SEL_V 0x0000001FU -#define GPIO_FUNC127_IN_SEL_S 0 -/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC127_IN_INV_SEL_M (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S) -#define GPIO_FUNC127_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC127_IN_INV_SEL_S 5 -/** GPIO_SIG127_IN_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG127_IN_SEL (BIT(6)) -#define GPIO_SIG127_IN_SEL_M (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S) -#define GPIO_SIG127_IN_SEL_V 0x00000001U -#define GPIO_SIG127_IN_SEL_S 6 - -/** GPIO_FUNC0_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) -/** GPIO_FUNC0_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC0_OUT_SEL 0x000000FFU -#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) -#define GPIO_FUNC0_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC0_OUT_SEL_S 0 -/** GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) -#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_OUT_INV_SEL_S 8 -/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC0_OEN_SEL (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) -#define GPIO_FUNC0_OEN_SEL_V 0x00000001U -#define GPIO_FUNC0_OEN_SEL_S 9 -/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) -#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_OEN_INV_SEL_S 10 - -/** GPIO_FUNC1_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) -/** GPIO_FUNC1_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC1_OUT_SEL 0x000000FFU -#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) -#define GPIO_FUNC1_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC1_OUT_SEL_S 0 -/** GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) -#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC1_OUT_INV_SEL_S 8 -/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC1_OEN_SEL (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) -#define GPIO_FUNC1_OEN_SEL_V 0x00000001U -#define GPIO_FUNC1_OEN_SEL_S 9 -/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) -#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC1_OEN_INV_SEL_S 10 - -/** GPIO_FUNC2_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) -/** GPIO_FUNC2_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC2_OUT_SEL 0x000000FFU -#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) -#define GPIO_FUNC2_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC2_OUT_SEL_S 0 -/** GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) -#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC2_OUT_INV_SEL_S 8 -/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC2_OEN_SEL (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) -#define GPIO_FUNC2_OEN_SEL_V 0x00000001U -#define GPIO_FUNC2_OEN_SEL_S 9 -/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) -#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC2_OEN_INV_SEL_S 10 - -/** GPIO_FUNC3_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) -/** GPIO_FUNC3_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC3_OUT_SEL 0x000000FFU -#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) -#define GPIO_FUNC3_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC3_OUT_SEL_S 0 -/** GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) -#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC3_OUT_INV_SEL_S 8 -/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC3_OEN_SEL (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) -#define GPIO_FUNC3_OEN_SEL_V 0x00000001U -#define GPIO_FUNC3_OEN_SEL_S 9 -/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) -#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC3_OEN_INV_SEL_S 10 - -/** GPIO_FUNC4_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) -/** GPIO_FUNC4_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC4_OUT_SEL 0x000000FFU -#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) -#define GPIO_FUNC4_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC4_OUT_SEL_S 0 -/** GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) -#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC4_OUT_INV_SEL_S 8 -/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC4_OEN_SEL (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) -#define GPIO_FUNC4_OEN_SEL_V 0x00000001U -#define GPIO_FUNC4_OEN_SEL_S 9 -/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) -#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC4_OEN_INV_SEL_S 10 - -/** GPIO_FUNC5_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) -/** GPIO_FUNC5_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC5_OUT_SEL 0x000000FFU -#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) -#define GPIO_FUNC5_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC5_OUT_SEL_S 0 -/** GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) -#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC5_OUT_INV_SEL_S 8 -/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC5_OEN_SEL (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) -#define GPIO_FUNC5_OEN_SEL_V 0x00000001U -#define GPIO_FUNC5_OEN_SEL_S 9 -/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) -#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC5_OEN_INV_SEL_S 10 - -/** GPIO_FUNC6_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) -/** GPIO_FUNC6_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC6_OUT_SEL 0x000000FFU -#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) -#define GPIO_FUNC6_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC6_OUT_SEL_S 0 -/** GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) -#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_OUT_INV_SEL_S 8 -/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC6_OEN_SEL (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) -#define GPIO_FUNC6_OEN_SEL_V 0x00000001U -#define GPIO_FUNC6_OEN_SEL_S 9 -/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) -#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_OEN_INV_SEL_S 10 - -/** GPIO_FUNC7_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) -/** GPIO_FUNC7_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC7_OUT_SEL 0x000000FFU -#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) -#define GPIO_FUNC7_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC7_OUT_SEL_S 0 -/** GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) -#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_OUT_INV_SEL_S 8 -/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC7_OEN_SEL (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) -#define GPIO_FUNC7_OEN_SEL_V 0x00000001U -#define GPIO_FUNC7_OEN_SEL_S 9 -/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) -#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_OEN_INV_SEL_S 10 - -/** GPIO_FUNC8_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) -/** GPIO_FUNC8_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC8_OUT_SEL 0x000000FFU -#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) -#define GPIO_FUNC8_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC8_OUT_SEL_S 0 -/** GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) -#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_OUT_INV_SEL_S 8 -/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC8_OEN_SEL (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) -#define GPIO_FUNC8_OEN_SEL_V 0x00000001U -#define GPIO_FUNC8_OEN_SEL_S 9 -/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) -#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_OEN_INV_SEL_S 10 - -/** GPIO_FUNC9_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) -/** GPIO_FUNC9_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC9_OUT_SEL 0x000000FFU -#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) -#define GPIO_FUNC9_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC9_OUT_SEL_S 0 -/** GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) -#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_OUT_INV_SEL_S 8 -/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC9_OEN_SEL (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) -#define GPIO_FUNC9_OEN_SEL_V 0x00000001U -#define GPIO_FUNC9_OEN_SEL_S 9 -/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) -#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_OEN_INV_SEL_S 10 - -/** GPIO_FUNC10_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) -/** GPIO_FUNC10_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC10_OUT_SEL 0x000000FFU -#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) -#define GPIO_FUNC10_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC10_OUT_SEL_S 0 -/** GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) -#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_OUT_INV_SEL_S 8 -/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC10_OEN_SEL (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) -#define GPIO_FUNC10_OEN_SEL_V 0x00000001U -#define GPIO_FUNC10_OEN_SEL_S 9 -/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) -#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_OEN_INV_SEL_S 10 - -/** GPIO_FUNC11_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) -/** GPIO_FUNC11_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC11_OUT_SEL 0x000000FFU -#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) -#define GPIO_FUNC11_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC11_OUT_SEL_S 0 -/** GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) -#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_OUT_INV_SEL_S 8 -/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC11_OEN_SEL (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) -#define GPIO_FUNC11_OEN_SEL_V 0x00000001U -#define GPIO_FUNC11_OEN_SEL_S 9 -/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) -#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_OEN_INV_SEL_S 10 - -/** GPIO_FUNC12_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) -/** GPIO_FUNC12_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC12_OUT_SEL 0x000000FFU -#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) -#define GPIO_FUNC12_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC12_OUT_SEL_S 0 -/** GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) -#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_OUT_INV_SEL_S 8 -/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC12_OEN_SEL (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) -#define GPIO_FUNC12_OEN_SEL_V 0x00000001U -#define GPIO_FUNC12_OEN_SEL_S 9 -/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) -#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_OEN_INV_SEL_S 10 - -/** GPIO_FUNC13_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) -/** GPIO_FUNC13_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC13_OUT_SEL 0x000000FFU -#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) -#define GPIO_FUNC13_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC13_OUT_SEL_S 0 -/** GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) -#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_OUT_INV_SEL_S 8 -/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC13_OEN_SEL (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) -#define GPIO_FUNC13_OEN_SEL_V 0x00000001U -#define GPIO_FUNC13_OEN_SEL_S 9 -/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) -#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_OEN_INV_SEL_S 10 - -/** GPIO_FUNC14_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) -/** GPIO_FUNC14_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC14_OUT_SEL 0x000000FFU -#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) -#define GPIO_FUNC14_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC14_OUT_SEL_S 0 -/** GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) -#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_OUT_INV_SEL_S 8 -/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC14_OEN_SEL (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) -#define GPIO_FUNC14_OEN_SEL_V 0x00000001U -#define GPIO_FUNC14_OEN_SEL_S 9 -/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) -#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_OEN_INV_SEL_S 10 - -/** GPIO_FUNC15_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) -/** GPIO_FUNC15_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC15_OUT_SEL 0x000000FFU -#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) -#define GPIO_FUNC15_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC15_OUT_SEL_S 0 -/** GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) -#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_OUT_INV_SEL_S 8 -/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC15_OEN_SEL (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) -#define GPIO_FUNC15_OEN_SEL_V 0x00000001U -#define GPIO_FUNC15_OEN_SEL_S 9 -/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) -#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_OEN_INV_SEL_S 10 - -/** GPIO_FUNC16_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) -/** GPIO_FUNC16_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC16_OUT_SEL 0x000000FFU -#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) -#define GPIO_FUNC16_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC16_OUT_SEL_S 0 -/** GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) -#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_OUT_INV_SEL_S 8 -/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC16_OEN_SEL (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) -#define GPIO_FUNC16_OEN_SEL_V 0x00000001U -#define GPIO_FUNC16_OEN_SEL_S 9 -/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) -#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_OEN_INV_SEL_S 10 - -/** GPIO_FUNC17_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) -/** GPIO_FUNC17_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC17_OUT_SEL 0x000000FFU -#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) -#define GPIO_FUNC17_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC17_OUT_SEL_S 0 -/** GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) -#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_OUT_INV_SEL_S 8 -/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC17_OEN_SEL (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) -#define GPIO_FUNC17_OEN_SEL_V 0x00000001U -#define GPIO_FUNC17_OEN_SEL_S 9 -/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) -#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_OEN_INV_SEL_S 10 - -/** GPIO_FUNC18_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) -/** GPIO_FUNC18_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC18_OUT_SEL 0x000000FFU -#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) -#define GPIO_FUNC18_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC18_OUT_SEL_S 0 -/** GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) -#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC18_OUT_INV_SEL_S 8 -/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC18_OEN_SEL (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) -#define GPIO_FUNC18_OEN_SEL_V 0x00000001U -#define GPIO_FUNC18_OEN_SEL_S 9 -/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) -#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC18_OEN_INV_SEL_S 10 - -/** GPIO_FUNC19_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) -/** GPIO_FUNC19_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC19_OUT_SEL 0x000000FFU -#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) -#define GPIO_FUNC19_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC19_OUT_SEL_S 0 -/** GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) -#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC19_OUT_INV_SEL_S 8 -/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC19_OEN_SEL (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) -#define GPIO_FUNC19_OEN_SEL_V 0x00000001U -#define GPIO_FUNC19_OEN_SEL_S 9 -/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) -#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC19_OEN_INV_SEL_S 10 - -/** GPIO_FUNC20_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) -/** GPIO_FUNC20_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC20_OUT_SEL 0x000000FFU -#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) -#define GPIO_FUNC20_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC20_OUT_SEL_S 0 -/** GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) -#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC20_OUT_INV_SEL_S 8 -/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC20_OEN_SEL (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) -#define GPIO_FUNC20_OEN_SEL_V 0x00000001U -#define GPIO_FUNC20_OEN_SEL_S 9 -/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) -#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC20_OEN_INV_SEL_S 10 - -/** GPIO_FUNC21_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) -/** GPIO_FUNC21_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC21_OUT_SEL 0x000000FFU -#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) -#define GPIO_FUNC21_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC21_OUT_SEL_S 0 -/** GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) -#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC21_OUT_INV_SEL_S 8 -/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC21_OEN_SEL (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) -#define GPIO_FUNC21_OEN_SEL_V 0x00000001U -#define GPIO_FUNC21_OEN_SEL_S 9 -/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) -#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC21_OEN_INV_SEL_S 10 - -/** GPIO_FUNC22_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) -/** GPIO_FUNC22_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC22_OUT_SEL 0x000000FFU -#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) -#define GPIO_FUNC22_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC22_OUT_SEL_S 0 -/** GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) -#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC22_OUT_INV_SEL_S 8 -/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC22_OEN_SEL (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) -#define GPIO_FUNC22_OEN_SEL_V 0x00000001U -#define GPIO_FUNC22_OEN_SEL_S 9 -/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) -#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC22_OEN_INV_SEL_S 10 - -/** GPIO_FUNC23_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) -/** GPIO_FUNC23_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC23_OUT_SEL 0x000000FFU -#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) -#define GPIO_FUNC23_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC23_OUT_SEL_S 0 -/** GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) -#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC23_OUT_INV_SEL_S 8 -/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC23_OEN_SEL (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) -#define GPIO_FUNC23_OEN_SEL_V 0x00000001U -#define GPIO_FUNC23_OEN_SEL_S 9 -/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) -#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC23_OEN_INV_SEL_S 10 - -/** GPIO_FUNC24_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) -/** GPIO_FUNC24_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC24_OUT_SEL 0x000000FFU -#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) -#define GPIO_FUNC24_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC24_OUT_SEL_S 0 -/** GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) -#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC24_OUT_INV_SEL_S 8 -/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC24_OEN_SEL (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) -#define GPIO_FUNC24_OEN_SEL_V 0x00000001U -#define GPIO_FUNC24_OEN_SEL_S 9 -/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) -#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC24_OEN_INV_SEL_S 10 - -/** GPIO_FUNC25_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) -/** GPIO_FUNC25_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC25_OUT_SEL 0x000000FFU -#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) -#define GPIO_FUNC25_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC25_OUT_SEL_S 0 -/** GPIO_FUNC25_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) -#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC25_OUT_INV_SEL_S 8 -/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC25_OEN_SEL (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) -#define GPIO_FUNC25_OEN_SEL_V 0x00000001U -#define GPIO_FUNC25_OEN_SEL_S 9 -/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) -#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC25_OEN_INV_SEL_S 10 - -/** GPIO_FUNC26_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) -/** GPIO_FUNC26_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC26_OUT_SEL 0x000000FFU -#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) -#define GPIO_FUNC26_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC26_OUT_SEL_S 0 -/** GPIO_FUNC26_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC26_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) -#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC26_OUT_INV_SEL_S 8 -/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC26_OEN_SEL (BIT(9)) -#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) -#define GPIO_FUNC26_OEN_SEL_V 0x00000001U -#define GPIO_FUNC26_OEN_SEL_S 9 -/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC26_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) -#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC26_OEN_INV_SEL_S 10 - -/** GPIO_FUNC27_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) -/** GPIO_FUNC27_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC27_OUT_SEL 0x000000FFU -#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) -#define GPIO_FUNC27_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC27_OUT_SEL_S 0 -/** GPIO_FUNC27_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC27_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) -#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_OUT_INV_SEL_S 8 -/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC27_OEN_SEL (BIT(9)) -#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) -#define GPIO_FUNC27_OEN_SEL_V 0x00000001U -#define GPIO_FUNC27_OEN_SEL_S 9 -/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC27_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) -#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_OEN_INV_SEL_S 10 - -/** GPIO_FUNC28_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) -/** GPIO_FUNC28_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC28_OUT_SEL 0x000000FFU -#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) -#define GPIO_FUNC28_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC28_OUT_SEL_S 0 -/** GPIO_FUNC28_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC28_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) -#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_OUT_INV_SEL_S 8 -/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC28_OEN_SEL (BIT(9)) -#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) -#define GPIO_FUNC28_OEN_SEL_V 0x00000001U -#define GPIO_FUNC28_OEN_SEL_S 9 -/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC28_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) -#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_OEN_INV_SEL_S 10 - -/** GPIO_FUNC29_OUT_SEL_CFG_REG register - * GPIO output function select register - */ -#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) -/** GPIO_FUNC29_OUT_SEL : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ -#define GPIO_FUNC29_OUT_SEL 0x000000FFU -#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) -#define GPIO_FUNC29_OUT_SEL_V 0x000000FFU -#define GPIO_FUNC29_OUT_SEL_S 0 -/** GPIO_FUNC29_OUT_INV_SEL : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ -#define GPIO_FUNC29_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) -#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_OUT_INV_SEL_S 8 -/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ -#define GPIO_FUNC29_OEN_SEL (BIT(9)) -#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) -#define GPIO_FUNC29_OEN_SEL_V 0x00000001U -#define GPIO_FUNC29_OEN_SEL_S 9 -/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ -#define GPIO_FUNC29_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) -#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_OEN_INV_SEL_S 10 - -/** GPIO_CLOCK_GATE_REG register - * GPIO clock gate register - */ -#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) -/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; - * set this bit to enable GPIO clock gate - */ -#define GPIO_CLK_EN (BIT(0)) -#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) -#define GPIO_CLK_EN_V 0x00000001U -#define GPIO_CLK_EN_S 0 - -/** GPIO_REG_DATE_REG register - * GPIO version register - */ -#define GPIO_REG_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) -/** GPIO_REG_DATE : R/W; bitpos: [27:0]; default: 34640016; - * version register - */ -#define GPIO_REG_DATE 0x0FFFFFFFU -#define GPIO_REG_DATE_M (GPIO_REG_DATE_V << GPIO_REG_DATE_S) -#define GPIO_REG_DATE_V 0x0FFFFFFFU -#define GPIO_REG_DATE_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_GPIO_REG_H_ */ diff --git a/components/soc/esp32h4/include/rev2/soc/gpio_sd_reg.h b/components/soc/esp32h4/include/rev2/soc/gpio_sd_reg.h deleted file mode 100644 index 1a4a0daccf..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/gpio_sd_reg.h +++ /dev/null @@ -1,229 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** GPIO_SD_SIGMADELTA0_REG register - * Duty Cycle Configure Register of SDM0 - */ -#define GPIO_SD_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0) -/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIO_SD_SD0_IN 0x000000FFU -#define GPIO_SD_SD0_IN_M (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S) -#define GPIO_SD_SD0_IN_V 0x000000FFU -#define GPIO_SD_SD0_IN_S 0 -/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIO_SD_SD0_PRESCALE 0x000000FFU -#define GPIO_SD_SD0_PRESCALE_M (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S) -#define GPIO_SD_SD0_PRESCALE_V 0x000000FFU -#define GPIO_SD_SD0_PRESCALE_S 8 - -/** GPIO_SD_SIGMADELTA1_REG register - * Duty Cycle Configure Register of SDM1 - */ -#define GPIO_SD_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4) -/** GPIO_SD_SD1_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIO_SD_SD1_IN 0x000000FFU -#define GPIO_SD_SD1_IN_M (GPIO_SD_SD1_IN_V << GPIO_SD_SD1_IN_S) -#define GPIO_SD_SD1_IN_V 0x000000FFU -#define GPIO_SD_SD1_IN_S 0 -/** GPIO_SD_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIO_SD_SD1_PRESCALE 0x000000FFU -#define GPIO_SD_SD1_PRESCALE_M (GPIO_SD_SD1_PRESCALE_V << GPIO_SD_SD1_PRESCALE_S) -#define GPIO_SD_SD1_PRESCALE_V 0x000000FFU -#define GPIO_SD_SD1_PRESCALE_S 8 - -/** GPIO_SD_SIGMADELTA2_REG register - * Duty Cycle Configure Register of SDM2 - */ -#define GPIO_SD_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8) -/** GPIO_SD_SD2_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIO_SD_SD2_IN 0x000000FFU -#define GPIO_SD_SD2_IN_M (GPIO_SD_SD2_IN_V << GPIO_SD_SD2_IN_S) -#define GPIO_SD_SD2_IN_V 0x000000FFU -#define GPIO_SD_SD2_IN_S 0 -/** GPIO_SD_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIO_SD_SD2_PRESCALE 0x000000FFU -#define GPIO_SD_SD2_PRESCALE_M (GPIO_SD_SD2_PRESCALE_V << GPIO_SD_SD2_PRESCALE_S) -#define GPIO_SD_SD2_PRESCALE_V 0x000000FFU -#define GPIO_SD_SD2_PRESCALE_S 8 - -/** GPIO_SD_SIGMADELTA3_REG register - * Duty Cycle Configure Register of SDM3 - */ -#define GPIO_SD_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xc) -/** GPIO_SD_SD3_IN : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ -#define GPIO_SD_SD3_IN 0x000000FFU -#define GPIO_SD_SD3_IN_M (GPIO_SD_SD3_IN_V << GPIO_SD_SD3_IN_S) -#define GPIO_SD_SD3_IN_V 0x000000FFU -#define GPIO_SD_SD3_IN_S 0 -/** GPIO_SD_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ -#define GPIO_SD_SD3_PRESCALE 0x000000FFU -#define GPIO_SD_SD3_PRESCALE_M (GPIO_SD_SD3_PRESCALE_V << GPIO_SD_SD3_PRESCALE_S) -#define GPIO_SD_SD3_PRESCALE_V 0x000000FFU -#define GPIO_SD_SD3_PRESCALE_S 8 - -/** GPIO_SD_SIGMADELTA_CG_REG register - * Clock Gating Configure Register - */ -#define GPIO_SD_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20) -/** GPIO_SD_CLK_EN : R/W; bitpos: [31]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ -#define GPIO_SD_CLK_EN (BIT(31)) -#define GPIO_SD_CLK_EN_M (GPIO_SD_CLK_EN_V << GPIO_SD_CLK_EN_S) -#define GPIO_SD_CLK_EN_V 0x00000001U -#define GPIO_SD_CLK_EN_S 31 - -/** GPIO_SD_SIGMADELTA_MISC_REG register - * MISC Register - */ -#define GPIO_SD_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24) -/** GPIO_SD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; - * Clock enable bit of sigma delta modulation. - */ -#define GPIO_SD_FUNCTION_CLK_EN (BIT(30)) -#define GPIO_SD_FUNCTION_CLK_EN_M (GPIO_SD_FUNCTION_CLK_EN_V << GPIO_SD_FUNCTION_CLK_EN_S) -#define GPIO_SD_FUNCTION_CLK_EN_V 0x00000001U -#define GPIO_SD_FUNCTION_CLK_EN_S 30 -/** GPIO_SD_SPI_SWAP : R/W; bitpos: [31]; default: 0; - * Reserved. - */ -#define GPIO_SD_SPI_SWAP (BIT(31)) -#define GPIO_SD_SPI_SWAP_M (GPIO_SD_SPI_SWAP_V << GPIO_SD_SPI_SWAP_S) -#define GPIO_SD_SPI_SWAP_V 0x00000001U -#define GPIO_SD_SPI_SWAP_S 31 - -/** GPIO_SD_PAD_COMP_CONFIG_REG register - * PAD Compare configure Register - */ -#define GPIO_SD_PAD_COMP_CONFIG_REG (DR_REG_GPIO_SD_BASE + 0x28) -/** GPIO_SD_XPD_COMP : R/W; bitpos: [0]; default: 0; - * Pad compare enable bit. - */ -#define GPIO_SD_XPD_COMP (BIT(0)) -#define GPIO_SD_XPD_COMP_M (GPIO_SD_XPD_COMP_V << GPIO_SD_XPD_COMP_S) -#define GPIO_SD_XPD_COMP_V 0x00000001U -#define GPIO_SD_XPD_COMP_S 0 -/** GPIO_SD_MODE_COMP : R/W; bitpos: [1]; default: 0; - * 1 to enable external reference from PAD[0]. 0 to enable internal reference, - * meanwhile PAD[0] can be used as a regular GPIO. - */ -#define GPIO_SD_MODE_COMP (BIT(1)) -#define GPIO_SD_MODE_COMP_M (GPIO_SD_MODE_COMP_V << GPIO_SD_MODE_COMP_S) -#define GPIO_SD_MODE_COMP_V 0x00000001U -#define GPIO_SD_MODE_COMP_S 1 -/** GPIO_SD_DREF_COMP : R/W; bitpos: [4:2]; default: 0; - * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. - */ -#define GPIO_SD_DREF_COMP 0x00000007U -#define GPIO_SD_DREF_COMP_M (GPIO_SD_DREF_COMP_V << GPIO_SD_DREF_COMP_S) -#define GPIO_SD_DREF_COMP_V 0x00000007U -#define GPIO_SD_DREF_COMP_S 2 -/** GPIO_SD_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0; - * Zero Detect mode select. - */ -#define GPIO_SD_ZERO_DET_MODE 0x00000003U -#define GPIO_SD_ZERO_DET_MODE_M (GPIO_SD_ZERO_DET_MODE_V << GPIO_SD_ZERO_DET_MODE_S) -#define GPIO_SD_ZERO_DET_MODE_V 0x00000003U -#define GPIO_SD_ZERO_DET_MODE_S 5 - -/** GPIO_SD_PAD_COMP_FILTER_REG register - * Zero Detect filter Register - */ -#define GPIO_SD_PAD_COMP_FILTER_REG (DR_REG_GPIO_SD_BASE + 0x2c) -/** GPIO_SD_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0; - * Zero Detect filter cycle length - */ -#define GPIO_SD_ZERO_DET_FILTER_CNT 0xFFFFFFFFU -#define GPIO_SD_ZERO_DET_FILTER_CNT_M (GPIO_SD_ZERO_DET_FILTER_CNT_V << GPIO_SD_ZERO_DET_FILTER_CNT_S) -#define GPIO_SD_ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU -#define GPIO_SD_ZERO_DET_FILTER_CNT_S 0 - -/** GPIO_SD_INT_RAW_REG register - * GPIO_SD interrupt raw register - */ -#define GPIO_SD_INT_RAW_REG (DR_REG_GPIO_SD_BASE + 0x80) -/** GPIO_SD_PAD_COMP_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; - * Pad compare raw interrupt - */ -#define GPIO_SD_PAD_COMP_INT_RAW (BIT(0)) -#define GPIO_SD_PAD_COMP_INT_RAW_M (GPIO_SD_PAD_COMP_INT_RAW_V << GPIO_SD_PAD_COMP_INT_RAW_S) -#define GPIO_SD_PAD_COMP_INT_RAW_V 0x00000001U -#define GPIO_SD_PAD_COMP_INT_RAW_S 0 - -/** GPIO_SD_INT_ST_REG register - * GPIO_SD interrupt masked register - */ -#define GPIO_SD_INT_ST_REG (DR_REG_GPIO_SD_BASE + 0x84) -/** GPIO_SD_PAD_COMP_INT_ST : RO; bitpos: [0]; default: 0; - * Pad compare masked interrupt - */ -#define GPIO_SD_PAD_COMP_INT_ST (BIT(0)) -#define GPIO_SD_PAD_COMP_INT_ST_M (GPIO_SD_PAD_COMP_INT_ST_V << GPIO_SD_PAD_COMP_INT_ST_S) -#define GPIO_SD_PAD_COMP_INT_ST_V 0x00000001U -#define GPIO_SD_PAD_COMP_INT_ST_S 0 - -/** GPIO_SD_INT_ENA_REG register - * GPIO_SD interrupt enable register - */ -#define GPIO_SD_INT_ENA_REG (DR_REG_GPIO_SD_BASE + 0x88) -/** GPIO_SD_PAD_COMP_INT_ENA : R/W; bitpos: [0]; default: 0; - * Pad compare interrupt enable - */ -#define GPIO_SD_PAD_COMP_INT_ENA (BIT(0)) -#define GPIO_SD_PAD_COMP_INT_ENA_M (GPIO_SD_PAD_COMP_INT_ENA_V << GPIO_SD_PAD_COMP_INT_ENA_S) -#define GPIO_SD_PAD_COMP_INT_ENA_V 0x00000001U -#define GPIO_SD_PAD_COMP_INT_ENA_S 0 - -/** GPIO_SD_INT_CLR_REG register - * GPIO_SD interrupt clear register - */ -#define GPIO_SD_INT_CLR_REG (DR_REG_GPIO_SD_BASE + 0x8c) -/** GPIO_SD_PAD_COMP_INT_CLR : WT; bitpos: [0]; default: 0; - * Pad compare interrupt clear - */ -#define GPIO_SD_PAD_COMP_INT_CLR (BIT(0)) -#define GPIO_SD_PAD_COMP_INT_CLR_M (GPIO_SD_PAD_COMP_INT_CLR_V << GPIO_SD_PAD_COMP_INT_CLR_S) -#define GPIO_SD_PAD_COMP_INT_CLR_V 0x00000001U -#define GPIO_SD_PAD_COMP_INT_CLR_S 0 - -/** GPIO_SD_SIGMADELTA_VERSION_REG register - * Version Control Register - */ -#define GPIO_SD_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0xfc) -/** GPIO_SD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 34668848; - * Version control register. - */ -#define GPIO_SD_GPIO_SD_DATE 0x0FFFFFFFU -#define GPIO_SD_GPIO_SD_DATE_M (GPIO_SD_GPIO_SD_DATE_V << GPIO_SD_GPIO_SD_DATE_S) -#define GPIO_SD_GPIO_SD_DATE_V 0x0FFFFFFFU -#define GPIO_SD_GPIO_SD_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/gpio_sig_map.h b/components/soc/esp32h4/include/rev2/soc/gpio_sig_map.h deleted file mode 100644 index a28ad30654..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/gpio_sig_map.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_GPIO_SIG_MAP_H_ -#define _SOC_GPIO_SIG_MAP_H_ - -#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX -#define SPIQ_IN_IDX 0 -#define SPIQ_OUT_IDX 0 -#define SPID_IN_IDX 1 -#define SPID_OUT_IDX 1 -#define SPIHD_IN_IDX 2 -#define SPIHD_OUT_IDX 2 -#define SPIWP_IN_IDX 3 -#define SPIWP_OUT_IDX 3 -#define SPICLK_OUT_IDX 4 -#define SPICS0_OUT_IDX 5 -#define U0RXD_IN_IDX 6 -#define U0TXD_OUT_IDX 6 -#define U0CTS_IN_IDX 7 -#define U0RTS_OUT_IDX 7 -#define U0DSR_IN_IDX 8 -#define U0DTR_OUT_IDX 8 -#define U1RXD_IN_IDX 9 -#define U1TXD_OUT_IDX 9 -#define U1CTS_IN_IDX 10 -#define U1RTS_OUT_IDX 10 -#define U1DSR_IN_IDX 11 -#define U1DTR_OUT_IDX 11 -#define I2S_MCLK_IN_IDX 12 -#define I2S_MCLK_OUT_IDX 12 -#define I2SO_BCK_IN_IDX 13 -#define I2SO_BCK_OUT_IDX 13 -#define I2SO_WS_IN_IDX 14 -#define I2SO_WS_OUT_IDX 14 -#define I2SI_SD_IN_IDX 15 -#define I2SO_SD_OUT_IDX 15 -#define I2SI_BCK_IN_IDX 16 -#define I2SI_BCK_OUT_IDX 16 -#define I2SI_WS_IN_IDX 17 -#define I2SI_WS_OUT_IDX 17 -#define I2SO_SD1_OUT_IDX 18 -#define CPU_TESTBUS0_IDX 20 -#define CPU_TESTBUS1_IDX 21 -#define CPU_TESTBUS2_IDX 22 -#define CPU_TESTBUS3_IDX 23 -#define CPU_TESTBUS4_IDX 24 -#define CPU_TESTBUS5_IDX 25 -#define CPU_TESTBUS6_IDX 26 -#define CPU_TESTBUS7_IDX 27 -#define CPU_GPIO_IN0_IDX 28 -#define CPU_GPIO_OUT0_IDX 28 -#define CPU_GPIO_IN1_IDX 29 -#define CPU_GPIO_OUT1_IDX 29 -#define CPU_GPIO_IN2_IDX 30 -#define CPU_GPIO_OUT2_IDX 30 -#define CPU_GPIO_IN3_IDX 31 -#define CPU_GPIO_OUT3_IDX 31 -#define CPU_GPIO_IN4_IDX 32 -#define CPU_GPIO_OUT4_IDX 32 -#define CPU_GPIO_IN5_IDX 33 -#define CPU_GPIO_OUT5_IDX 33 -#define CPU_GPIO_IN6_IDX 34 -#define CPU_GPIO_OUT6_IDX 34 -#define CPU_GPIO_IN7_IDX 35 -#define CPU_GPIO_OUT7_IDX 35 -#define USB_JTAG_TCK_IDX 36 -#define USB_JTAG_TMS_IDX 37 -#define USB_JTAG_TDI_IDX 38 -#define USB_JTAG_TDO_IDX 39 -#define USB_EXTPHY_VP_IDX 40 -#define USB_EXTPHY_OEN_IDX 40 -#define USB_EXTPHY_VM_IDX 41 -#define USB_EXTPHY_SPEED_IDX 41 -#define USB_EXTPHY_RCV_IDX 42 -#define USB_EXTPHY_VPO_IDX 42 -#define USB_EXTPHY_VMO_IDX 43 -#define USB_EXTPHY_SUSPND_IDX 44 -#define EXT_ADC_START_IDX 45 -#define LEDC_LS_SIG_OUT0_IDX 45 -#define LEDC_LS_SIG_OUT1_IDX 46 -#define LEDC_LS_SIG_OUT2_IDX 47 -#define LEDC_LS_SIG_OUT3_IDX 48 -#define LEDC_LS_SIG_OUT4_IDX 49 -#define LEDC_LS_SIG_OUT5_IDX 50 -#define RMT_SIG_IN0_IDX 51 -#define RMT_SIG_OUT0_IDX 51 -#define RMT_SIG_IN1_IDX 52 -#define RMT_SIG_OUT1_IDX 52 -#define I2CEXT0_SCL_IN_IDX 53 -#define I2CEXT0_SCL_OUT_IDX 53 -#define I2CEXT0_SDA_IN_IDX 54 -#define I2CEXT0_SDA_OUT_IDX 54 -#define GPIO_SD0_OUT_IDX 55 -#define GPIO_SD1_OUT_IDX 56 -#define GPIO_SD2_OUT_IDX 57 -#define GPIO_SD3_OUT_IDX 58 -#define EVENT_MATRIX_IN0_IDX 59 -#define TASK_MATRIX_OUT0_IDX 59 -#define EVENT_MATRIX_IN1_IDX 60 -#define TASK_MATRIX_OUT1_IDX 60 -#define EVENT_MATRIX_IN2_IDX 61 -#define TASK_MATRIX_OUT2_IDX 61 -#define EVENT_MATRIX_IN3_IDX 62 -#define TASK_MATRIX_OUT3_IDX 62 -#define FSPICLK_IN_IDX 63 -#define FSPICLK_OUT_IDX 63 -#define FSPIQ_IN_IDX 64 -#define FSPIQ_OUT_IDX 64 -#define FSPID_IN_IDX 65 -#define FSPID_OUT_IDX 65 -#define FSPIHD_IN_IDX 66 -#define FSPIHD_OUT_IDX 66 -#define FSPIWP_IN_IDX 67 -#define FSPIWP_OUT_IDX 67 -#define FSPICS0_IN_IDX 68 -#define FSPICS0_OUT_IDX 68 -#define FSPICS1_OUT_IDX 69 -#define FSPICS2_OUT_IDX 70 -#define FSPICS3_OUT_IDX 71 -#define FSPICS4_OUT_IDX 72 -#define FSPICS5_OUT_IDX 73 -#define TWAI_RX_IDX 74 -#define TWAI_TX_IDX 74 -#define TWAI_BUS_OFF_ON_IDX 75 -#define TWAI_CLKOUT_IDX 76 -#define PCMFSYNC_IN_IDX 77 -#define PCMFSYNC_OUT_IDX 77 -#define PCMCLK_IN_IDX 78 -#define PCMCLK_OUT_IDX 78 -#define PCMDIN_IDX 79 -#define PCMDOUT_IDX 79 -#define CO_EXT_PRIORITY_IN_IDX 80 -#define CO_EXT_PRIORITY_OUT_IDX 80 -#define CO_EXT_ACTIVE_IN_IDX 81 -#define CO_EXT_ACTIVE_OUT_IDX 81 -#define MODEM_COEX_GRANT1_IDX 87 -#define MODEM_COEX_GRANT2_IDX 88 -#define ANT_SEL0_IDX 89 -#define ANT_SEL1_IDX 90 -#define ANT_SEL2_IDX 91 -#define ANT_SEL3_IDX 92 -#define ANT_SEL4_IDX 93 -#define ANT_SEL5_IDX 94 -#define ANT_SEL6_IDX 95 -#define ANT_SEL7_IDX 96 -#define SIG_IN_FUNC_97_IDX 97 -#define SIG_IN_FUNC97_IDX 97 -#define SIG_IN_FUNC_98_IDX 98 -#define SIG_IN_FUNC98_IDX 98 -#define SIG_IN_FUNC_99_IDX 99 -#define SIG_IN_FUNC99_IDX 99 -#define SIG_IN_FUNC_100_IDX 100 -#define SIG_IN_FUNC100_IDX 100 -#define SYNCERR_IDX 101 -#define SYNC_FOUND_IDX 102 -#define CH_IDX_IDX 103 -#define SYNC_WINDOW_IDX 104 -#define DATA_EN_IDX 105 -#define DATA_IDX 106 -#define PKT_TX_ON_IDX 107 -#define PKT_RX_ON_IDX 108 -#define TXRU_ON_IDX 109 -#define RXRU_ON_IDX 110 -#define LELC_ST3_IDX 111 -#define LELC_ST2_IDX 112 -#define LELC_ST1_IDX 113 -#define LELC_ST0_IDX 114 -#define CRCOK_IDX 115 -#define CLK_GPIO_IDX 116 -#define RADIO_START_IDX 117 -#define SEQUENCE_ON_IDX 118 -#define PUMP_CLK_IDX 119 -#define PUMP_XPD_IDX 120 -#define PUMP_DRV1_IDX 121 -#define PUMP_DRV0_IDX 122 -#define CLK_OUT_OUT1_IDX 123 -#define CLK_OUT_OUT2_IDX 124 -#define CLK_OUT_OUT3_IDX 125 -#define SPICS1_OUT_IDX 126 -#define USB_JTAG_TRST_IDX 127 -#define SIG_GPIO_OUT_IDX 128 -#define GPIO_MAP_DATE_IDX 0x2109090 -#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32h4/include/rev2/soc/gpio_struct.h b/components/soc/esp32h4/include/rev2/soc/gpio_struct.h deleted file mode 100644 index 7e1516e42c..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/gpio_struct.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: configuration register */ -/** Type of bt_select register - * GPIO bit select register - */ -typedef union { - struct { - /** bt_sel : R/W; bitpos: [31:0]; default: 0; - * GPIO bit select register - */ - uint32_t bt_sel:32; - }; - uint32_t val; -} gpio_bt_select_reg_t; - -/** Type of out register - * GPIO output register for GPIO0-29 - */ -typedef union { - struct { - /** out_data_orig : R/W/WS/WC; bitpos: [29:0]; default: 0; - * GPIO output register for GPIO0-29 - */ - uint32_t out_data_orig:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_out_reg_t; - -/** Type of out_w1ts register - * GPIO output set register for GPIO0-29 - */ -typedef union { - struct { - /** out_w1ts : WT; bitpos: [29:0]; default: 0; - * GPIO output set register for GPIO0-29 - */ - uint32_t out_w1ts:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_out_w1ts_reg_t; - -/** Type of out_w1tc register - * GPIO output clear register for GPIO0-29 - */ -typedef union { - struct { - /** out_w1tc : WT; bitpos: [29:0]; default: 0; - * GPIO output clear register for GPIO0-29 - */ - uint32_t out_w1tc:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_out_w1tc_reg_t; - -/** Type of sdio_select register - * GPIO sdio select register - */ -typedef union { - struct { - /** sdio_sel : R/W; bitpos: [7:0]; default: 0; - * GPIO sdio select register - */ - uint32_t sdio_sel:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_sdio_select_reg_t; - -/** Type of enable register - * GPIO output enable register for GPIO0-29 - */ -typedef union { - struct { - /** enable_data : R/W/SS; bitpos: [29:0]; default: 0; - * GPIO output enable register for GPIO0-29 - */ - uint32_t enable_data:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_enable_reg_t; - -/** Type of enable_w1ts register - * GPIO output enable set register for GPIO0-29 - */ -typedef union { - struct { - /** enable_w1ts : WT; bitpos: [29:0]; default: 0; - * GPIO output enable set register for GPIO0-29 - */ - uint32_t enable_w1ts:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_enable_w1ts_reg_t; - -/** Type of enable_w1tc register - * GPIO output enable clear register for GPIO0-29 - */ -typedef union { - struct { - /** enable_w1tc : WT; bitpos: [29:0]; default: 0; - * GPIO output enable clear register for GPIO0-29 - */ - uint32_t enable_w1tc:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_enable_w1tc_reg_t; - -/** Type of strap register - * pad strapping register - */ -typedef union { - struct { - /** strapping : RO; bitpos: [15:0]; default: 0; - * pad strapping register - */ - uint32_t strapping:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} gpio_strap_reg_t; - -/** Type of in register - * GPIO input register for GPIO0-29 - */ -typedef union { - struct { - /** in_data_next : RO; bitpos: [29:0]; default: 0; - * GPIO input register for GPIO0-29 - */ - uint32_t in_data_next:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_in_reg_t; - -/** Type of status register - * GPIO interrupt status register for GPIO0-29 - */ -typedef union { - struct { - /** status_interrupt : R/W/SS; bitpos: [29:0]; default: 0; - * GPIO interrupt status register for GPIO0-29 - */ - uint32_t status_interrupt:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_status_reg_t; - -/** Type of status_w1ts register - * GPIO interrupt status set register for GPIO0-29 - */ -typedef union { - struct { - /** status_w1ts : WT; bitpos: [29:0]; default: 0; - * GPIO interrupt status set register for GPIO0-29 - */ - uint32_t status_w1ts:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_status_w1ts_reg_t; - -/** Type of status_w1tc register - * GPIO interrupt status clear register for GPIO0-29 - */ -typedef union { - struct { - /** status_w1tc : WT; bitpos: [29:0]; default: 0; - * GPIO interrupt status clear register for GPIO0-29 - */ - uint32_t status_w1tc:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_status_w1tc_reg_t; - -/** Type of pin register - * GPIO pin configuration register - */ -typedef union { - struct { - /** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ - uint32_t pin_sync2_bypass:2; - /** pin_pad_driver : R/W; bitpos: [2]; default: 0; - * set this bit to select pad driver. 1:open-drain. 0:normal. - */ - uint32_t pin_pad_driver:1; - /** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at - * posedge. - */ - uint32_t pin_sync1_bypass:2; - uint32_t reserved_5:2; - /** pin_int_type : R/W; bitpos: [9:7]; default: 0; - * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at - * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid - * at high level - */ - uint32_t pin_int_type:3; - /** pin_wakeup_enable : R/W; bitpos: [10]; default: 0; - * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - */ - uint32_t pin_wakeup_enable:1; - /** pin_config : R/W; bitpos: [12:11]; default: 0; - * reserved - */ - uint32_t pin_config:2; - /** pin_int_ena : R/W; bitpos: [17:13]; default: 0; - * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) - * interrupt. - */ - uint32_t pin_int_ena:5; - uint32_t reserved_18:14; - }; - uint32_t val; -} gpio_pin_reg_t; - -/** Type of status_next register - * GPIO interrupt source register for GPIO0-29 - */ -typedef union { - struct { - /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; - * GPIO interrupt source register for GPIO0-29 - */ - uint32_t status_interrupt_next:32; - }; - uint32_t val; -} gpio_status_next_reg_t; - -/** Type of func_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func_in_sel : R/W; bitpos: [4:0]; default: 0; - * set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always - * high level. s=0x3C: set this port always low level. - */ - uint32_t func_in_sel:5; - /** func_in_inv_sel : R/W; bitpos: [5]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func_in_inv_sel:1; - /** sig_in_sel : R/W; bitpos: [6]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig_in_sel:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} gpio_func_in_sel_cfg_reg_t; - -/** Type of func_out_sel_cfg register - * GPIO output function select register - */ -typedef union { - struct { - /** func_out_sel : R/W; bitpos: [7:0]; default: 128; - * The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127: - * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals - * GPIO_OUT_REG[n]. - */ - uint32_t func_out_sel:8; - /** func_out_inv_sel : R/W; bitpos: [8]; default: 0; - * set this bit to invert output signal.1:invert.0:not invert. - */ - uint32_t func_out_inv_sel:1; - /** func_oen_sel : R/W; bitpos: [9]; default: 0; - * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output - * enable signal.0:use peripheral output enable signal. - */ - uint32_t func_oen_sel:1; - /** func_oen_inv_sel : R/W; bitpos: [10]; default: 0; - * set this bit to invert output enable signal.1:invert.0:not invert. - */ - uint32_t func_oen_inv_sel:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} gpio_func_out_sel_cfg_reg_t; - -/** Type of clock_gate register - * GPIO clock gate register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * set this bit to enable GPIO clock gate - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_clock_gate_reg_t; - -/** Type of reg_date register - * GPIO version register - */ -typedef union { - struct { - /** reg_date : R/W; bitpos: [27:0]; default: 34640016; - * version register - */ - uint32_t reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpio_reg_date_reg_t; - - -/** Group: interrupt register */ -/** Type of pcpu_int register - * GPIO PRO_CPU interrupt status register for GPIO0-29 - */ -typedef union { - struct { - /** procpu_int : RO; bitpos: [29:0]; default: 0; - * GPIO PRO_CPU interrupt status register for GPIO0-29 - */ - uint32_t procpu_int:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_pcpu_int_reg_t; - -/** Type of pcpu_nmi_int register - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 - */ -typedef union { - struct { - /** procpu_nmi_int : RO; bitpos: [29:0]; default: 0; - * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29 - */ - uint32_t procpu_nmi_int:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_pcpu_nmi_int_reg_t; - -/** Type of cpusdio_int register - * GPIO CPUSDIO interrupt status register for GPIO0-29 - */ -typedef union { - struct { - /** sdio_int : RO; bitpos: [29:0]; default: 0; - * GPIO CPUSDIO interrupt status register for GPIO0-29 - */ - uint32_t sdio_int:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_cpusdio_int_reg_t; - - -typedef struct { - volatile gpio_bt_select_reg_t bt_select; - volatile gpio_out_reg_t out; - volatile gpio_out_w1ts_reg_t out_w1ts; - volatile gpio_out_w1tc_reg_t out_w1tc; - uint32_t reserved_010[3]; - volatile gpio_sdio_select_reg_t sdio_select; - volatile gpio_enable_reg_t enable; - volatile gpio_enable_w1ts_reg_t enable_w1ts; - volatile gpio_enable_w1tc_reg_t enable_w1tc; - uint32_t reserved_02c[3]; - volatile gpio_strap_reg_t strap; - volatile gpio_in_reg_t in; - uint32_t reserved_040; - volatile gpio_status_reg_t status; - volatile gpio_status_w1ts_reg_t status_w1ts; - volatile gpio_status_w1tc_reg_t status_w1tc; - uint32_t reserved_050[3]; - volatile gpio_pcpu_int_reg_t pcpu_int; - volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; - volatile gpio_cpusdio_int_reg_t cpusdio_int; - uint32_t reserved_068[3]; - volatile gpio_pin_reg_t pin[30]; - uint32_t reserved_0ec[24]; - volatile gpio_status_next_reg_t status_next; - uint32_t reserved_150; - volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; - uint32_t reserved_354[128]; - volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[30]; - uint32_t reserved_5cc[24]; - volatile gpio_clock_gate_reg_t clock_gate; - uint32_t reserved_630[51]; - volatile gpio_reg_date_reg_t reg_date; -} gpio_dev_t; - -extern gpio_dev_t GPIO; - -#ifndef __cplusplus -_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/interrupt_core0_reg.h b/components/soc/esp32h4/include/rev2/soc/interrupt_core0_reg.h deleted file mode 100644 index 13386df3c8..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/interrupt_core0_reg.h +++ /dev/null @@ -1,1366 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** INTERRUPT_CORE0_MAC_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0) -/** INTERRUPT_CORE0_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_MAC_INTR_MAP_M (INTERRUPT_CORE0_MAC_INTR_MAP_V << INTERRUPT_CORE0_MAC_INTR_MAP_S) -#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_MAC_NMI_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4) -/** INTERRUPT_CORE0_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001FU -#define INTERRUPT_CORE0_MAC_NMI_MAP_M (INTERRUPT_CORE0_MAC_NMI_MAP_V << INTERRUPT_CORE0_MAC_NMI_MAP_S) -#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 - -/** INTERRUPT_CORE0_PWR_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8) -/** INTERRUPT_CORE0_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_PWR_INTR_MAP_M (INTERRUPT_CORE0_PWR_INTR_MAP_V << INTERRUPT_CORE0_PWR_INTR_MAP_S) -#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_BB_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc) -/** INTERRUPT_CORE0_BB_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_BB_INT_MAP_M (INTERRUPT_CORE0_BB_INT_MAP_V << INTERRUPT_CORE0_BB_INT_MAP_S) -#define INTERRUPT_CORE0_BB_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_BB_INT_MAP_S 0 - -/** INTERRUPT_CORE0_BT_MAC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10) -/** INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M (INTERRUPT_CORE0_BT_MAC_INT_MAP_V << INTERRUPT_CORE0_BT_MAC_INT_MAP_S) -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_BT_BB_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14) -/** INTERRUPT_CORE0_BT_BB_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_BT_BB_INT_MAP_M (INTERRUPT_CORE0_BT_BB_INT_MAP_V << INTERRUPT_CORE0_BT_BB_INT_MAP_S) -#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 - -/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x18) -/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001FU -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 - -/** INTERRUPT_CORE0_RWBT_IRQ_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x1c) -/** INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001FU -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M (INTERRUPT_CORE0_RWBT_IRQ_MAP_V << INTERRUPT_CORE0_RWBT_IRQ_MAP_S) -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 - -/** INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x20) -/** INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001FU -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M (INTERRUPT_CORE0_RWBLE_IRQ_MAP_V << INTERRUPT_CORE0_RWBLE_IRQ_MAP_S) -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 - -/** INTERRUPT_CORE0_RWBT_NMI_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x24) -/** INTERRUPT_CORE0_RWBT_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001FU -#define INTERRUPT_CORE0_RWBT_NMI_MAP_M (INTERRUPT_CORE0_RWBT_NMI_MAP_V << INTERRUPT_CORE0_RWBT_NMI_MAP_S) -#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 - -/** INTERRUPT_CORE0_RWBLE_NMI_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x28) -/** INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001FU -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M (INTERRUPT_CORE0_RWBLE_NMI_MAP_V << INTERRUPT_CORE0_RWBLE_NMI_MAP_S) -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 - -/** INTERRUPT_CORE0_I2C_MST_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x2c) -/** INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M (INTERRUPT_CORE0_I2C_MST_INT_MAP_V << INTERRUPT_CORE0_I2C_MST_INT_MAP_S) -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 - -/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x30) -/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S) -#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x34) -/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S) -#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x38) -/** INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M (INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V << INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S) -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x3c) -/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S) -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x40) -/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 - -/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x44) -/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 - -/** INTERRUPT_CORE0_SPI_INTR_1_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x48) -/** INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001FU -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M (INTERRUPT_CORE0_SPI_INTR_1_MAP_V << INTERRUPT_CORE0_SPI_INTR_1_MAP_S) -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 - -/** INTERRUPT_CORE0_SPI_INTR_2_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4c) -/** INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001FU -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M (INTERRUPT_CORE0_SPI_INTR_2_MAP_V << INTERRUPT_CORE0_SPI_INTR_2_MAP_S) -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 - -/** INTERRUPT_CORE0_I2S1_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x50) -/** INTERRUPT_CORE0_I2S1_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_I2S1_INT_MAP_M (INTERRUPT_CORE0_I2S1_INT_MAP_V << INTERRUPT_CORE0_I2S1_INT_MAP_S) -#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 - -/** INTERRUPT_CORE0_UART_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x54) -/** INTERRUPT_CORE0_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_UART_INTR_MAP_M (INTERRUPT_CORE0_UART_INTR_MAP_V << INTERRUPT_CORE0_UART_INTR_MAP_S) -#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x58) -/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) -#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_LEDC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x5c) -/** INTERRUPT_CORE0_LEDC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_LEDC_INT_MAP_M (INTERRUPT_CORE0_LEDC_INT_MAP_V << INTERRUPT_CORE0_LEDC_INT_MAP_S) -#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_EFUSE_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x60) -/** INTERRUPT_CORE0_EFUSE_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_EFUSE_INT_MAP_M (INTERRUPT_CORE0_EFUSE_INT_MAP_V << INTERRUPT_CORE0_EFUSE_INT_MAP_S) -#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 - -/** INTERRUPT_CORE0_TWAI_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x64) -/** INTERRUPT_CORE0_TWAI_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TWAI_INT_MAP_M (INTERRUPT_CORE0_TWAI_INT_MAP_V << INTERRUPT_CORE0_TWAI_INT_MAP_S) -#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0 - -/** INTERRUPT_CORE0_USB_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x68) -/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S) -#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x6c) -/** INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M (INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V << INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S) -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x70) -/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_RMT_INTR_MAP_M (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S) -#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x74) -/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_TIMER_INT1_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x78) -/** INTERRUPT_CORE0_TIMER_INT1_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001FU -#define INTERRUPT_CORE0_TIMER_INT1_MAP_M (INTERRUPT_CORE0_TIMER_INT1_MAP_V << INTERRUPT_CORE0_TIMER_INT1_MAP_S) -#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 - -/** INTERRUPT_CORE0_TIMER_INT2_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x7c) -/** INTERRUPT_CORE0_TIMER_INT2_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001FU -#define INTERRUPT_CORE0_TIMER_INT2_MAP_M (INTERRUPT_CORE0_TIMER_INT2_MAP_V << INTERRUPT_CORE0_TIMER_INT2_MAP_S) -#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 - -/** INTERRUPT_CORE0_TG_T0_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x80) -/** INTERRUPT_CORE0_TG_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TG_T0_INT_MAP_M (INTERRUPT_CORE0_TG_T0_INT_MAP_V << INTERRUPT_CORE0_TG_T0_INT_MAP_S) -#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 - -/** INTERRUPT_CORE0_TG_WDT_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x84) -/** INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M (INTERRUPT_CORE0_TG_WDT_INT_MAP_V << INTERRUPT_CORE0_TG_WDT_INT_MAP_S) -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 - -/** INTERRUPT_CORE0_TG1_T0_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x88) -/** INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M (INTERRUPT_CORE0_TG1_T0_INT_MAP_V << INTERRUPT_CORE0_TG1_T0_INT_MAP_S) -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 - -/** INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8c) -/** INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M (INTERRUPT_CORE0_TG1_WDT_INT_MAP_V << INTERRUPT_CORE0_TG1_WDT_INT_MAP_S) -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 - -/** INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x90) -/** INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M (INTERRUPT_CORE0_CACHE_IA_INT_MAP_V << INTERRUPT_CORE0_CACHE_IA_INT_MAP_S) -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 - -/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x94) -/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S) -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 - -/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x98) -/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S) -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 - -/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x9c) -/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S) -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 - -/** INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa0) -/** INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M (INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V << INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S) -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa4) -/** INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M (INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V << INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S) -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 - -/** INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa8) -/** INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M (INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V << INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S) -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_APB_ADC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xac) -/** INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M (INTERRUPT_CORE0_APB_ADC_INT_MAP_V << INTERRUPT_CORE0_APB_ADC_INT_MAP_S) -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb0) -/** INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M (INTERRUPT_CORE0_DMA_CH0_INT_MAP_V << INTERRUPT_CORE0_DMA_CH0_INT_MAP_S) -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 - -/** INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb4) -/** INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M (INTERRUPT_CORE0_DMA_CH1_INT_MAP_V << INTERRUPT_CORE0_DMA_CH1_INT_MAP_S) -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0 - -/** INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb8) -/** INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M (INTERRUPT_CORE0_DMA_CH2_INT_MAP_V << INTERRUPT_CORE0_DMA_CH2_INT_MAP_S) -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0 - -/** INTERRUPT_CORE0_RSA_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xbc) -/** INTERRUPT_CORE0_RSA_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_RSA_INT_MAP_M (INTERRUPT_CORE0_RSA_INT_MAP_V << INTERRUPT_CORE0_RSA_INT_MAP_S) -#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 - -/** INTERRUPT_CORE0_AES_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc0) -/** INTERRUPT_CORE0_AES_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_AES_INT_MAP_M (INTERRUPT_CORE0_AES_INT_MAP_V << INTERRUPT_CORE0_AES_INT_MAP_S) -#define INTERRUPT_CORE0_AES_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_AES_INT_MAP_S 0 - -/** INTERRUPT_CORE0_SHA_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc4) -/** INTERRUPT_CORE0_SHA_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_SHA_INT_MAP_M (INTERRUPT_CORE0_SHA_INT_MAP_V << INTERRUPT_CORE0_SHA_INT_MAP_S) -#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc8) -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0xcc) -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd0) -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd4) -/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 - -/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd8) -/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xdc) -/** INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0]; - * default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M (INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S) -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe0) -/** INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0]; - * default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M (INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S) -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe4) -/** INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0]; - * default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M (INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S) -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe8) -/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0]; - * default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xec) -/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W; bitpos: [4:0]; - * default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S) -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf0) -/** INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001FU -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M (INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S) -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0 - -/** INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf4) -/** INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M (INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V << INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S) -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 - -/** INTERRUPT_CORE0_TG3_T0_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf8) -/** INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TG3_T0_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M (INTERRUPT_CORE0_TG3_T0_INT_MAP_V << INTERRUPT_CORE0_TG3_T0_INT_MAP_S) -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TG3_T0_INT_MAP_S 0 - -/** INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xfc) -/** INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M (INTERRUPT_CORE0_TG3_WDT_INT_MAP_V << INTERRUPT_CORE0_TG3_WDT_INT_MAP_S) -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S 0 - -/** INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100) -/** INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M (INTERRUPT_CORE0_BLE_SEC_INT_MAP_V << INTERRUPT_CORE0_BLE_SEC_INT_MAP_S) -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104) -/** INTERRUPT_CORE0_IEEE802154MAC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_M (INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V << INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S) -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108) -/** INTERRUPT_CORE0_IEEE802154BB_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_M (INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V << INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S) -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S 0 - -/** INTERRUPT_CORE0_COEX_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10c) -/** INTERRUPT_CORE0_COEX_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_COEX_INT_MAP_M (INTERRUPT_CORE0_COEX_INT_MAP_V << INTERRUPT_CORE0_COEX_INT_MAP_S) -#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_COEX_INT_MAP_S 0 - -/** INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110) -/** INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M (INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V << INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S) -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S 0 - -/** INTERRUPT_CORE0_ECC_INT_MAP_REG register - * register description - */ -#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114) -/** INTERRUPT_CORE0_ECC_INT_MAP : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000001FU -#define INTERRUPT_CORE0_ECC_INT_MAP_M (INTERRUPT_CORE0_ECC_INT_MAP_V << INTERRUPT_CORE0_ECC_INT_MAP_S) -#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x0000001FU -#define INTERRUPT_CORE0_ECC_INT_MAP_S 0 - -/** INTERRUPT_CORE0_INTR_STATUS_REG_0_REG register - * register description - */ -#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_BASE + 0x118) -/** INTERRUPT_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFFU -#define INTERRUPT_CORE0_INTR_STATUS_0_M (INTERRUPT_CORE0_INTR_STATUS_0_V << INTERRUPT_CORE0_INTR_STATUS_0_S) -#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 - -/** INTERRUPT_CORE0_INTR_STATUS_REG_1_REG register - * register description - */ -#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_BASE + 0x11c) -/** INTERRUPT_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFFU -#define INTERRUPT_CORE0_INTR_STATUS_1_M (INTERRUPT_CORE0_INTR_STATUS_1_V << INTERRUPT_CORE0_INTR_STATUS_1_S) -#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 - -/** INTERRUPT_CORE0_INTR_STATUS_REG_2_REG register - * register description - */ -#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_BASE + 0x120) -/** INTERRUPT_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFFU -#define INTERRUPT_CORE0_INTR_STATUS_2_M (INTERRUPT_CORE0_INTR_STATUS_2_V << INTERRUPT_CORE0_INTR_STATUS_2_S) -#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 - -/** INTERRUPT_CORE0_CLOCK_GATE_REG register - * register description - */ -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x124) -/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) -#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S) -#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U -#define INTERRUPT_CORE0_REG_CLK_EN_S 0 - -/** INTERRUPT_CORE0_CPU_INT_ENABLE_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_BASE + 0x128) -/** INTERRUPT_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_ENABLE_M (INTERRUPT_CORE0_CPU_INT_ENABLE_V << INTERRUPT_CORE0_CPU_INT_ENABLE_S) -#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0 - -/** INTERRUPT_CORE0_CPU_INT_TYPE_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_BASE + 0x12c) -/** INTERRUPT_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_TYPE_M (INTERRUPT_CORE0_CPU_INT_TYPE_V << INTERRUPT_CORE0_CPU_INT_TYPE_S) -#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0 - -/** INTERRUPT_CORE0_CPU_INT_CLEAR_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_BASE + 0x130) -/** INTERRUPT_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_CLEAR_M (INTERRUPT_CORE0_CPU_INT_CLEAR_V << INTERRUPT_CORE0_CPU_INT_CLEAR_S) -#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0 - -/** INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_BASE + 0x134) -/** INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M (INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V << INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S) -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU -#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_0_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_BASE + 0x138) - -#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4) -/** INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M (INTERRUPT_CORE0_CPU_PRI_0_MAP_V << INTERRUPT_CORE0_CPU_PRI_0_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_1_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_BASE + 0x13c) -/** INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M (INTERRUPT_CORE0_CPU_PRI_1_MAP_V << INTERRUPT_CORE0_CPU_PRI_1_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_2_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_BASE + 0x140) -/** INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M (INTERRUPT_CORE0_CPU_PRI_2_MAP_V << INTERRUPT_CORE0_CPU_PRI_2_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_3_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_BASE + 0x144) -/** INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M (INTERRUPT_CORE0_CPU_PRI_3_MAP_V << INTERRUPT_CORE0_CPU_PRI_3_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_4_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_BASE + 0x148) -/** INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M (INTERRUPT_CORE0_CPU_PRI_4_MAP_V << INTERRUPT_CORE0_CPU_PRI_4_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_5_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_BASE + 0x14c) -/** INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M (INTERRUPT_CORE0_CPU_PRI_5_MAP_V << INTERRUPT_CORE0_CPU_PRI_5_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_6_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_BASE + 0x150) -/** INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M (INTERRUPT_CORE0_CPU_PRI_6_MAP_V << INTERRUPT_CORE0_CPU_PRI_6_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_7_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_BASE + 0x154) -/** INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M (INTERRUPT_CORE0_CPU_PRI_7_MAP_V << INTERRUPT_CORE0_CPU_PRI_7_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_8_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_BASE + 0x158) -/** INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M (INTERRUPT_CORE0_CPU_PRI_8_MAP_V << INTERRUPT_CORE0_CPU_PRI_8_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_9_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_BASE + 0x15c) -/** INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M (INTERRUPT_CORE0_CPU_PRI_9_MAP_V << INTERRUPT_CORE0_CPU_PRI_9_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_10_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_BASE + 0x160) -/** INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M (INTERRUPT_CORE0_CPU_PRI_10_MAP_V << INTERRUPT_CORE0_CPU_PRI_10_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_11_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_BASE + 0x164) -/** INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M (INTERRUPT_CORE0_CPU_PRI_11_MAP_V << INTERRUPT_CORE0_CPU_PRI_11_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_12_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_BASE + 0x168) -/** INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M (INTERRUPT_CORE0_CPU_PRI_12_MAP_V << INTERRUPT_CORE0_CPU_PRI_12_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_13_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_BASE + 0x16c) -/** INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M (INTERRUPT_CORE0_CPU_PRI_13_MAP_V << INTERRUPT_CORE0_CPU_PRI_13_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_14_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_BASE + 0x170) -/** INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M (INTERRUPT_CORE0_CPU_PRI_14_MAP_V << INTERRUPT_CORE0_CPU_PRI_14_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_15_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_BASE + 0x174) -/** INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M (INTERRUPT_CORE0_CPU_PRI_15_MAP_V << INTERRUPT_CORE0_CPU_PRI_15_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_16_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_BASE + 0x178) -/** INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M (INTERRUPT_CORE0_CPU_PRI_16_MAP_V << INTERRUPT_CORE0_CPU_PRI_16_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_17_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_BASE + 0x17c) -/** INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M (INTERRUPT_CORE0_CPU_PRI_17_MAP_V << INTERRUPT_CORE0_CPU_PRI_17_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_18_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_BASE + 0x180) -/** INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M (INTERRUPT_CORE0_CPU_PRI_18_MAP_V << INTERRUPT_CORE0_CPU_PRI_18_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_19_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_BASE + 0x184) -/** INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M (INTERRUPT_CORE0_CPU_PRI_19_MAP_V << INTERRUPT_CORE0_CPU_PRI_19_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_20_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_BASE + 0x188) -/** INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M (INTERRUPT_CORE0_CPU_PRI_20_MAP_V << INTERRUPT_CORE0_CPU_PRI_20_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_21_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_BASE + 0x18c) -/** INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M (INTERRUPT_CORE0_CPU_PRI_21_MAP_V << INTERRUPT_CORE0_CPU_PRI_21_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_22_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_BASE + 0x190) -/** INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M (INTERRUPT_CORE0_CPU_PRI_22_MAP_V << INTERRUPT_CORE0_CPU_PRI_22_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_23_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_BASE + 0x194) -/** INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M (INTERRUPT_CORE0_CPU_PRI_23_MAP_V << INTERRUPT_CORE0_CPU_PRI_23_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_24_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_BASE + 0x198) -/** INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M (INTERRUPT_CORE0_CPU_PRI_24_MAP_V << INTERRUPT_CORE0_CPU_PRI_24_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_25_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_BASE + 0x19c) -/** INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M (INTERRUPT_CORE0_CPU_PRI_25_MAP_V << INTERRUPT_CORE0_CPU_PRI_25_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_26_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_BASE + 0x1a0) -/** INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M (INTERRUPT_CORE0_CPU_PRI_26_MAP_V << INTERRUPT_CORE0_CPU_PRI_26_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_27_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_BASE + 0x1a4) -/** INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M (INTERRUPT_CORE0_CPU_PRI_27_MAP_V << INTERRUPT_CORE0_CPU_PRI_27_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_28_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_BASE + 0x1a8) -/** INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M (INTERRUPT_CORE0_CPU_PRI_28_MAP_V << INTERRUPT_CORE0_CPU_PRI_28_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_29_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_BASE + 0x1ac) -/** INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M (INTERRUPT_CORE0_CPU_PRI_29_MAP_V << INTERRUPT_CORE0_CPU_PRI_29_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_30_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_BASE + 0x1b0) -/** INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M (INTERRUPT_CORE0_CPU_PRI_30_MAP_V << INTERRUPT_CORE0_CPU_PRI_30_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_PRI_31_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_BASE + 0x1b4) -/** INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M (INTERRUPT_CORE0_CPU_PRI_31_MAP_V << INTERRUPT_CORE0_CPU_PRI_31_MAP_S) -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0 - -/** INTERRUPT_CORE0_CPU_INT_THRESH_REG register - * register description - */ -#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_BASE + 0x1b8) -/** INTERRUPT_CORE0_CPU_INT_THRESH : R/W; bitpos: [3:0]; default: 0; - * Need add description - */ -#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000FU -#define INTERRUPT_CORE0_CPU_INT_THRESH_M (INTERRUPT_CORE0_CPU_INT_THRESH_V << INTERRUPT_CORE0_CPU_INT_THRESH_S) -#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0x0000000FU -#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0 - -/** INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG register - * register description - */ -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_BASE + 0x7fc) -/** INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33624208; - * Need add description - */ -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M (INTERRUPT_CORE0_INTERRUPT_REG_DATE_V << INTERRUPT_CORE0_INTERRUPT_REG_DATE_S) -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU -#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/io_mux_reg.h b/components/soc/esp32h4/include/rev2/soc/io_mux_reg.h deleted file mode 100644 index 9b5ae4f4dc..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/io_mux_reg.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc/soc.h" - -/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ -/* Output enable in sleep mode */ -#define SLP_OE (BIT(0)) -#define SLP_OE_M (BIT(0)) -#define SLP_OE_V 1 -#define SLP_OE_S 0 -/* Pin used for wakeup from sleep */ -#define SLP_SEL (BIT(1)) -#define SLP_SEL_M (BIT(1)) -#define SLP_SEL_V 1 -#define SLP_SEL_S 1 -/* Pulldown enable in sleep mode */ -#define SLP_PD (BIT(2)) -#define SLP_PD_M (BIT(2)) -#define SLP_PD_V 1 -#define SLP_PD_S 2 -/* Pullup enable in sleep mode */ -#define SLP_PU (BIT(3)) -#define SLP_PU_M (BIT(3)) -#define SLP_PU_V 1 -#define SLP_PU_S 3 -/* Input enable in sleep mode */ -#define SLP_IE (BIT(4)) -#define SLP_IE_M (BIT(4)) -#define SLP_IE_V 1 -#define SLP_IE_S 4 -/* Drive strength in sleep mode */ -#define SLP_DRV 0x3 -#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) -#define SLP_DRV_V 0x3 -#define SLP_DRV_S 5 -/* Pulldown enable */ -#define FUN_PD (BIT(7)) -#define FUN_PD_M (BIT(7)) -#define FUN_PD_V 1 -#define FUN_PD_S 7 -/* Pullup enable */ -#define FUN_PU (BIT(8)) -#define FUN_PU_M (BIT(8)) -#define FUN_PU_V 1 -#define FUN_PU_S 8 -/* Input enable */ -#define FUN_IE (BIT(9)) -#define FUN_IE_M (FUN_IE_V << FUN_IE_S) -#define FUN_IE_V 1 -#define FUN_IE_S 9 -/* Drive strength */ -#define FUN_DRV 0x3 -#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) -#define FUN_DRV_V 0x3 -#define FUN_DRV_S 10 -/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ -#define MCU_SEL 0x7 -#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) -#define MCU_SEL_V 0x7 -#define MCU_SEL_S 12 -/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ -#define FILTER_EN (BIT(15)) -#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) -#define FILTER_EN_V 1 -#define FILTER_EN_S 15 - -#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) -#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) - -#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); -#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) -#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) -#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) -#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) - -#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U -#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U -#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_MTMS_U -#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTDO_U -#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTCK_U -#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U -#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U -#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U -#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U -#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U -#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_XTAL_32K_P_U -#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_XTAL_32K_N_U -#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U -#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPICS0_U -#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPIQ_U -#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPIWP_U -#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIHD_U -#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPICLK_U -#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SPID_U -#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_VDD_SPI_U -#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U -#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0RXD_U -#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U0TXD_U -#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U -#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U -#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U - -#define PIN_FUNC_GPIO 1 - -#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) - -#define SPI_HD_GPIO_NUM 16 -#define SPI_WP_GPIO_NUM 15 -#define SPI_CS0_GPIO_NUM 13 -#define SPI_CLK_GPIO_NUM 17 -#define SPI_D_GPIO_NUM 18 -#define SPI_Q_GPIO_NUM 14 - -#define USB_DM_GPIO_NUM 24 -#define USB_DP_GPIO_NUM 25 - -#define XTAL32K_P_GPIO_NUM 10 -#define XTAL32K_N_GPIO_NUM 11 - -#define MAX_RTC_GPIO_NUM 12 // GPIO7~12 are the rtc_io pads -#define MAX_PAD_GPIO_NUM 25 -#define MAX_GPIO_NUM 29 -#define DIG_IO_HOLD_BIT_SHIFT 0 - - -#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE -#define PIN_CTRL (REG_IO_MUX_BASE +0x00) -#define PAD_POWER_SEL BIT(15) -#define PAD_POWER_SEL_V 0x1 -#define PAD_POWER_SEL_M BIT(15) -#define PAD_POWER_SEL_S 15 - -#define PAD_POWER_SWITCH_DELAY 0x7 -#define PAD_POWER_SWITCH_DELAY_V 0x7 -#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) -#define PAD_POWER_SWITCH_DELAY_S 12 - -#define CLK_OUT3 0xf -#define CLK_OUT3_V CLK_OUT3 -#define CLK_OUT3_S 8 -#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) -#define CLK_OUT2 0xf -#define CLK_OUT2_V CLK_OUT2 -#define CLK_OUT2_S 4 -#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) -#define CLK_OUT1 0xf -#define CLK_OUT1_V CLK_OUT1 -#define CLK_OUT1_S 0 -#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) -// definitions above are inherited from previous version of code, should double check - -// definitions below are generated from pin_txt.csv -#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4) -#define FUNC_GPIO0_FSPIQ 2 -#define FUNC_GPIO0_GPIO0 1 -#define FUNC_GPIO0_GPIO0_0 0 - -#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x8) -#define FUNC_GPIO1_FSPICS0 2 -#define FUNC_GPIO1_GPIO1 1 -#define FUNC_GPIO1_GPIO1_0 0 - -#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xC) -#define FUNC_MTMS_FSPIWP 2 -#define FUNC_MTMS_GPIO2 1 -#define FUNC_MTMS_MTMS 0 - -#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x10) -#define FUNC_MTDO_FSPIHD 2 -#define FUNC_MTDO_GPIO3 1 -#define FUNC_MTDO_MTDO 0 - -#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14) -#define FUNC_MTCK_FSPICLK 2 -#define FUNC_MTCK_GPIO4 1 -#define FUNC_MTCK_MTCK 0 - -#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18) -#define FUNC_MTDI_FSPID 2 -#define FUNC_MTDI_GPIO5 1 -#define FUNC_MTDI_MTDI 0 - -#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1C) -#define FUNC_GPIO6_GPIO6 1 -#define FUNC_GPIO6_GPIO6_0 0 - -#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20) -#define FUNC_GPIO7_GPIO7 1 -#define FUNC_GPIO7_GPIO7_0 0 - -#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24) -#define FUNC_GPIO8_GPIO8 1 -#define FUNC_GPIO8_GPIO8_0 0 - -#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28) -#define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_GPIO9_0 0 - -#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x2C) -#define FUNC_XTAL_32K_P_GPIO10 1 -#define FUNC_XTAL_32K_P_GPIO10_0 0 - -#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x30) -#define FUNC_XTAL_32K_N_GPIO11 1 -#define FUNC_XTAL_32K_N_GPIO11_0 0 - -#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34) -#define FUNC_GPIO12_GPIO12 1 -#define FUNC_GPIO12_GPIO12_0 0 - -#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x38) -#define FUNC_SPICS0_GPIO13 1 -#define FUNC_SPICS0_SPICS0 0 - -#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x3C) -#define FUNC_SPIQ_GPIO14 1 -#define FUNC_SPIQ_SPIQ 0 - -#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x40) -#define FUNC_SPIWP_GPIO15 1 -#define FUNC_SPIWP_SPIWP 0 - -#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x44) -#define FUNC_SPIHD_GPIO16 1 -#define FUNC_SPIHD_SPIHD 0 - -#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x48) -#define FUNC_SPICLK_GPIO17 1 -#define FUNC_SPICLK_SPICLK 0 - -#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x4C) -#define FUNC_SPID_GPIO18 1 -#define FUNC_SPID_SPID 0 - -#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x50) -#define FUNC_VDD_SPI_GPIO19 1 -#define FUNC_VDD_SPI_GPIO19_0 0 - -#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE + 0x54) -#define FUNC_GPIO20_GPIO20 1 -#define FUNC_GPIO20_GPIO20_0 0 - -#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x58) -#define FUNC_U0RXD_GPIO21 1 -#define FUNC_U0RXD_U0RXD 0 - -#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x5C) -#define FUNC_U0TXD_GPIO22 1 -#define FUNC_U0TXD_U0TXD 0 - -#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE + 0x60) -#define FUNC_GPIO23_GPIO23 1 -#define FUNC_GPIO23_GPIO23_0 0 - -#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x64) -#define FUNC_GPIO24_GPIO24 1 -#define FUNC_GPIO24_GPIO24_0 0 - -#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE + 0x68) -#define FUNC_GPIO25_GPIO25 1 -#define FUNC_GPIO25_GPIO25_0 0 - -/** IO_MUX_DATE_REG register - * IO MUX Version Control Register - */ -#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) -/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 0x2109090; - * Version control register - */ -#define IO_MUX_DATE 0x0FFFFFFF -#define IO_MUX_DATE_M (IO_MUX_DATE_V << IO_MUX_DATE_S) -#define IO_MUX_DATE_V 0x0FFFFFFFU -#define IO_MUX_DATE_S 0 -#define IO_MUX_DATE_VERSION 0x2109090 diff --git a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h b/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h deleted file mode 100644 index c2e6c19f9a..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_reg.h +++ /dev/null @@ -1,4028 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ -#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 -/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ -#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A - -/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ -#define RTC_WDT_RESET_LENGTH_100_NS 0 -#define RTC_WDT_RESET_LENGTH_200_NS 1 -#define RTC_WDT_RESET_LENGTH_300_NS 2 -#define RTC_WDT_RESET_LENGTH_400_NS 3 -#define RTC_WDT_RESET_LENGTH_500_NS 4 -#define RTC_WDT_RESET_LENGTH_800_NS 5 -#define RTC_WDT_RESET_LENGTH_1600_NS 6 -#define RTC_WDT_RESET_LENGTH_3200_NS 7 - -#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG -#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG - -/** RTC_CNTL_OPTIONS0_REG register - * register description - */ -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) -/** RTC_CNTL_SW_STALL_APPCPU_C0 : R/W; bitpos: [1:0]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP - * CPU - */ -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003U -#define RTC_CNTL_SW_STALL_APPCPU_C0_M (RTC_CNTL_SW_STALL_APPCPU_C0_V << RTC_CNTL_SW_STALL_APPCPU_C0_S) -#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x00000003U -#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 -/** RTC_CNTL_SW_STALL_PROCPU_C0 : R/W; bitpos: [3:2]; default: 0; - * {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO - * CPU - */ -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003U -#define RTC_CNTL_SW_STALL_PROCPU_C0_M (RTC_CNTL_SW_STALL_PROCPU_C0_V << RTC_CNTL_SW_STALL_PROCPU_C0_S) -#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x00000003U -#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 -/** RTC_CNTL_SW_APPCPU_RST : WO; bitpos: [4]; default: 0; - * APP CPU SW reset - */ -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_M (RTC_CNTL_SW_APPCPU_RST_V << RTC_CNTL_SW_APPCPU_RST_S) -#define RTC_CNTL_SW_APPCPU_RST_V 0x00000001U -#define RTC_CNTL_SW_APPCPU_RST_S 4 -/** RTC_CNTL_SW_PROCPU_RST : WO; bitpos: [5]; default: 0; - * PRO CPU SW reset - */ -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_M (RTC_CNTL_SW_PROCPU_RST_V << RTC_CNTL_SW_PROCPU_RST_S) -#define RTC_CNTL_SW_PROCPU_RST_V 0x00000001U -#define RTC_CNTL_SW_PROCPU_RST_S 5 -/** RTC_CNTL_BB_I2C_FORCE_PD : R/W; bitpos: [6]; default: 0; - * BB_I2C force power down - */ -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_M (RTC_CNTL_BB_I2C_FORCE_PD_V << RTC_CNTL_BB_I2C_FORCE_PD_S) -#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x00000001U -#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 -/** RTC_CNTL_BB_I2C_FORCE_PU : R/W; bitpos: [7]; default: 0; - * BB_I2C force power up - */ -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_M (RTC_CNTL_BB_I2C_FORCE_PU_V << RTC_CNTL_BB_I2C_FORCE_PU_S) -#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x00000001U -#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 -/** RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W; bitpos: [8]; default: 0; - * BB_PLL _I2C force power down - */ -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (RTC_CNTL_BBPLL_I2C_FORCE_PD_V << RTC_CNTL_BBPLL_I2C_FORCE_PD_S) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x00000001U -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 -/** RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W; bitpos: [9]; default: 0; - * BB_PLL_I2C force power up - */ -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (RTC_CNTL_BBPLL_I2C_FORCE_PU_V << RTC_CNTL_BBPLL_I2C_FORCE_PU_S) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x00000001U -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 -/** RTC_CNTL_BBPLL_FORCE_PD : R/W; bitpos: [10]; default: 0; - * BB_PLL force power down - */ -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_M (RTC_CNTL_BBPLL_FORCE_PD_V << RTC_CNTL_BBPLL_FORCE_PD_S) -#define RTC_CNTL_BBPLL_FORCE_PD_V 0x00000001U -#define RTC_CNTL_BBPLL_FORCE_PD_S 10 -/** RTC_CNTL_BBPLL_FORCE_PU : R/W; bitpos: [11]; default: 0; - * BB_PLL force power up - */ -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_M (RTC_CNTL_BBPLL_FORCE_PU_V << RTC_CNTL_BBPLL_FORCE_PU_S) -#define RTC_CNTL_BBPLL_FORCE_PU_V 0x00000001U -#define RTC_CNTL_BBPLL_FORCE_PU_S 11 -/** RTC_CNTL_XTL_FORCE_PD : R/W; bitpos: [12]; default: 0; - * crystall force power down - */ -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_M (RTC_CNTL_XTL_FORCE_PD_V << RTC_CNTL_XTL_FORCE_PD_S) -#define RTC_CNTL_XTL_FORCE_PD_V 0x00000001U -#define RTC_CNTL_XTL_FORCE_PD_S 12 -/** RTC_CNTL_XTL_FORCE_PU : R/W; bitpos: [13]; default: 1; - * crystall force power up - */ -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_M (RTC_CNTL_XTL_FORCE_PU_V << RTC_CNTL_XTL_FORCE_PU_S) -#define RTC_CNTL_XTL_FORCE_PU_V 0x00000001U -#define RTC_CNTL_XTL_FORCE_PU_S 13 -/** RTC_CNTL_XTL_EN_WAIT : R/W; bitpos: [17:14]; default: 2; - * wait bias_sleep and current source wakeup - */ -#define RTC_CNTL_XTL_EN_WAIT 0x0000000FU -#define RTC_CNTL_XTL_EN_WAIT_M (RTC_CNTL_XTL_EN_WAIT_V << RTC_CNTL_XTL_EN_WAIT_S) -#define RTC_CNTL_XTL_EN_WAIT_V 0x0000000FU -#define RTC_CNTL_XTL_EN_WAIT_S 14 -/** RTC_CNTL_XPD_RFPLL : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define RTC_CNTL_XPD_RFPLL (BIT(18)) -#define RTC_CNTL_XPD_RFPLL_M (RTC_CNTL_XPD_RFPLL_V << RTC_CNTL_XPD_RFPLL_S) -#define RTC_CNTL_XPD_RFPLL_V 0x00000001U -#define RTC_CNTL_XPD_RFPLL_S 18 -/** RTC_CNTL_XPD_RFPLL_FORCE : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define RTC_CNTL_XPD_RFPLL_FORCE (BIT(19)) -#define RTC_CNTL_XPD_RFPLL_FORCE_M (RTC_CNTL_XPD_RFPLL_FORCE_V << RTC_CNTL_XPD_RFPLL_FORCE_S) -#define RTC_CNTL_XPD_RFPLL_FORCE_V 0x00000001U -#define RTC_CNTL_XPD_RFPLL_FORCE_S 19 -/** RTC_CNTL_XTL_EXT_CTR_SEL : R/W; bitpos: [22:20]; default: 0; - * Need add description - */ -#define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007U -#define RTC_CNTL_XTL_EXT_CTR_SEL_M (RTC_CNTL_XTL_EXT_CTR_SEL_V << RTC_CNTL_XTL_EXT_CTR_SEL_S) -#define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x00000007U -#define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 -/** RTC_CNTL_XTL_FORCE_ISO : R/W; bitpos: [23]; default: 0; - * Need add description - */ -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_M (RTC_CNTL_XTL_FORCE_ISO_V << RTC_CNTL_XTL_FORCE_ISO_S) -#define RTC_CNTL_XTL_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_XTL_FORCE_ISO_S 23 -/** RTC_CNTL_PLL_FORCE_ISO : R/W; bitpos: [24]; default: 0; - * Need add description - */ -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_M (RTC_CNTL_PLL_FORCE_ISO_V << RTC_CNTL_PLL_FORCE_ISO_S) -#define RTC_CNTL_PLL_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_PLL_FORCE_ISO_S 24 -/** RTC_CNTL_ANALOG_FORCE_ISO : R/W; bitpos: [25]; default: 0; - * Need add description - */ -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_M (RTC_CNTL_ANALOG_FORCE_ISO_V << RTC_CNTL_ANALOG_FORCE_ISO_S) -#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 -/** RTC_CNTL_XTL_FORCE_NOISO : R/W; bitpos: [26]; default: 1; - * Need add description - */ -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_M (RTC_CNTL_XTL_FORCE_NOISO_V << RTC_CNTL_XTL_FORCE_NOISO_S) -#define RTC_CNTL_XTL_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_XTL_FORCE_NOISO_S 26 -/** RTC_CNTL_PLL_FORCE_NOISO : R/W; bitpos: [27]; default: 1; - * Need add description - */ -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_M (RTC_CNTL_PLL_FORCE_NOISO_V << RTC_CNTL_PLL_FORCE_NOISO_S) -#define RTC_CNTL_PLL_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_PLL_FORCE_NOISO_S 27 -/** RTC_CNTL_ANALOG_FORCE_NOISO : R/W; bitpos: [28]; default: 1; - * Need add description - */ -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_M (RTC_CNTL_ANALOG_FORCE_NOISO_V << RTC_CNTL_ANALOG_FORCE_NOISO_S) -#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 -/** RTC_CNTL_DG_WRAP_FORCE_RST : R/W; bitpos: [29]; default: 0; - * digital wrap force reset in deep sleep - */ -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_M (RTC_CNTL_DG_WRAP_FORCE_RST_V << RTC_CNTL_DG_WRAP_FORCE_RST_S) -#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x00000001U -#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 -/** RTC_CNTL_DG_WRAP_FORCE_NORST : R/W; bitpos: [30]; default: 0; - * digital core force no reset in deep sleep - */ -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (RTC_CNTL_DG_WRAP_FORCE_NORST_V << RTC_CNTL_DG_WRAP_FORCE_NORST_S) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x00000001U -#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 -/** RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0; - * SW system reset - */ -#define RTC_CNTL_SW_SYS_RST (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_M (RTC_CNTL_SW_SYS_RST_V << RTC_CNTL_SW_SYS_RST_S) -#define RTC_CNTL_SW_SYS_RST_V 0x00000001U -#define RTC_CNTL_SW_SYS_RST_S 31 - -/** RTC_CNTL_SLP_TIMER0_REG register - * register description - */ -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) -/** RTC_CNTL_SLP_VAL_LO : R/W; bitpos: [31:0]; default: 0; - * RTC sleep timer low 32 bits - */ -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFFU -#define RTC_CNTL_SLP_VAL_LO_M (RTC_CNTL_SLP_VAL_LO_V << RTC_CNTL_SLP_VAL_LO_S) -#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFFU -#define RTC_CNTL_SLP_VAL_LO_S 0 - -/** RTC_CNTL_SLP_TIMER1_REG register - * register description - */ -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) -/** RTC_CNTL_SLP_VAL_HI : R/W; bitpos: [15:0]; default: 0; - * RTC sleep timer high 16 bits - */ -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFFU -#define RTC_CNTL_SLP_VAL_HI_M (RTC_CNTL_SLP_VAL_HI_V << RTC_CNTL_SLP_VAL_HI_S) -#define RTC_CNTL_SLP_VAL_HI_V 0x0000FFFFU -#define RTC_CNTL_SLP_VAL_HI_S 0 -/** RTC_CNTL_MAIN_TIMER_ALARM_EN : WO; bitpos: [16]; default: 0; - * timer alarm enable bit - */ -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (RTC_CNTL_MAIN_TIMER_ALARM_EN_V << RTC_CNTL_MAIN_TIMER_ALARM_EN_S) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 - -/** RTC_CNTL_TIME_UPDATE_REG register - * register description - */ -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) -/** RTC_CNTL_TIMER_SYS_STALL : R/W; bitpos: [27]; default: 0; - * Enable to record system stall time - */ -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_M (RTC_CNTL_TIMER_SYS_STALL_V << RTC_CNTL_TIMER_SYS_STALL_S) -#define RTC_CNTL_TIMER_SYS_STALL_V 0x00000001U -#define RTC_CNTL_TIMER_SYS_STALL_S 27 -/** RTC_CNTL_TIMER_XTL_OFF : R/W; bitpos: [28]; default: 0; - * Enable to record 40M XTAL OFF time - */ -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_M (RTC_CNTL_TIMER_XTL_OFF_V << RTC_CNTL_TIMER_XTL_OFF_S) -#define RTC_CNTL_TIMER_XTL_OFF_V 0x00000001U -#define RTC_CNTL_TIMER_XTL_OFF_S 28 -/** RTC_CNTL_TIMER_SYS_RST : R/W; bitpos: [29]; default: 0; - * enable to record system reset time - */ -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_M (RTC_CNTL_TIMER_SYS_RST_V << RTC_CNTL_TIMER_SYS_RST_S) -#define RTC_CNTL_TIMER_SYS_RST_V 0x00000001U -#define RTC_CNTL_TIMER_SYS_RST_S 29 -/** RTC_CNTL_TIME_UPDATE : WO; bitpos: [31]; default: 0; - * Set 1: to update register with RTC timer - */ -#define RTC_CNTL_TIME_UPDATE (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_M (RTC_CNTL_TIME_UPDATE_V << RTC_CNTL_TIME_UPDATE_S) -#define RTC_CNTL_TIME_UPDATE_V 0x00000001U -#define RTC_CNTL_TIME_UPDATE_S 31 - -/** RTC_CNTL_TIME_LOW0_REG register - * register description - */ -#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) -/** RTC_CNTL_TIMER_VALUE0_LOW : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ -#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFFU -#define RTC_CNTL_TIMER_VALUE0_LOW_M (RTC_CNTL_TIMER_VALUE0_LOW_V << RTC_CNTL_TIMER_VALUE0_LOW_S) -#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFFU -#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 - -/** RTC_CNTL_TIME_HIGH0_REG register - * register description - */ -#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) -/** RTC_CNTL_TIMER_VALUE0_HIGH : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ -#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFFU -#define RTC_CNTL_TIMER_VALUE0_HIGH_M (RTC_CNTL_TIMER_VALUE0_HIGH_V << RTC_CNTL_TIMER_VALUE0_HIGH_S) -#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0x0000FFFFU -#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 - -/** RTC_CNTL_STATE0_REG register - * register description - */ -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) -/** RTC_CNTL_SW_CPU_INT : WO; bitpos: [0]; default: 0; - * rtc software interrupt to main cpu - */ -#define RTC_CNTL_SW_CPU_INT (BIT(0)) -#define RTC_CNTL_SW_CPU_INT_M (RTC_CNTL_SW_CPU_INT_V << RTC_CNTL_SW_CPU_INT_S) -#define RTC_CNTL_SW_CPU_INT_V 0x00000001U -#define RTC_CNTL_SW_CPU_INT_S 0 -/** RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO; bitpos: [1]; default: 0; - * clear rtc sleep reject cause - */ -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (RTC_CNTL_SLP_REJECT_CAUSE_CLR_V << RTC_CNTL_SLP_REJECT_CAUSE_CLR_S) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 -/** RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W; bitpos: [22]; default: 0; - * 1: APB to RTC using bridge, 0: APB to RTC using sync - */ -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (RTC_CNTL_APB2RTC_BRIDGE_SEL_V << RTC_CNTL_APB2RTC_BRIDGE_SEL_S) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x00000001U -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 -/** RTC_CNTL_SDIO_ACTIVE_IND : RO; bitpos: [28]; default: 0; - * SDIO active indication - */ -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_M (RTC_CNTL_SDIO_ACTIVE_IND_V << RTC_CNTL_SDIO_ACTIVE_IND_S) -#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x00000001U -#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 -/** RTC_CNTL_SLP_WAKEUP : R/W; bitpos: [29]; default: 0; - * leep wakeup bit - */ -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_M (RTC_CNTL_SLP_WAKEUP_V << RTC_CNTL_SLP_WAKEUP_S) -#define RTC_CNTL_SLP_WAKEUP_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_S 29 -/** RTC_CNTL_SLP_REJECT : R/W; bitpos: [30]; default: 0; - * leep reject bit - */ -#define RTC_CNTL_SLP_REJECT (BIT(30)) -#define RTC_CNTL_SLP_REJECT_M (RTC_CNTL_SLP_REJECT_V << RTC_CNTL_SLP_REJECT_S) -#define RTC_CNTL_SLP_REJECT_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_S 30 -/** RTC_CNTL_SLEEP_EN : R/W; bitpos: [31]; default: 0; - * sleep enable bit - */ -#define RTC_CNTL_SLEEP_EN (BIT(31)) -#define RTC_CNTL_SLEEP_EN_M (RTC_CNTL_SLEEP_EN_V << RTC_CNTL_SLEEP_EN_S) -#define RTC_CNTL_SLEEP_EN_V 0x00000001U -#define RTC_CNTL_SLEEP_EN_S 31 - -/** RTC_CNTL_TIMER1_REG register - * register description - */ -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) -/** RTC_CNTL_CPU_STALL_EN : R/W; bitpos: [0]; default: 1; - * CPU stall enable bit - */ -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_M (RTC_CNTL_CPU_STALL_EN_V << RTC_CNTL_CPU_STALL_EN_S) -#define RTC_CNTL_CPU_STALL_EN_V 0x00000001U -#define RTC_CNTL_CPU_STALL_EN_S 0 -/** RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1; - * CPU stall wait cycles in fast_clk_rtc - */ -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001FU -#define RTC_CNTL_CPU_STALL_WAIT_M (RTC_CNTL_CPU_STALL_WAIT_V << RTC_CNTL_CPU_STALL_WAIT_S) -#define RTC_CNTL_CPU_STALL_WAIT_V 0x0000001FU -#define RTC_CNTL_CPU_STALL_WAIT_S 1 -/** RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16; - * CK8M wait cycles in slow_clk_rtc - */ -#define RTC_CNTL_CK8M_WAIT 0x000000FFU -#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S) -#define RTC_CNTL_CK8M_WAIT_V 0x000000FFU -#define RTC_CNTL_CK8M_WAIT_S 6 -/** RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80; - * XTAL wait cycles in slow_clk_rtc - */ -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FFU -#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S) -#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003FFU -#define RTC_CNTL_XTL_BUF_WAIT_S 14 -/** RTC_CNTL_PLL_BUF_WAIT : R/W; bitpos: [31:24]; default: 40; - * PLL wait cycles in slow_clk_rtc - */ -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FFU -#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S) -#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000FFU -#define RTC_CNTL_PLL_BUF_WAIT_S 24 - -/** RTC_CNTL_TIMER2_REG register - * register description - */ -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) -/** RTC_CNTL_MIN_TIME_CK8M_OFF : R/W; bitpos: [31:24]; default: 1; - * minimal cycles in slow_clk_rtc for CK8M in power down state - */ -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FFU -#define RTC_CNTL_MIN_TIME_CK8M_OFF_M (RTC_CNTL_MIN_TIME_CK8M_OFF_V << RTC_CNTL_MIN_TIME_CK8M_OFF_S) -#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0x000000FFU -#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 - -/** RTC_CNTL_TIMER3_REG register - * register description - */ -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) -/** RTC_CNTL_WIFI_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; - * Need add description - */ -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FFU -#define RTC_CNTL_WIFI_WAIT_TIMER_M (RTC_CNTL_WIFI_WAIT_TIMER_V << RTC_CNTL_WIFI_WAIT_TIMER_S) -#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x000001FFU -#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 -/** RTC_CNTL_WIFI_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; - * Need add description - */ -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007FU -#define RTC_CNTL_WIFI_POWERUP_TIMER_M (RTC_CNTL_WIFI_POWERUP_TIMER_V << RTC_CNTL_WIFI_POWERUP_TIMER_S) -#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x0000007FU -#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 -/** RTC_CNTL_BT_WAIT_TIMER : R/W; bitpos: [24:16]; default: 8; - * Need add description - */ -#define RTC_CNTL_BT_WAIT_TIMER 0x000001FFU -#define RTC_CNTL_BT_WAIT_TIMER_M (RTC_CNTL_BT_WAIT_TIMER_V << RTC_CNTL_BT_WAIT_TIMER_S) -#define RTC_CNTL_BT_WAIT_TIMER_V 0x000001FFU -#define RTC_CNTL_BT_WAIT_TIMER_S 16 -/** RTC_CNTL_BT_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 5; - * Need add description - */ -#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007FU -#define RTC_CNTL_BT_POWERUP_TIMER_M (RTC_CNTL_BT_POWERUP_TIMER_V << RTC_CNTL_BT_POWERUP_TIMER_S) -#define RTC_CNTL_BT_POWERUP_TIMER_V 0x0000007FU -#define RTC_CNTL_BT_POWERUP_TIMER_S 25 - -/** RTC_CNTL_TIMER4_REG register - * register description - */ -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) -/** RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; - * Need add description - */ -#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FFU -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M (RTC_CNTL_CPU_TOP_WAIT_TIMER_V << RTC_CNTL_CPU_TOP_WAIT_TIMER_S) -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x000001FFU -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 -/** RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; - * Need add description - */ -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007FU -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M (RTC_CNTL_CPU_TOP_POWERUP_TIMER_V << RTC_CNTL_CPU_TOP_POWERUP_TIMER_S) -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x0000007FU -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 -/** RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FFU -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M (RTC_CNTL_DG_WRAP_WAIT_TIMER_V << RTC_CNTL_DG_WRAP_WAIT_TIMER_S) -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x000001FFU -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 -/** RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007FU -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M (RTC_CNTL_DG_WRAP_POWERUP_TIMER_V << RTC_CNTL_DG_WRAP_POWERUP_TIMER_S) -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x0000007FU -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 - -/** RTC_CNTL_TIMER5_REG register - * register description - */ -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) -/** RTC_CNTL_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 128; - * minimal sleep cycles in slow_clk_rtc - */ -#define RTC_CNTL_MIN_SLP_VAL 0x000000FFU -#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S) -#define RTC_CNTL_MIN_SLP_VAL_V 0x000000FFU -#define RTC_CNTL_MIN_SLP_VAL_S 8 - -/** RTC_CNTL_TIMER6_REG register - * register description - */ -#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) -/** RTC_CNTL_DG_PERI_WAIT_TIMER : R/W; bitpos: [24:16]; default: 8; - * Need add description - */ -#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FFU -#define RTC_CNTL_DG_PERI_WAIT_TIMER_M (RTC_CNTL_DG_PERI_WAIT_TIMER_V << RTC_CNTL_DG_PERI_WAIT_TIMER_S) -#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x000001FFU -#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 -/** RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 5; - * Need add description - */ -#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007FU -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M (RTC_CNTL_DG_PERI_POWERUP_TIMER_V << RTC_CNTL_DG_PERI_POWERUP_TIMER_S) -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x0000007FU -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 - -/** RTC_CNTL_ANA_CONF_REG register - * register description - */ -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) -/** RTC_CNTL_XPD_TRX_FORCE_PD : R/W; bitpos: [16]; default: 0; - * Need add description - */ -#define RTC_CNTL_XPD_TRX_FORCE_PD (BIT(16)) -#define RTC_CNTL_XPD_TRX_FORCE_PD_M (RTC_CNTL_XPD_TRX_FORCE_PD_V << RTC_CNTL_XPD_TRX_FORCE_PD_S) -#define RTC_CNTL_XPD_TRX_FORCE_PD_V 0x00000001U -#define RTC_CNTL_XPD_TRX_FORCE_PD_S 16 -/** RTC_CNTL_XPD_TRX_FORCE_PU : R/W; bitpos: [17]; default: 1; - * Need add description - */ -#define RTC_CNTL_XPD_TRX_FORCE_PU (BIT(17)) -#define RTC_CNTL_XPD_TRX_FORCE_PU_M (RTC_CNTL_XPD_TRX_FORCE_PU_V << RTC_CNTL_XPD_TRX_FORCE_PU_S) -#define RTC_CNTL_XPD_TRX_FORCE_PU_V 0x00000001U -#define RTC_CNTL_XPD_TRX_FORCE_PU_S 17 -/** RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W; bitpos: [18]; default: 1; - * Need add description - */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (RTC_CNTL_I2C_RESET_POR_FORCE_PD_V << RTC_CNTL_I2C_RESET_POR_FORCE_PD_S) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x00000001U -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 -/** RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (RTC_CNTL_I2C_RESET_POR_FORCE_PU_V << RTC_CNTL_I2C_RESET_POR_FORCE_PU_S) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x00000001U -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 -/** RTC_CNTL_GLITCH_RST_EN : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_M (RTC_CNTL_GLITCH_RST_EN_V << RTC_CNTL_GLITCH_RST_EN_S) -#define RTC_CNTL_GLITCH_RST_EN_V 0x00000001U -#define RTC_CNTL_GLITCH_RST_EN_S 20 -/** RTC_CNTL_PERI_I2C_PU : R/W; bitpos: [22]; default: 1; - * PLLA force power up - */ -#define RTC_CNTL_PERI_I2C_PU (BIT(22)) -#define RTC_CNTL_PERI_I2C_PU_M (RTC_CNTL_PERI_I2C_PU_V << RTC_CNTL_PERI_I2C_PU_S) -#define RTC_CNTL_PERI_I2C_PU_V 0x00000001U -#define RTC_CNTL_PERI_I2C_PU_S 22 - -#define RTC_CNTL_SAR_I2C_PU RTC_CNTL_PERI_I2C_PU -#define RTC_CNTL_SAR_I2C_PU_V RTC_CNTL_PERI_I2C_PU_M -#define RTC_CNTL_SAR_I2C_PU_M RTC_CNTL_PERI_I2C_PU_V -#define RTC_CNTL_SAR_I2C_PU_S RTC_CNTL_PERI_I2C_PU_S -/** RTC_CNTL_PLLA_FORCE_PD : R/W; bitpos: [23]; default: 1; - * PLLA force power down - */ -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_M (RTC_CNTL_PLLA_FORCE_PD_V << RTC_CNTL_PLLA_FORCE_PD_S) -#define RTC_CNTL_PLLA_FORCE_PD_V 0x00000001U -#define RTC_CNTL_PLLA_FORCE_PD_S 23 -/** RTC_CNTL_PLLA_FORCE_PU : R/W; bitpos: [24]; default: 0; - * PLLA force power up - */ -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_M (RTC_CNTL_PLLA_FORCE_PU_V << RTC_CNTL_PLLA_FORCE_PU_S) -#define RTC_CNTL_PLLA_FORCE_PU_V 0x00000001U -#define RTC_CNTL_PLLA_FORCE_PU_S 24 -/** RTC_CNTL_BBPLL_CAL_SLP_START : R/W; bitpos: [25]; default: 0; - * start BBPLL calibration during sleep - */ -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_M (RTC_CNTL_BBPLL_CAL_SLP_START_V << RTC_CNTL_BBPLL_CAL_SLP_START_S) -#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 -/** RTC_CNTL_PVTMON_PU : R/W; bitpos: [26]; default: 0; - * 1: PVTMON power up , otherwise power down - */ -#define RTC_CNTL_PVTMON_PU (BIT(26)) -#define RTC_CNTL_PVTMON_PU_M (RTC_CNTL_PVTMON_PU_V << RTC_CNTL_PVTMON_PU_S) -#define RTC_CNTL_PVTMON_PU_V 0x00000001U -#define RTC_CNTL_PVTMON_PU_S 26 -/** RTC_CNTL_TXRF_I2C_PU : R/W; bitpos: [27]; default: 0; - * 1: TXRF_I2C power up , otherwise power down - */ -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_M (RTC_CNTL_TXRF_I2C_PU_V << RTC_CNTL_TXRF_I2C_PU_S) -#define RTC_CNTL_TXRF_I2C_PU_V 0x00000001U -#define RTC_CNTL_TXRF_I2C_PU_S 27 -/** RTC_CNTL_RFRX_PBUS_PU : R/W; bitpos: [28]; default: 0; - * 1: RFRX_PBUS power up , otherwise power down - */ -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_M (RTC_CNTL_RFRX_PBUS_PU_V << RTC_CNTL_RFRX_PBUS_PU_S) -#define RTC_CNTL_RFRX_PBUS_PU_V 0x00000001U -#define RTC_CNTL_RFRX_PBUS_PU_S 28 -/** RTC_CNTL_CKGEN_I2C_PU : R/W; bitpos: [30]; default: 0; - * 1: CKGEN_I2C power up , otherwise power down - */ -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_M (RTC_CNTL_CKGEN_I2C_PU_V << RTC_CNTL_CKGEN_I2C_PU_S) -#define RTC_CNTL_CKGEN_I2C_PU_V 0x00000001U -#define RTC_CNTL_CKGEN_I2C_PU_S 30 -/** RTC_CNTL_PLL_I2C_PU : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_M (RTC_CNTL_PLL_I2C_PU_V << RTC_CNTL_PLL_I2C_PU_S) -#define RTC_CNTL_PLL_I2C_PU_V 0x00000001U -#define RTC_CNTL_PLL_I2C_PU_S 31 - -/** RTC_CNTL_RESET_STATE_REG register - * register description - */ -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) -/** RTC_CNTL_RESET_CAUSE_PROCPU : RO; bitpos: [5:0]; default: 0; - * reset cause of PRO CPU - */ -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003FU -#define RTC_CNTL_RESET_CAUSE_PROCPU_M (RTC_CNTL_RESET_CAUSE_PROCPU_V << RTC_CNTL_RESET_CAUSE_PROCPU_S) -#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x0000003FU -#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 -/** RTC_CNTL_RESET_CAUSE_APPCPU : RO; bitpos: [11:6]; default: 0; - * reset cause of APP CPU - */ -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003FU -#define RTC_CNTL_RESET_CAUSE_APPCPU_M (RTC_CNTL_RESET_CAUSE_APPCPU_V << RTC_CNTL_RESET_CAUSE_APPCPU_S) -#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x0000003FU -#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 -/** RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W; bitpos: [12]; default: 1; - * APP CPU state vector sel - */ -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V << RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S) -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x00000001U -#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 -/** RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W; bitpos: [13]; default: 1; - * PRO CPU state vector sel - */ -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V << RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S) -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x00000001U -#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 -/** RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO; bitpos: [14]; default: 0; - * PRO CPU reset_flag - */ -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (RTC_CNTL_ALL_RESET_FLAG_PROCPU_V << RTC_CNTL_ALL_RESET_FLAG_PROCPU_S) -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x00000001U -#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 -/** RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO; bitpos: [15]; default: 0; - * APP CPU reset flag - */ -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (RTC_CNTL_ALL_RESET_FLAG_APPCPU_V << RTC_CNTL_ALL_RESET_FLAG_APPCPU_S) -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x00000001U -#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 -/** RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO; bitpos: [16]; default: 0; - * clear PRO CPU reset_flag - */ -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V << RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x00000001U -#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 -/** RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO; bitpos: [17]; default: 0; - * clear APP CPU reset flag - */ -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V << RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S) -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x00000001U -#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 -/** RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W; bitpos: [18]; default: 0; - * APPCPU OcdHaltOnReset - */ -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V << RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S) -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x00000001U -#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 -/** RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W; bitpos: [19]; default: 0; - * PROCPU OcdHaltOnReset - */ -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V << RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S) -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x00000001U -#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 -/** RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V << RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S) -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x00000001U -#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 -/** RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V << RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S) -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x00000001U -#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 -/** RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V << RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x00000001U -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 -/** RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO; bitpos: [23]; default: 0; - * Need add description - */ -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V << RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S) -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x00000001U -#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 -/** RTC_CNTL_DRESET_MASK_APPCPU : R/W; bitpos: [24]; default: 0; - * Need add description - */ -#define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) -#define RTC_CNTL_DRESET_MASK_APPCPU_M (RTC_CNTL_DRESET_MASK_APPCPU_V << RTC_CNTL_DRESET_MASK_APPCPU_S) -#define RTC_CNTL_DRESET_MASK_APPCPU_V 0x00000001U -#define RTC_CNTL_DRESET_MASK_APPCPU_S 24 -/** RTC_CNTL_DRESET_MASK_PROCPU : R/W; bitpos: [25]; default: 0; - * Need add description - */ -#define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) -#define RTC_CNTL_DRESET_MASK_PROCPU_M (RTC_CNTL_DRESET_MASK_PROCPU_V << RTC_CNTL_DRESET_MASK_PROCPU_S) -#define RTC_CNTL_DRESET_MASK_PROCPU_V 0x00000001U -#define RTC_CNTL_DRESET_MASK_PROCPU_S 25 - -/** RTC_CNTL_WAKEUP_STATE_REG register - * register description - */ -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3c) -/** RTC_CNTL_WAKEUP_ENA : R/W; bitpos: [31:13]; default: 12; - * wakeup enable bitmap - */ -#define RTC_CNTL_WAKEUP_ENA 0x0007FFFFU -#define RTC_CNTL_WAKEUP_ENA_M (RTC_CNTL_WAKEUP_ENA_V << RTC_CNTL_WAKEUP_ENA_S) -#define RTC_CNTL_WAKEUP_ENA_V 0x0007FFFFU -#define RTC_CNTL_WAKEUP_ENA_S 13 - -/** RTC_CNTL_INT_ENA_REG register - * register description - */ -#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) -/** RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 -/** RTC_CNTL_SLP_REJECT_INT_ENA : R/W; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_M (RTC_CNTL_SLP_REJECT_INT_ENA_V << RTC_CNTL_SLP_REJECT_INT_ENA_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 -/** RTC_CNTL_WDT_INT_ENA : R/W; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_M (RTC_CNTL_WDT_INT_ENA_V << RTC_CNTL_WDT_INT_ENA_S) -#define RTC_CNTL_WDT_INT_ENA_V 0x00000001U -#define RTC_CNTL_WDT_INT_ENA_S 3 -/** RTC_CNTL_BROWN_OUT_INT_ENA : R/W; bitpos: [9]; default: 0; - * enable brown out interrupt - */ -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_M (RTC_CNTL_BROWN_OUT_INT_ENA_V << RTC_CNTL_BROWN_OUT_INT_ENA_S) -#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 -/** RTC_CNTL_MAIN_TIMER_INT_ENA : R/W; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (RTC_CNTL_MAIN_TIMER_INT_ENA_V << RTC_CNTL_MAIN_TIMER_INT_ENA_S) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 -/** RTC_CNTL_SWD_INT_ENA : R/W; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ -#define RTC_CNTL_SWD_INT_ENA (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_M (RTC_CNTL_SWD_INT_ENA_V << RTC_CNTL_SWD_INT_ENA_S) -#define RTC_CNTL_SWD_INT_ENA_V 0x00000001U -#define RTC_CNTL_SWD_INT_ENA_S 15 -/** RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (RTC_CNTL_XTAL32K_DEAD_INT_ENA_V << RTC_CNTL_XTAL32K_DEAD_INT_ENA_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x00000001U -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 -/** RTC_CNTL_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; - * enbale gitch det interrupt - */ -#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_M (RTC_CNTL_GLITCH_DET_INT_ENA_V << RTC_CNTL_GLITCH_DET_INT_ENA_S) -#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x00000001U -#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 -/** RTC_CNTL_BBPLL_CAL_INT_ENA : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_M (RTC_CNTL_BBPLL_CAL_INT_ENA_V << RTC_CNTL_BBPLL_CAL_INT_ENA_S) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 -/** RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA : RW; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_M (RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_V << RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_S) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_V 0x00000001U -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_S 21 -/** RTC_CNTL_VSET_DCDC_DONE_INT_ENA : R/W; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_M (RTC_CNTL_VSET_DCDC_DONE_INT_ENA_V << RTC_CNTL_VSET_DCDC_DONE_INT_ENA_S) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_S 22 - -/** RTC_CNTL_INT_RAW_REG register - * register description - */ -#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) -/** RTC_CNTL_SLP_WAKEUP_INT_RAW : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt raw - */ -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (RTC_CNTL_SLP_WAKEUP_INT_RAW_V << RTC_CNTL_SLP_WAKEUP_INT_RAW_S) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 -/** RTC_CNTL_SLP_REJECT_INT_RAW : RO; bitpos: [1]; default: 0; - * sleep reject interrupt raw - */ -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_M (RTC_CNTL_SLP_REJECT_INT_RAW_V << RTC_CNTL_SLP_REJECT_INT_RAW_S) -#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 -/** RTC_CNTL_WDT_INT_RAW : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt raw - */ -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_M (RTC_CNTL_WDT_INT_RAW_V << RTC_CNTL_WDT_INT_RAW_S) -#define RTC_CNTL_WDT_INT_RAW_V 0x00000001U -#define RTC_CNTL_WDT_INT_RAW_S 3 -/** RTC_CNTL_BROWN_OUT_INT_RAW : RO; bitpos: [9]; default: 0; - * brown out interrupt raw - */ -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_M (RTC_CNTL_BROWN_OUT_INT_RAW_V << RTC_CNTL_BROWN_OUT_INT_RAW_S) -#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 -/** RTC_CNTL_MAIN_TIMER_INT_RAW : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt raw - */ -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (RTC_CNTL_MAIN_TIMER_INT_RAW_V << RTC_CNTL_MAIN_TIMER_INT_RAW_S) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 -/** RTC_CNTL_SWD_INT_RAW : RO; bitpos: [15]; default: 0; - * super watch dog interrupt raw - */ -#define RTC_CNTL_SWD_INT_RAW (BIT(15)) -#define RTC_CNTL_SWD_INT_RAW_M (RTC_CNTL_SWD_INT_RAW_V << RTC_CNTL_SWD_INT_RAW_S) -#define RTC_CNTL_SWD_INT_RAW_V 0x00000001U -#define RTC_CNTL_SWD_INT_RAW_S 15 -/** RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt raw - */ -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (RTC_CNTL_XTAL32K_DEAD_INT_RAW_V << RTC_CNTL_XTAL32K_DEAD_INT_RAW_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x00000001U -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 -/** RTC_CNTL_GLITCH_DET_INT_RAW : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt_raw - */ -#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_RAW_M (RTC_CNTL_GLITCH_DET_INT_RAW_V << RTC_CNTL_GLITCH_DET_INT_RAW_S) -#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x00000001U -#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 -/** RTC_CNTL_BBPLL_CAL_INT_RAW : RO; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (RTC_CNTL_BBPLL_CAL_INT_RAW_V << RTC_CNTL_BBPLL_CAL_INT_RAW_S) -#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 -/** RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW : RO; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_M (RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_V << RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_S) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_V 0x00000001U -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_RAW_S 21 -/** RTC_CNTL_VSET_DCDC_DONE_INT_RAW : RO; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_M (RTC_CNTL_VSET_DCDC_DONE_INT_RAW_V << RTC_CNTL_VSET_DCDC_DONE_INT_RAW_S) -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_DONE_INT_RAW_S 22 - -/** RTC_CNTL_INT_ST_REG register - * register description - */ -#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) -/** RTC_CNTL_SLP_WAKEUP_INT_ST : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt state - */ -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (RTC_CNTL_SLP_WAKEUP_INT_ST_V << RTC_CNTL_SLP_WAKEUP_INT_ST_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 -/** RTC_CNTL_SLP_REJECT_INT_ST : RO; bitpos: [1]; default: 0; - * sleep reject interrupt state - */ -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_M (RTC_CNTL_SLP_REJECT_INT_ST_V << RTC_CNTL_SLP_REJECT_INT_ST_S) -#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 -/** RTC_CNTL_WDT_INT_ST : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt state - */ -#define RTC_CNTL_WDT_INT_ST (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_M (RTC_CNTL_WDT_INT_ST_V << RTC_CNTL_WDT_INT_ST_S) -#define RTC_CNTL_WDT_INT_ST_V 0x00000001U -#define RTC_CNTL_WDT_INT_ST_S 3 -/** RTC_CNTL_BROWN_OUT_INT_ST : RO; bitpos: [9]; default: 0; - * brown out interrupt state - */ -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ST_M (RTC_CNTL_BROWN_OUT_INT_ST_V << RTC_CNTL_BROWN_OUT_INT_ST_S) -#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 -/** RTC_CNTL_MAIN_TIMER_INT_ST : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt state - */ -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_M (RTC_CNTL_MAIN_TIMER_INT_ST_V << RTC_CNTL_MAIN_TIMER_INT_ST_S) -#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 -/** RTC_CNTL_SWD_INT_ST : RO; bitpos: [15]; default: 0; - * super watch dog interrupt state - */ -#define RTC_CNTL_SWD_INT_ST (BIT(15)) -#define RTC_CNTL_SWD_INT_ST_M (RTC_CNTL_SWD_INT_ST_V << RTC_CNTL_SWD_INT_ST_S) -#define RTC_CNTL_SWD_INT_ST_V 0x00000001U -#define RTC_CNTL_SWD_INT_ST_S 15 -/** RTC_CNTL_XTAL32K_DEAD_INT_ST : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt state - */ -#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (RTC_CNTL_XTAL32K_DEAD_INT_ST_V << RTC_CNTL_XTAL32K_DEAD_INT_ST_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x00000001U -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 -/** RTC_CNTL_GLITCH_DET_INT_ST : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt state - */ -#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ST_M (RTC_CNTL_GLITCH_DET_INT_ST_V << RTC_CNTL_GLITCH_DET_INT_ST_S) -#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x00000001U -#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 -/** RTC_CNTL_BBPLL_CAL_INT_ST : RO; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ST_M (RTC_CNTL_BBPLL_CAL_INT_ST_V << RTC_CNTL_BBPLL_CAL_INT_ST_S) -#define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 -/** RTC_CNTL_BLE_COMPARE_WAKE_INT_ST : RO; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_M (RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_V << RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_S) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_V 0x00000001U -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ST_S 21 -/** RTC_CNTL_VSET_DCDC_DONE_INT_ST : RO; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_M (RTC_CNTL_VSET_DCDC_DONE_INT_ST_V << RTC_CNTL_VSET_DCDC_DONE_INT_ST_S) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_DONE_INT_ST_S 22 - -/** RTC_CNTL_INT_CLR_REG register - * register description - */ -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4c) -/** RTC_CNTL_SLP_WAKEUP_INT_CLR : WO; bitpos: [0]; default: 0; - * Clear sleep wakeup interrupt state - */ -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (RTC_CNTL_SLP_WAKEUP_INT_CLR_V << RTC_CNTL_SLP_WAKEUP_INT_CLR_S) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 -/** RTC_CNTL_SLP_REJECT_INT_CLR : WO; bitpos: [1]; default: 0; - * Clear sleep reject interrupt state - */ -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_M (RTC_CNTL_SLP_REJECT_INT_CLR_V << RTC_CNTL_SLP_REJECT_INT_CLR_S) -#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 -/** RTC_CNTL_WDT_INT_CLR : WO; bitpos: [3]; default: 0; - * Clear RTC WDT interrupt state - */ -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_M (RTC_CNTL_WDT_INT_CLR_V << RTC_CNTL_WDT_INT_CLR_S) -#define RTC_CNTL_WDT_INT_CLR_V 0x00000001U -#define RTC_CNTL_WDT_INT_CLR_S 3 -/** RTC_CNTL_BROWN_OUT_INT_CLR : WO; bitpos: [9]; default: 0; - * Clear brown out interrupt state - */ -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_M (RTC_CNTL_BROWN_OUT_INT_CLR_V << RTC_CNTL_BROWN_OUT_INT_CLR_S) -#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 -/** RTC_CNTL_MAIN_TIMER_INT_CLR : WO; bitpos: [10]; default: 0; - * Clear RTC main timer interrupt state - */ -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (RTC_CNTL_MAIN_TIMER_INT_CLR_V << RTC_CNTL_MAIN_TIMER_INT_CLR_S) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 -/** RTC_CNTL_SWD_INT_CLR : WO; bitpos: [15]; default: 0; - * Clear super watch dog interrupt state - */ -#define RTC_CNTL_SWD_INT_CLR (BIT(15)) -#define RTC_CNTL_SWD_INT_CLR_M (RTC_CNTL_SWD_INT_CLR_V << RTC_CNTL_SWD_INT_CLR_S) -#define RTC_CNTL_SWD_INT_CLR_V 0x00000001U -#define RTC_CNTL_SWD_INT_CLR_S 15 -/** RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO; bitpos: [16]; default: 0; - * Clear RTC WDT interrupt state - */ -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (RTC_CNTL_XTAL32K_DEAD_INT_CLR_V << RTC_CNTL_XTAL32K_DEAD_INT_CLR_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x00000001U -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 -/** RTC_CNTL_GLITCH_DET_INT_CLR : WO; bitpos: [19]; default: 0; - * Clear glitch det interrupt state - */ -#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_CLR_M (RTC_CNTL_GLITCH_DET_INT_CLR_V << RTC_CNTL_GLITCH_DET_INT_CLR_S) -#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x00000001U -#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 -/** RTC_CNTL_BBPLL_CAL_INT_CLR : WO; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_CLR_M (RTC_CNTL_BBPLL_CAL_INT_CLR_V << RTC_CNTL_BBPLL_CAL_INT_CLR_S) -#define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 -/** RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR : WO; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_M (RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_V << RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_S) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_V 0x00000001U -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_CLR_S 21 -/** RTC_CNTL_VSET_DCDC_DONE_INT_CLR : WO; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_M (RTC_CNTL_VSET_DCDC_DONE_INT_CLR_V << RTC_CNTL_VSET_DCDC_DONE_INT_CLR_S) -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_DONE_INT_CLR_S 22 - -/** RTC_CNTL_STORE0_REG register - * register description - */ -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) -/** RTC_CNTL_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH0 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH0_M (RTC_CNTL_SCRATCH0_V << RTC_CNTL_SCRATCH0_S) -#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH0_S 0 - -/** RTC_CNTL_STORE1_REG register - * register description - */ -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) -/** RTC_CNTL_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH1 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH1_M (RTC_CNTL_SCRATCH1_V << RTC_CNTL_SCRATCH1_S) -#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH1_S 0 - -/** RTC_CNTL_STORE2_REG register - * register description - */ -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) -/** RTC_CNTL_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH2 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH2_M (RTC_CNTL_SCRATCH2_V << RTC_CNTL_SCRATCH2_S) -#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH2_S 0 - -/** RTC_CNTL_STORE3_REG register - * register description - */ -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5c) -/** RTC_CNTL_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH3 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH3_M (RTC_CNTL_SCRATCH3_V << RTC_CNTL_SCRATCH3_S) -#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH3_S 0 - -/** RTC_CNTL_EXT_XTL_CONF_REG register - * register description - */ -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) -/** RTC_CNTL_XTAL32K_WDT_EN : R/W; bitpos: [0]; default: 0; - * xtal 32k watch dog enable - */ -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_M (RTC_CNTL_XTAL32K_WDT_EN_V << RTC_CNTL_XTAL32K_WDT_EN_S) -#define RTC_CNTL_XTAL32K_WDT_EN_V 0x00000001U -#define RTC_CNTL_XTAL32K_WDT_EN_S 0 -/** RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W; bitpos: [1]; default: 0; - * xtal 32k watch dog clock force on - */ -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (RTC_CNTL_XTAL32K_WDT_CLK_FO_V << RTC_CNTL_XTAL32K_WDT_CLK_FO_S) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x00000001U -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 -/** RTC_CNTL_XTAL32K_WDT_RESET : R/W; bitpos: [2]; default: 0; - * xtal 32k watch dog sw reset - */ -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_M (RTC_CNTL_XTAL32K_WDT_RESET_V << RTC_CNTL_XTAL32K_WDT_RESET_S) -#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x00000001U -#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 -/** RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W; bitpos: [3]; default: 0; - * xtal 32k external xtal clock force on - */ -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (RTC_CNTL_XTAL32K_EXT_CLK_FO_V << RTC_CNTL_XTAL32K_EXT_CLK_FO_S) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x00000001U -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 -/** RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W; bitpos: [4]; default: 0; - * xtal 32k switch to back up clock when xtal is dead - */ -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (RTC_CNTL_XTAL32K_AUTO_BACKUP_V << RTC_CNTL_XTAL32K_AUTO_BACKUP_S) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x00000001U -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 -/** RTC_CNTL_XTAL32K_AUTO_RESTART : R/W; bitpos: [5]; default: 0; - * xtal 32k restart xtal when xtal is dead - */ -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (RTC_CNTL_XTAL32K_AUTO_RESTART_V << RTC_CNTL_XTAL32K_AUTO_RESTART_S) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x00000001U -#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 -/** RTC_CNTL_XTAL32K_AUTO_RETURN : R/W; bitpos: [6]; default: 0; - * xtal 32k switch back xtal when xtal is restarted - */ -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (RTC_CNTL_XTAL32K_AUTO_RETURN_V << RTC_CNTL_XTAL32K_AUTO_RETURN_S) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x00000001U -#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 -/** RTC_CNTL_XTAL32K_XPD_FORCE : R/W; bitpos: [7]; default: 1; - * Xtal 32k xpd control by sw or fsm - */ -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_M (RTC_CNTL_XTAL32K_XPD_FORCE_V << RTC_CNTL_XTAL32K_XPD_FORCE_S) -#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x00000001U -#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 -/** RTC_CNTL_ENCKINIT_XTAL_32K : R/W; bitpos: [8]; default: 0; - * apply an internal clock to help xtal 32k to start - */ -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_M (RTC_CNTL_ENCKINIT_XTAL_32K_V << RTC_CNTL_ENCKINIT_XTAL_32K_S) -#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x00000001U -#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 -/** RTC_CNTL_DBUF_XTAL_32K : R/W; bitpos: [9]; default: 0; - * 0: single-end buffer 1: differential buffer - */ -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_M (RTC_CNTL_DBUF_XTAL_32K_V << RTC_CNTL_DBUF_XTAL_32K_S) -#define RTC_CNTL_DBUF_XTAL_32K_V 0x00000001U -#define RTC_CNTL_DBUF_XTAL_32K_S 9 -/** RTC_CNTL_DGM_XTAL_32K : R/W; bitpos: [12:10]; default: 3; - * xtal_32k gm control - */ -#define RTC_CNTL_DGM_XTAL_32K 0x00000007U -#define RTC_CNTL_DGM_XTAL_32K_M (RTC_CNTL_DGM_XTAL_32K_V << RTC_CNTL_DGM_XTAL_32K_S) -#define RTC_CNTL_DGM_XTAL_32K_V 0x00000007U -#define RTC_CNTL_DGM_XTAL_32K_S 10 -/** RTC_CNTL_DRES_XTAL_32K : R/W; bitpos: [15:13]; default: 3; - * DRES_XTAL_32K - */ -#define RTC_CNTL_DRES_XTAL_32K 0x00000007U -#define RTC_CNTL_DRES_XTAL_32K_M (RTC_CNTL_DRES_XTAL_32K_V << RTC_CNTL_DRES_XTAL_32K_S) -#define RTC_CNTL_DRES_XTAL_32K_V 0x00000007U -#define RTC_CNTL_DRES_XTAL_32K_S 13 -/** RTC_CNTL_XPD_XTAL_32K : R/W; bitpos: [16]; default: 0; - * XPD_XTAL_32K - */ -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_M (RTC_CNTL_XPD_XTAL_32K_V << RTC_CNTL_XPD_XTAL_32K_S) -#define RTC_CNTL_XPD_XTAL_32K_V 0x00000001U -#define RTC_CNTL_XPD_XTAL_32K_S 16 -/** RTC_CNTL_DAC_XTAL_32K : R/W; bitpos: [19:17]; default: 3; - * DAC_XTAL_32K - */ -#define RTC_CNTL_DAC_XTAL_32K 0x00000007U -#define RTC_CNTL_DAC_XTAL_32K_M (RTC_CNTL_DAC_XTAL_32K_V << RTC_CNTL_DAC_XTAL_32K_S) -#define RTC_CNTL_DAC_XTAL_32K_V 0x00000007U -#define RTC_CNTL_DAC_XTAL_32K_S 17 -/** RTC_CNTL_WDT_STATE : RO; bitpos: [22:20]; default: 0; - * state of 32k_wdt - */ -#define RTC_CNTL_WDT_STATE 0x00000007U -#define RTC_CNTL_WDT_STATE_M (RTC_CNTL_WDT_STATE_V << RTC_CNTL_WDT_STATE_S) -#define RTC_CNTL_WDT_STATE_V 0x00000007U -#define RTC_CNTL_WDT_STATE_S 20 -/** RTC_CNTL_XTAL32K_GPIO_SEL : R/W; bitpos: [23]; default: 0; - * XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C - */ -#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) -#define RTC_CNTL_XTAL32K_GPIO_SEL_M (RTC_CNTL_XTAL32K_GPIO_SEL_V << RTC_CNTL_XTAL32K_GPIO_SEL_S) -#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x00000001U -#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 -/** RTC_CNTL_XTL_EXT_CTR_LV : R/W; bitpos: [30]; default: 0; - * 0: power down XTAL at high level, 1: power down XTAL at low level - */ -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_M (RTC_CNTL_XTL_EXT_CTR_LV_V << RTC_CNTL_XTL_EXT_CTR_LV_S) -#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x00000001U -#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 -/** RTC_CNTL_XTL_EXT_CTR_EN : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_M (RTC_CNTL_XTL_EXT_CTR_EN_V << RTC_CNTL_XTL_EXT_CTR_EN_S) -#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x00000001U -#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 - -/** RTC_CNTL_EXT_WAKEUP_CONF_REG register - * register description - */ -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) -/** RTC_CNTL_GPIO_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; - * enable filter for gpio wakeup event - */ -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (RTC_CNTL_GPIO_WAKEUP_FILTER_V << RTC_CNTL_GPIO_WAKEUP_FILTER_S) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x00000001U -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 - -/** RTC_CNTL_SLP_REJECT_CONF_REG register - * register description - */ -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) -/** RTC_CNTL_SLEEP_REJECT_ENA : R/W; bitpos: [29:11]; default: 0; - * sleep reject enable - */ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0007FFFFU -#define RTC_CNTL_SLEEP_REJECT_ENA_M (RTC_CNTL_SLEEP_REJECT_ENA_V << RTC_CNTL_SLEEP_REJECT_ENA_S) -#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x0007FFFFU -#define RTC_CNTL_SLEEP_REJECT_ENA_S 11 -/** RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W; bitpos: [30]; default: 0; - * enable reject for light sleep - */ -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (RTC_CNTL_LIGHT_SLP_REJECT_EN_V << RTC_CNTL_LIGHT_SLP_REJECT_EN_S) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x00000001U -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 -/** RTC_CNTL_DEEP_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; - * enable reject for deep sleep - */ -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (RTC_CNTL_DEEP_SLP_REJECT_EN_V << RTC_CNTL_DEEP_SLP_REJECT_EN_S) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x00000001U -#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 - -/** RTC_CNTL_CPU_PERIOD_CONF_REG register - * register description - */ -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) -/** RTC_CNTL_CPUSEL_CONF : R/W; bitpos: [29]; default: 0; - * CPU sel option - */ -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_M (RTC_CNTL_CPUSEL_CONF_V << RTC_CNTL_CPUSEL_CONF_S) -#define RTC_CNTL_CPUSEL_CONF_V 0x00000001U -#define RTC_CNTL_CPUSEL_CONF_S 29 -/** RTC_CNTL_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0; - * Need add description - */ -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003U -#define RTC_CNTL_CPUPERIOD_SEL_M (RTC_CNTL_CPUPERIOD_SEL_V << RTC_CNTL_CPUPERIOD_SEL_S) -#define RTC_CNTL_CPUPERIOD_SEL_V 0x00000003U -#define RTC_CNTL_CPUPERIOD_SEL_S 30 - -/** RTC_CNTL_CLK_CONF_REG register - * register description - */ -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) -/** RTC_CNTL_BLE_TMR_RST : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_TMR_RST (BIT(0)) -#define RTC_CNTL_BLE_TMR_RST_M (RTC_CNTL_BLE_TMR_RST_V << RTC_CNTL_BLE_TMR_RST_S) -#define RTC_CNTL_BLE_TMR_RST_V 0x00000001U -#define RTC_CNTL_BLE_TMR_RST_S 0 -/** RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (RTC_CNTL_EFUSE_CLK_FORCE_GATING_V << RTC_CNTL_EFUSE_CLK_FORCE_GATING_S) -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x00000001U -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 -/** RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V << RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S) -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x00000001U -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 -/** RTC_CNTL_CK8M_DIV_SEL_VLD : R/W; bitpos: [3]; default: 1; - * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set - * vld to actually switch the clk - */ -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (RTC_CNTL_CK8M_DIV_SEL_VLD_V << RTC_CNTL_CK8M_DIV_SEL_VLD_S) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x00000001U -#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 -/** RTC_CNTL_DIG_XTAL32K_EN : R/W; bitpos: [4]; default: 0; - * enable CK_XTAL_32K for digital core (no relationship with RTC core) - */ -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(4)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (RTC_CNTL_DIG_XTAL32K_EN_V << RTC_CNTL_DIG_XTAL32K_EN_S) -#define RTC_CNTL_DIG_XTAL32K_EN_V 0x00000001U -#define RTC_CNTL_DIG_XTAL32K_EN_S 4 -/** RTC_CNTL_DIG_RC32K_EN : R/W; bitpos: [5]; default: 1; - * enable RC32K for digital core (no relationship with RTC core) - */ -#define RTC_CNTL_DIG_RC32K_EN (BIT(5)) -#define RTC_CNTL_DIG_RC32K_EN_M (RTC_CNTL_DIG_RC32K_EN_V << RTC_CNTL_DIG_RC32K_EN_S) -#define RTC_CNTL_DIG_RC32K_EN_V 0x00000001U -#define RTC_CNTL_DIG_RC32K_EN_S 5 -/** RTC_CNTL_DIG_CLK8M_EN : R/W; bitpos: [6]; default: 0; - * enable CK8M for digital core (no relationship with RTC core) - */ -#define RTC_CNTL_DIG_CLK8M_EN (BIT(6)) -#define RTC_CNTL_DIG_CLK8M_EN_M (RTC_CNTL_DIG_CLK8M_EN_V << RTC_CNTL_DIG_CLK8M_EN_S) -#define RTC_CNTL_DIG_CLK8M_EN_V 0x00000001U -#define RTC_CNTL_DIG_CLK8M_EN_S 6 -/** RTC_CNTL_BLE_TIMER_SEL : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_TIMER_SEL (BIT(7)) -#define RTC_CNTL_BLE_TIMER_SEL_M (RTC_CNTL_BLE_TIMER_SEL_V << RTC_CNTL_BLE_TIMER_SEL_S) -#define RTC_CNTL_BLE_TIMER_SEL_V 0x00000001U -#define RTC_CNTL_BLE_TIMER_SEL_S 7 -/** RTC_CNTL_CK8M_DIV_SEL : R/W; bitpos: [12:10]; default: 3; - * divider = reg_ck8m_div_sel + 1 - */ -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007U -#define RTC_CNTL_CK8M_DIV_SEL_M (RTC_CNTL_CK8M_DIV_SEL_V << RTC_CNTL_CK8M_DIV_SEL_S) -#define RTC_CNTL_CK8M_DIV_SEL_V 0x00000007U -#define RTC_CNTL_CK8M_DIV_SEL_S 10 -/** RTC_CNTL_XTAL_FORCE_NOGATING : R/W; bitpos: [13]; default: 0; - * XTAL force no gating during sleep - */ -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(13)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_FORCE_NOGATING_S) -#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x00000001U -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 13 -/** RTC_CNTL_CK8M_FORCE_NOGATING : R/W; bitpos: [14]; default: 0; - * CK8M force no gating during sleep - */ -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(14)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (RTC_CNTL_CK8M_FORCE_NOGATING_V << RTC_CNTL_CK8M_FORCE_NOGATING_S) -#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x00000001U -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 14 -/** RTC_CNTL_CK8M_DFREQ : R/W; bitpos: [24:15]; default: 600; - * CK8M_DFREQ - */ -#define RTC_CNTL_CK8M_DFREQ 0x000003FFU -#define RTC_CNTL_CK8M_DFREQ_M (RTC_CNTL_CK8M_DFREQ_V << RTC_CNTL_CK8M_DFREQ_S) -#define RTC_CNTL_CK8M_DFREQ_V 0x000003FFU -#define RTC_CNTL_CK8M_DFREQ_S 15 -/** RTC_CNTL_CK8M_FORCE_PD : R/W; bitpos: [25]; default: 0; - * CK8M force power down - */ -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_M (RTC_CNTL_CK8M_FORCE_PD_V << RTC_CNTL_CK8M_FORCE_PD_S) -#define RTC_CNTL_CK8M_FORCE_PD_V 0x00000001U -#define RTC_CNTL_CK8M_FORCE_PD_S 25 -/** RTC_CNTL_CK8M_FORCE_PU : R/W; bitpos: [26]; default: 0; - * CK8M force power up - */ -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_M (RTC_CNTL_CK8M_FORCE_PU_V << RTC_CNTL_CK8M_FORCE_PU_S) -#define RTC_CNTL_CK8M_FORCE_PU_V 0x00000001U -#define RTC_CNTL_CK8M_FORCE_PU_S 26 -/** RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V << RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x00000001U -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 -/** RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W; bitpos: [28]; default: 1; - * Need add description - */ -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x00000001U -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 -/** RTC_CNTL_FAST_CLK_RTC_SEL : R/W; bitpos: [29]; default: 0; - * fast_clk_rtc sel. 0: XTAL div 2, 1: CK8M - */ -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_M (RTC_CNTL_FAST_CLK_RTC_SEL_V << RTC_CNTL_FAST_CLK_RTC_SEL_S) -#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x00000001U -#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 -/** RTC_CNTL_ANA_CLK_RTC_SEL : R/W; bitpos: [31:30]; default: 0; - * Need add description - */ -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003U -#define RTC_CNTL_ANA_CLK_RTC_SEL_M (RTC_CNTL_ANA_CLK_RTC_SEL_V << RTC_CNTL_ANA_CLK_RTC_SEL_S) -#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x00000003U -#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 - -/** RTC_CNTL_SLOW_CLK_CONF_REG register - * register description - */ -#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) -/** RTC_CNTL_ANA_CLK_PD_SLP : R/W; bitpos: [19]; default: 0; - * Need add description - */ -#define RTC_CNTL_ANA_CLK_PD_SLP (BIT(19)) -#define RTC_CNTL_ANA_CLK_PD_SLP_M (RTC_CNTL_ANA_CLK_PD_SLP_V << RTC_CNTL_ANA_CLK_PD_SLP_S) -#define RTC_CNTL_ANA_CLK_PD_SLP_V 0x00000001U -#define RTC_CNTL_ANA_CLK_PD_SLP_S 19 -/** RTC_CNTL_ANA_CLK_PD_MONITOR : R/W; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_ANA_CLK_PD_MONITOR (BIT(20)) -#define RTC_CNTL_ANA_CLK_PD_MONITOR_M (RTC_CNTL_ANA_CLK_PD_MONITOR_V << RTC_CNTL_ANA_CLK_PD_MONITOR_S) -#define RTC_CNTL_ANA_CLK_PD_MONITOR_V 0x00000001U -#define RTC_CNTL_ANA_CLK_PD_MONITOR_S 20 -/** RTC_CNTL_ANA_CLK_PD_IDLE : R/W; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_ANA_CLK_PD_IDLE (BIT(21)) -#define RTC_CNTL_ANA_CLK_PD_IDLE_M (RTC_CNTL_ANA_CLK_PD_IDLE_V << RTC_CNTL_ANA_CLK_PD_IDLE_S) -#define RTC_CNTL_ANA_CLK_PD_IDLE_V 0x00000001U -#define RTC_CNTL_ANA_CLK_PD_IDLE_S 21 -/** RTC_CNTL_ANA_CLK_DIV_VLD : R/W; bitpos: [22]; default: 1; - * used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to - * actually switch the clk - */ -#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) -#define RTC_CNTL_ANA_CLK_DIV_VLD_M (RTC_CNTL_ANA_CLK_DIV_VLD_V << RTC_CNTL_ANA_CLK_DIV_VLD_S) -#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x00000001U -#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 -/** RTC_CNTL_ANA_CLK_DIV : R/W; bitpos: [30:23]; default: 0; - * Need add description - */ -#define RTC_CNTL_ANA_CLK_DIV 0x000000FFU -#define RTC_CNTL_ANA_CLK_DIV_M (RTC_CNTL_ANA_CLK_DIV_V << RTC_CNTL_ANA_CLK_DIV_S) -#define RTC_CNTL_ANA_CLK_DIV_V 0x000000FFU -#define RTC_CNTL_ANA_CLK_DIV_S 23 -/** RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (RTC_CNTL_SLOW_CLK_NEXT_EDGE_V << RTC_CNTL_SLOW_CLK_NEXT_EDGE_S) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x00000001U -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 - -/** RTC_CNTL_SDIO_CONF_REG register - * register description - */ -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) -/** RTC_CNTL_SDIO_TIMER_TARGET : R/W; bitpos: [7:0]; default: 10; - * timer count to apply reg_sdio_dcap after sdio power on - */ -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FFU -#define RTC_CNTL_SDIO_TIMER_TARGET_M (RTC_CNTL_SDIO_TIMER_TARGET_V << RTC_CNTL_SDIO_TIMER_TARGET_S) -#define RTC_CNTL_SDIO_TIMER_TARGET_V 0x000000FFU -#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 -/** RTC_CNTL_SDIO_DTHDRV : R/W; bitpos: [10:9]; default: 3; - * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 - * after several us. - */ -#define RTC_CNTL_SDIO_DTHDRV 0x00000003U -#define RTC_CNTL_SDIO_DTHDRV_M (RTC_CNTL_SDIO_DTHDRV_V << RTC_CNTL_SDIO_DTHDRV_S) -#define RTC_CNTL_SDIO_DTHDRV_V 0x00000003U -#define RTC_CNTL_SDIO_DTHDRV_S 9 -/** RTC_CNTL_SDIO_DCAP : R/W; bitpos: [12:11]; default: 3; - * ability to prevent LDO from overshoot - */ -#define RTC_CNTL_SDIO_DCAP 0x00000003U -#define RTC_CNTL_SDIO_DCAP_M (RTC_CNTL_SDIO_DCAP_V << RTC_CNTL_SDIO_DCAP_S) -#define RTC_CNTL_SDIO_DCAP_V 0x00000003U -#define RTC_CNTL_SDIO_DCAP_S 11 -/** RTC_CNTL_SDIO_INITI : R/W; bitpos: [14:13]; default: 1; - * add resistor from ldo output to ground. 0: no res, 1: 6k, 2: 4k, 3: 2k - */ -#define RTC_CNTL_SDIO_INITI 0x00000003U -#define RTC_CNTL_SDIO_INITI_M (RTC_CNTL_SDIO_INITI_V << RTC_CNTL_SDIO_INITI_S) -#define RTC_CNTL_SDIO_INITI_V 0x00000003U -#define RTC_CNTL_SDIO_INITI_S 13 -/** RTC_CNTL_SDIO_EN_INITI : R/W; bitpos: [15]; default: 1; - * 0 to set init[1:0]=0 - */ -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_M (RTC_CNTL_SDIO_EN_INITI_V << RTC_CNTL_SDIO_EN_INITI_S) -#define RTC_CNTL_SDIO_EN_INITI_V 0x00000001U -#define RTC_CNTL_SDIO_EN_INITI_S 15 -/** RTC_CNTL_SDIO_DCURLIM : R/W; bitpos: [18:16]; default: 0; - * tune current limit threshold when tieh = 0. About 800mA/(8+d) - */ -#define RTC_CNTL_SDIO_DCURLIM 0x00000007U -#define RTC_CNTL_SDIO_DCURLIM_M (RTC_CNTL_SDIO_DCURLIM_V << RTC_CNTL_SDIO_DCURLIM_S) -#define RTC_CNTL_SDIO_DCURLIM_V 0x00000007U -#define RTC_CNTL_SDIO_DCURLIM_S 16 -/** RTC_CNTL_SDIO_MODECURLIM : R/W; bitpos: [19]; default: 0; - * select current limit mode - */ -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_M (RTC_CNTL_SDIO_MODECURLIM_V << RTC_CNTL_SDIO_MODECURLIM_S) -#define RTC_CNTL_SDIO_MODECURLIM_V 0x00000001U -#define RTC_CNTL_SDIO_MODECURLIM_S 19 -/** RTC_CNTL_SDIO_ENCURLIM : R/W; bitpos: [20]; default: 1; - * enable current limit - */ -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_M (RTC_CNTL_SDIO_ENCURLIM_V << RTC_CNTL_SDIO_ENCURLIM_S) -#define RTC_CNTL_SDIO_ENCURLIM_V 0x00000001U -#define RTC_CNTL_SDIO_ENCURLIM_S 20 -/** RTC_CNTL_SDIO_PD_EN : R/W; bitpos: [21]; default: 1; - * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 - */ -#define RTC_CNTL_SDIO_PD_EN (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_M (RTC_CNTL_SDIO_PD_EN_V << RTC_CNTL_SDIO_PD_EN_S) -#define RTC_CNTL_SDIO_PD_EN_V 0x00000001U -#define RTC_CNTL_SDIO_PD_EN_S 21 -/** RTC_CNTL_SDIO_FORCE : R/W; bitpos: [22]; default: 0; - * 1: use SW option to control SDIO_REG ,0: use state machine - */ -#define RTC_CNTL_SDIO_FORCE (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_M (RTC_CNTL_SDIO_FORCE_V << RTC_CNTL_SDIO_FORCE_S) -#define RTC_CNTL_SDIO_FORCE_V 0x00000001U -#define RTC_CNTL_SDIO_FORCE_S 22 -/** RTC_CNTL_SDIO_TIEH : R/W; bitpos: [23]; default: 1; - * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 - */ -#define RTC_CNTL_SDIO_TIEH (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_M (RTC_CNTL_SDIO_TIEH_V << RTC_CNTL_SDIO_TIEH_S) -#define RTC_CNTL_SDIO_TIEH_V 0x00000001U -#define RTC_CNTL_SDIO_TIEH_S 23 -/** RTC_CNTL_REG1P8_READY : RO; bitpos: [24]; default: 0; - * read only register for REG1P8_READY - */ -#define RTC_CNTL_REG1P8_READY (BIT(24)) -#define RTC_CNTL_REG1P8_READY_M (RTC_CNTL_REG1P8_READY_V << RTC_CNTL_REG1P8_READY_S) -#define RTC_CNTL_REG1P8_READY_V 0x00000001U -#define RTC_CNTL_REG1P8_READY_S 24 -/** RTC_CNTL_DREFL_SDIO : R/W; bitpos: [26:25]; default: 1; - * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 - */ -#define RTC_CNTL_DREFL_SDIO 0x00000003U -#define RTC_CNTL_DREFL_SDIO_M (RTC_CNTL_DREFL_SDIO_V << RTC_CNTL_DREFL_SDIO_S) -#define RTC_CNTL_DREFL_SDIO_V 0x00000003U -#define RTC_CNTL_DREFL_SDIO_S 25 -/** RTC_CNTL_DREFM_SDIO : R/W; bitpos: [28:27]; default: 1; - * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 - */ -#define RTC_CNTL_DREFM_SDIO 0x00000003U -#define RTC_CNTL_DREFM_SDIO_M (RTC_CNTL_DREFM_SDIO_V << RTC_CNTL_DREFM_SDIO_S) -#define RTC_CNTL_DREFM_SDIO_V 0x00000003U -#define RTC_CNTL_DREFM_SDIO_S 27 -/** RTC_CNTL_DREFH_SDIO : R/W; bitpos: [30:29]; default: 0; - * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 - */ -#define RTC_CNTL_DREFH_SDIO 0x00000003U -#define RTC_CNTL_DREFH_SDIO_M (RTC_CNTL_DREFH_SDIO_V << RTC_CNTL_DREFH_SDIO_S) -#define RTC_CNTL_DREFH_SDIO_V 0x00000003U -#define RTC_CNTL_DREFH_SDIO_S 29 -/** RTC_CNTL_XPD_SDIO_REG : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_M (RTC_CNTL_XPD_SDIO_REG_V << RTC_CNTL_XPD_SDIO_REG_S) -#define RTC_CNTL_XPD_SDIO_REG_V 0x00000001U -#define RTC_CNTL_XPD_SDIO_REG_S 31 - -/** RTC_CNTL_BIAS_CONF_REG register - * register description - */ -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7c) -/** RTC_CNTL_BIAS_BUF_IDLE : R/W; bitpos: [10]; default: 0; - * Need add description - */ -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_M (RTC_CNTL_BIAS_BUF_IDLE_V << RTC_CNTL_BIAS_BUF_IDLE_S) -#define RTC_CNTL_BIAS_BUF_IDLE_V 0x00000001U -#define RTC_CNTL_BIAS_BUF_IDLE_S 10 -/** RTC_CNTL_BIAS_BUF_WAKE : R/W; bitpos: [11]; default: 1; - * Need add description - */ -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_M (RTC_CNTL_BIAS_BUF_WAKE_V << RTC_CNTL_BIAS_BUF_WAKE_S) -#define RTC_CNTL_BIAS_BUF_WAKE_V 0x00000001U -#define RTC_CNTL_BIAS_BUF_WAKE_S 11 -/** RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W; bitpos: [12]; default: 0; - * Need add description - */ -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (RTC_CNTL_BIAS_BUF_DEEP_SLP_V << RTC_CNTL_BIAS_BUF_DEEP_SLP_S) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x00000001U -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 -/** RTC_CNTL_BIAS_BUF_MONITOR : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_M (RTC_CNTL_BIAS_BUF_MONITOR_V << RTC_CNTL_BIAS_BUF_MONITOR_S) -#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x00000001U -#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 -/** RTC_CNTL_PD_CUR_DEEP_SLP : R/W; bitpos: [14]; default: 0; - * xpd cur when rtc in sleep_state - */ -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_M (RTC_CNTL_PD_CUR_DEEP_SLP_V << RTC_CNTL_PD_CUR_DEEP_SLP_S) -#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x00000001U -#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 -/** RTC_CNTL_PD_CUR_MONITOR : R/W; bitpos: [15]; default: 0; - * xpd cur when rtc in monitor state - */ -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_M (RTC_CNTL_PD_CUR_MONITOR_V << RTC_CNTL_PD_CUR_MONITOR_S) -#define RTC_CNTL_PD_CUR_MONITOR_V 0x00000001U -#define RTC_CNTL_PD_CUR_MONITOR_S 15 -/** RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W; bitpos: [16]; default: 1; - * bias_sleep when rtc in sleep_state - */ -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V << RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x00000001U -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 -/** RTC_CNTL_BIAS_SLEEP_MONITOR : R/W; bitpos: [17]; default: 0; - * bias_sleep when rtc in monitor state - */ -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (RTC_CNTL_BIAS_SLEEP_MONITOR_V << RTC_CNTL_BIAS_SLEEP_MONITOR_S) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x00000001U -#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 -/** RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W; bitpos: [21:18]; default: 0; - * DBG_ATTEN when rtc in sleep state - */ -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000FU -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M (RTC_CNTL_DBG_ATTEN_DEEP_SLP_V << RTC_CNTL_DBG_ATTEN_DEEP_SLP_S) -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0x0000000FU -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 -/** RTC_CNTL_DBG_ATTEN_MONITOR : R/W; bitpos: [25:22]; default: 0; - * DBG_ATTEN when rtc in monitor state - */ -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000FU -#define RTC_CNTL_DBG_ATTEN_MONITOR_M (RTC_CNTL_DBG_ATTEN_MONITOR_V << RTC_CNTL_DBG_ATTEN_MONITOR_S) -#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0x0000000FU -#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 -/** RTC_CNTL_XPD_DCDC_SLP : R/W; bitpos: [26]; default: 1; - * Need add description - */ -#define RTC_CNTL_XPD_DCDC_SLP (BIT(26)) -#define RTC_CNTL_XPD_DCDC_SLP_M (RTC_CNTL_XPD_DCDC_SLP_V << RTC_CNTL_XPD_DCDC_SLP_S) -#define RTC_CNTL_XPD_DCDC_SLP_V 0x00000001U -#define RTC_CNTL_XPD_DCDC_SLP_S 26 -/** RTC_CNTL_XPD_DCDC_MONITOR : R/W; bitpos: [27]; default: 1; - * Need add description - */ -#define RTC_CNTL_XPD_DCDC_MONITOR (BIT(27)) -#define RTC_CNTL_XPD_DCDC_MONITOR_M (RTC_CNTL_XPD_DCDC_MONITOR_V << RTC_CNTL_XPD_DCDC_MONITOR_S) -#define RTC_CNTL_XPD_DCDC_MONITOR_V 0x00000001U -#define RTC_CNTL_XPD_DCDC_MONITOR_S 27 -/** RTC_CNTL_XPD_DCDC_IDLE : R/W; bitpos: [28]; default: 1; - * Need add description - */ -#define RTC_CNTL_XPD_DCDC_IDLE (BIT(28)) -#define RTC_CNTL_XPD_DCDC_IDLE_M (RTC_CNTL_XPD_DCDC_IDLE_V << RTC_CNTL_XPD_DCDC_IDLE_S) -#define RTC_CNTL_XPD_DCDC_IDLE_V 0x00000001U -#define RTC_CNTL_XPD_DCDC_IDLE_S 28 - -/** RTC_CNTL_REGULATOR_REG register - * register description - */ -#define RTC_CNTL_REGULATOR_REG (DR_REG_RTCCNTL_BASE + 0x80) -/** RTC_CNTL_DBIAS_SWITCH_SLP : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define RTC_CNTL_DBIAS_SWITCH_SLP (BIT(0)) -#define RTC_CNTL_DBIAS_SWITCH_SLP_M (RTC_CNTL_DBIAS_SWITCH_SLP_V << RTC_CNTL_DBIAS_SWITCH_SLP_S) -#define RTC_CNTL_DBIAS_SWITCH_SLP_V 0x00000001U -#define RTC_CNTL_DBIAS_SWITCH_SLP_S 0 -/** RTC_CNTL_DBIAS_SWITCH_MONITOR : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define RTC_CNTL_DBIAS_SWITCH_MONITOR (BIT(1)) -#define RTC_CNTL_DBIAS_SWITCH_MONITOR_M (RTC_CNTL_DBIAS_SWITCH_MONITOR_V << RTC_CNTL_DBIAS_SWITCH_MONITOR_S) -#define RTC_CNTL_DBIAS_SWITCH_MONITOR_V 0x00000001U -#define RTC_CNTL_DBIAS_SWITCH_MONITOR_S 1 -/** RTC_CNTL_DBIAS_SWITCH_IDLE : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define RTC_CNTL_DBIAS_SWITCH_IDLE (BIT(2)) -#define RTC_CNTL_DBIAS_SWITCH_IDLE_M (RTC_CNTL_DBIAS_SWITCH_IDLE_V << RTC_CNTL_DBIAS_SWITCH_IDLE_S) -#define RTC_CNTL_DBIAS_SWITCH_IDLE_V 0x00000001U -#define RTC_CNTL_DBIAS_SWITCH_IDLE_S 2 -/** RTC_CNTL_DIG_REG_CAL_EN : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define RTC_CNTL_DIG_REG_CAL_EN (BIT(3)) -#define RTC_CNTL_DIG_REG_CAL_EN_M (RTC_CNTL_DIG_REG_CAL_EN_V << RTC_CNTL_DIG_REG_CAL_EN_S) -#define RTC_CNTL_DIG_REG_CAL_EN_V 0x00000001U -#define RTC_CNTL_DIG_REG_CAL_EN_S 3 -/** RTC_CNTL_SCK_DCAP : R/W; bitpos: [11:4]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCK_DCAP 0x000000FFU -#define RTC_CNTL_SCK_DCAP_M (RTC_CNTL_SCK_DCAP_V << RTC_CNTL_SCK_DCAP_S) -#define RTC_CNTL_SCK_DCAP_V 0x000000FFU -#define RTC_CNTL_SCK_DCAP_S 4 -/** RTC_CNTL_VDD_DRV_B_ACTIVE : R/W; bitpos: [20:15]; default: 0; - * SCK_DCAP - */ -#define RTC_CNTL_VDD_DRV_B_ACTIVE 0x0000003FU -#define RTC_CNTL_VDD_DRV_B_ACTIVE_M (RTC_CNTL_VDD_DRV_B_ACTIVE_V << RTC_CNTL_VDD_DRV_B_ACTIVE_S) -#define RTC_CNTL_VDD_DRV_B_ACTIVE_V 0x0000003FU -#define RTC_CNTL_VDD_DRV_B_ACTIVE_S 15 -/** RTC_CNTL_VDD_DRV_B_SLP : R/W; bitpos: [26:21]; default: 0; - * Need add description - */ -#define RTC_CNTL_VDD_DRV_B_SLP 0x0000003FU -#define RTC_CNTL_VDD_DRV_B_SLP_M (RTC_CNTL_VDD_DRV_B_SLP_V << RTC_CNTL_VDD_DRV_B_SLP_S) -#define RTC_CNTL_VDD_DRV_B_SLP_V 0x0000003FU -#define RTC_CNTL_VDD_DRV_B_SLP_S 21 -/** RTC_CNTL_VDD_DRV_B_SLP_EN : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define RTC_CNTL_VDD_DRV_B_SLP_EN (BIT(27)) -#define RTC_CNTL_VDD_DRV_B_SLP_EN_M (RTC_CNTL_VDD_DRV_B_SLP_EN_V << RTC_CNTL_VDD_DRV_B_SLP_EN_S) -#define RTC_CNTL_VDD_DRV_B_SLP_EN_V 0x00000001U -#define RTC_CNTL_VDD_DRV_B_SLP_EN_S 27 -/** RTC_CNTL_DBOOST_FORCE_PD : R/W; bitpos: [28]; default: 0; - * RTC_DBOOST force power down - */ -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_M (RTC_CNTL_DBOOST_FORCE_PD_V << RTC_CNTL_DBOOST_FORCE_PD_S) -#define RTC_CNTL_DBOOST_FORCE_PD_V 0x00000001U -#define RTC_CNTL_DBOOST_FORCE_PD_S 28 -/** RTC_CNTL_DBOOST_FORCE_PU : R/W; bitpos: [29]; default: 1; - * RTC_DBOOST force power up - */ -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_M (RTC_CNTL_DBOOST_FORCE_PU_V << RTC_CNTL_DBOOST_FORCE_PU_S) -#define RTC_CNTL_DBOOST_FORCE_PU_V 0x00000001U -#define RTC_CNTL_DBOOST_FORCE_PU_S 29 -/** RTC_CNTL_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0; - * RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v - * or lower ) - */ -#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_REGULATOR_FORCE_PD_M (RTC_CNTL_REGULATOR_FORCE_PD_V << RTC_CNTL_REGULATOR_FORCE_PD_S) -#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x00000001U -#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 -/** RTC_CNTL_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1; - * Need add description - */ -#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_REGULATOR_FORCE_PU_M (RTC_CNTL_REGULATOR_FORCE_PU_V << RTC_CNTL_REGULATOR_FORCE_PU_S) -#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x00000001U -#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 - -/** RTC_CNTL_REGULATOR0_DBIAS_REG register - * register description - */ -#define RTC_CNTL_REGULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x84) -/** RTC_CNTL_PVT_RTC_DBIAS : RO; bitpos: [19:15]; default: 20; - * get pvt dbias value - */ -#define RTC_CNTL_PVT_RTC_DBIAS 0x0000001FU -#define RTC_CNTL_PVT_RTC_DBIAS_M (RTC_CNTL_PVT_RTC_DBIAS_V << RTC_CNTL_PVT_RTC_DBIAS_S) -#define RTC_CNTL_PVT_RTC_DBIAS_V 0x0000001FU -#define RTC_CNTL_PVT_RTC_DBIAS_S 15 -/** RTC_CNTL_REGULATOR0_DBIAS_SLP : R/W; bitpos: [24:20]; default: 20; - * the rtc regulator0 dbias when chip in sleep state - */ -#define RTC_CNTL_REGULATOR0_DBIAS_SLP 0x0000001FU -#define RTC_CNTL_REGULATOR0_DBIAS_SLP_M (RTC_CNTL_REGULATOR0_DBIAS_SLP_V << RTC_CNTL_REGULATOR0_DBIAS_SLP_S) -#define RTC_CNTL_REGULATOR0_DBIAS_SLP_V 0x0000001FU -#define RTC_CNTL_REGULATOR0_DBIAS_SLP_S 20 -/** RTC_CNTL_REGULATOR0_DBIAS_ACTIVE : R/W; bitpos: [29:25]; default: 20; - * the rtc regulator0 dbias when chip in active state - */ -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE 0x0000001FU -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_M (RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V << RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S) -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_V 0x0000001FU -#define RTC_CNTL_REGULATOR0_DBIAS_ACTIVE_S 25 -/** RTC_CNTL_REGULATOR0_DBIAS_SEL : R/W; bitpos: [31]; default: 1; - * 1: select sw dbias_active 0: select pvt value - */ -#define RTC_CNTL_REGULATOR0_DBIAS_SEL (BIT(31)) -#define RTC_CNTL_REGULATOR0_DBIAS_SEL_M (RTC_CNTL_REGULATOR0_DBIAS_SEL_V << RTC_CNTL_REGULATOR0_DBIAS_SEL_S) -#define RTC_CNTL_REGULATOR0_DBIAS_SEL_V 0x00000001U -#define RTC_CNTL_REGULATOR0_DBIAS_SEL_S 31 - -/** RTC_CNTL_REGULATOR1_DBIAS_REG register - * register description - */ -#define RTC_CNTL_REGULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x88) -/** RTC_CNTL_REGULATOR1_DBIAS_SLP : R/W; bitpos: [23:20]; default: 8; - * the rtc regulator1 dbias when chip in sleep state - */ -#define RTC_CNTL_REGULATOR1_DBIAS_SLP 0x0000000FU -#define RTC_CNTL_REGULATOR1_DBIAS_SLP_M (RTC_CNTL_REGULATOR1_DBIAS_SLP_V << RTC_CNTL_REGULATOR1_DBIAS_SLP_S) -#define RTC_CNTL_REGULATOR1_DBIAS_SLP_V 0x0000000FU -#define RTC_CNTL_REGULATOR1_DBIAS_SLP_S 20 -/** RTC_CNTL_REGULATOR1_DBIAS_ACTIVE : R/W; bitpos: [28:25]; default: 8; - * the rtc regulator1 dbias when chip in active state - */ -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE 0x0000000FU -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_M (RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V << RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S) -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_V 0x0000000FU -#define RTC_CNTL_REGULATOR1_DBIAS_ACTIVE_S 25 - -/** RTC_CNTL_DIG_REGULATOR_REG register - * register description - */ -#define RTC_CNTL_DIG_REGULATOR_REG (DR_REG_RTCCNTL_BASE + 0x8c) -/** RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD (BIT(1)) -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_M (RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_V << RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_S) -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_V 0x00000001U -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PD_S 1 -/** RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU : R/W; bitpos: [2]; default: 1; - * Need add description - */ -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU (BIT(2)) -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_M (RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_V << RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_S) -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_V 0x00000001U -#define RTC_CNTL_MEM_REGULATOR_SLP_FORCE_PU_S 2 -/** RTC_CNTL_DG_VDD_DRV_B_SLP : R/W; bitpos: [26:3]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x00FFFFFFU -#define RTC_CNTL_DG_VDD_DRV_B_SLP_M (RTC_CNTL_DG_VDD_DRV_B_SLP_V << RTC_CNTL_DG_VDD_DRV_B_SLP_S) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0x00FFFFFFU -#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 3 -/** RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(27)) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V << RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x00000001U -#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 27 -/** RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD (BIT(28)) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_M (RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_V << RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_S) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_V 0x00000001U -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD_S 28 -/** RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU : R/W; bitpos: [29]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU (BIT(29)) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_M (RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_V << RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_S) -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_V 0x00000001U -#define RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU_S 29 -/** RTC_CNTL_DG_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_DG_REGULATOR_FORCE_PD_M (RTC_CNTL_DG_REGULATOR_FORCE_PD_V << RTC_CNTL_DG_REGULATOR_FORCE_PD_S) -#define RTC_CNTL_DG_REGULATOR_FORCE_PD_V 0x00000001U -#define RTC_CNTL_DG_REGULATOR_FORCE_PD_S 30 -/** RTC_CNTL_DG_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_DG_REGULATOR_FORCE_PU_M (RTC_CNTL_DG_REGULATOR_FORCE_PU_V << RTC_CNTL_DG_REGULATOR_FORCE_PU_S) -#define RTC_CNTL_DG_REGULATOR_FORCE_PU_V 0x00000001U -#define RTC_CNTL_DG_REGULATOR_FORCE_PU_S 31 - -/** RTC_CNTL_DIG_REGULATOR_DRVB_REG register - * register description - */ -#define RTC_CNTL_DIG_REGULATOR_DRVB_REG (DR_REG_RTCCNTL_BASE + 0x90) -/** RTC_CNTL_DG_VDD_DRV_B_ACTIVE : R/W; bitpos: [23:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE 0x00FFFFFFU -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_M (RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V << RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S) -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_V 0x00FFFFFFU -#define RTC_CNTL_DG_VDD_DRV_B_ACTIVE_S 0 - -/** RTC_CNTL_DIG_REGULATOR0_DBIAS_REG register - * register description - */ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x94) -/** RTC_CNTL_PVT_DIG_DBIAS : RO; bitpos: [19:15]; default: 20; - * get pvt dbias value - */ -#define RTC_CNTL_PVT_DIG_DBIAS 0x0000001FU -#define RTC_CNTL_PVT_DIG_DBIAS_M (RTC_CNTL_PVT_DIG_DBIAS_V << RTC_CNTL_PVT_DIG_DBIAS_S) -#define RTC_CNTL_PVT_DIG_DBIAS_V 0x0000001FU -#define RTC_CNTL_PVT_DIG_DBIAS_S 15 -/** RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP : R/W; bitpos: [24:20]; default: 20; - * the dig regulator0 dbias when chip in sleep state - */ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP 0x0000001FU -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_M (RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V << RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_V 0x0000001FU -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP_S 20 -/** RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE : R/W; bitpos: [29:25]; default: 20; - * the dig regulator0 dbias when chip in active state - */ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE 0x0000001FU -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_M (RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V << RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_V 0x0000001FU -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE_S 25 -/** RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT : WO; bitpos: [30]; default: 0; - * initial pvt dbias value - */ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT (BIT(30)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_M (RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_V << RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_S) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_V 0x00000001U -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_INIT_S 30 -/** RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [31]; default: 1; - * 1: select sw dbias_active 0: select pvt value - */ -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL (BIT(31)) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_M (RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_V << RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_S) -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U -#define RTC_CNTL_DIG_REGULATOR0_DBIAS_SEL_S 31 - -/** RTC_CNTL_DIG_REGULATOR1_DBIAS_REG register - * register description - */ -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG (DR_REG_RTCCNTL_BASE + 0x98) -/** RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP : R/W; bitpos: [15:12]; default: 8; - * Need add description - */ -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP 0x0000000FU -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_M (RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_V << RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_S) -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_V 0x0000000FU -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_SLP_S 12 -/** RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE : R/W; bitpos: [19:16]; default: 8; - * Need add description - */ -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE 0x0000000FU -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_M (RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_V << RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_S) -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_V 0x0000000FU -#define RTC_CNTL_MEM_REGULATOR1_DBIAS_ACTIVE_S 16 -/** RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP : R/W; bitpos: [23:20]; default: 8; - * the dig regulator1 dbias when chip in sleep state - */ -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP 0x0000000FU -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_M (RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V << RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S) -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_V 0x0000000FU -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP_S 20 -/** RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE : R/W; bitpos: [28:25]; default: 8; - * the dig regulator1 dbias when chip in active state - */ -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE 0x0000000FU -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_M (RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V << RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S) -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_V 0x0000000FU -#define RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE_S 25 - -/** RTC_CNTL_PWC_REG register - * register description - */ -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x9c) -/** RTC_CNTL_PAD_FORCE_HOLD : R/W; bitpos: [21]; default: 0; - * rtc pad force hold - */ -#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) -#define RTC_CNTL_PAD_FORCE_HOLD_M (RTC_CNTL_PAD_FORCE_HOLD_V << RTC_CNTL_PAD_FORCE_HOLD_S) -#define RTC_CNTL_PAD_FORCE_HOLD_V 0x00000001U -#define RTC_CNTL_PAD_FORCE_HOLD_S 21 - -/** RTC_CNTL_DIG_PWC_REG register - * register description - */ -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0xa0) -/** RTC_CNTL_VDD_SPI_PWR_DRV : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003U -#define RTC_CNTL_VDD_SPI_PWR_DRV_M (RTC_CNTL_VDD_SPI_PWR_DRV_V << RTC_CNTL_VDD_SPI_PWR_DRV_S) -#define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x00000003U -#define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 -/** RTC_CNTL_VDD_SPI_PWR_FORCE : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) -#define RTC_CNTL_VDD_SPI_PWR_FORCE_M (RTC_CNTL_VDD_SPI_PWR_FORCE_V << RTC_CNTL_VDD_SPI_PWR_FORCE_S) -#define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x00000001U -#define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 -/** RTC_CNTL_LSLP_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; - * memories in digital core force PD in sleep - */ -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (RTC_CNTL_LSLP_MEM_FORCE_PD_V << RTC_CNTL_LSLP_MEM_FORCE_PD_S) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x00000001U -#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 -/** RTC_CNTL_LSLP_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; - * memories in digital core force no PD in sleep - */ -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (RTC_CNTL_LSLP_MEM_FORCE_PU_V << RTC_CNTL_LSLP_MEM_FORCE_PU_S) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x00000001U -#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 -/** RTC_CNTL_DG_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_MEM_FORCE_PD (BIT(7)) -#define RTC_CNTL_DG_MEM_FORCE_PD_M (RTC_CNTL_DG_MEM_FORCE_PD_V << RTC_CNTL_DG_MEM_FORCE_PD_S) -#define RTC_CNTL_DG_MEM_FORCE_PD_V 0x00000001U -#define RTC_CNTL_DG_MEM_FORCE_PD_S 7 -/** RTC_CNTL_DG_MEM_FORCE_PU : R/W; bitpos: [8]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_MEM_FORCE_PU (BIT(8)) -#define RTC_CNTL_DG_MEM_FORCE_PU_M (RTC_CNTL_DG_MEM_FORCE_PU_V << RTC_CNTL_DG_MEM_FORCE_PU_S) -#define RTC_CNTL_DG_MEM_FORCE_PU_V 0x00000001U -#define RTC_CNTL_DG_MEM_FORCE_PU_S 8 -/** RTC_CNTL_DG_WRAP_FORCE_PD : R/W; bitpos: [9]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(9)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (RTC_CNTL_DG_WRAP_FORCE_PD_V << RTC_CNTL_DG_WRAP_FORCE_PD_S) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x00000001U -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 9 -/** RTC_CNTL_DG_WRAP_FORCE_PU : R/W; bitpos: [10]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(10)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (RTC_CNTL_DG_WRAP_FORCE_PU_V << RTC_CNTL_DG_WRAP_FORCE_PU_S) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x00000001U -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 10 -/** RTC_CNTL_BT_FORCE_PD : R/W; bitpos: [11]; default: 0; - * Need add description - */ -#define RTC_CNTL_BT_FORCE_PD (BIT(11)) -#define RTC_CNTL_BT_FORCE_PD_M (RTC_CNTL_BT_FORCE_PD_V << RTC_CNTL_BT_FORCE_PD_S) -#define RTC_CNTL_BT_FORCE_PD_V 0x00000001U -#define RTC_CNTL_BT_FORCE_PD_S 11 -/** RTC_CNTL_BT_FORCE_PU : R/W; bitpos: [12]; default: 1; - * Need add description - */ -#define RTC_CNTL_BT_FORCE_PU (BIT(12)) -#define RTC_CNTL_BT_FORCE_PU_M (RTC_CNTL_BT_FORCE_PU_V << RTC_CNTL_BT_FORCE_PU_S) -#define RTC_CNTL_BT_FORCE_PU_V 0x00000001U -#define RTC_CNTL_BT_FORCE_PU_S 12 -/** RTC_CNTL_DG_PERI_FORCE_PD : R/W; bitpos: [13]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) -#define RTC_CNTL_DG_PERI_FORCE_PD_M (RTC_CNTL_DG_PERI_FORCE_PD_V << RTC_CNTL_DG_PERI_FORCE_PD_S) -#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x00000001U -#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 -/** RTC_CNTL_DG_PERI_FORCE_PU : R/W; bitpos: [14]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) -#define RTC_CNTL_DG_PERI_FORCE_PU_M (RTC_CNTL_DG_PERI_FORCE_PU_V << RTC_CNTL_DG_PERI_FORCE_PU_S) -#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x00000001U -#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 -/** RTC_CNTL_FASTMEM_FORCE_LPD : R/W; bitpos: [15]; default: 0; - * Need add description - */ -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_M (RTC_CNTL_FASTMEM_FORCE_LPD_V << RTC_CNTL_FASTMEM_FORCE_LPD_S) -#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x00000001U -#define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 -/** RTC_CNTL_FASTMEM_FORCE_LPU : R/W; bitpos: [16]; default: 1; - * Need add description - */ -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_M (RTC_CNTL_FASTMEM_FORCE_LPU_V << RTC_CNTL_FASTMEM_FORCE_LPU_S) -#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x00000001U -#define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 -/** RTC_CNTL_WIFI_FORCE_PD : R/W; bitpos: [17]; default: 0; - * wifi force power down - */ -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_M (RTC_CNTL_WIFI_FORCE_PD_V << RTC_CNTL_WIFI_FORCE_PD_S) -#define RTC_CNTL_WIFI_FORCE_PD_V 0x00000001U -#define RTC_CNTL_WIFI_FORCE_PD_S 17 -/** RTC_CNTL_WIFI_FORCE_PU : R/W; bitpos: [18]; default: 1; - * wifi force power up - */ -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_M (RTC_CNTL_WIFI_FORCE_PU_V << RTC_CNTL_WIFI_FORCE_PU_S) -#define RTC_CNTL_WIFI_FORCE_PU_V 0x00000001U -#define RTC_CNTL_WIFI_FORCE_PU_S 18 -/** RTC_CNTL_CPU_TOP_FORCE_PD : R/W; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) -#define RTC_CNTL_CPU_TOP_FORCE_PD_M (RTC_CNTL_CPU_TOP_FORCE_PD_V << RTC_CNTL_CPU_TOP_FORCE_PD_S) -#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x00000001U -#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 -/** RTC_CNTL_CPU_TOP_FORCE_PU : R/W; bitpos: [22]; default: 1; - * Need add description - */ -#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) -#define RTC_CNTL_CPU_TOP_FORCE_PU_M (RTC_CNTL_CPU_TOP_FORCE_PU_V << RTC_CNTL_CPU_TOP_FORCE_PU_S) -#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x00000001U -#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 -/** RTC_CNTL_DG_WRAP_RET_PD_EN : R/W; bitpos: [26]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_RET_PD_EN (BIT(26)) -#define RTC_CNTL_DG_WRAP_RET_PD_EN_M (RTC_CNTL_DG_WRAP_RET_PD_EN_V << RTC_CNTL_DG_WRAP_RET_PD_EN_S) -#define RTC_CNTL_DG_WRAP_RET_PD_EN_V 0x00000001U -#define RTC_CNTL_DG_WRAP_RET_PD_EN_S 26 -/** RTC_CNTL_BT_PD_EN : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define RTC_CNTL_BT_PD_EN (BIT(27)) -#define RTC_CNTL_BT_PD_EN_M (RTC_CNTL_BT_PD_EN_V << RTC_CNTL_BT_PD_EN_S) -#define RTC_CNTL_BT_PD_EN_V 0x00000001U -#define RTC_CNTL_BT_PD_EN_S 27 -/** RTC_CNTL_DG_PERI_PD_EN : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) -#define RTC_CNTL_DG_PERI_PD_EN_M (RTC_CNTL_DG_PERI_PD_EN_V << RTC_CNTL_DG_PERI_PD_EN_S) -#define RTC_CNTL_DG_PERI_PD_EN_V 0x00000001U -#define RTC_CNTL_DG_PERI_PD_EN_S 28 -/** RTC_CNTL_CPU_TOP_PD_EN : R/W; bitpos: [29]; default: 0; - * Need add description - */ -#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) -#define RTC_CNTL_CPU_TOP_PD_EN_M (RTC_CNTL_CPU_TOP_PD_EN_V << RTC_CNTL_CPU_TOP_PD_EN_S) -#define RTC_CNTL_CPU_TOP_PD_EN_V 0x00000001U -#define RTC_CNTL_CPU_TOP_PD_EN_S 29 -/** RTC_CNTL_WIFI_PD_EN : R/W; bitpos: [30]; default: 0; - * enable power down wifi in sleep - */ -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_M (RTC_CNTL_WIFI_PD_EN_V << RTC_CNTL_WIFI_PD_EN_S) -#define RTC_CNTL_WIFI_PD_EN_V 0x00000001U -#define RTC_CNTL_WIFI_PD_EN_S 30 -/** RTC_CNTL_DG_WRAP_PD_EN : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_M (RTC_CNTL_DG_WRAP_PD_EN_V << RTC_CNTL_DG_WRAP_PD_EN_S) -#define RTC_CNTL_DG_WRAP_PD_EN_V 0x00000001U -#define RTC_CNTL_DG_WRAP_PD_EN_S 31 - -/** RTC_CNTL_DIG_POWER_SLAVE0_PD_REG register - * register description - */ -#define RTC_CNTL_DIG_POWER_SLAVE0_PD_REG (DR_REG_RTCCNTL_BASE + 0xa4) -/** RTC_CNTL_PD_DG_PERI_SWITCH_MASK : R/W; bitpos: [6:2]; default: 0; - * Need add description - */ -#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK_M (RTC_CNTL_PD_DG_PERI_SWITCH_MASK_V << RTC_CNTL_PD_DG_PERI_SWITCH_MASK_S) -#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_PD_DG_PERI_SWITCH_MASK_S 2 -/** RTC_CNTL_PD_DG_WRAP_SWITCH_MASK : R/W; bitpos: [11:7]; default: 0; - * Need add description - */ -#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_M (RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_V << RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_S) -#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_PD_DG_WRAP_SWITCH_MASK_S 7 -/** RTC_CNTL_PD_MEM_SWITCH_MASK : R/W; bitpos: [31:12]; default: 0; - * Need add description - */ -#define RTC_CNTL_PD_MEM_SWITCH_MASK 0x000FFFFFU -#define RTC_CNTL_PD_MEM_SWITCH_MASK_M (RTC_CNTL_PD_MEM_SWITCH_MASK_V << RTC_CNTL_PD_MEM_SWITCH_MASK_S) -#define RTC_CNTL_PD_MEM_SWITCH_MASK_V 0x000FFFFFU -#define RTC_CNTL_PD_MEM_SWITCH_MASK_S 12 - -/** RTC_CNTL_DIG_POWER_SLAVE1_PD_REG register - * register description - */ -#define RTC_CNTL_DIG_POWER_SLAVE1_PD_REG (DR_REG_RTCCNTL_BASE + 0xa8) -/** RTC_CNTL_PD_WIFI_SWITCH_MASK : R/W; bitpos: [26:22]; default: 0; - * Need add description - */ -#define RTC_CNTL_PD_WIFI_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_PD_WIFI_SWITCH_MASK_M (RTC_CNTL_PD_WIFI_SWITCH_MASK_V << RTC_CNTL_PD_WIFI_SWITCH_MASK_S) -#define RTC_CNTL_PD_WIFI_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_PD_WIFI_SWITCH_MASK_S 22 -/** RTC_CNTL_PD_CPU_SWITCH_MASK : R/W; bitpos: [31:27]; default: 0; - * Need add description - */ -#define RTC_CNTL_PD_CPU_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_PD_CPU_SWITCH_MASK_M (RTC_CNTL_PD_CPU_SWITCH_MASK_V << RTC_CNTL_PD_CPU_SWITCH_MASK_S) -#define RTC_CNTL_PD_CPU_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_PD_CPU_SWITCH_MASK_S 27 - -/** RTC_CNTL_DIG_POWER_SLAVE0_FPU_REG register - * register description - */ -#define RTC_CNTL_DIG_POWER_SLAVE0_FPU_REG (DR_REG_RTCCNTL_BASE + 0xac) -/** RTC_CNTL_XPD_DG_PERI_SWITCH_MASK : R/W; bitpos: [6:2]; default: 31; - * Need add description - */ -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_M (RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V << RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S) -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_XPD_DG_PERI_SWITCH_MASK_S 2 -/** RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK : R/W; bitpos: [11:7]; default: 31; - * Need add description - */ -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_M (RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V << RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S) -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_XPD_DG_WRAP_SWITCH_MASK_S 7 -/** RTC_CNTL_XPD_MEM_SWITCH_MASK : R/W; bitpos: [31:12]; default: 1048575; - * Need add description - */ -#define RTC_CNTL_XPD_MEM_SWITCH_MASK 0x000FFFFFU -#define RTC_CNTL_XPD_MEM_SWITCH_MASK_M (RTC_CNTL_XPD_MEM_SWITCH_MASK_V << RTC_CNTL_XPD_MEM_SWITCH_MASK_S) -#define RTC_CNTL_XPD_MEM_SWITCH_MASK_V 0x000FFFFFU -#define RTC_CNTL_XPD_MEM_SWITCH_MASK_S 12 - -/** RTC_CNTL_DIG_POWER_SLAVE1_FPU_REG register - * register description - */ -#define RTC_CNTL_DIG_POWER_SLAVE1_FPU_REG (DR_REG_RTCCNTL_BASE + 0xb0) -/** RTC_CNTL_XPD_WIFI_SWITCH_MASK : R/W; bitpos: [26:22]; default: 31; - * Need add description - */ -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_M (RTC_CNTL_XPD_WIFI_SWITCH_MASK_V << RTC_CNTL_XPD_WIFI_SWITCH_MASK_S) -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_XPD_WIFI_SWITCH_MASK_S 22 -/** RTC_CNTL_XPD_CPU_SWITCH_MASK : R/W; bitpos: [31:27]; default: 31; - * Need add description - */ -#define RTC_CNTL_XPD_CPU_SWITCH_MASK 0x0000001FU -#define RTC_CNTL_XPD_CPU_SWITCH_MASK_M (RTC_CNTL_XPD_CPU_SWITCH_MASK_V << RTC_CNTL_XPD_CPU_SWITCH_MASK_S) -#define RTC_CNTL_XPD_CPU_SWITCH_MASK_V 0x0000001FU -#define RTC_CNTL_XPD_CPU_SWITCH_MASK_S 27 - -/** RTC_CNTL_DIG_ISO_REG register - * register description - */ -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0xb4) -/** RTC_CNTL_DG_MEM_FORCE_NOISO : R/W; bitpos: [5]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_MEM_FORCE_NOISO (BIT(5)) -#define RTC_CNTL_DG_MEM_FORCE_NOISO_M (RTC_CNTL_DG_MEM_FORCE_NOISO_V << RTC_CNTL_DG_MEM_FORCE_NOISO_S) -#define RTC_CNTL_DG_MEM_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_DG_MEM_FORCE_NOISO_S 5 -/** RTC_CNTL_DG_MEM_FORCE_ISO : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_MEM_FORCE_ISO (BIT(6)) -#define RTC_CNTL_DG_MEM_FORCE_ISO_M (RTC_CNTL_DG_MEM_FORCE_ISO_V << RTC_CNTL_DG_MEM_FORCE_ISO_S) -#define RTC_CNTL_DG_MEM_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_DG_MEM_FORCE_ISO_S 6 -/** RTC_CNTL_DIG_ISO_FORCE_OFF : R/W; bitpos: [7]; default: 1; - * Need add description - */ -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (RTC_CNTL_DIG_ISO_FORCE_OFF_V << RTC_CNTL_DIG_ISO_FORCE_OFF_S) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x00000001U -#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 -/** RTC_CNTL_DIG_ISO_FORCE_ON : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_M (RTC_CNTL_DIG_ISO_FORCE_ON_V << RTC_CNTL_DIG_ISO_FORCE_ON_S) -#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x00000001U -#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 -/** RTC_CNTL_DG_PAD_AUTOHOLD : RO; bitpos: [9]; default: 0; - * read only register to indicate digital pad auto-hold status - */ -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_M (RTC_CNTL_DG_PAD_AUTOHOLD_V << RTC_CNTL_DG_PAD_AUTOHOLD_S) -#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x00000001U -#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 -/** RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO; bitpos: [10]; default: 0; - * wtite only register to clear digital pad auto-hold - */ -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V << RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x00000001U -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 -/** RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W; bitpos: [11]; default: 0; - * digital pad enable auto-hold - */ -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (RTC_CNTL_DG_PAD_AUTOHOLD_EN_V << RTC_CNTL_DG_PAD_AUTOHOLD_EN_S) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x00000001U -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 -/** RTC_CNTL_DG_PAD_FORCE_NOISO : R/W; bitpos: [12]; default: 1; - * digital pad force no ISO - */ -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (RTC_CNTL_DG_PAD_FORCE_NOISO_V << RTC_CNTL_DG_PAD_FORCE_NOISO_S) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 -/** RTC_CNTL_DG_PAD_FORCE_ISO : R/W; bitpos: [13]; default: 0; - * digital pad force ISO - */ -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_M (RTC_CNTL_DG_PAD_FORCE_ISO_V << RTC_CNTL_DG_PAD_FORCE_ISO_S) -#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 -/** RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W; bitpos: [14]; default: 1; - * digital pad force un-hold - */ -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (RTC_CNTL_DG_PAD_FORCE_UNHOLD_V << RTC_CNTL_DG_PAD_FORCE_UNHOLD_S) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x00000001U -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 -/** RTC_CNTL_DG_PAD_FORCE_HOLD : R/W; bitpos: [15]; default: 0; - * digital pad force hold - */ -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (RTC_CNTL_DG_PAD_FORCE_HOLD_V << RTC_CNTL_DG_PAD_FORCE_HOLD_S) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x00000001U -#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 -/** RTC_CNTL_BT_FORCE_ISO : R/W; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) -#define RTC_CNTL_BT_FORCE_ISO_M (RTC_CNTL_BT_FORCE_ISO_V << RTC_CNTL_BT_FORCE_ISO_S) -#define RTC_CNTL_BT_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_BT_FORCE_ISO_S 22 -/** RTC_CNTL_BT_FORCE_NOISO : R/W; bitpos: [23]; default: 1; - * Need add description - */ -#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_BT_FORCE_NOISO_M (RTC_CNTL_BT_FORCE_NOISO_V << RTC_CNTL_BT_FORCE_NOISO_S) -#define RTC_CNTL_BT_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_BT_FORCE_NOISO_S 23 -/** RTC_CNTL_DG_PERI_FORCE_ISO : R/W; bitpos: [24]; default: 0; - * Need add description - */ -#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) -#define RTC_CNTL_DG_PERI_FORCE_ISO_M (RTC_CNTL_DG_PERI_FORCE_ISO_V << RTC_CNTL_DG_PERI_FORCE_ISO_S) -#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 -/** RTC_CNTL_DG_PERI_FORCE_NOISO : R/W; bitpos: [25]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (RTC_CNTL_DG_PERI_FORCE_NOISO_V << RTC_CNTL_DG_PERI_FORCE_NOISO_S) -#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 -/** RTC_CNTL_CPU_TOP_FORCE_ISO : R/W; bitpos: [26]; default: 0; - * cpu force ISO - */ -#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) -#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (RTC_CNTL_CPU_TOP_FORCE_ISO_V << RTC_CNTL_CPU_TOP_FORCE_ISO_S) -#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 -/** RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W; bitpos: [27]; default: 1; - * cpu force no ISO - */ -#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (RTC_CNTL_CPU_TOP_FORCE_NOISO_V << RTC_CNTL_CPU_TOP_FORCE_NOISO_S) -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 -/** RTC_CNTL_WIFI_FORCE_ISO : R/W; bitpos: [28]; default: 0; - * wifi force ISO - */ -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_M (RTC_CNTL_WIFI_FORCE_ISO_V << RTC_CNTL_WIFI_FORCE_ISO_S) -#define RTC_CNTL_WIFI_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_WIFI_FORCE_ISO_S 28 -/** RTC_CNTL_WIFI_FORCE_NOISO : R/W; bitpos: [29]; default: 1; - * wifi force no ISO - */ -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_M (RTC_CNTL_WIFI_FORCE_NOISO_V << RTC_CNTL_WIFI_FORCE_NOISO_S) -#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 -/** RTC_CNTL_DG_WRAP_FORCE_ISO : R/W; bitpos: [30]; default: 0; - * digital core force ISO - */ -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (RTC_CNTL_DG_WRAP_FORCE_ISO_V << RTC_CNTL_DG_WRAP_FORCE_ISO_S) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x00000001U -#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 -/** RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W; bitpos: [31]; default: 1; - * Need add description - */ -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (RTC_CNTL_DG_WRAP_FORCE_NOISO_V << RTC_CNTL_DG_WRAP_FORCE_NOISO_S) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x00000001U -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 - -/** RTC_CNTL_WDTCONFIG0_REG register - * register description - */ -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0xb8) -/** RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; - * chip reset siginal pulse width - */ -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FFU -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M (RTC_CNTL_WDT_CHIP_RESET_WIDTH_V << RTC_CNTL_WDT_CHIP_RESET_WIDTH_S) -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0x000000FFU -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 -/** RTC_CNTL_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; - * wdt reset whole chip enable - */ -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_M (RTC_CNTL_WDT_CHIP_RESET_EN_V << RTC_CNTL_WDT_CHIP_RESET_EN_S) -#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x00000001U -#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 -/** RTC_CNTL_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; - * pause WDT in sleep - */ -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (RTC_CNTL_WDT_PAUSE_IN_SLP_V << RTC_CNTL_WDT_PAUSE_IN_SLP_S) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x00000001U -#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 -/** RTC_CNTL_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; - * enable WDT reset APP CPU - */ -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (RTC_CNTL_WDT_APPCPU_RESET_EN_V << RTC_CNTL_WDT_APPCPU_RESET_EN_S) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x00000001U -#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 -/** RTC_CNTL_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; - * enable WDT reset PRO CPU - */ -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (RTC_CNTL_WDT_PROCPU_RESET_EN_V << RTC_CNTL_WDT_PROCPU_RESET_EN_S) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x00000001U -#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 -/** RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; - * enable WDT in flash boot - */ -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V << RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x00000001U -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 -/** RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; - * system reset counter length - */ -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007U -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M (RTC_CNTL_WDT_SYS_RESET_LENGTH_V << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x00000007U -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 -/** RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; - * CPU reset counter length - */ -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007U -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M (RTC_CNTL_WDT_CPU_RESET_LENGTH_V << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x00000007U -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 -/* RTC_CNTL_WDT_STGX : */ -/*description: stage action selection values */ -#define RTC_WDT_STG_SEL_OFF 0 -#define RTC_WDT_STG_SEL_INT 1 -#define RTC_WDT_STG_SEL_RESET_CPU 2 -#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 -#define RTC_WDT_STG_SEL_RESET_RTC 4 -/** RTC_CNTL_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ -#define RTC_CNTL_WDT_STG3 0x00000007U -#define RTC_CNTL_WDT_STG3_M (RTC_CNTL_WDT_STG3_V << RTC_CNTL_WDT_STG3_S) -#define RTC_CNTL_WDT_STG3_V 0x00000007U -#define RTC_CNTL_WDT_STG3_S 19 -/** RTC_CNTL_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ -#define RTC_CNTL_WDT_STG2 0x00000007U -#define RTC_CNTL_WDT_STG2_M (RTC_CNTL_WDT_STG2_V << RTC_CNTL_WDT_STG2_S) -#define RTC_CNTL_WDT_STG2_V 0x00000007U -#define RTC_CNTL_WDT_STG2_S 22 -/** RTC_CNTL_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ -#define RTC_CNTL_WDT_STG1 0x00000007U -#define RTC_CNTL_WDT_STG1_M (RTC_CNTL_WDT_STG1_V << RTC_CNTL_WDT_STG1_S) -#define RTC_CNTL_WDT_STG1_V 0x00000007U -#define RTC_CNTL_WDT_STG1_S 25 -/** RTC_CNTL_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ -#define RTC_CNTL_WDT_STG0 0x00000007U -#define RTC_CNTL_WDT_STG0_M (RTC_CNTL_WDT_STG0_V << RTC_CNTL_WDT_STG0_S) -#define RTC_CNTL_WDT_STG0_V 0x00000007U -#define RTC_CNTL_WDT_STG0_S 28 -/** RTC_CNTL_WDT_EN : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_WDT_EN (BIT(31)) -#define RTC_CNTL_WDT_EN_M (RTC_CNTL_WDT_EN_V << RTC_CNTL_WDT_EN_S) -#define RTC_CNTL_WDT_EN_V 0x00000001U -#define RTC_CNTL_WDT_EN_S 31 - -/** RTC_CNTL_WDTCONFIG1_REG register - * register description - */ -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0xbc) -/** RTC_CNTL_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; - * Need add description - */ -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG0_HOLD_M (RTC_CNTL_WDT_STG0_HOLD_V << RTC_CNTL_WDT_STG0_HOLD_S) -#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG0_HOLD_S 0 - -/** RTC_CNTL_WDTCONFIG2_REG register - * register description - */ -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xc0) -/** RTC_CNTL_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; - * Need add description - */ -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG1_HOLD_M (RTC_CNTL_WDT_STG1_HOLD_V << RTC_CNTL_WDT_STG1_HOLD_S) -#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG1_HOLD_S 0 - -/** RTC_CNTL_WDTCONFIG3_REG register - * register description - */ -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xc4) -/** RTC_CNTL_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; - * Need add description - */ -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG2_HOLD_M (RTC_CNTL_WDT_STG2_HOLD_V << RTC_CNTL_WDT_STG2_HOLD_S) -#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG2_HOLD_S 0 - -/** RTC_CNTL_WDTCONFIG4_REG register - * register description - */ -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xc8) -/** RTC_CNTL_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; - * Need add description - */ -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG3_HOLD_M (RTC_CNTL_WDT_STG3_HOLD_V << RTC_CNTL_WDT_STG3_HOLD_S) -#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFFU -#define RTC_CNTL_WDT_STG3_HOLD_S 0 - -/** RTC_CNTL_WDTFEED_REG register - * register description - */ -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xcc) -/** RTC_CNTL_WDT_FEED : WO; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_WDT_FEED (BIT(31)) -#define RTC_CNTL_WDT_FEED_M (RTC_CNTL_WDT_FEED_V << RTC_CNTL_WDT_FEED_S) -#define RTC_CNTL_WDT_FEED_V 0x00000001U -#define RTC_CNTL_WDT_FEED_S 31 - -/** RTC_CNTL_WDTWPROTECT_REG register - * register description - */ -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xd0) -/** RTC_CNTL_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFFU -#define RTC_CNTL_WDT_WKEY_M (RTC_CNTL_WDT_WKEY_V << RTC_CNTL_WDT_WKEY_S) -#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFFU -#define RTC_CNTL_WDT_WKEY_S 0 - -/** RTC_CNTL_WDTRESET_CHIP_REG register - * register description - */ -#define RTC_CNTL_WDTRESET_CHIP_REG (DR_REG_RTCCNTL_BASE + 0xd4) -/** RTC_CNTL_RESET_CHIP_TARGET : R/W; bitpos: [23:16]; default: 165; - * Need add description - */ -#define RTC_CNTL_RESET_CHIP_TARGET 0x000000FFU -#define RTC_CNTL_RESET_CHIP_TARGET_M (RTC_CNTL_RESET_CHIP_TARGET_V << RTC_CNTL_RESET_CHIP_TARGET_S) -#define RTC_CNTL_RESET_CHIP_TARGET_V 0x000000FFU -#define RTC_CNTL_RESET_CHIP_TARGET_S 16 -/** RTC_CNTL_RESET_CHIP_KEY : R/W; bitpos: [31:24]; default: 0; - * Need add description - */ -#define RTC_CNTL_RESET_CHIP_KEY 0x000000FFU -#define RTC_CNTL_RESET_CHIP_KEY_M (RTC_CNTL_RESET_CHIP_KEY_V << RTC_CNTL_RESET_CHIP_KEY_S) -#define RTC_CNTL_RESET_CHIP_KEY_V 0x000000FFU -#define RTC_CNTL_RESET_CHIP_KEY_S 24 - -/** RTC_CNTL_SWD_CONF_REG register - * register description - */ -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xd8) -/** RTC_CNTL_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; - * swd reset flag - */ -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_M (RTC_CNTL_SWD_RESET_FLAG_V << RTC_CNTL_SWD_RESET_FLAG_S) -#define RTC_CNTL_SWD_RESET_FLAG_V 0x00000001U -#define RTC_CNTL_SWD_RESET_FLAG_S 0 -/** RTC_CNTL_SWD_FEED_INT : RO; bitpos: [1]; default: 0; - * swd interrupt for feeding - */ -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_M (RTC_CNTL_SWD_FEED_INT_V << RTC_CNTL_SWD_FEED_INT_S) -#define RTC_CNTL_SWD_FEED_INT_V 0x00000001U -#define RTC_CNTL_SWD_FEED_INT_S 1 -/** RTC_CNTL_SWD_BYPASS_RST : R/W; bitpos: [17]; default: 0; - * Need add description - */ -#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) -#define RTC_CNTL_SWD_BYPASS_RST_M (RTC_CNTL_SWD_BYPASS_RST_V << RTC_CNTL_SWD_BYPASS_RST_S) -#define RTC_CNTL_SWD_BYPASS_RST_V 0x00000001U -#define RTC_CNTL_SWD_BYPASS_RST_S 17 -/** RTC_CNTL_SWD_SIGNAL_WIDTH : R/W; bitpos: [27:18]; default: 300; - * adjust signal width send to swd - */ -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FFU -#define RTC_CNTL_SWD_SIGNAL_WIDTH_M (RTC_CNTL_SWD_SIGNAL_WIDTH_V << RTC_CNTL_SWD_SIGNAL_WIDTH_S) -#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x000003FFU -#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 -/** RTC_CNTL_SWD_RST_FLAG_CLR : WO; bitpos: [28]; default: 0; - * reset swd reset flag - */ -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_M (RTC_CNTL_SWD_RST_FLAG_CLR_V << RTC_CNTL_SWD_RST_FLAG_CLR_S) -#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x00000001U -#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 -/** RTC_CNTL_SWD_FEED : WO; bitpos: [29]; default: 0; - * Sw feed swd - */ -#define RTC_CNTL_SWD_FEED (BIT(29)) -#define RTC_CNTL_SWD_FEED_M (RTC_CNTL_SWD_FEED_V << RTC_CNTL_SWD_FEED_S) -#define RTC_CNTL_SWD_FEED_V 0x00000001U -#define RTC_CNTL_SWD_FEED_S 29 -/** RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * disabel SWD - */ -#define RTC_CNTL_SWD_DISABLE (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_M (RTC_CNTL_SWD_DISABLE_V << RTC_CNTL_SWD_DISABLE_S) -#define RTC_CNTL_SWD_DISABLE_V 0x00000001U -#define RTC_CNTL_SWD_DISABLE_S 30 -/** RTC_CNTL_SWD_AUTO_FEED_EN : R/W; bitpos: [31]; default: 0; - * automatically feed swd when int comes - */ -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_M (RTC_CNTL_SWD_AUTO_FEED_EN_V << RTC_CNTL_SWD_AUTO_FEED_EN_S) -#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x00000001U -#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 - -/** RTC_CNTL_SWD_WPROTECT_REG register - * register description - */ -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xdc) -/** RTC_CNTL_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; - * swd write protect - */ -#define RTC_CNTL_SWD_WKEY 0xFFFFFFFFU -#define RTC_CNTL_SWD_WKEY_M (RTC_CNTL_SWD_WKEY_V << RTC_CNTL_SWD_WKEY_S) -#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFFU -#define RTC_CNTL_SWD_WKEY_S 0 - -/** RTC_CNTL_SW_CPU_STALL_REG register - * register description - */ -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xe0) -/** RTC_CNTL_SW_STALL_APPCPU_C1 : R/W; bitpos: [25:20]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP - * CPU - */ -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003FU -#define RTC_CNTL_SW_STALL_APPCPU_C1_M (RTC_CNTL_SW_STALL_APPCPU_C1_V << RTC_CNTL_SW_STALL_APPCPU_C1_S) -#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x0000003FU -#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 -/** RTC_CNTL_SW_STALL_PROCPU_C1 : R/W; bitpos: [31:26]; default: 0; - * Need add description - */ -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003FU -#define RTC_CNTL_SW_STALL_PROCPU_C1_M (RTC_CNTL_SW_STALL_PROCPU_C1_V << RTC_CNTL_SW_STALL_PROCPU_C1_S) -#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x0000003FU -#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 - -/** RTC_CNTL_STORE4_REG register - * register description - */ -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xe4) -/** RTC_CNTL_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH4 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH4_M (RTC_CNTL_SCRATCH4_V << RTC_CNTL_SCRATCH4_S) -#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH4_S 0 - -/** RTC_CNTL_STORE5_REG register - * register description - */ -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xe8) -/** RTC_CNTL_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH5 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH5_M (RTC_CNTL_SCRATCH5_V << RTC_CNTL_SCRATCH5_S) -#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH5_S 0 - -/** RTC_CNTL_STORE6_REG register - * register description - */ -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xec) -/** RTC_CNTL_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH6 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH6_M (RTC_CNTL_SCRATCH6_V << RTC_CNTL_SCRATCH6_S) -#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH6_S 0 - -/** RTC_CNTL_STORE7_REG register - * register description - */ -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xf0) -/** RTC_CNTL_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_SCRATCH7 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH7_M (RTC_CNTL_SCRATCH7_V << RTC_CNTL_SCRATCH7_S) -#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFFU -#define RTC_CNTL_SCRATCH7_S 0 - -/** RTC_CNTL_LOW_POWER_ST_REG register - * register description - */ -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xf4) -/** RTC_CNTL_XPD_ROM0 : RO; bitpos: [0]; default: 0; - * rom0 power down - */ -#define RTC_CNTL_XPD_ROM0 (BIT(0)) -#define RTC_CNTL_XPD_ROM0_M (RTC_CNTL_XPD_ROM0_V << RTC_CNTL_XPD_ROM0_S) -#define RTC_CNTL_XPD_ROM0_V 0x00000001U -#define RTC_CNTL_XPD_ROM0_S 0 -/** RTC_CNTL_XPD_DIG_DCDC : RO; bitpos: [2]; default: 0; - * External DCDC power down - */ -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_M (RTC_CNTL_XPD_DIG_DCDC_V << RTC_CNTL_XPD_DIG_DCDC_S) -#define RTC_CNTL_XPD_DIG_DCDC_V 0x00000001U -#define RTC_CNTL_XPD_DIG_DCDC_S 2 -/** RTC_CNTL_PERI_ISO : RO; bitpos: [3]; default: 0; - * rtc peripheral iso - */ -#define RTC_CNTL_PERI_ISO (BIT(3)) -#define RTC_CNTL_PERI_ISO_M (RTC_CNTL_PERI_ISO_V << RTC_CNTL_PERI_ISO_S) -#define RTC_CNTL_PERI_ISO_V 0x00000001U -#define RTC_CNTL_PERI_ISO_S 3 -/** RTC_CNTL_XPD_RTC_PERI : RO; bitpos: [4]; default: 0; - * rtc peripheral power down - */ -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_M (RTC_CNTL_XPD_RTC_PERI_V << RTC_CNTL_XPD_RTC_PERI_S) -#define RTC_CNTL_XPD_RTC_PERI_V 0x00000001U -#define RTC_CNTL_XPD_RTC_PERI_S 4 -/** RTC_CNTL_WIFI_ISO : RO; bitpos: [5]; default: 0; - * wifi iso - */ -#define RTC_CNTL_WIFI_ISO (BIT(5)) -#define RTC_CNTL_WIFI_ISO_M (RTC_CNTL_WIFI_ISO_V << RTC_CNTL_WIFI_ISO_S) -#define RTC_CNTL_WIFI_ISO_V 0x00000001U -#define RTC_CNTL_WIFI_ISO_S 5 -/** RTC_CNTL_XPD_WIFI : RO; bitpos: [6]; default: 0; - * wifi wrap power down - */ -#define RTC_CNTL_XPD_WIFI (BIT(6)) -#define RTC_CNTL_XPD_WIFI_M (RTC_CNTL_XPD_WIFI_V << RTC_CNTL_XPD_WIFI_S) -#define RTC_CNTL_XPD_WIFI_V 0x00000001U -#define RTC_CNTL_XPD_WIFI_S 6 -/** RTC_CNTL_DIG_ISO : RO; bitpos: [7]; default: 0; - * digital wrap iso - */ -#define RTC_CNTL_DIG_ISO (BIT(7)) -#define RTC_CNTL_DIG_ISO_M (RTC_CNTL_DIG_ISO_V << RTC_CNTL_DIG_ISO_S) -#define RTC_CNTL_DIG_ISO_V 0x00000001U -#define RTC_CNTL_DIG_ISO_S 7 -/** RTC_CNTL_XPD_DIG : RO; bitpos: [8]; default: 0; - * digital wrap power down - */ -#define RTC_CNTL_XPD_DIG (BIT(8)) -#define RTC_CNTL_XPD_DIG_M (RTC_CNTL_XPD_DIG_V << RTC_CNTL_XPD_DIG_S) -#define RTC_CNTL_XPD_DIG_V 0x00000001U -#define RTC_CNTL_XPD_DIG_S 8 -/** RTC_CNTL_TOUCH_STATE_START : RO; bitpos: [9]; default: 0; - * touch should start to work - */ -#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) -#define RTC_CNTL_TOUCH_STATE_START_M (RTC_CNTL_TOUCH_STATE_START_V << RTC_CNTL_TOUCH_STATE_START_S) -#define RTC_CNTL_TOUCH_STATE_START_V 0x00000001U -#define RTC_CNTL_TOUCH_STATE_START_S 9 -/** RTC_CNTL_TOUCH_STATE_SWITCH : RO; bitpos: [10]; default: 0; - * touch is about to working. Switch rtc main state - */ -#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) -#define RTC_CNTL_TOUCH_STATE_SWITCH_M (RTC_CNTL_TOUCH_STATE_SWITCH_V << RTC_CNTL_TOUCH_STATE_SWITCH_S) -#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x00000001U -#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 -/** RTC_CNTL_TOUCH_STATE_SLP : RO; bitpos: [11]; default: 0; - * touch is in sleep state - */ -#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) -#define RTC_CNTL_TOUCH_STATE_SLP_M (RTC_CNTL_TOUCH_STATE_SLP_V << RTC_CNTL_TOUCH_STATE_SLP_S) -#define RTC_CNTL_TOUCH_STATE_SLP_V 0x00000001U -#define RTC_CNTL_TOUCH_STATE_SLP_S 11 -/** RTC_CNTL_TOUCH_STATE_DONE : RO; bitpos: [12]; default: 0; - * touch is done - */ -#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) -#define RTC_CNTL_TOUCH_STATE_DONE_M (RTC_CNTL_TOUCH_STATE_DONE_V << RTC_CNTL_TOUCH_STATE_DONE_S) -#define RTC_CNTL_TOUCH_STATE_DONE_V 0x00000001U -#define RTC_CNTL_TOUCH_STATE_DONE_S 12 -/** RTC_CNTL_COCPU_STATE_START : RO; bitpos: [13]; default: 0; - * ulp/cocpu should start to work - */ -#define RTC_CNTL_COCPU_STATE_START (BIT(13)) -#define RTC_CNTL_COCPU_STATE_START_M (RTC_CNTL_COCPU_STATE_START_V << RTC_CNTL_COCPU_STATE_START_S) -#define RTC_CNTL_COCPU_STATE_START_V 0x00000001U -#define RTC_CNTL_COCPU_STATE_START_S 13 -/** RTC_CNTL_COCPU_STATE_SWITCH : RO; bitpos: [14]; default: 0; - * ulp/cocpu is about to working. Switch rtc main state - */ -#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) -#define RTC_CNTL_COCPU_STATE_SWITCH_M (RTC_CNTL_COCPU_STATE_SWITCH_V << RTC_CNTL_COCPU_STATE_SWITCH_S) -#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x00000001U -#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 -/** RTC_CNTL_COCPU_STATE_SLP : RO; bitpos: [15]; default: 0; - * ulp/cocpu is in sleep state - */ -#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) -#define RTC_CNTL_COCPU_STATE_SLP_M (RTC_CNTL_COCPU_STATE_SLP_V << RTC_CNTL_COCPU_STATE_SLP_S) -#define RTC_CNTL_COCPU_STATE_SLP_V 0x00000001U -#define RTC_CNTL_COCPU_STATE_SLP_S 15 -/** RTC_CNTL_COCPU_STATE_DONE : RO; bitpos: [16]; default: 0; - * ulp/cocpu is done - */ -#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) -#define RTC_CNTL_COCPU_STATE_DONE_M (RTC_CNTL_COCPU_STATE_DONE_V << RTC_CNTL_COCPU_STATE_DONE_S) -#define RTC_CNTL_COCPU_STATE_DONE_V 0x00000001U -#define RTC_CNTL_COCPU_STATE_DONE_S 16 -/** RTC_CNTL_MAIN_STATE_XTAL_ISO : RO; bitpos: [17]; default: 0; - * no use any more - */ -#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (RTC_CNTL_MAIN_STATE_XTAL_ISO_V << RTC_CNTL_MAIN_STATE_XTAL_ISO_S) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 -/** RTC_CNTL_MAIN_STATE_PLL_ON : RO; bitpos: [18]; default: 0; - * rtc main state machine is in states that pll should be running - */ -#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) -#define RTC_CNTL_MAIN_STATE_PLL_ON_M (RTC_CNTL_MAIN_STATE_PLL_ON_V << RTC_CNTL_MAIN_STATE_PLL_ON_S) -#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 -/** RTC_CNTL_RDY_FOR_WAKEUP : RO; bitpos: [19]; default: 0; - * rtc is ready to receive wake up trigger from wake up source - */ -#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) -#define RTC_CNTL_RDY_FOR_WAKEUP_M (RTC_CNTL_RDY_FOR_WAKEUP_V << RTC_CNTL_RDY_FOR_WAKEUP_S) -#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x00000001U -#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 -/** RTC_CNTL_MAIN_STATE_WAIT_END : RO; bitpos: [20]; default: 0; - * rtc main state machine has been waited for some cycles - */ -#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) -#define RTC_CNTL_MAIN_STATE_WAIT_END_M (RTC_CNTL_MAIN_STATE_WAIT_END_V << RTC_CNTL_MAIN_STATE_WAIT_END_S) -#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 -/** RTC_CNTL_IN_WAKEUP_STATE : RO; bitpos: [21]; default: 0; - * rtc main state machine is in the states of wakeup process - */ -#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) -#define RTC_CNTL_IN_WAKEUP_STATE_M (RTC_CNTL_IN_WAKEUP_STATE_V << RTC_CNTL_IN_WAKEUP_STATE_S) -#define RTC_CNTL_IN_WAKEUP_STATE_V 0x00000001U -#define RTC_CNTL_IN_WAKEUP_STATE_S 21 -/** RTC_CNTL_IN_LOW_POWER_STATE : RO; bitpos: [22]; default: 0; - * rtc main state machine is in the states of low power - */ -#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) -#define RTC_CNTL_IN_LOW_POWER_STATE_M (RTC_CNTL_IN_LOW_POWER_STATE_V << RTC_CNTL_IN_LOW_POWER_STATE_S) -#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x00000001U -#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 -/** RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO; bitpos: [23]; default: 0; - * rtc main state machine is in wait 8m state - */ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V << RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 -/** RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO; bitpos: [24]; default: 0; - * rtc main state machine is in wait pll state - */ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 -/** RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO; bitpos: [25]; default: 0; - * rtc main state machine is in wait xtal state - */ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 -/** RTC_CNTL_MAIN_STATE_IN_SLP : RO; bitpos: [26]; default: 0; - * rtc main state machine is in sleep state - */ -#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) -#define RTC_CNTL_MAIN_STATE_IN_SLP_M (RTC_CNTL_MAIN_STATE_IN_SLP_V << RTC_CNTL_MAIN_STATE_IN_SLP_S) -#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 -/** RTC_CNTL_MAIN_STATE_IN_IDLE : RO; bitpos: [27]; default: 0; - * rtc main state machine is in idle state - */ -#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (RTC_CNTL_MAIN_STATE_IN_IDLE_V << RTC_CNTL_MAIN_STATE_IN_IDLE_S) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x00000001U -#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 -/** RTC_CNTL_MAIN_STATE : RO; bitpos: [31:28]; default: 0; - * rtc main state machine status - */ -#define RTC_CNTL_MAIN_STATE 0x0000000FU -#define RTC_CNTL_MAIN_STATE_M (RTC_CNTL_MAIN_STATE_V << RTC_CNTL_MAIN_STATE_S) -#define RTC_CNTL_MAIN_STATE_V 0x0000000FU -#define RTC_CNTL_MAIN_STATE_S 28 - -/** RTC_CNTL_DIAG0_REG register - * register description - */ -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xf8) -/** RTC_CNTL_LOW_POWER_DIAG1 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFFU -#define RTC_CNTL_LOW_POWER_DIAG1_M (RTC_CNTL_LOW_POWER_DIAG1_V << RTC_CNTL_LOW_POWER_DIAG1_S) -#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFFU -#define RTC_CNTL_LOW_POWER_DIAG1_S 0 - -/** RTC_CNTL_PAD_HOLD_REG register - * register description - */ -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xfc) -/** RTC_CNTL_GPIO_PIN0_HOLD : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) -#define RTC_CNTL_GPIO_PIN0_HOLD_M (RTC_CNTL_GPIO_PIN0_HOLD_V << RTC_CNTL_GPIO_PIN0_HOLD_S) -#define RTC_CNTL_GPIO_PIN0_HOLD_V 0x00000001U -#define RTC_CNTL_GPIO_PIN0_HOLD_S 0 -/** RTC_CNTL_GPIO_PIN1_HOLD : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) -#define RTC_CNTL_GPIO_PIN1_HOLD_M (RTC_CNTL_GPIO_PIN1_HOLD_V << RTC_CNTL_GPIO_PIN1_HOLD_S) -#define RTC_CNTL_GPIO_PIN1_HOLD_V 0x00000001U -#define RTC_CNTL_GPIO_PIN1_HOLD_S 1 -/** RTC_CNTL_GPIO_PIN2_HOLD : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) -#define RTC_CNTL_GPIO_PIN2_HOLD_M (RTC_CNTL_GPIO_PIN2_HOLD_V << RTC_CNTL_GPIO_PIN2_HOLD_S) -#define RTC_CNTL_GPIO_PIN2_HOLD_V 0x00000001U -#define RTC_CNTL_GPIO_PIN2_HOLD_S 2 -/** RTC_CNTL_GPIO_PIN3_HOLD : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) -#define RTC_CNTL_GPIO_PIN3_HOLD_M (RTC_CNTL_GPIO_PIN3_HOLD_V << RTC_CNTL_GPIO_PIN3_HOLD_S) -#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x00000001U -#define RTC_CNTL_GPIO_PIN3_HOLD_S 3 -/** RTC_CNTL_GPIO_PIN4_HOLD : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) -#define RTC_CNTL_GPIO_PIN4_HOLD_M (RTC_CNTL_GPIO_PIN4_HOLD_V << RTC_CNTL_GPIO_PIN4_HOLD_S) -#define RTC_CNTL_GPIO_PIN4_HOLD_V 0x00000001U -#define RTC_CNTL_GPIO_PIN4_HOLD_S 4 -/** RTC_CNTL_GPIO_PIN5_HOLD : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) -#define RTC_CNTL_GPIO_PIN5_HOLD_M (RTC_CNTL_GPIO_PIN5_HOLD_V << RTC_CNTL_GPIO_PIN5_HOLD_S) -#define RTC_CNTL_GPIO_PIN5_HOLD_V 0x00000001U -#define RTC_CNTL_GPIO_PIN5_HOLD_S 5 - -/** RTC_CNTL_DIG_PAD_HOLD_REG register - * register description - */ -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x100) -/** RTC_CNTL_DIG_PAD_HOLD : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFFU -#define RTC_CNTL_DIG_PAD_HOLD_M (RTC_CNTL_DIG_PAD_HOLD_V << RTC_CNTL_DIG_PAD_HOLD_S) -#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFFU -#define RTC_CNTL_DIG_PAD_HOLD_S 0 - -/** RTC_CNTL_DIG_PAD_HOLD1_REG register - * register description - */ -#define RTC_CNTL_DIG_PAD_HOLD1_REG (DR_REG_RTCCNTL_BASE + 0x104) -/** RTC_CNTL_DIG_PAD_HOLD1 : R/W; bitpos: [8:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_DIG_PAD_HOLD1 0x000001FFU -#define RTC_CNTL_DIG_PAD_HOLD1_M (RTC_CNTL_DIG_PAD_HOLD1_V << RTC_CNTL_DIG_PAD_HOLD1_S) -#define RTC_CNTL_DIG_PAD_HOLD1_V 0x000001FFU -#define RTC_CNTL_DIG_PAD_HOLD1_S 0 - -/** RTC_CNTL_BROWN_OUT_REG register - * register description - */ -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x108) -/** RTC_CNTL_BROWN_OUT_INT_WAIT : R/W; bitpos: [13:4]; default: 1; - * brown out interrupt wait cycles - */ -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FFU -#define RTC_CNTL_BROWN_OUT_INT_WAIT_M (RTC_CNTL_BROWN_OUT_INT_WAIT_V << RTC_CNTL_BROWN_OUT_INT_WAIT_S) -#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x000003FFU -#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 -/** RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W; bitpos: [14]; default: 0; - * enable close flash when brown out happens - */ -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V << RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 -/** RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W; bitpos: [15]; default: 0; - * enable power down RF when brown out happens - */ -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (RTC_CNTL_BROWN_OUT_PD_RF_ENA_V << RTC_CNTL_BROWN_OUT_PD_RF_ENA_S) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 -/** RTC_CNTL_BROWN_OUT_RST_WAIT : R/W; bitpos: [25:16]; default: 1023; - * brown out reset wait cycles - */ -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FFU -#define RTC_CNTL_BROWN_OUT_RST_WAIT_M (RTC_CNTL_BROWN_OUT_RST_WAIT_V << RTC_CNTL_BROWN_OUT_RST_WAIT_S) -#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x000003FFU -#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 -/** RTC_CNTL_BROWN_OUT_RST_ENA : R/W; bitpos: [26]; default: 0; - * enable brown out reset - */ -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_M (RTC_CNTL_BROWN_OUT_RST_ENA_V << RTC_CNTL_BROWN_OUT_RST_ENA_S) -#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 -/** RTC_CNTL_BROWN_OUT_RST_SEL : R/W; bitpos: [27]; default: 0; - * 1: 4-pos reset, 0: sys_reset - */ -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_M (RTC_CNTL_BROWN_OUT_RST_SEL_V << RTC_CNTL_BROWN_OUT_RST_SEL_S) -#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 -/** RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (RTC_CNTL_BROWN_OUT_ANA_RST_EN_V << RTC_CNTL_BROWN_OUT_ANA_RST_EN_S) -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 -/** RTC_CNTL_BROWN_OUT_CNT_CLR : WO; bitpos: [29]; default: 0; - * clear brown out counter - */ -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (RTC_CNTL_BROWN_OUT_CNT_CLR_V << RTC_CNTL_BROWN_OUT_CNT_CLR_S) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 -/** RTC_CNTL_BROWN_OUT_ENA : R/W; bitpos: [30]; default: 1; - * enable brown out - */ -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_M (RTC_CNTL_BROWN_OUT_ENA_V << RTC_CNTL_BROWN_OUT_ENA_S) -#define RTC_CNTL_BROWN_OUT_ENA_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_ENA_S 30 -/** RTC_CNTL_BROWN_OUT_DET : RO; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_M (RTC_CNTL_BROWN_OUT_DET_V << RTC_CNTL_BROWN_OUT_DET_S) -#define RTC_CNTL_BROWN_OUT_DET_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_DET_S 31 - -/** RTC_CNTL_TIME_LOW1_REG register - * register description - */ -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x10c) -/** RTC_CNTL_TIMER_VALUE1_LOW : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ -#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFFU -#define RTC_CNTL_TIMER_VALUE1_LOW_M (RTC_CNTL_TIMER_VALUE1_LOW_V << RTC_CNTL_TIMER_VALUE1_LOW_S) -#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFFU -#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 - -/** RTC_CNTL_TIME_HIGH1_REG register - * register description - */ -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x110) -/** RTC_CNTL_TIMER_VALUE1_HIGH : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ -#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFFU -#define RTC_CNTL_TIMER_VALUE1_HIGH_M (RTC_CNTL_TIMER_VALUE1_HIGH_V << RTC_CNTL_TIMER_VALUE1_HIGH_S) -#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0x0000FFFFU -#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 - -/** RTC_CNTL_XTAL32K_CLK_FACTOR_REG register - * register description - */ -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x114) -/** RTC_CNTL_XTAL32K_CLK_FACTOR : R/W; bitpos: [31:0]; default: 0; - * xtal 32k watch dog backup clock factor - */ -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFFU -#define RTC_CNTL_XTAL32K_CLK_FACTOR_M (RTC_CNTL_XTAL32K_CLK_FACTOR_V << RTC_CNTL_XTAL32K_CLK_FACTOR_S) -#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFFU -#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 - -/** RTC_CNTL_XTAL32K_CONF_REG register - * register description - */ -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x118) -/** RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; - * cycles to wait to return noral xtal 32k - */ -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000FU -#define RTC_CNTL_XTAL32K_RETURN_WAIT_M (RTC_CNTL_XTAL32K_RETURN_WAIT_V << RTC_CNTL_XTAL32K_RETURN_WAIT_S) -#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000FU -#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 -/** RTC_CNTL_XTAL32K_RESTART_WAIT : R/W; bitpos: [19:4]; default: 0; - * cycles to wait to repower on xtal 32k - */ -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFFU -#define RTC_CNTL_XTAL32K_RESTART_WAIT_M (RTC_CNTL_XTAL32K_RESTART_WAIT_V << RTC_CNTL_XTAL32K_RESTART_WAIT_S) -#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0x0000FFFFU -#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 -/** RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W; bitpos: [27:20]; default: 255; - * If no clock detected for this amount of time, 32k is regarded as dead - */ -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FFU -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M (RTC_CNTL_XTAL32K_WDT_TIMEOUT_V << RTC_CNTL_XTAL32K_WDT_TIMEOUT_S) -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0x000000FFU -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 -/** RTC_CNTL_XTAL32K_STABLE_THRES : R/W; bitpos: [31:28]; default: 0; - * if restarted xtal32k period is smaller than this, it is regarded as stable - */ -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000FU -#define RTC_CNTL_XTAL32K_STABLE_THRES_M (RTC_CNTL_XTAL32K_STABLE_THRES_V << RTC_CNTL_XTAL32K_STABLE_THRES_S) -#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0x0000000FU -#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 - -/** RTC_CNTL_USB_CONF_REG register - * register description - */ -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11c) -/** RTC_CNTL_IO_MUX_RESET_DISABLE : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (RTC_CNTL_IO_MUX_RESET_DISABLE_V << RTC_CNTL_IO_MUX_RESET_DISABLE_S) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x00000001U -#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 - -/** RTC_CNTL_SLP_REJECT_CAUSE_REG register - * register description - */ -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x120) -/** RTC_CNTL_REJECT_CAUSE : RO; bitpos: [18:0]; default: 0; - * sleep reject cause - */ -#define RTC_CNTL_REJECT_CAUSE 0x0007FFFFU -#define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S) -#define RTC_CNTL_REJECT_CAUSE_V 0x0007FFFFU -#define RTC_CNTL_REJECT_CAUSE_S 0 - -/** RTC_CNTL_OPTION1_REG register - * register description - */ -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x124) -/** RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (RTC_CNTL_FORCE_DOWNLOAD_BOOT_V << RTC_CNTL_FORCE_DOWNLOAD_BOOT_S) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x00000001U -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 - -/** RTC_CNTL_SLP_WAKEUP_CAUSE_REG register - * register description - */ -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) -/** RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [18:0]; default: 0; - * sleep wakeup cause - */ -#define RTC_CNTL_WAKEUP_CAUSE 0x0007FFFFU -#define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x0007FFFFU -#define RTC_CNTL_WAKEUP_CAUSE_S 0 - -/** RTC_CNTL_ULP_CP_TIMER_1_REG register - * register description - */ -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x12c) -/** RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W; bitpos: [31:8]; default: 200; - * sleep cycles for ULP-coprocessor timer - */ -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFFU -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V << RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S) -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0x00FFFFFFU -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 - -/** RTC_CNTL_INT_ENA_RTC_W1TS_REG register - * register description - */ -#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x130) -/** RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 -/** RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V << RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 -/** RTC_CNTL_WDT_INT_ENA_W1TS : WO; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ -#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TS_M (RTC_CNTL_WDT_INT_ENA_W1TS_V << RTC_CNTL_WDT_INT_ENA_W1TS_S) -#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 -/** RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO; bitpos: [9]; default: 0; - * enable brown out interrupt - */ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V << RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 -/** RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V << RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 -/** RTC_CNTL_SWD_INT_ENA_W1TS : WO; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ -#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TS_M (RTC_CNTL_SWD_INT_ENA_W1TS_V << RTC_CNTL_SWD_INT_ENA_W1TS_S) -#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 -/** RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V << RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 -/** RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO; bitpos: [19]; default: 0; - * enbale gitch det interrupt - */ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V << RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 -/** RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V << RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 -/** RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS : WO; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_M (RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_V << RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_S) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TS_S 21 -/** RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS : WO; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_M (RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_V << RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_S) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TS_S 22 - -/** RTC_CNTL_INT_ENA_RTC_W1TC_REG register - * register description - */ -#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x134) -/** RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 -/** RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V << RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 -/** RTC_CNTL_WDT_INT_ENA_W1TC : WO; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ -#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_W1TC_M (RTC_CNTL_WDT_INT_ENA_W1TC_V << RTC_CNTL_WDT_INT_ENA_W1TC_S) -#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 -/** RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO; bitpos: [9]; default: 0; - * enable brown out interrupt - */ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V << RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S) -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 -/** RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V << RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 -/** RTC_CNTL_SWD_INT_ENA_W1TC : WO; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ -#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_W1TC_M (RTC_CNTL_SWD_INT_ENA_W1TC_V << RTC_CNTL_SWD_INT_ENA_W1TC_S) -#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 -/** RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V << RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 -/** RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO; bitpos: [19]; default: 0; - * enbale gitch det interrupt - */ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V << RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S) -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 -/** RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO; bitpos: [20]; default: 0; - * Need add description - */ -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V << RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S) -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 -/** RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC : WO; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC (BIT(21)) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_M (RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_V << RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_S) -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_BLE_COMPARE_WAKE_INT_ENA_W1TC_S 21 -/** RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC : WO; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC (BIT(22)) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_M (RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_V << RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_S) -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_DONE_INT_ENA_W1TC_S 22 - -/** RTC_CNTL_RETENTION_CTRL_REG register - * register description - */ -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x138) -/** RTC_CNTL_CLK_EN : R/W; bitpos: [17]; default: 0; - * Need add description - */ -#define RTC_CNTL_CLK_EN (BIT(17)) -#define RTC_CNTL_CLK_EN_M (RTC_CNTL_CLK_EN_V << RTC_CNTL_CLK_EN_S) -#define RTC_CNTL_CLK_EN_V 0x00000001U -#define RTC_CNTL_CLK_EN_S 17 -/** RTC_CNTL_RETENTION_CLK_SEL : R/W; bitpos: [18]; default: 0; - * Need add description - */ -#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) -#define RTC_CNTL_RETENTION_CLK_SEL_M (RTC_CNTL_RETENTION_CLK_SEL_V << RTC_CNTL_RETENTION_CLK_SEL_S) -#define RTC_CNTL_RETENTION_CLK_SEL_V 0x00000001U -#define RTC_CNTL_RETENTION_CLK_SEL_S 18 -/** RTC_CNTL_RETENTION_DONE_WAIT : R/W; bitpos: [21:19]; default: 2; - * Need add description - */ -#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007U -#define RTC_CNTL_RETENTION_DONE_WAIT_M (RTC_CNTL_RETENTION_DONE_WAIT_V << RTC_CNTL_RETENTION_DONE_WAIT_S) -#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x00000007U -#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 -/** RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W; bitpos: [25:22]; default: 3; - * Need add description - */ -#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000FU -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M (RTC_CNTL_RETENTION_CLKOFF_WAIT_V << RTC_CNTL_RETENTION_CLKOFF_WAIT_S) -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0x0000000FU -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 -/** RTC_CNTL_RETENTION_EN : R/W; bitpos: [26]; default: 0; - * Need add description - */ -#define RTC_CNTL_RETENTION_EN (BIT(26)) -#define RTC_CNTL_RETENTION_EN_M (RTC_CNTL_RETENTION_EN_V << RTC_CNTL_RETENTION_EN_S) -#define RTC_CNTL_RETENTION_EN_V 0x00000001U -#define RTC_CNTL_RETENTION_EN_S 26 -/** RTC_CNTL_RETENTION_WAIT : R/W; bitpos: [31:27]; default: 20; - * wait cycles for rention operation - */ -#define RTC_CNTL_RETENTION_WAIT 0x0000001FU -#define RTC_CNTL_RETENTION_WAIT_M (RTC_CNTL_RETENTION_WAIT_V << RTC_CNTL_RETENTION_WAIT_S) -#define RTC_CNTL_RETENTION_WAIT_V 0x0000001FU -#define RTC_CNTL_RETENTION_WAIT_S 27 - -/** RTC_CNTL_RETENTION_CTRL1_REG register - * register description - */ -#define RTC_CNTL_RETENTION_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x13c) -/** RTC_CNTL_RETENTION_LINK_ADDR : R/W; bitpos: [26:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_RETENTION_LINK_ADDR 0x07FFFFFFU -#define RTC_CNTL_RETENTION_LINK_ADDR_M (RTC_CNTL_RETENTION_LINK_ADDR_V << RTC_CNTL_RETENTION_LINK_ADDR_S) -#define RTC_CNTL_RETENTION_LINK_ADDR_V 0x07FFFFFFU -#define RTC_CNTL_RETENTION_LINK_ADDR_S 0 - -/** RTC_CNTL_FIB_SEL_REG register - * register description - */ -#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x140) -/** RTC_CNTL_FIB_SEL : R/W; bitpos: [2:0]; default: 7; - * select use analog fib signal - */ -#define RTC_CNTL_FIB_SEL 0x00000007U -#define RTC_CNTL_FIB_SEL_M (RTC_CNTL_FIB_SEL_V << RTC_CNTL_FIB_SEL_S) -#define RTC_CNTL_FIB_SEL_V 0x00000007U -#define RTC_CNTL_FIB_SEL_S 0 - -#define RTC_CNTL_FIB_GLITCH_RST BIT(0) -#define RTC_CNTL_FIB_BOD_RST BIT(1) -#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) - -/** RTC_CNTL_GPIO_WAKEUP_REG register - * register description - */ -#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x144) -/** RTC_CNTL_GPIO_WAKEUP_STATUS : RO; bitpos: [5:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003FU -#define RTC_CNTL_GPIO_WAKEUP_STATUS_M (RTC_CNTL_GPIO_WAKEUP_STATUS_V << RTC_CNTL_GPIO_WAKEUP_STATUS_S) -#define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x0000003FU -#define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 -/** RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V << RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S) -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x00000001U -#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 -/** RTC_CNTL_GPIO_PIN_CLK_GATE : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) -#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (RTC_CNTL_GPIO_PIN_CLK_GATE_V << RTC_CNTL_GPIO_PIN_CLK_GATE_S) -#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 -/** RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W; bitpos: [10:8]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007U -#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M (RTC_CNTL_GPIO_PIN5_INT_TYPE_V << RTC_CNTL_GPIO_PIN5_INT_TYPE_S) -#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x00000007U -#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 -/** RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W; bitpos: [13:11]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007U -#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M (RTC_CNTL_GPIO_PIN4_INT_TYPE_V << RTC_CNTL_GPIO_PIN4_INT_TYPE_S) -#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x00000007U -#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 -/** RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W; bitpos: [16:14]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007U -#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M (RTC_CNTL_GPIO_PIN3_INT_TYPE_V << RTC_CNTL_GPIO_PIN3_INT_TYPE_S) -#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x00000007U -#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 -/** RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W; bitpos: [19:17]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007U -#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M (RTC_CNTL_GPIO_PIN2_INT_TYPE_V << RTC_CNTL_GPIO_PIN2_INT_TYPE_S) -#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x00000007U -#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 -/** RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W; bitpos: [22:20]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007U -#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M (RTC_CNTL_GPIO_PIN1_INT_TYPE_V << RTC_CNTL_GPIO_PIN1_INT_TYPE_S) -#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x00000007U -#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 -/** RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W; bitpos: [25:23]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007U -#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M (RTC_CNTL_GPIO_PIN0_INT_TYPE_V << RTC_CNTL_GPIO_PIN0_INT_TYPE_S) -#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x00000007U -#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 -/** RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [26]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V << RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S) -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 -/** RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V << RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S) -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 -/** RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V << RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S) -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 -/** RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [29]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V << RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S) -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 -/** RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V << RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S) -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 -/** RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V << RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S) -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U -#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 - -/** RTC_CNTL_DBG_SEL_REG register - * register description - */ -#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) -/** RTC_CNTL_MTDI_ENAMUX : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define RTC_CNTL_MTDI_ENAMUX (BIT(0)) -#define RTC_CNTL_MTDI_ENAMUX_M (RTC_CNTL_MTDI_ENAMUX_V << RTC_CNTL_MTDI_ENAMUX_S) -#define RTC_CNTL_MTDI_ENAMUX_V 0x00000001U -#define RTC_CNTL_MTDI_ENAMUX_S 0 -/** RTC_CNTL_DEBUG_12M_NO_GATING : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) -#define RTC_CNTL_DEBUG_12M_NO_GATING_M (RTC_CNTL_DEBUG_12M_NO_GATING_V << RTC_CNTL_DEBUG_12M_NO_GATING_S) -#define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x00000001U -#define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 -/** RTC_CNTL_DEBUG_BIT_SEL : R/W; bitpos: [6:2]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001FU -#define RTC_CNTL_DEBUG_BIT_SEL_M (RTC_CNTL_DEBUG_BIT_SEL_V << RTC_CNTL_DEBUG_BIT_SEL_S) -#define RTC_CNTL_DEBUG_BIT_SEL_V 0x0000001FU -#define RTC_CNTL_DEBUG_BIT_SEL_S 2 -/** RTC_CNTL_DEBUG_SEL0 : R/W; bitpos: [11:7]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_SEL0 0x0000001FU -#define RTC_CNTL_DEBUG_SEL0_M (RTC_CNTL_DEBUG_SEL0_V << RTC_CNTL_DEBUG_SEL0_S) -#define RTC_CNTL_DEBUG_SEL0_V 0x0000001FU -#define RTC_CNTL_DEBUG_SEL0_S 7 -/** RTC_CNTL_DEBUG_SEL1 : R/W; bitpos: [16:12]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_SEL1 0x0000001FU -#define RTC_CNTL_DEBUG_SEL1_M (RTC_CNTL_DEBUG_SEL1_V << RTC_CNTL_DEBUG_SEL1_S) -#define RTC_CNTL_DEBUG_SEL1_V 0x0000001FU -#define RTC_CNTL_DEBUG_SEL1_S 12 -/** RTC_CNTL_DEBUG_SEL2 : R/W; bitpos: [21:17]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_SEL2 0x0000001FU -#define RTC_CNTL_DEBUG_SEL2_M (RTC_CNTL_DEBUG_SEL2_V << RTC_CNTL_DEBUG_SEL2_S) -#define RTC_CNTL_DEBUG_SEL2_V 0x0000001FU -#define RTC_CNTL_DEBUG_SEL2_S 17 -/** RTC_CNTL_DEBUG_SEL3 : R/W; bitpos: [26:22]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_SEL3 0x0000001FU -#define RTC_CNTL_DEBUG_SEL3_M (RTC_CNTL_DEBUG_SEL3_V << RTC_CNTL_DEBUG_SEL3_S) -#define RTC_CNTL_DEBUG_SEL3_V 0x0000001FU -#define RTC_CNTL_DEBUG_SEL3_S 22 -/** RTC_CNTL_DEBUG_SEL4 : R/W; bitpos: [31:27]; default: 0; - * Need add description - */ -#define RTC_CNTL_DEBUG_SEL4 0x0000001FU -#define RTC_CNTL_DEBUG_SEL4_M (RTC_CNTL_DEBUG_SEL4_V << RTC_CNTL_DEBUG_SEL4_S) -#define RTC_CNTL_DEBUG_SEL4_V 0x0000001FU -#define RTC_CNTL_DEBUG_SEL4_S 27 - -/** RTC_CNTL_DBG_MAP_REG register - * register description - */ -#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x14c) -/** RTC_CNTL_VDD_DIG_TEST : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_VDD_DIG_TEST 0x00000003U -#define RTC_CNTL_VDD_DIG_TEST_M (RTC_CNTL_VDD_DIG_TEST_V << RTC_CNTL_VDD_DIG_TEST_S) -#define RTC_CNTL_VDD_DIG_TEST_V 0x00000003U -#define RTC_CNTL_VDD_DIG_TEST_S 0 -/** RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) -#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (RTC_CNTL_GPIO_PIN5_MUX_SEL_V << RTC_CNTL_GPIO_PIN5_MUX_SEL_S) -#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x00000001U -#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 -/** RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) -#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (RTC_CNTL_GPIO_PIN4_MUX_SEL_V << RTC_CNTL_GPIO_PIN4_MUX_SEL_S) -#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x00000001U -#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 -/** RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W; bitpos: [4]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) -#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (RTC_CNTL_GPIO_PIN3_MUX_SEL_V << RTC_CNTL_GPIO_PIN3_MUX_SEL_S) -#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x00000001U -#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 -/** RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) -#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (RTC_CNTL_GPIO_PIN2_MUX_SEL_V << RTC_CNTL_GPIO_PIN2_MUX_SEL_S) -#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x00000001U -#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 -/** RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) -#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (RTC_CNTL_GPIO_PIN1_MUX_SEL_V << RTC_CNTL_GPIO_PIN1_MUX_SEL_S) -#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x00000001U -#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 -/** RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) -#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (RTC_CNTL_GPIO_PIN0_MUX_SEL_V << RTC_CNTL_GPIO_PIN0_MUX_SEL_S) -#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x00000001U -#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 -/** RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W; bitpos: [11:8]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000FU -#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M (RTC_CNTL_GPIO_PIN5_FUN_SEL_V << RTC_CNTL_GPIO_PIN5_FUN_SEL_S) -#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0x0000000FU -#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 -/** RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W; bitpos: [15:12]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000FU -#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M (RTC_CNTL_GPIO_PIN4_FUN_SEL_V << RTC_CNTL_GPIO_PIN4_FUN_SEL_S) -#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0x0000000FU -#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 -/** RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W; bitpos: [19:16]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000FU -#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M (RTC_CNTL_GPIO_PIN3_FUN_SEL_V << RTC_CNTL_GPIO_PIN3_FUN_SEL_S) -#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0x0000000FU -#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 -/** RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W; bitpos: [23:20]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000FU -#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M (RTC_CNTL_GPIO_PIN2_FUN_SEL_V << RTC_CNTL_GPIO_PIN2_FUN_SEL_S) -#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0x0000000FU -#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 -/** RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W; bitpos: [27:24]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000FU -#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M (RTC_CNTL_GPIO_PIN1_FUN_SEL_V << RTC_CNTL_GPIO_PIN1_FUN_SEL_S) -#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0x0000000FU -#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 -/** RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W; bitpos: [31:28]; default: 0; - * Need add description - */ -#define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000FU -#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M (RTC_CNTL_GPIO_PIN0_FUN_SEL_V << RTC_CNTL_GPIO_PIN0_FUN_SEL_S) -#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0x0000000FU -#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 - -/** RTC_CNTL_DBG_SAR_SEL_REG register - * register description - */ -#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x150) -/** RTC_CNTL_SAR_DEBUG_SEL : R/W; bitpos: [31:27]; default: 0; - * Need add description - */ -#define RTC_CNTL_SAR_DEBUG_SEL 0x0000001FU -#define RTC_CNTL_SAR_DEBUG_SEL_M (RTC_CNTL_SAR_DEBUG_SEL_V << RTC_CNTL_SAR_DEBUG_SEL_S) -#define RTC_CNTL_SAR_DEBUG_SEL_V 0x0000001FU -#define RTC_CNTL_SAR_DEBUG_SEL_S 27 - -/** RTC_CNTL_PG_CTRL_REG register - * register description - */ -#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x154) -/** RTC_CNTL_POWER_GLITCH_DSENSE : R/W; bitpos: [27:26]; default: 0; - * Need add description - */ -#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003U -#define RTC_CNTL_POWER_GLITCH_DSENSE_M (RTC_CNTL_POWER_GLITCH_DSENSE_V << RTC_CNTL_POWER_GLITCH_DSENSE_S) -#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x00000003U -#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 -/** RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (RTC_CNTL_POWER_GLITCH_FORCE_PD_V << RTC_CNTL_POWER_GLITCH_FORCE_PD_S) -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x00000001U -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 -/** RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W; bitpos: [29]; default: 0; - * Need add description - */ -#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (RTC_CNTL_POWER_GLITCH_FORCE_PU_V << RTC_CNTL_POWER_GLITCH_FORCE_PU_S) -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x00000001U -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 -/** RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V << RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S) -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x00000001U -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 -/** RTC_CNTL_POWER_GLITCH_EN : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) -#define RTC_CNTL_POWER_GLITCH_EN_M (RTC_CNTL_POWER_GLITCH_EN_V << RTC_CNTL_POWER_GLITCH_EN_S) -#define RTC_CNTL_POWER_GLITCH_EN_V 0x00000001U -#define RTC_CNTL_POWER_GLITCH_EN_S 31 - -/** RTC_CNTL_DCDC_CTRL0_REG register - * register description - */ -#define RTC_CNTL_DCDC_CTRL0_REG (DR_REG_RTCCNTL_BASE + 0x158) -/** RTC_CNTL_VSET_DCDC_VALUE : RO; bitpos: [4:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_VALUE 0x0000001FU -#define RTC_CNTL_VSET_DCDC_VALUE_M (RTC_CNTL_VSET_DCDC_VALUE_V << RTC_CNTL_VSET_DCDC_VALUE_S) -#define RTC_CNTL_VSET_DCDC_VALUE_V 0x0000001FU -#define RTC_CNTL_VSET_DCDC_VALUE_S 0 -/** RTC_CNTL_POWER_GOOD_DCDC : RO; bitpos: [5]; default: 1; - * Need add description - */ -#define RTC_CNTL_POWER_GOOD_DCDC (BIT(5)) -#define RTC_CNTL_POWER_GOOD_DCDC_M (RTC_CNTL_POWER_GOOD_DCDC_V << RTC_CNTL_POWER_GOOD_DCDC_S) -#define RTC_CNTL_POWER_GOOD_DCDC_V 0x00000001U -#define RTC_CNTL_POWER_GOOD_DCDC_S 5 -/** RTC_CNTL_PMU_MODE : R/W; bitpos: [20:19]; default: 0; - * Need add description - */ -#define RTC_CNTL_PMU_MODE 0x00000003U -#define RTC_CNTL_PMU_MODE_M (RTC_CNTL_PMU_MODE_V << RTC_CNTL_PMU_MODE_S) -#define RTC_CNTL_PMU_MODE_V 0x00000003U -#define RTC_CNTL_PMU_MODE_S 19 -/** RTC_CNTL_RAMPLEVEL_DCDC : R/W; bitpos: [21]; default: 0; - * Need add description - */ -#define RTC_CNTL_RAMPLEVEL_DCDC (BIT(21)) -#define RTC_CNTL_RAMPLEVEL_DCDC_M (RTC_CNTL_RAMPLEVEL_DCDC_V << RTC_CNTL_RAMPLEVEL_DCDC_S) -#define RTC_CNTL_RAMPLEVEL_DCDC_V 0x00000001U -#define RTC_CNTL_RAMPLEVEL_DCDC_S 21 -/** RTC_CNTL_RAMP_DCDC : R/W; bitpos: [22]; default: 0; - * Need add description - */ -#define RTC_CNTL_RAMP_DCDC (BIT(22)) -#define RTC_CNTL_RAMP_DCDC_M (RTC_CNTL_RAMP_DCDC_V << RTC_CNTL_RAMP_DCDC_S) -#define RTC_CNTL_RAMP_DCDC_V 0x00000001U -#define RTC_CNTL_RAMP_DCDC_S 22 -/** RTC_CNTL_DCM2ENB_DCDC : R/W; bitpos: [23]; default: 0; - * Need add description - */ -#define RTC_CNTL_DCM2ENB_DCDC (BIT(23)) -#define RTC_CNTL_DCM2ENB_DCDC_M (RTC_CNTL_DCM2ENB_DCDC_V << RTC_CNTL_DCM2ENB_DCDC_S) -#define RTC_CNTL_DCM2ENB_DCDC_V 0x00000001U -#define RTC_CNTL_DCM2ENB_DCDC_S 23 -/** RTC_CNTL_DCMLEVEL_DCDC : R/W; bitpos: [25:24]; default: 0; - * Need add description - */ -#define RTC_CNTL_DCMLEVEL_DCDC 0x00000003U -#define RTC_CNTL_DCMLEVEL_DCDC_M (RTC_CNTL_DCMLEVEL_DCDC_V << RTC_CNTL_DCMLEVEL_DCDC_S) -#define RTC_CNTL_DCMLEVEL_DCDC_V 0x00000003U -#define RTC_CNTL_DCMLEVEL_DCDC_S 24 -/** RTC_CNTL_FSW_DCDC : R/W; bitpos: [28:26]; default: 0; - * Need add description - */ -#define RTC_CNTL_FSW_DCDC 0x00000007U -#define RTC_CNTL_FSW_DCDC_M (RTC_CNTL_FSW_DCDC_V << RTC_CNTL_FSW_DCDC_S) -#define RTC_CNTL_FSW_DCDC_V 0x00000007U -#define RTC_CNTL_FSW_DCDC_S 26 -/** RTC_CNTL_CCM_DCDC : R/W; bitpos: [29]; default: 0; - * Need add description - */ -#define RTC_CNTL_CCM_DCDC (BIT(29)) -#define RTC_CNTL_CCM_DCDC_M (RTC_CNTL_CCM_DCDC_V << RTC_CNTL_CCM_DCDC_S) -#define RTC_CNTL_CCM_DCDC_V 0x00000001U -#define RTC_CNTL_CCM_DCDC_S 29 -/** RTC_CNTL_SSTIME_DCDC : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define RTC_CNTL_SSTIME_DCDC (BIT(30)) -#define RTC_CNTL_SSTIME_DCDC_M (RTC_CNTL_SSTIME_DCDC_V << RTC_CNTL_SSTIME_DCDC_S) -#define RTC_CNTL_SSTIME_DCDC_V 0x00000001U -#define RTC_CNTL_SSTIME_DCDC_S 30 -/** RTC_CNTL_POCPENB_DCDC : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_POCPENB_DCDC (BIT(31)) -#define RTC_CNTL_POCPENB_DCDC_M (RTC_CNTL_POCPENB_DCDC_V << RTC_CNTL_POCPENB_DCDC_S) -#define RTC_CNTL_POCPENB_DCDC_V 0x00000001U -#define RTC_CNTL_POCPENB_DCDC_S 31 - -/** RTC_CNTL_DCDC_CTRL1_REG register - * register description - */ -#define RTC_CNTL_DCDC_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x15c) -/** RTC_CNTL_DCDC_MODE_SLP : R/W; bitpos: [25:23]; default: 4; - * Need add description - */ -#define RTC_CNTL_DCDC_MODE_SLP 0x00000007U -#define RTC_CNTL_DCDC_MODE_SLP_M (RTC_CNTL_DCDC_MODE_SLP_V << RTC_CNTL_DCDC_MODE_SLP_S) -#define RTC_CNTL_DCDC_MODE_SLP_V 0x00000007U -#define RTC_CNTL_DCDC_MODE_SLP_S 23 -/** RTC_CNTL_DCDC_MODE_MONITOR : R/W; bitpos: [28:26]; default: 4; - * Need add description - */ -#define RTC_CNTL_DCDC_MODE_MONITOR 0x00000007U -#define RTC_CNTL_DCDC_MODE_MONITOR_M (RTC_CNTL_DCDC_MODE_MONITOR_V << RTC_CNTL_DCDC_MODE_MONITOR_S) -#define RTC_CNTL_DCDC_MODE_MONITOR_V 0x00000007U -#define RTC_CNTL_DCDC_MODE_MONITOR_S 26 -/** RTC_CNTL_DCDC_MODE_IDLE : R/W; bitpos: [31:29]; default: 4; - * Need add description - */ -#define RTC_CNTL_DCDC_MODE_IDLE 0x00000007U -#define RTC_CNTL_DCDC_MODE_IDLE_M (RTC_CNTL_DCDC_MODE_IDLE_V << RTC_CNTL_DCDC_MODE_IDLE_S) -#define RTC_CNTL_DCDC_MODE_IDLE_V 0x00000007U -#define RTC_CNTL_DCDC_MODE_IDLE_S 29 - -/** RTC_CNTL_DCDC_CTRL2_REG register - * register description - */ -#define RTC_CNTL_DCDC_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x160) -/** RTC_CNTL_VSET_DCDC_TARGET_VALUE1 : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1 0x0000001FU -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_M (RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V << RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S) -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_V 0x0000001FU -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE1_S 0 -/** RTC_CNTL_VSET_DCDC_TARGET_VALUE0 : R/W; bitpos: [9:5]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0 0x0000001FU -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_M (RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V << RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S) -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_V 0x0000001FU -#define RTC_CNTL_VSET_DCDC_TARGET_VALUE0_S 5 -/** RTC_CNTL_VSET_DCDC_INIT_VALUE : R/W; bitpos: [14:10]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_INIT_VALUE 0x0000001FU -#define RTC_CNTL_VSET_DCDC_INIT_VALUE_M (RTC_CNTL_VSET_DCDC_INIT_VALUE_V << RTC_CNTL_VSET_DCDC_INIT_VALUE_S) -#define RTC_CNTL_VSET_DCDC_INIT_VALUE_V 0x0000001FU -#define RTC_CNTL_VSET_DCDC_INIT_VALUE_S 10 -/** RTC_CNTL_VSET_DCDC_INIT : WO; bitpos: [15]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_INIT (BIT(15)) -#define RTC_CNTL_VSET_DCDC_INIT_M (RTC_CNTL_VSET_DCDC_INIT_V << RTC_CNTL_VSET_DCDC_INIT_S) -#define RTC_CNTL_VSET_DCDC_INIT_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_INIT_S 15 -/** RTC_CNTL_VSET_DCDC_FIX : R/W; bitpos: [16]; default: 1; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_FIX (BIT(16)) -#define RTC_CNTL_VSET_DCDC_FIX_M (RTC_CNTL_VSET_DCDC_FIX_V << RTC_CNTL_VSET_DCDC_FIX_S) -#define RTC_CNTL_VSET_DCDC_FIX_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_FIX_S 16 -/** RTC_CNTL_VSET_DCDC_STEP : R/W; bitpos: [21:17]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_STEP 0x0000001FU -#define RTC_CNTL_VSET_DCDC_STEP_M (RTC_CNTL_VSET_DCDC_STEP_V << RTC_CNTL_VSET_DCDC_STEP_S) -#define RTC_CNTL_VSET_DCDC_STEP_V 0x0000001FU -#define RTC_CNTL_VSET_DCDC_STEP_S 17 -/** RTC_CNTL_VSET_DCDC_GAP : R/W; bitpos: [26:22]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_GAP 0x0000001FU -#define RTC_CNTL_VSET_DCDC_GAP_M (RTC_CNTL_VSET_DCDC_GAP_V << RTC_CNTL_VSET_DCDC_GAP_S) -#define RTC_CNTL_VSET_DCDC_GAP_V 0x0000001FU -#define RTC_CNTL_VSET_DCDC_GAP_S 22 -/** RTC_CNTL_VSET_DCDC_SEL_HW_SW : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW (BIT(27)) -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_M (RTC_CNTL_VSET_DCDC_SEL_HW_SW_V << RTC_CNTL_VSET_DCDC_SEL_HW_SW_S) -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_SEL_HW_SW_S 27 -/** RTC_CNTL_VSET_DCDC_SW_SEL : R/W; bitpos: [28]; default: 0; - * Need add description - */ -#define RTC_CNTL_VSET_DCDC_SW_SEL (BIT(28)) -#define RTC_CNTL_VSET_DCDC_SW_SEL_M (RTC_CNTL_VSET_DCDC_SW_SEL_V << RTC_CNTL_VSET_DCDC_SW_SEL_S) -#define RTC_CNTL_VSET_DCDC_SW_SEL_V 0x00000001U -#define RTC_CNTL_VSET_DCDC_SW_SEL_S 28 - -/** RTC_CNTL_RC32K_CTRL_REG register - * register description - */ -#define RTC_CNTL_RC32K_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x164) -/** RTC_CNTL_RC32K_DFREQ : R/W; bitpos: [30:21]; default: 511; - * Need add description - */ -#define RTC_CNTL_RC32K_DFREQ 0x000003FFU -#define RTC_CNTL_RC32K_DFREQ_M (RTC_CNTL_RC32K_DFREQ_V << RTC_CNTL_RC32K_DFREQ_S) -#define RTC_CNTL_RC32K_DFREQ_V 0x000003FFU -#define RTC_CNTL_RC32K_DFREQ_S 21 -/** RTC_CNTL_RC32K_XPD : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_RC32K_XPD (BIT(31)) -#define RTC_CNTL_RC32K_XPD_M (RTC_CNTL_RC32K_XPD_V << RTC_CNTL_RC32K_XPD_S) -#define RTC_CNTL_RC32K_XPD_V 0x00000001U -#define RTC_CNTL_RC32K_XPD_S 31 - -/** RTC_CNTL_PLL8M_REG register - * register description - */ -#define RTC_CNTL_PLL8M_REG (DR_REG_RTCCNTL_BASE + 0x168) -/** RTC_CNTL_CKREF_PLL8M_SEL : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define RTC_CNTL_CKREF_PLL8M_SEL (BIT(30)) -#define RTC_CNTL_CKREF_PLL8M_SEL_M (RTC_CNTL_CKREF_PLL8M_SEL_V << RTC_CNTL_CKREF_PLL8M_SEL_S) -#define RTC_CNTL_CKREF_PLL8M_SEL_V 0x00000001U -#define RTC_CNTL_CKREF_PLL8M_SEL_S 30 -/** RTC_CNTL_XPD_PLL8M : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define RTC_CNTL_XPD_PLL8M (BIT(31)) -#define RTC_CNTL_XPD_PLL8M_M (RTC_CNTL_XPD_PLL8M_V << RTC_CNTL_XPD_PLL8M_S) -#define RTC_CNTL_XPD_PLL8M_V 0x00000001U -#define RTC_CNTL_XPD_PLL8M_S 31 - -/** RTC_CNTL_DATE_REG register - * register description - */ -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1fc) -/** RTC_CNTL_DATE : R/W; bitpos: [27:0]; default: 34640480; - * Need add description - */ -#define RTC_CNTL_DATE 0x0FFFFFFFU -#define RTC_CNTL_DATE_M (RTC_CNTL_DATE_V << RTC_CNTL_DATE_S) -#define RTC_CNTL_DATE_V 0x0FFFFFFFU -#define RTC_CNTL_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_struct.h b/components/soc/esp32h4/include/rev2/soc/rtc_cntl_struct.h deleted file mode 100644 index ac7dc18000..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/rtc_cntl_struct.h +++ /dev/null @@ -1,2984 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of rtc_options0 register - * register description - */ -typedef union { - struct { - /** sw_stall_appcpu_c0 : R/W; bitpos: [1:0]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP - * CPU - */ - uint32_t sw_stall_appcpu_c0:2; - /** sw_stall_procpu_c0 : R/W; bitpos: [3:2]; default: 0; - * {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO - * CPU - */ - uint32_t sw_stall_procpu_c0:2; - /** sw_appcpu_rst : WO; bitpos: [4]; default: 0; - * APP CPU SW reset - */ - uint32_t sw_appcpu_rst:1; - /** sw_procpu_rst : WO; bitpos: [5]; default: 0; - * PRO CPU SW reset - */ - uint32_t sw_procpu_rst:1; - /** bb_i2c_force_pd : R/W; bitpos: [6]; default: 0; - * BB_I2C force power down - */ - uint32_t bb_i2c_force_pd:1; - /** bb_i2c_force_pu : R/W; bitpos: [7]; default: 0; - * BB_I2C force power up - */ - uint32_t bb_i2c_force_pu:1; - /** bbpll_i2c_force_pd : R/W; bitpos: [8]; default: 0; - * BB_PLL _I2C force power down - */ - uint32_t bbpll_i2c_force_pd:1; - /** bbpll_i2c_force_pu : R/W; bitpos: [9]; default: 0; - * BB_PLL_I2C force power up - */ - uint32_t bbpll_i2c_force_pu:1; - /** bbpll_force_pd : R/W; bitpos: [10]; default: 0; - * BB_PLL force power down - */ - uint32_t bbpll_force_pd:1; - /** bbpll_force_pu : R/W; bitpos: [11]; default: 0; - * BB_PLL force power up - */ - uint32_t bbpll_force_pu:1; - /** xtl_force_pd : R/W; bitpos: [12]; default: 0; - * crystall force power down - */ - uint32_t xtl_force_pd:1; - /** xtl_force_pu : R/W; bitpos: [13]; default: 1; - * crystall force power up - */ - uint32_t xtl_force_pu:1; - /** xtl_en_wait : R/W; bitpos: [17:14]; default: 2; - * wait bias_sleep and current source wakeup - */ - uint32_t xtl_en_wait:4; - /** xpd_rfpll : R/W; bitpos: [18]; default: 0; - * Need add description - */ - uint32_t xpd_rfpll:1; - /** xpd_rfpll_force : R/W; bitpos: [19]; default: 0; - * Need add description - */ - uint32_t xpd_rfpll_force:1; - /** xtl_ext_ctr_sel : R/W; bitpos: [22:20]; default: 0; - * Need add description - */ - uint32_t xtl_ext_ctr_sel:3; - /** xtl_force_iso : R/W; bitpos: [23]; default: 0; - * Need add description - */ - uint32_t xtl_force_iso:1; - /** pll_force_iso : R/W; bitpos: [24]; default: 0; - * Need add description - */ - uint32_t pll_force_iso:1; - /** analog_force_iso : R/W; bitpos: [25]; default: 0; - * Need add description - */ - uint32_t analog_force_iso:1; - /** xtl_force_noiso : R/W; bitpos: [26]; default: 1; - * Need add description - */ - uint32_t xtl_force_noiso:1; - /** pll_force_noiso : R/W; bitpos: [27]; default: 1; - * Need add description - */ - uint32_t pll_force_noiso:1; - /** analog_force_noiso : R/W; bitpos: [28]; default: 1; - * Need add description - */ - uint32_t analog_force_noiso:1; - /** dg_wrap_force_rst : R/W; bitpos: [29]; default: 0; - * digital wrap force reset in deep sleep - */ - uint32_t dg_wrap_force_rst:1; - /** dg_wrap_force_norst : R/W; bitpos: [30]; default: 0; - * digital core force no reset in deep sleep - */ - uint32_t dg_wrap_force_norst:1; - /** sw_sys_rst : WO; bitpos: [31]; default: 0; - * SW system reset - */ - uint32_t sw_sys_rst:1; - }; - uint32_t val; -} rtc_cntl_options0_reg_t; - -/** Type of rtc_slp_timer0 register - * register description - */ -typedef union { - struct { - /** slp_val_lo : R/W; bitpos: [31:0]; default: 0; - * RTC sleep timer low 32 bits - */ - uint32_t slp_val_lo:32; - }; - uint32_t val; -} rtc_cntl_slp_timer0_reg_t; - -/** Type of rtc_slp_timer1 register - * register description - */ -typedef union { - struct { - /** slp_val_hi : R/W; bitpos: [15:0]; default: 0; - * RTC sleep timer high 16 bits - */ - uint32_t slp_val_hi:16; - /** main_timer_alarm_en : WO; bitpos: [16]; default: 0; - * timer alarm enable bit - */ - uint32_t main_timer_alarm_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} rtc_cntl_slp_timer1_reg_t; - -/** Type of rtc_time_update register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** timer_sys_stall : R/W; bitpos: [27]; default: 0; - * Enable to record system stall time - */ - uint32_t timer_sys_stall:1; - /** timer_xtl_off : R/W; bitpos: [28]; default: 0; - * Enable to record 40M XTAL OFF time - */ - uint32_t timer_xtl_off:1; - /** timer_sys_rst : R/W; bitpos: [29]; default: 0; - * enable to record system reset time - */ - uint32_t timer_sys_rst:1; - uint32_t reserved_30:1; - /** update : WO; bitpos: [31]; default: 0; - * Set 1: to update register with RTC timer - */ - uint32_t update:1; - }; - uint32_t val; -} rtc_cntl_time_update_reg_t; - -/** Type of rtc_time_low0 register - * register description - */ -typedef union { - struct { - /** rtc_timer_value0_low : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ - uint32_t rtc_timer_value0_low:32; - }; - uint32_t val; -} rtc_cntl_time_low0_reg_t; - -/** Type of rtc_time_high0 register - * register description - */ -typedef union { - struct { - /** rtc_timer_value0_high : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ - uint32_t rtc_timer_value0_high:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} rtc_cntl_time_high0_reg_t; - -/** Type of rtc_state0 register - * register description - */ -typedef union { - struct { - /** rtc_sw_cpu_int : WO; bitpos: [0]; default: 0; - * rtc software interrupt to main cpu - */ - uint32_t rtc_sw_cpu_int:1; - /** rtc_slp_reject_cause_clr : WO; bitpos: [1]; default: 0; - * clear rtc sleep reject cause - */ - uint32_t rtc_slp_reject_cause_clr:1; - uint32_t reserved_2:20; - /** apb2rtc_bridge_sel : R/W; bitpos: [22]; default: 0; - * 1: APB to RTC using bridge, 0: APB to RTC using sync - */ - uint32_t apb2rtc_bridge_sel:1; - uint32_t reserved_23:5; - /** sdio_active_ind : RO; bitpos: [28]; default: 0; - * SDIO active indication - */ - uint32_t sdio_active_ind:1; - /** slp_wakeup : R/W; bitpos: [29]; default: 0; - * leep wakeup bit - */ - uint32_t slp_wakeup:1; - /** slp_reject : R/W; bitpos: [30]; default: 0; - * leep reject bit - */ - uint32_t slp_reject:1; - /** sleep_en : R/W; bitpos: [31]; default: 0; - * sleep enable bit - */ - uint32_t sleep_en:1; - }; - uint32_t val; -} rtc_cntl_state0_reg_t; - -/** Type of rtc_timer1 register - * register description - */ -typedef union { - struct { - /** cpu_stall_en : R/W; bitpos: [0]; default: 1; - * CPU stall enable bit - */ - uint32_t cpu_stall_en:1; - /** cpu_stall_wait : R/W; bitpos: [5:1]; default: 1; - * CPU stall wait cycles in fast_clk_rtc - */ - uint32_t cpu_stall_wait:5; - /** ck8m_wait : R/W; bitpos: [13:6]; default: 16; - * CK8M wait cycles in slow_clk_rtc - */ - uint32_t ck8m_wait:8; - /** xtl_buf_wait : R/W; bitpos: [23:14]; default: 80; - * XTAL wait cycles in slow_clk_rtc - */ - uint32_t xtl_buf_wait:10; - /** pll_buf_wait : R/W; bitpos: [31:24]; default: 40; - * PLL wait cycles in slow_clk_rtc - */ - uint32_t pll_buf_wait:8; - }; - uint32_t val; -} rtc_cntl_timer1_reg_t; - -/** Type of rtc_timer2 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** min_time_ck8m_off : R/W; bitpos: [31:24]; default: 1; - * minimal cycles in slow_clk_rtc for CK8M in power down state - */ - uint32_t min_time_ck8m_off:8; - }; - uint32_t val; -} rtc_cntl_timer2_reg_t; - -/** Type of rtc_timer3 register - * register description - */ -typedef union { - struct { - /** wifi_wait_timer : R/W; bitpos: [8:0]; default: 8; - * Need add description - */ - uint32_t wifi_wait_timer:9; - /** wifi_powerup_timer : R/W; bitpos: [15:9]; default: 5; - * Need add description - */ - uint32_t wifi_powerup_timer:7; - /** bt_wait_timer : R/W; bitpos: [24:16]; default: 8; - * Need add description - */ - uint32_t bt_wait_timer:9; - /** bt_powerup_timer : R/W; bitpos: [31:25]; default: 5; - * Need add description - */ - uint32_t bt_powerup_timer:7; - }; - uint32_t val; -} rtc_cntl_timer3_reg_t; - -/** Type of rtc_timer4 register - * register description - */ -typedef union { - struct { - /** cpu_top_wait_timer : R/W; bitpos: [8:0]; default: 8; - * Need add description - */ - uint32_t cpu_top_wait_timer:9; - /** cpu_top_powerup_timer : R/W; bitpos: [15:9]; default: 5; - * Need add description - */ - uint32_t cpu_top_powerup_timer:7; - /** dg_wrap_wait_timer : R/W; bitpos: [24:16]; default: 32; - * Need add description - */ - uint32_t dg_wrap_wait_timer:9; - /** dg_wrap_powerup_timer : R/W; bitpos: [31:25]; default: 8; - * Need add description - */ - uint32_t dg_wrap_powerup_timer:7; - }; - uint32_t val; -} rtc_cntl_timer4_reg_t; - -/** Type of rtc_timer5 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** min_slp_val : R/W; bitpos: [15:8]; default: 128; - * minimal sleep cycles in slow_clk_rtc - */ - uint32_t min_slp_val:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} rtc_cntl_timer5_reg_t; - -/** Type of rtc_timer6 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** dg_peri_wait_timer : R/W; bitpos: [24:16]; default: 8; - * Need add description - */ - uint32_t dg_peri_wait_timer:9; - /** dg_peri_powerup_timer : R/W; bitpos: [31:25]; default: 5; - * Need add description - */ - uint32_t dg_peri_powerup_timer:7; - }; - uint32_t val; -} rtc_cntl_timer6_reg_t; - -/** Type of rtc_ana_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** xpd_trx_force_pd : R/W; bitpos: [16]; default: 0; - * Need add description - */ - uint32_t xpd_trx_force_pd:1; - /** xpd_trx_force_pu : R/W; bitpos: [17]; default: 1; - * Need add description - */ - uint32_t xpd_trx_force_pu:1; - /** i2c_reset_por_force_pd : R/W; bitpos: [18]; default: 1; - * Need add description - */ - uint32_t i2c_reset_por_force_pd:1; - /** i2c_reset_por_force_pu : R/W; bitpos: [19]; default: 0; - * Need add description - */ - uint32_t i2c_reset_por_force_pu:1; - /** glitch_rst_en : R/W; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t glitch_rst_en:1; - uint32_t reserved_21:1; - /** peri_i2c_pu : R/W; bitpos: [22]; default: 1; - * PLLA force power up - */ - uint32_t peri_i2c_pu:1; - /** plla_force_pd : R/W; bitpos: [23]; default: 1; - * PLLA force power down - */ - uint32_t plla_force_pd:1; - /** plla_force_pu : R/W; bitpos: [24]; default: 0; - * PLLA force power up - */ - uint32_t plla_force_pu:1; - /** bbpll_cal_slp_start : R/W; bitpos: [25]; default: 0; - * start BBPLL calibration during sleep - */ - uint32_t bbpll_cal_slp_start:1; - /** pvtmon_pu : R/W; bitpos: [26]; default: 0; - * 1: PVTMON power up , otherwise power down - */ - uint32_t pvtmon_pu:1; - /** txrf_i2c_pu : R/W; bitpos: [27]; default: 0; - * 1: TXRF_I2C power up , otherwise power down - */ - uint32_t txrf_i2c_pu:1; - /** rfrx_pbus_pu : R/W; bitpos: [28]; default: 0; - * 1: RFRX_PBUS power up , otherwise power down - */ - uint32_t rfrx_pbus_pu:1; - uint32_t reserved_29:1; - /** ckgen_i2c_pu : R/W; bitpos: [30]; default: 0; - * 1: CKGEN_I2C power up , otherwise power down - */ - uint32_t ckgen_i2c_pu:1; - /** pll_i2c_pu : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t pll_i2c_pu:1; - }; - uint32_t val; -} rtc_cntl_ana_conf_reg_t; - -/** Type of rtc_reset_state register - * register description - */ -typedef union { - struct { - /** reset_cause_procpu : RO; bitpos: [5:0]; default: 0; - * reset cause of PRO CPU - */ - uint32_t reset_cause_procpu:6; - /** reset_cause_appcpu : RO; bitpos: [11:6]; default: 0; - * reset cause of APP CPU - */ - uint32_t reset_cause_appcpu:6; - /** stat_vector_sel_appcpu : R/W; bitpos: [12]; default: 1; - * APP CPU state vector sel - */ - uint32_t stat_vector_sel_appcpu:1; - /** stat_vector_sel_procpu : R/W; bitpos: [13]; default: 1; - * PRO CPU state vector sel - */ - uint32_t stat_vector_sel_procpu:1; - /** all_reset_flag_procpu : RO; bitpos: [14]; default: 0; - * PRO CPU reset_flag - */ - uint32_t all_reset_flag_procpu:1; - /** all_reset_flag_appcpu : RO; bitpos: [15]; default: 0; - * APP CPU reset flag - */ - uint32_t all_reset_flag_appcpu:1; - /** all_reset_flag_clr_procpu : WO; bitpos: [16]; default: 0; - * clear PRO CPU reset_flag - */ - uint32_t all_reset_flag_clr_procpu:1; - /** all_reset_flag_clr_appcpu : WO; bitpos: [17]; default: 0; - * clear APP CPU reset flag - */ - uint32_t all_reset_flag_clr_appcpu:1; - /** ocd_halt_on_reset_appcpu : R/W; bitpos: [18]; default: 0; - * APPCPU OcdHaltOnReset - */ - uint32_t ocd_halt_on_reset_appcpu:1; - /** ocd_halt_on_reset_procpu : R/W; bitpos: [19]; default: 0; - * PROCPU OcdHaltOnReset - */ - uint32_t ocd_halt_on_reset_procpu:1; - /** jtag_reset_flag_procpu : RO; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t jtag_reset_flag_procpu:1; - /** jtag_reset_flag_appcpu : RO; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t jtag_reset_flag_appcpu:1; - /** jtag_reset_flag_clr_procpu : WO; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t jtag_reset_flag_clr_procpu:1; - /** jtag_reset_flag_clr_appcpu : WO; bitpos: [23]; default: 0; - * Need add description - */ - uint32_t jtag_reset_flag_clr_appcpu:1; - /** rtc_dreset_mask_appcpu : R/W; bitpos: [24]; default: 0; - * Need add description - */ - uint32_t rtc_dreset_mask_appcpu:1; - /** rtc_dreset_mask_procpu : R/W; bitpos: [25]; default: 0; - * Need add description - */ - uint32_t rtc_dreset_mask_procpu:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} rtc_cntl_reset_state_reg_t; - -/** Type of rtc_wakeup_state register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** rtc_wakeup_ena : R/W; bitpos: [31:13]; default: 12; - * wakeup enable bitmap - */ - uint32_t rtc_wakeup_ena:19; - }; - uint32_t val; -} rtc_cntl_wakeup_state_reg_t; - -/** Type of int_ena register - * register description - */ -typedef union { - struct { - /** slp_wakeup : R/W; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - uint32_t slp_wakeup:1; - /** slp_reject : R/W; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - uint32_t slp_reject:1; - uint32_t reserved_2:1; - /** rtc_wdt : R/W; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - uint32_t rtc_wdt:1; - uint32_t reserved_4:5; - /** rtc_brown_out : R/W; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - uint32_t rtc_brown_out:1; - /** rtc_main_timer : R/W; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - uint32_t rtc_main_timer:1; - uint32_t reserved_11:4; - /** rtc_swd : R/W; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - uint32_t rtc_swd:1; - /** rtc_xtal32k_dead : R/W; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - uint32_t rtc_xtal32k_dead:1; - uint32_t reserved_17:2; - /** rtc_glitch_det : R/W; bitpos: [19]; default: 0; - * enbale gitch det interrupt - */ - uint32_t rtc_glitch_det:1; - /** rtc_bbpll_cal : R/W; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_bbpll_cal:1; - /** rtc_ble_compare_wake : RW; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ble_compare_wake:1; - /** vset_dcdc_done : R/W; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_cntl_int_ena_reg_t; - -/** Type of int_raw register - * register description - */ -typedef union { - struct { - /** slp_wakeup : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt raw - */ - uint32_t slp_wakeup:1; - /** slp_reject : RO; bitpos: [1]; default: 0; - * sleep reject interrupt raw - */ - uint32_t slp_reject:1; - uint32_t reserved_2:1; - /** rtc_wdt : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt raw - */ - uint32_t rtc_wdt:1; - uint32_t reserved_4:5; - /** rtc_brown_out : RO; bitpos: [9]; default: 0; - * brown out interrupt raw - */ - uint32_t rtc_brown_out:1; - /** rtc_main_timer : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt raw - */ - uint32_t rtc_main_timer:1; - uint32_t reserved_11:4; - /** rtc_swd : RO; bitpos: [15]; default: 0; - * super watch dog interrupt raw - */ - uint32_t rtc_swd:1; - /** rtc_xtal32k_dead : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt raw - */ - uint32_t rtc_xtal32k_dead:1; - uint32_t reserved_17:2; - /** rtc_glitch_det : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt_raw - */ - uint32_t rtc_glitch_det:1; - /** rtc_bbpll_cal : RO; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_bbpll_cal:1; - /** rtc_ble_compare_wake : RO; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ble_compare_wake:1; - /** vset_dcdc_done : RO; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_cntl_int_raw_reg_t; - -/** Type of int_st register - * register description - */ -typedef union { - struct { - /** slp_wakeup : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt state - */ - uint32_t slp_wakeup:1; - /** slp_reject : RO; bitpos: [1]; default: 0; - * sleep reject interrupt state - */ - uint32_t slp_reject:1; - uint32_t reserved_2:1; - /** rtc_wdt : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt state - */ - uint32_t rtc_wdt:1; - uint32_t reserved_4:5; - /** rtc_brown_out : RO; bitpos: [9]; default: 0; - * brown out interrupt state - */ - uint32_t rtc_brown_out:1; - /** rtc_main_timer : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt state - */ - uint32_t rtc_main_timer:1; - uint32_t reserved_11:4; - /** rtc_swd : RO; bitpos: [15]; default: 0; - * super watch dog interrupt state - */ - uint32_t rtc_swd:1; - /** rtc_xtal32k_dead : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt state - */ - uint32_t rtc_xtal32k_dead:1; - uint32_t reserved_17:2; - /** rtc_glitch_det : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt state - */ - uint32_t rtc_glitch_det:1; - /** rtc_bbpll_cal : RO; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_bbpll_cal:1; - /** rtc_ble_compare_wake : RO; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ble_compare_wake:1; - /** vset_dcdc_done : RO; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_cntl_int_st_reg_t; - -/** Type of int_clr register - * register description - */ -typedef union { - struct { - /** slp_wakeup : WO; bitpos: [0]; default: 0; - * Clear sleep wakeup interrupt state - */ - uint32_t slp_wakeup:1; - /** slp_reject : WO; bitpos: [1]; default: 0; - * Clear sleep reject interrupt state - */ - uint32_t slp_reject:1; - uint32_t reserved_2:1; - /** rtc_wdt : WO; bitpos: [3]; default: 0; - * Clear RTC WDT interrupt state - */ - uint32_t rtc_wdt:1; - uint32_t reserved_4:5; - /** rtc_brown_out : WO; bitpos: [9]; default: 0; - * Clear brown out interrupt state - */ - uint32_t rtc_brown_out:1; - /** rtc_main_timer : WO; bitpos: [10]; default: 0; - * Clear RTC main timer interrupt state - */ - uint32_t rtc_main_timer:1; - uint32_t reserved_11:4; - /** rtc_swd : WO; bitpos: [15]; default: 0; - * Clear super watch dog interrupt state - */ - uint32_t rtc_swd:1; - /** rtc_xtal32k_dead : WO; bitpos: [16]; default: 0; - * Clear RTC WDT interrupt state - */ - uint32_t rtc_xtal32k_dead:1; - uint32_t reserved_17:2; - /** rtc_glitch_det : WO; bitpos: [19]; default: 0; - * Clear glitch det interrupt state - */ - uint32_t rtc_glitch_det:1; - /** rtc_bbpll_cal : WO; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_bbpll_cal:1; - /** rtc_ble_compare_wake : WO; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ble_compare_wake:1; - /** vset_dcdc_done : WO; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_cntl_int_clr_reg_t; - -/** Type of register - * register description - */ -typedef union { - struct { - /** rtc_scratch : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t rtc_scratch:32; - }; - uint32_t val; -} rtc_cntl_store_reg_t; - - -/** Type of rtc_ext_xtl_conf register - * register description - */ -typedef union { - struct { - /** xtal32k_wdt_en : R/W; bitpos: [0]; default: 0; - * xtal 32k watch dog enable - */ - uint32_t xtal32k_wdt_en:1; - /** xtal32k_wdt_clk_fo : R/W; bitpos: [1]; default: 0; - * xtal 32k watch dog clock force on - */ - uint32_t xtal32k_wdt_clk_fo:1; - /** xtal32k_wdt_reset : R/W; bitpos: [2]; default: 0; - * xtal 32k watch dog sw reset - */ - uint32_t xtal32k_wdt_reset:1; - /** xtal32k_ext_clk_fo : R/W; bitpos: [3]; default: 0; - * xtal 32k external xtal clock force on - */ - uint32_t xtal32k_ext_clk_fo:1; - /** xtal32k_auto_backup : R/W; bitpos: [4]; default: 0; - * xtal 32k switch to back up clock when xtal is dead - */ - uint32_t xtal32k_auto_backup:1; - /** xtal32k_auto_restart : R/W; bitpos: [5]; default: 0; - * xtal 32k restart xtal when xtal is dead - */ - uint32_t xtal32k_auto_restart:1; - /** xtal32k_auto_return : R/W; bitpos: [6]; default: 0; - * xtal 32k switch back xtal when xtal is restarted - */ - uint32_t xtal32k_auto_return:1; - /** xtal32k_xpd_force : R/W; bitpos: [7]; default: 1; - * Xtal 32k xpd control by sw or fsm - */ - uint32_t xtal32k_xpd_force:1; - /** enckinit_xtal_32k : R/W; bitpos: [8]; default: 0; - * apply an internal clock to help xtal 32k to start - */ - uint32_t enckinit_xtal_32k:1; - /** dbuf_xtal_32k : R/W; bitpos: [9]; default: 0; - * 0: single-end buffer 1: differential buffer - */ - uint32_t dbuf_xtal_32k:1; - /** dgm_xtal_32k : R/W; bitpos: [12:10]; default: 3; - * xtal_32k gm control - */ - uint32_t dgm_xtal_32k:3; - /** dres_xtal_32k : R/W; bitpos: [15:13]; default: 3; - * DRES_XTAL_32K - */ - uint32_t dres_xtal_32k:3; - /** xpd_xtal_32k : R/W; bitpos: [16]; default: 0; - * XPD_XTAL_32K - */ - uint32_t xpd_xtal_32k:1; - /** dac_xtal_32k : R/W; bitpos: [19:17]; default: 3; - * DAC_XTAL_32K - */ - uint32_t dac_xtal_32k:3; - /** rtc_wdt_state : RO; bitpos: [22:20]; default: 0; - * state of 32k_wdt - */ - uint32_t rtc_wdt_state:3; - /** rtc_xtal32k_gpio_sel : R/W; bitpos: [23]; default: 0; - * XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C - */ - uint32_t rtc_xtal32k_gpio_sel:1; - uint32_t reserved_24:6; - /** ctr_lv : R/W; bitpos: [30]; default: 0; - * 0: power down XTAL at high level, 1: power down XTAL at low level - */ - uint32_t ctr_lv:1; - /** ctr_en : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t ctr_en:1; - }; - uint32_t val; -} rtc_cntl_ext_xtl_conf_reg_t; - -/** Type of rtc_ext_wakeup_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** gpio_wakeup_filter : R/W; bitpos: [31]; default: 0; - * enable filter for gpio wakeup event - */ - uint32_t gpio_wakeup_filter:1; - }; - uint32_t val; -} rtc_cntl_ext_wakeup_conf_reg_t; - -/** Type of rtc_slp_reject_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** rtc_sleep_reject_ena : R/W; bitpos: [29:11]; default: 0; - * sleep reject enable - */ - uint32_t rtc_sleep_reject_ena:19; - /** light_slp_reject_en : R/W; bitpos: [30]; default: 0; - * enable reject for light sleep - */ - uint32_t light_slp_reject_en:1; - /** deep_slp_reject_en : R/W; bitpos: [31]; default: 0; - * enable reject for deep sleep - */ - uint32_t deep_slp_reject_en:1; - }; - uint32_t val; -} rtc_cntl_slp_reject_conf_reg_t; - -/** Type of rtc_cpu_period_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:29; - /** cpusel_conf : R/W; bitpos: [29]; default: 0; - * CPU sel option - */ - uint32_t cpusel_conf:1; - /** cpuperiod_sel : R/W; bitpos: [31:30]; default: 0; - * Need add description - */ - uint32_t cpuperiod_sel:2; - }; - uint32_t val; -} rtc_cntl_cpu_period_conf_reg_t; - -/** Type of rtc_clk_conf register - * register description - */ -typedef union { - struct { - /** rtc_ble_tmr_rst : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t rtc_ble_tmr_rst:1; - /** efuse_clk_force_gating : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t efuse_clk_force_gating:1; - /** efuse_clk_force_nogating : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t efuse_clk_force_nogating:1; - /** ck8m_div_sel_vld : R/W; bitpos: [3]; default: 1; - * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set - * vld to actually switch the clk - */ - uint32_t ck8m_div_sel_vld:1; - /** dig_xtal32k_en : R/W; bitpos: [4]; default: 0; - * enable CK_XTAL_32K for digital core (no relationship with RTC core) - */ - uint32_t dig_xtal32k_en:1; - /** dig_rc32k_en : R/W; bitpos: [5]; default: 1; - * enable RC32K for digital core (no relationship with RTC core) - */ - uint32_t dig_rc32k_en:1; - /** dig_clk8m_en : R/W; bitpos: [6]; default: 0; - * enable CK8M for digital core (no relationship with RTC core) - */ - uint32_t dig_clk8m_en:1; - /** rtc_ble_timer_sel : R/W; bitpos: [7]; default: 0; - * Need add description - */ - uint32_t rtc_ble_timer_sel:1; - uint32_t reserved_8:2; - /** ck8m_div_sel : R/W; bitpos: [12:10]; default: 3; - * divider = reg_ck8m_div_sel + 1 - */ - uint32_t ck8m_div_sel:3; - /** xtal_force_nogating : R/W; bitpos: [13]; default: 0; - * XTAL force no gating during sleep - */ - uint32_t xtal_force_nogating:1; - /** ck8m_force_nogating : R/W; bitpos: [14]; default: 0; - * CK8M force no gating during sleep - */ - uint32_t ck8m_force_nogating:1; - /** ck8m_dfreq : R/W; bitpos: [24:15]; default: 600; - * CK8M_DFREQ - */ - uint32_t ck8m_dfreq:10; - /** ck8m_force_pd : R/W; bitpos: [25]; default: 0; - * CK8M force power down - */ - uint32_t ck8m_force_pd:1; - /** ck8m_force_pu : R/W; bitpos: [26]; default: 0; - * CK8M force power up - */ - uint32_t ck8m_force_pu:1; - /** xtal_global_force_gating : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t xtal_global_force_gating:1; - /** xtal_global_force_nogating : R/W; bitpos: [28]; default: 1; - * Need add description - */ - uint32_t xtal_global_force_nogating:1; - /** fast_clk_rtc_sel : R/W; bitpos: [29]; default: 0; - * fast_clk_rtc sel. 0: XTAL div 2, 1: CK8M - */ - uint32_t fast_clk_rtc_sel:1; - /** ana_clk_rtc_sel : R/W; bitpos: [31:30]; default: 0; - * Need add description - */ - uint32_t ana_clk_rtc_sel:2; - }; - uint32_t val; -} rtc_cntl_clk_conf_reg_t; - -/** Type of rtc_slow_clk_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:19; - /** rtc_ana_clk_pd_slp : R/W; bitpos: [19]; default: 0; - * Need add description - */ - uint32_t rtc_ana_clk_pd_slp:1; - /** rtc_ana_clk_pd_monitor : R/W; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_ana_clk_pd_monitor:1; - /** rtc_ana_clk_pd_idle : R/W; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ana_clk_pd_idle:1; - /** rtc_ana_clk_div_vld : R/W; bitpos: [22]; default: 1; - * used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to - * actually switch the clk - */ - uint32_t rtc_ana_clk_div_vld:1; - /** rtc_ana_clk_div : R/W; bitpos: [30:23]; default: 0; - * Need add description - */ - uint32_t rtc_ana_clk_div:8; - /** slow_clk_next_edge : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t slow_clk_next_edge:1; - }; - uint32_t val; -} rtc_cntl_slow_clk_conf_reg_t; - -/** Type of rtc_sdio_conf register - * register description - */ -typedef union { - struct { - /** sdio_timer_target : R/W; bitpos: [7:0]; default: 10; - * timer count to apply reg_sdio_dcap after sdio power on - */ - uint32_t sdio_timer_target:8; - uint32_t reserved_8:1; - /** sdio_dthdrv : R/W; bitpos: [10:9]; default: 3; - * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 - * after several us. - */ - uint32_t sdio_dthdrv:2; - /** sdio_dcap : R/W; bitpos: [12:11]; default: 3; - * ability to prevent LDO from overshoot - */ - uint32_t sdio_dcap:2; - /** sdio_initi : R/W; bitpos: [14:13]; default: 1; - * add resistor from ldo output to ground. 0: no res, 1: 6k, 2: 4k, 3: 2k - */ - uint32_t sdio_initi:2; - /** sdio_en_initi : R/W; bitpos: [15]; default: 1; - * 0 to set init[1:0]=0 - */ - uint32_t sdio_en_initi:1; - /** sdio_dcurlim : R/W; bitpos: [18:16]; default: 0; - * tune current limit threshold when tieh = 0. About 800mA/(8+d) - */ - uint32_t sdio_dcurlim:3; - /** sdio_modecurlim : R/W; bitpos: [19]; default: 0; - * select current limit mode - */ - uint32_t sdio_modecurlim:1; - /** sdio_encurlim : R/W; bitpos: [20]; default: 1; - * enable current limit - */ - uint32_t sdio_encurlim:1; - /** sdio_reg_pd_en : R/W; bitpos: [21]; default: 1; - * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 - */ - uint32_t sdio_reg_pd_en:1; - /** sdio_force : R/W; bitpos: [22]; default: 0; - * 1: use SW option to control SDIO_REG ,0: use state machine - */ - uint32_t sdio_force:1; - /** sdio_tieh : R/W; bitpos: [23]; default: 1; - * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 - */ - uint32_t sdio_tieh:1; - /** reg1p8_ready : RO; bitpos: [24]; default: 0; - * read only register for REG1P8_READY - */ - uint32_t reg1p8_ready:1; - /** drefl_sdio : R/W; bitpos: [26:25]; default: 1; - * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 - */ - uint32_t drefl_sdio:2; - /** drefm_sdio : R/W; bitpos: [28:27]; default: 1; - * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 - */ - uint32_t drefm_sdio:2; - /** drefh_sdio : R/W; bitpos: [30:29]; default: 0; - * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 - */ - uint32_t drefh_sdio:2; - /** xpd_sdio_reg : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t xpd_sdio_reg:1; - }; - uint32_t val; -} rtc_cntl_sdio_conf_reg_t; - -/** Type of rtc_bias_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:10; - /** bias_buf_idle : R/W; bitpos: [10]; default: 0; - * Need add description - */ - uint32_t bias_buf_idle:1; - /** bias_buf_wake : R/W; bitpos: [11]; default: 1; - * Need add description - */ - uint32_t bias_buf_wake:1; - /** bias_buf_deep_slp : R/W; bitpos: [12]; default: 0; - * Need add description - */ - uint32_t bias_buf_deep_slp:1; - /** bias_buf_monitor : R/W; bitpos: [13]; default: 0; - * Need add description - */ - uint32_t bias_buf_monitor:1; - /** pd_cur_deep_slp : R/W; bitpos: [14]; default: 0; - * xpd cur when rtc in sleep_state - */ - uint32_t pd_cur_deep_slp:1; - /** pd_cur_monitor : R/W; bitpos: [15]; default: 0; - * xpd cur when rtc in monitor state - */ - uint32_t pd_cur_monitor:1; - /** bias_sleep_deep_slp : R/W; bitpos: [16]; default: 1; - * bias_sleep when rtc in sleep_state - */ - uint32_t bias_sleep_deep_slp:1; - /** bias_sleep_monitor : R/W; bitpos: [17]; default: 0; - * bias_sleep when rtc in monitor state - */ - uint32_t bias_sleep_monitor:1; - /** dbg_atten_deep_slp : R/W; bitpos: [21:18]; default: 0; - * DBG_ATTEN when rtc in sleep state - */ - uint32_t dbg_atten_deep_slp:4; - /** dbg_atten_monitor : R/W; bitpos: [25:22]; default: 0; - * DBG_ATTEN when rtc in monitor state - */ - uint32_t dbg_atten_monitor:4; - /** xpd_dcdc_slp : R/W; bitpos: [26]; default: 1; - * Need add description - */ - uint32_t xpd_dcdc_slp:1; - /** xpd_dcdc_monitor : R/W; bitpos: [27]; default: 1; - * Need add description - */ - uint32_t xpd_dcdc_monitor:1; - /** xpd_dcdc_idle : R/W; bitpos: [28]; default: 1; - * Need add description - */ - uint32_t xpd_dcdc_idle:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} rtc_cntl_bias_conf_reg_t; - -/** Type of rtc_regulator register - * register description - */ -typedef union { - struct { - /** dbias_switch_slp : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dbias_switch_slp:1; - /** dbias_switch_monitor : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t dbias_switch_monitor:1; - /** dbias_switch_idle : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t dbias_switch_idle:1; - /** dig_reg_cal_en : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t dig_reg_cal_en:1; - /** sck_dcap : R/W; bitpos: [11:4]; default: 0; - * Need add description - */ - uint32_t sck_dcap:8; - uint32_t reserved_12:3; - /** rtc_vdd_drv_b_active : R/W; bitpos: [20:15]; default: 0; - * SCK_DCAP - */ - uint32_t rtc_vdd_drv_b_active:6; - /** rtc_vdd_drv_b_slp : R/W; bitpos: [26:21]; default: 0; - * Need add description - */ - uint32_t rtc_vdd_drv_b_slp:6; - /** rtc_vdd_drv_b_slp_en : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t rtc_vdd_drv_b_slp_en:1; - /** rtc_dboost_force_pd : R/W; bitpos: [28]; default: 0; - * RTC_DBOOST force power down - */ - uint32_t rtc_dboost_force_pd:1; - /** rtc_dboost_force_pu : R/W; bitpos: [29]; default: 1; - * RTC_DBOOST force power up - */ - uint32_t rtc_dboost_force_pu:1; - /** rtc_regulator_force_pd : R/W; bitpos: [30]; default: 0; - * RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v - * or lower ) - */ - uint32_t rtc_regulator_force_pd:1; - /** rtc_regulator_force_pu : R/W; bitpos: [31]; default: 1; - * Need add description - */ - uint32_t rtc_regulator_force_pu:1; - }; - uint32_t val; -} rtc_cntl_regulator_reg_t; - -/** Type of rtc_regulator0_dbias register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:15; - /** pvt_rtc_dbias : RO; bitpos: [19:15]; default: 20; - * get pvt dbias value - */ - uint32_t pvt_rtc_dbias:5; - /** rtc_regulator0_dbias_slp : R/W; bitpos: [24:20]; default: 20; - * the rtc regulator0 dbias when chip in sleep state - */ - uint32_t rtc_regulator0_dbias_slp:5; - /** rtc_regulator0_dbias_active : R/W; bitpos: [29:25]; default: 20; - * the rtc regulator0 dbias when chip in active state - */ - uint32_t rtc_regulator0_dbias_active:5; - uint32_t reserved_30:1; - /** rtc_regulator0_dbias_sel : R/W; bitpos: [31]; default: 1; - * 1: select sw dbias_active 0: select pvt value - */ - uint32_t rtc_regulator0_dbias_sel:1; - }; - uint32_t val; -} rtc_cntl_regulator0_dbias_reg_t; - -/** Type of rtc_regulator1_dbias register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** rtc_regulator1_dbias_slp : R/W; bitpos: [23:20]; default: 8; - * the rtc regulator1 dbias when chip in sleep state - */ - uint32_t rtc_regulator1_dbias_slp:4; - uint32_t reserved_24:1; - /** rtc_regulator1_dbias_active : R/W; bitpos: [28:25]; default: 8; - * the rtc regulator1 dbias when chip in active state - */ - uint32_t rtc_regulator1_dbias_active:4; - uint32_t reserved_29:3; - }; - uint32_t val; -} rtc_cntl_regulator1_dbias_reg_t; - -/** Type of dig_regulator register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:1; - /** mem_regulator_slp_force_pd : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t mem_regulator_slp_force_pd:1; - /** mem_regulator_slp_force_pu : R/W; bitpos: [2]; default: 1; - * Need add description - */ - uint32_t mem_regulator_slp_force_pu:1; - /** dg_vdd_drv_b_slp : R/W; bitpos: [26:3]; default: 0; - * Need add description - */ - uint32_t dg_vdd_drv_b_slp:24; - /** dg_vdd_drv_b_slp_en : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t dg_vdd_drv_b_slp_en:1; - /** dg_regulator_slp_force_pd : R/W; bitpos: [28]; default: 0; - * Need add description - */ - uint32_t dg_regulator_slp_force_pd:1; - /** dg_regulator_slp_force_pu : R/W; bitpos: [29]; default: 1; - * Need add description - */ - uint32_t dg_regulator_slp_force_pu:1; - /** dg_regulator_force_pd : R/W; bitpos: [30]; default: 0; - * Need add description - */ - uint32_t dg_regulator_force_pd:1; - /** dg_regulator_force_pu : R/W; bitpos: [31]; default: 1; - * Need add description - */ - uint32_t dg_regulator_force_pu:1; - }; - uint32_t val; -} rtc_cntl_dig_regulator_reg_t; - -/** Type of dig_regulator_drvb register - * register description - */ -typedef union { - struct { - /** dg_vdd_drv_b_active : R/W; bitpos: [23:0]; default: 0; - * Need add description - */ - uint32_t dg_vdd_drv_b_active:24; - uint32_t reserved_24:8; - }; - uint32_t val; -} rtc_cntl_dig_regulator_drvb_reg_t; - -/** Type of dig_regulator0_dbias register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:15; - /** pvt_dig_dbias : RO; bitpos: [19:15]; default: 20; - * get pvt dbias value - */ - uint32_t pvt_dig_dbias:5; - /** dig_regulator0_dbias_slp : R/W; bitpos: [24:20]; default: 20; - * the dig regulator0 dbias when chip in sleep state - */ - uint32_t dig_regulator0_dbias_slp:5; - /** dig_regulator0_dbias_active : R/W; bitpos: [29:25]; default: 20; - * the dig regulator0 dbias when chip in active state - */ - uint32_t dig_regulator0_dbias_active:5; - /** dig_regulator0_dbias_init : WO; bitpos: [30]; default: 0; - * initial pvt dbias value - */ - uint32_t dig_regulator0_dbias_init:1; - /** dig_regulator0_dbias_sel : R/W; bitpos: [31]; default: 1; - * 1: select sw dbias_active 0: select pvt value - */ - uint32_t dig_regulator0_dbias_sel:1; - }; - uint32_t val; -} rtc_cntl_dig_regulator0_dbias_reg_t; - -/** Type of dig_regulator1_dbias register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:12; - /** mem_regulator1_dbias_slp : R/W; bitpos: [15:12]; default: 8; - * Need add description - */ - uint32_t mem_regulator1_dbias_slp:4; - /** mem_regulator1_dbias_active : R/W; bitpos: [19:16]; default: 8; - * Need add description - */ - uint32_t mem_regulator1_dbias_active:4; - /** dig_regulator1_dbias_slp : R/W; bitpos: [23:20]; default: 8; - * the dig regulator1 dbias when chip in sleep state - */ - uint32_t dig_regulator1_dbias_slp:4; - uint32_t reserved_24:1; - /** dig_regulator1_dbias_active : R/W; bitpos: [28:25]; default: 8; - * the dig regulator1 dbias when chip in active state - */ - uint32_t dig_regulator1_dbias_active:4; - uint32_t reserved_29:3; - }; - uint32_t val; -} rtc_cntl_dig_regulator1_dbias_reg_t; - -/** Type of rtc_pwc register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** rtc_pad_force_hold : R/W; bitpos: [21]; default: 0; - * rtc pad force hold - */ - uint32_t rtc_pad_force_hold:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} rtc_cntl_pwc_reg_t; - -/** Type of dig_pwc register - * register description - */ -typedef union { - struct { - /** vdd_spi_pwr_drv : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t vdd_spi_pwr_drv:2; - /** vdd_spi_pwr_force : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t vdd_spi_pwr_force:1; - /** lslp_mem_force_pd : R/W; bitpos: [3]; default: 0; - * memories in digital core force PD in sleep - */ - uint32_t lslp_mem_force_pd:1; - /** lslp_mem_force_pu : R/W; bitpos: [4]; default: 1; - * memories in digital core force no PD in sleep - */ - uint32_t lslp_mem_force_pu:1; - uint32_t reserved_5:2; - /** dg_mem_force_pd : R/W; bitpos: [7]; default: 0; - * Need add description - */ - uint32_t dg_mem_force_pd:1; - /** dg_mem_force_pu : R/W; bitpos: [8]; default: 1; - * Need add description - */ - uint32_t dg_mem_force_pu:1; - /** dg_wrap_force_pd : R/W; bitpos: [9]; default: 0; - * Need add description - */ - uint32_t dg_wrap_force_pd:1; - /** dg_wrap_force_pu : R/W; bitpos: [10]; default: 1; - * Need add description - */ - uint32_t dg_wrap_force_pu:1; - /** bt_force_pd : R/W; bitpos: [11]; default: 0; - * Need add description - */ - uint32_t bt_force_pd:1; - /** bt_force_pu : R/W; bitpos: [12]; default: 1; - * Need add description - */ - uint32_t bt_force_pu:1; - /** dg_peri_force_pd : R/W; bitpos: [13]; default: 0; - * Need add description - */ - uint32_t dg_peri_force_pd:1; - /** dg_peri_force_pu : R/W; bitpos: [14]; default: 1; - * Need add description - */ - uint32_t dg_peri_force_pu:1; - /** fastmem_force_lpd : R/W; bitpos: [15]; default: 0; - * Need add description - */ - uint32_t fastmem_force_lpd:1; - /** fastmem_force_lpu : R/W; bitpos: [16]; default: 1; - * Need add description - */ - uint32_t fastmem_force_lpu:1; - /** wifi_force_pd : R/W; bitpos: [17]; default: 0; - * wifi force power down - */ - uint32_t wifi_force_pd:1; - /** wifi_force_pu : R/W; bitpos: [18]; default: 1; - * wifi force power up - */ - uint32_t wifi_force_pu:1; - uint32_t reserved_19:2; - /** cpu_top_force_pd : R/W; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t cpu_top_force_pd:1; - /** cpu_top_force_pu : R/W; bitpos: [22]; default: 1; - * Need add description - */ - uint32_t cpu_top_force_pu:1; - uint32_t reserved_23:3; - /** dg_wrap_ret_pd_en : R/W; bitpos: [26]; default: 0; - * Need add description - */ - uint32_t dg_wrap_ret_pd_en:1; - /** bt_pd_en : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t bt_pd_en:1; - /** dg_peri_pd_en : R/W; bitpos: [28]; default: 0; - * Need add description - */ - uint32_t dg_peri_pd_en:1; - /** cpu_top_pd_en : R/W; bitpos: [29]; default: 0; - * Need add description - */ - uint32_t cpu_top_pd_en:1; - /** wifi_pd_en : R/W; bitpos: [30]; default: 0; - * enable power down wifi in sleep - */ - uint32_t wifi_pd_en:1; - /** dg_wrap_pd_en : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t dg_wrap_pd_en:1; - }; - uint32_t val; -} rtc_cntl_dig_pwc_reg_t; - -/** Type of dig_power_slave0_pd register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** pd_dg_peri_switch_mask : R/W; bitpos: [6:2]; default: 0; - * Need add description - */ - uint32_t pd_dg_peri_switch_mask:5; - /** pd_dg_wrap_switch_mask : R/W; bitpos: [11:7]; default: 0; - * Need add description - */ - uint32_t pd_dg_wrap_switch_mask:5; - /** pd_mem_switch_mask : R/W; bitpos: [31:12]; default: 0; - * Need add description - */ - uint32_t pd_mem_switch_mask:20; - }; - uint32_t val; -} rtc_cntl_dig_power_slave0_pd_reg_t; - -/** Type of dig_power_slave1_pd register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** pd_wifi_switch_mask : R/W; bitpos: [26:22]; default: 0; - * Need add description - */ - uint32_t pd_wifi_switch_mask:5; - /** pd_cpu_switch_mask : R/W; bitpos: [31:27]; default: 0; - * Need add description - */ - uint32_t pd_cpu_switch_mask:5; - }; - uint32_t val; -} rtc_cntl_dig_power_slave1_pd_reg_t; - -/** Type of dig_power_slave0_fpu register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:2; - /** xpd_dg_peri_switch_mask : R/W; bitpos: [6:2]; default: 31; - * Need add description - */ - uint32_t xpd_dg_peri_switch_mask:5; - /** xpd_dg_wrap_switch_mask : R/W; bitpos: [11:7]; default: 31; - * Need add description - */ - uint32_t xpd_dg_wrap_switch_mask:5; - /** xpd_mem_switch_mask : R/W; bitpos: [31:12]; default: 1048575; - * Need add description - */ - uint32_t xpd_mem_switch_mask:20; - }; - uint32_t val; -} rtc_cntl_dig_power_slave0_fpu_reg_t; - -/** Type of dig_power_slave1_fpu register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** xpd_wifi_switch_mask : R/W; bitpos: [26:22]; default: 31; - * Need add description - */ - uint32_t xpd_wifi_switch_mask:5; - /** xpd_cpu_switch_mask : R/W; bitpos: [31:27]; default: 31; - * Need add description - */ - uint32_t xpd_cpu_switch_mask:5; - }; - uint32_t val; -} rtc_cntl_dig_power_slave1_fpu_reg_t; - -/** Type of dig_iso register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** dg_mem_force_noiso : R/W; bitpos: [5]; default: 1; - * Need add description - */ - uint32_t dg_mem_force_noiso:1; - /** dg_mem_force_iso : R/W; bitpos: [6]; default: 0; - * Need add description - */ - uint32_t dg_mem_force_iso:1; - /** dig_iso_force_off : R/W; bitpos: [7]; default: 1; - * Need add description - */ - uint32_t dig_iso_force_off:1; - /** dig_iso_force_on : R/W; bitpos: [8]; default: 0; - * Need add description - */ - uint32_t dig_iso_force_on:1; - /** dg_pad_autohold : RO; bitpos: [9]; default: 0; - * read only register to indicate digital pad auto-hold status - */ - uint32_t dg_pad_autohold:1; - /** clr_dg_pad_autohold : WO; bitpos: [10]; default: 0; - * wtite only register to clear digital pad auto-hold - */ - uint32_t clr_dg_pad_autohold:1; - /** dg_pad_autohold_en : R/W; bitpos: [11]; default: 0; - * digital pad enable auto-hold - */ - uint32_t dg_pad_autohold_en:1; - /** dg_pad_force_noiso : R/W; bitpos: [12]; default: 1; - * digital pad force no ISO - */ - uint32_t dg_pad_force_noiso:1; - /** dg_pad_force_iso : R/W; bitpos: [13]; default: 0; - * digital pad force ISO - */ - uint32_t dg_pad_force_iso:1; - /** dg_pad_force_unhold : R/W; bitpos: [14]; default: 1; - * digital pad force un-hold - */ - uint32_t dg_pad_force_unhold:1; - /** dg_pad_force_hold : R/W; bitpos: [15]; default: 0; - * digital pad force hold - */ - uint32_t dg_pad_force_hold:1; - uint32_t reserved_16:6; - /** bt_force_iso : R/W; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t bt_force_iso:1; - /** bt_force_noiso : R/W; bitpos: [23]; default: 1; - * Need add description - */ - uint32_t bt_force_noiso:1; - /** dg_peri_force_iso : R/W; bitpos: [24]; default: 0; - * Need add description - */ - uint32_t dg_peri_force_iso:1; - /** dg_peri_force_noiso : R/W; bitpos: [25]; default: 1; - * Need add description - */ - uint32_t dg_peri_force_noiso:1; - /** cpu_top_force_iso : R/W; bitpos: [26]; default: 0; - * cpu force ISO - */ - uint32_t cpu_top_force_iso:1; - /** cpu_top_force_noiso : R/W; bitpos: [27]; default: 1; - * cpu force no ISO - */ - uint32_t cpu_top_force_noiso:1; - /** wifi_force_iso : R/W; bitpos: [28]; default: 0; - * wifi force ISO - */ - uint32_t wifi_force_iso:1; - /** wifi_force_noiso : R/W; bitpos: [29]; default: 1; - * wifi force no ISO - */ - uint32_t wifi_force_noiso:1; - /** dg_wrap_force_iso : R/W; bitpos: [30]; default: 0; - * digital core force ISO - */ - uint32_t dg_wrap_force_iso:1; - /** dg_wrap_force_noiso : R/W; bitpos: [31]; default: 1; - * Need add description - */ - uint32_t dg_wrap_force_noiso:1; - }; - uint32_t val; -} rtc_cntl_dig_iso_reg_t; - -/** Type of rtc_wdtconfig0 register - * register description - */ -typedef union { - struct { - /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20; - * chip reset siginal pulse width - */ - uint32_t chip_reset_width:8; - /** chip_reset_en : R/W; bitpos: [8]; default: 0; - * wdt reset whole chip enable - */ - uint32_t chip_reset_en:1; - /** pause_in_slp : R/W; bitpos: [9]; default: 1; - * pause WDT in sleep - */ - uint32_t pause_in_slp:1; - /** appcpu_reset_en : R/W; bitpos: [10]; default: 0; - * enable WDT reset APP CPU - */ - uint32_t appcpu_reset_en:1; - /** procpu_reset_en : R/W; bitpos: [11]; default: 0; - * enable WDT reset PRO CPU - */ - uint32_t procpu_reset_en:1; - /** flashboot_mod_en : R/W; bitpos: [12]; default: 1; - * enable WDT in flash boot - */ - uint32_t flashboot_mod_en:1; - /** sys_reset_length : R/W; bitpos: [15:13]; default: 1; - * system reset counter length - */ - uint32_t sys_reset_length:3; - /** cpu_reset_length : R/W; bitpos: [18:16]; default: 1; - * CPU reset counter length - */ - uint32_t cpu_reset_length:3; - /** stg3 : R/W; bitpos: [21:19]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ - uint32_t stg3:3; - /** stg2 : R/W; bitpos: [24:22]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ - uint32_t stg2:3; - /** stg1 : R/W; bitpos: [27:25]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ - uint32_t stg1:3; - /** stg0 : R/W; bitpos: [30:28]; default: 0; - * 1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC - * reset stage en - */ - uint32_t stg0:3; - /** en : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t en:1; - }; - uint32_t val; -} rtc_cntl_wdtconfig0_reg_t; - -/** Type of rtc_wdtconfig1 register - * register description - */ -typedef union { - struct { - /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; - * Need add description - */ - uint32_t wdt_stg0_hold:32; - }; - uint32_t val; -} rtc_cntl_wdtconfig1_reg_t; - -/** Type of rtc_wdtconfig2 register - * register description - */ -typedef union { - struct { - /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; - * Need add description - */ - uint32_t wdt_stg1_hold:32; - }; - uint32_t val; -} rtc_cntl_wdtconfig2_reg_t; - -/** Type of rtc_wdtconfig3 register - * register description - */ -typedef union { - struct { - /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; - * Need add description - */ - uint32_t wdt_stg2_hold:32; - }; - uint32_t val; -} rtc_cntl_wdtconfig3_reg_t; - -/** Type of rtc_wdtconfig4 register - * register description - */ -typedef union { - struct { - /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; - * Need add description - */ - uint32_t wdt_stg3_hold:32; - }; - uint32_t val; -} rtc_cntl_wdtconfig4_reg_t; - -/** Type of rtc_wdtfeed register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** feed : WO; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t feed:1; - }; - uint32_t val; -} rtc_cntl_wdtfeed_reg_t; - -/** Type of rtc_wdtwprotect register - * register description - */ -typedef union { - struct { - /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t wdt_wkey:32; - }; - uint32_t val; -} rtc_cntl_wdtwprotect_reg_t; - -/** Type of rtc_wdtreset_chip register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** reset_chip_target : R/W; bitpos: [23:16]; default: 165; - * Need add description - */ - uint32_t reset_chip_target:8; - /** reset_chip_key : R/W; bitpos: [31:24]; default: 0; - * Need add description - */ - uint32_t reset_chip_key:8; - }; - uint32_t val; -} rtc_cntl_wdtreset_chip_reg_t; - -/** Type of rtc_swd_conf register - * register description - */ -typedef union { - struct { - /** swd_reset_flag : RO; bitpos: [0]; default: 0; - * swd reset flag - */ - uint32_t swd_reset_flag:1; - /** swd_feed_int : RO; bitpos: [1]; default: 0; - * swd interrupt for feeding - */ - uint32_t swd_feed_int:1; - uint32_t reserved_2:15; - /** swd_bypass_rst : R/W; bitpos: [17]; default: 0; - * Need add description - */ - uint32_t swd_bypass_rst:1; - /** swd_signal_width : R/W; bitpos: [27:18]; default: 300; - * adjust signal width send to swd - */ - uint32_t swd_signal_width:10; - /** swd_rst_flag_clr : WO; bitpos: [28]; default: 0; - * reset swd reset flag - */ - uint32_t swd_rst_flag_clr:1; - /** swd_feed : WO; bitpos: [29]; default: 0; - * Sw feed swd - */ - uint32_t swd_feed:1; - /** swd_disable : R/W; bitpos: [30]; default: 0; - * disabel SWD - */ - uint32_t swd_disable:1; - /** swd_auto_feed_en : R/W; bitpos: [31]; default: 0; - * automatically feed swd when int comes - */ - uint32_t swd_auto_feed_en:1; - }; - uint32_t val; -} rtc_cntl_swd_conf_reg_t; - -/** Type of rtc_swd_wprotect register - * register description - */ -typedef union { - struct { - /** swd_wkey : R/W; bitpos: [31:0]; default: 0; - * swd write protect - */ - uint32_t swd_wkey:32; - }; - uint32_t val; -} rtc_cntl_swd_wprotect_reg_t; - -/** Type of rtc_sw_cpu_stall register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** appcpu_c1 : R/W; bitpos: [25:20]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP - * CPU - */ - uint32_t appcpu_c1:6; - /** procpu_c1 : R/W; bitpos: [31:26]; default: 0; - * Need add description - */ - uint32_t procpu_c1:6; - }; - uint32_t val; -} rtc_cntl_sw_cpu_stall_reg_t; - -/** Type of rtc_low_power_st register - * register description - */ -typedef union { - struct { - /** xpd_rom0 : RO; bitpos: [0]; default: 0; - * rom0 power down - */ - uint32_t xpd_rom0:1; - uint32_t reserved_1:1; - /** xpd_dig_dcdc : RO; bitpos: [2]; default: 0; - * External DCDC power down - */ - uint32_t xpd_dig_dcdc:1; - /** rtc_peri_iso : RO; bitpos: [3]; default: 0; - * rtc peripheral iso - */ - uint32_t rtc_peri_iso:1; - /** xpd_rtc_peri : RO; bitpos: [4]; default: 0; - * rtc peripheral power down - */ - uint32_t xpd_rtc_peri:1; - /** wifi_iso : RO; bitpos: [5]; default: 0; - * wifi iso - */ - uint32_t wifi_iso:1; - /** xpd_wifi : RO; bitpos: [6]; default: 0; - * wifi wrap power down - */ - uint32_t xpd_wifi:1; - /** dig_iso : RO; bitpos: [7]; default: 0; - * digital wrap iso - */ - uint32_t dig_iso:1; - /** xpd_dig : RO; bitpos: [8]; default: 0; - * digital wrap power down - */ - uint32_t xpd_dig:1; - /** rtc_touch_state_start : RO; bitpos: [9]; default: 0; - * touch should start to work - */ - uint32_t rtc_touch_state_start:1; - /** rtc_touch_state_switch : RO; bitpos: [10]; default: 0; - * touch is about to working. Switch rtc main state - */ - uint32_t rtc_touch_state_switch:1; - /** rtc_touch_state_slp : RO; bitpos: [11]; default: 0; - * touch is in sleep state - */ - uint32_t rtc_touch_state_slp:1; - /** rtc_touch_state_done : RO; bitpos: [12]; default: 0; - * touch is done - */ - uint32_t rtc_touch_state_done:1; - /** rtc_cocpu_state_start : RO; bitpos: [13]; default: 0; - * ulp/cocpu should start to work - */ - uint32_t rtc_cocpu_state_start:1; - /** rtc_cocpu_state_switch : RO; bitpos: [14]; default: 0; - * ulp/cocpu is about to working. Switch rtc main state - */ - uint32_t rtc_cocpu_state_switch:1; - /** rtc_cocpu_state_slp : RO; bitpos: [15]; default: 0; - * ulp/cocpu is in sleep state - */ - uint32_t rtc_cocpu_state_slp:1; - /** rtc_cocpu_state_done : RO; bitpos: [16]; default: 0; - * ulp/cocpu is done - */ - uint32_t rtc_cocpu_state_done:1; - /** rtc_main_state_xtal_iso : RO; bitpos: [17]; default: 0; - * no use any more - */ - uint32_t rtc_main_state_xtal_iso:1; - /** rtc_main_state_pll_on : RO; bitpos: [18]; default: 0; - * rtc main state machine is in states that pll should be running - */ - uint32_t rtc_main_state_pll_on:1; - /** rtc_rdy_for_wakeup : RO; bitpos: [19]; default: 0; - * rtc is ready to receive wake up trigger from wake up source - */ - uint32_t rtc_rdy_for_wakeup:1; - /** rtc_main_state_wait_end : RO; bitpos: [20]; default: 0; - * rtc main state machine has been waited for some cycles - */ - uint32_t rtc_main_state_wait_end:1; - /** rtc_in_wakeup_state : RO; bitpos: [21]; default: 0; - * rtc main state machine is in the states of wakeup process - */ - uint32_t rtc_in_wakeup_state:1; - /** rtc_in_low_power_state : RO; bitpos: [22]; default: 0; - * rtc main state machine is in the states of low power - */ - uint32_t rtc_in_low_power_state:1; - /** rtc_main_state_in_wait_8m : RO; bitpos: [23]; default: 0; - * rtc main state machine is in wait 8m state - */ - uint32_t rtc_main_state_in_wait_8m:1; - /** rtc_main_state_in_wait_pll : RO; bitpos: [24]; default: 0; - * rtc main state machine is in wait pll state - */ - uint32_t rtc_main_state_in_wait_pll:1; - /** rtc_main_state_in_wait_xtl : RO; bitpos: [25]; default: 0; - * rtc main state machine is in wait xtal state - */ - uint32_t rtc_main_state_in_wait_xtl:1; - /** rtc_main_state_in_slp : RO; bitpos: [26]; default: 0; - * rtc main state machine is in sleep state - */ - uint32_t rtc_main_state_in_slp:1; - /** rtc_main_state_in_idle : RO; bitpos: [27]; default: 0; - * rtc main state machine is in idle state - */ - uint32_t rtc_main_state_in_idle:1; - /** rtc_main_state : RO; bitpos: [31:28]; default: 0; - * rtc main state machine status - */ - uint32_t rtc_main_state:4; - }; - uint32_t val; -} rtc_cntl_low_power_st_reg_t; - -/** Type of rtc_diag0 register - * register description - */ -typedef union { - struct { - /** rtc_low_power_diag1 : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t rtc_low_power_diag1:32; - }; - uint32_t val; -} rtc_cntl_diag0_reg_t; - -/** Type of rtc_pad_hold register - * register description - */ -typedef union { - struct { - /** rtc_gpio_pin0_hold : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin0_hold:1; - /** rtc_gpio_pin1_hold : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin1_hold:1; - /** rtc_gpio_pin2_hold : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin2_hold:1; - /** rtc_gpio_pin3_hold : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin3_hold:1; - /** rtc_gpio_pin4_hold : R/W; bitpos: [4]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin4_hold:1; - /** rtc_gpio_pin5_hold : R/W; bitpos: [5]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin5_hold:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} rtc_cntl_pad_hold_reg_t; - -/** Type of dig_pad_hold register - * register description - */ -typedef union { - struct { - /** dig_pad_hold : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t dig_pad_hold:32; - }; - uint32_t val; -} rtc_cntl_dig_pad_hold_reg_t; - -/** Type of dig_pad_hold1 register - * register description - */ -typedef union { - struct { - /** dig_pad_hold1 : R/W; bitpos: [8:0]; default: 0; - * Need add description - */ - uint32_t dig_pad_hold1:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} rtc_cntl_dig_pad_hold1_reg_t; - -/** Type of rtc_brown_out register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** int_wait : R/W; bitpos: [13:4]; default: 1; - * brown out interrupt wait cycles - */ - uint32_t int_wait:10; - /** close_flash_ena : R/W; bitpos: [14]; default: 0; - * enable close flash when brown out happens - */ - uint32_t close_flash_ena:1; - /** pd_rf_ena : R/W; bitpos: [15]; default: 0; - * enable power down RF when brown out happens - */ - uint32_t pd_rf_ena:1; - /** rst_wait : R/W; bitpos: [25:16]; default: 1023; - * brown out reset wait cycles - */ - uint32_t rst_wait:10; - /** rst_ena : R/W; bitpos: [26]; default: 0; - * enable brown out reset - */ - uint32_t rst_ena:1; - /** rst_sel : R/W; bitpos: [27]; default: 0; - * 1: 4-pos reset, 0: sys_reset - */ - uint32_t rst_sel:1; - /** ana_rst_en : R/W; bitpos: [28]; default: 0; - * Need add description - */ - uint32_t ana_rst_en:1; - /** cnt_clr : WO; bitpos: [29]; default: 0; - * clear brown out counter - */ - uint32_t cnt_clr:1; - /** ena : R/W; bitpos: [30]; default: 1; - * enable brown out - */ - uint32_t ena:1; - /** det : RO; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t det:1; - }; - uint32_t val; -} rtc_cntl_brown_out_reg_t; - -/** Type of rtc_time_low1 register - * register description - */ -typedef union { - struct { - /** rtc_timer_value1_low : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ - uint32_t rtc_timer_value1_low:32; - }; - uint32_t val; -} rtc_cntl_time_low1_reg_t; - -/** Type of rtc_time_high1 register - * register description - */ -typedef union { - struct { - /** rtc_timer_value1_high : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ - uint32_t rtc_timer_value1_high:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} rtc_cntl_time_high1_reg_t; - -/** Type of rtc_xtal32k_clk_factor register - * register description - */ -typedef union { - struct { - /** xtal32k_clk_factor : R/W; bitpos: [31:0]; default: 0; - * xtal 32k watch dog backup clock factor - */ - uint32_t xtal32k_clk_factor:32; - }; - uint32_t val; -} rtc_cntl_xtal32k_clk_factor_reg_t; - -/** Type of rtc_xtal32k_conf register - * register description - */ -typedef union { - struct { - /** xtal32k_return_wait : R/W; bitpos: [3:0]; default: 0; - * cycles to wait to return noral xtal 32k - */ - uint32_t xtal32k_return_wait:4; - /** xtal32k_restart_wait : R/W; bitpos: [19:4]; default: 0; - * cycles to wait to repower on xtal 32k - */ - uint32_t xtal32k_restart_wait:16; - /** xtal32k_wdt_timeout : R/W; bitpos: [27:20]; default: 255; - * If no clock detected for this amount of time, 32k is regarded as dead - */ - uint32_t xtal32k_wdt_timeout:8; - /** xtal32k_stable_thres : R/W; bitpos: [31:28]; default: 0; - * if restarted xtal32k period is smaller than this, it is regarded as stable - */ - uint32_t xtal32k_stable_thres:4; - }; - uint32_t val; -} rtc_cntl_xtal32k_conf_reg_t; - -/** Type of rtc_usb_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** io_mux_reset_disable : R/W; bitpos: [18]; default: 0; - * Need add description - */ - uint32_t io_mux_reset_disable:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} rtc_cntl_usb_conf_reg_t; - -/** Type of rtc_slp_reject_cause register - * register description - */ -typedef union { - struct { - /** reject_cause : RO; bitpos: [18:0]; default: 0; - * sleep reject cause - */ - uint32_t reject_cause:19; - uint32_t reserved_19:13; - }; - uint32_t val; -} rtc_cntl_slp_reject_cause_reg_t; - -/** Type of rtc_option1 register - * register description - */ -typedef union { - struct { - /** force_download_boot : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t force_download_boot:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} rtc_cntl_option1_reg_t; - -/** Type of rtc_slp_wakeup_cause register - * register description - */ -typedef union { - struct { - /** wakeup_cause : RO; bitpos: [18:0]; default: 0; - * sleep wakeup cause - */ - uint32_t wakeup_cause:19; - uint32_t reserved_19:13; - }; - uint32_t val; -} rtc_cntl_slp_wakeup_cause_reg_t; - -/** Type of rtc_ulp_cp_timer_1 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** ulp_cp_timer_slp_cycle : R/W; bitpos: [31:8]; default: 200; - * sleep cycles for ULP-coprocessor timer - */ - uint32_t ulp_cp_timer_slp_cycle:24; - }; - uint32_t val; -} rtc_cntl_ulp_cp_timer_1_reg_t; - -/** Type of int_ena_w1ts register - * register description - */ -typedef union { - struct { - /** slp_wakeup_w1ts : WO; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - uint32_t slp_wakeup_w1ts:1; - /** slp_reject_w1ts : WO; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - uint32_t slp_reject_w1ts:1; - uint32_t reserved_2:1; - /** rtc_wdt_w1ts : WO; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - uint32_t rtc_wdt_w1ts:1; - uint32_t reserved_4:5; - /** w1ts : WO; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - uint32_t w1ts:1; - /** rtc_main_timer_w1ts : WO; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - uint32_t rtc_main_timer_w1ts:1; - uint32_t reserved_11:4; - /** rtc_swd_w1ts : WO; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - uint32_t rtc_swd_w1ts:1; - /** rtc_xtal32k_dead_w1ts : WO; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - uint32_t rtc_xtal32k_dead_w1ts:1; - uint32_t reserved_17:2; - /** rtc_glitch_det_w1ts : WO; bitpos: [19]; default: 0; - * enbale gitch det interrupt - */ - uint32_t rtc_glitch_det_w1ts:1; - /** rtc_bbpll_cal_w1ts : WO; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_bbpll_cal_w1ts:1; - /** rtc_ble_compare_wake_w1ts : WO; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ble_compare_wake_w1ts:1; - /** vset_dcdc_done_w1ts : WO; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_done_w1ts:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_cntl_int_ena_w1ts_reg_t; - -/** Type of int_ena_w1tc register - * register description - */ -typedef union { - struct { - /** slp_wakeup_w1tc : WO; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - uint32_t slp_wakeup_w1tc:1; - /** slp_reject_w1tc : WO; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - uint32_t slp_reject_w1tc:1; - uint32_t reserved_2:1; - /** rtc_wdt_w1tc : WO; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - uint32_t rtc_wdt_w1tc:1; - uint32_t reserved_4:5; - /** rtc_brown_out_w1tc : WO; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - uint32_t rtc_brown_out_w1tc:1; - /** rtc_main_timer_w1tc : WO; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - uint32_t rtc_main_timer_w1tc:1; - uint32_t reserved_11:4; - /** rtc_swd_w1tc : WO; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - uint32_t rtc_swd_w1tc:1; - /** rtc_xtal32k_dead_w1tc : WO; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - uint32_t rtc_xtal32k_dead_w1tc:1; - uint32_t reserved_17:2; - /** rtc_glitch_det_w1tc : WO; bitpos: [19]; default: 0; - * enbale gitch det interrupt - */ - uint32_t rtc_glitch_det_w1tc:1; - /** rtc_bbpll_cal_w1tc : WO; bitpos: [20]; default: 0; - * Need add description - */ - uint32_t rtc_bbpll_cal_w1tc:1; - /** rtc_ble_compare_wake_w1tc : WO; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t rtc_ble_compare_wake_w1tc:1; - /** vset_dcdc_done_w1tc : WO; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_done_w1tc:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} rtc_cntl_int_ena_w1tc_reg_t; - -/** Type of rtc_cntl_retention_ctrl register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:17; - /** clk_en : R/W; bitpos: [17]; default: 0; - * Need add description - */ - uint32_t clk_en:1; - /** retention_clk_sel : R/W; bitpos: [18]; default: 0; - * Need add description - */ - uint32_t retention_clk_sel:1; - /** retention_done_wait : R/W; bitpos: [21:19]; default: 2; - * Need add description - */ - uint32_t retention_done_wait:3; - /** retention_clkoff_wait : R/W; bitpos: [25:22]; default: 3; - * Need add description - */ - uint32_t retention_clkoff_wait:4; - /** retention_en : R/W; bitpos: [26]; default: 0; - * Need add description - */ - uint32_t retention_en:1; - /** retention_wait : R/W; bitpos: [31:27]; default: 20; - * wait cycles for rention operation - */ - uint32_t retention_wait:5; - }; - uint32_t val; -} rtc_cntl_retention_ctrl_reg_t; - -/** Type of rtc_cntl_retention_ctrl1 register - * register description - */ -typedef union { - struct { - /** retention_link_addr : R/W; bitpos: [26:0]; default: 0; - * Need add description - */ - uint32_t retention_link_addr:27; - uint32_t reserved_27:5; - }; - uint32_t val; -} rtc_cntl_retention_ctrl1_reg_t; - -/** Type of rtc_fib_sel register - * register description - */ -typedef union { - struct { - /** rtc_fib_sel : R/W; bitpos: [2:0]; default: 7; - * select use analog fib signal - */ - uint32_t rtc_fib_sel:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} rtc_cntl_fib_sel_reg_t; - -/** Type of rtc_cntl_gpio_wakeup register - * register description - */ -typedef union { - struct { - /** rtc_gpio_wakeup_status : RO; bitpos: [5:0]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_wakeup_status:6; - /** rtc_gpio_wakeup_status_clr : R/W; bitpos: [6]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_wakeup_status_clr:1; - /** rtc_gpio_pin_clk_gate : R/W; bitpos: [7]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin_clk_gate:1; - /** rtc_gpio_pin5_int_type : R/W; bitpos: [10:8]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin5_int_type:3; - /** rtc_gpio_pin4_int_type : R/W; bitpos: [13:11]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin4_int_type:3; - /** rtc_gpio_pin3_int_type : R/W; bitpos: [16:14]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin3_int_type:3; - /** rtc_gpio_pin2_int_type : R/W; bitpos: [19:17]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin2_int_type:3; - /** rtc_gpio_pin1_int_type : R/W; bitpos: [22:20]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin1_int_type:3; - /** rtc_gpio_pin0_int_type : R/W; bitpos: [25:23]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin0_int_type:3; - /** rtc_gpio_pin5_wakeup_enable : R/W; bitpos: [26]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin5_wakeup_enable:1; - /** rtc_gpio_pin4_wakeup_enable : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin4_wakeup_enable:1; - /** rtc_gpio_pin3_wakeup_enable : R/W; bitpos: [28]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin3_wakeup_enable:1; - /** rtc_gpio_pin2_wakeup_enable : R/W; bitpos: [29]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin2_wakeup_enable:1; - /** rtc_gpio_pin1_wakeup_enable : R/W; bitpos: [30]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin1_wakeup_enable:1; - /** rtc_gpio_pin0_wakeup_enable : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin0_wakeup_enable:1; - }; - uint32_t val; -} rtc_cntl_gpio_wakeup_reg_t; - -/** Type of rtc_cntl_dbg_sel register - * register description - */ -typedef union { - struct { - /** rtc_mtdi_enamux : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t rtc_mtdi_enamux:1; - /** rtc_debug_12m_no_gating : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t rtc_debug_12m_no_gating:1; - /** rtc_debug_bit_sel : R/W; bitpos: [6:2]; default: 0; - * Need add description - */ - uint32_t rtc_debug_bit_sel:5; - /** rtc_debug_sel0 : R/W; bitpos: [11:7]; default: 0; - * Need add description - */ - uint32_t rtc_debug_sel0:5; - /** rtc_debug_sel1 : R/W; bitpos: [16:12]; default: 0; - * Need add description - */ - uint32_t rtc_debug_sel1:5; - /** rtc_debug_sel2 : R/W; bitpos: [21:17]; default: 0; - * Need add description - */ - uint32_t rtc_debug_sel2:5; - /** rtc_debug_sel3 : R/W; bitpos: [26:22]; default: 0; - * Need add description - */ - uint32_t rtc_debug_sel3:5; - /** rtc_debug_sel4 : R/W; bitpos: [31:27]; default: 0; - * Need add description - */ - uint32_t rtc_debug_sel4:5; - }; - uint32_t val; -} rtc_cntl_dbg_sel_reg_t; - -/** Type of rtc_cntl_dbg_map register - * register description - */ -typedef union { - struct { - /** vdd_dig_test : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t vdd_dig_test:2; - /** rtc_gpio_pin5_mux_sel : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin5_mux_sel:1; - /** rtc_gpio_pin4_mux_sel : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin4_mux_sel:1; - /** rtc_gpio_pin3_mux_sel : R/W; bitpos: [4]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin3_mux_sel:1; - /** rtc_gpio_pin2_mux_sel : R/W; bitpos: [5]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin2_mux_sel:1; - /** rtc_gpio_pin1_mux_sel : R/W; bitpos: [6]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin1_mux_sel:1; - /** rtc_gpio_pin0_mux_sel : R/W; bitpos: [7]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin0_mux_sel:1; - /** rtc_gpio_pin5_fun_sel : R/W; bitpos: [11:8]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin5_fun_sel:4; - /** rtc_gpio_pin4_fun_sel : R/W; bitpos: [15:12]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin4_fun_sel:4; - /** rtc_gpio_pin3_fun_sel : R/W; bitpos: [19:16]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin3_fun_sel:4; - /** rtc_gpio_pin2_fun_sel : R/W; bitpos: [23:20]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin2_fun_sel:4; - /** rtc_gpio_pin1_fun_sel : R/W; bitpos: [27:24]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin1_fun_sel:4; - /** rtc_gpio_pin0_fun_sel : R/W; bitpos: [31:28]; default: 0; - * Need add description - */ - uint32_t rtc_gpio_pin0_fun_sel:4; - }; - uint32_t val; -} rtc_cntl_dbg_map_reg_t; - -/** Type of rtc_cntl_dbg_sar_sel register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** sar_debug_sel : R/W; bitpos: [31:27]; default: 0; - * Need add description - */ - uint32_t sar_debug_sel:5; - }; - uint32_t val; -} rtc_cntl_dbg_sar_sel_reg_t; - -/** Type of rtc_cntl_pg_ctrl register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** power_glitch_dsense : R/W; bitpos: [27:26]; default: 0; - * Need add description - */ - uint32_t power_glitch_dsense:2; - /** power_glitch_force_pd : R/W; bitpos: [28]; default: 0; - * Need add description - */ - uint32_t power_glitch_force_pd:1; - /** power_glitch_force_pu : R/W; bitpos: [29]; default: 0; - * Need add description - */ - uint32_t power_glitch_force_pu:1; - /** power_glitch_efuse_sel : R/W; bitpos: [30]; default: 0; - * Need add description - */ - uint32_t power_glitch_efuse_sel:1; - /** power_glitch_en : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t power_glitch_en:1; - }; - uint32_t val; -} rtc_cntl_pg_ctrl_reg_t; - -/** Type of rtc_cntl_dcdc_ctrl0 register - * register description - */ -typedef union { - struct { - /** vset_dcdc_value : RO; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_value:5; - /** power_good_dcdc : RO; bitpos: [5]; default: 1; - * Need add description - */ - uint32_t power_good_dcdc:1; - uint32_t reserved_6:13; - /** pmu_mode : R/W; bitpos: [20:19]; default: 0; - * Need add description - */ - uint32_t pmu_mode:2; - /** ramplevel_dcdc : R/W; bitpos: [21]; default: 0; - * Need add description - */ - uint32_t ramplevel_dcdc:1; - /** ramp_dcdc : R/W; bitpos: [22]; default: 0; - * Need add description - */ - uint32_t ramp_dcdc:1; - /** dcm2enb_dcdc : R/W; bitpos: [23]; default: 0; - * Need add description - */ - uint32_t dcm2enb_dcdc:1; - /** dcmlevel_dcdc : R/W; bitpos: [25:24]; default: 0; - * Need add description - */ - uint32_t dcmlevel_dcdc:2; - /** fsw_dcdc : R/W; bitpos: [28:26]; default: 0; - * Need add description - */ - uint32_t fsw_dcdc:3; - /** ccm_dcdc : R/W; bitpos: [29]; default: 0; - * Need add description - */ - uint32_t ccm_dcdc:1; - /** sstime_dcdc : R/W; bitpos: [30]; default: 0; - * Need add description - */ - uint32_t sstime_dcdc:1; - /** pocpenb_dcdc : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t pocpenb_dcdc:1; - }; - uint32_t val; -} rtc_cntl_dcdc_ctrl0_reg_t; - -/** Type of rtc_cntl_dcdc_ctrl1 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** dcdc_mode_slp : R/W; bitpos: [25:23]; default: 4; - * Need add description - */ - uint32_t dcdc_mode_slp:3; - /** dcdc_mode_monitor : R/W; bitpos: [28:26]; default: 4; - * Need add description - */ - uint32_t dcdc_mode_monitor:3; - /** dcdc_mode_idle : R/W; bitpos: [31:29]; default: 4; - * Need add description - */ - uint32_t dcdc_mode_idle:3; - }; - uint32_t val; -} rtc_cntl_dcdc_ctrl1_reg_t; - -/** Type of rtc_cntl_dcdc_ctrl2 register - * register description - */ -typedef union { - struct { - /** vset_dcdc_target_value1 : R/W; bitpos: [4:0]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_target_value1:5; - /** vset_dcdc_target_value0 : R/W; bitpos: [9:5]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_target_value0:5; - /** vset_dcdc_init_value : R/W; bitpos: [14:10]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_init_value:5; - /** vset_dcdc_init : WO; bitpos: [15]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_init:1; - /** vset_dcdc_fix : R/W; bitpos: [16]; default: 1; - * Need add description - */ - uint32_t vset_dcdc_fix:1; - /** vset_dcdc_step : R/W; bitpos: [21:17]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_step:5; - /** vset_dcdc_gap : R/W; bitpos: [26:22]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_gap:5; - /** vset_dcdc_sel_hw_sw : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_sel_hw_sw:1; - /** vset_dcdc_sw_sel : R/W; bitpos: [28]; default: 0; - * Need add description - */ - uint32_t vset_dcdc_sw_sel:1; - uint32_t reserved_29:3; - }; - uint32_t val; -} rtc_cntl_dcdc_ctrl2_reg_t; - -/** Type of rtc_cntl_rc32k_ctrl register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** rc32k_dfreq : R/W; bitpos: [30:21]; default: 511; - * Need add description - */ - uint32_t rc32k_dfreq:10; - /** rc32k_xpd : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t rc32k_xpd:1; - }; - uint32_t val; -} rtc_cntl_rc32k_ctrl_reg_t; - -/** Type of rtc_cntl_pll8m register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** ckref_pll8m_sel : R/W; bitpos: [30]; default: 0; - * Need add description - */ - uint32_t ckref_pll8m_sel:1; - /** xpd_pll8m : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t xpd_pll8m:1; - }; - uint32_t val; -} rtc_cntl_pll8m_reg_t; - -/** Type of rtc_cntl_date register - * register description - */ -typedef union { - struct { - /** rtc_cntl_date : R/W; bitpos: [27:0]; default: 34640480; - * Need add description - */ - uint32_t rtc_cntl_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} rtc_cntl_date_reg_t; - - -typedef struct { - volatile rtc_cntl_options0_reg_t options0; - volatile rtc_cntl_slp_timer0_reg_t slp_timer0; - volatile rtc_cntl_slp_timer1_reg_t slp_timer1; - volatile rtc_cntl_time_update_reg_t time_update; - volatile rtc_cntl_time_low0_reg_t time_low0; - volatile rtc_cntl_time_high0_reg_t time_high0; - volatile rtc_cntl_state0_reg_t state0; - volatile rtc_cntl_timer1_reg_t timer1; - volatile rtc_cntl_timer2_reg_t timer2; - volatile rtc_cntl_timer3_reg_t timer3; - volatile rtc_cntl_timer4_reg_t timer4; - volatile rtc_cntl_timer5_reg_t timer5; - volatile rtc_cntl_timer6_reg_t timer6; - volatile rtc_cntl_ana_conf_reg_t ana_conf; - volatile rtc_cntl_reset_state_reg_t reset_state; - volatile rtc_cntl_wakeup_state_reg_t wakeup_state; - volatile rtc_cntl_int_ena_reg_t int_ena; - volatile rtc_cntl_int_raw_reg_t int_raw; - volatile rtc_cntl_int_st_reg_t int_st; - volatile rtc_cntl_int_clr_reg_t int_clr; - volatile rtc_cntl_store_reg_t store[4]; - volatile rtc_cntl_ext_xtl_conf_reg_t ext_xtl_conf; - volatile rtc_cntl_ext_wakeup_conf_reg_t ext_wakeup_conf; - volatile rtc_cntl_slp_reject_conf_reg_t slp_reject_conf; - volatile rtc_cntl_cpu_period_conf_reg_t cpu_period_conf; - volatile rtc_cntl_clk_conf_reg_t clk_conf; - volatile rtc_cntl_slow_clk_conf_reg_t slow_clk_conf; - volatile rtc_cntl_sdio_conf_reg_t sdio_conf; - volatile rtc_cntl_bias_conf_reg_t bias_conf; - volatile rtc_cntl_regulator_reg_t regulator; - volatile rtc_cntl_regulator0_dbias_reg_t regulator0_dbias; - volatile rtc_cntl_regulator1_dbias_reg_t regulator1_dbias; - volatile rtc_cntl_dig_regulator_reg_t dig_regulator; - volatile rtc_cntl_dig_regulator_drvb_reg_t dig_regulator_drvb; - volatile rtc_cntl_dig_regulator0_dbias_reg_t dig_regulator0_dbias; - volatile rtc_cntl_dig_regulator1_dbias_reg_t dig_regulator1_dbias; - volatile rtc_cntl_pwc_reg_t rtc_pwc; - volatile rtc_cntl_dig_pwc_reg_t dig_pwc; - volatile rtc_cntl_dig_power_slave0_pd_reg_t dig_power_slave0_pd; - volatile rtc_cntl_dig_power_slave1_pd_reg_t dig_power_slave1_pd; - volatile rtc_cntl_dig_power_slave0_fpu_reg_t dig_power_slave0_fpu; - volatile rtc_cntl_dig_power_slave1_fpu_reg_t dig_power_slave1_fpu; - volatile rtc_cntl_dig_iso_reg_t dig_iso; - volatile rtc_cntl_wdtconfig0_reg_t wdt_config0; - union { - volatile rtc_cntl_wdtconfig1_reg_t wdtconfig1; - volatile uint32_t wdt_config1; - }; - union { - volatile rtc_cntl_wdtconfig2_reg_t wdtconfig2; - volatile uint32_t wdt_config2; - }; - union { - volatile rtc_cntl_wdtconfig3_reg_t wdtconfig3; - volatile uint32_t wdt_config3; - }; - union { - volatile rtc_cntl_wdtconfig4_reg_t wdtconfig4; - volatile uint32_t wdt_config4; - }; - volatile rtc_cntl_wdtfeed_reg_t wdt_feed; - union { - volatile rtc_cntl_wdtwprotect_reg_t wdtwprotect; - volatile uint32_t wdt_wprotect; - }; - volatile rtc_cntl_wdtreset_chip_reg_t wdtreset_chip; - volatile rtc_cntl_swd_conf_reg_t swd_conf; - volatile rtc_cntl_swd_wprotect_reg_t swd_wprotect; - volatile rtc_cntl_sw_cpu_stall_reg_t sw_cpu_stall; - volatile rtc_cntl_store_reg_t store4[4]; - volatile rtc_cntl_low_power_st_reg_t low_power_st; - volatile rtc_cntl_diag0_reg_t diag0; - volatile rtc_cntl_pad_hold_reg_t pad_hold; - volatile rtc_cntl_dig_pad_hold_reg_t dig_pad_hold; - volatile rtc_cntl_dig_pad_hold1_reg_t dig_pad_hold1; - volatile rtc_cntl_brown_out_reg_t brown_out; - volatile rtc_cntl_time_low1_reg_t time_low1; - volatile rtc_cntl_time_high1_reg_t time_high1; - volatile rtc_cntl_xtal32k_clk_factor_reg_t xtal32k_clk_factor; - volatile rtc_cntl_xtal32k_conf_reg_t xtal32k_conf; - volatile rtc_cntl_usb_conf_reg_t usb_conf; - volatile rtc_cntl_slp_reject_cause_reg_t slp_reject_cause; - volatile rtc_cntl_option1_reg_t option1; - volatile rtc_cntl_slp_wakeup_cause_reg_t slp_wakeup_cause; - volatile rtc_cntl_ulp_cp_timer_1_reg_t ulp_cp_timer_1; - volatile rtc_cntl_int_ena_w1ts_reg_t int_ena_w1ts; - volatile rtc_cntl_int_ena_w1tc_reg_t int_ena_w1tc; - volatile rtc_cntl_retention_ctrl_reg_t retention_ctrl; - volatile rtc_cntl_retention_ctrl1_reg_t retention_ctrl1; - volatile rtc_cntl_fib_sel_reg_t fib_sel; - volatile rtc_cntl_gpio_wakeup_reg_t gpio_wakeup; - volatile rtc_cntl_dbg_sel_reg_t dbg_sel; - volatile rtc_cntl_dbg_map_reg_t dbg_map; - volatile rtc_cntl_dbg_sar_sel_reg_t dbg_sar_sel; - volatile rtc_cntl_pg_ctrl_reg_t pg_ctrl; - volatile rtc_cntl_dcdc_ctrl0_reg_t dcdc_ctrl0; - volatile rtc_cntl_dcdc_ctrl1_reg_t dcdc_ctrl1; - volatile rtc_cntl_dcdc_ctrl2_reg_t dcdc_ctrl2; - volatile rtc_cntl_rc32k_ctrl_reg_t rc32k_ctrl; - volatile rtc_cntl_pll8m_reg_t pll8m; - uint32_t reserved_16c[36]; - volatile rtc_cntl_date_reg_t date; -} rtc_cntl_dev_t; - -extern rtc_cntl_dev_t RTCCNTL; - -#ifndef __cplusplus -_Static_assert(sizeof(rtc_cntl_dev_t) == 0x200, "Invalid size of rtc_cntl_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/sensitive_reg.h b/components/soc/esp32h4/include/rev2/soc/sensitive_reg.h deleted file mode 100644 index fe3e3eaa33..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/sensitive_reg.h +++ /dev/null @@ -1,3405 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SENSITIVE_ROM_TABLE_LOCK_REG register - * register description - */ -#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0) -/** SENSITIVE_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_ROM_TABLE_LOCK (BIT(0)) -#define SENSITIVE_ROM_TABLE_LOCK_M (SENSITIVE_ROM_TABLE_LOCK_V << SENSITIVE_ROM_TABLE_LOCK_S) -#define SENSITIVE_ROM_TABLE_LOCK_V 0x00000001U -#define SENSITIVE_ROM_TABLE_LOCK_S 0 - -/** SENSITIVE_ROM_TABLE_REG register - * register description - */ -#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4) -/** SENSITIVE_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SENSITIVE_ROM_TABLE 0xFFFFFFFFU -#define SENSITIVE_ROM_TABLE_M (SENSITIVE_ROM_TABLE_V << SENSITIVE_ROM_TABLE_S) -#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFFU -#define SENSITIVE_ROM_TABLE_S 0 - -/** SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG register - * register description - */ -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x8) -/** SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK (BIT(0)) -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M (SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V << SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S) -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V 0x00000001U -#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S 0 - -/** SENSITIVE_PRIVILEGE_MODE_SEL_REG register - * register description - */ -#define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0xc) -/** SENSITIVE_PRIVILEGE_MODE_SEL : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_PRIVILEGE_MODE_SEL (BIT(0)) -#define SENSITIVE_PRIVILEGE_MODE_SEL_M (SENSITIVE_PRIVILEGE_MODE_SEL_V << SENSITIVE_PRIVILEGE_MODE_SEL_S) -#define SENSITIVE_PRIVILEGE_MODE_SEL_V 0x00000001U -#define SENSITIVE_PRIVILEGE_MODE_SEL_S 0 - -/** SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG register - * register description - */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x10) -/** SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V << SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x00000001U -#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 - -/** SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG register - * register description - */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x14) -/** SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V << SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S) -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x00000001U -#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 - -/** SENSITIVE_INTERNAL_SRAM_USAGE_0_REG register - * register description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x18) -/** SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x00000001U -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 - -/** SENSITIVE_INTERNAL_SRAM_USAGE_1_REG register - * register description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x1c) -/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x00000001U -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0 -/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W; bitpos: [3:1]; default: 7; - * Need add description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007U -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S) -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x00000007U -#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1 - -/** SENSITIVE_INTERNAL_SRAM_USAGE_3_REG register - * register description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x20) -/** SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W; bitpos: [2:0]; default: 0; - * Need add description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007U -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S) -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x00000007U -#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0 -/** SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3)) -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V << SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S) -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x00000001U -#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3 - -/** SENSITIVE_INTERNAL_SRAM_USAGE_4_REG register - * register description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x24) -/** SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM (BIT(0)) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S) -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V 0x00000001U -#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S 0 - -/** SENSITIVE_CACHE_TAG_ACCESS_0_REG register - * register description - */ -#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x28) -/** SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (SENSITIVE_CACHE_TAG_ACCESS_LOCK_V << SENSITIVE_CACHE_TAG_ACCESS_LOCK_S) -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x00000001U -#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 - -/** SENSITIVE_CACHE_TAG_ACCESS_1_REG register - * register description - */ -#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x2c) -/** SENSITIVE_PRO_I_TAG_RD_ACS : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_I_TAG_RD_ACS_M (SENSITIVE_PRO_I_TAG_RD_ACS_V << SENSITIVE_PRO_I_TAG_RD_ACS_S) -#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x00000001U -#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 -/** SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_I_TAG_WR_ACS_M (SENSITIVE_PRO_I_TAG_WR_ACS_V << SENSITIVE_PRO_I_TAG_WR_ACS_S) -#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x00000001U -#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 -/** SENSITIVE_PRO_D_TAG_RD_ACS : R/W; bitpos: [2]; default: 1; - * Need add description - */ -#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) -#define SENSITIVE_PRO_D_TAG_RD_ACS_M (SENSITIVE_PRO_D_TAG_RD_ACS_V << SENSITIVE_PRO_D_TAG_RD_ACS_S) -#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x00000001U -#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 -/** SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1; - * Need add description - */ -#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) -#define SENSITIVE_PRO_D_TAG_WR_ACS_M (SENSITIVE_PRO_D_TAG_WR_ACS_V << SENSITIVE_PRO_D_TAG_WR_ACS_S) -#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x00000001U -#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 - -/** SENSITIVE_CACHE_MMU_ACCESS_0_REG register - * register description - */ -#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x30) -/** SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (SENSITIVE_CACHE_MMU_ACCESS_LOCK_V << SENSITIVE_CACHE_MMU_ACCESS_LOCK_S) -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x00000001U -#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 - -/** SENSITIVE_CACHE_MMU_ACCESS_1_REG register - * register description - */ -#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x34) -/** SENSITIVE_PRO_MMU_RD_ACS : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) -#define SENSITIVE_PRO_MMU_RD_ACS_M (SENSITIVE_PRO_MMU_RD_ACS_V << SENSITIVE_PRO_MMU_RD_ACS_S) -#define SENSITIVE_PRO_MMU_RD_ACS_V 0x00000001U -#define SENSITIVE_PRO_MMU_RD_ACS_S 0 -/** SENSITIVE_PRO_MMU_WR_ACS : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) -#define SENSITIVE_PRO_MMU_WR_ACS_M (SENSITIVE_PRO_MMU_WR_ACS_V << SENSITIVE_PRO_MMU_WR_ACS_S) -#define SENSITIVE_PRO_MMU_WR_ACS_V 0x00000001U -#define SENSITIVE_PRO_MMU_WR_ACS_S 1 - -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x38) -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x3c) -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x40) -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x44) -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: - * [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: - * [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: - * [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: - * [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x48) -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x4c) -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x50) -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x54) -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x58) -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x5c) -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: - * [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: - * [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: - * [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: - * [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x60) -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x64) -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x68) -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x6c) -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x70) -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x74) -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x78) -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x7c) -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: - * [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: - * [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: - * [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: - * [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: - * [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: - * [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: - * [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: - * [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x80) -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x84) -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: - * [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: - * [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: - * [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: - * [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: - * [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: - * [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: - * [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: - * [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x88) -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x8c) -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: - * [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: - * [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: - * [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: - * [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: - * [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: - * [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: - * [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: - * [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x90) -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x94) -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: - * [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: - * [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: - * [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: - * [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: - * [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: - * [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: - * [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: - * [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 - -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x98) -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 - -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x9c) -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 - -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xa0) -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: [2:1]; - * default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: [26:3]; - * default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFFU -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x00FFFFFFU -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 - -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG register - * register description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xa4) -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001U -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: [4:1]; - * default: 0; - * Need add description - */ -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000FU -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S) -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0x0000000FU -#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 - -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xa8) -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W; bitpos: [0]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xac) -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000FFU -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S) -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0x000000FFU -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 - -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xb0) -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000FFU -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0x000000FFU -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 - -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xb4) -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x00000003U -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 -/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000FFU -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S) -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0x000000FFU -#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 - -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0xb8) -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000FFU -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0x000000FFU -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 - -/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0xbc) -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 -/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000FFU -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S) -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0x000000FFU -#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 - -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xc0) -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xc4) -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [2:0]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [5:3]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [8:6]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [11:9]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W; - * bitpos: [14:12]; default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: [20:18]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 - -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG register - * register description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xc8) -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [2:0]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [5:3]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [8:6]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [11:9]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W; - * bitpos: [14:12]; default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 -/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: [20:18]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S) -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x00000007U -#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 - -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG register - * register description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xcc) -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x00000001U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 - -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG register - * register description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xd0) -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x00000001U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x00000001U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 - -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG register - * register description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xd4) -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x00000001U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [1]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO; bitpos: [2]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x00000001U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: [4:3]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003U -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 -/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: [28:5]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFFU -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x00FFFFFFU -#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 - -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xd8) -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xdc) -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: [25:24]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 -/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: [27:26]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S) -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x00000003U -#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 - -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG register - * register description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xe0) -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x00000001U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 - -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG register - * register description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xe4) -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x00000001U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x00000001U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 - -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG register - * register description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xe8) -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x00000001U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO; bitpos: [1]; default: - * 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x00000001U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: [3:2]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: [27:4]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFFU -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x00FFFFFFU -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 - -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG register - * register description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xec) -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001U -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 -/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: [4:1]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000000FU -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S) -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0x0000000FU -#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xf0) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xf4) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W; bitpos: [17:16]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xf8) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W; bitpos: [27:26]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W; bitpos: [29:28]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W; bitpos: [31:30]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xfc) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x100) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S 18 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC : R/W; bitpos: [21:20]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S 20 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC : R/W; bitpos: [23:22]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S 22 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S 26 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR : R/W; bitpos: [29:28]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S 28 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST : R/W; bitpos: [31:30]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S 30 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x104) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S 2 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W; bitpos: [7:6]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W; bitpos: [9:8]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 8 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W; bitpos: [11:10]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 12 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 18 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x108) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W; bitpos: [17:16]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x10c) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W; bitpos: [27:26]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W; bitpos: [29:28]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W; bitpos: [31:30]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x110) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x114) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S 18 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC : R/W; bitpos: [21:20]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S 20 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC : R/W; bitpos: [23:22]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S 22 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S 26 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR : R/W; bitpos: [29:28]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S 28 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST : R/W; bitpos: [31:30]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S 30 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x118) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S 2 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 4 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W; bitpos: [7:6]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W; bitpos: [9:8]; default: - * 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 8 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W; bitpos: [11:10]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 10 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 12 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 14 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 16 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 18 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x11c) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W; bitpos: [10:0]; - * default: 2047; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FFU -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x000007FFU -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W; bitpos: [21:11]; - * default: 2047; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FFU -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x000007FFU -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 - -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x120) -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W; bitpos: [2:0]; default: - * 7; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W; bitpos: [5:3]; default: - * 7; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W; bitpos: [8:6]; default: - * 7; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 -/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W; bitpos: [11:9]; - * default: 7; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S) -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124) -/** SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M (SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V << SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128) -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_2_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12c) -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 -/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x00000003U -#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_3_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_4_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_5_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_6_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13c) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_7_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_8_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_9_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S 0 - -/** SENSITIVE_REGION_PMS_CONSTRAIN_10_REG register - * register description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14c) -/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S) -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3FFFFFFFU -#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S 0 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x150) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x154) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x158) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO; bitpos: [1]; default: - * 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: [4:2]; default: - * 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x00000007U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [5]; default: - * 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO; bitpos: [7:6]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x15c) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFFU -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFFU -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x160) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x164) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x00000001U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; bitpos: [2:1]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO; bitpos: [4:3]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x00000003U -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 - -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG register - * register description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x168) -/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0]; - * default: 0; - * Need add description - */ -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFFU -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S) -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFFU -#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 - -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x16c) -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x00000001U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 - -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x170) -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S 2 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S 4 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S 6 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S 16 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S 18 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S 24 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S 26 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S 30 - -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x174) -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S 4 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S 6 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S 18 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S 28 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S 30 - -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x178) -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S 4 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S 10 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22 - -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x17c) -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S 6 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S 8 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 14 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S 16 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S 18 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC : R/W; bitpos: [21:20]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S 20 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S 22 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S 26 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S 28 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S 30 - -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x180) -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S 0 -/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S) -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S 2 - -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x184) -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x00000001U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 - -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x188) -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x00000001U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V 0x00000001U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S 1 - -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x18c) -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR (BIT(0)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x00000001U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO; bitpos: [2:1]; - * default: 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V 0x00000003U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S 1 -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: [5:3]; default: - * 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x00000007U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 3 -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [6]; default: - * 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x00000001U -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 6 - -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG register - * register description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x190) -/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xFFFFFFFFU -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S) -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xFFFFFFFFU -#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 - -/** SENSITIVE_CLOCK_GATE_REG register - * register description - */ -#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x194) -/** SENSITIVE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SENSITIVE_CLK_EN (BIT(0)) -#define SENSITIVE_CLK_EN_M (SENSITIVE_CLK_EN_V << SENSITIVE_CLK_EN_S) -#define SENSITIVE_CLK_EN_V 0x00000001U -#define SENSITIVE_CLK_EN_S 0 - -/** SENSITIVE_SENSITIVE_REG_DATE_REG register - * register description - */ -#define SENSITIVE_SENSITIVE_REG_DATE_REG (DR_REG_SENSITIVE_BASE + 0xffc) -/** SENSITIVE_SENSITIVE_REG_DATE : R/W; bitpos: [27:0]; default: 34636368; - * Need add description - */ -#define SENSITIVE_SENSITIVE_REG_DATE 0x0FFFFFFFU -#define SENSITIVE_SENSITIVE_REG_DATE_M (SENSITIVE_SENSITIVE_REG_DATE_V << SENSITIVE_SENSITIVE_REG_DATE_S) -#define SENSITIVE_SENSITIVE_REG_DATE_V 0x0FFFFFFFU -#define SENSITIVE_SENSITIVE_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/sensitive_struct.h b/components/soc/esp32h4/include/rev2/soc/sensitive_struct.h deleted file mode 100644 index 45bc6faa82..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/sensitive_struct.h +++ /dev/null @@ -1,2809 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of rom_table_lock register - * register description - */ -typedef union { - struct { - /** rom_table_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t rom_table_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_rom_table_lock_reg_t; - -/** Type of rom_table register - * register description - */ -typedef union { - struct { - /** rom_table : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t rom_table:32; - }; - uint32_t val; -} sensitive_rom_table_reg_t; - -/** Type of privilege_mode_sel_lock register - * register description - */ -typedef union { - struct { - /** privilege_mode_sel_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t privilege_mode_sel_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_privilege_mode_sel_lock_reg_t; - -/** Type of privilege_mode_sel register - * register description - */ -typedef union { - struct { - /** privilege_mode_sel : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t privilege_mode_sel:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_privilege_mode_sel_reg_t; - -/** Type of apb_peripheral_access_0 register - * register description - */ -typedef union { - struct { - /** apb_peripheral_access_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t apb_peripheral_access_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_apb_peripheral_access_0_reg_t; - -/** Type of apb_peripheral_access_1 register - * register description - */ -typedef union { - struct { - /** apb_peripheral_access_split_burst : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t apb_peripheral_access_split_burst:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_apb_peripheral_access_1_reg_t; - -/** Type of internal_sram_usage_0 register - * register description - */ -typedef union { - struct { - /** internal_sram_usage_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t internal_sram_usage_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_internal_sram_usage_0_reg_t; - -/** Type of internal_sram_usage_1 register - * register description - */ -typedef union { - struct { - /** internal_sram_usage_cpu_cache : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t internal_sram_usage_cpu_cache:1; - /** internal_sram_usage_cpu_sram : R/W; bitpos: [3:1]; default: 7; - * Need add description - */ - uint32_t internal_sram_usage_cpu_sram:3; - uint32_t reserved_4:28; - }; - uint32_t val; -} sensitive_internal_sram_usage_1_reg_t; - -/** Type of internal_sram_usage_3 register - * register description - */ -typedef union { - struct { - /** internal_sram_usage_mac_dump_sram : R/W; bitpos: [2:0]; default: 0; - * Need add description - */ - uint32_t internal_sram_usage_mac_dump_sram:3; - /** internal_sram_alloc_mac_dump : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t internal_sram_alloc_mac_dump:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} sensitive_internal_sram_usage_3_reg_t; - -/** Type of internal_sram_usage_4 register - * register description - */ -typedef union { - struct { - /** internal_sram_usage_log_sram : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t internal_sram_usage_log_sram:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_internal_sram_usage_4_reg_t; - -/** Type of cache_tag_access_0 register - * register description - */ -typedef union { - struct { - /** cache_tag_access_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cache_tag_access_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_cache_tag_access_0_reg_t; - -/** Type of cache_tag_access_1 register - * register description - */ -typedef union { - struct { - /** pro_i_tag_rd_acs : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t pro_i_tag_rd_acs:1; - /** pro_i_tag_wr_acs : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t pro_i_tag_wr_acs:1; - /** pro_d_tag_rd_acs : R/W; bitpos: [2]; default: 1; - * Need add description - */ - uint32_t pro_d_tag_rd_acs:1; - /** pro_d_tag_wr_acs : R/W; bitpos: [3]; default: 1; - * Need add description - */ - uint32_t pro_d_tag_wr_acs:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} sensitive_cache_tag_access_1_reg_t; - -/** Type of cache_mmu_access_0 register - * register description - */ -typedef union { - struct { - /** cache_mmu_access_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cache_mmu_access_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_cache_mmu_access_0_reg_t; - -/** Type of cache_mmu_access_1 register - * register description - */ -typedef union { - struct { - /** pro_mmu_rd_acs : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t pro_mmu_rd_acs:1; - /** pro_mmu_wr_acs : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t pro_mmu_wr_acs:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_cache_mmu_access_1_reg_t; - -/** Type of dma_apbperi_spi2_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_spi2_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_spi2_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_spi2_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_spi2_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_uchi0_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_uchi0_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_uchi0_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_uchi0_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_uchi0_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_i2s0_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_i2s0_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_i2s0_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_i2s0_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_i2s0_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_mac_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_mac_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_mac_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_mac_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_mac_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_backup_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_backup_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_backup_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_backup_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_backup_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_lc_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_lc_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_lc_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_lc_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_lc_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_aes_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_aes_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_aes_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_aes_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_aes_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_sha_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_sha_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_sha_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_sha_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_sha_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_adc_dac_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_adc_dac_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_adc_dac_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_adc_dac_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_adc_dac_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_ble_sec_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_ble_sec_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_ble_sec_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_ble_sec_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: - * 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_ble_sec_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_white_list_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_white_list_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_white_list_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_white_list_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_white_list_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_sdio_host_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_sdio_host_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_sdio_host_pms_constrain_0_reg_t; - -/** Type of dma_apbperi_sdio_host_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0:2; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1:2; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2:2; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0:2; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1:2; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2:2; - /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; - * default: 3; - * Need add description - */ - uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_dma_apbperi_sdio_host_pms_constrain_1_reg_t; - -/** Type of dma_apbperi_pms_monitor_0 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_pms_monitor_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_dma_apbperi_pms_monitor_0_reg_t; - -/** Type of dma_apbperi_pms_monitor_1 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_clr:1; - /** dma_apbperi_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_dma_apbperi_pms_monitor_1_reg_t; - -/** Type of dma_apbperi_pms_monitor_2 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_intr:1; - /** dma_apbperi_pms_monitor_violate_status_world : RO; bitpos: [2:1]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_status_world:2; - /** dma_apbperi_pms_monitor_violate_status_addr : RO; bitpos: [26:3]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_status_addr:24; - uint32_t reserved_27:5; - }; - uint32_t val; -} sensitive_dma_apbperi_pms_monitor_2_reg_t; - -/** Type of dma_apbperi_pms_monitor_3 register - * register description - */ -typedef union { - struct { - /** dma_apbperi_pms_monitor_violate_status_wr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_status_wr:1; - /** dma_apbperi_pms_monitor_violate_status_byteen : RO; bitpos: [4:1]; default: 0; - * Need add description - */ - uint32_t dma_apbperi_pms_monitor_violate_status_byteen:4; - uint32_t reserved_5:27; - }; - uint32_t val; -} sensitive_dma_apbperi_pms_monitor_3_reg_t; - -/** Type of core_x_iram0_dram0_dma_split_line_constrain_0 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_dram0_dma_split_line_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_x_iram0_dram0_dma_split_line_constrain_0_reg_t; - -/** Type of core_x_iram0_dram0_dma_split_line_constrain_1 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_dram0_dma_sram_category_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_dram0_dma_sram_category_0:2; - /** core_x_iram0_dram0_dma_sram_category_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_dram0_dma_sram_category_1:2; - /** core_x_iram0_dram0_dma_sram_category_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_dram0_dma_sram_category_2:2; - uint32_t reserved_6:8; - /** core_x_iram0_dram0_dma_sram_splitaddr : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_dram0_dma_sram_splitaddr:8; - uint32_t reserved_22:10; - }; - uint32_t val; -} sensitive_core_x_iram0_dram0_dma_split_line_constrain_1_reg_t; - -/** Type of core_x_iram0_dram0_dma_split_line_constrain_2 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_sram_line_0_category_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_0_category_0:2; - /** core_x_iram0_sram_line_0_category_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_0_category_1:2; - /** core_x_iram0_sram_line_0_category_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_0_category_2:2; - uint32_t reserved_6:8; - /** core_x_iram0_sram_line_0_splitaddr : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_0_splitaddr:8; - uint32_t reserved_22:10; - }; - uint32_t val; -} sensitive_core_x_iram0_dram0_dma_split_line_constrain_2_reg_t; - -/** Type of core_x_iram0_dram0_dma_split_line_constrain_3 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_sram_line_1_category_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_1_category_0:2; - /** core_x_iram0_sram_line_1_category_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_1_category_1:2; - /** core_x_iram0_sram_line_1_category_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_1_category_2:2; - uint32_t reserved_6:8; - /** core_x_iram0_sram_line_1_splitaddr : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_sram_line_1_splitaddr:8; - uint32_t reserved_22:10; - }; - uint32_t val; -} sensitive_core_x_iram0_dram0_dma_split_line_constrain_3_reg_t; - -/** Type of core_x_iram0_dram0_dma_split_line_constrain_4 register - * register description - */ -typedef union { - struct { - /** core_x_dram0_dma_sram_line_0_category_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_0_category_0:2; - /** core_x_dram0_dma_sram_line_0_category_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_0_category_1:2; - /** core_x_dram0_dma_sram_line_0_category_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_0_category_2:2; - uint32_t reserved_6:8; - /** core_x_dram0_dma_sram_line_0_splitaddr : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_0_splitaddr:8; - uint32_t reserved_22:10; - }; - uint32_t val; -} sensitive_core_x_iram0_dram0_dma_split_line_constrain_4_reg_t; - -/** Type of core_x_iram0_dram0_dma_split_line_constrain_5 register - * register description - */ -typedef union { - struct { - /** core_x_dram0_dma_sram_line_1_category_0 : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_1_category_0:2; - /** core_x_dram0_dma_sram_line_1_category_1 : R/W; bitpos: [3:2]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_1_category_1:2; - /** core_x_dram0_dma_sram_line_1_category_2 : R/W; bitpos: [5:4]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_1_category_2:2; - uint32_t reserved_6:8; - /** core_x_dram0_dma_sram_line_1_splitaddr : R/W; bitpos: [21:14]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_dma_sram_line_1_splitaddr:8; - uint32_t reserved_22:10; - }; - uint32_t val; -} sensitive_core_x_iram0_dram0_dma_split_line_constrain_5_reg_t; - -/** Type of core_x_iram0_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_x_iram0_pms_constrain_0_reg_t; - -/** Type of core_x_iram0_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [2:0]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0:3; - /** core_x_iram0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [5:3]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1:3; - /** core_x_iram0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [8:6]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2:3; - /** core_x_iram0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [11:9]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3:3; - /** core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0 : R/W; bitpos: - * [14:12]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:3; - uint32_t reserved_15:3; - /** core_x_iram0_pms_constrain_rom_world_1_pms : R/W; bitpos: [20:18]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_rom_world_1_pms:3; - uint32_t reserved_21:11; - }; - uint32_t val; -} sensitive_core_x_iram0_pms_constrain_1_reg_t; - -/** Type of core_x_iram0_pms_constrain_2 register - * register description - */ -typedef union { - struct { - /** core_x_iram0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [2:0]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0:3; - /** core_x_iram0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [5:3]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1:3; - /** core_x_iram0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [8:6]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2:3; - /** core_x_iram0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [11:9]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3:3; - /** core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0 : R/W; bitpos: - * [14:12]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:3; - uint32_t reserved_15:3; - /** core_x_iram0_pms_constrain_rom_world_0_pms : R/W; bitpos: [20:18]; default: 7; - * Need add description - */ - uint32_t core_x_iram0_pms_constrain_rom_world_0_pms:3; - uint32_t reserved_21:11; - }; - uint32_t val; -} sensitive_core_x_iram0_pms_constrain_2_reg_t; - -/** Type of core_0_iram0_pms_monitor_0 register - * register description - */ -typedef union { - struct { - /** core_0_iram0_pms_monitor_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_0_iram0_pms_monitor_0_reg_t; - -/** Type of core_0_iram0_pms_monitor_1 register - * register description - */ -typedef union { - struct { - /** core_0_iram0_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_clr:1; - /** core_0_iram0_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_core_0_iram0_pms_monitor_1_reg_t; - -/** Type of core_0_iram0_pms_monitor_2 register - * register description - */ -typedef union { - struct { - /** core_0_iram0_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_intr:1; - /** core_0_iram0_pms_monitor_violate_status_wr : RO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_status_wr:1; - /** core_0_iram0_pms_monitor_violate_status_loadstore : RO; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_status_loadstore:1; - /** core_0_iram0_pms_monitor_violate_status_world : RO; bitpos: [4:3]; default: 0; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_status_world:2; - /** core_0_iram0_pms_monitor_violate_status_addr : RO; bitpos: [28:5]; default: 0; - * Need add description - */ - uint32_t core_0_iram0_pms_monitor_violate_status_addr:24; - uint32_t reserved_29:3; - }; - uint32_t val; -} sensitive_core_0_iram0_pms_monitor_2_reg_t; - -/** Type of core_x_dram0_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** core_x_dram0_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_x_dram0_pms_constrain_0_reg_t; - -/** Type of core_x_dram0_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** core_x_dram0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0:2; - /** core_x_dram0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1:2; - /** core_x_dram0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2:2; - /** core_x_dram0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3:2; - uint32_t reserved_8:4; - /** core_x_dram0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0:2; - /** core_x_dram0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1:2; - /** core_x_dram0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2:2; - /** core_x_dram0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3:2; - uint32_t reserved_20:4; - /** core_x_dram0_pms_constrain_rom_world_0_pms : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_rom_world_0_pms:2; - /** core_x_dram0_pms_constrain_rom_world_1_pms : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_x_dram0_pms_constrain_rom_world_1_pms:2; - uint32_t reserved_28:4; - }; - uint32_t val; -} sensitive_core_x_dram0_pms_constrain_1_reg_t; - -/** Type of core_0_dram0_pms_monitor_0 register - * register description - */ -typedef union { - struct { - /** core_0_dram0_pms_monitor_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_0_dram0_pms_monitor_0_reg_t; - -/** Type of core_0_dram0_pms_monitor_1 register - * register description - */ -typedef union { - struct { - /** core_0_dram0_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_clr:1; - /** core_0_dram0_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_core_0_dram0_pms_monitor_1_reg_t; - -/** Type of core_0_dram0_pms_monitor_2 register - * register description - */ -typedef union { - struct { - /** core_0_dram0_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_intr:1; - /** core_0_dram0_pms_monitor_violate_status_lock : RO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_status_lock:1; - /** core_0_dram0_pms_monitor_violate_status_world : RO; bitpos: [3:2]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_status_world:2; - /** core_0_dram0_pms_monitor_violate_status_addr : RO; bitpos: [27:4]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_status_addr:24; - uint32_t reserved_28:4; - }; - uint32_t val; -} sensitive_core_0_dram0_pms_monitor_2_reg_t; - -/** Type of core_0_dram0_pms_monitor_3 register - * register description - */ -typedef union { - struct { - /** core_0_dram0_pms_monitor_violate_status_wr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_status_wr:1; - /** core_0_dram0_pms_monitor_violate_status_byteen : RO; bitpos: [4:1]; default: 0; - * Need add description - */ - uint32_t core_0_dram0_pms_monitor_violate_status_byteen:4; - uint32_t reserved_5:27; - }; - uint32_t val; -} sensitive_core_0_dram0_pms_monitor_3_reg_t; - -/** Type of core_0_pif_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_0_reg_t; - -/** Type of core_0_pif_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_0_uart : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_uart:2; - /** core_0_pif_pms_constrain_world_0_g0spi_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_g0spi_1:2; - /** core_0_pif_pms_constrain_world_0_g0spi_0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_g0spi_0:2; - /** core_0_pif_pms_constrain_world_0_gpio : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_gpio:2; - uint32_t reserved_8:2; - /** core_0_pif_pms_constrain_world_0_fe : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_fe:2; - uint32_t reserved_12:2; - /** core_0_pif_pms_constrain_world_0_rtc : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_rtc:2; - /** core_0_pif_pms_constrain_world_0_io_mux : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_io_mux:2; - /** core_0_pif_pms_constrain_world_0_wdg : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_wdg:2; - uint32_t reserved_20:4; - /** core_0_pif_pms_constrain_world_0_misc : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_misc:2; - /** core_0_pif_pms_constrain_world_0_i2c : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_i2c:2; - uint32_t reserved_28:2; - /** core_0_pif_pms_constrain_world_0_uart1 : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_uart1:2; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_1_reg_t; - -/** Type of core_0_pif_pms_constrain_2 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_0_bt : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_bt:2; - uint32_t reserved_2:2; - /** core_0_pif_pms_constrain_world_0_i2c_ext0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0:2; - /** core_0_pif_pms_constrain_world_0_uhci0 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_uhci0:2; - uint32_t reserved_8:2; - /** core_0_pif_pms_constrain_world_0_rmt : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_rmt:2; - uint32_t reserved_12:4; - /** core_0_pif_pms_constrain_world_0_ledc : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_ledc:2; - /** core_0_pif_pms_constrain_world_0_efuse : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_efuse:2; - uint32_t reserved_20:6; - /** core_0_pif_pms_constrain_world_0_timergroup : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_timergroup:2; - /** core_0_pif_pms_constrain_world_0_timergroup1 : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_timergroup1:2; - /** core_0_pif_pms_constrain_world_0_systimer : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_systimer:2; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_2_reg_t; - -/** Type of core_0_pif_pms_constrain_3 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_0_spi_2 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_spi_2:2; - uint32_t reserved_2:2; - /** core_0_pif_pms_constrain_world_0_apb_ctrl : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl:2; - uint32_t reserved_6:4; - /** core_0_pif_pms_constrain_world_0_twai : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_twai:2; - uint32_t reserved_12:2; - /** core_0_pif_pms_constrain_world_0_i2s1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_i2s1:2; - uint32_t reserved_16:6; - /** core_0_pif_pms_constrain_world_0_rwbt : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_rwbt:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_3_reg_t; - -/** Type of core_0_pif_pms_constrain_4 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** core_0_pif_pms_constrain_world_0_crypto_peri : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_crypto_peri:2; - /** core_0_pif_pms_constrain_world_0_crypto_dma : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_crypto_dma:2; - /** core_0_pif_pms_constrain_world_0_apb_adc : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_apb_adc:2; - uint32_t reserved_10:4; - /** core_0_pif_pms_constrain_world_0_usb_device : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_usb_device:2; - /** core_0_pif_pms_constrain_world_0_etm : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_etm:2; - /** core_0_pif_pms_constrain_world_0_timergroup3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_timergroup3:2; - /** core_0_pif_pms_constrain_world_0_ble_sec : R/W; bitpos: [21:20]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_ble_sec:2; - /** core_0_pif_pms_constrain_world_0_ieee802154mac : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_ieee802154mac:2; - uint32_t reserved_24:2; - /** core_0_pif_pms_constrain_world_0_coex : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_coex:2; - /** core_0_pif_pms_constrain_world_0_rtc_ble_tmr : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_rtc_ble_tmr:2; - /** core_0_pif_pms_constrain_world_0_clkrst : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_clkrst:2; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_4_reg_t; - -/** Type of core_0_pif_pms_constrain_5 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_0_pvt : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_pvt:2; - /** core_0_pif_pms_constrain_world_0_modem_widgets : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_modem_widgets:2; - /** core_0_pif_pms_constrain_world_0_system : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_system:2; - /** core_0_pif_pms_constrain_world_0_sensitive : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_sensitive:2; - /** core_0_pif_pms_constrain_world_0_interrupt : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_interrupt:2; - /** core_0_pif_pms_constrain_world_0_dma_copy : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_dma_copy:2; - /** core_0_pif_pms_constrain_world_0_cache_config : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_cache_config:2; - /** core_0_pif_pms_constrain_world_0_ad : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_ad:2; - /** core_0_pif_pms_constrain_world_0_dio : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_dio:2; - /** core_0_pif_pms_constrain_world_0_world_controller : R/W; bitpos: [19:18]; default: - * 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_0_world_controller:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_5_reg_t; - -/** Type of core_0_pif_pms_constrain_6 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_1_uart : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_uart:2; - /** core_0_pif_pms_constrain_world_1_g0spi_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_g0spi_1:2; - /** core_0_pif_pms_constrain_world_1_g0spi_0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_g0spi_0:2; - /** core_0_pif_pms_constrain_world_1_gpio : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_gpio:2; - uint32_t reserved_8:2; - /** core_0_pif_pms_constrain_world_1_fe : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_fe:2; - uint32_t reserved_12:2; - /** core_0_pif_pms_constrain_world_1_rtc : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_rtc:2; - /** core_0_pif_pms_constrain_world_1_io_mux : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_io_mux:2; - /** core_0_pif_pms_constrain_world_1_wdg : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_wdg:2; - uint32_t reserved_20:4; - /** core_0_pif_pms_constrain_world_1_misc : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_misc:2; - /** core_0_pif_pms_constrain_world_1_i2c : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_i2c:2; - uint32_t reserved_28:2; - /** core_0_pif_pms_constrain_world_1_uart1 : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_uart1:2; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_6_reg_t; - -/** Type of core_0_pif_pms_constrain_7 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_1_bt : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_bt:2; - uint32_t reserved_2:2; - /** core_0_pif_pms_constrain_world_1_i2c_ext0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0:2; - /** core_0_pif_pms_constrain_world_1_uhci0 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_uhci0:2; - uint32_t reserved_8:2; - /** core_0_pif_pms_constrain_world_1_rmt : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_rmt:2; - uint32_t reserved_12:4; - /** core_0_pif_pms_constrain_world_1_ledc : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_ledc:2; - /** core_0_pif_pms_constrain_world_1_efuse : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_efuse:2; - uint32_t reserved_20:6; - /** core_0_pif_pms_constrain_world_1_timergroup : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_timergroup:2; - /** core_0_pif_pms_constrain_world_1_timergroup1 : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_timergroup1:2; - /** core_0_pif_pms_constrain_world_1_systimer : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_systimer:2; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_7_reg_t; - -/** Type of core_0_pif_pms_constrain_8 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_1_spi_2 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_spi_2:2; - uint32_t reserved_2:2; - /** core_0_pif_pms_constrain_world_1_apb_ctrl : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl:2; - uint32_t reserved_6:4; - /** core_0_pif_pms_constrain_world_1_twai : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_twai:2; - uint32_t reserved_12:2; - /** core_0_pif_pms_constrain_world_1_i2s1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_i2s1:2; - uint32_t reserved_16:6; - /** core_0_pif_pms_constrain_world_1_rwbt : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_rwbt:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_8_reg_t; - -/** Type of core_0_pif_pms_constrain_9 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** core_0_pif_pms_constrain_world_1_crypto_peri : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_crypto_peri:2; - /** core_0_pif_pms_constrain_world_1_crypto_dma : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_crypto_dma:2; - /** core_0_pif_pms_constrain_world_1_apb_adc : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_apb_adc:2; - uint32_t reserved_10:4; - /** core_0_pif_pms_constrain_world_1_usb_device : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_usb_device:2; - /** core_0_pif_pms_constrain_world_1_etm : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_etm:2; - /** core_0_pif_pms_constrain_world_1_timergroup3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_timergroup3:2; - /** core_0_pif_pms_constrain_world_1_ble_sec : R/W; bitpos: [21:20]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_ble_sec:2; - /** core_0_pif_pms_constrain_world_1_ieee802154mac : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_ieee802154mac:2; - uint32_t reserved_24:2; - /** core_0_pif_pms_constrain_world_1_coex : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_coex:2; - /** core_0_pif_pms_constrain_world_1_rtc_ble_tmr : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_rtc_ble_tmr:2; - /** core_0_pif_pms_constrain_world_1_clkrst : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_clkrst:2; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_9_reg_t; - -/** Type of core_0_pif_pms_constrain_10 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_world_1_pvt : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_pvt:2; - /** core_0_pif_pms_constrain_world_1_modem_widgets : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_modem_widgets:2; - /** core_0_pif_pms_constrain_world_1_system : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_system:2; - /** core_0_pif_pms_constrain_world_1_sensitive : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_sensitive:2; - /** core_0_pif_pms_constrain_world_1_interrupt : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_interrupt:2; - /** core_0_pif_pms_constrain_world_1_dma_copy : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_dma_copy:2; - /** core_0_pif_pms_constrain_world_1_cache_config : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_cache_config:2; - /** core_0_pif_pms_constrain_world_1_ad : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_ad:2; - /** core_0_pif_pms_constrain_world_1_dio : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_dio:2; - /** core_0_pif_pms_constrain_world_1_world_controller : R/W; bitpos: [19:18]; default: - * 3; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_world_1_world_controller:2; - uint32_t reserved_20:12; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_10_reg_t; - -/** Type of core_0_pif_pms_constrain_11 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_rtcfast_spltaddr_world_0 : R/W; bitpos: [10:0]; default: - * 2047; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:11; - /** core_0_pif_pms_constrain_rtcfast_spltaddr_world_1 : R/W; bitpos: [21:11]; default: - * 2047; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:11; - uint32_t reserved_22:10; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_11_reg_t; - -/** Type of core_0_pif_pms_constrain_12 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_constrain_rtcfast_world_0_l : R/W; bitpos: [2:0]; default: 7; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l:3; - /** core_0_pif_pms_constrain_rtcfast_world_0_h : R/W; bitpos: [5:3]; default: 7; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h:3; - /** core_0_pif_pms_constrain_rtcfast_world_1_l : R/W; bitpos: [8:6]; default: 7; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l:3; - /** core_0_pif_pms_constrain_rtcfast_world_1_h : R/W; bitpos: [11:9]; default: 7; - * Need add description - */ - uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h:3; - uint32_t reserved_12:20; - }; - uint32_t val; -} sensitive_core_0_pif_pms_constrain_12_reg_t; - -/** Type of region_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_region_pms_constrain_0_reg_t; - -/** Type of region_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_world_0_area_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_0:2; - /** region_pms_constrain_world_0_area_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_1:2; - /** region_pms_constrain_world_0_area_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_2:2; - /** region_pms_constrain_world_0_area_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_3:2; - /** region_pms_constrain_world_0_area_4 : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_4:2; - /** region_pms_constrain_world_0_area_5 : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_5:2; - /** region_pms_constrain_world_0_area_6 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_0_area_6:2; - uint32_t reserved_14:18; - }; - uint32_t val; -} sensitive_region_pms_constrain_1_reg_t; - -/** Type of region_pms_constrain_2 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_world_1_area_0 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_0:2; - /** region_pms_constrain_world_1_area_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_1:2; - /** region_pms_constrain_world_1_area_2 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_2:2; - /** region_pms_constrain_world_1_area_3 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_3:2; - /** region_pms_constrain_world_1_area_4 : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_4:2; - /** region_pms_constrain_world_1_area_5 : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_5:2; - /** region_pms_constrain_world_1_area_6 : R/W; bitpos: [13:12]; default: 3; - * Need add description - */ - uint32_t region_pms_constrain_world_1_area_6:2; - uint32_t reserved_14:18; - }; - uint32_t val; -} sensitive_region_pms_constrain_2_reg_t; - -/** Type of region_pms_constrain_3 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_0 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_0:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_3_reg_t; - -/** Type of region_pms_constrain_4 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_1 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_1:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_4_reg_t; - -/** Type of region_pms_constrain_5 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_2 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_2:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_5_reg_t; - -/** Type of region_pms_constrain_6 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_3 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_3:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_6_reg_t; - -/** Type of region_pms_constrain_7 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_4 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_4:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_7_reg_t; - -/** Type of region_pms_constrain_8 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_5 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_5:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_8_reg_t; - -/** Type of region_pms_constrain_9 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_6 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_6:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_9_reg_t; - -/** Type of region_pms_constrain_10 register - * register description - */ -typedef union { - struct { - /** region_pms_constrain_addr_7 : R/W; bitpos: [29:0]; default: 0; - * Need add description - */ - uint32_t region_pms_constrain_addr_7:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} sensitive_region_pms_constrain_10_reg_t; - -/** Type of core_0_pif_pms_monitor_0 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_0_reg_t; - -/** Type of core_0_pif_pms_monitor_1 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_clr:1; - /** core_0_pif_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_1_reg_t; - -/** Type of core_0_pif_pms_monitor_2 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_intr:1; - /** core_0_pif_pms_monitor_violate_status_hport_0 : RO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_status_hport_0:1; - /** core_0_pif_pms_monitor_violate_status_hsize : RO; bitpos: [4:2]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_status_hsize:3; - /** core_0_pif_pms_monitor_violate_status_hwrite : RO; bitpos: [5]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_status_hwrite:1; - /** core_0_pif_pms_monitor_violate_status_hworld : RO; bitpos: [7:6]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_status_hworld:2; - uint32_t reserved_8:24; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_2_reg_t; - -/** Type of core_0_pif_pms_monitor_3 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_violate_status_haddr : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_violate_status_haddr:32; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_3_reg_t; - -/** Type of core_0_pif_pms_monitor_4 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_nonword_violate_clr : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_nonword_violate_clr:1; - /** core_0_pif_pms_monitor_nonword_violate_en : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_nonword_violate_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_4_reg_t; - -/** Type of core_0_pif_pms_monitor_5 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_nonword_violate_intr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_nonword_violate_intr:1; - /** core_0_pif_pms_monitor_nonword_violate_status_hsize : RO; bitpos: [2:1]; default: 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_nonword_violate_status_hsize:2; - /** core_0_pif_pms_monitor_nonword_violate_status_hworld : RO; bitpos: [4:3]; default: - * 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_nonword_violate_status_hworld:2; - uint32_t reserved_5:27; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_5_reg_t; - -/** Type of core_0_pif_pms_monitor_6 register - * register description - */ -typedef union { - struct { - /** core_0_pif_pms_monitor_nonword_violate_status_haddr : RO; bitpos: [31:0]; default: - * 0; - * Need add description - */ - uint32_t core_0_pif_pms_monitor_nonword_violate_status_haddr:32; - }; - uint32_t val; -} sensitive_core_0_pif_pms_monitor_6_reg_t; - -/** Type of backup_bus_pms_constrain_0 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_constrain_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_constrain_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_backup_bus_pms_constrain_0_reg_t; - -/** Type of backup_bus_pms_constrain_1 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_constrain_uart : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_uart:2; - /** backup_bus_pms_constrain_g0spi_1 : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_g0spi_1:2; - /** backup_bus_pms_constrain_g0spi_0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_g0spi_0:2; - /** backup_bus_pms_constrain_gpio : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_gpio:2; - uint32_t reserved_8:2; - /** backup_bus_pms_constrain_fe : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_fe:2; - uint32_t reserved_12:2; - /** backup_bus_pms_constrain_rtc : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_rtc:2; - /** backup_bus_pms_constrain_io_mux : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_io_mux:2; - /** backup_bus_pms_constrain_wdg : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_wdg:2; - uint32_t reserved_20:4; - /** backup_bus_pms_constrain_misc : R/W; bitpos: [25:24]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_misc:2; - /** backup_bus_pms_constrain_i2c : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_i2c:2; - uint32_t reserved_28:2; - /** backup_bus_pms_constrain_uart1 : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_uart1:2; - }; - uint32_t val; -} sensitive_backup_bus_pms_constrain_1_reg_t; - -/** Type of backup_bus_pms_constrain_2 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_constrain_bt : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_bt:2; - uint32_t reserved_2:2; - /** backup_bus_pms_constrain_i2c_ext0 : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_i2c_ext0:2; - /** backup_bus_pms_constrain_uhci0 : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_uhci0:2; - uint32_t reserved_8:2; - /** backup_bus_pms_constrain_rmt : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_rmt:2; - uint32_t reserved_12:4; - /** backup_bus_pms_constrain_ledc : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_ledc:2; - /** backup_bus_pms_constrain_efuse : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_efuse:2; - uint32_t reserved_20:6; - /** backup_bus_pms_constrain_timergroup : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_timergroup:2; - /** backup_bus_pms_constrain_timergroup1 : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_timergroup1:2; - /** backup_bus_pms_constrain_systimer : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_systimer:2; - }; - uint32_t val; -} sensitive_backup_bus_pms_constrain_2_reg_t; - -/** Type of backup_bus_pms_constrain_3 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_constrain_spi_2 : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_spi_2:2; - uint32_t reserved_2:2; - /** backup_bus_pms_constrain_apb_ctrl : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_apb_ctrl:2; - uint32_t reserved_6:4; - /** backup_bus_pms_constrain_twai : R/W; bitpos: [11:10]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_twai:2; - uint32_t reserved_12:2; - /** backup_bus_pms_constrain_i2s1 : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_i2s1:2; - uint32_t reserved_16:6; - /** backup_bus_pms_constrain_rwbt : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_rwbt:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} sensitive_backup_bus_pms_constrain_3_reg_t; - -/** Type of backup_bus_pms_constrain_4 register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** backup_bus_pms_constrain_crypto_peri : R/W; bitpos: [5:4]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_crypto_peri:2; - /** backup_bus_pms_constrain_crypto_dma : R/W; bitpos: [7:6]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_crypto_dma:2; - /** backup_bus_pms_constrain_apb_adc : R/W; bitpos: [9:8]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_apb_adc:2; - uint32_t reserved_10:4; - /** backup_bus_pms_constrain_usb_device : R/W; bitpos: [15:14]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_usb_device:2; - /** backup_bus_pms_constrain_etm : R/W; bitpos: [17:16]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_etm:2; - /** backup_bus_pms_constrain_timergroup3 : R/W; bitpos: [19:18]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_timergroup3:2; - /** backup_bus_pms_constrain_ble_sec : R/W; bitpos: [21:20]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_ble_sec:2; - /** backup_bus_pms_constrain_ieee802154mac : R/W; bitpos: [23:22]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_ieee802154mac:2; - uint32_t reserved_24:2; - /** backup_bus_pms_constrain_coex : R/W; bitpos: [27:26]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_coex:2; - /** backup_bus_pms_constrain_rtc_ble_tmr : R/W; bitpos: [29:28]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_rtc_ble_tmr:2; - /** backup_bus_pms_constrain_clkrst : R/W; bitpos: [31:30]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_clkrst:2; - }; - uint32_t val; -} sensitive_backup_bus_pms_constrain_4_reg_t; - -/** Type of backup_bus_pms_constrain_5 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_constrain_pvt : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_pvt:2; - /** backup_bus_pms_constrain_modem_widgets : R/W; bitpos: [3:2]; default: 3; - * Need add description - */ - uint32_t backup_bus_pms_constrain_modem_widgets:2; - uint32_t reserved_4:28; - }; - uint32_t val; -} sensitive_backup_bus_pms_constrain_5_reg_t; - -/** Type of backup_bus_pms_monitor_0 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_monitor_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_monitor_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_backup_bus_pms_monitor_0_reg_t; - -/** Type of backup_bus_pms_monitor_1 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_clr:1; - /** backup_bus_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} sensitive_backup_bus_pms_monitor_1_reg_t; - -/** Type of backup_bus_pms_monitor_2 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_intr:1; - /** backup_bus_pms_monitor_violate_status_htrans : RO; bitpos: [2:1]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_status_htrans:2; - /** backup_bus_pms_monitor_violate_status_hsize : RO; bitpos: [5:3]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_status_hsize:3; - /** backup_bus_pms_monitor_violate_status_hwrite : RO; bitpos: [6]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_status_hwrite:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} sensitive_backup_bus_pms_monitor_2_reg_t; - -/** Type of backup_bus_pms_monitor_3 register - * register description - */ -typedef union { - struct { - /** backup_bus_pms_monitor_violate_haddr : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t backup_bus_pms_monitor_violate_haddr:32; - }; - uint32_t val; -} sensitive_backup_bus_pms_monitor_3_reg_t; - -/** Type of clock_gate register - * register description - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} sensitive_clock_gate_reg_t; - -/** Type of sensitive_reg_date register - * register description - */ -typedef union { - struct { - /** sensitive_reg_date : R/W; bitpos: [27:0]; default: 34636368; - * Need add description - */ - uint32_t sensitive_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} sensitive_sensitive_reg_date_reg_t; - - -typedef struct { - volatile sensitive_rom_table_lock_reg_t rom_table_lock; - volatile sensitive_rom_table_reg_t rom_table; - volatile sensitive_privilege_mode_sel_lock_reg_t privilege_mode_sel_lock; - volatile sensitive_privilege_mode_sel_reg_t privilege_mode_sel; - volatile sensitive_apb_peripheral_access_0_reg_t apb_peripheral_access_0; - volatile sensitive_apb_peripheral_access_1_reg_t apb_peripheral_access_1; - volatile sensitive_internal_sram_usage_0_reg_t internal_sram_usage_0; - volatile sensitive_internal_sram_usage_1_reg_t internal_sram_usage_1; - volatile sensitive_internal_sram_usage_3_reg_t internal_sram_usage_3; - volatile sensitive_internal_sram_usage_4_reg_t internal_sram_usage_4; - volatile sensitive_cache_tag_access_0_reg_t cache_tag_access_0; - volatile sensitive_cache_tag_access_1_reg_t cache_tag_access_1; - volatile sensitive_cache_mmu_access_0_reg_t cache_mmu_access_0; - volatile sensitive_cache_mmu_access_1_reg_t cache_mmu_access_1; - volatile sensitive_dma_apbperi_spi2_pms_constrain_0_reg_t dma_apbperi_spi2_pms_constrain_0; - volatile sensitive_dma_apbperi_spi2_pms_constrain_1_reg_t dma_apbperi_spi2_pms_constrain_1; - volatile sensitive_dma_apbperi_uchi0_pms_constrain_0_reg_t dma_apbperi_uchi0_pms_constrain_0; - volatile sensitive_dma_apbperi_uchi0_pms_constrain_1_reg_t dma_apbperi_uchi0_pms_constrain_1; - volatile sensitive_dma_apbperi_i2s0_pms_constrain_0_reg_t dma_apbperi_i2s0_pms_constrain_0; - volatile sensitive_dma_apbperi_i2s0_pms_constrain_1_reg_t dma_apbperi_i2s0_pms_constrain_1; - volatile sensitive_dma_apbperi_mac_pms_constrain_0_reg_t dma_apbperi_mac_pms_constrain_0; - volatile sensitive_dma_apbperi_mac_pms_constrain_1_reg_t dma_apbperi_mac_pms_constrain_1; - volatile sensitive_dma_apbperi_backup_pms_constrain_0_reg_t dma_apbperi_backup_pms_constrain_0; - volatile sensitive_dma_apbperi_backup_pms_constrain_1_reg_t dma_apbperi_backup_pms_constrain_1; - volatile sensitive_dma_apbperi_lc_pms_constrain_0_reg_t dma_apbperi_lc_pms_constrain_0; - volatile sensitive_dma_apbperi_lc_pms_constrain_1_reg_t dma_apbperi_lc_pms_constrain_1; - volatile sensitive_dma_apbperi_aes_pms_constrain_0_reg_t dma_apbperi_aes_pms_constrain_0; - volatile sensitive_dma_apbperi_aes_pms_constrain_1_reg_t dma_apbperi_aes_pms_constrain_1; - volatile sensitive_dma_apbperi_sha_pms_constrain_0_reg_t dma_apbperi_sha_pms_constrain_0; - volatile sensitive_dma_apbperi_sha_pms_constrain_1_reg_t dma_apbperi_sha_pms_constrain_1; - volatile sensitive_dma_apbperi_adc_dac_pms_constrain_0_reg_t dma_apbperi_adc_dac_pms_constrain_0; - volatile sensitive_dma_apbperi_adc_dac_pms_constrain_1_reg_t dma_apbperi_adc_dac_pms_constrain_1; - volatile sensitive_dma_apbperi_ble_sec_pms_constrain_0_reg_t dma_apbperi_ble_sec_pms_constrain_0; - volatile sensitive_dma_apbperi_ble_sec_pms_constrain_1_reg_t dma_apbperi_ble_sec_pms_constrain_1; - volatile sensitive_dma_apbperi_white_list_pms_constrain_0_reg_t dma_apbperi_white_list_pms_constrain_0; - volatile sensitive_dma_apbperi_white_list_pms_constrain_1_reg_t dma_apbperi_white_list_pms_constrain_1; - volatile sensitive_dma_apbperi_sdio_host_pms_constrain_0_reg_t dma_apbperi_sdio_host_pms_constrain_0; - volatile sensitive_dma_apbperi_sdio_host_pms_constrain_1_reg_t dma_apbperi_sdio_host_pms_constrain_1; - volatile sensitive_dma_apbperi_pms_monitor_0_reg_t dma_apbperi_pms_monitor_0; - volatile sensitive_dma_apbperi_pms_monitor_1_reg_t dma_apbperi_pms_monitor_1; - volatile sensitive_dma_apbperi_pms_monitor_2_reg_t dma_apbperi_pms_monitor_2; - volatile sensitive_dma_apbperi_pms_monitor_3_reg_t dma_apbperi_pms_monitor_3; - volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_0_reg_t core_x_iram0_dram0_dma_split_line_constrain_0; - volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_1_reg_t core_x_iram0_dram0_dma_split_line_constrain_1; - volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_2_reg_t core_x_iram0_dram0_dma_split_line_constrain_2; - volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_3_reg_t core_x_iram0_dram0_dma_split_line_constrain_3; - volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_4_reg_t core_x_iram0_dram0_dma_split_line_constrain_4; - volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_5_reg_t core_x_iram0_dram0_dma_split_line_constrain_5; - volatile sensitive_core_x_iram0_pms_constrain_0_reg_t core_x_iram0_pms_constrain_0; - volatile sensitive_core_x_iram0_pms_constrain_1_reg_t core_x_iram0_pms_constrain_1; - volatile sensitive_core_x_iram0_pms_constrain_2_reg_t core_x_iram0_pms_constrain_2; - volatile sensitive_core_0_iram0_pms_monitor_0_reg_t core_0_iram0_pms_monitor_0; - volatile sensitive_core_0_iram0_pms_monitor_1_reg_t core_0_iram0_pms_monitor_1; - volatile sensitive_core_0_iram0_pms_monitor_2_reg_t core_0_iram0_pms_monitor_2; - volatile sensitive_core_x_dram0_pms_constrain_0_reg_t core_x_dram0_pms_constrain_0; - volatile sensitive_core_x_dram0_pms_constrain_1_reg_t core_x_dram0_pms_constrain_1; - volatile sensitive_core_0_dram0_pms_monitor_0_reg_t core_0_dram0_pms_monitor_0; - volatile sensitive_core_0_dram0_pms_monitor_1_reg_t core_0_dram0_pms_monitor_1; - volatile sensitive_core_0_dram0_pms_monitor_2_reg_t core_0_dram0_pms_monitor_2; - volatile sensitive_core_0_dram0_pms_monitor_3_reg_t core_0_dram0_pms_monitor_3; - volatile sensitive_core_0_pif_pms_constrain_0_reg_t core_0_pif_pms_constrain_0; - volatile sensitive_core_0_pif_pms_constrain_1_reg_t core_0_pif_pms_constrain_1; - volatile sensitive_core_0_pif_pms_constrain_2_reg_t core_0_pif_pms_constrain_2; - volatile sensitive_core_0_pif_pms_constrain_3_reg_t core_0_pif_pms_constrain_3; - volatile sensitive_core_0_pif_pms_constrain_4_reg_t core_0_pif_pms_constrain_4; - volatile sensitive_core_0_pif_pms_constrain_5_reg_t core_0_pif_pms_constrain_5; - volatile sensitive_core_0_pif_pms_constrain_6_reg_t core_0_pif_pms_constrain_6; - volatile sensitive_core_0_pif_pms_constrain_7_reg_t core_0_pif_pms_constrain_7; - volatile sensitive_core_0_pif_pms_constrain_8_reg_t core_0_pif_pms_constrain_8; - volatile sensitive_core_0_pif_pms_constrain_9_reg_t core_0_pif_pms_constrain_9; - volatile sensitive_core_0_pif_pms_constrain_10_reg_t core_0_pif_pms_constrain_10; - volatile sensitive_core_0_pif_pms_constrain_11_reg_t core_0_pif_pms_constrain_11; - volatile sensitive_core_0_pif_pms_constrain_12_reg_t core_0_pif_pms_constrain_12; - volatile sensitive_region_pms_constrain_0_reg_t region_pms_constrain_0; - volatile sensitive_region_pms_constrain_1_reg_t region_pms_constrain_1; - volatile sensitive_region_pms_constrain_2_reg_t region_pms_constrain_2; - volatile sensitive_region_pms_constrain_3_reg_t region_pms_constrain_3; - volatile sensitive_region_pms_constrain_4_reg_t region_pms_constrain_4; - volatile sensitive_region_pms_constrain_5_reg_t region_pms_constrain_5; - volatile sensitive_region_pms_constrain_6_reg_t region_pms_constrain_6; - volatile sensitive_region_pms_constrain_7_reg_t region_pms_constrain_7; - volatile sensitive_region_pms_constrain_8_reg_t region_pms_constrain_8; - volatile sensitive_region_pms_constrain_9_reg_t region_pms_constrain_9; - volatile sensitive_region_pms_constrain_10_reg_t region_pms_constrain_10; - volatile sensitive_core_0_pif_pms_monitor_0_reg_t core_0_pif_pms_monitor_0; - volatile sensitive_core_0_pif_pms_monitor_1_reg_t core_0_pif_pms_monitor_1; - volatile sensitive_core_0_pif_pms_monitor_2_reg_t core_0_pif_pms_monitor_2; - volatile sensitive_core_0_pif_pms_monitor_3_reg_t core_0_pif_pms_monitor_3; - volatile sensitive_core_0_pif_pms_monitor_4_reg_t core_0_pif_pms_monitor_4; - volatile sensitive_core_0_pif_pms_monitor_5_reg_t core_0_pif_pms_monitor_5; - volatile sensitive_core_0_pif_pms_monitor_6_reg_t core_0_pif_pms_monitor_6; - volatile sensitive_backup_bus_pms_constrain_0_reg_t backup_bus_pms_constrain_0; - volatile sensitive_backup_bus_pms_constrain_1_reg_t backup_bus_pms_constrain_1; - volatile sensitive_backup_bus_pms_constrain_2_reg_t backup_bus_pms_constrain_2; - volatile sensitive_backup_bus_pms_constrain_3_reg_t backup_bus_pms_constrain_3; - volatile sensitive_backup_bus_pms_constrain_4_reg_t backup_bus_pms_constrain_4; - volatile sensitive_backup_bus_pms_constrain_5_reg_t backup_bus_pms_constrain_5; - volatile sensitive_backup_bus_pms_monitor_0_reg_t backup_bus_pms_monitor_0; - volatile sensitive_backup_bus_pms_monitor_1_reg_t backup_bus_pms_monitor_1; - volatile sensitive_backup_bus_pms_monitor_2_reg_t backup_bus_pms_monitor_2; - volatile sensitive_backup_bus_pms_monitor_3_reg_t backup_bus_pms_monitor_3; - volatile sensitive_clock_gate_reg_t clock_gate; - uint32_t reserved_198[921]; - volatile sensitive_sensitive_reg_date_reg_t sensitive_reg_date; -} sensitive_dev_t; - -extern sensitive_dev_t SENSITIVE; - -#ifndef __cplusplus -_Static_assert(sizeof(sensitive_dev_t) == 0x1000, "Invalid size of sensitive_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/syscon_reg.h b/components/soc/esp32h4/include/rev2/soc/syscon_reg.h deleted file mode 100644 index c49615526a..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/syscon_reg.h +++ /dev/null @@ -1,657 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SYSCON_WIFI_BB_CFG_REG register - * register description - */ -#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xc) -/** SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_WIFI_BB_CFG 0xFFFFFFFFU -#define SYSCON_WIFI_BB_CFG_M (SYSCON_WIFI_BB_CFG_V << SYSCON_WIFI_BB_CFG_S) -#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU -#define SYSCON_WIFI_BB_CFG_S 0 - -/** SYSCON_WIFI_BB_CFG_2_REG register - * register description - */ -#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10) -/** SYSCON_WIFI_BB_CFG_2 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFFU -#define SYSCON_WIFI_BB_CFG_2_M (SYSCON_WIFI_BB_CFG_2_V << SYSCON_WIFI_BB_CFG_2_S) -#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFFU -#define SYSCON_WIFI_BB_CFG_2_S 0 - -/** SYSCON_HOST_INF_SEL_REG register - * register description - */ -#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1c) -/** SYSCON_PERI_IO_SWAP : R/W; bitpos: [7:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_IO_SWAP 0x000000FFU -#define SYSCON_PERI_IO_SWAP_M (SYSCON_PERI_IO_SWAP_V << SYSCON_PERI_IO_SWAP_S) -#define SYSCON_PERI_IO_SWAP_V 0x000000FFU -#define SYSCON_PERI_IO_SWAP_S 0 - -/** SYSCON_EXT_MEM_PMS_LOCK_REG register - * register description - */ -#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20) -/** SYSCON_EXT_MEM_PMS_LOCK : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) -#define SYSCON_EXT_MEM_PMS_LOCK_M (SYSCON_EXT_MEM_PMS_LOCK_V << SYSCON_EXT_MEM_PMS_LOCK_S) -#define SYSCON_EXT_MEM_PMS_LOCK_V 0x00000001U -#define SYSCON_EXT_MEM_PMS_LOCK_S 0 - -/** SYSCON_FLASH_ACE0_ATTR_REG register - * register description - */ -#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28) -/** SYSCON_FLASH_ACE0_ATTR : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SYSCON_FLASH_ACE0_ATTR 0x00000003U -#define SYSCON_FLASH_ACE0_ATTR_M (SYSCON_FLASH_ACE0_ATTR_V << SYSCON_FLASH_ACE0_ATTR_S) -#define SYSCON_FLASH_ACE0_ATTR_V 0x00000003U -#define SYSCON_FLASH_ACE0_ATTR_S 0 - -/** SYSCON_FLASH_ACE1_ATTR_REG register - * register description - */ -#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2c) -/** SYSCON_FLASH_ACE1_ATTR : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SYSCON_FLASH_ACE1_ATTR 0x00000003U -#define SYSCON_FLASH_ACE1_ATTR_M (SYSCON_FLASH_ACE1_ATTR_V << SYSCON_FLASH_ACE1_ATTR_S) -#define SYSCON_FLASH_ACE1_ATTR_V 0x00000003U -#define SYSCON_FLASH_ACE1_ATTR_S 0 - -/** SYSCON_FLASH_ACE2_ATTR_REG register - * register description - */ -#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30) -/** SYSCON_FLASH_ACE2_ATTR : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SYSCON_FLASH_ACE2_ATTR 0x00000003U -#define SYSCON_FLASH_ACE2_ATTR_M (SYSCON_FLASH_ACE2_ATTR_V << SYSCON_FLASH_ACE2_ATTR_S) -#define SYSCON_FLASH_ACE2_ATTR_V 0x00000003U -#define SYSCON_FLASH_ACE2_ATTR_S 0 - -/** SYSCON_FLASH_ACE3_ATTR_REG register - * register description - */ -#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34) -/** SYSCON_FLASH_ACE3_ATTR : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SYSCON_FLASH_ACE3_ATTR 0x00000003U -#define SYSCON_FLASH_ACE3_ATTR_M (SYSCON_FLASH_ACE3_ATTR_V << SYSCON_FLASH_ACE3_ATTR_S) -#define SYSCON_FLASH_ACE3_ATTR_V 0x00000003U -#define SYSCON_FLASH_ACE3_ATTR_S 0 - -/** SYSCON_FLASH_ACE0_ADDR_REG register - * register description - */ -#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38) -/** SYSCON_FLASH_ACE0_ADDR_S : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFFU -#define SYSCON_FLASH_ACE0_ADDR_S_M (SYSCON_FLASH_ACE0_ADDR_S_V << SYSCON_FLASH_ACE0_ADDR_S_S) -#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFFU -#define SYSCON_FLASH_ACE0_ADDR_S_S 0 - -/** SYSCON_FLASH_ACE1_ADDR_REG register - * register description - */ -#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3c) -/** SYSCON_FLASH_ACE1_ADDR_S : R/W; bitpos: [31:0]; default: 4194304; - * Need add description - */ -#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFFU -#define SYSCON_FLASH_ACE1_ADDR_S_M (SYSCON_FLASH_ACE1_ADDR_S_V << SYSCON_FLASH_ACE1_ADDR_S_S) -#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFFU -#define SYSCON_FLASH_ACE1_ADDR_S_S 0 - -/** SYSCON_FLASH_ACE2_ADDR_REG register - * register description - */ -#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40) -/** SYSCON_FLASH_ACE2_ADDR_S : R/W; bitpos: [31:0]; default: 8388608; - * Need add description - */ -#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFFU -#define SYSCON_FLASH_ACE2_ADDR_S_M (SYSCON_FLASH_ACE2_ADDR_S_V << SYSCON_FLASH_ACE2_ADDR_S_S) -#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFFU -#define SYSCON_FLASH_ACE2_ADDR_S_S 0 - -/** SYSCON_FLASH_ACE3_ADDR_REG register - * register description - */ -#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44) -/** SYSCON_FLASH_ACE3_ADDR_S : R/W; bitpos: [31:0]; default: 12582912; - * Need add description - */ -#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFFU -#define SYSCON_FLASH_ACE3_ADDR_S_M (SYSCON_FLASH_ACE3_ADDR_S_V << SYSCON_FLASH_ACE3_ADDR_S_S) -#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFFU -#define SYSCON_FLASH_ACE3_ADDR_S_S 0 - -/** SYSCON_FLASH_ACE0_SIZE_REG register - * register description - */ -#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48) -/** SYSCON_FLASH_ACE0_SIZE : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ -#define SYSCON_FLASH_ACE0_SIZE 0x00001FFFU -#define SYSCON_FLASH_ACE0_SIZE_M (SYSCON_FLASH_ACE0_SIZE_V << SYSCON_FLASH_ACE0_SIZE_S) -#define SYSCON_FLASH_ACE0_SIZE_V 0x00001FFFU -#define SYSCON_FLASH_ACE0_SIZE_S 0 - -/** SYSCON_FLASH_ACE1_SIZE_REG register - * register description - */ -#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4c) -/** SYSCON_FLASH_ACE1_SIZE : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ -#define SYSCON_FLASH_ACE1_SIZE 0x00001FFFU -#define SYSCON_FLASH_ACE1_SIZE_M (SYSCON_FLASH_ACE1_SIZE_V << SYSCON_FLASH_ACE1_SIZE_S) -#define SYSCON_FLASH_ACE1_SIZE_V 0x00001FFFU -#define SYSCON_FLASH_ACE1_SIZE_S 0 - -/** SYSCON_FLASH_ACE2_SIZE_REG register - * register description - */ -#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50) -/** SYSCON_FLASH_ACE2_SIZE : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ -#define SYSCON_FLASH_ACE2_SIZE 0x00001FFFU -#define SYSCON_FLASH_ACE2_SIZE_M (SYSCON_FLASH_ACE2_SIZE_V << SYSCON_FLASH_ACE2_SIZE_S) -#define SYSCON_FLASH_ACE2_SIZE_V 0x00001FFFU -#define SYSCON_FLASH_ACE2_SIZE_S 0 - -/** SYSCON_FLASH_ACE3_SIZE_REG register - * register description - */ -#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54) -/** SYSCON_FLASH_ACE3_SIZE : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ -#define SYSCON_FLASH_ACE3_SIZE 0x00001FFFU -#define SYSCON_FLASH_ACE3_SIZE_M (SYSCON_FLASH_ACE3_SIZE_V << SYSCON_FLASH_ACE3_SIZE_S) -#define SYSCON_FLASH_ACE3_SIZE_V 0x00001FFFU -#define SYSCON_FLASH_ACE3_SIZE_S 0 - -/** SYSCON_SPI_MEM_PMS_CTRL_REG register - * register description - */ -#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88) -/** SYSCON_SPI_MEM_REJECT_INT : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) -#define SYSCON_SPI_MEM_REJECT_INT_M (SYSCON_SPI_MEM_REJECT_INT_V << SYSCON_SPI_MEM_REJECT_INT_S) -#define SYSCON_SPI_MEM_REJECT_INT_V 0x00000001U -#define SYSCON_SPI_MEM_REJECT_INT_S 0 -/** SYSCON_SPI_MEM_REJECT_CLR : WOD; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) -#define SYSCON_SPI_MEM_REJECT_CLR_M (SYSCON_SPI_MEM_REJECT_CLR_V << SYSCON_SPI_MEM_REJECT_CLR_S) -#define SYSCON_SPI_MEM_REJECT_CLR_V 0x00000001U -#define SYSCON_SPI_MEM_REJECT_CLR_S 1 -/** SYSCON_SPI_MEM_REJECT_CDE : RO; bitpos: [6:2]; default: 0; - * Need add description - */ -#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001FU -#define SYSCON_SPI_MEM_REJECT_CDE_M (SYSCON_SPI_MEM_REJECT_CDE_V << SYSCON_SPI_MEM_REJECT_CDE_S) -#define SYSCON_SPI_MEM_REJECT_CDE_V 0x0000001FU -#define SYSCON_SPI_MEM_REJECT_CDE_S 2 - -/** SYSCON_SPI_MEM_REJECT_ADDR_REG register - * register description - */ -#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8c) -/** SYSCON_SPI_MEM_REJECT_ADDR : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFFU -#define SYSCON_SPI_MEM_REJECT_ADDR_M (SYSCON_SPI_MEM_REJECT_ADDR_V << SYSCON_SPI_MEM_REJECT_ADDR_S) -#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFFU -#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 - -/** SYSCON_SYSCON_SDIO_CTRL_REG register - * register description - */ -#define SYSCON_SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90) -/** SYSCON_SDIO_WIN_ACCESS_EN : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) -#define SYSCON_SDIO_WIN_ACCESS_EN_M (SYSCON_SDIO_WIN_ACCESS_EN_V << SYSCON_SDIO_WIN_ACCESS_EN_S) -#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x00000001U -#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 - -/** SYSCON_REDCY_SIG0_REG register - * register description - */ -#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94) -/** SYSCON_REDCY_SIG0 : R/W; bitpos: [30:0]; default: 0; - * Need add description - */ -#define SYSCON_REDCY_SIG0 0x7FFFFFFFU -#define SYSCON_REDCY_SIG0_M (SYSCON_REDCY_SIG0_V << SYSCON_REDCY_SIG0_S) -#define SYSCON_REDCY_SIG0_V 0x7FFFFFFFU -#define SYSCON_REDCY_SIG0_S 0 -/** SYSCON_REDCY_ANDOR : RO; bitpos: [31]; default: 0; - * Need add description - */ -#define SYSCON_REDCY_ANDOR (BIT(31)) -#define SYSCON_REDCY_ANDOR_M (SYSCON_REDCY_ANDOR_V << SYSCON_REDCY_ANDOR_S) -#define SYSCON_REDCY_ANDOR_V 0x00000001U -#define SYSCON_REDCY_ANDOR_S 31 - -/** SYSCON_REDCY_SIG1_REG register - * register description - */ -#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98) -/** SYSCON_REDCY_SIG1 : R/W; bitpos: [30:0]; default: 0; - * Need add description - */ -#define SYSCON_REDCY_SIG1 0x7FFFFFFFU -#define SYSCON_REDCY_SIG1_M (SYSCON_REDCY_SIG1_V << SYSCON_REDCY_SIG1_S) -#define SYSCON_REDCY_SIG1_V 0x7FFFFFFFU -#define SYSCON_REDCY_SIG1_S 0 -/** SYSCON_REDCY_NANDOR : RO; bitpos: [31]; default: 0; - * Need add description - */ -#define SYSCON_REDCY_NANDOR (BIT(31)) -#define SYSCON_REDCY_NANDOR_M (SYSCON_REDCY_NANDOR_V << SYSCON_REDCY_NANDOR_S) -#define SYSCON_REDCY_NANDOR_V 0x00000001U -#define SYSCON_REDCY_NANDOR_S 31 - -/** SYSCON_FRONT_END_MEM_PD_REG register - * register description - */ -#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9c) -/** SYSCON_AGC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) -#define SYSCON_AGC_MEM_FORCE_PU_M (SYSCON_AGC_MEM_FORCE_PU_V << SYSCON_AGC_MEM_FORCE_PU_S) -#define SYSCON_AGC_MEM_FORCE_PU_V 0x00000001U -#define SYSCON_AGC_MEM_FORCE_PU_S 0 -/** SYSCON_AGC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) -#define SYSCON_AGC_MEM_FORCE_PD_M (SYSCON_AGC_MEM_FORCE_PD_V << SYSCON_AGC_MEM_FORCE_PD_S) -#define SYSCON_AGC_MEM_FORCE_PD_V 0x00000001U -#define SYSCON_AGC_MEM_FORCE_PD_S 1 -/** SYSCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * Need add description - */ -#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) -#define SYSCON_PBUS_MEM_FORCE_PU_M (SYSCON_PBUS_MEM_FORCE_PU_V << SYSCON_PBUS_MEM_FORCE_PU_S) -#define SYSCON_PBUS_MEM_FORCE_PU_V 0x00000001U -#define SYSCON_PBUS_MEM_FORCE_PU_S 2 -/** SYSCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) -#define SYSCON_PBUS_MEM_FORCE_PD_M (SYSCON_PBUS_MEM_FORCE_PD_V << SYSCON_PBUS_MEM_FORCE_PD_S) -#define SYSCON_PBUS_MEM_FORCE_PD_V 0x00000001U -#define SYSCON_PBUS_MEM_FORCE_PD_S 3 -/** SYSCON_DC_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; - * Need add description - */ -#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) -#define SYSCON_DC_MEM_FORCE_PU_M (SYSCON_DC_MEM_FORCE_PU_V << SYSCON_DC_MEM_FORCE_PU_S) -#define SYSCON_DC_MEM_FORCE_PU_V 0x00000001U -#define SYSCON_DC_MEM_FORCE_PU_S 4 -/** SYSCON_DC_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) -#define SYSCON_DC_MEM_FORCE_PD_M (SYSCON_DC_MEM_FORCE_PD_V << SYSCON_DC_MEM_FORCE_PD_S) -#define SYSCON_DC_MEM_FORCE_PD_V 0x00000001U -#define SYSCON_DC_MEM_FORCE_PD_S 5 - -/** SYSCON_RETENTION_CTRL_REG register - * register description - */ -#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xa0) -/** SYSCON_NOBYPASS_CPU_ISO_RST : R/W; bitpos: [27]; default: 0; - * Need add description - */ -#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) -#define SYSCON_NOBYPASS_CPU_ISO_RST_M (SYSCON_NOBYPASS_CPU_ISO_RST_V << SYSCON_NOBYPASS_CPU_ISO_RST_S) -#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x00000001U -#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 - -/** SYSCON_CLKGATE_FORCE_ON_REG register - * register description - */ -#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xa4) -/** SYSCON_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003U -#define SYSCON_ROM_CLKGATE_FORCE_ON_M (SYSCON_ROM_CLKGATE_FORCE_ON_V << SYSCON_ROM_CLKGATE_FORCE_ON_S) -#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x00000003U -#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 -/** SYSCON_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [5:2]; default: 15; - * Need add description - */ -#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000FU -#define SYSCON_SRAM_CLKGATE_FORCE_ON_M (SYSCON_SRAM_CLKGATE_FORCE_ON_V << SYSCON_SRAM_CLKGATE_FORCE_ON_S) -#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU -#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2 - -/** SYSCON_MEM_POWER_DOWN_REG register - * register description - */ -#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xa8) -/** SYSCON_ROM_POWER_DOWN : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ -#define SYSCON_ROM_POWER_DOWN 0x00000003U -#define SYSCON_ROM_POWER_DOWN_M (SYSCON_ROM_POWER_DOWN_V << SYSCON_ROM_POWER_DOWN_S) -#define SYSCON_ROM_POWER_DOWN_V 0x00000003U -#define SYSCON_ROM_POWER_DOWN_S 0 -/** SYSCON_SRAM_POWER_DOWN : R/W; bitpos: [5:2]; default: 0; - * Need add description - */ -#define SYSCON_SRAM_POWER_DOWN 0x0000000FU -#define SYSCON_SRAM_POWER_DOWN_M (SYSCON_SRAM_POWER_DOWN_V << SYSCON_SRAM_POWER_DOWN_S) -#define SYSCON_SRAM_POWER_DOWN_V 0x0000000FU -#define SYSCON_SRAM_POWER_DOWN_S 2 - -/** SYSCON_MEM_POWER_UP_REG register - * register description - */ -#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xac) -/** SYSCON_ROM_POWER_UP : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ -#define SYSCON_ROM_POWER_UP 0x00000003U -#define SYSCON_ROM_POWER_UP_M (SYSCON_ROM_POWER_UP_V << SYSCON_ROM_POWER_UP_S) -#define SYSCON_ROM_POWER_UP_V 0x00000003U -#define SYSCON_ROM_POWER_UP_S 0 -/** SYSCON_SRAM_POWER_UP : R/W; bitpos: [5:2]; default: 15; - * Need add description - */ -#define SYSCON_SRAM_POWER_UP 0x0000000FU -#define SYSCON_SRAM_POWER_UP_M (SYSCON_SRAM_POWER_UP_V << SYSCON_SRAM_POWER_UP_S) -#define SYSCON_SRAM_POWER_UP_V 0x0000000FU -#define SYSCON_SRAM_POWER_UP_S 2 - -/** SYSCON_RND_DATA_REG register - * register description - */ -#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xb0) -/** SYSCON_RND_DATA : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_RND_DATA 0xFFFFFFFFU -#define SYSCON_RND_DATA_M (SYSCON_RND_DATA_V << SYSCON_RND_DATA_S) -#define SYSCON_RND_DATA_V 0xFFFFFFFFU -#define SYSCON_RND_DATA_S 0 - -/** SYSCON_PERI_BACKUP_CONFIG_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xb4) -/** SYSCON_PERI_BACKUP_FLOW_ERR : RO; bitpos: [2:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000007U -#define SYSCON_PERI_BACKUP_FLOW_ERR_M (SYSCON_PERI_BACKUP_FLOW_ERR_V << SYSCON_PERI_BACKUP_FLOW_ERR_S) -#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x00000007U -#define SYSCON_PERI_BACKUP_FLOW_ERR_S 0 -/** SYSCON_PERI_BACKUP_ADDR_MAP_MODE : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE (BIT(3)) -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_M (SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V << SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S) -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V 0x00000001U -#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S 3 -/** SYSCON_PERI_BACKUP_BURST_LIMIT : R/W; bitpos: [8:4]; default: 8; - * Need add description - */ -#define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001FU -#define SYSCON_PERI_BACKUP_BURST_LIMIT_M (SYSCON_PERI_BACKUP_BURST_LIMIT_V << SYSCON_PERI_BACKUP_BURST_LIMIT_S) -#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x0000001FU -#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 -/** SYSCON_PERI_BACKUP_TOUT_THRES : R/W; bitpos: [18:9]; default: 50; - * Need add description - */ -#define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FFU -#define SYSCON_PERI_BACKUP_TOUT_THRES_M (SYSCON_PERI_BACKUP_TOUT_THRES_V << SYSCON_PERI_BACKUP_TOUT_THRES_S) -#define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x000003FFU -#define SYSCON_PERI_BACKUP_TOUT_THRES_S 9 -/** SYSCON_PERI_BACKUP_SIZE : R/W; bitpos: [28:19]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_SIZE 0x000003FFU -#define SYSCON_PERI_BACKUP_SIZE_M (SYSCON_PERI_BACKUP_SIZE_V << SYSCON_PERI_BACKUP_SIZE_S) -#define SYSCON_PERI_BACKUP_SIZE_V 0x000003FFU -#define SYSCON_PERI_BACKUP_SIZE_S 19 -/** SYSCON_PERI_BACKUP_START : WO; bitpos: [29]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_START (BIT(29)) -#define SYSCON_PERI_BACKUP_START_M (SYSCON_PERI_BACKUP_START_V << SYSCON_PERI_BACKUP_START_S) -#define SYSCON_PERI_BACKUP_START_V 0x00000001U -#define SYSCON_PERI_BACKUP_START_S 29 -/** SYSCON_PERI_BACKUP_TO_MEM : R/W; bitpos: [30]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_TO_MEM (BIT(30)) -#define SYSCON_PERI_BACKUP_TO_MEM_M (SYSCON_PERI_BACKUP_TO_MEM_V << SYSCON_PERI_BACKUP_TO_MEM_S) -#define SYSCON_PERI_BACKUP_TO_MEM_V 0x00000001U -#define SYSCON_PERI_BACKUP_TO_MEM_S 30 -/** SYSCON_PERI_BACKUP_ENA : R/W; bitpos: [31]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_ENA (BIT(31)) -#define SYSCON_PERI_BACKUP_ENA_M (SYSCON_PERI_BACKUP_ENA_V << SYSCON_PERI_BACKUP_ENA_S) -#define SYSCON_PERI_BACKUP_ENA_V 0x00000001U -#define SYSCON_PERI_BACKUP_ENA_S 31 - -/** SYSCON_PERI_BACKUP_APB_ADDR_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xb8) -/** SYSCON_PERI_BACKUP_APB_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_APB_START_ADDR_M (SYSCON_PERI_BACKUP_APB_START_ADDR_V << SYSCON_PERI_BACKUP_APB_START_ADDR_S) -#define SYSCON_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_APB_START_ADDR_S 0 - -/** SYSCON_PERI_BACKUP_MEM_ADDR_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xbc) -/** SYSCON_PERI_BACKUP_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_MEM_START_ADDR_M (SYSCON_PERI_BACKUP_MEM_START_ADDR_V << SYSCON_PERI_BACKUP_MEM_START_ADDR_S) -#define SYSCON_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_MEM_START_ADDR_S 0 - -/** SYSCON_PERI_BACKUP_REG_MAP0_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_REG_MAP0_REG (DR_REG_SYSCON_BASE + 0xc0) -/** SYSCON_PERI_BACKUP_REG_MAP0 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_REG_MAP0 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP0_M (SYSCON_PERI_BACKUP_REG_MAP0_V << SYSCON_PERI_BACKUP_REG_MAP0_S) -#define SYSCON_PERI_BACKUP_REG_MAP0_V 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP0_S 0 - -/** SYSCON_PERI_BACKUP_REG_MAP1_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_REG_MAP1_REG (DR_REG_SYSCON_BASE + 0xc4) -/** SYSCON_PERI_BACKUP_REG_MAP1 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_REG_MAP1 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP1_M (SYSCON_PERI_BACKUP_REG_MAP1_V << SYSCON_PERI_BACKUP_REG_MAP1_S) -#define SYSCON_PERI_BACKUP_REG_MAP1_V 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP1_S 0 - -/** SYSCON_PERI_BACKUP_REG_MAP2_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_REG_MAP2_REG (DR_REG_SYSCON_BASE + 0xc8) -/** SYSCON_PERI_BACKUP_REG_MAP2 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_REG_MAP2 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP2_M (SYSCON_PERI_BACKUP_REG_MAP2_V << SYSCON_PERI_BACKUP_REG_MAP2_S) -#define SYSCON_PERI_BACKUP_REG_MAP2_V 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP2_S 0 - -/** SYSCON_PERI_BACKUP_REG_MAP3_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_REG_MAP3_REG (DR_REG_SYSCON_BASE + 0xcc) -/** SYSCON_PERI_BACKUP_REG_MAP3 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_REG_MAP3 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP3_M (SYSCON_PERI_BACKUP_REG_MAP3_V << SYSCON_PERI_BACKUP_REG_MAP3_S) -#define SYSCON_PERI_BACKUP_REG_MAP3_V 0xFFFFFFFFU -#define SYSCON_PERI_BACKUP_REG_MAP3_S 0 - -/** SYSCON_PERI_BACKUP_INT_RAW_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xd0) -/** SYSCON_PERI_BACKUP_DONE_INT_RAW : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (SYSCON_PERI_BACKUP_DONE_INT_RAW_V << SYSCON_PERI_BACKUP_DONE_INT_RAW_S) -#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x00000001U -#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 -/** SYSCON_PERI_BACKUP_ERR_INT_RAW : RO; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (SYSCON_PERI_BACKUP_ERR_INT_RAW_V << SYSCON_PERI_BACKUP_ERR_INT_RAW_S) -#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x00000001U -#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1 - -/** SYSCON_PERI_BACKUP_INT_ST_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xd4) -/** SYSCON_PERI_BACKUP_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (SYSCON_PERI_BACKUP_DONE_INT_ST_V << SYSCON_PERI_BACKUP_DONE_INT_ST_S) -#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x00000001U -#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 -/** SYSCON_PERI_BACKUP_ERR_INT_ST : RO; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_ST_M (SYSCON_PERI_BACKUP_ERR_INT_ST_V << SYSCON_PERI_BACKUP_ERR_INT_ST_S) -#define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x00000001U -#define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1 - -/** SYSCON_PERI_BACKUP_INT_ENA_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xd8) -/** SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (SYSCON_PERI_BACKUP_DONE_INT_ENA_V << SYSCON_PERI_BACKUP_DONE_INT_ENA_S) -#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x00000001U -#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 -/** SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (SYSCON_PERI_BACKUP_ERR_INT_ENA_V << SYSCON_PERI_BACKUP_ERR_INT_ENA_S) -#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x00000001U -#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1 - -/** SYSCON_PERI_BACKUP_INT_CLR_REG register - * register description - */ -#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xdc) -/** SYSCON_PERI_BACKUP_DONE_INT_CLR : WO; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0)) -#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (SYSCON_PERI_BACKUP_DONE_INT_CLR_V << SYSCON_PERI_BACKUP_DONE_INT_CLR_S) -#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x00000001U -#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 -/** SYSCON_PERI_BACKUP_ERR_INT_CLR : WO; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) -#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (SYSCON_PERI_BACKUP_ERR_INT_CLR_V << SYSCON_PERI_BACKUP_ERR_INT_CLR_S) -#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x00000001U -#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1 - -/** SYSCON_SYSCON_REGCLK_CONF_REG register - * register description - */ -#define SYSCON_SYSCON_REGCLK_CONF_REG (DR_REG_SYSCON_BASE + 0xe0) -/** SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSCON_CLK_EN (BIT(0)) -#define SYSCON_CLK_EN_M (SYSCON_CLK_EN_V << SYSCON_CLK_EN_S) -#define SYSCON_CLK_EN_V 0x00000001U -#define SYSCON_CLK_EN_S 0 - -/** SYSCON_SYSCON_DATE_REG register - * register description - */ -#define SYSCON_SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3fc) -/** SYSCON_SYSCON_DATE : R/W; bitpos: [31:0]; default: 34607184; - * Version control - */ -#define SYSCON_SYSCON_DATE 0xFFFFFFFFU -#define SYSCON_SYSCON_DATE_M (SYSCON_SYSCON_DATE_V << SYSCON_SYSCON_DATE_S) -#define SYSCON_SYSCON_DATE_V 0xFFFFFFFFU -#define SYSCON_SYSCON_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/syscon_struct.h b/components/soc/esp32h4/include/rev2/soc/syscon_struct.h deleted file mode 100644 index 6e50a408f8..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/syscon_struct.h +++ /dev/null @@ -1,706 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of wifi_bb_cfg register - * register description - */ -typedef union { - struct { - /** wifi_bb_cfg : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t wifi_bb_cfg:32; - }; - uint32_t val; -} syscon_wifi_bb_cfg_reg_t; - -/** Type of wifi_bb_cfg_2 register - * register description - */ -typedef union { - struct { - /** wifi_bb_cfg_2 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t wifi_bb_cfg_2:32; - }; - uint32_t val; -} syscon_wifi_bb_cfg_2_reg_t; - -/** Type of host_inf_sel register - * register description - */ -typedef union { - struct { - /** peri_io_swap : R/W; bitpos: [7:0]; default: 0; - * Need add description - */ - uint32_t peri_io_swap:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} syscon_host_inf_sel_reg_t; - -/** Type of ext_mem_pms_lock register - * register description - */ -typedef union { - struct { - /** ext_mem_pms_lock : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t ext_mem_pms_lock:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} syscon_ext_mem_pms_lock_reg_t; - -/** Type of flash_ace0_attr register - * register description - */ -typedef union { - struct { - /** flash_ace0_attr : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t flash_ace0_attr:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_flash_ace0_attr_reg_t; - -/** Type of flash_ace1_attr register - * register description - */ -typedef union { - struct { - /** flash_ace1_attr : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t flash_ace1_attr:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_flash_ace1_attr_reg_t; - -/** Type of flash_ace2_attr register - * register description - */ -typedef union { - struct { - /** flash_ace2_attr : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t flash_ace2_attr:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_flash_ace2_attr_reg_t; - -/** Type of flash_ace3_attr register - * register description - */ -typedef union { - struct { - /** flash_ace3_attr : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t flash_ace3_attr:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_flash_ace3_attr_reg_t; - -/** Type of flash_ace0_addr register - * register description - */ -typedef union { - struct { - /** flash_ace0_addr_s : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t flash_ace0_addr_s:32; - }; - uint32_t val; -} syscon_flash_ace0_addr_reg_t; - -/** Type of flash_ace1_addr register - * register description - */ -typedef union { - struct { - /** flash_ace1_addr_s : R/W; bitpos: [31:0]; default: 4194304; - * Need add description - */ - uint32_t flash_ace1_addr_s:32; - }; - uint32_t val; -} syscon_flash_ace1_addr_reg_t; - -/** Type of flash_ace2_addr register - * register description - */ -typedef union { - struct { - /** flash_ace2_addr_s : R/W; bitpos: [31:0]; default: 8388608; - * Need add description - */ - uint32_t flash_ace2_addr_s:32; - }; - uint32_t val; -} syscon_flash_ace2_addr_reg_t; - -/** Type of flash_ace3_addr register - * register description - */ -typedef union { - struct { - /** flash_ace3_addr_s : R/W; bitpos: [31:0]; default: 12582912; - * Need add description - */ - uint32_t flash_ace3_addr_s:32; - }; - uint32_t val; -} syscon_flash_ace3_addr_reg_t; - -/** Type of flash_ace0_size register - * register description - */ -typedef union { - struct { - /** flash_ace0_size : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ - uint32_t flash_ace0_size:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} syscon_flash_ace0_size_reg_t; - -/** Type of flash_ace1_size register - * register description - */ -typedef union { - struct { - /** flash_ace1_size : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ - uint32_t flash_ace1_size:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} syscon_flash_ace1_size_reg_t; - -/** Type of flash_ace2_size register - * register description - */ -typedef union { - struct { - /** flash_ace2_size : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ - uint32_t flash_ace2_size:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} syscon_flash_ace2_size_reg_t; - -/** Type of flash_ace3_size register - * register description - */ -typedef union { - struct { - /** flash_ace3_size : R/W; bitpos: [12:0]; default: 1024; - * Need add description - */ - uint32_t flash_ace3_size:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} syscon_flash_ace3_size_reg_t; - -/** Type of spi_mem_pms_ctrl register - * register description - */ -typedef union { - struct { - /** spi_mem_reject_int : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t spi_mem_reject_int:1; - /** spi_mem_reject_clr : WOD; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t spi_mem_reject_clr:1; - /** spi_mem_reject_cde : RO; bitpos: [6:2]; default: 0; - * Need add description - */ - uint32_t spi_mem_reject_cde:5; - uint32_t reserved_7:25; - }; - uint32_t val; -} syscon_spi_mem_pms_ctrl_reg_t; - -/** Type of spi_mem_reject_addr register - * register description - */ -typedef union { - struct { - /** spi_mem_reject_addr : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t spi_mem_reject_addr:32; - }; - uint32_t val; -} syscon_spi_mem_reject_addr_reg_t; - -/** Type of syscon_sdio_ctrl register - * register description - */ -typedef union { - struct { - /** sdio_win_access_en : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t sdio_win_access_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} syscon_syscon_sdio_ctrl_reg_t; - -/** Type of redcy_sig0 register - * register description - */ -typedef union { - struct { - /** redcy_sig0 : R/W; bitpos: [30:0]; default: 0; - * Need add description - */ - uint32_t redcy_sig0:31; - /** redcy_andor : RO; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t redcy_andor:1; - }; - uint32_t val; -} syscon_redcy_sig0_reg_t; - -/** Type of redcy_sig1 register - * register description - */ -typedef union { - struct { - /** redcy_sig1 : R/W; bitpos: [30:0]; default: 0; - * Need add description - */ - uint32_t redcy_sig1:31; - /** redcy_nandor : RO; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t redcy_nandor:1; - }; - uint32_t val; -} syscon_redcy_sig1_reg_t; - -/** Type of front_end_mem_pd register - * register description - */ -typedef union { - struct { - /** agc_mem_force_pu : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t agc_mem_force_pu:1; - /** agc_mem_force_pd : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t agc_mem_force_pd:1; - /** pbus_mem_force_pu : R/W; bitpos: [2]; default: 1; - * Need add description - */ - uint32_t pbus_mem_force_pu:1; - /** pbus_mem_force_pd : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t pbus_mem_force_pd:1; - /** dc_mem_force_pu : R/W; bitpos: [4]; default: 1; - * Need add description - */ - uint32_t dc_mem_force_pu:1; - /** dc_mem_force_pd : R/W; bitpos: [5]; default: 0; - * Need add description - */ - uint32_t dc_mem_force_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} syscon_front_end_mem_pd_reg_t; - -/** Type of retention_ctrl register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** nobypass_cpu_iso_rst : R/W; bitpos: [27]; default: 0; - * Need add description - */ - uint32_t nobypass_cpu_iso_rst:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} syscon_retention_ctrl_reg_t; - -/** Type of clkgate_force_on register - * register description - */ -typedef union { - struct { - /** rom_clkgate_force_on : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t rom_clkgate_force_on:2; - /** sram_clkgate_force_on : R/W; bitpos: [5:2]; default: 15; - * Need add description - */ - uint32_t sram_clkgate_force_on:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} syscon_clkgate_force_on_reg_t; - -/** Type of mem_power_down register - * register description - */ -typedef union { - struct { - /** rom_power_down : R/W; bitpos: [1:0]; default: 0; - * Need add description - */ - uint32_t rom_power_down:2; - /** sram_power_down : R/W; bitpos: [5:2]; default: 0; - * Need add description - */ - uint32_t sram_power_down:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} syscon_mem_power_down_reg_t; - -/** Type of mem_power_up register - * register description - */ -typedef union { - struct { - /** rom_power_up : R/W; bitpos: [1:0]; default: 3; - * Need add description - */ - uint32_t rom_power_up:2; - /** sram_power_up : R/W; bitpos: [5:2]; default: 15; - * Need add description - */ - uint32_t sram_power_up:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} syscon_mem_power_up_reg_t; - -/** Type of rnd_data register - * register description - */ -typedef union { - struct { - /** rnd_data : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t rnd_data:32; - }; - uint32_t val; -} syscon_rnd_data_reg_t; - -/** Type of peri_backup_config register - * register description - */ -typedef union { - struct { - /** peri_backup_flow_err : RO; bitpos: [2:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_flow_err:3; - /** peri_backup_addr_map_mode : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t peri_backup_addr_map_mode:1; - /** peri_backup_burst_limit : R/W; bitpos: [8:4]; default: 8; - * Need add description - */ - uint32_t peri_backup_burst_limit:5; - /** peri_backup_tout_thres : R/W; bitpos: [18:9]; default: 50; - * Need add description - */ - uint32_t peri_backup_tout_thres:10; - /** peri_backup_size : R/W; bitpos: [28:19]; default: 0; - * Need add description - */ - uint32_t peri_backup_size:10; - /** peri_backup_start : WO; bitpos: [29]; default: 0; - * Need add description - */ - uint32_t peri_backup_start:1; - /** peri_backup_to_mem : R/W; bitpos: [30]; default: 0; - * Need add description - */ - uint32_t peri_backup_to_mem:1; - /** peri_backup_ena : R/W; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t peri_backup_ena:1; - }; - uint32_t val; -} syscon_peri_backup_config_reg_t; - -/** Type of peri_backup_apb_addr register - * register description - */ -typedef union { - struct { - /** peri_backup_apb_start_addr : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_apb_start_addr:32; - }; - uint32_t val; -} syscon_peri_backup_apb_addr_reg_t; - -/** Type of peri_backup_mem_addr register - * register description - */ -typedef union { - struct { - /** peri_backup_mem_start_addr : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_mem_start_addr:32; - }; - uint32_t val; -} syscon_peri_backup_mem_addr_reg_t; - -/** Type of peri_backup_reg_map0 register - * register description - */ -typedef union { - struct { - /** peri_backup_reg_map0 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_reg_map0:32; - }; - uint32_t val; -} syscon_peri_backup_reg_map0_reg_t; - -/** Type of peri_backup_reg_map1 register - * register description - */ -typedef union { - struct { - /** peri_backup_reg_map1 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_reg_map1:32; - }; - uint32_t val; -} syscon_peri_backup_reg_map1_reg_t; - -/** Type of peri_backup_reg_map2 register - * register description - */ -typedef union { - struct { - /** peri_backup_reg_map2 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_reg_map2:32; - }; - uint32_t val; -} syscon_peri_backup_reg_map2_reg_t; - -/** Type of peri_backup_reg_map3 register - * register description - */ -typedef union { - struct { - /** peri_backup_reg_map3 : R/W; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t peri_backup_reg_map3:32; - }; - uint32_t val; -} syscon_peri_backup_reg_map3_reg_t; - -/** Type of peri_backup_int_raw register - * register description - */ -typedef union { - struct { - /** peri_backup_done_int_raw : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t peri_backup_done_int_raw:1; - /** peri_backup_err_int_raw : RO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t peri_backup_err_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_peri_backup_int_raw_reg_t; - -/** Type of peri_backup_int_st register - * register description - */ -typedef union { - struct { - /** peri_backup_done_int_st : RO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t peri_backup_done_int_st:1; - /** peri_backup_err_int_st : RO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t peri_backup_err_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_peri_backup_int_st_reg_t; - -/** Type of peri_backup_int_ena register - * register description - */ -typedef union { - struct { - /** peri_backup_done_int_ena : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t peri_backup_done_int_ena:1; - /** peri_backup_err_int_ena : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t peri_backup_err_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_peri_backup_int_ena_reg_t; - -/** Type of peri_backup_int_clr register - * register description - */ -typedef union { - struct { - /** peri_backup_done_int_clr : WO; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t peri_backup_done_int_clr:1; - /** peri_backup_err_int_clr : WO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t peri_backup_err_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} syscon_peri_backup_int_clr_reg_t; - -/** Type of syscon_regclk_conf register - * register description - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} syscon_syscon_regclk_conf_reg_t; - -/** Type of syscon_date register - * register description - */ -typedef union { - struct { - /** syscon_date : R/W; bitpos: [31:0]; default: 34607184; - * Version control - */ - uint32_t syscon_date:32; - }; - uint32_t val; -} syscon_syscon_date_reg_t; - - -typedef struct { - uint32_t reserved_000[3]; - volatile syscon_wifi_bb_cfg_reg_t wifi_bb_cfg; - volatile syscon_wifi_bb_cfg_2_reg_t wifi_bb_cfg_2; - uint32_t reserved_014[2]; - volatile syscon_host_inf_sel_reg_t host_inf_sel; - volatile syscon_ext_mem_pms_lock_reg_t ext_mem_pms_lock; - uint32_t reserved_024; - volatile syscon_flash_ace0_attr_reg_t flash_ace0_attr; - volatile syscon_flash_ace1_attr_reg_t flash_ace1_attr; - volatile syscon_flash_ace2_attr_reg_t flash_ace2_attr; - volatile syscon_flash_ace3_attr_reg_t flash_ace3_attr; - volatile syscon_flash_ace0_addr_reg_t flash_ace0_addr; - volatile syscon_flash_ace1_addr_reg_t flash_ace1_addr; - volatile syscon_flash_ace2_addr_reg_t flash_ace2_addr; - volatile syscon_flash_ace3_addr_reg_t flash_ace3_addr; - volatile syscon_flash_ace0_size_reg_t flash_ace0_size; - volatile syscon_flash_ace1_size_reg_t flash_ace1_size; - volatile syscon_flash_ace2_size_reg_t flash_ace2_size; - volatile syscon_flash_ace3_size_reg_t flash_ace3_size; - uint32_t reserved_058[12]; - volatile syscon_spi_mem_pms_ctrl_reg_t spi_mem_pms_ctrl; - volatile syscon_spi_mem_reject_addr_reg_t spi_mem_reject_addr; - volatile syscon_syscon_sdio_ctrl_reg_t syscon_sdio_ctrl; - volatile syscon_redcy_sig0_reg_t redcy_sig0; - volatile syscon_redcy_sig1_reg_t redcy_sig1; - volatile syscon_front_end_mem_pd_reg_t front_end_mem_pd; - volatile syscon_retention_ctrl_reg_t retention_ctrl; - volatile syscon_clkgate_force_on_reg_t clkgate_force_on; - volatile syscon_mem_power_down_reg_t mem_power_down; - volatile syscon_mem_power_up_reg_t mem_power_up; - volatile syscon_rnd_data_reg_t rnd_data; - volatile syscon_peri_backup_config_reg_t peri_backup_config; - volatile syscon_peri_backup_apb_addr_reg_t peri_backup_apb_addr; - volatile syscon_peri_backup_mem_addr_reg_t peri_backup_mem_addr; - volatile syscon_peri_backup_reg_map0_reg_t peri_backup_reg_map0; - volatile syscon_peri_backup_reg_map1_reg_t peri_backup_reg_map1; - volatile syscon_peri_backup_reg_map2_reg_t peri_backup_reg_map2; - volatile syscon_peri_backup_reg_map3_reg_t peri_backup_reg_map3; - volatile syscon_peri_backup_int_raw_reg_t peri_backup_int_raw; - volatile syscon_peri_backup_int_st_reg_t peri_backup_int_st; - volatile syscon_peri_backup_int_ena_reg_t peri_backup_int_ena; - volatile syscon_peri_backup_int_clr_reg_t peri_backup_int_clr; - volatile syscon_syscon_regclk_conf_reg_t syscon_regclk_conf; - uint32_t reserved_0e4[198]; - volatile syscon_syscon_date_reg_t syscon_date; -} syscon_dev_t; - -extern syscon_dev_t SYSCON; - -#ifndef __cplusplus -_Static_assert(sizeof(syscon_dev_t) == 0x400, "Invalid size of syscon_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/system_reg.h b/components/soc/esp32h4/include/rev2/soc/system_reg.h deleted file mode 100644 index bd7affc00a..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/system_reg.h +++ /dev/null @@ -1,373 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#include "soc/clkrst_reg.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SYSTEM_CPU_PERI_CLK_EN_REG register - * register description - */ -#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0) -/** SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0; - * Need add description - */ -#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x00000001U -#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 -/** SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0; - * Need add description - */ -#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001U -#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 - -/** SYSTEM_CPU_PERI_RST_EN_REG register - * register description - */ -#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4) -/** SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1; - * Need add description - */ -#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_M (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S) -#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x00000001U -#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 -/** SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1; - * Need add description - */ -#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S) -#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001U -#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 - -/** SYSTEM_CPU_PER_CONF_REG register - * register description - */ -#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8) -/** SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; - * Need add description - */ -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 -/** SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000FU -#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S) -#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000FU -#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 - -/** SYSTEM_MEM_PD_MASK_REG register - * register description - */ -#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc) -/** SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S) -#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001U -#define SYSTEM_LSLP_MEM_PD_MASK_S 0 - -/** SYSTEM_CPU_INTR_FROM_CPU_0_REG register - * register description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x10) -/** SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S) -#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001U -#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 - -/** SYSTEM_CPU_INTR_FROM_CPU_1_REG register - * register description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x14) -/** SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S) -#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001U -#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 - -/** SYSTEM_CPU_INTR_FROM_CPU_2_REG register - * register description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x18) -/** SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S) -#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001U -#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 - -/** SYSTEM_CPU_INTR_FROM_CPU_3_REG register - * register description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x1c) -/** SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S) -#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001U -#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 - -/** SYSTEM_RSA_PD_CTRL_REG register - * register description - */ -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x20) -/** SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_RSA_MEM_PD (BIT(0)) -#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S) -#define SYSTEM_RSA_MEM_PD_V 0x00000001U -#define SYSTEM_RSA_MEM_PD_S 0 -/** SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S) -#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001U -#define SYSTEM_RSA_MEM_FORCE_PU_S 1 -/** SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S) -#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001U -#define SYSTEM_RSA_MEM_FORCE_PD_S 2 - -/** SYSTEM_EDMA_CTRL_REG register - * register description - */ -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x24) -/** SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_EDMA_CLK_ON (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_M (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S) -#define SYSTEM_EDMA_CLK_ON_V 0x00000001U -#define SYSTEM_EDMA_CLK_ON_S 0 -/** SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_EDMA_RESET (BIT(1)) -#define SYSTEM_EDMA_RESET_M (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S) -#define SYSTEM_EDMA_RESET_V 0x00000001U -#define SYSTEM_EDMA_RESET_S 1 - -/** SYSTEM_CACHE_CONTROL_REG register - * register description - */ -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x28) -/** SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_ICACHE_CLK_ON (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_M (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S) -#define SYSTEM_ICACHE_CLK_ON_V 0x00000001U -#define SYSTEM_ICACHE_CLK_ON_S 0 -/** SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_ICACHE_RESET (BIT(1)) -#define SYSTEM_ICACHE_RESET_M (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S) -#define SYSTEM_ICACHE_RESET_V 0x00000001U -#define SYSTEM_ICACHE_RESET_S 1 -/** SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1; - * Need add description - */ -#define SYSTEM_DCACHE_CLK_ON (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_M (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S) -#define SYSTEM_DCACHE_CLK_ON_V 0x00000001U -#define SYSTEM_DCACHE_CLK_ON_S 2 -/** SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_DCACHE_RESET (BIT(3)) -#define SYSTEM_DCACHE_RESET_M (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S) -#define SYSTEM_DCACHE_RESET_V 0x00000001U -#define SYSTEM_DCACHE_RESET_S 3 - -/** SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register - * register description - */ -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x2c) -/** SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 -/** SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 -/** SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; - * Need add description - */ -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 -/** SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; - * Need add description - */ -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 - -/** SYSTEM_RTC_FASTMEM_CONFIG_REG register - * register description - */ -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x30) -/** SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0; - * Need add description - */ -#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S) -#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001U -#define SYSTEM_RTC_MEM_CRC_START_S 8 -/** SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0; - * Need add description - */ -#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FFU -#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) -#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FFU -#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 -/** SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047; - * Need add description - */ -#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FFU -#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) -#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FFU -#define SYSTEM_RTC_MEM_CRC_LEN_S 20 -/** SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0; - * Need add description - */ -#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S) -#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001U -#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 - -/** SYSTEM_RTC_FASTMEM_CRC_REG register - * register description - */ -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x34) -/** SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0; - * Need add description - */ -#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFFU -#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) -#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFFU -#define SYSTEM_RTC_MEM_CRC_RES_S 0 - -/** SYSTEM_REDUNDANT_ECO_CTRL_REG register - * register description - */ -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38) -/** SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0; - * Need add description - */ -#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S) -#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001U -#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 -/** SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0; - * Need add description - */ -#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S) -#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001U -#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 - -/** SYSTEM_CLOCK_GATE_REG register - * register description - */ -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x3c) -/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Need add description - */ -#define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) -#define SYSTEM_CLK_EN_V 0x00000001U -#define SYSTEM_CLK_EN_S 0 - -/** SYSTEM_MEM_PVT_REG register - * register description - */ -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x40) -/** SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3; - * Need add description - */ -#define SYSTEM_MEM_PATH_LEN 0x0000000FU -#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S) -#define SYSTEM_MEM_PATH_LEN_V 0x0000000FU -#define SYSTEM_MEM_PATH_LEN_S 0 -/** SYSTEM_MEM_ERR_CNT_CLR : WO; bitpos: [4]; default: 0; - * Need add description - */ -#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_M (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S) -#define SYSTEM_MEM_ERR_CNT_CLR_V 0x00000001U -#define SYSTEM_MEM_ERR_CNT_CLR_S 4 -/** SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0; - * Need add description - */ -#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_M (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S) -#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x00000001U -#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 -/** SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0; - * Need add description - */ -#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFFU -#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S) -#define SYSTEM_MEM_TIMING_ERR_CNT_V 0x0000FFFFU -#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 -/** SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0; - * Need add description - */ -#define SYSTEM_MEM_VT_SEL 0x00000003U -#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S) -#define SYSTEM_MEM_VT_SEL_V 0x00000003U -#define SYSTEM_MEM_VT_SEL_S 22 - -/** SYSTEM_REG_DATE_REG register - * register description - */ -#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) -/** SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872; - * Need add description - */ -#define SYSTEM_REG_DATE 0x0FFFFFFFU -#define SYSTEM_REG_DATE_M (SYSTEM_REG_DATE_V << SYSTEM_REG_DATE_S) -#define SYSTEM_REG_DATE_V 0x0FFFFFFFU -#define SYSTEM_REG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/system_struct.h b/components/soc/esp32h4/include/rev2/soc/system_struct.h deleted file mode 100644 index d893cb6a15..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/system_struct.h +++ /dev/null @@ -1,379 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of cpu_peri_clk_en register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** clk_en_assist_debug : R/W; bitpos: [6]; default: 0; - * Need add description - */ - uint32_t clk_en_assist_debug:1; - /** clk_en_dedicated_gpio : R/W; bitpos: [7]; default: 0; - * Need add description - */ - uint32_t clk_en_dedicated_gpio:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} system_cpu_peri_clk_en_reg_t; - -/** Type of cpu_peri_rst_en register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** rst_en_assist_debug : R/W; bitpos: [6]; default: 1; - * Need add description - */ - uint32_t rst_en_assist_debug:1; - /** rst_en_dedicated_gpio : R/W; bitpos: [7]; default: 1; - * Need add description - */ - uint32_t rst_en_dedicated_gpio:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} system_cpu_peri_rst_en_reg_t; - -/** Type of cpu_per_conf register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; - * Need add description - */ - uint32_t cpu_wait_mode_force_on:1; - /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; - * Need add description - */ - uint32_t cpu_waiti_delay_num:4; - uint32_t reserved_8:24; - }; - uint32_t val; -} system_cpu_per_conf_reg_t; - -/** Type of mem_pd_mask register - * register description - */ -typedef union { - struct { - /** lslp_mem_pd_mask : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t lslp_mem_pd_mask:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} system_mem_pd_mask_reg_t; - -/** Type of cpu_intr_from_cpu_0 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_0:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} system_cpu_intr_from_cpu_0_reg_t; - -/** Type of cpu_intr_from_cpu_1 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_1:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} system_cpu_intr_from_cpu_1_reg_t; - -/** Type of cpu_intr_from_cpu_2 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_2:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} system_cpu_intr_from_cpu_2_reg_t; - -/** Type of cpu_intr_from_cpu_3 register - * register description - */ -typedef union { - struct { - /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t cpu_intr_from_cpu_3:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} system_cpu_intr_from_cpu_3_reg_t; - -/** Type of rsa_pd_ctrl register - * register description - */ -typedef union { - struct { - /** rsa_mem_pd : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t rsa_mem_pd:1; - /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t rsa_mem_force_pu:1; - /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t rsa_mem_force_pd:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} system_rsa_pd_ctrl_reg_t; - -/** Type of edma_ctrl register - * register description - */ -typedef union { - struct { - /** edma_clk_on : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t edma_clk_on:1; - /** edma_reset : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t edma_reset:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} system_edma_ctrl_reg_t; - -/** Type of cache_control register - * register description - */ -typedef union { - struct { - /** icache_clk_on : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t icache_clk_on:1; - /** icache_reset : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t icache_reset:1; - /** dcache_clk_on : R/W; bitpos: [2]; default: 1; - * Need add description - */ - uint32_t dcache_clk_on:1; - /** dcache_reset : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t dcache_reset:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} system_cache_control_reg_t; - -/** Type of external_device_encrypt_decrypt_control register - * register description - */ -typedef union { - struct { - /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t enable_spi_manual_encrypt:1; - /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t enable_download_db_encrypt:1; - /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; - * Need add description - */ - uint32_t enable_download_g0cb_decrypt:1; - /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; - * Need add description - */ - uint32_t enable_download_manual_encrypt:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} system_external_device_encrypt_decrypt_control_reg_t; - -/** Type of rtc_fastmem_config register - * register description - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** rtc_mem_crc_start : R/W; bitpos: [8]; default: 0; - * Need add description - */ - uint32_t rtc_mem_crc_start:1; - /** rtc_mem_crc_addr : R/W; bitpos: [19:9]; default: 0; - * Need add description - */ - uint32_t rtc_mem_crc_addr:11; - /** rtc_mem_crc_len : R/W; bitpos: [30:20]; default: 2047; - * Need add description - */ - uint32_t rtc_mem_crc_len:11; - /** rtc_mem_crc_finish : RO; bitpos: [31]; default: 0; - * Need add description - */ - uint32_t rtc_mem_crc_finish:1; - }; - uint32_t val; -} system_rtc_fastmem_config_reg_t; - -/** Type of rtc_fastmem_crc register - * register description - */ -typedef union { - struct { - /** rtc_mem_crc_res : RO; bitpos: [31:0]; default: 0; - * Need add description - */ - uint32_t rtc_mem_crc_res:32; - }; - uint32_t val; -} system_rtc_fastmem_crc_reg_t; - -/** Type of redundant_eco_ctrl register - * register description - */ -typedef union { - struct { - /** redundant_eco_drive : R/W; bitpos: [0]; default: 0; - * Need add description - */ - uint32_t redundant_eco_drive:1; - /** redundant_eco_result : RO; bitpos: [1]; default: 0; - * Need add description - */ - uint32_t redundant_eco_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} system_redundant_eco_ctrl_reg_t; - -/** Type of clock_gate register - * register description - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Need add description - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} system_clock_gate_reg_t; - -/** Type of mem_pvt register - * register description - */ -typedef union { - struct { - /** mem_path_len : R/W; bitpos: [3:0]; default: 3; - * Need add description - */ - uint32_t mem_path_len:4; - /** mem_err_cnt_clr : WO; bitpos: [4]; default: 0; - * Need add description - */ - uint32_t mem_err_cnt_clr:1; - /** mem_pvt_monitor_en : R/W; bitpos: [5]; default: 0; - * Need add description - */ - uint32_t mem_pvt_monitor_en:1; - /** mem_timing_err_cnt : RO; bitpos: [21:6]; default: 0; - * Need add description - */ - uint32_t mem_timing_err_cnt:16; - /** mem_vt_sel : R/W; bitpos: [23:22]; default: 0; - * Need add description - */ - uint32_t mem_vt_sel:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} system_mem_pvt_reg_t; - -/** Type of system_reg_date register - * register description - */ -typedef union { - struct { - /** system_reg_date : R/W; bitpos: [27:0]; default: 34615872; - * Need add description - */ - uint32_t system_reg_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} system_system_reg_date_reg_t; - - -typedef struct { - volatile system_cpu_peri_clk_en_reg_t cpu_peri_clk_en; - volatile system_cpu_peri_rst_en_reg_t cpu_peri_rst_en; - volatile system_cpu_per_conf_reg_t cpu_per_conf; - volatile system_mem_pd_mask_reg_t mem_pd_mask; - volatile system_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; - volatile system_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; - volatile system_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; - volatile system_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; - volatile system_rsa_pd_ctrl_reg_t rsa_pd_ctrl; - volatile system_edma_ctrl_reg_t edma_ctrl; - volatile system_cache_control_reg_t cache_control; - volatile system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; - volatile system_rtc_fastmem_config_reg_t rtc_fastmem_config; - volatile system_rtc_fastmem_crc_reg_t rtc_fastmem_crc; - volatile system_redundant_eco_ctrl_reg_t redundant_eco_ctrl; - volatile system_clock_gate_reg_t clock_gate; - volatile system_mem_pvt_reg_t mem_pvt; - uint32_t reserved_044[1006]; - volatile system_system_reg_date_reg_t system_reg_date; -} system_dev_t; - -extern system_dev_t SYSTEM; - -#ifndef __cplusplus -_Static_assert(sizeof(system_dev_t) == 0x1000, "Invalid size of system_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/usb_serial_jtag_reg.h b/components/soc/esp32h4/include/rev2/soc/usb_serial_jtag_reg.h deleted file mode 100644 index f65e780350..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/usb_serial_jtag_reg.h +++ /dev/null @@ -1,899 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** USB_SERIAL_JTAG_EP1_REG register - * FIFO access for the CDC-ACM data IN and OUT endpoints. - */ -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) -/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; - * Write and read byte data to/from UART Tx/Rx FIFO through this field. When - * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 - * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user - * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know - * how many data is received, then read data from UART Rx FIFO. - */ -#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU -#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) -#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU -#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 - -/** USB_SERIAL_JTAG_EP1_CONF_REG register - * Configuration and control registers for the CDC-ACM FIFOs. - */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) -/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; - * Set this bit to indicate writing byte data to UART Tx FIFO is done. - */ -#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) -#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) -#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U -#define USB_SERIAL_JTAG_WR_DONE_S 0 -/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; - * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing - * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by - * USB Host. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; - * 1'b1: Indicate there is data in UART Rx FIFO. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 - -/** USB_SERIAL_JTAG_INT_RAW_REG register - * Interrupt raw status register. - */ -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when flush cmd is received for IN - * endpoint 2 of JTAG. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when SOF frame is received. - */ -#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) -#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received - * one packet. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; - * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when pid error is detected. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when CRC5 error is detected. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when CRC16 error is detected. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when stuff error is detected. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is - * received. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when usb bus reset is detected. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with - * zero palyload. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with - * zero palyload. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 - -/** USB_SERIAL_JTAG_INT_ST_REG register - * Interrupt status register. - */ -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) -#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT - * interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 - -/** USB_SERIAL_JTAG_INT_ENA_REG register - * Interrupt enable status register. - */ -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) -#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 - -/** USB_SERIAL_JTAG_INT_CLR_REG register - * Interrupt clear status register. - */ -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) -/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. - */ -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. - */ -#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) -#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) -#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 -/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. - */ -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 -/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 -/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 -/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 -/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. - */ -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 -/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. - */ -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. - */ -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 - -/** USB_SERIAL_JTAG_CONF0_REG register - * PHY hardware configuration. - */ -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) -/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY - */ -#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) -#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_SERIAL_JTAG_PHY_SEL_S 0 -/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; - * Enable software control USB D+ D- exchange - */ -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U -#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 -/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; - * USB D+ D- exchange - */ -#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) -#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) -#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U -#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 -/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; - * Control single-end input high threshold,1.76V to 2V, step 80mV - */ -#define USB_SERIAL_JTAG_VREFH 0x00000003U -#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) -#define USB_SERIAL_JTAG_VREFH_V 0x00000003U -#define USB_SERIAL_JTAG_VREFH_S 3 -/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; - * Control single-end input low threshold,0.8V to 1.04V, step 80mV - */ -#define USB_SERIAL_JTAG_VREFL 0x00000003U -#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) -#define USB_SERIAL_JTAG_VREFL_V 0x00000003U -#define USB_SERIAL_JTAG_VREFL_S 5 -/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; - * Enable software control input threshold - */ -#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) -#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) -#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U -#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 -/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; - * Enable software control USB D+ D- pullup pulldown - */ -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U -#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 -/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; - * Control USB D+ pull up. - */ -#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) -#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) -#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U -#define USB_SERIAL_JTAG_DP_PULLUP_S 9 -/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; - * Control USB D+ pull down. - */ -#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) -#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) -#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U -#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 -/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; - * Control USB D- pull up. - */ -#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) -#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) -#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U -#define USB_SERIAL_JTAG_DM_PULLUP_S 11 -/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; - * Control USB D- pull down. - */ -#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) -#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) -#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U -#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 -/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; - * Control pull up value. - */ -#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) -#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) -#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U -#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 -/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; - * Enable USB pad function. - */ -#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U -#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 -/** USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W; bitpos: [15]; default: 0; - * 0: TX output at clock negedge. 1: Tx output at clock posedge. - */ -#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL (BIT(15)) -#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S) -#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V 0x00000001U -#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S 15 -/** USB_SERIAL_JTAG_PLL_DIV2_EN : R/W; bitpos: [16]; default: 1; - * This bit is used to set divider coefficient of PLL. 0: PLL divider coefficient is - * 0. 1: PLL divider coefficient is 1. - */ -#define USB_SERIAL_JTAG_PLL_DIV2_EN (BIT(16)) -#define USB_SERIAL_JTAG_PLL_DIV2_EN_M (USB_SERIAL_JTAG_PLL_DIV2_EN_V << USB_SERIAL_JTAG_PLL_DIV2_EN_S) -#define USB_SERIAL_JTAG_PLL_DIV2_EN_V 0x00000001U -#define USB_SERIAL_JTAG_PLL_DIV2_EN_S 16 - -/** USB_SERIAL_JTAG_TEST_REG register - * Registers used for debugging the PHY. - */ -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) -/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; - * Enable test of the USB pad - */ -#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) -#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) -#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 -/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; - * USB pad oen in test - */ -#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) -#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) -#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 -/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; - * USB D+ tx value in test - */ -#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) -#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) -#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 -/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; - * USB D- tx value in test - */ -#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) -#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) -#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 -/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 0; - * USB differential rx value in test - */ -#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) -#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) -#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 -/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 0; - * USB D+ rx value in test - */ -#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) -#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) -#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 -/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; - * USB D- rx value in test - */ -#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) -#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) -#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U -#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 - -/** USB_SERIAL_JTAG_JFIFO_ST_REG register - * JTAG FIFO status and control registers. - */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) -/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; - * JTAT in fifo counter. - */ -#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U -#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) -#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U -#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 -/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; - * 1: JTAG in fifo is empty. - */ -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U -#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 -/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; - * 1: JTAG in fifo is full. - */ -#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) -#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) -#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U -#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 -/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; - * JTAT out fifo counter. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 -/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; - * 1: JTAG out fifo is empty. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 -/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; - * 1: JTAG out fifo is full. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 -/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; - * Write 1 to reset JTAG in fifo. - */ -#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) -#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) -#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U -#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 -/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; - * Write 1 to reset JTAG out fifo. - */ -#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U -#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 - -/** USB_SERIAL_JTAG_FRAM_NUM_REG register - * Last received SOF frame index register. - */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) -/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; - * Frame index of received SOF frame. - */ -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU -#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 - -/** USB_SERIAL_JTAG_IN_EP0_ST_REG register - * Control IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) -/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) -#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 0. - */ -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP1_ST_REG register - * CDC-ACM IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) -/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) -#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 1. - */ -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP2_ST_REG register - * CDC-ACM interrupt IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) -/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) -#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 2. - */ -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_IN_EP3_ST_REG register - * JTAG IN endpoint status information. - */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) -/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U -#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) -#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 -/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 3. - */ -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register - * Control OUT endpoint status information. - */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) -/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 -/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 0. - */ -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register - * CDC-ACM OUT endpoint status information. - */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) -/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 -/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 1. - */ -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 -/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; - * Data count in OUT endpoint 1 when one packet is received. - */ -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 - -/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register - * JTAG OUT endpoint status information. - */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) -/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) -#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U -#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 -/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 -/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 2. - */ -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU -#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 - -/** USB_SERIAL_JTAG_MISC_CONF_REG register - * Clock enable control - */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) -/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ -#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) -#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) -#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U -#define USB_SERIAL_JTAG_CLK_EN_S 0 - -/** USB_SERIAL_JTAG_MEM_CONF_REG register - * Memory power control - */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) -/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; - * 1: power down usb memory. - */ -#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) -#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) -#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U -#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 -/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; - * 1: Force clock on for usb memory. - */ -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U -#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 - -/** USB_SERIAL_JTAG_DATE_REG register - * Date register - */ -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) -/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34607505; - * register version. - */ -#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU -#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) -#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU -#define USB_SERIAL_JTAG_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/rev2/soc/usb_serial_jtag_struct.h b/components/soc/esp32h4/include/rev2/soc/usb_serial_jtag_struct.h deleted file mode 100644 index 44ff6b3ee5..0000000000 --- a/components/soc/esp32h4/include/rev2/soc/usb_serial_jtag_struct.h +++ /dev/null @@ -1,708 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of ep1 register - * FIFO access for the CDC-ACM data IN and OUT endpoints. - */ -typedef union { - struct { - /** rdwr_byte : R/W; bitpos: [7:0]; default: 0; - * Write and read byte data to/from UART Tx/Rx FIFO through this field. When - * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 - * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user - * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know - * how many data is received, then read data from UART Rx FIFO. - */ - uint32_t rdwr_byte:8; - uint32_t reserved_8:24; - }; - uint32_t val; -} usb_serial_jtag_ep1_reg_t; - -/** Type of ep1_conf register - * Configuration and control registers for the CDC-ACM FIFOs. - */ -typedef union { - struct { - /** wr_done : WT; bitpos: [0]; default: 0; - * Set this bit to indicate writing byte data to UART Tx FIFO is done. - */ - uint32_t wr_done:1; - /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; - * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing - * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by - * USB Host. - */ - uint32_t serial_in_ep_data_free:1; - /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; - * 1'b1: Indicate there is data in UART Rx FIFO. - */ - uint32_t serial_out_ep_data_avail:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} usb_serial_jtag_ep1_conf_reg_t; - -/** Type of conf0 register - * PHY hardware configuration. - */ -typedef union { - struct { - /** phy_sel : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY - */ - uint32_t phy_sel:1; - /** exchg_pins_override : R/W; bitpos: [1]; default: 0; - * Enable software control USB D+ D- exchange - */ - uint32_t exchg_pins_override:1; - /** exchg_pins : R/W; bitpos: [2]; default: 0; - * USB D+ D- exchange - */ - uint32_t exchg_pins:1; - /** vrefh : R/W; bitpos: [4:3]; default: 0; - * Control single-end input high threshold,1.76V to 2V, step 80mV - */ - uint32_t vrefh:2; - /** vrefl : R/W; bitpos: [6:5]; default: 0; - * Control single-end input low threshold,0.8V to 1.04V, step 80mV - */ - uint32_t vrefl:2; - /** vref_override : R/W; bitpos: [7]; default: 0; - * Enable software control input threshold - */ - uint32_t vref_override:1; - /** pad_pull_override : R/W; bitpos: [8]; default: 0; - * Enable software control USB D+ D- pullup pulldown - */ - uint32_t pad_pull_override:1; - /** dp_pullup : R/W; bitpos: [9]; default: 1; - * Control USB D+ pull up. - */ - uint32_t dp_pullup:1; - /** dp_pulldown : R/W; bitpos: [10]; default: 0; - * Control USB D+ pull down. - */ - uint32_t dp_pulldown:1; - /** dm_pullup : R/W; bitpos: [11]; default: 0; - * Control USB D- pull up. - */ - uint32_t dm_pullup:1; - /** dm_pulldown : R/W; bitpos: [12]; default: 0; - * Control USB D- pull down. - */ - uint32_t dm_pulldown:1; - /** pullup_value : R/W; bitpos: [13]; default: 0; - * Control pull up value. - */ - uint32_t pullup_value:1; - /** usb_pad_enable : R/W; bitpos: [14]; default: 1; - * Enable USB pad function. - */ - uint32_t usb_pad_enable:1; - /** phy_tx_edge_sel : R/W; bitpos: [15]; default: 0; - * 0: TX output at clock negedge. 1: Tx output at clock posedge. - */ - uint32_t phy_tx_edge_sel:1; - /** pll_div2_en : R/W; bitpos: [16]; default: 1; - * This bit is used to set divider coefficient of PLL. 0: PLL divider coefficient is - * 0. 1: PLL divider coefficient is 1. - */ - uint32_t pll_div2_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} usb_serial_jtag_conf0_reg_t; - -/** Type of test register - * Registers used for debugging the PHY. - */ -typedef union { - struct { - /** test_enable : R/W; bitpos: [0]; default: 0; - * Enable test of the USB pad - */ - uint32_t test_enable:1; - /** test_usb_oe : R/W; bitpos: [1]; default: 0; - * USB pad oen in test - */ - uint32_t test_usb_oe:1; - /** test_tx_dp : R/W; bitpos: [2]; default: 0; - * USB D+ tx value in test - */ - uint32_t test_tx_dp:1; - /** test_tx_dm : R/W; bitpos: [3]; default: 0; - * USB D- tx value in test - */ - uint32_t test_tx_dm:1; - /** test_rx_rcv : RO; bitpos: [4]; default: 0; - * USB differential rx value in test - */ - uint32_t test_rx_rcv:1; - /** test_rx_dp : RO; bitpos: [5]; default: 0; - * USB D+ rx value in test - */ - uint32_t test_rx_dp:1; - /** test_rx_dm : RO; bitpos: [6]; default: 0; - * USB D- rx value in test - */ - uint32_t test_rx_dm:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} usb_serial_jtag_test_reg_t; - -/** Type of misc_conf register - * Clock enable control - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes - * registers. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} usb_serial_jtag_misc_conf_reg_t; - -/** Type of mem_conf register - * Memory power control - */ -typedef union { - struct { - /** usb_mem_pd : R/W; bitpos: [0]; default: 0; - * 1: power down usb memory. - */ - uint32_t usb_mem_pd:1; - /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; - * 1: Force clock on for usb memory. - */ - uint32_t usb_mem_clk_en:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} usb_serial_jtag_mem_conf_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * Interrupt raw status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when flush cmd is received for IN - * endpoint 2 of JTAG. - */ - uint32_t jtag_in_flush_int_raw:1; - /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when SOF frame is received. - */ - uint32_t sof_int_raw:1; - /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received - * one packet. - */ - uint32_t serial_out_recv_pkt_int_raw:1; - /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; - * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. - */ - uint32_t serial_in_empty_int_raw:1; - /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when pid error is detected. - */ - uint32_t pid_err_int_raw:1; - /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when CRC5 error is detected. - */ - uint32_t crc5_err_int_raw:1; - /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when CRC16 error is detected. - */ - uint32_t crc16_err_int_raw:1; - /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when stuff error is detected. - */ - uint32_t stuff_err_int_raw:1; - /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is - * received. - */ - uint32_t in_token_rec_in_ep1_int_raw:1; - /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw interrupt bit turns to high level when usb bus reset is detected. - */ - uint32_t usb_bus_reset_int_raw:1; - /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with - * zero palyload. - */ - uint32_t out_ep1_zero_payload_int_raw:1; - /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with - * zero palyload. - */ - uint32_t out_ep2_zero_payload_int_raw:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} usb_serial_jtag_int_raw_reg_t; - -/** Type of int_st register - * Interrupt status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. - */ - uint32_t jtag_in_flush_int_st:1; - /** sof_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. - */ - uint32_t sof_int_st:1; - /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * interrupt. - */ - uint32_t serial_out_recv_pkt_int_st:1; - /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. - */ - uint32_t serial_in_empty_int_st:1; - /** pid_err_int_st : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. - */ - uint32_t pid_err_int_st:1; - /** crc5_err_int_st : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. - */ - uint32_t crc5_err_int_st:1; - /** crc16_err_int_st : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. - */ - uint32_t crc16_err_int_st:1; - /** stuff_err_int_st : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. - */ - uint32_t stuff_err_int_st:1; - /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT - * interrupt. - */ - uint32_t in_token_rec_in_ep1_int_st:1; - /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. - */ - uint32_t usb_bus_reset_int_st:1; - /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT - * interrupt. - */ - uint32_t out_ep1_zero_payload_int_st:1; - /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT - * interrupt. - */ - uint32_t out_ep2_zero_payload_int_st:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} usb_serial_jtag_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. - */ - uint32_t jtag_in_flush_int_ena:1; - /** sof_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. - */ - uint32_t sof_int_ena:1; - /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. - */ - uint32_t serial_out_recv_pkt_int_ena:1; - /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. - */ - uint32_t serial_in_empty_int_ena:1; - /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. - */ - uint32_t pid_err_int_ena:1; - /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. - */ - uint32_t crc5_err_int_ena:1; - /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. - */ - uint32_t crc16_err_int_ena:1; - /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. - */ - uint32_t stuff_err_int_ena:1; - /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. - */ - uint32_t in_token_rec_in_ep1_int_ena:1; - /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. - */ - uint32_t usb_bus_reset_int_ena:1; - /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep1_zero_payload_int_ena:1; - /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep2_zero_payload_int_ena:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} usb_serial_jtag_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear status register. - */ -typedef union { - struct { - /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. - */ - uint32_t jtag_in_flush_int_clr:1; - /** sof_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. - */ - uint32_t sof_int_clr:1; - /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. - */ - uint32_t serial_out_recv_pkt_int_clr:1; - /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. - */ - uint32_t serial_in_empty_int_clr:1; - /** pid_err_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. - */ - uint32_t pid_err_int_clr:1; - /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. - */ - uint32_t crc5_err_int_clr:1; - /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. - */ - uint32_t crc16_err_int_clr:1; - /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. - */ - uint32_t stuff_err_int_clr:1; - /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. - */ - uint32_t in_token_rec_in_ep1_int_clr:1; - /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. - */ - uint32_t usb_bus_reset_int_clr:1; - /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep1_zero_payload_int_clr:1; - /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - */ - uint32_t out_ep2_zero_payload_int_clr:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} usb_serial_jtag_int_clr_reg_t; - - -/** Group: Status Registers */ -/** Type of jfifo_st register - * JTAG FIFO status and control registers. - */ -typedef union { - struct { - /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; - * JTAT in fifo counter. - */ - uint32_t in_fifo_cnt:2; - /** in_fifo_empty : RO; bitpos: [2]; default: 1; - * 1: JTAG in fifo is empty. - */ - uint32_t in_fifo_empty:1; - /** in_fifo_full : RO; bitpos: [3]; default: 0; - * 1: JTAG in fifo is full. - */ - uint32_t in_fifo_full:1; - /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; - * JTAT out fifo counter. - */ - uint32_t out_fifo_cnt:2; - /** out_fifo_empty : RO; bitpos: [6]; default: 1; - * 1: JTAG out fifo is empty. - */ - uint32_t out_fifo_empty:1; - /** out_fifo_full : RO; bitpos: [7]; default: 0; - * 1: JTAG out fifo is full. - */ - uint32_t out_fifo_full:1; - /** in_fifo_reset : R/W; bitpos: [8]; default: 0; - * Write 1 to reset JTAG in fifo. - */ - uint32_t in_fifo_reset:1; - /** out_fifo_reset : R/W; bitpos: [9]; default: 0; - * Write 1 to reset JTAG out fifo. - */ - uint32_t out_fifo_reset:1; - uint32_t reserved_10:22; - }; - uint32_t val; -} usb_serial_jtag_jfifo_st_reg_t; - -/** Type of fram_num register - * Last received SOF frame index register. - */ -typedef union { - struct { - /** sof_frame_index : RO; bitpos: [10:0]; default: 0; - * Frame index of received SOF frame. - */ - uint32_t sof_frame_index:11; - uint32_t reserved_11:21; - }; - uint32_t val; -} usb_serial_jtag_fram_num_reg_t; - -/** Type of in_ep0_st register - * Control IN endpoint status information. - */ -typedef union { - struct { - /** in_ep0_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 0. - */ - uint32_t in_ep0_state:2; - /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 0. - */ - uint32_t in_ep0_wr_addr:7; - /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 0. - */ - uint32_t in_ep0_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep0_st_reg_t; - -/** Type of in_ep1_st register - * CDC-ACM IN endpoint status information. - */ -typedef union { - struct { - /** in_ep1_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 1. - */ - uint32_t in_ep1_state:2; - /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 1. - */ - uint32_t in_ep1_wr_addr:7; - /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 1. - */ - uint32_t in_ep1_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep1_st_reg_t; - -/** Type of in_ep2_st register - * CDC-ACM interrupt IN endpoint status information. - */ -typedef union { - struct { - /** in_ep2_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 2. - */ - uint32_t in_ep2_state:2; - /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 2. - */ - uint32_t in_ep2_wr_addr:7; - /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 2. - */ - uint32_t in_ep2_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep2_st_reg_t; - -/** Type of in_ep3_st register - * JTAG IN endpoint status information. - */ -typedef union { - struct { - /** in_ep3_state : RO; bitpos: [1:0]; default: 1; - * State of IN Endpoint 3. - */ - uint32_t in_ep3_state:2; - /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of IN endpoint 3. - */ - uint32_t in_ep3_wr_addr:7; - /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of IN endpoint 3. - */ - uint32_t in_ep3_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_in_ep3_st_reg_t; - -/** Type of out_ep0_st register - * Control OUT endpoint status information. - */ -typedef union { - struct { - /** out_ep0_state : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 0. - */ - uint32_t out_ep0_state:2; - /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. - */ - uint32_t out_ep0_wr_addr:7; - /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 0. - */ - uint32_t out_ep0_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_out_ep0_st_reg_t; - -/** Type of out_ep1_st register - * CDC-ACM OUT endpoint status information. - */ -typedef union { - struct { - /** out_ep1_state : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 1. - */ - uint32_t out_ep1_state:2; - /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. - */ - uint32_t out_ep1_wr_addr:7; - /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 1. - */ - uint32_t out_ep1_rd_addr:7; - /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; - * Data count in OUT endpoint 1 when one packet is received. - */ - uint32_t out_ep1_rec_data_cnt:7; - uint32_t reserved_23:9; - }; - uint32_t val; -} usb_serial_jtag_out_ep1_st_reg_t; - -/** Type of out_ep2_st register - * JTAG OUT endpoint status information. - */ -typedef union { - struct { - /** out_ep2_state : RO; bitpos: [1:0]; default: 0; - * State of OUT Endpoint 2. - */ - uint32_t out_ep2_state:2; - /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; - * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT - * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. - */ - uint32_t out_ep2_wr_addr:7; - /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; - * Read data address of OUT endpoint 2. - */ - uint32_t out_ep2_rd_addr:7; - uint32_t reserved_16:16; - }; - uint32_t val; -} usb_serial_jtag_out_ep2_st_reg_t; - - -/** Group: Version Registers */ -/** Type of date register - * Date register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 34607505; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} usb_serial_jtag_date_reg_t; - - -typedef struct { - volatile usb_serial_jtag_ep1_reg_t ep1; - volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; - volatile usb_serial_jtag_int_raw_reg_t int_raw; - volatile usb_serial_jtag_int_st_reg_t int_st; - volatile usb_serial_jtag_int_ena_reg_t int_ena; - volatile usb_serial_jtag_int_clr_reg_t int_clr; - volatile usb_serial_jtag_conf0_reg_t conf0; - volatile usb_serial_jtag_test_reg_t test; - volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; - volatile usb_serial_jtag_fram_num_reg_t fram_num; - volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; - volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; - volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; - volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; - volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; - volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; - volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; - volatile usb_serial_jtag_misc_conf_reg_t misc_conf; - volatile usb_serial_jtag_mem_conf_reg_t mem_conf; - uint32_t reserved_04c[13]; - volatile usb_serial_jtag_date_reg_t date; -} usb_serial_jtag_dev_t; - -extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; - -#ifndef __cplusplus -_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in deleted file mode 100644 index 9d1facc11e..0000000000 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ /dev/null @@ -1,872 +0,0 @@ -##################################################### -# This file is auto-generated from SoC caps -# using gen_soc_caps_kconfig.py, do not edit manually -##################################################### - -config SOC_ADC_SUPPORTED - bool - default y - -config SOC_DEDICATED_GPIO_SUPPORTED - bool - default y - -config SOC_UART_SUPPORTED - bool - default y - -config SOC_GDMA_SUPPORTED - bool - default y - -config SOC_GPTIMER_SUPPORTED - bool - default y - -config SOC_BT_SUPPORTED - bool - default y - -config SOC_IEEE802154_SUPPORTED - bool - default y - -config SOC_IEEE802154_BLE_ONLY - bool - default y - -config SOC_ASYNC_MEMCPY_SUPPORTED - bool - default y - -config SOC_USB_SERIAL_JTAG_SUPPORTED - bool - default y - -config SOC_SUPPORTS_SECURE_DL_MODE - bool - default y - -config SOC_EFUSE_KEY_PURPOSE_FIELD - bool - default y - -config SOC_TEMP_SENSOR_SUPPORTED - bool - default y - -config SOC_RTC_FAST_MEM_SUPPORTED - bool - default y - -config SOC_RTC_MEM_SUPPORTED - bool - default y - -config SOC_I2S_SUPPORTED - bool - default y - -config SOC_RMT_SUPPORTED - bool - default y - -config SOC_SDM_SUPPORTED - bool - default y - -config SOC_GPSPI_SUPPORTED - bool - default y - -config SOC_LEDC_SUPPORTED - bool - default y - -config SOC_I2C_SUPPORTED - bool - default y - -config SOC_SYSTIMER_SUPPORTED - bool - default y - -config SOC_AES_SUPPORTED - bool - default y - -config SOC_MPI_SUPPORTED - bool - default y - -config SOC_SHA_SUPPORTED - bool - default y - -config SOC_HMAC_SUPPORTED - bool - default y - -config SOC_DIG_SIGN_SUPPORTED - bool - default y - -config SOC_ECC_SUPPORTED - bool - default y - -config SOC_FLASH_ENC_SUPPORTED - bool - default y - -config SOC_SECURE_BOOT_SUPPORTED - bool - default y - -config SOC_BOD_SUPPORTED - bool - default y - -config SOC_XTAL_SUPPORT_32M - bool - default y - -config SOC_AES_SUPPORT_DMA - bool - default y - -config SOC_AES_GDMA - bool - default y - -config SOC_AES_SUPPORT_AES_128 - bool - default y - -config SOC_AES_SUPPORT_AES_256 - bool - default y - -config SOC_ADC_DIG_CTRL_SUPPORTED - bool - default y - -config SOC_ADC_ARBITER_SUPPORTED - bool - default y - -config SOC_ADC_DIG_IIR_FILTER_SUPPORTED - bool - default y - -config SOC_ADC_MONITOR_SUPPORTED - bool - default y - -config SOC_ADC_DMA_SUPPORTED - bool - default y - -config SOC_ADC_PERIPH_NUM - int - default 1 - -config SOC_ADC_MAX_CHANNEL_NUM - int - default 5 - -config SOC_ADC_ATTEN_NUM - int - default 4 - -config SOC_ADC_DIGI_CONTROLLER_NUM - int - default 1 - -config SOC_ADC_PATT_LEN_MAX - int - default 8 - -config SOC_ADC_DIGI_MIN_BITWIDTH - int - default 12 - -config SOC_ADC_DIGI_MAX_BITWIDTH - int - default 12 - -config SOC_ADC_DIGI_RESULT_BYTES - int - default 4 - -config SOC_ADC_DIGI_DATA_BYTES_PER_CONV - int - default 4 - -config SOC_ADC_DIGI_IIR_FILTER_NUM - int - default 2 - -config SOC_ADC_DIGI_MONITOR_NUM - int - default 2 - -config SOC_ADC_SAMPLE_FREQ_THRES_HIGH - int - default 83333 - -config SOC_ADC_SAMPLE_FREQ_THRES_LOW - int - default 611 - -config SOC_ADC_RTC_MIN_BITWIDTH - int - default 12 - -config SOC_ADC_RTC_MAX_BITWIDTH - int - default 12 - -config SOC_APB_BACKUP_DMA - bool - default y - -config SOC_BROWNOUT_RESET_SUPPORTED - bool - default y - -config SOC_SHARED_IDCACHE_SUPPORTED - bool - default y - -config SOC_CPU_CORES_NUM - int - default 1 - -config SOC_CPU_INTR_NUM - int - default 32 - -config SOC_CPU_HAS_FLEXIBLE_INTC - bool - default y - -config SOC_CPU_BREAKPOINTS_NUM - int - default 8 - -config SOC_CPU_WATCHPOINTS_NUM - int - default 8 - -config SOC_CPU_WATCHPOINT_SIZE - hex - default 0x80000000 - -config SOC_DS_SIGNATURE_MAX_BIT_LEN - int - default 3072 - -config SOC_DS_KEY_PARAM_MD_IV_LENGTH - int - default 16 - -config SOC_DS_KEY_CHECK_MAX_WAIT_US - int - default 1100 - -config SOC_GDMA_GROUPS - int - default 1 - -config SOC_GDMA_PAIRS_PER_GROUP - int - default 3 - -config SOC_GDMA_TX_RX_SHARE_INTERRUPT - bool - default y - -config SOC_GPIO_PORT - int - default 1 - -config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER - bool - default y - -config SOC_GPIO_FILTER_CLK_SUPPORT_APB - bool - default y - -config SOC_GPIO_PIN_COUNT - int - default 41 - -config SOC_GPIO_SUPPORT_FORCE_HOLD - bool - default y - -config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP - bool - default y - -config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK - int - default 0 - -config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK - hex - default 0x000001FFFFFFFFC0 - -config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP - bool - default y - -config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_GPIO_IN_CHANNELS_NUM - int - default 8 - -config SOC_DEDIC_PERIPH_ALWAYS_ENABLE - bool - default y - -config SOC_I2C_NUM - int - default 1 - -config SOC_I2C_FIFO_LEN - int - default 32 - -config SOC_I2C_SUPPORT_SLAVE - bool - default y - -config SOC_I2C_SUPPORT_HW_CLR_BUS - bool - default y - -config SOC_I2C_SUPPORT_XTAL - bool - default y - -config SOC_I2C_SUPPORT_RTC - bool - default y - -config SOC_I2S_NUM - int - default 1 - -config SOC_I2S_HW_VERSION_2 - bool - default y - -config SOC_I2S_SUPPORTS_XTAL - bool - default y - -config SOC_I2S_SUPPORTS_PLL_F96M - bool - default y - -config SOC_I2S_SUPPORTS_PCM - bool - default y - -config SOC_I2S_SUPPORTS_PDM - bool - default y - -config SOC_I2S_SUPPORTS_PDM_TX - bool - default y - -config SOC_I2S_PDM_MAX_TX_LINES - int - default 2 - -config SOC_I2S_SUPPORTS_TDM - bool - default y - -config SOC_LEDC_SUPPORT_APB_CLOCK - bool - default y - -config SOC_LEDC_SUPPORT_XTAL_CLOCK - bool - default y - -config SOC_LEDC_CHANNEL_NUM - int - default 6 - -config SOC_LEDC_TIMER_BIT_WIDTH - int - default 14 - -config SOC_LEDC_SUPPORT_FADE_STOP - bool - default y - -config SOC_MMU_LINEAR_ADDRESS_REGION_NUM - int - default 1 - -config SOC_MMU_PERIPH_NUM - int - default 1 - -config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED - bool - default n - -config SOC_MPU_MIN_REGION_SIZE - hex - default 0x20000000 - -config SOC_MPU_REGIONS_MAX_NUM - int - default 8 - -config SOC_MPU_REGION_RO_SUPPORTED - bool - default n - -config SOC_MPU_REGION_WO_SUPPORTED - bool - default n - -config SOC_RMT_GROUPS - int - default 1 - -config SOC_RMT_TX_CANDIDATES_PER_GROUP - int - default 2 - -config SOC_RMT_RX_CANDIDATES_PER_GROUP - int - default 2 - -config SOC_RMT_CHANNELS_PER_GROUP - int - default 4 - -config SOC_RMT_MEM_WORDS_PER_CHANNEL - int - default 48 - -config SOC_RMT_SUPPORT_RX_PINGPONG - bool - default y - -config SOC_RMT_SUPPORT_RX_DEMODULATION - bool - default y - -config SOC_RMT_SUPPORT_TX_ASYNC_STOP - bool - default y - -config SOC_RMT_SUPPORT_TX_LOOP_COUNT - bool - default y - -config SOC_RMT_SUPPORT_TX_SYNCHRO - bool - default y - -config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY - bool - default y - -config SOC_RMT_SUPPORT_XTAL - bool - default y - -config SOC_RMT_SUPPORT_AHB - bool - default y - -config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH - int - default 128 - -config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM - int - default 108 - -config SOC_RTCIO_PIN_COUNT - int - default 0 - -config SOC_RSA_MAX_BIT_LEN - int - default 3072 - -config SOC_SHA_DMA_MAX_BUFFER_SIZE - int - default 3968 - -config SOC_SHA_SUPPORT_DMA - bool - default y - -config SOC_SHA_SUPPORT_RESUME - bool - default y - -config SOC_SHA_GDMA - bool - default y - -config SOC_SHA_SUPPORT_SHA1 - bool - default y - -config SOC_SHA_SUPPORT_SHA224 - bool - default y - -config SOC_SHA_SUPPORT_SHA256 - bool - default y - -config SOC_SDM_GROUPS - int - default 1 - -config SOC_SDM_CHANNELS_PER_GROUP - int - default 4 - -config SOC_SDM_CLK_SUPPORT_APB - bool - default y - -config SOC_SPI_PERIPH_NUM - int - default 2 - -config SOC_SPI_MAX_CS_NUM - int - default 6 - -config SOC_SPI_MAXIMUM_BUFFER_SIZE - int - default 64 - -config SOC_SPI_SUPPORT_DDRCLK - bool - default y - -config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS - bool - default y - -config SOC_SPI_SUPPORT_CD_SIG - bool - default y - -config SOC_SPI_SUPPORT_CONTINUOUS_TRANS - bool - default y - -config SOC_SPI_SUPPORT_SLAVE_HD_VER2 - bool - default y - -config SOC_SPI_SUPPORT_CLK_AHB - bool - default y - -config SOC_SPI_SUPPORT_CLK_XTAL - bool - default y - -config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT - bool - default y - -config SOC_MEMSPI_IS_INDEPENDENT - bool - default y - -config SOC_SPI_MAX_PRE_DIVIDER - int - default 16 - -config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE - bool - default y - -config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND - bool - default y - -config SOC_SPI_MEM_SUPPORT_AUTO_RESUME - bool - default y - -config SOC_SPI_MEM_SUPPORT_IDLE_INTR - bool - default y - -config SOC_SPI_MEM_SUPPORT_SW_SUSPEND - bool - default y - -config SOC_SPI_MEM_SUPPORT_CHECK_SUS - bool - default y - -config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE - bool - default y - -config SOC_SPI_MEM_SUPPORT_WRAP - bool - default y - -config SOC_MEMSPI_SRC_FREQ_48M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_24M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_12M_SUPPORTED - bool - default y - -config SOC_SYSTIMER_COUNTER_NUM - int - default 2 - -config SOC_SYSTIMER_ALARM_NUM - int - default 3 - -config SOC_SYSTIMER_BIT_WIDTH_LO - int - default 32 - -config SOC_SYSTIMER_BIT_WIDTH_HI - int - default 20 - -config SOC_SYSTIMER_FIXED_DIVIDER - bool - default y - -config SOC_SYSTIMER_INT_LEVEL - bool - default y - -config SOC_SYSTIMER_ALARM_MISS_COMPENSATE - bool - default y - -config SOC_TIMER_GROUPS - int - default 2 - -config SOC_TIMER_GROUP_TIMERS_PER_GROUP - int - default 1 - -config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH - int - default 54 - -config SOC_TIMER_GROUP_SUPPORT_XTAL - bool - default y - -config SOC_TIMER_GROUP_SUPPORT_AHB - bool - default y - -config SOC_TIMER_GROUP_TOTAL_TIMERS - int - default 2 - -config SOC_TWAI_CONTROLLER_NUM - int - default 1 - -config SOC_TWAI_CLK_SUPPORT_APB - bool - default y - -config SOC_TWAI_BRP_MIN - int - default 2 - -config SOC_TWAI_BRP_MAX - int - default 16384 - -config SOC_TWAI_SUPPORTS_RX_STATUS - bool - default y - -config SOC_EFUSE_DIS_PAD_JTAG - bool - default y - -config SOC_EFUSE_DIS_USB_JTAG - bool - default y - -config SOC_EFUSE_DIS_DIRECT_BOOT - bool - default y - -config SOC_EFUSE_SOFT_DIS_JTAG - bool - default y - -config SOC_EFUSE_DIS_ICACHE - bool - default y - -config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK - bool - default y - -config SOC_SECURE_BOOT_V2_RSA - bool - default y - -config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS - int - default 3 - -config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS - bool - default y - -config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY - bool - default y - -config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX - int - default 32 - -config SOC_FLASH_ENCRYPTION_XTS_AES - bool - default y - -config SOC_FLASH_ENCRYPTION_XTS_AES_128 - bool - default y - -config SOC_UART_NUM - int - default 2 - -config SOC_UART_FIFO_LEN - int - default 128 - -config SOC_UART_BITRATE_MAX - int - default 5000000 - -config SOC_UART_SUPPORT_WAKEUP_INT - bool - default y - -config SOC_UART_SUPPORT_AHB_CLK - bool - default y - -config SOC_UART_SUPPORT_RTC_CLK - bool - default y - -config SOC_UART_SUPPORT_XTAL_CLK - bool - default y - -config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND - bool - default y - -config SOC_COEX_HW_PTI - bool - default y - -config SOC_PHY_DIG_REGS_MEM_SIZE - int - default 21 - -config SOC_PM_SUPPORT_BT_WAKEUP - bool - default y - -config SOC_PM_SUPPORT_CPU_PD - bool - default y - -config SOC_PM_SUPPORT_BT_PD - bool - default y - -config SOC_PM_SUPPORT_RC_FAST_PD - bool - default y - -config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY - bool - default y - -config SOC_CLK_XTAL32K_SUPPORTED - bool - default y - -config SOC_CLK_RC32K_SUPPORTED - bool - default y - -config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC - bool - default y - -config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL - bool - default y - -config SOC_BLE_SUPPORTED - bool - default y - -config SOC_BLE_MESH_SUPPORTED - bool - default y - -config SOC_ESP_NIMBLE_CONTROLLER - bool - default y - -config SOC_BLE_50_SUPPORTED - bool - default y - -config SOC_BLE_DEVICE_PRIVACY_SUPPORTED - bool - default y diff --git a/components/soc/esp32h4/include/soc/adc_channel.h b/components/soc/esp32h4/include/soc/adc_channel.h deleted file mode 100644 index dbaf294e0c..0000000000 --- a/components/soc/esp32h4/include/soc/adc_channel.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define ADC1_GPIO0_CHANNEL 0 -#define ADC1_CHANNEL_0_GPIO_NUM 0 - -#define ADC1_GPIO1_CHANNEL 1 -#define ADC1_CHANNEL_1_GPIO_NUM 1 - -#define ADC1_GPIO2_CHANNEL 2 -#define ADC1_CHANNEL_2_GPIO_NUM 2 - -#define ADC1_GPIO3_CHANNEL 3 -#define ADC1_CHANNEL_3_GPIO_NUM 3 - -#define ADC1_GPIO4_CHANNEL 4 -#define ADC1_CHANNEL_4_GPIO_NUM 4 - -#define ADC2_GPIO5_CHANNEL 0 -#define ADC2_CHANNEL_0_GPIO_NUM 5 diff --git a/components/soc/esp32h4/include/soc/apb_saradc_reg.h b/components/soc/esp32h4/include/soc/apb_saradc_reg.h deleted file mode 100644 index 13b87a95ce..0000000000 --- a/components/soc/esp32h4/include/soc/apb_saradc_reg.h +++ /dev/null @@ -1,642 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_APB_SARADC_REG_H_ -#define _SOC_APB_SARADC_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) -/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ -/*description: wait arbit signal stable after sar_done*/ -#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 -#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) -#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 -#define APB_SARADC_WAIT_ARB_CYCLE_S 30 -/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ -/*description: force option to xpd sar blocks*/ -#define APB_SARADC_XPD_SAR_FORCE 0x00000003 -#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) -#define APB_SARADC_XPD_SAR_FORCE_V 0x3 -#define APB_SARADC_XPD_SAR_FORCE_S 27 -/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ -#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) -#define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23)) -#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1 -#define APB_SARADC_SAR_PATT_P_CLEAR_S 23 -/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define APB_SARADC_SAR_PATT_LEN 0x00000007 -#define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S)) -#define APB_SARADC_SAR_PATT_LEN_V 0x7 -#define APB_SARADC_SAR_PATT_LEN_S 15 -/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ -/*description: SAR clock divider*/ -#define APB_SARADC_SAR_CLK_DIV 0x000000FF -#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) -#define APB_SARADC_SAR_CLK_DIV_V 0xFF -#define APB_SARADC_SAR_CLK_DIV_S 7 -/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define APB_SARADC_SAR_CLK_GATED (BIT(6)) -#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) -#define APB_SARADC_SAR_CLK_GATED_V 0x1 -#define APB_SARADC_SAR_CLK_GATED_S 6 -/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_START (BIT(1)) -#define APB_SARADC_START_M (BIT(1)) -#define APB_SARADC_START_V 0x1 -#define APB_SARADC_START_S 1 -/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_START_FORCE (BIT(0)) -#define APB_SARADC_START_FORCE_M (BIT(0)) -#define APB_SARADC_START_FORCE_V 0x1 -#define APB_SARADC_START_FORCE_S 0 - -#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) -/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: to enable saradc timer trigger*/ -#define APB_SARADC_TIMER_EN (BIT(24)) -#define APB_SARADC_TIMER_EN_M (BIT(24)) -#define APB_SARADC_TIMER_EN_V 0x1 -#define APB_SARADC_TIMER_EN_S 24 -/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ -/*description: to set saradc timer target*/ -#define APB_SARADC_TIMER_TARGET 0x00000FFF -#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) -#define APB_SARADC_TIMER_TARGET_V 0xFFF -#define APB_SARADC_TIMER_TARGET_S 12 -/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ -#define APB_SARADC_SAR2_INV (BIT(10)) -#define APB_SARADC_SAR2_INV_M (BIT(10)) -#define APB_SARADC_SAR2_INV_V 0x1 -#define APB_SARADC_SAR2_INV_S 10 -/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ -#define APB_SARADC_SAR1_INV (BIT(9)) -#define APB_SARADC_SAR1_INV_M (BIT(9)) -#define APB_SARADC_SAR1_INV_V 0x1 -#define APB_SARADC_SAR1_INV_S 9 -/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ -/*description: max conversion number*/ -#define APB_SARADC_MAX_MEAS_NUM 0x000000FF -#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) -#define APB_SARADC_MAX_MEAS_NUM_V 0xFF -#define APB_SARADC_MAX_MEAS_NUM_S 1 -/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) -#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 -#define APB_SARADC_MEAS_NUM_LIMIT_S 0 - -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008) -/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define APB_SARADC_FILTER_FACTOR0 0x00000007 -#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S)) -#define APB_SARADC_FILTER_FACTOR0_V 0x7 -#define APB_SARADC_FILTER_FACTOR0_S 29 -/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ -/*description: */ -#define APB_SARADC_FILTER_FACTOR1 0x00000007 -#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S)) -#define APB_SARADC_FILTER_FACTOR1_V 0x7 -#define APB_SARADC_FILTER_FACTOR1_S 26 - -#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) -/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ -/*description: */ -#define APB_SARADC_STANDBY_WAIT 0x000000FF -#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) -#define APB_SARADC_STANDBY_WAIT_V 0xFF -#define APB_SARADC_STANDBY_WAIT_S 16 -/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ -/*description: */ -#define APB_SARADC_RSTB_WAIT 0x000000FF -#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) -#define APB_SARADC_RSTB_WAIT_V 0xFF -#define APB_SARADC_RSTB_WAIT_S 8 -/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ -/*description: */ -#define APB_SARADC_XPD_WAIT 0x000000FF -#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) -#define APB_SARADC_XPD_WAIT_V 0xFF -#define APB_SARADC_XPD_WAIT_S 0 - -#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) -/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF -#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) -#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF -#define APB_SARADC_SAR1_STATUS_S 0 - -#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) -/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF -#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) -#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF -#define APB_SARADC_SAR2_STATUS_S 0 - -#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) -/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ -#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF -#define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S)) -#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF -#define APB_SARADC_SAR_PATT_TAB1_S 0 - -#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) -/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ -#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF -#define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S)) -#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF -#define APB_SARADC_SAR_PATT_TAB2_S 0 - -#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x020) -/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) -#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31)) -#define APB_SARADC1_ONETIME_SAMPLE_V 0x1 -#define APB_SARADC1_ONETIME_SAMPLE_S 31 -/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) -#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30)) -#define APB_SARADC2_ONETIME_SAMPLE_V 0x1 -#define APB_SARADC2_ONETIME_SAMPLE_S 30 -/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ONETIME_START (BIT(29)) -#define APB_SARADC_ONETIME_START_M (BIT(29)) -#define APB_SARADC_ONETIME_START_V 0x1 -#define APB_SARADC_ONETIME_START_S 29 -/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */ -/*description: */ -#define APB_SARADC_ONETIME_CHANNEL 0x0000000F -#define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S)) -#define APB_SARADC_ONETIME_CHANNEL_V 0xF -#define APB_SARADC_ONETIME_CHANNEL_S 25 -/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ -/*description: */ -#define APB_SARADC_ONETIME_ATTEN 0x00000003 -#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S)) -#define APB_SARADC_ONETIME_ATTEN_V 0x3 -#define APB_SARADC_ONETIME_ATTEN_S 23 -/* APB_SARADC_ONETIME_EN_TEST : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ONETIME_EN_TEST (BIT(22)) -#define APB_SARADC_ONETIME_EN_TEST_M (BIT(22)) -#define APB_SARADC_ONETIME_EN_TEST_V 0x1 -#define APB_SARADC_ONETIME_EN_TEST_S 22 - -#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024) -/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: adc2 arbiter uses fixed priority*/ -#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 -#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 -/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ -/*description: Set adc2 arbiter wifi priority*/ -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 -/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ -/*description: Set adc2 arbiter rtc priority*/ -#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 -/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Set adc2 arbiterapb priority*/ -#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 -#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) -#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 -#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 -/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: adc2 arbiter force grant*/ -#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) -#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 -/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable wifi controller*/ -#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) -#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 -/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable rtc controller*/ -#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) -#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 -/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enableapb controller*/ -#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) -#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 -#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 - -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x028) -/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable apb_adc1_filter*/ -#define APB_SARADC_FILTER_RESET (BIT(31)) -#define APB_SARADC_FILTER_RESET_M (BIT(31)) -#define APB_SARADC_FILTER_RESET_V 0x1 -#define APB_SARADC_FILTER_RESET_S 31 -/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */ -/*description: apb_adc1_filter_factor*/ -#define APB_SARADC_FILTER_CHANNEL0 0x0000000F -#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S)) -#define APB_SARADC_FILTER_CHANNEL0_V 0xF -#define APB_SARADC_FILTER_CHANNEL0_S 22 -/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */ -/*description: */ -#define APB_SARADC_FILTER_CHANNEL1 0x0000000F -#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S)) -#define APB_SARADC_FILTER_CHANNEL1_V 0xF -#define APB_SARADC_FILTER_CHANNEL1_S 18 - -#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x02C) -/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DATA 0x0001FFFF -#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S)) -#define APB_SARADC_ADC1_DATA_V 0x1FFFF -#define APB_SARADC_ADC1_DATA_S 0 - -#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x030) -/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DATA 0x0001FFFF -#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S)) -#define APB_SARADC_ADC2_DATA_V 0x1FFFF -#define APB_SARADC_ADC2_DATA_S 0 - -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x034) -/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES0_LOW 0x00001FFF -#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S)) -#define APB_SARADC_THRES0_LOW_V 0x1FFF -#define APB_SARADC_THRES0_LOW_S 18 -/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES0_HIGH 0x00001FFF -#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S)) -#define APB_SARADC_THRES0_HIGH_V 0x1FFF -#define APB_SARADC_THRES0_HIGH_S 5 -/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ -/*description: */ -#define APB_SARADC_THRES0_CHANNEL 0x0000000F -#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S)) -#define APB_SARADC_THRES0_CHANNEL_V 0xF -#define APB_SARADC_THRES0_CHANNEL_S 0 - -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) -/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES1_LOW 0x00001FFF -#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S)) -#define APB_SARADC_THRES1_LOW_V 0x1FFF -#define APB_SARADC_THRES1_LOW_S 18 -/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ -/*description: saradc1's thres0 monitor thres*/ -#define APB_SARADC_THRES1_HIGH 0x00001FFF -#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S)) -#define APB_SARADC_THRES1_HIGH_V 0x1FFF -#define APB_SARADC_THRES1_HIGH_S 5 -/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ -/*description: */ -#define APB_SARADC_THRES1_CHANNEL 0x0000000F -#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S)) -#define APB_SARADC_THRES1_CHANNEL_V 0xF -#define APB_SARADC_THRES1_CHANNEL_S 0 - -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C) -/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_EN (BIT(31)) -#define APB_SARADC_THRES0_EN_M (BIT(31)) -#define APB_SARADC_THRES0_EN_V 0x1 -#define APB_SARADC_THRES0_EN_S 31 -/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_EN (BIT(30)) -#define APB_SARADC_THRES1_EN_M (BIT(30)) -#define APB_SARADC_THRES1_EN_V 0x1 -#define APB_SARADC_THRES1_EN_S 30 -/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES2_EN (BIT(29)) -#define APB_SARADC_THRES2_EN_M (BIT(29)) -#define APB_SARADC_THRES2_EN_V 0x1 -#define APB_SARADC_THRES2_EN_S 29 -/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES3_EN (BIT(28)) -#define APB_SARADC_THRES3_EN_M (BIT(28)) -#define APB_SARADC_THRES3_EN_V 0x1 -#define APB_SARADC_THRES3_EN_S 28 -/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_THRES_ALL_EN (BIT(27)) -#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) -#define APB_SARADC_THRES_ALL_EN_V 0x1 -#define APB_SARADC_THRES_ALL_EN_S 27 - -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x040) -/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 -/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 -/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 -/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 -/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 -/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_ENA_S 26 - -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044) -/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 -/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 -/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 -/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 -/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 -/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_RAW_S 26 - -#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x048) -/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_ST_S 31 -/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_ST_S 30 -/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 -/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 -/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_ST_S 27 -/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_ST_S 26 - -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x04C) -/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) -#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 -#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 -/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) -#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 -#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 -/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) -#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 -#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 -/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) -#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 -#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 -/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) -#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 -#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 -/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) -#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 -#define APB_SARADC_THRES1_LOW_INT_CLR_S 26 - -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x050) -/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: enable apb_adc use spi_dma*/ -#define APB_SARADC_APB_ADC_TRANS (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) -#define APB_SARADC_APB_ADC_TRANS_V 0x1 -#define APB_SARADC_APB_ADC_TRANS_S 31 -/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: reset_apb_adc_state*/ -#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) -#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 -#define APB_SARADC_APB_ADC_RESET_FSM_S 30 -/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ -/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ -#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF -#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) -#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF -#define APB_SARADC_APB_ADC_EOF_NUM_S 0 - -#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x054) -/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ -/*description: Set this bit to enable clk_apll*/ -#define APB_SARADC_CLK_SEL 0x00000003 -#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) -#define APB_SARADC_CLK_SEL_V 0x3 -#define APB_SARADC_CLK_SEL_S 21 -/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: */ -#define APB_SARADC_CLK_EN (BIT(20)) -#define APB_SARADC_CLK_EN_M (BIT(20)) -#define APB_SARADC_CLK_EN_V 0x1 -#define APB_SARADC_CLK_EN_S 20 -/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ -/*description: Fractional clock divider denominator value*/ -#define APB_SARADC_CLKM_DIV_A 0x0000003F -#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) -#define APB_SARADC_CLKM_DIV_A_V 0x3F -#define APB_SARADC_CLKM_DIV_A_S 14 -/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ -/*description: Fractional clock divider numerator value*/ -#define APB_SARADC_CLKM_DIV_B 0x0000003F -#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) -#define APB_SARADC_CLKM_DIV_B_V 0x3F -#define APB_SARADC_CLKM_DIV_B_S 8 -/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ -/*description: Integral I2S clock divider value*/ -#define APB_SARADC_CLKM_DIV_NUM 0x000000FF -#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) -#define APB_SARADC_CLKM_DIV_NUM_V 0xFF -#define APB_SARADC_CLKM_DIV_NUM_S 0 - -#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058) -/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_TSENS_PU (BIT(22)) -#define APB_SARADC_TSENS_PU_M (BIT(22)) -#define APB_SARADC_TSENS_PU_V 0x1 -#define APB_SARADC_TSENS_PU_S 22 -/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ -/*description: */ -#define APB_SARADC_TSENS_CLK_DIV 0x000000FF -#define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S)) -#define APB_SARADC_TSENS_CLK_DIV_V 0xFF -#define APB_SARADC_TSENS_CLK_DIV_S 14 -/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_TSENS_IN_INV (BIT(13)) -#define APB_SARADC_TSENS_IN_INV_M (BIT(13)) -#define APB_SARADC_TSENS_IN_INV_V 0x1 -#define APB_SARADC_TSENS_IN_INV_S 13 -/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define APB_SARADC_TSENS_OUT 0x000000FF -#define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S)) -#define APB_SARADC_TSENS_OUT_V 0xFF -#define APB_SARADC_TSENS_OUT_S 0 - -#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x05C) -/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define APB_SARADC_TSENS_CLK_SEL (BIT(15)) -#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15)) -#define APB_SARADC_TSENS_CLK_SEL_V 0x1 -#define APB_SARADC_TSENS_CLK_SEL_S 15 -/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define APB_SARADC_TSENS_CLK_INV (BIT(14)) -#define APB_SARADC_TSENS_CLK_INV_M (BIT(14)) -#define APB_SARADC_TSENS_CLK_INV_V 0x1 -#define APB_SARADC_TSENS_CLK_INV_S 14 -/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define APB_SARADC_TSENS_XPD_FORCE 0x00000003 -#define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S)) -#define APB_SARADC_TSENS_XPD_FORCE_V 0x3 -#define APB_SARADC_TSENS_XPD_FORCE_S 12 -/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ -/*description: */ -#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF -#define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S)) -#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF -#define APB_SARADC_TSENS_XPD_WAIT_S 0 - -#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x060) -/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */ -/*description: */ -#define APB_SARADC_CALI_CFG 0x0001FFFF -#define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S)) -#define APB_SARADC_CALI_CFG_V 0x1FFFF -#define APB_SARADC_CALI_CFG_S 0 - -#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) -/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02102260 ; */ -/*description: */ -#define APB_SARADC_DATE 0xFFFFFFFF -#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S)) -#define APB_SARADC_DATE_V 0xFFFFFFFF -#define APB_SARADC_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_APB_SARADC_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/apb_saradc_struct.h b/components/soc/esp32h4/include/soc/apb_saradc_struct.h deleted file mode 100644 index d1aef9be56..0000000000 --- a/components/soc/esp32h4/include/soc/apb_saradc_struct.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_APB_SARADC_STRUCT_H_ -#define _SOC_APB_SARADC_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct apb_saradc_dev_s { - union { - struct { - uint32_t start_force: 1; - uint32_t start: 1; - uint32_t reserved2: 4; /*0: single mode 1: double mode 2: alternate mode*/ - uint32_t sar_clk_gated: 1; - uint32_t sar_clk_div: 8; /*SAR clock divider*/ - uint32_t sar_patt_len: 3; /*0 ~ 15 means length 1 ~ 16*/ - uint32_t reserved18: 5; - uint32_t sar_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ - uint32_t reserved24: 3; - uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ - uint32_t reserved29: 1; - uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t meas_num_limit: 1; - uint32_t max_meas_num: 8; /*max conversion number*/ - uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ - uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ - uint32_t reserved11: 1; /*1: select saradc timer 0: i2s_ws trigger*/ - uint32_t timer_target: 12; /*to set saradc timer target*/ - uint32_t timer_en: 1; /*to enable saradc timer trigger*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } ctrl2; - union { - struct { - uint32_t reserved0: 26; - uint32_t filter_factor1: 3; - uint32_t filter_factor0: 3; - }; - uint32_t val; - } filter_ctrl1; - union { - struct { - uint32_t xpd_wait: 8; - uint32_t rstb_wait: 8; - uint32_t standby_wait: 8; - uint32_t reserved24: 8; - }; - uint32_t val; - } fsm_wait; - uint32_t sar1_status; /**/ - uint32_t sar2_status; /**/ - union { - struct { - uint32_t sar_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } sar_patt_tab[2]; - union { - struct { - uint32_t reserved0: 22; - uint32_t onetime_en_test: 1; - uint32_t onetime_atten: 2; - uint32_t onetime_channel: 4; - uint32_t onetime_start: 1; - uint32_t adc2_onetime_sample: 1; - uint32_t adc1_onetime_sample: 1; - }; - uint32_t val; - } onetime_sample; - union { - struct { - uint32_t reserved0: 2; - uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ - uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ - uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ - uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ - uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ - uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ - uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ - uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ - uint32_t reserved13: 19; - }; - uint32_t val; - } apb_adc_arb_ctrl; - union { - struct { - uint32_t reserved0: 18; - uint32_t filter_channel1: 4; - uint32_t filter_channel0: 4; /*apb_adc1_filter_factor*/ - uint32_t reserved26: 5; - uint32_t filter_reset: 1; /*enable apb_adc1_filter*/ - }; - uint32_t val; - } filter_ctrl0; - union { - struct { - uint32_t adc1_data: 17; - uint32_t reserved17:15; - }; - uint32_t val; - } apb_saradc1_data_status; - union { - struct { - uint32_t adc2_data: 17; - uint32_t reserved17:15; - }; - uint32_t val; - } apb_saradc2_data_status; - union { - struct { - uint32_t thres0_channel: 4; - uint32_t reserved4: 1; - uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/ - uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/ - uint32_t reserved31: 1; - }; - uint32_t val; - } thres0_ctrl; - union { - struct { - uint32_t thres1_channel: 4; - uint32_t reserved4: 1; - uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/ - uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/ - uint32_t reserved31: 1; - }; - uint32_t val; - } thres1_ctrl; - union { - struct { - uint32_t reserved0: 27; - uint32_t thres_all_en: 1; - uint32_t thres3_en: 1; - uint32_t thres2_en: 1; - uint32_t thres1_en: 1; - uint32_t thres0_en: 1; - }; - uint32_t val; - } thres_ctrl; - union { - struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t reserved0: 26; - uint32_t thres1_low: 1; - uint32_t thres0_low: 1; - uint32_t thres1_high: 1; - uint32_t thres0_high: 1; - uint32_t adc2_done: 1; - uint32_t adc1_done: 1; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ - uint32_t reserved16: 14; - uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ - uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ - uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ - uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ - uint32_t clk_en: 1; - uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ - uint32_t reserved23: 9; - }; - uint32_t val; - } apb_adc_clkm_conf; - union { - struct { - uint32_t tsens_out: 8; - uint32_t reserved8: 5; - uint32_t tsens_in_inv: 1; - uint32_t tsens_clk_div: 8; - uint32_t tsens_pu: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } apb_tsens_ctrl; - union { - struct { - uint32_t tsens_xpd_wait: 12; - uint32_t tsens_xpd_force: 2; - uint32_t tsens_clk_inv: 1; - uint32_t tsens_clk_sel: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } apb_tsens_ctrl2; - union { - struct { - uint32_t cali_cfg: 17; - uint32_t reserved17:15; - }; - uint32_t val; - } cali; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - uint32_t apb_ctrl_date; /**/ -} apb_saradc_dev_t; -extern apb_saradc_dev_t APB_SARADC; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_APB_SARADC_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/soc/bb_reg.h b/components/soc/esp32h4/include/soc/bb_reg.h deleted file mode 100644 index cd950c4da9..0000000000 --- a/components/soc/esp32h4/include/soc/bb_reg.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/* Some of the baseband control registers. - * PU/PD fields defined here are used in sleep related functions. - */ - -#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) -#define BB_FFT_FORCE_PU (BIT(3)) -#define BB_FFT_FORCE_PU_M (BIT(3)) -#define BB_FFT_FORCE_PU_V 1 -#define BB_FFT_FORCE_PU_S 3 -#define BB_FFT_FORCE_PD (BIT(2)) -#define BB_FFT_FORCE_PD_M (BIT(2)) -#define BB_FFT_FORCE_PD_V 1 -#define BB_FFT_FORCE_PD_S 2 -#define BB_DC_EST_FORCE_PU (BIT(1)) -#define BB_DC_EST_FORCE_PU_M (BIT(1)) -#define BB_DC_EST_FORCE_PU_V 1 -#define BB_DC_EST_FORCE_PU_S 1 -#define BB_DC_EST_FORCE_PD (BIT(0)) -#define BB_DC_EST_FORCE_PD_M (BIT(0)) -#define BB_DC_EST_FORCE_PD_V 1 -#define BB_DC_EST_FORCE_PD_S 0 diff --git a/components/soc/esp32h4/include/soc/boot_mode.h b/components/soc/esp32h4/include/soc/boot_mode.h deleted file mode 100644 index f782959272..0000000000 --- a/components/soc/esp32h4/include/soc/boot_mode.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SOC_BOOT_MODE_H_ -#define _SOC_BOOT_MODE_H_ - -#include "soc.h" - -/*SPI Boot*/ -#define IS_1XXX(v) (((v)&0x08)==0x08) - -/*Download Boot, SPI(or SDIO_V2)/UART0*/ -#define IS_00XX(v) (((v)&0x0c)==0x00) - -/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ -#define IS_0000(v) (((v)&0x0f)==0x00) - -/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ -#define IS_0001(v) (((v)&0x0f)==0x01) - -/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ -#define IS_0010(v) (((v)&0x0f)==0x02) - -/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ -#define IS_0011(v) (((v)&0x0f)==0x03) - -/*legacy SPI Boot*/ -#define IS_0100(v) (((v)&0x0f)==0x04) - -/*ATE/ANALOG Mode*/ -#define IS_0101(v) (((v)&0x0f)==0x05) - -/*SPI(or SDIO_V1) download Mode*/ -#define IS_0110(v) (((v)&0x0f)==0x06) - -/*Diagnostic Mode+UART0 download Mode*/ -#define IS_0111(v) (((v)&0x0f)==0x07) - - - -#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) - -/*do not include download mode*/ -#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) - -/*all spi boot including spi/legacy*/ -#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) - -/*all faster spi boot including spi*/ -#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) - -#if SUPPORT_SDIO_DOWNLOAD - -/*all sdio V2 of failing edge input, failing edge output*/ -#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) - -/*all sdio V2 of failing edge input, raising edge output*/ -#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) - -/*all sdio V2 of raising edge input, failing edge output*/ -#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) - -/*all sdio V2 of raising edge input, raising edge output*/ -#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) - -/*all sdio V1 of raising edge input, failing edge output*/ -#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) - -/*do not include joint download mode*/ -#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) -#else - -/*do not include joint download mode*/ -#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) - -#endif - -/*joint download boot*/ -#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) - -/*ATE mode*/ -#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) - -/*used by ETS_IS_SDIO_UART_BOOT*/ -#define SEL_NO_BOOT 0 -#define SEL_SDIO_BOOT BIT0 -#define SEL_UART_BOOT BIT1 -#define SEL_SPI_SLAVE_BOOT BIT2 - -#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32h4/include/soc/clk_tree_defs.h b/components/soc/esp32h4/include/soc/clk_tree_defs.h deleted file mode 100644 index 6e4cc77920..0000000000 --- a/components/soc/esp32h4/include/soc/clk_tree_defs.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/* - ************************ ESP32H4 Root Clock Source *************************** - * 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description) - * - * This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK. - * - * The exact frequency of RC_FAST_CLK cannot be computed in runtime through calibration. You can output the RC_FAST - * clock signal to a gpio pin in order to get the frequency through an oscillscope or a logic analyzer. - * - * 2) External 32MHz Crystal Clock: XTAL - * - * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description) - * - * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock - * can be computed in runtime through calibration. - * - * 4) External 32kHz Crystal Clock (optional): XTAL32K - * - * The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N - * pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the - * XTAL_32K_P pin. - * - * XTAL32K_CLK can also be calibrated to get its exact frequency. - * - * 5) Internal 32kHz RC Oscillator: RC32K - * - * The exact frequency of this clock can be computed in runtime through calibration. - */ - -/* With the default value of CK8M_DFREQ = 600, RC_FAST clock frequency nears 7 MHz +/- 7% */ //<---- DFREQ to be adjusted! */ -#define SOC_CLK_RC_FAST_FREQ_APPROX 7000000 /*!< Approximate RC_FAST_CLK frequency in Hz */ -/* With the default value of DCAP = 128 */ //<---- DCAP to be adjusted! -#define SOC_CLK_RC_SLOW_FREQ_APPROX 130000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ -/* With the default value of DFREQ = 707 */ //<---- DFREQ to be adjusted! -#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ -#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ - -// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr] -// {loc}: EXT, INT -// {type}: XTAL, RC -// [attr] - optional: [frequency], FAST, SLOW -/** - * @brief Root clock - */ -typedef enum { - SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8MHz RC oscillator */ - SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ - SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */ - SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */ - SOC_ROOT_CLK_INT_RC32K /*!< Internal 32kHz RC oscillator */ -} soc_root_clk_t; - -/** - * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK - * @note Enum values are matched with the register field values on purpose - */ -typedef enum { - SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */ - SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_XTAL_D2 = 3, /*!< Select XTAL_D2_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ -} soc_cpu_clk_src_t; - -/** - * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK - * @note Enum values are matched with the register field values on purpose - */ -typedef enum { - SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ - SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ -} soc_rtc_slow_clk_src_t; - -/** - * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK - * @note Enum values are matched with the register field values on purpose - */ -typedef enum { - SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ - SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ - SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ -} soc_rtc_fast_clk_src_t; - -// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] -// {[upstream]clock_name}: AHB etc. -// [attr] - optional: FAST, SLOW, D, F -/** - * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) - * - * @note enum starts from 1, to save 0 for special purpose - */ -typedef enum { - // For CPU domain - SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or XTAL_D2 by configuring soc_cpu_clk_src_t */ - // For RTC domain - SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ - SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */ - // For digital domain: peripherals, WIFI, BLE - SOC_MOD_CLK_AHB, /*< AHB_CLK sources from CPU with a configurable divider */ - SOC_MOD_CLK_APB, /*< APB_CLK source is derived from AHB clock */ - SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */ - SOC_MOD_CLK_XTAL32K, /*< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ - SOC_MOD_CLK_RC_FAST, /*< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */ - SOC_MOD_CLK_XTAL, /*< XTAL_CLK comes from the external 32MHz crystal */ - SOC_MOD_CLK_PLL, /*< PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz */ - SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ -} soc_module_clk_t; - -//////////////////////////////////////////////////SYSTIMER/////////////////////////////////////////////////////////////// - -/** - * @brief Type of SYSTIMER clock source - */ -typedef enum { - SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ - SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ -} soc_periph_systimer_clk_src_t; - -//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of GPTimer - * - * The following code can be used to iterate all possible clocks: - * @code{c} - * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; - * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { - * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; - * // Test GPTimer with the clock `clk` - * } - * @endcode - */ -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL} - -/** - * @brief Type of GPTimer clock source - */ -typedef enum { - GPTIMER_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB as the source clock */ - GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */ -} soc_periph_gptimer_clk_src_t; - -/** - * @brief Type of Timer Group clock source, reserved for the legacy timer group driver - */ -typedef enum { - TIMER_SRC_CLK_AHB = SOC_MOD_CLK_AHB, /*!< Timer group clock source is AHB */ - TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ - TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< Timer group clock source default choice is AHB */ -} soc_periph_tg_clk_src_legacy_t; - -//////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of RMT - */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL} - -/** - * @brief Type of RMT clock source - */ -typedef enum { - RMT_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB clock as the source clock */ - RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */ -} soc_periph_rmt_clk_src_t; - -/** - * @brief Type of RMT clock source, reserved for the legacy RMT driver - */ -typedef enum { - RMT_BASECLK_AHB = SOC_MOD_CLK_AHB, /*!< RMT source clock is AHB */ - RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */ - RMT_BASECLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< RMT source clock default choice is AHB */ -} soc_periph_rmt_clk_src_legacy_t; - -//////////////////////////////////////////////////Temp Sensor/////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of Temperature Sensor - */ -#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} - -/** - * @brief Type of Temp Sensor clock source - */ -typedef enum { - TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ -} soc_periph_temperature_sensor_clk_src_t; - -///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// - -/** - * @brief Type of UART clock source, reserved for the legacy UART driver - */ -typedef enum { - UART_SCLK_AHB = SOC_MOD_CLK_AHB, /*!< UART source clock is AHB CLK */ - UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ - UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ - UART_SCLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< UART source clock default choice is AHB */ -} soc_periph_uart_clk_src_legacy_t; - -///////////////////////////////////////////////////// I2S ////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of - */ -#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL, SOC_MOD_CLK_XTAL} - -/** - * @brief I2S clock source enum - */ -typedef enum { - I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL, /*!< Select SOC_MOD_CLK_PLL as the default source clock */ - I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL, /*!< Select PLL as the source clock */ - I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ -} soc_periph_i2s_clk_src_t; - -/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of I2C - */ -#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} - -/** - * @brief Type of I2C clock source. - */ -typedef enum { - I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, - I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, - I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, -} soc_periph_i2c_clk_src_t; - -/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of SPI - */ -#define SOC_SPI_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL} - -/** - * @brief Type of SPI clock source. - */ -typedef enum { - SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB 48M as SPI source clock */ - SPI_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB 48M as SPI source clock */ - SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL 32M as SPI source clock */ -} soc_periph_spi_clk_src_t; - -//////////////////////////////////////////////////SDM////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of SDM - */ -#define SOC_SDM_CLKS {SOC_MOD_CLK_APB} - -/** - * @brief Sigma Delta Modulator clock source - */ -typedef enum { - SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ - SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ -} soc_periph_sdm_clk_src_t; - -//////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of Glitch Filter - */ -#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB} - -/** - * @brief Glitch filter clock source - */ - -typedef enum { - GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */ - GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */ -} soc_periph_glitch_filter_clk_src_t; - -//////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of ADC digital controller - */ -// TODO: temporary support, need to check while supporting -#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M} - -/** - * @brief ADC digital controller clock source - */ -// TODO: temporary support, need to check while supporting -typedef enum { - ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ - ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ -} soc_periph_adc_digi_clk_src_t; - -//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of MWDT - */ -#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APB} - -/** - * @brief MWDT clock source - */ -typedef enum { - MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MWDT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ - MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */ -} soc_periph_mwdt_clk_src_t; - -//////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// - -/** - * @brief Array initializer for all supported clock sources of LEDC - */ -#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_AHB, SOC_MOD_CLK_RC_FAST} - -/** - * @brief Type of LEDC clock source, reserved for the legacy LEDC driver - */ -typedef enum { - LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ - LEDC_USE_APB_CLK = SOC_MOD_CLK_AHB, /*!< Select APB(=AHB) as the source clock */ - LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - - LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ -} soc_periph_ledc_clk_src_legacy_t; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/clkout_channel.h b/components/soc/esp32h4/include/soc/clkout_channel.h deleted file mode 100644 index e86e92c09d..0000000000 --- a/components/soc/esp32h4/include/soc/clkout_channel.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SOC_CLKOUT_CHANNEL_H -#define _SOC_CLKOUT_CHANNEL_H - -// ESP32H4 CLKOUT signals has no corresponding iomux pins - -#endif diff --git a/components/soc/esp32h4/include/soc/dport_access.h b/components/soc/esp32h4/include/soc/dport_access.h deleted file mode 100644 index d8bc730478..0000000000 --- a/components/soc/esp32h4/include/soc/dport_access.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _DPORT_ACCESS_H_ -#define _DPORT_ACCESS_H_ - -#include -#include "soc.h" -#include "soc/uart_reg.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions - -#define DPORT_INTERRUPT_DISABLE() -#define DPORT_INTERRUPT_RESTORE() - -/** - * @brief Read a sequence of DPORT registers to the buffer. - * - * @param[out] buff_out Contains the read data. - * @param[in] address Initial address for reading registers. - * @param[in] num_words The number of words. - */ -void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); - -// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. -#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) -#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) - -// Write value to DPORT register (does not require protecting) -#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) - -#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) -#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) - -//get bit or get bits from register -#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) - -//set bit or set bits to register -#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) - -//clear bit or clear bits of register -#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) - -//set bits of register controlled by mask -#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) - -//get field from register, uses field _S & _V to determine mask -#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) - -//set field to register, used when _f is not left shifted by _f##_S -#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) - -//get field value from a variable, used when _f is not left shifted by _f##_S -#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) - -//get field value from a variable, used when _f is left shifted by _f##_S -#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) - -//set field value to a variable, used when _f is not left shifted by _f##_S -#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) - -//set field value to a variable, used when _f is left shifted by _f##_S -#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) - -//generate a value from a field value, used when _f is not left shifted by _f##_S -#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) - -//generate a value from a field value, used when _f is left shifted by _f##_S -#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) - -//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. -#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) -#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) -#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) -#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) - -#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) - -//write value to register -#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) - -//clear bits of register controlled by mask -#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) - -//set bits of register controlled by mask -#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) - -//get bits of register controlled by mask -#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) - -//get bits of register controlled by highest bit and lowest bit -#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) - -//set bits of register controlled by mask and shift -#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) - -//get field of register -#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) -//}} - -#ifdef __cplusplus -} -#endif - -#endif /* _DPORT_ACCESS_H_ */ diff --git a/components/soc/esp32h4/include/soc/dport_reg.h b/components/soc/esp32h4/include/soc/dport_reg.h deleted file mode 100644 index 1fcf518d3d..0000000000 --- a/components/soc/esp32h4/include/soc/dport_reg.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_DPORT_REG_H_ -#define _SOC_DPORT_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "soc.h" - -#ifndef __ASSEMBLER__ -#include "dport_access.h" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /*_SOC_DPORT_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/ext_mem_defs.h b/components/soc/esp32h4/include/soc/ext_mem_defs.h deleted file mode 100644 index 0bde2f7b4f..0000000000 --- a/components/soc/esp32h4/include/soc/ext_mem_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _CACHE_MEMORY_H_ -#define _CACHE_MEMORY_H_ - -#include "esp_bit_defs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*IRAM0 is connected with Cache IBUS0*/ -#define IRAM0_ADDRESS_LOW 0x4037C000 -#define IRAM0_ADDRESS_HIGH 0x403E0000 -#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 -#define IRAM0_CACHE_ADDRESS_HIGH 0x42800000 - -/*DRAM0 is connected with Cache DBUS0*/ -#define DRAM0_ADDRESS_LOW 0x3FC80000 -#define DRAM0_ADDRESS_HIGH 0x3FCE0000 -#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 -#define DRAM0_CACHE_ADDRESS_HIGH 0x3C800000 -#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH - -#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) - -#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) -#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) -#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) -#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) - -#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) -#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) - -//TODO, remove these cache function dependencies -#define CACHE_IBUS 0 -#define CACHE_IBUS_MMU_START 0 -#define CACHE_IBUS_MMU_END 0x200 - -#define CACHE_DBUS 1 -#define CACHE_DBUS_MMU_START 0 -#define CACHE_DBUS_MMU_END 0x200 - -#define CACHE_IROM_MMU_START 0 -#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() -#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) - -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END -#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() -#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) - -#define CACHE_DROM_MMU_MAX_END 0x200 - -#define ICACHE_MMU_SIZE 0x200 -#define DCACHE_MMU_SIZE 0x200 - -#define MMU_BUS_START(i) 0 -#define MMU_BUS_SIZE(i) 0x200 - -#define MMU_INVALID BIT(8) -#define MMU_VALID 0 -#define MMU_TYPE 0 -#define MMU_ACCESS_FLASH 0 - -#define CACHE_MAX_SYNC_NUM 0x400000 -#define CACHE_MAX_LOCK_NUM 0x8000 - -/** - * MMU entry valid bit mask for mapping value. For an entry: - * valid bit + value bits - * valid bit is BIT(8), so value bits are 0xff - */ -#define MMU_VALID_VAL_MASK 0xff -/** - * Max MMU available paddr page num. - * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: - * 256 * 64KB, means MMU can support 16MB paddr at most - */ -#define MMU_MAX_PADDR_PAGE_NUM 256 -/** - * This is the mask used for mapping. e.g.: - * 0x4200_0000 & MMU_VADDR_MASK - */ -#define MMU_VADDR_MASK 0x7fffff -//MMU entry num -#define MMU_ENTRY_NUM 128 - -#define CACHE_ICACHE_LOW_SHIFT 0 -#define CACHE_ICACHE_HIGH_SHIFT 2 -#define CACHE_DCACHE_LOW_SHIFT 4 -#define CACHE_DCACHE_HIGH_SHIFT 6 - -#define CACHE_MEMORY_IBANK0_ADDR 0x4037c000 - -#define SOC_MMU_DBUS_VADDR_BASE 0x3C000000 -#define SOC_MMU_IBUS_VADDR_BASE 0x42000000 - -/*------------------------------------------------------------------------------ - * MMU Linear Address - *----------------------------------------------------------------------------*/ -/** - * - 64KB MMU page size: the last 0xFFFF, which is the offset - * - 128 MMU entries, needs 0x7F to hold it. - * - * Therefore, 0x7F,FFFF - */ -#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF - -/** - * - If high linear address isn't 0, this means MMU can recognize these addresses - * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. - * Under this condition, we use the max linear space. - */ -#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) -#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) -#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) -#else -#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) -#endif - -#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) -#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) -#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) -#else -#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) -#endif - -/** - * I/D share the MMU linear address range - */ -_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); - - -#ifdef __cplusplus -} -#endif - -#endif /*_CACHE_MEMORY_H_ */ diff --git a/components/soc/esp32h4/include/soc/extmem_reg.h b/components/soc/esp32h4/include/soc/extmem_reg.h deleted file mode 100644 index a830b14ad3..0000000000 --- a/components/soc/esp32h4/include/soc/extmem_reg.h +++ /dev/null @@ -1,984 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_EXTMEM_REG_H_ -#define _SOC_EXTMEM_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) -/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ -#define EXTMEM_ICACHE_ENABLE (BIT(0)) -#define EXTMEM_ICACHE_ENABLE_M (BIT(0)) -#define EXTMEM_ICACHE_ENABLE_V 0x1 -#define EXTMEM_ICACHE_ENABLE_S 0 - -#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) -/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable core1 ibus 0: enable 1: disable*/ -#define EXTMEM_ICACHE_SHUT_DBUS (BIT(1)) -#define EXTMEM_ICACHE_SHUT_DBUS_M (BIT(1)) -#define EXTMEM_ICACHE_SHUT_DBUS_V 0x1 -#define EXTMEM_ICACHE_SHUT_DBUS_S 1 -/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable core0 ibus 0: enable 1: disable*/ -#define EXTMEM_ICACHE_SHUT_IBUS (BIT(0)) -#define EXTMEM_ICACHE_SHUT_IBUS_M (BIT(0)) -#define EXTMEM_ICACHE_SHUT_IBUS_V 0x1 -#define EXTMEM_ICACHE_SHUT_IBUS_S 0 - -#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp - 1: power down*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 -/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of icache tag memory. - 1: close gating 0: open clock gating.*/ -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 - -#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C) -/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: The bit is used to enable the second section of prelock function.*/ -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 -/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The bit is used to enable the first section of prelock function.*/ -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 - -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010) -/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to configure the first start virtual address - of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 - -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) -/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to configure the second start virtual address - of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 - -#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) -/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The bits are used to configure the first length of data locking - which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 -/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the second length of data locking - which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 - -#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C) -/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to indicate unlock/lock operation is finished.*/ -#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) -#define EXTMEM_ICACHE_LOCK_DONE_V 0x1 -#define EXTMEM_ICACHE_LOCK_DONE_S 2 -/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable unlock operation. It will be cleared - by hardware after unlock operation done.*/ -#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 -#define EXTMEM_ICACHE_UNLOCK_ENA_S 1 -/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable lock operation. It will be cleared - by hardware after lock operation done.*/ -#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_LOCK_ENA_V 0x1 -#define EXTMEM_ICACHE_LOCK_ENA_S 0 - -#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020) -/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ -#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) -#define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_LOCK_ADDR_S 0 - -#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024) -/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for lock operations. - The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ -#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF -#define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) -#define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF -#define EXTMEM_ICACHE_LOCK_SIZE_S 0 - -#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028) -/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate invalidate operation is finished.*/ -#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) -#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) -#define EXTMEM_ICACHE_SYNC_DONE_V 0x1 -#define EXTMEM_ICACHE_SYNC_DONE_S 1 -/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable invalidate operation. It will be cleared - by hardware after invalidate operation done.*/ -#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 -#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 - -#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C) -/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ -#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) -#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_SYNC_ADDR_S 0 - -#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030) -/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ -/*description: The bits are used to configure the length for sync operations. - The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ -#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF -#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) -#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF -#define EXTMEM_ICACHE_SYNC_SIZE_S 0 - -#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034) -/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to configure the direction of preload operation. - 1: descending 0: ascending.*/ -#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 -/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to indicate preload operation is finished.*/ -#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_DONE_S 1 -/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable preload operation. It will be cleared - by hardware after preload operation done.*/ -#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_ENA_S 0 - -#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) -/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address for - preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ -#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) -#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 - -#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) -/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The bits are used to configure the length for preload operation. - The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ -#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF -#define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) -#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF -#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 - -#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) -/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ -/*description: The bits are used to configure trigger conditions for autoload. - 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ -#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) -#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 -#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 -/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bits are used to configure the direction of autoload. 1: - descending 0: ascending.*/ -#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 -/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ -/*description: The bit is used to indicate autoload operation is finished.*/ -#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) -#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) -#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 -#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 -/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable and disable autoload operation. It - is combined with icache_autoload_done. 1: enable 0: disable.*/ -#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) -#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) -#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 -#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bits are used to enable the second section for autoload operation.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bits are used to enable the first section for autoload operation.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044) -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the - first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048) -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: The bits are used to configure the length of the first section - for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x04C) -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The bits are used to configure the start virtual address of the - second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x050) -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: The bits are used to configure the length of the second section - for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 - -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x054) -/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */ -/*description: The bits are used to configure the start virtual address of ibus - to access flash. The register is used to give constraints to ibus access counter.*/ -#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 - -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x058) -/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */ -/*description: The bits are used to configure the end virtual address of ibus - to access flash. The register is used to give constraints to ibus access counter.*/ -#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 - -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x05C) -/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */ -/*description: The bits are used to configure the start virtual address of dbus - to access flash. The register is used to give constraints to dbus access counter.*/ -#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 - -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x060) -/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */ -/*description: The bits are used to configure the end virtual address of dbus - to access flash. The register is used to give constraints to dbus access counter.*/ -#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 - -#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x064) -/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear dbus counter.*/ -#define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1)) -#define EXTMEM_DBUS_ACS_CNT_CLR_M (BIT(1)) -#define EXTMEM_DBUS_ACS_CNT_CLR_V 0x1 -#define EXTMEM_DBUS_ACS_CNT_CLR_S 1 -/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear ibus counter.*/ -#define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0)) -#define EXTMEM_IBUS_ACS_CNT_CLR_M (BIT(0)) -#define EXTMEM_IBUS_ACS_CNT_CLR_V 0x1 -#define EXTMEM_IBUS_ACS_CNT_CLR_S 0 - -#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x068) -/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of the cache miss caused - by ibus access flash.*/ -#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF -#define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) -#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_IBUS_ACS_MISS_CNT_S 0 - -#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x06C) -/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of ibus access flash through icache.*/ -#define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF -#define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) -#define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF -#define EXTMEM_IBUS_ACS_CNT_S 0 - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x070) -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of the cache miss caused - by dbus access flash.*/ -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 - -#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x074) -/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to count the number of dbus access flash through icache.*/ -#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF -#define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) -#define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF -#define EXTMEM_DBUS_ACS_CNT_S 0 - -#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x078) -/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dbus counter overflow.*/ -#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 -/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus counter overflow.*/ -#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 -/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by mmu entry fault.*/ -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by preload configurations fault.*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by sync configurations fault.*/ -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 - -#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x07C) -/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dbus counter overflow.*/ -#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 -/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus counter overflow.*/ -#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 -/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by mmu entry fault.*/ -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by preload configurations fault.*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by sync configurations fault.*/ -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 - -#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x080) -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash miss - counter overflow.*/ -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 -/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus access flash/spiram - counter overflow.*/ -#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 -/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram - miss counter overflow.*/ -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 -/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus access flash/spiram - counter overflow.*/ -#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 -/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by mmu entry fault.*/ -#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 -#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by preload configurations fault.*/ -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 -/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by sync configurations fault.*/ -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 - -#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x084) -/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by dbus trying to write icache*/ -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5 -/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail.*/ -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 -/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access icache while - the corresponding dbus is disabled which include speculative access.*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3 -/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by authentication fail.*/ -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 -/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable interrupt by cpu access icache while - the corresponding ibus is disabled which include speculative access.*/ -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 - -#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x088) -/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by dbus trying to write icache*/ -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5 -/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail.*/ -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 -/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access icache while - the corresponding dbus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3 -/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by authentication fail.*/ -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 -/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to clear interrupt by cpu access icache while - the corresponding ibus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 - -#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x08C) -/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by dbus trying to write icache*/ -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (BIT(5)) -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5 -/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail.*/ -#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 -#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 -/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access icache while - the core0_dbus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3 -/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by authentication fail.*/ -#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 -#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 -/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by ibus trying to write icache*/ -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 -/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate interrupt by cpu access icache while - the core0_ibus is disabled or icache is disabled which include speculative access.*/ -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 - -#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x090) -/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access dbus when - authentication fail. 0: WORLD0 1: WORLD1*/ -#define EXTMEM_CORE0_DBUS_WORLD (BIT(3)) -#define EXTMEM_CORE0_DBUS_WORLD_M (BIT(3)) -#define EXTMEM_CORE0_DBUS_WORLD_V 0x1 -#define EXTMEM_CORE0_DBUS_WORLD_S 3 -/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access dbus - when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ -#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) -#define EXTMEM_CORE0_DBUS_ATTR_V 0x7 -#define EXTMEM_CORE0_DBUS_ATTR_S 0 - -#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x094) -/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: The bits are used to indicate the virtual address of CPU access - dbus when authentication fail.*/ -#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF -#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) -#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF -#define EXTMEM_CORE0_DBUS_VADDR_S 0 - -#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x098) -/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the world of CPU access ibus when - authentication fail. 0: WORLD0 1: WORLD1*/ -#define EXTMEM_CORE0_IBUS_WORLD (BIT(3)) -#define EXTMEM_CORE0_IBUS_WORLD_M (BIT(3)) -#define EXTMEM_CORE0_IBUS_WORLD_V 0x1 -#define EXTMEM_CORE0_IBUS_WORLD_S 3 -/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The bits are used to indicate the attribute of CPU access ibus - when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ -#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) -#define EXTMEM_CORE0_IBUS_ATTR_V 0x7 -#define EXTMEM_CORE0_IBUS_ATTR_S 0 - -#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x09C) -/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: The bits are used to indicate the virtual address of CPU access - ibus when authentication fail.*/ -#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF -#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) -#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF -#define EXTMEM_CORE0_IBUS_VADDR_S 0 - -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x0A0) -/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */ -/*description: The right-most 3 bits are used to indicate the operations which - cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ -#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F -#define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) -#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF -#define EXTMEM_CACHE_MMU_FAULT_CODE_S 10 -/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ -#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000003FF -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x3FF -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 - -#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4) -/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The bits are used to indicate the virtual address which cause mmu fault..*/ -#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF -#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) -#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF -#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 - -#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A8) -/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable wrap around mode when read data from flash.*/ -#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 - -#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0AC) -/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 -/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 -/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable clock gating to save power when access - mmu memory 0: enable 1: disable*/ -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 - -#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x0B0) -/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */ -/*description: The bit is used to indicate whether icache main fsm is in idle - state or not. 1: in idle state 0: not in idle state*/ -#define EXTMEM_ICACHE_STATE 0x00000FFF -#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) -#define EXTMEM_ICACHE_STATE_V 0xFFF -#define EXTMEM_ICACHE_STATE_S 0 - -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x0B4) -/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 -/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 - -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x0B8) -/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of external memory encrypt - and decrypt clock. 1: close gating 0: open clock gating.*/ -#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) -#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) -#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 -#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 -/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of automatic crypt clock. - 1: close gating 0: open clock gating.*/ -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 -/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to close clock gating of manual crypt clock. - 1: close gating 0: open clock gating.*/ -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 - -#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0BC) -/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by icache pre-load done.*/ -#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 -/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by icache pre-load done.*/ -#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 -/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by icache pre-load done.*/ -#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 -#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 - -#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0C0) -/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to clear the interrupt by icache sync done.*/ -#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) -#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 -#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 -/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable the interrupt by icache sync done.*/ -#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) -#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 -#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 -/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to indicate the interrupt by icache sync done.*/ -#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) -#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 -#define EXTMEM_ICACHE_SYNC_INT_ST_S 0 - -#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x0C4) -/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus bit1/bit3: dbus*/ -#define EXTMEM_CACHE_MMU_OWNER 0x0000000F -#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) -#define EXTMEM_CACHE_MMU_OWNER_V 0xF -#define EXTMEM_CACHE_MMU_OWNER_S 0 - -#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x0C8) -/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: The bit is used to enable cache trace function.*/ -#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) -#define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) -#define EXTMEM_CACHE_TRACE_ENA_V 0x1 -#define EXTMEM_CACHE_TRACE_ENA_S 2 -/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The bit is used to disable checking mmu entry fault by sync operation.*/ -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 -/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to disable checking mmu entry fault by preload operation.*/ -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 - -#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x0CC) -/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to indicate icache freeze success*/ -#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) -#define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) -#define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 -#define EXTMEM_ICACHE_FREEZE_DONE_S 2 -/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to configure freeze mode 0: assert busy if - CPU miss 1: assert hit if CPU miss*/ -#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) -#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) -#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 -#define EXTMEM_ICACHE_FREEZE_MODE_S 1 -/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to enable icache freeze mode*/ -#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) -#define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 -#define EXTMEM_ICACHE_FREEZE_ENA_S 0 - -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x0D0) -/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to activate icache atomic operation protection. - In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 - -#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x0D4) -/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to disable request recording which could cause performance issue*/ -#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) -#define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) -#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 -#define EXTMEM_CACHE_REQUEST_BYPASS_S 0 - -#define EXTMEM_IBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0D8) -/* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to configure the ibus permission control section boundary0*/ -#define EXTMEM_IBUS_PMS_LOCK (BIT(0)) -#define EXTMEM_IBUS_PMS_LOCK_M (BIT(0)) -#define EXTMEM_IBUS_PMS_LOCK_V 0x1 -#define EXTMEM_IBUS_PMS_LOCK_S 0 - -#define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0DC) -/* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: The bit is used to configure the ibus permission control section boundary0*/ -#define EXTMEM_IBUS_PMS_BOUNDARY0 0x00000FFF -#define EXTMEM_IBUS_PMS_BOUNDARY0_M ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S)) -#define EXTMEM_IBUS_PMS_BOUNDARY0_V 0xFFF -#define EXTMEM_IBUS_PMS_BOUNDARY0_S 0 - -#define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0E0) -/* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: The bit is used to configure the ibus permission control section boundary1*/ -#define EXTMEM_IBUS_PMS_BOUNDARY1 0x00000FFF -#define EXTMEM_IBUS_PMS_BOUNDARY1_M ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S)) -#define EXTMEM_IBUS_PMS_BOUNDARY1_V 0xFFF -#define EXTMEM_IBUS_PMS_BOUNDARY1_S 0 - -#define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0E4) -/* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: The bit is used to configure the ibus permission control section boundary2*/ -#define EXTMEM_IBUS_PMS_BOUNDARY2 0x00000FFF -#define EXTMEM_IBUS_PMS_BOUNDARY2_M ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S)) -#define EXTMEM_IBUS_PMS_BOUNDARY2_V 0xFFF -#define EXTMEM_IBUS_PMS_BOUNDARY2_S 0 - -#define EXTMEM_IBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0E8) -/* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */ -/*description: The bit is used to configure attribute of the ibus permission - control section2 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/ -#define EXTMEM_IBUS_PMS_SCT2_ATTR 0x0000000F -#define EXTMEM_IBUS_PMS_SCT2_ATTR_M ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S)) -#define EXTMEM_IBUS_PMS_SCT2_ATTR_V 0xF -#define EXTMEM_IBUS_PMS_SCT2_ATTR_S 4 -/* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */ -/*description: The bit is used to configure attribute of the ibus permission - control section1 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/ -#define EXTMEM_IBUS_PMS_SCT1_ATTR 0x0000000F -#define EXTMEM_IBUS_PMS_SCT1_ATTR_M ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S)) -#define EXTMEM_IBUS_PMS_SCT1_ATTR_V 0xF -#define EXTMEM_IBUS_PMS_SCT1_ATTR_S 0 - -#define EXTMEM_DBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0EC) -/* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The bit is used to configure the ibus permission control section boundary0*/ -#define EXTMEM_DBUS_PMS_LOCK (BIT(0)) -#define EXTMEM_DBUS_PMS_LOCK_M (BIT(0)) -#define EXTMEM_DBUS_PMS_LOCK_V 0x1 -#define EXTMEM_DBUS_PMS_LOCK_S 0 - -#define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0F0) -/* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: The bit is used to configure the dbus permission control section boundary0*/ -#define EXTMEM_DBUS_PMS_BOUNDARY0 0x00000FFF -#define EXTMEM_DBUS_PMS_BOUNDARY0_M ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S)) -#define EXTMEM_DBUS_PMS_BOUNDARY0_V 0xFFF -#define EXTMEM_DBUS_PMS_BOUNDARY0_S 0 - -#define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0F4) -/* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: The bit is used to configure the dbus permission control section boundary1*/ -#define EXTMEM_DBUS_PMS_BOUNDARY1 0x00000FFF -#define EXTMEM_DBUS_PMS_BOUNDARY1_M ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S)) -#define EXTMEM_DBUS_PMS_BOUNDARY1_V 0xFFF -#define EXTMEM_DBUS_PMS_BOUNDARY1_S 0 - -#define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0F8) -/* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: The bit is used to configure the dbus permission control section boundary2*/ -#define EXTMEM_DBUS_PMS_BOUNDARY2 0x00000FFF -#define EXTMEM_DBUS_PMS_BOUNDARY2_M ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S)) -#define EXTMEM_DBUS_PMS_BOUNDARY2_V 0xFFF -#define EXTMEM_DBUS_PMS_BOUNDARY2_S 0 - -#define EXTMEM_DBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0FC) -/* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ -/*description: The bit is used to configure attribute of the dbus permission - control section2 bit0: load in world0 bit2: load in world1*/ -#define EXTMEM_DBUS_PMS_SCT2_ATTR 0x00000003 -#define EXTMEM_DBUS_PMS_SCT2_ATTR_M ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S)) -#define EXTMEM_DBUS_PMS_SCT2_ATTR_V 0x3 -#define EXTMEM_DBUS_PMS_SCT2_ATTR_S 2 -/* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */ -/*description: The bit is used to configure attribute of the dbus permission - control section1 bit0: load in world0 bit2: load in world1*/ -#define EXTMEM_DBUS_PMS_SCT1_ATTR 0x00000003 -#define EXTMEM_DBUS_PMS_SCT1_ATTR_M ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S)) -#define EXTMEM_DBUS_PMS_SCT1_ATTR_V 0x3 -#define EXTMEM_DBUS_PMS_SCT1_ATTR_S 0 - -#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100) -/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Reserved.*/ -#define EXTMEM_CLK_EN (BIT(0)) -#define EXTMEM_CLK_EN_M (BIT(0)) -#define EXTMEM_CLK_EN_V 0x1 -#define EXTMEM_CLK_EN_S 0 - -#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) -/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */ -/*description: Reserved.*/ -#define EXTMEM_DATE 0x0FFFFFFF -#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) -#define EXTMEM_DATE_V 0xFFFFFFF -#define EXTMEM_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_EXTMEM_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/fe_reg.h b/components/soc/esp32h4/include/soc/fe_reg.h deleted file mode 100644 index 52bd44bd49..0000000000 --- a/components/soc/esp32h4/include/soc/fe_reg.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" - -/* Some of the RF frontend control registers. - * PU/PD fields defined here are used in sleep related functions. - */ - -#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) -#define FE_IQ_EST_FORCE_PU (BIT(5)) -#define FE_IQ_EST_FORCE_PU_M (BIT(5)) -#define FE_IQ_EST_FORCE_PU_V 1 -#define FE_IQ_EST_FORCE_PU_S 5 -#define FE_IQ_EST_FORCE_PD (BIT(4)) -#define FE_IQ_EST_FORCE_PD_M (BIT(4)) -#define FE_IQ_EST_FORCE_PD_V 1 -#define FE_IQ_EST_FORCE_PD_S 4 - -#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) -#define FE2_TX_INF_FORCE_PU (BIT(10)) -#define FE2_TX_INF_FORCE_PU_M (BIT(10)) -#define FE2_TX_INF_FORCE_PU_V 1 -#define FE2_TX_INF_FORCE_PU_S 10 -#define FE2_TX_INF_FORCE_PD (BIT(9)) -#define FE2_TX_INF_FORCE_PD_M (BIT(9)) -#define FE2_TX_INF_FORCE_PD_V 1 -#define FE2_TX_INF_FORCE_PD_S 9 diff --git a/components/soc/esp32h4/include/soc/gdma_channel.h b/components/soc/esp32h4/include/soc/gdma_channel.h deleted file mode 100644 index 5f0b818bd2..0000000000 --- a/components/soc/esp32h4/include/soc/gdma_channel.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER` -#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1) -#define SOC_GDMA_TRIG_PERIPH_SPI2 (0) -#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2) -#define SOC_GDMA_TRIG_PERIPH_I2S0 (3) -#define SOC_GDMA_TRIG_PERIPH_AES0 (6) -#define SOC_GDMA_TRIG_PERIPH_SHA0 (7) -#define SOC_GDMA_TRIG_PERIPH_ADC0 (8) diff --git a/components/soc/esp32h4/include/soc/gdma_reg.h b/components/soc/esp32h4/include/soc/gdma_reg.h deleted file mode 100644 index 2669dee6d1..0000000000 --- a/components/soc/esp32h4/include/soc/gdma_reg.h +++ /dev/null @@ -1,2411 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_DMA_REG_H_ -#define _SOC_DMA_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x000) -/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is underflow.*/ -#define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x1 -#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S 12 -/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is overflow.*/ -#define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x1 -#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S 11 -/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is underflow.*/ -#define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_RAW_M (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_RAW_V 0x1 -#define DMA_INFIFO_UDF_CH0_INT_RAW_S 10 -/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is overflow.*/ -#define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_RAW_M (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_RAW_V 0x1 -#define DMA_INFIFO_OVF_CH0_INT_RAW_S 9 -/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 -/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 -/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 -/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ -#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 -#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 -/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ -#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_RAW_M (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_RAW_V 0x1 -#define DMA_OUT_EOF_CH0_INT_RAW_S 4 -/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ -#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_RAW_M (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_RAW_V 0x1 -#define DMA_OUT_DONE_CH0_INT_RAW_S 3 -/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ -#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 -#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 -/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ -#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 -#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 -/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 0.*/ -#define DMA_IN_DONE_CH0_INT_RAW (BIT(0)) -#define DMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) -#define DMA_IN_DONE_CH0_INT_RAW_V 0x1 -#define DMA_IN_DONE_CH0_INT_RAW_S 0 - -#define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x004) -/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_ST_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x1 -#define DMA_OUTFIFO_UDF_CH0_INT_ST_S 12 -/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_ST_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x1 -#define DMA_OUTFIFO_OVF_CH0_INT_ST_S 11 -/* DMA_INFIFO_UDF_CH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH0_INT_ST (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_ST_M (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_ST_V 0x1 -#define DMA_INFIFO_UDF_CH0_INT_ST_S 10 -/* DMA_INFIFO_OVF_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH0_INT_ST (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_ST_M (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_ST_V 0x1 -#define DMA_INFIFO_OVF_CH0_INT_ST_S 9 -/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 -/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 -/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x1 -#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 -/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x1 -#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5 -/* DMA_OUT_EOF_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH0_INT_ST (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_ST_M (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_ST_V 0x1 -#define DMA_OUT_EOF_CH0_INT_ST_S 4 -/* DMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH0_INT_ST (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_ST_M (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_ST_V 0x1 -#define DMA_OUT_DONE_CH0_INT_ST_S 3 -/* DMA_IN_ERR_EOF_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_ST_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x1 -#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2 -/* DMA_IN_SUC_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_ST_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x1 -#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1 -/* DMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH0_INT_ST (BIT(0)) -#define DMA_IN_DONE_CH0_INT_ST_M (BIT(0)) -#define DMA_IN_DONE_CH0_INT_ST_V 0x1 -#define DMA_IN_DONE_CH0_INT_ST_S 0 - -#define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x008) -/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x1 -#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S 12 -/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x1 -#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S 11 -/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH0_INT_ENA (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_ENA_M (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_ENA_V 0x1 -#define DMA_INFIFO_UDF_CH0_INT_ENA_S 10 -/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH0_INT_ENA (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_ENA_M (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_ENA_V 0x1 -#define DMA_INFIFO_OVF_CH0_INT_ENA_S 9 -/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 -/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 -/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x1 -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 -/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x1 -#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 -/* DMA_OUT_EOF_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_ENA_M (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_ENA_V 0x1 -#define DMA_OUT_EOF_CH0_INT_ENA_S 4 -/* DMA_OUT_DONE_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_ENA_M (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_ENA_V 0x1 -#define DMA_OUT_DONE_CH0_INT_ENA_S 3 -/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x1 -#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 -/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x1 -#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 -/* DMA_IN_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH0_INT_ENA (BIT(0)) -#define DMA_IN_DONE_CH0_INT_ENA_M (BIT(0)) -#define DMA_IN_DONE_CH0_INT_ENA_V 0x1 -#define DMA_IN_DONE_CH0_INT_ENA_S 0 - -#define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x00C) -/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x1 -#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S 12 -/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x1 -#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S 11 -/* DMA_INFIFO_UDF_CH0_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH0_INT_CLR (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_CLR_M (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_CLR_V 0x1 -#define DMA_INFIFO_UDF_CH0_INT_CLR_S 10 -/* DMA_INFIFO_OVF_CH0_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH0_INT_CLR (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_CLR_M (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_CLR_V 0x1 -#define DMA_INFIFO_OVF_CH0_INT_CLR_S 9 -/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 -/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 -/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x1 -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 -/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x1 -#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 -/* DMA_OUT_EOF_CH0_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_CLR_M (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_CLR_V 0x1 -#define DMA_OUT_EOF_CH0_INT_CLR_S 4 -/* DMA_OUT_DONE_CH0_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_CLR_M (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_CLR_V 0x1 -#define DMA_OUT_DONE_CH0_INT_CLR_S 3 -/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x1 -#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 -/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x1 -#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 -/* DMA_IN_DONE_CH0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH0_INT_CLR (BIT(0)) -#define DMA_IN_DONE_CH0_INT_CLR_M (BIT(0)) -#define DMA_IN_DONE_CH0_INT_CLR_V 0x1 -#define DMA_IN_DONE_CH0_INT_CLR_S 0 - -#define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x010) -/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 1 is underflow.*/ -#define DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x1 -#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S 12 -/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 1 is overflow.*/ -#define DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x1 -#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S 11 -/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 1 is underflow.*/ -#define DMA_INFIFO_UDF_CH1_INT_RAW (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_RAW_M (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_RAW_V 0x1 -#define DMA_INFIFO_UDF_CH1_INT_RAW_S 10 -/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 1 is overflow.*/ -#define DMA_INFIFO_OVF_CH1_INT_RAW (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_RAW_M (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_RAW_V 0x1 -#define DMA_INFIFO_OVF_CH1_INT_RAW_S 9 -/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.*/ -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 -/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 1.*/ -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 -/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 1.*/ -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 -/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 1.*/ -#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 -#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 -/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 1.*/ -#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_RAW_M (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_RAW_V 0x1 -#define DMA_OUT_EOF_CH1_INT_RAW_S 4 -/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.*/ -#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_RAW_M (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_RAW_V 0x1 -#define DMA_OUT_DONE_CH1_INT_RAW_S 3 -/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw interrupt is reserved.*/ -#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 -#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 -/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.*/ -#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 -#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 -/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 1.*/ -#define DMA_IN_DONE_CH1_INT_RAW (BIT(0)) -#define DMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) -#define DMA_IN_DONE_CH1_INT_RAW_V 0x1 -#define DMA_IN_DONE_CH1_INT_RAW_S 0 - -#define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x014) -/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_ST_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x1 -#define DMA_OUTFIFO_UDF_CH1_INT_ST_S 12 -/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_ST_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x1 -#define DMA_OUTFIFO_OVF_CH1_INT_ST_S 11 -/* DMA_INFIFO_UDF_CH1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH1_INT_ST (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_ST_M (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_ST_V 0x1 -#define DMA_INFIFO_UDF_CH1_INT_ST_S 10 -/* DMA_INFIFO_OVF_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH1_INT_ST (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_ST_M (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_ST_V 0x1 -#define DMA_INFIFO_OVF_CH1_INT_ST_S 9 -/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 -/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 -/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x1 -#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 -/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x1 -#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5 -/* DMA_OUT_EOF_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH1_INT_ST (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_ST_M (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_ST_V 0x1 -#define DMA_OUT_EOF_CH1_INT_ST_S 4 -/* DMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH1_INT_ST (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_ST_M (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_ST_V 0x1 -#define DMA_OUT_DONE_CH1_INT_ST_S 3 -/* DMA_IN_ERR_EOF_CH1_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_ST_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x1 -#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2 -/* DMA_IN_SUC_EOF_CH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_ST_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x1 -#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1 -/* DMA_IN_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH1_INT_ST (BIT(0)) -#define DMA_IN_DONE_CH1_INT_ST_M (BIT(0)) -#define DMA_IN_DONE_CH1_INT_ST_V 0x1 -#define DMA_IN_DONE_CH1_INT_ST_S 0 - -#define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x018) -/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x1 -#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S 12 -/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x1 -#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S 11 -/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH1_INT_ENA (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_ENA_M (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_ENA_V 0x1 -#define DMA_INFIFO_UDF_CH1_INT_ENA_S 10 -/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH1_INT_ENA (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_ENA_M (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_ENA_V 0x1 -#define DMA_INFIFO_OVF_CH1_INT_ENA_S 9 -/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 -/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 -/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x1 -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 -/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x1 -#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 -/* DMA_OUT_EOF_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_ENA_M (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_ENA_V 0x1 -#define DMA_OUT_EOF_CH1_INT_ENA_S 4 -/* DMA_OUT_DONE_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_ENA_M (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_ENA_V 0x1 -#define DMA_OUT_DONE_CH1_INT_ENA_S 3 -/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x1 -#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 -/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x1 -#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 -/* DMA_IN_DONE_CH1_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH1_INT_ENA (BIT(0)) -#define DMA_IN_DONE_CH1_INT_ENA_M (BIT(0)) -#define DMA_IN_DONE_CH1_INT_ENA_V 0x1 -#define DMA_IN_DONE_CH1_INT_ENA_S 0 - -#define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x01C) -/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x1 -#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S 12 -/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x1 -#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S 11 -/* DMA_INFIFO_UDF_CH1_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH1_INT_CLR (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_CLR_M (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_CLR_V 0x1 -#define DMA_INFIFO_UDF_CH1_INT_CLR_S 10 -/* DMA_INFIFO_OVF_CH1_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH1_INT_CLR (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_CLR_M (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_CLR_V 0x1 -#define DMA_INFIFO_OVF_CH1_INT_CLR_S 9 -/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 -/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 -/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x1 -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 -/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x1 -#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 -/* DMA_OUT_EOF_CH1_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_CLR_M (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_CLR_V 0x1 -#define DMA_OUT_EOF_CH1_INT_CLR_S 4 -/* DMA_OUT_DONE_CH1_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_CLR_M (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_CLR_V 0x1 -#define DMA_OUT_DONE_CH1_INT_CLR_S 3 -/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x1 -#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 -/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x1 -#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 -/* DMA_IN_DONE_CH1_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH1_INT_CLR (BIT(0)) -#define DMA_IN_DONE_CH1_INT_CLR_M (BIT(0)) -#define DMA_IN_DONE_CH1_INT_CLR_V 0x1 -#define DMA_IN_DONE_CH1_INT_CLR_S 0 - -#define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x020) -/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 2 is underflow.*/ -#define DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x1 -#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S 12 -/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 2 is overflow.*/ -#define DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x1 -#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S 11 -/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 2 is underflow.*/ -#define DMA_INFIFO_UDF_CH2_INT_RAW (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_RAW_M (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_RAW_V 0x1 -#define DMA_INFIFO_UDF_CH2_INT_RAW_S 10 -/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 2 is overflow.*/ -#define DMA_INFIFO_OVF_CH2_INT_RAW (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_RAW_M (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_RAW_V 0x1 -#define DMA_INFIFO_OVF_CH2_INT_RAW_S 9 -/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.*/ -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 -/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 2.*/ -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 -/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 2.*/ -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 -/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 2.*/ -#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 -#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 -/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory for Tx channel 2.*/ -#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_RAW_M (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_RAW_V 0x1 -#define DMA_OUT_EOF_CH2_INT_RAW_S 4 -/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.*/ -#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_RAW_M (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_RAW_V 0x1 -#define DMA_OUT_DONE_CH2_INT_RAW_S 3 -/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw interrupt is reserved.*/ -#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 -#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 -/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.*/ -#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x1 -#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 -/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for Rx channel 2.*/ -#define DMA_IN_DONE_CH2_INT_RAW (BIT(0)) -#define DMA_IN_DONE_CH2_INT_RAW_M (BIT(0)) -#define DMA_IN_DONE_CH2_INT_RAW_V 0x1 -#define DMA_IN_DONE_CH2_INT_RAW_S 0 - -#define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x024) -/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_ST_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x1 -#define DMA_OUTFIFO_UDF_CH2_INT_ST_S 12 -/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_ST_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x1 -#define DMA_OUTFIFO_OVF_CH2_INT_ST_S 11 -/* DMA_INFIFO_UDF_CH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH2_INT_ST (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_ST_M (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_ST_V 0x1 -#define DMA_INFIFO_UDF_CH2_INT_ST_S 10 -/* DMA_INFIFO_OVF_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH2_INT_ST (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_ST_M (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_ST_V 0x1 -#define DMA_INFIFO_OVF_CH2_INT_ST_S 9 -/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 -/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 -/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x1 -#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 -/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x1 -#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5 -/* DMA_OUT_EOF_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH2_INT_ST (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_ST_M (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_ST_V 0x1 -#define DMA_OUT_EOF_CH2_INT_ST_S 4 -/* DMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH2_INT_ST (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_ST_M (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_ST_V 0x1 -#define DMA_OUT_DONE_CH2_INT_ST_S 3 -/* DMA_IN_ERR_EOF_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_ST_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x1 -#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2 -/* DMA_IN_SUC_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_ST_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x1 -#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1 -/* DMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH2_INT_ST (BIT(0)) -#define DMA_IN_DONE_CH2_INT_ST_M (BIT(0)) -#define DMA_IN_DONE_CH2_INT_ST_V 0x1 -#define DMA_IN_DONE_CH2_INT_ST_S 0 - -#define DMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x028) -/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x1 -#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S 12 -/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x1 -#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S 11 -/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH2_INT_ENA (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_ENA_M (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_ENA_V 0x1 -#define DMA_INFIFO_UDF_CH2_INT_ENA_S 10 -/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH2_INT_ENA (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_ENA_M (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_ENA_V 0x1 -#define DMA_INFIFO_OVF_CH2_INT_ENA_S 9 -/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 -/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 -/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x1 -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 -/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x1 -#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 -/* DMA_OUT_EOF_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_ENA_M (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_ENA_V 0x1 -#define DMA_OUT_EOF_CH2_INT_ENA_S 4 -/* DMA_OUT_DONE_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_ENA_M (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_ENA_V 0x1 -#define DMA_OUT_DONE_CH2_INT_ENA_S 3 -/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x1 -#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 -/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x1 -#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 -/* DMA_IN_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH2_INT_ENA (BIT(0)) -#define DMA_IN_DONE_CH2_INT_ENA_M (BIT(0)) -#define DMA_IN_DONE_CH2_INT_ENA_V 0x1 -#define DMA_IN_DONE_CH2_INT_ENA_S 0 - -#define DMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x02C) -/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x1 -#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S 12 -/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x1 -#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S 11 -/* DMA_INFIFO_UDF_CH2_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_UDF_CH2_INT_CLR (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_CLR_M (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_CLR_V 0x1 -#define DMA_INFIFO_UDF_CH2_INT_CLR_S 10 -/* DMA_INFIFO_OVF_CH2_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ -#define DMA_INFIFO_OVF_CH2_INT_CLR (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_CLR_M (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_CLR_V 0x1 -#define DMA_INFIFO_OVF_CH2_INT_CLR_S 9 -/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x1 -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 -/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x1 -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 -/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x1 -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 -/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ -#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x1 -#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 -/* DMA_OUT_EOF_CH2_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ -#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_CLR_M (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_CLR_V 0x1 -#define DMA_OUT_EOF_CH2_INT_CLR_S 4 -/* DMA_OUT_DONE_CH2_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ -#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_CLR_M (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_CLR_V 0x1 -#define DMA_OUT_DONE_CH2_INT_CLR_S 3 -/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ -#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x1 -#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 -/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ -#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x1 -#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 -/* DMA_IN_DONE_CH2_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ -#define DMA_IN_DONE_CH2_INT_CLR (BIT(0)) -#define DMA_IN_DONE_CH2_INT_CLR_M (BIT(0)) -#define DMA_IN_DONE_CH2_INT_CLR_V 0x1 -#define DMA_IN_DONE_CH2_INT_CLR_S 0 - -#define DMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x040) -/* DMA_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_AHB_TESTADDR 0x00000003 -#define DMA_AHB_TESTADDR_M ((DMA_AHB_TESTADDR_V)<<(DMA_AHB_TESTADDR_S)) -#define DMA_AHB_TESTADDR_V 0x3 -#define DMA_AHB_TESTADDR_S 4 -/* DMA_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_AHB_TESTMODE 0x00000007 -#define DMA_AHB_TESTMODE_M ((DMA_AHB_TESTMODE_V)<<(DMA_AHB_TESTMODE_S)) -#define DMA_AHB_TESTMODE_V 0x7 -#define DMA_AHB_TESTMODE_S 0 - -#define DMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x044) -/* DMA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DMA_CLK_EN (BIT(3)) -#define DMA_CLK_EN_M (BIT(3)) -#define DMA_CLK_EN_V 0x1 -#define DMA_CLK_EN_S 3 -/* DMA_ARB_PRI_DIS : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to disable priority arbitration function.*/ -#define DMA_ARB_PRI_DIS (BIT(2)) -#define DMA_ARB_PRI_DIS_M (BIT(2)) -#define DMA_ARB_PRI_DIS_V 0x1 -#define DMA_ARB_PRI_DIS_S 2 -/* DMA_AHBM_RST_INTER : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit then clear this bit to reset the internal ahb FSM.*/ -#define DMA_AHBM_RST_INTER (BIT(0)) -#define DMA_AHBM_RST_INTER_M (BIT(0)) -#define DMA_AHBM_RST_INTER_V 0x1 -#define DMA_AHBM_RST_INTER_S 0 - -#define DMA_DATE_REG (DR_REG_GDMA_BASE + 0x048) -/* DMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008250 ; */ -/*description: register version.*/ -#define DMA_DATE 0xFFFFFFFF -#define DMA_DATE_M ((DMA_DATE_V)<<(DMA_DATE_S)) -#define DMA_DATE_V 0xFFFFFFFF -#define DMA_DATE_S 0 - -#define DMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x070) -/* DMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define DMA_MEM_TRANS_EN_CH0 (BIT(4)) -#define DMA_MEM_TRANS_EN_CH0_M (BIT(4)) -#define DMA_MEM_TRANS_EN_CH0_V 0x1 -#define DMA_MEM_TRANS_EN_CH0_S 4 -/* DMA_IN_DATA_BURST_EN_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 0 receiving data when accessing internal SRAM.*/ -#define DMA_IN_DATA_BURST_EN_CH0 (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH0_M (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH0_V 0x1 -#define DMA_IN_DATA_BURST_EN_CH0_S 3 -/* DMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 0 reading link descriptor when accessing internal SRAM.*/ -#define DMA_INDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH0_M (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH0_V 0x1 -#define DMA_INDSCR_BURST_EN_CH0_S 2 -/* DMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_IN_LOOP_TEST_CH0 (BIT(1)) -#define DMA_IN_LOOP_TEST_CH0_M (BIT(1)) -#define DMA_IN_LOOP_TEST_CH0_V 0x1 -#define DMA_IN_LOOP_TEST_CH0_S 1 -/* DMA_IN_RST_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ -#define DMA_IN_RST_CH0 (BIT(0)) -#define DMA_IN_RST_CH0_M (BIT(0)) -#define DMA_IN_RST_CH0_V 0x1 -#define DMA_IN_RST_CH0_S 0 - -#define DMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x074) -/* DMA_IN_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define DMA_IN_CHECK_OWNER_CH0 (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH0_M (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH0_V 0x1 -#define DMA_IN_CHECK_OWNER_CH0_S 12 - -#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x078) -/* DMA_IN_BUF_HUNGRY_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH0_M (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH0_V 0x1 -#define DMA_IN_BUF_HUNGRY_CH0_S 27 -/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH0_M (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH0_V 0x1 -#define DMA_IN_REMAIN_UNDER_4B_CH0_S 26 -/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH0_M (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH0_V 0x1 -#define DMA_IN_REMAIN_UNDER_3B_CH0_S 25 -/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH0_M (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH0_V 0x1 -#define DMA_IN_REMAIN_UNDER_2B_CH0_S 24 -/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH0_M (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH0_V 0x1 -#define DMA_IN_REMAIN_UNDER_1B_CH0_S 23 -/* DMA_INFIFO_CNT_CH0 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ -#define DMA_INFIFO_CNT_CH0 0x0000003F -#define DMA_INFIFO_CNT_CH0_M ((DMA_INFIFO_CNT_CH0_V)<<(DMA_INFIFO_CNT_CH0_S)) -#define DMA_INFIFO_CNT_CH0_V 0x3F -#define DMA_INFIFO_CNT_CH0_S 2 -/* DMA_INFIFO_EMPTY_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 0.*/ -#define DMA_INFIFO_EMPTY_CH0 (BIT(1)) -#define DMA_INFIFO_EMPTY_CH0_M (BIT(1)) -#define DMA_INFIFO_EMPTY_CH0_V 0x1 -#define DMA_INFIFO_EMPTY_CH0_S 1 -/* DMA_INFIFO_FULL_CH0 : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 0.*/ -#define DMA_INFIFO_FULL_CH0 (BIT(0)) -#define DMA_INFIFO_FULL_CH0_M (BIT(0)) -#define DMA_INFIFO_FULL_CH0_V 0x1 -#define DMA_INFIFO_FULL_CH0_S 0 - -#define DMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x07C) -/* DMA_INFIFO_POP_CH0 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define DMA_INFIFO_POP_CH0 (BIT(12)) -#define DMA_INFIFO_POP_CH0_M (BIT(12)) -#define DMA_INFIFO_POP_CH0_V 0x1 -#define DMA_INFIFO_POP_CH0_S 12 -/* DMA_INFIFO_RDATA_CH0 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define DMA_INFIFO_RDATA_CH0 0x00000FFF -#define DMA_INFIFO_RDATA_CH0_M ((DMA_INFIFO_RDATA_CH0_V)<<(DMA_INFIFO_RDATA_CH0_S)) -#define DMA_INFIFO_RDATA_CH0_V 0xFFF -#define DMA_INFIFO_RDATA_CH0_S 0 - -#define DMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x080) -/* DMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define DMA_INLINK_PARK_CH0 (BIT(24)) -#define DMA_INLINK_PARK_CH0_M (BIT(24)) -#define DMA_INLINK_PARK_CH0_V 0x1 -#define DMA_INLINK_PARK_CH0_S 24 -/* DMA_INLINK_RESTART_CH0 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define DMA_INLINK_RESTART_CH0 (BIT(23)) -#define DMA_INLINK_RESTART_CH0_M (BIT(23)) -#define DMA_INLINK_RESTART_CH0_V 0x1 -#define DMA_INLINK_RESTART_CH0_S 23 -/* DMA_INLINK_START_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define DMA_INLINK_START_CH0 (BIT(22)) -#define DMA_INLINK_START_CH0_M (BIT(22)) -#define DMA_INLINK_START_CH0_V 0x1 -#define DMA_INLINK_START_CH0_S 22 -/* DMA_INLINK_STOP_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define DMA_INLINK_STOP_CH0 (BIT(21)) -#define DMA_INLINK_STOP_CH0_M (BIT(21)) -#define DMA_INLINK_STOP_CH0_V 0x1 -#define DMA_INLINK_STOP_CH0_S 21 -/* DMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define DMA_INLINK_AUTO_RET_CH0 (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH0_M (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH0_V 0x1 -#define DMA_INLINK_AUTO_RET_CH0_S 20 -/* DMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define DMA_INLINK_ADDR_CH0 0x000FFFFF -#define DMA_INLINK_ADDR_CH0_M ((DMA_INLINK_ADDR_CH0_V)<<(DMA_INLINK_ADDR_CH0_S)) -#define DMA_INLINK_ADDR_CH0_V 0xFFFFF -#define DMA_INLINK_ADDR_CH0_S 0 - -#define DMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x084) -/* DMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_IN_STATE_CH0 0x00000007 -#define DMA_IN_STATE_CH0_M ((DMA_IN_STATE_CH0_V)<<(DMA_IN_STATE_CH0_S)) -#define DMA_IN_STATE_CH0_V 0x7 -#define DMA_IN_STATE_CH0_S 20 -/* DMA_IN_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_IN_DSCR_STATE_CH0 0x00000003 -#define DMA_IN_DSCR_STATE_CH0_M ((DMA_IN_DSCR_STATE_CH0_V)<<(DMA_IN_DSCR_STATE_CH0_S)) -#define DMA_IN_DSCR_STATE_CH0_V 0x3 -#define DMA_IN_DSCR_STATE_CH0_S 18 -/* DMA_INLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH0_M ((DMA_INLINK_DSCR_ADDR_CH0_V)<<(DMA_INLINK_DSCR_ADDR_CH0_S)) -#define DMA_INLINK_DSCR_ADDR_CH0_V 0x3FFFF -#define DMA_INLINK_DSCR_ADDR_CH0_S 0 - -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x088) -/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M ((DMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH0_S)) -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x08C) -/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M ((DMA_IN_ERR_EOF_DES_ADDR_CH0_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH0_S)) -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -#define DMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x090) -/* DMA_INLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH0_M ((DMA_INLINK_DSCR_CH0_V)<<(DMA_INLINK_DSCR_CH0_S)) -#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH0_S 0 - -#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x094) -/* DMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH0_M ((DMA_INLINK_DSCR_BF0_CH0_V)<<(DMA_INLINK_DSCR_BF0_CH0_S)) -#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH0_S 0 - -#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x098) -/* DMA_INLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH0_M ((DMA_INLINK_DSCR_BF1_CH0_V)<<(DMA_INLINK_DSCR_BF1_CH0_S)) -#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH0_S 0 - -#define DMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x09C) -/* DMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 0. The larger of the value the higher - of the priority.*/ -#define DMA_RX_PRI_CH0 0x0000000F -#define DMA_RX_PRI_CH0_M ((DMA_RX_PRI_CH0_V)<<(DMA_RX_PRI_CH0_S)) -#define DMA_RX_PRI_CH0_V 0xF -#define DMA_RX_PRI_CH0_S 0 - -#define DMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x0A0) -/* DMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 0. - 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ -#define DMA_PERI_IN_SEL_CH0 0x0000003F -#define DMA_PERI_IN_SEL_CH0_M ((DMA_PERI_IN_SEL_CH0_V)<<(DMA_PERI_IN_SEL_CH0_S)) -#define DMA_PERI_IN_SEL_CH0_V 0x3F -#define DMA_PERI_IN_SEL_CH0_S 0 - -#define DMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0D0) -/* DMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 transmitting data when accessing internal SRAM.*/ -#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH0_M (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH0_V 0x1 -#define DMA_OUT_DATA_BURST_EN_CH0_S 5 -/* DMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM.*/ -#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH0_M (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH0_V 0x1 -#define DMA_OUTDSCR_BURST_EN_CH0_S 4 -/* DMA_OUT_EOF_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define DMA_OUT_EOF_MODE_CH0 (BIT(3)) -#define DMA_OUT_EOF_MODE_CH0_M (BIT(3)) -#define DMA_OUT_EOF_MODE_CH0_V 0x1 -#define DMA_OUT_EOF_MODE_CH0_S 3 -/* DMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH0_M (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH0_V 0x1 -#define DMA_OUT_AUTO_WRBACK_CH0_S 2 -/* DMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_LOOP_TEST_CH0 (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH0_M (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH0_V 0x1 -#define DMA_OUT_LOOP_TEST_CH0_S 1 -/* DMA_OUT_RST_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ -#define DMA_OUT_RST_CH0 (BIT(0)) -#define DMA_OUT_RST_CH0_M (BIT(0)) -#define DMA_OUT_RST_CH0_V 0x1 -#define DMA_OUT_RST_CH0_S 0 - -#define DMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x0D4) -/* DMA_OUT_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH0_M (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH0_V 0x1 -#define DMA_OUT_CHECK_OWNER_CH0_S 12 - -#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x0D8) -/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH0_M (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x1 -#define DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 -/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH0_M (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x1 -#define DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 -/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH0_M (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x1 -#define DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 -/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH0_M (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x1 -#define DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 -/* DMA_OUTFIFO_CNT_CH0 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ -#define DMA_OUTFIFO_CNT_CH0 0x0000003F -#define DMA_OUTFIFO_CNT_CH0_M ((DMA_OUTFIFO_CNT_CH0_V)<<(DMA_OUTFIFO_CNT_CH0_S)) -#define DMA_OUTFIFO_CNT_CH0_V 0x3F -#define DMA_OUTFIFO_CNT_CH0_S 2 -/* DMA_OUTFIFO_EMPTY_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 0.*/ -#define DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH0_M (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH0_V 0x1 -#define DMA_OUTFIFO_EMPTY_CH0_S 1 -/* DMA_OUTFIFO_FULL_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 0.*/ -#define DMA_OUTFIFO_FULL_CH0 (BIT(0)) -#define DMA_OUTFIFO_FULL_CH0_M (BIT(0)) -#define DMA_OUTFIFO_FULL_CH0_V 0x1 -#define DMA_OUTFIFO_FULL_CH0_S 0 - -#define DMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0x0DC) -/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define DMA_OUTFIFO_PUSH_CH0 (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH0_M (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH0_V 0x1 -#define DMA_OUTFIFO_PUSH_CH0_S 9 -/* DMA_OUTFIFO_WDATA_CH0 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define DMA_OUTFIFO_WDATA_CH0 0x000001FF -#define DMA_OUTFIFO_WDATA_CH0_M ((DMA_OUTFIFO_WDATA_CH0_V)<<(DMA_OUTFIFO_WDATA_CH0_S)) -#define DMA_OUTFIFO_WDATA_CH0_V 0x1FF -#define DMA_OUTFIFO_WDATA_CH0_S 0 - -#define DMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x0E0) -/* DMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define DMA_OUTLINK_PARK_CH0 (BIT(23)) -#define DMA_OUTLINK_PARK_CH0_M (BIT(23)) -#define DMA_OUTLINK_PARK_CH0_V 0x1 -#define DMA_OUTLINK_PARK_CH0_S 23 -/* DMA_OUTLINK_RESTART_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define DMA_OUTLINK_RESTART_CH0 (BIT(22)) -#define DMA_OUTLINK_RESTART_CH0_M (BIT(22)) -#define DMA_OUTLINK_RESTART_CH0_V 0x1 -#define DMA_OUTLINK_RESTART_CH0_S 22 -/* DMA_OUTLINK_START_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define DMA_OUTLINK_START_CH0 (BIT(21)) -#define DMA_OUTLINK_START_CH0_M (BIT(21)) -#define DMA_OUTLINK_START_CH0_V 0x1 -#define DMA_OUTLINK_START_CH0_S 21 -/* DMA_OUTLINK_STOP_CH0 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define DMA_OUTLINK_STOP_CH0 (BIT(20)) -#define DMA_OUTLINK_STOP_CH0_M (BIT(20)) -#define DMA_OUTLINK_STOP_CH0_V 0x1 -#define DMA_OUTLINK_STOP_CH0_S 20 -/* DMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH0_M ((DMA_OUTLINK_ADDR_CH0_V)<<(DMA_OUTLINK_ADDR_CH0_S)) -#define DMA_OUTLINK_ADDR_CH0_V 0xFFFFF -#define DMA_OUTLINK_ADDR_CH0_S 0 - -#define DMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x0E4) -/* DMA_OUT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_STATE_CH0 0x00000007 -#define DMA_OUT_STATE_CH0_M ((DMA_OUT_STATE_CH0_V)<<(DMA_OUT_STATE_CH0_S)) -#define DMA_OUT_STATE_CH0_V 0x7 -#define DMA_OUT_STATE_CH0_S 20 -/* DMA_OUT_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_DSCR_STATE_CH0 0x00000003 -#define DMA_OUT_DSCR_STATE_CH0_M ((DMA_OUT_DSCR_STATE_CH0_V)<<(DMA_OUT_DSCR_STATE_CH0_S)) -#define DMA_OUT_DSCR_STATE_CH0_V 0x3 -#define DMA_OUT_DSCR_STATE_CH0_S 18 -/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH0_M ((DMA_OUTLINK_DSCR_ADDR_CH0_V)<<(DMA_OUTLINK_DSCR_ADDR_CH0_S)) -#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x3FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0 - -#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x0E8) -/* DMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH0_M ((DMA_OUT_EOF_DES_ADDR_CH0_V)<<(DMA_OUT_EOF_DES_ADDR_CH0_S)) -#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH0_S 0 - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x0EC) -/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 - -#define DMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x0F0) -/* DMA_OUTLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH0_M ((DMA_OUTLINK_DSCR_CH0_V)<<(DMA_OUTLINK_DSCR_CH0_S)) -#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH0_S 0 - -#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x0F4) -/* DMA_OUTLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH0_M ((DMA_OUTLINK_DSCR_BF0_CH0_V)<<(DMA_OUTLINK_DSCR_BF0_CH0_S)) -#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH0_S 0 - -#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x0F8) -/* DMA_OUTLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH0_M ((DMA_OUTLINK_DSCR_BF1_CH0_V)<<(DMA_OUTLINK_DSCR_BF1_CH0_S)) -#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH0_S 0 - -#define DMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x0FC) -/* DMA_TX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 0. The larger of the value the higher - of the priority.*/ -#define DMA_TX_PRI_CH0 0x0000000F -#define DMA_TX_PRI_CH0_M ((DMA_TX_PRI_CH0_V)<<(DMA_TX_PRI_CH0_S)) -#define DMA_TX_PRI_CH0_V 0xF -#define DMA_TX_PRI_CH0_S 0 - -#define DMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) -/* DMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 0. - 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ -#define DMA_PERI_OUT_SEL_CH0 0x0000003F -#define DMA_PERI_OUT_SEL_CH0_M ((DMA_PERI_OUT_SEL_CH0_V)<<(DMA_PERI_OUT_SEL_CH0_S)) -#define DMA_PERI_OUT_SEL_CH0_V 0x3F -#define DMA_PERI_OUT_SEL_CH0_S 0 - -#define DMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) -/* DMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define DMA_MEM_TRANS_EN_CH1 (BIT(4)) -#define DMA_MEM_TRANS_EN_CH1_M (BIT(4)) -#define DMA_MEM_TRANS_EN_CH1_V 0x1 -#define DMA_MEM_TRANS_EN_CH1_S 4 -/* DMA_IN_DATA_BURST_EN_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 1 receiving data when accessing internal SRAM.*/ -#define DMA_IN_DATA_BURST_EN_CH1 (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH1_M (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH1_V 0x1 -#define DMA_IN_DATA_BURST_EN_CH1_S 3 -/* DMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 1 reading link descriptor when accessing internal SRAM.*/ -#define DMA_INDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH1_M (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH1_V 0x1 -#define DMA_INDSCR_BURST_EN_CH1_S 2 -/* DMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_IN_LOOP_TEST_CH1 (BIT(1)) -#define DMA_IN_LOOP_TEST_CH1_M (BIT(1)) -#define DMA_IN_LOOP_TEST_CH1_V 0x1 -#define DMA_IN_LOOP_TEST_CH1_S 1 -/* DMA_IN_RST_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.*/ -#define DMA_IN_RST_CH1 (BIT(0)) -#define DMA_IN_RST_CH1_M (BIT(0)) -#define DMA_IN_RST_CH1_V 0x1 -#define DMA_IN_RST_CH1_S 0 - -#define DMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) -/* DMA_IN_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define DMA_IN_CHECK_OWNER_CH1 (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH1_M (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH1_V 0x1 -#define DMA_IN_CHECK_OWNER_CH1_S 12 - -#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) -/* DMA_IN_BUF_HUNGRY_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH1_M (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH1_V 0x1 -#define DMA_IN_BUF_HUNGRY_CH1_S 27 -/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH1_M (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH1_V 0x1 -#define DMA_IN_REMAIN_UNDER_4B_CH1_S 26 -/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH1_M (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH1_V 0x1 -#define DMA_IN_REMAIN_UNDER_3B_CH1_S 25 -/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH1_M (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH1_V 0x1 -#define DMA_IN_REMAIN_UNDER_2B_CH1_S 24 -/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH1_M (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH1_V 0x1 -#define DMA_IN_REMAIN_UNDER_1B_CH1_S 23 -/* DMA_INFIFO_CNT_CH1 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.*/ -#define DMA_INFIFO_CNT_CH1 0x0000003F -#define DMA_INFIFO_CNT_CH1_M ((DMA_INFIFO_CNT_CH1_V)<<(DMA_INFIFO_CNT_CH1_S)) -#define DMA_INFIFO_CNT_CH1_V 0x3F -#define DMA_INFIFO_CNT_CH1_S 2 -/* DMA_INFIFO_EMPTY_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 1.*/ -#define DMA_INFIFO_EMPTY_CH1 (BIT(1)) -#define DMA_INFIFO_EMPTY_CH1_M (BIT(1)) -#define DMA_INFIFO_EMPTY_CH1_V 0x1 -#define DMA_INFIFO_EMPTY_CH1_S 1 -/* DMA_INFIFO_FULL_CH1 : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 1.*/ -#define DMA_INFIFO_FULL_CH1 (BIT(0)) -#define DMA_INFIFO_FULL_CH1_M (BIT(0)) -#define DMA_INFIFO_FULL_CH1_V 0x1 -#define DMA_INFIFO_FULL_CH1_S 0 - -#define DMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13C) -/* DMA_INFIFO_POP_CH1 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define DMA_INFIFO_POP_CH1 (BIT(12)) -#define DMA_INFIFO_POP_CH1_M (BIT(12)) -#define DMA_INFIFO_POP_CH1_V 0x1 -#define DMA_INFIFO_POP_CH1_S 12 -/* DMA_INFIFO_RDATA_CH1 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define DMA_INFIFO_RDATA_CH1 0x00000FFF -#define DMA_INFIFO_RDATA_CH1_M ((DMA_INFIFO_RDATA_CH1_V)<<(DMA_INFIFO_RDATA_CH1_S)) -#define DMA_INFIFO_RDATA_CH1_V 0xFFF -#define DMA_INFIFO_RDATA_CH1_S 0 - -#define DMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) -/* DMA_INLINK_PARK_CH1 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define DMA_INLINK_PARK_CH1 (BIT(24)) -#define DMA_INLINK_PARK_CH1_M (BIT(24)) -#define DMA_INLINK_PARK_CH1_V 0x1 -#define DMA_INLINK_PARK_CH1_S 24 -/* DMA_INLINK_RESTART_CH1 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define DMA_INLINK_RESTART_CH1 (BIT(23)) -#define DMA_INLINK_RESTART_CH1_M (BIT(23)) -#define DMA_INLINK_RESTART_CH1_V 0x1 -#define DMA_INLINK_RESTART_CH1_S 23 -/* DMA_INLINK_START_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define DMA_INLINK_START_CH1 (BIT(22)) -#define DMA_INLINK_START_CH1_M (BIT(22)) -#define DMA_INLINK_START_CH1_V 0x1 -#define DMA_INLINK_START_CH1_S 22 -/* DMA_INLINK_STOP_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define DMA_INLINK_STOP_CH1 (BIT(21)) -#define DMA_INLINK_STOP_CH1_M (BIT(21)) -#define DMA_INLINK_STOP_CH1_V 0x1 -#define DMA_INLINK_STOP_CH1_S 21 -/* DMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define DMA_INLINK_AUTO_RET_CH1 (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH1_M (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH1_V 0x1 -#define DMA_INLINK_AUTO_RET_CH1_S 20 -/* DMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define DMA_INLINK_ADDR_CH1 0x000FFFFF -#define DMA_INLINK_ADDR_CH1_M ((DMA_INLINK_ADDR_CH1_V)<<(DMA_INLINK_ADDR_CH1_S)) -#define DMA_INLINK_ADDR_CH1_V 0xFFFFF -#define DMA_INLINK_ADDR_CH1_S 0 - -#define DMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) -/* DMA_IN_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_IN_STATE_CH1 0x00000007 -#define DMA_IN_STATE_CH1_M ((DMA_IN_STATE_CH1_V)<<(DMA_IN_STATE_CH1_S)) -#define DMA_IN_STATE_CH1_V 0x7 -#define DMA_IN_STATE_CH1_S 20 -/* DMA_IN_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_IN_DSCR_STATE_CH1 0x00000003 -#define DMA_IN_DSCR_STATE_CH1_M ((DMA_IN_DSCR_STATE_CH1_V)<<(DMA_IN_DSCR_STATE_CH1_S)) -#define DMA_IN_DSCR_STATE_CH1_V 0x3 -#define DMA_IN_DSCR_STATE_CH1_S 18 -/* DMA_INLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH1_M ((DMA_INLINK_DSCR_ADDR_CH1_V)<<(DMA_INLINK_DSCR_ADDR_CH1_S)) -#define DMA_INLINK_DSCR_ADDR_CH1_V 0x3FFFF -#define DMA_INLINK_DSCR_ADDR_CH1_S 0 - -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) -/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M ((DMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH1_S)) -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 - -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14C) -/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M ((DMA_IN_ERR_EOF_DES_ADDR_CH1_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH1_S)) -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 - -#define DMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) -/* DMA_INLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH1_M ((DMA_INLINK_DSCR_CH1_V)<<(DMA_INLINK_DSCR_CH1_S)) -#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH1_S 0 - -#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) -/* DMA_INLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH1_M ((DMA_INLINK_DSCR_BF0_CH1_V)<<(DMA_INLINK_DSCR_BF0_CH1_S)) -#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH1_S 0 - -#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) -/* DMA_INLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH1_M ((DMA_INLINK_DSCR_BF1_CH1_V)<<(DMA_INLINK_DSCR_BF1_CH1_S)) -#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH1_S 0 - -#define DMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15C) -/* DMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 1. The larger of the value the higher - of the priority.*/ -#define DMA_RX_PRI_CH1 0x0000000F -#define DMA_RX_PRI_CH1_M ((DMA_RX_PRI_CH1_V)<<(DMA_RX_PRI_CH1_S)) -#define DMA_RX_PRI_CH1_V 0xF -#define DMA_RX_PRI_CH1_S 0 - -#define DMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) -/* DMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 1. - 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ -#define DMA_PERI_IN_SEL_CH1 0x0000003F -#define DMA_PERI_IN_SEL_CH1_M ((DMA_PERI_IN_SEL_CH1_V)<<(DMA_PERI_IN_SEL_CH1_S)) -#define DMA_PERI_IN_SEL_CH1_V 0x3F -#define DMA_PERI_IN_SEL_CH1_S 0 - -#define DMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) -/* DMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 1 transmitting data when accessing internal SRAM.*/ -#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH1_M (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH1_V 0x1 -#define DMA_OUT_DATA_BURST_EN_CH1_S 5 -/* DMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 1 reading link descriptor when accessing internal SRAM.*/ -#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH1_M (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH1_V 0x1 -#define DMA_OUTDSCR_BURST_EN_CH1_S 4 -/* DMA_OUT_EOF_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define DMA_OUT_EOF_MODE_CH1 (BIT(3)) -#define DMA_OUT_EOF_MODE_CH1_M (BIT(3)) -#define DMA_OUT_EOF_MODE_CH1_V 0x1 -#define DMA_OUT_EOF_MODE_CH1_S 3 -/* DMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH1_M (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH1_V 0x1 -#define DMA_OUT_AUTO_WRBACK_CH1_S 2 -/* DMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_LOOP_TEST_CH1 (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH1_M (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH1_V 0x1 -#define DMA_OUT_LOOP_TEST_CH1_S 1 -/* DMA_OUT_RST_CH1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.*/ -#define DMA_OUT_RST_CH1 (BIT(0)) -#define DMA_OUT_RST_CH1_M (BIT(0)) -#define DMA_OUT_RST_CH1_V 0x1 -#define DMA_OUT_RST_CH1_S 0 - -#define DMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) -/* DMA_OUT_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH1_M (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH1_V 0x1 -#define DMA_OUT_CHECK_OWNER_CH1_S 12 - -#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) -/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH1_M (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x1 -#define DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 -/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH1_M (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x1 -#define DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 -/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH1_M (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x1 -#define DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 -/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH1_M (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x1 -#define DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 -/* DMA_OUTFIFO_CNT_CH1 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.*/ -#define DMA_OUTFIFO_CNT_CH1 0x0000003F -#define DMA_OUTFIFO_CNT_CH1_M ((DMA_OUTFIFO_CNT_CH1_V)<<(DMA_OUTFIFO_CNT_CH1_S)) -#define DMA_OUTFIFO_CNT_CH1_V 0x3F -#define DMA_OUTFIFO_CNT_CH1_S 2 -/* DMA_OUTFIFO_EMPTY_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 1.*/ -#define DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH1_M (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH1_V 0x1 -#define DMA_OUTFIFO_EMPTY_CH1_S 1 -/* DMA_OUTFIFO_FULL_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 1.*/ -#define DMA_OUTFIFO_FULL_CH1 (BIT(0)) -#define DMA_OUTFIFO_FULL_CH1_M (BIT(0)) -#define DMA_OUTFIFO_FULL_CH1_V 0x1 -#define DMA_OUTFIFO_FULL_CH1_S 0 - -#define DMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19C) -/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define DMA_OUTFIFO_PUSH_CH1 (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH1_M (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH1_V 0x1 -#define DMA_OUTFIFO_PUSH_CH1_S 9 -/* DMA_OUTFIFO_WDATA_CH1 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define DMA_OUTFIFO_WDATA_CH1 0x000001FF -#define DMA_OUTFIFO_WDATA_CH1_M ((DMA_OUTFIFO_WDATA_CH1_V)<<(DMA_OUTFIFO_WDATA_CH1_S)) -#define DMA_OUTFIFO_WDATA_CH1_V 0x1FF -#define DMA_OUTFIFO_WDATA_CH1_S 0 - -#define DMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1A0) -/* DMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define DMA_OUTLINK_PARK_CH1 (BIT(23)) -#define DMA_OUTLINK_PARK_CH1_M (BIT(23)) -#define DMA_OUTLINK_PARK_CH1_V 0x1 -#define DMA_OUTLINK_PARK_CH1_S 23 -/* DMA_OUTLINK_RESTART_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define DMA_OUTLINK_RESTART_CH1 (BIT(22)) -#define DMA_OUTLINK_RESTART_CH1_M (BIT(22)) -#define DMA_OUTLINK_RESTART_CH1_V 0x1 -#define DMA_OUTLINK_RESTART_CH1_S 22 -/* DMA_OUTLINK_START_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define DMA_OUTLINK_START_CH1 (BIT(21)) -#define DMA_OUTLINK_START_CH1_M (BIT(21)) -#define DMA_OUTLINK_START_CH1_V 0x1 -#define DMA_OUTLINK_START_CH1_S 21 -/* DMA_OUTLINK_STOP_CH1 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define DMA_OUTLINK_STOP_CH1 (BIT(20)) -#define DMA_OUTLINK_STOP_CH1_M (BIT(20)) -#define DMA_OUTLINK_STOP_CH1_V 0x1 -#define DMA_OUTLINK_STOP_CH1_S 20 -/* DMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH1_M ((DMA_OUTLINK_ADDR_CH1_V)<<(DMA_OUTLINK_ADDR_CH1_S)) -#define DMA_OUTLINK_ADDR_CH1_V 0xFFFFF -#define DMA_OUTLINK_ADDR_CH1_S 0 - -#define DMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1A4) -/* DMA_OUT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_STATE_CH1 0x00000007 -#define DMA_OUT_STATE_CH1_M ((DMA_OUT_STATE_CH1_V)<<(DMA_OUT_STATE_CH1_S)) -#define DMA_OUT_STATE_CH1_V 0x7 -#define DMA_OUT_STATE_CH1_S 20 -/* DMA_OUT_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_DSCR_STATE_CH1 0x00000003 -#define DMA_OUT_DSCR_STATE_CH1_M ((DMA_OUT_DSCR_STATE_CH1_V)<<(DMA_OUT_DSCR_STATE_CH1_S)) -#define DMA_OUT_DSCR_STATE_CH1_V 0x3 -#define DMA_OUT_DSCR_STATE_CH1_S 18 -/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH1_M ((DMA_OUTLINK_DSCR_ADDR_CH1_V)<<(DMA_OUTLINK_DSCR_ADDR_CH1_S)) -#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x3FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0 - -#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1A8) -/* DMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH1_M ((DMA_OUT_EOF_DES_ADDR_CH1_V)<<(DMA_OUT_EOF_DES_ADDR_CH1_S)) -#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH1_S 0 - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1AC) -/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 - -#define DMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1B0) -/* DMA_OUTLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH1_M ((DMA_OUTLINK_DSCR_CH1_V)<<(DMA_OUTLINK_DSCR_CH1_S)) -#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH1_S 0 - -#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1B4) -/* DMA_OUTLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH1_M ((DMA_OUTLINK_DSCR_BF0_CH1_V)<<(DMA_OUTLINK_DSCR_BF0_CH1_S)) -#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH1_S 0 - -#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1B8) -/* DMA_OUTLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH1_M ((DMA_OUTLINK_DSCR_BF1_CH1_V)<<(DMA_OUTLINK_DSCR_BF1_CH1_S)) -#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH1_S 0 - -#define DMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1BC) -/* DMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 1. The larger of the value the higher - of the priority.*/ -#define DMA_TX_PRI_CH1 0x0000000F -#define DMA_TX_PRI_CH1_M ((DMA_TX_PRI_CH1_V)<<(DMA_TX_PRI_CH1_S)) -#define DMA_TX_PRI_CH1_V 0xF -#define DMA_TX_PRI_CH1_S 0 - -#define DMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1C0) -/* DMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 1. - 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ -#define DMA_PERI_OUT_SEL_CH1 0x0000003F -#define DMA_PERI_OUT_SEL_CH1_M ((DMA_PERI_OUT_SEL_CH1_V)<<(DMA_PERI_OUT_SEL_CH1_S)) -#define DMA_PERI_OUT_SEL_CH1_V 0x3F -#define DMA_PERI_OUT_SEL_CH1_S 0 - -#define DMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1F0) -/* DMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory - to memory via DMA.*/ -#define DMA_MEM_TRANS_EN_CH2 (BIT(4)) -#define DMA_MEM_TRANS_EN_CH2_M (BIT(4)) -#define DMA_MEM_TRANS_EN_CH2_V 0x1 -#define DMA_MEM_TRANS_EN_CH2_S 4 -/* DMA_IN_DATA_BURST_EN_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 2 receiving data when accessing internal SRAM.*/ -#define DMA_IN_DATA_BURST_EN_CH2 (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH2_M (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH2_V 0x1 -#define DMA_IN_DATA_BURST_EN_CH2_S 3 -/* DMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel - 2 reading link descriptor when accessing internal SRAM.*/ -#define DMA_INDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH2_M (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH2_V 0x1 -#define DMA_INDSCR_BURST_EN_CH2_S 2 -/* DMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_IN_LOOP_TEST_CH2 (BIT(1)) -#define DMA_IN_LOOP_TEST_CH2_M (BIT(1)) -#define DMA_IN_LOOP_TEST_CH2_V 0x1 -#define DMA_IN_LOOP_TEST_CH2_S 1 -/* DMA_IN_RST_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.*/ -#define DMA_IN_RST_CH2 (BIT(0)) -#define DMA_IN_RST_CH2_M (BIT(0)) -#define DMA_IN_RST_CH2_V 0x1 -#define DMA_IN_RST_CH2_S 0 - -#define DMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1F4) -/* DMA_IN_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define DMA_IN_CHECK_OWNER_CH2 (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH2_M (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH2_V 0x1 -#define DMA_IN_CHECK_OWNER_CH2_S 12 - -#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1F8) -/* DMA_IN_BUF_HUNGRY_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH2_M (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH2_V 0x1 -#define DMA_IN_BUF_HUNGRY_CH2_S 27 -/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH2_M (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH2_V 0x1 -#define DMA_IN_REMAIN_UNDER_4B_CH2_S 26 -/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH2_M (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH2_V 0x1 -#define DMA_IN_REMAIN_UNDER_3B_CH2_S 25 -/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH2_M (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH2_V 0x1 -#define DMA_IN_REMAIN_UNDER_2B_CH2_S 24 -/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH2_M (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH2_V 0x1 -#define DMA_IN_REMAIN_UNDER_1B_CH2_S 23 -/* DMA_INFIFO_CNT_CH2 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ -/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.*/ -#define DMA_INFIFO_CNT_CH2 0x0000003F -#define DMA_INFIFO_CNT_CH2_M ((DMA_INFIFO_CNT_CH2_V)<<(DMA_INFIFO_CNT_CH2_S)) -#define DMA_INFIFO_CNT_CH2_V 0x3F -#define DMA_INFIFO_CNT_CH2_S 2 -/* DMA_INFIFO_EMPTY_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO empty signal for Rx channel 2.*/ -#define DMA_INFIFO_EMPTY_CH2 (BIT(1)) -#define DMA_INFIFO_EMPTY_CH2_M (BIT(1)) -#define DMA_INFIFO_EMPTY_CH2_V 0x1 -#define DMA_INFIFO_EMPTY_CH2_S 1 -/* DMA_INFIFO_FULL_CH2 : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: L1 Rx FIFO full signal for Rx channel 2.*/ -#define DMA_INFIFO_FULL_CH2 (BIT(0)) -#define DMA_INFIFO_FULL_CH2_M (BIT(0)) -#define DMA_INFIFO_FULL_CH2_V 0x1 -#define DMA_INFIFO_FULL_CH2_S 0 - -#define DMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1FC) -/* DMA_INFIFO_POP_CH2 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */ -/*description: Set this bit to pop data from DMA FIFO.*/ -#define DMA_INFIFO_POP_CH2 (BIT(12)) -#define DMA_INFIFO_POP_CH2_M (BIT(12)) -#define DMA_INFIFO_POP_CH2_V 0x1 -#define DMA_INFIFO_POP_CH2_S 12 -/* DMA_INFIFO_RDATA_CH2 : RO ;bitpos:[11:0] ;default: 12'h800 ; */ -/*description: This register stores the data popping from DMA FIFO.*/ -#define DMA_INFIFO_RDATA_CH2 0x00000FFF -#define DMA_INFIFO_RDATA_CH2_M ((DMA_INFIFO_RDATA_CH2_V)<<(DMA_INFIFO_RDATA_CH2_S)) -#define DMA_INFIFO_RDATA_CH2_V 0xFFF -#define DMA_INFIFO_RDATA_CH2_S 0 - -#define DMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) -/* DMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;default: 1'h1 ; */ -/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working.*/ -#define DMA_INLINK_PARK_CH2 (BIT(24)) -#define DMA_INLINK_PARK_CH2_M (BIT(24)) -#define DMA_INLINK_PARK_CH2_V 0x1 -#define DMA_INLINK_PARK_CH2_S 24 -/* DMA_INLINK_RESTART_CH2 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to mount a new inlink descriptor.*/ -#define DMA_INLINK_RESTART_CH2 (BIT(23)) -#define DMA_INLINK_RESTART_CH2_M (BIT(23)) -#define DMA_INLINK_RESTART_CH2_V 0x1 -#define DMA_INLINK_RESTART_CH2_S 23 -/* DMA_INLINK_START_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the inlink descriptors.*/ -#define DMA_INLINK_START_CH2 (BIT(22)) -#define DMA_INLINK_START_CH2_M (BIT(22)) -#define DMA_INLINK_START_CH2_V 0x1 -#define DMA_INLINK_START_CH2_S 22 -/* DMA_INLINK_STOP_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the inlink descriptors.*/ -#define DMA_INLINK_STOP_CH2 (BIT(21)) -#define DMA_INLINK_STOP_CH2_M (BIT(21)) -#define DMA_INLINK_STOP_CH2_V 0x1 -#define DMA_INLINK_STOP_CH2_S 21 -/* DMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data.*/ -#define DMA_INLINK_AUTO_RET_CH2 (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH2_M (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH2_V 0x1 -#define DMA_INLINK_AUTO_RET_CH2_S 20 -/* DMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - inlink descriptor's address.*/ -#define DMA_INLINK_ADDR_CH2 0x000FFFFF -#define DMA_INLINK_ADDR_CH2_M ((DMA_INLINK_ADDR_CH2_V)<<(DMA_INLINK_ADDR_CH2_S)) -#define DMA_INLINK_ADDR_CH2_V 0xFFFFF -#define DMA_INLINK_ADDR_CH2_S 0 - -#define DMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) -/* DMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_IN_STATE_CH2 0x00000007 -#define DMA_IN_STATE_CH2_M ((DMA_IN_STATE_CH2_V)<<(DMA_IN_STATE_CH2_S)) -#define DMA_IN_STATE_CH2_V 0x7 -#define DMA_IN_STATE_CH2_S 20 -/* DMA_IN_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_IN_DSCR_STATE_CH2 0x00000003 -#define DMA_IN_DSCR_STATE_CH2_M ((DMA_IN_DSCR_STATE_CH2_V)<<(DMA_IN_DSCR_STATE_CH2_S)) -#define DMA_IN_DSCR_STATE_CH2_V 0x3 -#define DMA_IN_DSCR_STATE_CH2_S 18 -/* DMA_INLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current inlink descriptor's address.*/ -#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH2_M ((DMA_INLINK_DSCR_ADDR_CH2_V)<<(DMA_INLINK_DSCR_ADDR_CH2_S)) -#define DMA_INLINK_DSCR_ADDR_CH2_V 0x3FFFF -#define DMA_INLINK_DSCR_ADDR_CH2_S 0 - -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) -/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M ((DMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH2_S)) -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20C) -/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ -#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M ((DMA_IN_ERR_EOF_DES_ADDR_CH2_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH2_S)) -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -#define DMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) -/* DMA_INLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current inlink descriptor x.*/ -#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH2_M ((DMA_INLINK_DSCR_CH2_V)<<(DMA_INLINK_DSCR_CH2_S)) -#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH2_S 0 - -#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) -/* DMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last inlink descriptor x-1.*/ -#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH2_M ((DMA_INLINK_DSCR_BF0_CH2_V)<<(DMA_INLINK_DSCR_BF0_CH2_S)) -#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH2_S 0 - -#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) -/* DMA_INLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH2_M ((DMA_INLINK_DSCR_BF1_CH2_V)<<(DMA_INLINK_DSCR_BF1_CH2_S)) -#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH2_S 0 - -#define DMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21C) -/* DMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 2. The larger of the value the higher - of the priority.*/ -#define DMA_RX_PRI_CH2 0x0000000F -#define DMA_RX_PRI_CH2_M ((DMA_RX_PRI_CH2_V)<<(DMA_RX_PRI_CH2_S)) -#define DMA_RX_PRI_CH2_V 0xF -#define DMA_RX_PRI_CH2_S 0 - -#define DMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) -/* DMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Rx channel 2. - 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ -#define DMA_PERI_IN_SEL_CH2 0x0000003F -#define DMA_PERI_IN_SEL_CH2_M ((DMA_PERI_IN_SEL_CH2_V)<<(DMA_PERI_IN_SEL_CH2_S)) -#define DMA_PERI_IN_SEL_CH2_V 0x3F -#define DMA_PERI_IN_SEL_CH2_S 0 - -#define DMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) -/* DMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 2 transmitting data when accessing internal SRAM.*/ -#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH2_M (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH2_V 0x1 -#define DMA_OUT_DATA_BURST_EN_CH2_S 5 -/* DMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel - 2 reading link descriptor when accessing internal SRAM.*/ -#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH2_M (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH2_V 0x1 -#define DMA_OUTDSCR_BURST_EN_CH2_S 4 -/* DMA_OUT_EOF_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA*/ -#define DMA_OUT_EOF_MODE_CH2 (BIT(3)) -#define DMA_OUT_EOF_MODE_CH2_M (BIT(3)) -#define DMA_OUT_EOF_MODE_CH2_V 0x1 -#define DMA_OUT_EOF_MODE_CH2_S 3 -/* DMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the - data in tx buffer has been transmitted.*/ -#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH2_M (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH2_V 0x1 -#define DMA_OUT_AUTO_WRBACK_CH2_S 2 -/* DMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_LOOP_TEST_CH2 (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH2_M (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH2_V 0x1 -#define DMA_OUT_LOOP_TEST_CH2_S 1 -/* DMA_OUT_RST_CH2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.*/ -#define DMA_OUT_RST_CH2 (BIT(0)) -#define DMA_OUT_RST_CH2_M (BIT(0)) -#define DMA_OUT_RST_CH2_V 0x1 -#define DMA_OUT_RST_CH2_S 0 - -#define DMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) -/* DMA_OUT_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ -#define DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH2_M (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH2_V 0x1 -#define DMA_OUT_CHECK_OWNER_CH2_S 12 - -#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) -/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH2_M (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x1 -#define DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 -/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH2_M (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x1 -#define DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 -/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH2_M (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x1 -#define DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 -/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: reserved*/ -#define DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH2_M (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x1 -#define DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 -/* DMA_OUTFIFO_CNT_CH2 : RO ;bitpos:[7:2] ;default: 6'b0 ; */ -/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.*/ -#define DMA_OUTFIFO_CNT_CH2 0x0000003F -#define DMA_OUTFIFO_CNT_CH2_M ((DMA_OUTFIFO_CNT_CH2_V)<<(DMA_OUTFIFO_CNT_CH2_S)) -#define DMA_OUTFIFO_CNT_CH2_V 0x3F -#define DMA_OUTFIFO_CNT_CH2_S 2 -/* DMA_OUTFIFO_EMPTY_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: L1 Tx FIFO empty signal for Tx channel 2.*/ -#define DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH2_M (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH2_V 0x1 -#define DMA_OUTFIFO_EMPTY_CH2_S 1 -/* DMA_OUTFIFO_FULL_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: L1 Tx FIFO full signal for Tx channel 2.*/ -#define DMA_OUTFIFO_FULL_CH2 (BIT(0)) -#define DMA_OUTFIFO_FULL_CH2_M (BIT(0)) -#define DMA_OUTFIFO_FULL_CH2_V 0x1 -#define DMA_OUTFIFO_FULL_CH2_S 0 - -#define DMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25C) -/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */ -/*description: Set this bit to push data into DMA FIFO.*/ -#define DMA_OUTFIFO_PUSH_CH2 (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH2_M (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH2_V 0x1 -#define DMA_OUTFIFO_PUSH_CH2_S 9 -/* DMA_OUTFIFO_WDATA_CH2 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: This register stores the data that need to be pushed into DMA FIFO.*/ -#define DMA_OUTFIFO_WDATA_CH2 0x000001FF -#define DMA_OUTFIFO_WDATA_CH2_M ((DMA_OUTFIFO_WDATA_CH2_V)<<(DMA_OUTFIFO_WDATA_CH2_S)) -#define DMA_OUTFIFO_WDATA_CH2_V 0x1FF -#define DMA_OUTFIFO_WDATA_CH2_S 0 - -#define DMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) -/* DMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working.*/ -#define DMA_OUTLINK_PARK_CH2 (BIT(23)) -#define DMA_OUTLINK_PARK_CH2_M (BIT(23)) -#define DMA_OUTLINK_PARK_CH2_V 0x1 -#define DMA_OUTLINK_PARK_CH2_S 23 -/* DMA_OUTLINK_RESTART_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to restart a new outlink from the last address.*/ -#define DMA_OUTLINK_RESTART_CH2 (BIT(22)) -#define DMA_OUTLINK_RESTART_CH2_M (BIT(22)) -#define DMA_OUTLINK_RESTART_CH2_V 0x1 -#define DMA_OUTLINK_RESTART_CH2_S 22 -/* DMA_OUTLINK_START_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to start dealing with the outlink descriptors.*/ -#define DMA_OUTLINK_START_CH2 (BIT(21)) -#define DMA_OUTLINK_START_CH2_M (BIT(21)) -#define DMA_OUTLINK_START_CH2_V 0x1 -#define DMA_OUTLINK_START_CH2_S 21 -/* DMA_OUTLINK_STOP_CH2 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to stop dealing with the outlink descriptors.*/ -#define DMA_OUTLINK_STOP_CH2 (BIT(20)) -#define DMA_OUTLINK_STOP_CH2_M (BIT(20)) -#define DMA_OUTLINK_STOP_CH2_V 0x1 -#define DMA_OUTLINK_STOP_CH2_S 20 -/* DMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first - outlink descriptor's address.*/ -#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH2_M ((DMA_OUTLINK_ADDR_CH2_V)<<(DMA_OUTLINK_ADDR_CH2_S)) -#define DMA_OUTLINK_ADDR_CH2_V 0xFFFFF -#define DMA_OUTLINK_ADDR_CH2_S 0 - -#define DMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) -/* DMA_OUT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_STATE_CH2 0x00000007 -#define DMA_OUT_STATE_CH2_M ((DMA_OUT_STATE_CH2_V)<<(DMA_OUT_STATE_CH2_S)) -#define DMA_OUT_STATE_CH2_V 0x7 -#define DMA_OUT_STATE_CH2_S 20 -/* DMA_OUT_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: reserved*/ -#define DMA_OUT_DSCR_STATE_CH2 0x00000003 -#define DMA_OUT_DSCR_STATE_CH2_M ((DMA_OUT_DSCR_STATE_CH2_V)<<(DMA_OUT_DSCR_STATE_CH2_S)) -#define DMA_OUT_DSCR_STATE_CH2_V 0x3 -#define DMA_OUT_DSCR_STATE_CH2_S 18 -/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: This register stores the current outlink descriptor's address.*/ -#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH2_M ((DMA_OUTLINK_DSCR_ADDR_CH2_V)<<(DMA_OUTLINK_DSCR_ADDR_CH2_S)) -#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x3FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0 - -#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) -/* DMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1.*/ -#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH2_M ((DMA_OUT_EOF_DES_ADDR_CH2_V)<<(DMA_OUT_EOF_DES_ADDR_CH2_S)) -#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH2_S 0 - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26C) -/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before - the last outlink descriptor.*/ -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH2_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 - -#define DMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) -/* DMA_OUTLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the current outlink descriptor y.*/ -#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH2_M ((DMA_OUTLINK_DSCR_CH2_V)<<(DMA_OUTLINK_DSCR_CH2_S)) -#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH2_S 0 - -#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) -/* DMA_OUTLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the last outlink descriptor y-1.*/ -#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH2_M ((DMA_OUTLINK_DSCR_BF0_CH2_V)<<(DMA_OUTLINK_DSCR_BF0_CH2_S)) -#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH2_S 0 - -#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) -/* DMA_OUTLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of the second-to-last inlink descriptor x-2.*/ -#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH2_M ((DMA_OUTLINK_DSCR_BF1_CH2_V)<<(DMA_OUTLINK_DSCR_BF1_CH2_S)) -#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH2_S 0 - -#define DMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27C) -/* DMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 2. The larger of the value the higher - of the priority.*/ -#define DMA_TX_PRI_CH2 0x0000000F -#define DMA_TX_PRI_CH2_M ((DMA_TX_PRI_CH2_V)<<(DMA_TX_PRI_CH2_S)) -#define DMA_TX_PRI_CH2_V 0xF -#define DMA_TX_PRI_CH2_S 0 - -#define DMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) -/* DMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ -/*description: This register is used to select peripheral for Tx channel 2. - 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ -#define DMA_PERI_OUT_SEL_CH2 0x0000003F -#define DMA_PERI_OUT_SEL_CH2_M ((DMA_PERI_OUT_SEL_CH2_V)<<(DMA_PERI_OUT_SEL_CH2_S)) -#define DMA_PERI_OUT_SEL_CH2_V 0x3F -#define DMA_PERI_OUT_SEL_CH2_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_DMA_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/gdma_struct.h b/components/soc/esp32h4/include/soc/gdma_struct.h deleted file mode 100644 index f9f102beb4..0000000000 --- a/components/soc/esp32h4/include/soc/gdma_struct.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct gdma_dev_s { - struct { - union { - struct { - uint32_t in_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ - uint32_t in_suc_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ - uint32_t in_err_eof: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ - uint32_t out_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ - uint32_t out_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ - uint32_t in_dscr_err: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ - uint32_t out_dscr_err: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ - uint32_t in_dscr_empty: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ - uint32_t out_total_eof: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ - uint32_t infifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/ - uint32_t infifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/ - uint32_t outfifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/ - uint32_t outfifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } raw; - union { - struct { - uint32_t in_done: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t out_done: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t out_total_eof: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t infifo_ovf: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } st; - union { - struct { - uint32_t in_done: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t out_done: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_dscr_err: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t out_total_eof: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t infifo_ovf: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } ena; - union { - struct { - uint32_t in_done: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t out_done: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_dscr_err: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t out_total_eof: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t infifo_ovf: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } clr; - } intr[3]; - uint32_t reserved_30; - uint32_t reserved_34; - uint32_t reserved_38; - uint32_t reserved_3c; - union { - struct { - uint32_t ahb_testmode: 3; /*reserved*/ - uint32_t reserved3: 1; /*reserved*/ - uint32_t ahb_testaddr: 2; /*reserved*/ - uint32_t reserved6: 26; /*reserved*/ - }; - uint32_t val; - } ahb_test; - union { - struct { - uint32_t ahbm_rst_inter: 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/ - uint32_t reserved1: 1; - uint32_t arb_pri_dis: 1; /*Set this bit to disable priority arbitration function.*/ - uint32_t clk_en: 1; - uint32_t reserved4: 28; - }; - uint32_t val; - } misc_conf; - uint32_t date; /**/ - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - struct { - struct { - union { - struct { - uint32_t in_rst: 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ - uint32_t in_loop_test: 1; /*reserved*/ - uint32_t indscr_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/ - uint32_t in_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/ - uint32_t mem_trans_en: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ - uint32_t reserved5: 27; /*reserved*/ - }; - uint32_t val; - } in_conf0; - union { - struct { - uint32_t reserved0: 12; - uint32_t in_check_owner: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } in_conf1; - union { - struct { - uint32_t infifo_full: 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty: 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_cnt: 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ - uint32_t reserved8: 15; /*reserved*/ - uint32_t in_remain_under_1b: 1; /*reserved*/ - uint32_t in_remain_under_2b: 1; /*reserved*/ - uint32_t in_remain_under_3b: 1; /*reserved*/ - uint32_t in_remain_under_4b: 1; /*reserved*/ - uint32_t in_buf_hungry: 1; /*reserved*/ - uint32_t reserved28: 4; /*reserved*/ - }; - uint32_t val; - } infifo_status; - union { - struct { - uint32_t infifo_rdata: 12; /*This register stores the data popping from DMA FIFO.*/ - uint32_t infifo_pop: 1; /*Set this bit to pop data from DMA FIFO.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } in_pop; - union { - struct { - uint32_t addr: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ - uint32_t auto_ret: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ - uint32_t stop: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ - uint32_t start: 1; /*Set this bit to start dealing with the inlink descriptors.*/ - uint32_t restart: 1; /*Set this bit to mount a new inlink descriptor.*/ - uint32_t park: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } in_link; - union { - struct { - uint32_t inlink_dscr_addr: 18; /*This register stores the current inlink descriptor's address.*/ - uint32_t in_dscr_state: 2; /*reserved*/ - uint32_t in_state: 3; /*reserved*/ - uint32_t reserved23: 9; /*reserved*/ - }; - uint32_t val; - } in_state; - uint32_t in_suc_eof_des_addr; /**/ - uint32_t in_err_eof_des_addr; /**/ - uint32_t in_dscr; /**/ - uint32_t in_dscr_bf0; /**/ - uint32_t in_dscr_bf1; /**/ - union { - struct { - uint32_t rx_pri: 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/ - uint32_t reserved4: 28; - }; - uint32_t val; - } in_pri; - union { - struct { - uint32_t sel: 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ - uint32_t reserved6: 26; - }; - uint32_t val; - } in_peri_sel; - } in; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - struct { - union { - struct { - uint32_t out_rst: 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ - uint32_t out_loop_test: 1; /*reserved*/ - uint32_t out_auto_wrback: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ - uint32_t out_eof_mode: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ - uint32_t outdscr_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/ - uint32_t out_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/ - uint32_t reserved6: 26; - }; - uint32_t val; - } out_conf0; - union { - struct { - uint32_t reserved0: 12; - uint32_t out_check_owner: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ - uint32_t reserved13: 19; /*reserved*/ - }; - uint32_t val; - } out_conf1; - union { - struct { - uint32_t outfifo_full: 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty: 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_cnt: 6; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ - uint32_t reserved8: 15; /*reserved*/ - uint32_t out_remain_under_1b: 1; /*reserved*/ - uint32_t out_remain_under_2b: 1; /*reserved*/ - uint32_t out_remain_under_3b: 1; /*reserved*/ - uint32_t out_remain_under_4b: 1; /*reserved*/ - uint32_t reserved27: 5; /*reserved*/ - }; - uint32_t val; - } outfifo_status; - union { - struct { - uint32_t outfifo_wdata: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ - uint32_t outfifo_push: 1; /*Set this bit to push data into DMA FIFO.*/ - uint32_t reserved10: 22; /*reserved*/ - }; - uint32_t val; - } out_push; - union { - struct { - uint32_t addr: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ - uint32_t stop: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ - uint32_t start: 1; /*Set this bit to start dealing with the outlink descriptors.*/ - uint32_t restart: 1; /*Set this bit to restart a new outlink from the last address.*/ - uint32_t park: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } out_link; - union { - struct { - uint32_t outlink_dscr_addr: 18; /*This register stores the current outlink descriptor's address.*/ - uint32_t out_dscr_state: 2; /*reserved*/ - uint32_t out_state: 3; /*reserved*/ - uint32_t reserved23: 9; /*reserved*/ - }; - uint32_t val; - } out_state; - uint32_t out_eof_des_addr; /**/ - uint32_t out_eof_bfr_des_addr; /**/ - uint32_t out_dscr; /**/ - uint32_t out_dscr_bf0; /**/ - uint32_t out_dscr_bf1; /**/ - union { - struct { - uint32_t tx_pri: 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/ - uint32_t reserved4: 28; - }; - uint32_t val; - } out_pri; - union { - struct { - uint32_t sel: 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/ - uint32_t reserved6: 26; - }; - uint32_t val; - } out_peri_sel; - } out; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - } channel[3]; -} gdma_dev_t; - -extern gdma_dev_t GDMA; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/gpio_pins.h b/components/soc/esp32h4/include/soc/gpio_pins.h deleted file mode 100644 index ffb8ad836a..0000000000 --- a/components/soc/esp32h4/include/soc/gpio_pins.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -#include "sdkconfig.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) -#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E) -#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F) -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/gpio_sd_struct.h b/components/soc/esp32h4/include/soc/gpio_sd_struct.h deleted file mode 100644 index 59fb95f13f..0000000000 --- a/components/soc/esp32h4/include/soc/gpio_sd_struct.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct gpio_sd_dev_t { - volatile union { - struct { - uint32_t duty: 8; - uint32_t prescale: 8; - uint32_t reserved16: 16; - }; - uint32_t val; - } channel[4]; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - uint32_t reserved_1c; - volatile union { - struct { - uint32_t reserved0: 31; - uint32_t clk_en: 1; - }; - uint32_t val; - } cg; - volatile union { - struct { - uint32_t reserved0: 30; - uint32_t function_clk_en: 1; - uint32_t spi_swap: 1; - }; - uint32_t val; - } misc; - volatile union { - struct { - uint32_t date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } version; -} gpio_sd_dev_t; - -extern gpio_sd_dev_t SDM; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/hwcrypto_reg.h b/components/soc/esp32h4/include/soc/hwcrypto_reg.h deleted file mode 100644 index 0e4ceb3000..0000000000 --- a/components/soc/esp32h4/include/soc/hwcrypto_reg.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __HWCRYPTO_REG_H__ -#define __HWCRYPTO_REG_H__ - -#include "soc.h" - -/* registers for RSA acceleration via Multiple Precision Integer ops */ -#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) -/* RB & Z use the same memory block, depending on phase of operation */ -#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) -#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) -#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400) -#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600) - -/* Configuration registers */ -#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800) -#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804) -#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) -#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) -#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) - -/* Initialization registers */ -#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) - -/* Calculation start registers */ -#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) -#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810) -#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) - -/* Interrupt registers */ -#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818) -#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C) -#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) -#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x82C) - -#define SHA_MODE_SHA1 0 -#define SHA_MODE_SHA224 1 -#define SHA_MODE_SHA256 2 - -/* SHA acceleration registers */ -#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00) -#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C) -#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10) -#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14) -#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18) -#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C) -#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20) -#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24) -#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28) -#define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C) - -#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40) -#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80) - -/* AES Block operation modes */ -#define AES_BLOCK_MODE_ECB 0 -#define AES_BLOCK_MODE_CBC 1 -#define AES_BLOCK_MODE_OFB 2 -#define AES_BLOCK_MODE_CTR 3 -#define AES_BLOCK_MODE_CFB8 4 -#define AES_BLOCK_MODE_CFB128 5 - -/* AES Block operation modes (used with DMA) */ -#define AES_BLOCK_MODE_ECB 0 -#define AES_BLOCK_MODE_CBC 1 -#define AES_BLOCK_MODE_OFB 2 -#define AES_BLOCK_MODE_CTR 3 -#define AES_BLOCK_MODE_CFB8 4 -#define AES_BLOCK_MODE_CFB128 5 - -/* AES acceleration registers */ -#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40) -#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44) -#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48) -#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c) -#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) -#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) -#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) -#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) -#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) -#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) -#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) -#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) -#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) -#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) -#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) - -#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) -#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) -#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) -#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) -#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) -#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) -#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) - -#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00) -#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20) -#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) -#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) -#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60) -#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) -#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) - -/* AES_STATE_REG values */ -#define AES_STATE_IDLE 0 -#define AES_STATE_BUSY 1 -#define AES_STATE_DONE 2 - -/* HMAC Module */ -#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) -#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44) -#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48) -#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c) -#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50) -#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54) -#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58) -#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c) -#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60) -#define HMAC_INVALIDATE_JTAG BIT(0) -#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64) -#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68) -#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c) - -#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80) -#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0) -#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0) -#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4) - -#define HMAC_SOFT_JTAG_CTRL_REG ((DR_REG_HMAC_BASE) + 0xF8) -#define HMAC_WR_JTAG_REG ((DR_REG_HMAC_BASE) + 0xFC) - -#define HMAC_DATE_REG ((DR_REG_HMAC_BASE) + 0xF8) - - -/* AES-XTS registers */ -#define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00) -#define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40) -#define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44) -#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48) - -#define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C) -#define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50) -#define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54) -#define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58) -#define AES_XTS_DATE_REG ((DR_REG_AES_XTS_BASE) + 0x5C) - -/* Digital Signature registers and memory blocks */ -#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) -#define DS_C_Y_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) -#define DS_C_M_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 ) -#define DS_C_RB_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 ) -#define DS_C_BOX_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 ) -#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 ) -#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 ) -#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 ) - -#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00) -#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04) -#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08) - -#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C) -#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10) -#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14) - -#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0) -#define DS_QUERY_CHECK_INVALID_PADDING (1<<1) - -#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20) - -#endif diff --git a/components/soc/esp32h4/include/soc/i2c_reg.h b/components/soc/esp32h4/include/soc/i2c_reg.h deleted file mode 100644 index 1c9fff1db8..0000000000 --- a/components/soc/esp32h4/include/soc/i2c_reg.h +++ /dev/null @@ -1,1054 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_I2C_REG_H_ -#define _SOC_I2C_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) -/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: .*/ -#define I2C_SCL_LOW_PERIOD 0x000001FF -#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) -#define I2C_SCL_LOW_PERIOD_V 0x1FF -#define I2C_SCL_LOW_PERIOD_S 0 - -#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) -/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ADDR_BROADCASTING_EN (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_V 0x1 -#define I2C_ADDR_BROADCASTING_EN_S 14 -/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 -#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 -/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_V 0x1 -#define I2C_SLV_TX_AUTO_START_EN_S 12 -/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (BIT(11)) -#define I2C_CONF_UPGATE_V 0x1 -#define I2C_CONF_UPGATE_S 11 -/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (BIT(10)) -#define I2C_FSM_RST_V 0x1 -#define I2C_FSM_RST_S 10 -/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (BIT(9)) -#define I2C_ARBITRATION_EN_V 0x1 -#define I2C_ARBITRATION_EN_S 9 -/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (BIT(8)) -#define I2C_CLK_EN_V 0x1 -#define I2C_CLK_EN_S 8 -/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: .*/ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (BIT(7)) -#define I2C_RX_LSB_FIRST_V 0x1 -#define I2C_RX_LSB_FIRST_S 7 -/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (BIT(6)) -#define I2C_TX_LSB_FIRST_V 0x1 -#define I2C_TX_LSB_FIRST_S 6 -/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (BIT(5)) -#define I2C_TRANS_START_V 0x1 -#define I2C_TRANS_START_S 5 -/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_MS_MODE (BIT(4)) -#define I2C_MS_MODE_M (BIT(4)) -#define I2C_MS_MODE_V 0x1 -#define I2C_MS_MODE_S 4 -/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_V 0x1 -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_V 0x1 -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (BIT(1)) -#define I2C_SCL_FORCE_OUT_V 0x1 -#define I2C_SCL_FORCE_OUT_S 1 -/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (BIT(0)) -#define I2C_SDA_FORCE_OUT_V 0x1 -#define I2C_SDA_FORCE_OUT_S 0 - -#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) -/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: .*/ -#define I2C_SCL_STATE_LAST 0x00000007 -#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) -#define I2C_SCL_STATE_LAST_V 0x7 -#define I2C_SCL_STATE_LAST_S 28 -/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: .*/ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) -#define I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_CNT 0x0000003F -#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) -#define I2C_TXFIFO_CNT_V 0x3F -#define I2C_TXFIFO_CNT_S 18 -/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ -/*description: .*/ -#define I2C_STRETCH_CAUSE 0x00000003 -#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) -#define I2C_STRETCH_CAUSE_V 0x3 -#define I2C_STRETCH_CAUSE_S 14 -/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_CNT 0x0000003F -#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) -#define I2C_RXFIFO_CNT_V 0x3F -#define I2C_RXFIFO_CNT_S 8 -/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_ADDRESSED (BIT(5)) -#define I2C_SLAVE_ADDRESSED_M (BIT(5)) -#define I2C_SLAVE_ADDRESSED_V 0x1 -#define I2C_SLAVE_ADDRESSED_S 5 -/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (BIT(4)) -#define I2C_BUS_BUSY_V 0x1 -#define I2C_BUS_BUSY_S 4 -/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (BIT(3)) -#define I2C_ARB_LOST_V 0x1 -#define I2C_ARB_LOST_S 3 -/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_RW (BIT(1)) -#define I2C_SLAVE_RW_M (BIT(1)) -#define I2C_SLAVE_RW_V 0x1 -#define I2C_SLAVE_RW_S 1 -/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (BIT(0)) -#define I2C_RESP_REC_V 0x1 -#define I2C_RESP_REC_S 0 - -#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) -/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (BIT(5)) -#define I2C_TIME_OUT_EN_V 0x1 -#define I2C_TIME_OUT_EN_S 5 -/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ -/*description: .*/ -#define I2C_TIME_OUT_REG 0x0000001F -#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S)) -#define I2C_TIME_OUT_REG_V 0x1F -#define I2C_TIME_OUT_REG_S 0 - -#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) -/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ADDR_10BIT_EN (BIT(31)) -#define I2C_ADDR_10BIT_EN_M (BIT(31)) -#define I2C_ADDR_10BIT_EN_V 0x1 -#define I2C_ADDR_10BIT_EN_S 31 -/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_ADDR 0x00007FFF -#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) -#define I2C_SLAVE_ADDR_V 0x7FFF -#define I2C_SLAVE_ADDR_S 0 - -#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) -/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_RW_POINT 0x000000FF -#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) -#define I2C_SLAVE_RW_POINT_V 0xFF -#define I2C_SLAVE_RW_POINT_S 22 -/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_WADDR 0x0000001F -#define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) -#define I2C_TXFIFO_WADDR_V 0x1F -#define I2C_TXFIFO_WADDR_S 15 -/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_RADDR 0x0000001F -#define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) -#define I2C_TXFIFO_RADDR_V 0x1F -#define I2C_TXFIFO_RADDR_S 10 -/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_WADDR 0x0000001F -#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) -#define I2C_RXFIFO_WADDR_V 0x1F -#define I2C_RXFIFO_WADDR_S 5 -/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_RADDR 0x0000001F -#define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) -#define I2C_RXFIFO_RADDR_V 0x1F -#define I2C_RXFIFO_RADDR_S 0 - -#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) -/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (BIT(14)) -#define I2C_FIFO_PRT_EN_V 0x1 -#define I2C_FIFO_PRT_EN_S 14 -/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (BIT(13)) -#define I2C_TX_FIFO_RST_V 0x1 -#define I2C_TX_FIFO_RST_S 13 -/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (BIT(12)) -#define I2C_RX_FIFO_RST_V 0x1 -#define I2C_RX_FIFO_RST_S 12 -/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_V 0x1 -#define I2C_FIFO_ADDR_CFG_EN_S 11 -/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (BIT(10)) -#define I2C_NONFIFO_EN_V 0x1 -#define I2C_NONFIFO_EN_S 10 -/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ -/*description: .*/ -#define I2C_TXFIFO_WM_THRHD 0x0000001F -#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) -#define I2C_TXFIFO_WM_THRHD_V 0x1F -#define I2C_TXFIFO_WM_THRHD_S 5 -/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ -/*description: .*/ -#define I2C_RXFIFO_WM_THRHD 0x0000001F -#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) -#define I2C_RXFIFO_WM_THRHD_V 0x1F -#define I2C_RXFIFO_WM_THRHD_S 0 - -#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) -/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: .*/ -#define I2C_FIFO_RDATA 0x000000FF -#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) -#define I2C_FIFO_RDATA_V 0xFF -#define I2C_FIFO_RDATA_S 0 - -#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) -/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_V 0x1 -#define I2C_GENERAL_CALL_INT_RAW_S 17 -/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 -#define I2C_SLAVE_STRETCH_INT_RAW_S 16 -/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (BIT(15)) -#define I2C_DET_START_INT_RAW_V 0x1 -#define I2C_DET_START_INT_RAW_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_V 0x1 -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (BIT(10)) -#define I2C_NACK_INT_RAW_V 0x1 -#define I2C_NACK_INT_RAW_S 10 -/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (BIT(9)) -#define I2C_TRANS_START_INT_RAW_V 0x1 -#define I2C_TRANS_START_INT_RAW_S 9 -/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_V 0x1 -#define I2C_TIME_OUT_INT_RAW_S 8 -/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (BIT(3)) -#define I2C_END_DETECT_INT_RAW_V 0x1 -#define I2C_END_DETECT_INT_RAW_S 3 -/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_V 0x1 -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_V 0x1 -#define I2C_RXFIFO_WM_INT_RAW_S 0 - -#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) -/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_V 0x1 -#define I2C_GENERAL_CALL_INT_CLR_S 17 -/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 -#define I2C_SLAVE_STRETCH_INT_CLR_S 16 -/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (BIT(15)) -#define I2C_DET_START_INT_CLR_V 0x1 -#define I2C_DET_START_INT_CLR_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_V 0x1 -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (BIT(10)) -#define I2C_NACK_INT_CLR_V 0x1 -#define I2C_NACK_INT_CLR_S 10 -/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (BIT(9)) -#define I2C_TRANS_START_INT_CLR_V 0x1 -#define I2C_TRANS_START_INT_CLR_S 9 -/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_V 0x1 -#define I2C_TIME_OUT_INT_CLR_S 8 -/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (BIT(3)) -#define I2C_END_DETECT_INT_CLR_V 0x1 -#define I2C_END_DETECT_INT_CLR_S 3 -/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_V 0x1 -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_V 0x1 -#define I2C_RXFIFO_WM_INT_CLR_S 0 - -#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) -/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_V 0x1 -#define I2C_GENERAL_CALL_INT_ENA_S 17 -/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 -#define I2C_SLAVE_STRETCH_INT_ENA_S 16 -/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (BIT(15)) -#define I2C_DET_START_INT_ENA_V 0x1 -#define I2C_DET_START_INT_ENA_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_V 0x1 -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (BIT(10)) -#define I2C_NACK_INT_ENA_V 0x1 -#define I2C_NACK_INT_ENA_S 10 -/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (BIT(9)) -#define I2C_TRANS_START_INT_ENA_V 0x1 -#define I2C_TRANS_START_INT_ENA_S 9 -/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_V 0x1 -#define I2C_TIME_OUT_INT_ENA_S 8 -/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (BIT(3)) -#define I2C_END_DETECT_INT_ENA_V 0x1 -#define I2C_END_DETECT_INT_ENA_S 3 -/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_V 0x1 -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_V 0x1 -#define I2C_RXFIFO_WM_INT_ENA_S 0 - -#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) -/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_GENERAL_CALL_INT_ST (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_V 0x1 -#define I2C_GENERAL_CALL_INT_ST_S 17 -/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 -#define I2C_SLAVE_STRETCH_INT_ST_S 16 -/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (BIT(15)) -#define I2C_DET_START_INT_ST_V 0x1 -#define I2C_DET_START_INT_ST_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_V 0x1 -#define I2C_SCL_ST_TO_INT_ST_S 13 -/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_V 0x1 -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_V 0x1 -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (BIT(10)) -#define I2C_NACK_INT_ST_V 0x1 -#define I2C_NACK_INT_ST_S 10 -/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (BIT(9)) -#define I2C_TRANS_START_INT_ST_V 0x1 -#define I2C_TRANS_START_INT_ST_S 9 -/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (BIT(8)) -#define I2C_TIME_OUT_INT_ST_V 0x1 -#define I2C_TIME_OUT_INT_ST_S 8 -/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (BIT(3)) -#define I2C_END_DETECT_INT_ST_V 0x1 -#define I2C_END_DETECT_INT_ST_S 3 -/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_V 0x1 -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_V 0x1 -#define I2C_TXFIFO_WM_INT_ST_S 1 -/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_V 0x1 -#define I2C_RXFIFO_WM_INT_ST_S 0 - -#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) -/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: .*/ -#define I2C_SDA_HOLD_TIME 0x000001FF -#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) -#define I2C_SDA_HOLD_TIME_V 0x1FF -#define I2C_SDA_HOLD_TIME_S 0 - -#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) -/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: .*/ -#define I2C_SDA_SAMPLE_TIME 0x000001FF -#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) -#define I2C_SDA_SAMPLE_TIME_V 0x1FF -#define I2C_SDA_SAMPLE_TIME_S 0 - -#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) -/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ -/*description: .*/ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F -#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 -/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: .*/ -#define I2C_SCL_HIGH_PERIOD 0x000001FF -#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) -#define I2C_SCL_HIGH_PERIOD_V 0x1FF -#define I2C_SCL_HIGH_PERIOD_S 0 - -#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) -/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: .*/ -#define I2C_SCL_START_HOLD_TIME 0x000001FF -#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) -#define I2C_SCL_START_HOLD_TIME_V 0x1FF -#define I2C_SCL_START_HOLD_TIME_S 0 - -#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) -/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: .*/ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF -#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF -#define I2C_SCL_RSTART_SETUP_TIME_S 0 - -#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) -/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: .*/ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FF -#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) -#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF -#define I2C_SCL_STOP_HOLD_TIME_S 0 - -#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) -/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: .*/ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FF -#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) -#define I2C_SCL_STOP_SETUP_TIME_V 0x1FF -#define I2C_SCL_STOP_SETUP_TIME_S 0 - -#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) -/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (BIT(9)) -#define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 9 -/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (BIT(8)) -#define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 8 -/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: .*/ -#define I2C_SDA_FILTER_THRES 0x0000000F -#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) -#define I2C_SDA_FILTER_THRES_V 0xF -#define I2C_SDA_FILTER_THRES_S 4 -/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: .*/ -#define I2C_SCL_FILTER_THRES 0x0000000F -#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) -#define I2C_SCL_FILTER_THRES_V 0xF -#define I2C_SCL_FILTER_THRES_S 0 - -#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) -/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: .*/ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (BIT(21)) -#define I2C_SCLK_ACTIVE_V 0x1 -#define I2C_SCLK_ACTIVE_S 21 -/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (BIT(20)) -#define I2C_SCLK_SEL_V 0x1 -#define I2C_SCLK_SEL_S 20 -/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ -/*description: .*/ -#define I2C_SCLK_DIV_B 0x0000003F -#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) -#define I2C_SCLK_DIV_B_V 0x3F -#define I2C_SCLK_DIV_B_S 14 -/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: .*/ -#define I2C_SCLK_DIV_A 0x0000003F -#define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) -#define I2C_SCLK_DIV_A_V 0x3F -#define I2C_SCLK_DIV_A_S 8 -/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: .*/ -#define I2C_SCLK_DIV_NUM 0x000000FF -#define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) -#define I2C_SCLK_DIV_NUM_V 0xFF -#define I2C_SCLK_DIV_NUM_S 0 - -#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) -/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (BIT(31)) -#define I2C_COMMAND0_DONE_V 0x1 -#define I2C_COMMAND0_DONE_S 31 -/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND0 0x00003FFF -#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) -#define I2C_COMMAND0_V 0x3FFF -#define I2C_COMMAND0_S 0 - -#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) -/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (BIT(31)) -#define I2C_COMMAND1_DONE_V 0x1 -#define I2C_COMMAND1_DONE_S 31 -/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND1 0x00003FFF -#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) -#define I2C_COMMAND1_V 0x3FFF -#define I2C_COMMAND1_S 0 - -#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) -/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (BIT(31)) -#define I2C_COMMAND2_DONE_V 0x1 -#define I2C_COMMAND2_DONE_S 31 -/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND2 0x00003FFF -#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) -#define I2C_COMMAND2_V 0x3FFF -#define I2C_COMMAND2_S 0 - -#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) -/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (BIT(31)) -#define I2C_COMMAND3_DONE_V 0x1 -#define I2C_COMMAND3_DONE_S 31 -/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND3 0x00003FFF -#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) -#define I2C_COMMAND3_V 0x3FFF -#define I2C_COMMAND3_S 0 - -#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) -/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (BIT(31)) -#define I2C_COMMAND4_DONE_V 0x1 -#define I2C_COMMAND4_DONE_S 31 -/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND4 0x00003FFF -#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) -#define I2C_COMMAND4_V 0x3FFF -#define I2C_COMMAND4_S 0 - -#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) -/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (BIT(31)) -#define I2C_COMMAND5_DONE_V 0x1 -#define I2C_COMMAND5_DONE_S 31 -/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND5 0x00003FFF -#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) -#define I2C_COMMAND5_V 0x3FFF -#define I2C_COMMAND5_S 0 - -#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) -/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (BIT(31)) -#define I2C_COMMAND6_DONE_V 0x1 -#define I2C_COMMAND6_DONE_S 31 -/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND6 0x00003FFF -#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) -#define I2C_COMMAND6_V 0x3FFF -#define I2C_COMMAND6_S 0 - -#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) -/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (BIT(31)) -#define I2C_COMMAND7_DONE_V 0x1 -#define I2C_COMMAND7_DONE_S 31 -/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: .*/ -#define I2C_COMMAND7 0x00003FFF -#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) -#define I2C_COMMAND7_V 0x3FFF -#define I2C_COMMAND7_S 0 - -#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) -/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ -/*description: no more than 23.*/ -#define I2C_SCL_ST_TO_REG 0x0000001F -#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) -#define I2C_SCL_ST_TO_REG_V 0x1F -#define I2C_SCL_ST_TO_REG_S 0 - -#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) -/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ -/*description: no more than 23.*/ -#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F -#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) -#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F -#define I2C_SCL_MAIN_ST_TO_REG_S 0 - -#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) -/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (BIT(7)) -#define I2C_SDA_PD_EN_V 0x1 -#define I2C_SDA_PD_EN_S 7 -/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (BIT(6)) -#define I2C_SCL_PD_EN_V 0x1 -#define I2C_SCL_PD_EN_S 6 -/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ -/*description: .*/ -#define I2C_SCL_RST_SLV_NUM 0x0000001F -#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) -#define I2C_SCL_RST_SLV_NUM_V 0x1F -#define I2C_SCL_RST_SLV_NUM_S 1 -/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (BIT(0)) -#define I2C_SCL_RST_SLV_EN_V 0x1 -#define I2C_SCL_RST_SLV_EN_S 0 - -#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) -/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 -#define I2C_SLAVE_BYTE_ACK_LVL_S 13 -/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 -#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 -/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 -#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 -/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 -#define I2C_SLAVE_SCL_STRETCH_EN_S 10 -/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: .*/ -#define I2C_STRETCH_PROTECT_NUM 0x000003FF -#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) -#define I2C_STRETCH_PROTECT_NUM_V 0x3FF -#define I2C_STRETCH_PROTECT_NUM_S 0 - -#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) -/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ -/*description: .*/ -#define I2C_DATE 0xFFFFFFFF -#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) -#define I2C_DATE_V 0xFFFFFFFF -#define I2C_DATE_S 0 - -#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) - -#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_I2C_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/i2c_struct.h b/components/soc/esp32h4/include/soc/i2c_struct.h deleted file mode 100644 index 5eb6bca92b..0000000000 --- a/components/soc/esp32h4/include/soc/i2c_struct.h +++ /dev/null @@ -1,399 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_I2C_STRUCT_H_ -#define _SOC_I2C_STRUCT_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct i2c_dev_s { - union { - struct { - uint32_t period : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } scl_low_period; - union { - struct { - uint32_t sda_force_out : 1; - uint32_t scl_force_out : 1; - uint32_t sample_scl_level : 1; - uint32_t rx_full_ack_level : 1; - uint32_t ms_mode : 1; - uint32_t trans_start : 1; - uint32_t tx_lsb_first : 1; - uint32_t rx_lsb_first : 1; - uint32_t clk_en : 1; - uint32_t arbitration_en : 1; - uint32_t fsm_rst : 1; - uint32_t conf_upgate : 1; - uint32_t slv_tx_auto_start_en : 1; - uint32_t addr_10bit_rw_check_en : 1; - uint32_t addr_broadcasting_en : 1; - uint32_t reserved15 : 17; - }; - uint32_t val; - } ctr; - union { - struct { - uint32_t resp_rec : 1; - uint32_t slave_rw : 1; - uint32_t reserved2 : 1; - uint32_t arb_lost : 1; - uint32_t bus_busy : 1; - uint32_t slave_addressed : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t rx_fifo_cnt : 6; - uint32_t stretch_cause : 2; - uint32_t reserved16 : 2; - uint32_t tx_fifo_cnt : 6; - uint32_t scl_main_state_last : 3; - uint32_t reserved27 : 1; - uint32_t scl_state_last : 3; - uint32_t reserved31 : 1; - }; - uint32_t val; - } sr; - union { - struct { - uint32_t time_out_value : 5; - uint32_t time_out_en : 1; - uint32_t reserved6 : 26; - }; - uint32_t val; - } timeout; - union { - struct { - uint32_t addr : 15; - uint32_t reserved15 : 16; - uint32_t en_10bit : 1; - }; - uint32_t val; - } slave_addr; - union { - struct { - uint32_t rx_fifo_raddr : 5; - uint32_t rx_fifo_waddr : 5; - uint32_t tx_fifo_raddr : 5; - uint32_t tx_fifo_waddr : 5; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t slave_rw_point : 8; - uint32_t reserved30 : 2; - }; - uint32_t val; - } fifo_st; - union { - struct { - uint32_t rx_fifo_wm_thrhd : 5; - uint32_t tx_fifo_wm_thrhd : 5; - uint32_t nonfifo_en : 1; - uint32_t fifo_addr_cfg_en : 1; - uint32_t rx_fifo_rst : 1; - uint32_t tx_fifo_rst : 1; - uint32_t fifo_prt_en : 1; - uint32_t reserved15 : 5; - uint32_t reserved20 : 6; - uint32_t reserved26 : 1; - uint32_t reserved27 : 5; - }; - uint32_t val; - } fifo_conf; - union { - struct { - uint32_t data : 8; - uint32_t reserved8 : 24; - }; - uint32_t val; - } fifo_data; - union { - struct { - uint32_t rx_fifo_wm : 1; - uint32_t tx_fifo_wm : 1; - uint32_t rx_fifo_ovf : 1; - uint32_t end_detect : 1; - uint32_t byte_trans_done : 1; - uint32_t arbitration_lost : 1; - uint32_t mst_tx_fifo_udf : 1; - uint32_t trans_complete : 1; - uint32_t time_out : 1; - uint32_t trans_start : 1; - uint32_t nack : 1; - uint32_t tx_fifo_ovf : 1; - uint32_t rx_fifo_udf : 1; - uint32_t scl_st_to : 1; - uint32_t scl_main_st_to : 1; - uint32_t det_start : 1; - uint32_t slave_stretch : 1; - uint32_t general_call : 1; - uint32_t reserved18 : 14; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t rx_fifo_wm : 1; - uint32_t tx_fifo_wm : 1; - uint32_t rx_fifo_ovf : 1; - uint32_t end_detect : 1; - uint32_t byte_trans_done : 1; - uint32_t arbitration_lost : 1; - uint32_t mst_tx_fifo_udf : 1; - uint32_t trans_complete : 1; - uint32_t time_out : 1; - uint32_t trans_start : 1; - uint32_t nack : 1; - uint32_t tx_fifo_ovf : 1; - uint32_t rx_fifo_udf : 1; - uint32_t scl_st_to : 1; - uint32_t scl_main_st_to : 1; - uint32_t det_start : 1; - uint32_t slave_stretch : 1; - uint32_t general_call : 1; - uint32_t reserved18 : 14; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t rx_fifo_wm : 1; - uint32_t tx_fifo_wm : 1; - uint32_t rx_fifo_ovf : 1; - uint32_t end_detect : 1; - uint32_t byte_trans_done : 1; - uint32_t arbitration_lost : 1; - uint32_t mst_tx_fifo_udf : 1; - uint32_t trans_complete : 1; - uint32_t time_out : 1; - uint32_t trans_start : 1; - uint32_t nack : 1; - uint32_t tx_fifo_ovf : 1; - uint32_t rx_fifo_udf : 1; - uint32_t scl_st_to : 1; - uint32_t scl_main_st_to : 1; - uint32_t det_start : 1; - uint32_t slave_stretch : 1; - uint32_t general_call : 1; - uint32_t reserved18 : 14; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t rx_fifo_wm : 1; - uint32_t tx_fifo_wm : 1; - uint32_t rx_fifo_ovf : 1; - uint32_t end_detect : 1; - uint32_t byte_trans_done : 1; - uint32_t arbitration_lost : 1; - uint32_t mst_tx_fifo_udf : 1; - uint32_t trans_complete : 1; - uint32_t time_out : 1; - uint32_t trans_start : 1; - uint32_t nack : 1; - uint32_t tx_fifo_ovf : 1; - uint32_t rx_fifo_udf : 1; - uint32_t scl_st_to : 1; - uint32_t scl_main_st_to : 1; - uint32_t det_start : 1; - uint32_t slave_stretch : 1; - uint32_t general_call : 1; - uint32_t reserved18 : 14; - }; - uint32_t val; - } int_status; - union { - struct { - uint32_t time : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } sda_hold; - union { - struct { - uint32_t time : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } sda_sample; - union { - struct { - uint32_t period : 9; - uint32_t scl_wait_high_period : 7; - uint32_t reserved16 : 16; - }; - uint32_t val; - } scl_high_period; - uint32_t reserved_3c; - union { - struct { - uint32_t time : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } scl_start_hold; - union { - struct { - uint32_t time : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } scl_rstart_setup; - union { - struct { - uint32_t time : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } scl_stop_hold; - union { - struct { - uint32_t time : 9; - uint32_t reserved9 : 23; - }; - uint32_t val; - } scl_stop_setup; - union { - struct { - uint32_t scl_thres : 4; - uint32_t sda_thres : 4; - uint32_t scl_en : 1; - uint32_t sda_en : 1; - uint32_t reserved10 : 22; - }; - uint32_t val; - } filter_cfg; - union { - struct { - uint32_t sclk_div_num : 8; - uint32_t sclk_div_a : 6; - uint32_t sclk_div_b : 6; - uint32_t sclk_sel : 1; - uint32_t sclk_active : 1; - uint32_t reserved22 : 10; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t command0 : 14; - uint32_t reserved14 : 17; - uint32_t command0_done : 1; - }; - uint32_t val; - } command[8]; - union { - struct { - uint32_t scl_st_to : 5; /*no more than 23*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } scl_st_time_out; - union { - struct { - uint32_t scl_main_st_to : 5; /*no more than 23*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } scl_main_st_time_out; - union { - struct { - uint32_t scl_rst_slv_en : 1; - uint32_t scl_rst_slv_num : 5; - uint32_t scl_pd_en : 1; - uint32_t sda_pd_en : 1; - uint32_t reserved8 : 24; - }; - uint32_t val; - } scl_sp_conf; - union { - struct { - uint32_t stretch_protect_num : 10; - uint32_t slave_scl_stretch_en : 1; - uint32_t slave_scl_stretch_clr : 1; - uint32_t slave_byte_ack_ctl_en : 1; - uint32_t slave_byte_ack_level : 1; - uint32_t reserved14 : 18; - }; - uint32_t val; - } scl_stretch_conf; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t date; - uint32_t reserved_fc; - uint32_t txfifo_start_addr; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t rxfifo_start_addr; -} i2c_dev_t; -extern i2c_dev_t I2C0; -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_I2C_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/soc/i2s_reg.h b/components/soc/esp32h4/include/soc/i2s_reg.h deleted file mode 100644 index c7baddb70b..0000000000 --- a/components/soc/esp32h4/include/soc/i2s_reg.h +++ /dev/null @@ -1,1076 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_I2S_REG_H_ -#define _SOC_I2S_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) -/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_RAW (BIT(3)) -#define I2S_TX_HUNG_INT_RAW_M (BIT(3)) -#define I2S_TX_HUNG_INT_RAW_V 0x1 -#define I2S_TX_HUNG_INT_RAW_S 3 -/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_RAW (BIT(2)) -#define I2S_RX_HUNG_INT_RAW_M (BIT(2)) -#define I2S_RX_HUNG_INT_RAW_V 0x1 -#define I2S_RX_HUNG_INT_RAW_S 2 -/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_RAW (BIT(1)) -#define I2S_TX_DONE_INT_RAW_M (BIT(1)) -#define I2S_TX_DONE_INT_RAW_V 0x1 -#define I2S_TX_DONE_INT_RAW_S 1 -/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_RAW (BIT(0)) -#define I2S_RX_DONE_INT_RAW_M (BIT(0)) -#define I2S_RX_DONE_INT_RAW_V 0x1 -#define I2S_RX_DONE_INT_RAW_S 0 - -#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) -/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_ST (BIT(3)) -#define I2S_TX_HUNG_INT_ST_M (BIT(3)) -#define I2S_TX_HUNG_INT_ST_V 0x1 -#define I2S_TX_HUNG_INT_ST_S 3 -/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_ST (BIT(2)) -#define I2S_RX_HUNG_INT_ST_M (BIT(2)) -#define I2S_RX_HUNG_INT_ST_V 0x1 -#define I2S_RX_HUNG_INT_ST_S 2 -/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_ST (BIT(1)) -#define I2S_TX_DONE_INT_ST_M (BIT(1)) -#define I2S_TX_DONE_INT_ST_V 0x1 -#define I2S_TX_DONE_INT_ST_S 1 -/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_ST (BIT(0)) -#define I2S_RX_DONE_INT_ST_M (BIT(0)) -#define I2S_RX_DONE_INT_ST_V 0x1 -#define I2S_RX_DONE_INT_ST_S 0 - -#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) -/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_ENA (BIT(3)) -#define I2S_TX_HUNG_INT_ENA_M (BIT(3)) -#define I2S_TX_HUNG_INT_ENA_V 0x1 -#define I2S_TX_HUNG_INT_ENA_S 3 -/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_ENA (BIT(2)) -#define I2S_RX_HUNG_INT_ENA_M (BIT(2)) -#define I2S_RX_HUNG_INT_ENA_V 0x1 -#define I2S_RX_HUNG_INT_ENA_S 2 -/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_ENA (BIT(1)) -#define I2S_TX_DONE_INT_ENA_M (BIT(1)) -#define I2S_TX_DONE_INT_ENA_V 0x1 -#define I2S_TX_DONE_INT_ENA_S 1 -/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_ENA (BIT(0)) -#define I2S_RX_DONE_INT_ENA_M (BIT(0)) -#define I2S_RX_DONE_INT_ENA_V 0x1 -#define I2S_RX_DONE_INT_ENA_S 0 - -#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) -/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/ -#define I2S_TX_HUNG_INT_CLR (BIT(3)) -#define I2S_TX_HUNG_INT_CLR_M (BIT(3)) -#define I2S_TX_HUNG_INT_CLR_V 0x1 -#define I2S_TX_HUNG_INT_CLR_S 3 -/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/ -#define I2S_RX_HUNG_INT_CLR (BIT(2)) -#define I2S_RX_HUNG_INT_CLR_M (BIT(2)) -#define I2S_RX_HUNG_INT_CLR_V 0x1 -#define I2S_RX_HUNG_INT_CLR_S 2 -/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_tx_done_int interrupt*/ -#define I2S_TX_DONE_INT_CLR (BIT(1)) -#define I2S_TX_DONE_INT_CLR_M (BIT(1)) -#define I2S_TX_DONE_INT_CLR_V 0x1 -#define I2S_TX_DONE_INT_CLR_S 1 -/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the i2s_rx_done_int interrupt*/ -#define I2S_RX_DONE_INT_CLR (BIT(0)) -#define I2S_RX_DONE_INT_CLR_M (BIT(0)) -#define I2S_RX_DONE_INT_CLR_V 0x1 -#define I2S_RX_DONE_INT_CLR_S 0 - -#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) -/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: */ -#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22)) -#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22)) -#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 -#define I2S_RX_PDM_SINC_DSR_16_EN_S 22 -/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: 1: Enable PDM2PCM RX mode. 0: DIsable.*/ -#define I2S_RX_PDM2PCM_EN (BIT(21)) -#define I2S_RX_PDM2PCM_EN_M (BIT(21)) -#define I2S_RX_PDM2PCM_EN_V 0x1 -#define I2S_RX_PDM2PCM_EN_S 21 -/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/ -#define I2S_RX_PDM_EN (BIT(20)) -#define I2S_RX_PDM_EN_M (BIT(20)) -#define I2S_RX_PDM_EN_V 0x1 -#define I2S_RX_PDM_EN_S 20 -/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/ -#define I2S_RX_TDM_EN (BIT(19)) -#define I2S_RX_TDM_EN_M (BIT(19)) -#define I2S_RX_TDM_EN_V 0x1 -#define I2S_RX_TDM_EN_S 19 -/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: I2S Rx bit endian. 1:small endian the LSB is received first. - 0:big endian the MSB is received first.*/ -#define I2S_RX_BIT_ORDER (BIT(18)) -#define I2S_RX_BIT_ORDER_M (BIT(18)) -#define I2S_RX_BIT_ORDER_V 0x1 -#define I2S_RX_BIT_ORDER_S 18 -/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: 0: WS should be 0 when receiving left channel data and WS is - 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ -#define I2S_RX_WS_IDLE_POL (BIT(17)) -#define I2S_RX_WS_IDLE_POL_M (BIT(17)) -#define I2S_RX_WS_IDLE_POL_V 0x1 -#define I2S_RX_WS_IDLE_POL_S 17 -/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ -#define I2S_RX_24_FILL_EN (BIT(16)) -#define I2S_RX_24_FILL_EN_M (BIT(16)) -#define I2S_RX_24_FILL_EN_V 0x1 -#define I2S_RX_24_FILL_EN_S 16 -/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ -#define I2S_RX_LEFT_ALIGN (BIT(15)) -#define I2S_RX_LEFT_ALIGN_M (BIT(15)) -#define I2S_RX_LEFT_ALIGN_V 0x1 -#define I2S_RX_LEFT_ALIGN_S 15 -/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */ -/*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop - when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ -#define I2S_RX_STOP_MODE 0x00000003 -#define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S)) -#define I2S_RX_STOP_MODE_V 0x3 -#define I2S_RX_STOP_MODE_S 13 -/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to bypass Compress/Decompress module for received data.*/ -#define I2S_RX_PCM_BYPASS (BIT(12)) -#define I2S_RX_PCM_BYPASS_M (BIT(12)) -#define I2S_RX_PCM_BYPASS_V 0x1 -#define I2S_RX_PCM_BYPASS_S 12 -/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */ -/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law - decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ -#define I2S_RX_PCM_CONF 0x00000003 -#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) -#define I2S_RX_PCM_CONF_V 0x3 -#define I2S_RX_PCM_CONF_S 10 -/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: 1: The first channel data value is valid in I2S RX mono mode. - 0: The second channel data value is valid in I2S RX mono mode.*/ -#define I2S_RX_MONO_FST_VLD (BIT(9)) -#define I2S_RX_MONO_FST_VLD_M (BIT(9)) -#define I2S_RX_MONO_FST_VLD_V 0x1 -#define I2S_RX_MONO_FST_VLD_S 9 -/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set 1 to update I2S RX registers from APB clock domain to I2S - RX clock domain. This bit will be cleared by hardware after update register done.*/ -#define I2S_RX_UPDATE (BIT(8)) -#define I2S_RX_UPDATE_M (BIT(8)) -#define I2S_RX_UPDATE_V 0x1 -#define I2S_RX_UPDATE_S 8 -/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: I2S Rx byte endian 1: low addr value to high addr. 0: low addr - with low addr value.*/ -#define I2S_RX_BIG_ENDIAN (BIT(7)) -#define I2S_RX_BIG_ENDIAN_M (BIT(7)) -#define I2S_RX_BIG_ENDIAN_V 0x1 -#define I2S_RX_BIG_ENDIAN_S 7 -/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable receiver in mono mode*/ -#define I2S_RX_MONO (BIT(5)) -#define I2S_RX_MONO_M (BIT(5)) -#define I2S_RX_MONO_V 0x1 -#define I2S_RX_MONO_S 5 -/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable slave receiver mode*/ -#define I2S_RX_SLAVE_MOD (BIT(3)) -#define I2S_RX_SLAVE_MOD_M (BIT(3)) -#define I2S_RX_SLAVE_MOD_V 0x1 -#define I2S_RX_SLAVE_MOD_S 3 -/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to start receiving data*/ -#define I2S_RX_START (BIT(2)) -#define I2S_RX_START_M (BIT(2)) -#define I2S_RX_START_V 0x1 -#define I2S_RX_START_S 2 -/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset Rx AFIFO*/ -#define I2S_RX_FIFO_RESET (BIT(1)) -#define I2S_RX_FIFO_RESET_M (BIT(1)) -#define I2S_RX_FIFO_RESET_V 0x1 -#define I2S_RX_FIFO_RESET_S 1 -/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to reset receiver*/ -#define I2S_RX_RESET (BIT(0)) -#define I2S_RX_RESET_M (BIT(0)) -#define I2S_RX_RESET_V 0x1 -#define I2S_RX_RESET_S 0 - -#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0024) -/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Enable signal loop back mode with transmitter module and receiver - module sharing the same WS and BCK signals.*/ -#define I2S_SIG_LOOPBACK (BIT(27)) -#define I2S_SIG_LOOPBACK_M (BIT(27)) -#define I2S_SIG_LOOPBACK_V 0x1 -#define I2S_SIG_LOOPBACK_S 27 -/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: I2S transmitter channel mode configuration bits.*/ -#define I2S_TX_CHAN_MOD 0x00000007 -#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) -#define I2S_TX_CHAN_MOD_V 0x7 -#define I2S_TX_CHAN_MOD_S 24 -/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/ -#define I2S_TX_PDM_EN (BIT(20)) -#define I2S_TX_PDM_EN_M (BIT(20)) -#define I2S_TX_PDM_EN_V 0x1 -#define I2S_TX_PDM_EN_S 20 -/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/ -#define I2S_TX_TDM_EN (BIT(19)) -#define I2S_TX_TDM_EN_M (BIT(19)) -#define I2S_TX_TDM_EN_V 0x1 -#define I2S_TX_TDM_EN_S 19 -/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big - endian the MSB is sent first.*/ -#define I2S_TX_BIT_ORDER (BIT(18)) -#define I2S_TX_BIT_ORDER_M (BIT(18)) -#define I2S_TX_BIT_ORDER_V 0x1 -#define I2S_TX_BIT_ORDER_S 18 -/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: 0: WS should be 0 when sending left channel data and WS is 1in - right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ -#define I2S_TX_WS_IDLE_POL (BIT(17)) -#define I2S_TX_WS_IDLE_POL_M (BIT(17)) -#define I2S_TX_WS_IDLE_POL_V 0x1 -#define I2S_TX_WS_IDLE_POL_S 17 -/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ -#define I2S_TX_24_FILL_EN (BIT(16)) -#define I2S_TX_24_FILL_EN_M (BIT(16)) -#define I2S_TX_24_FILL_EN_V 0x1 -#define I2S_TX_24_FILL_EN_S 16 -/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ -#define I2S_TX_LEFT_ALIGN (BIT(15)) -#define I2S_TX_LEFT_ALIGN_M (BIT(15)) -#define I2S_TX_LEFT_ALIGN_V 0x1 -#define I2S_TX_LEFT_ALIGN_S 15 -/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: Set this bit to stop disable output BCK signal and WS signal - when tx FIFO is emtpy*/ -#define I2S_TX_STOP_EN (BIT(13)) -#define I2S_TX_STOP_EN_M (BIT(13)) -#define I2S_TX_STOP_EN_V 0x1 -#define I2S_TX_STOP_EN_S 13 -/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/ -#define I2S_TX_PCM_BYPASS (BIT(12)) -#define I2S_TX_PCM_BYPASS_M (BIT(12)) -#define I2S_TX_PCM_BYPASS_V 0x1 -#define I2S_TX_PCM_BYPASS_S 12 -/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law - decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ -#define I2S_TX_PCM_CONF 0x00000003 -#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) -#define I2S_TX_PCM_CONF_V 0x3 -#define I2S_TX_PCM_CONF_S 10 -/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: 1: The first channel data value is valid in I2S TX mono mode. - 0: The second channel data value is valid in I2S TX mono mode.*/ -#define I2S_TX_MONO_FST_VLD (BIT(9)) -#define I2S_TX_MONO_FST_VLD_M (BIT(9)) -#define I2S_TX_MONO_FST_VLD_V 0x1 -#define I2S_TX_MONO_FST_VLD_S 9 -/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set 1 to update I2S TX registers from APB clock domain to I2S - TX clock domain. This bit will be cleared by hardware after update register done.*/ -#define I2S_TX_UPDATE (BIT(8)) -#define I2S_TX_UPDATE_M (BIT(8)) -#define I2S_TX_UPDATE_V 0x1 -#define I2S_TX_UPDATE_S 8 -/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: I2S Tx byte endian 1: low addr value to high addr. 0: low addr - with low addr value.*/ -#define I2S_TX_BIG_ENDIAN (BIT(7)) -#define I2S_TX_BIG_ENDIAN_M (BIT(7)) -#define I2S_TX_BIG_ENDIAN_V 0x1 -#define I2S_TX_BIG_ENDIAN_S 7 -/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: The value of Left channel data is equal to the value of right - channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ -#define I2S_TX_CHAN_EQUAL (BIT(6)) -#define I2S_TX_CHAN_EQUAL_M (BIT(6)) -#define I2S_TX_CHAN_EQUAL_V 0x1 -#define I2S_TX_CHAN_EQUAL_S 6 -/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable transmitter in mono mode*/ -#define I2S_TX_MONO (BIT(5)) -#define I2S_TX_MONO_M (BIT(5)) -#define I2S_TX_MONO_V 0x1 -#define I2S_TX_MONO_S 5 -/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable slave transmitter mode*/ -#define I2S_TX_SLAVE_MOD (BIT(3)) -#define I2S_TX_SLAVE_MOD_M (BIT(3)) -#define I2S_TX_SLAVE_MOD_V 0x1 -#define I2S_TX_SLAVE_MOD_S 3 -/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to start transmitting data*/ -#define I2S_TX_START (BIT(2)) -#define I2S_TX_START_M (BIT(2)) -#define I2S_TX_START_V 0x1 -#define I2S_TX_START_S 2 -/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset Tx AFIFO*/ -#define I2S_TX_FIFO_RESET (BIT(1)) -#define I2S_TX_FIFO_RESET_M (BIT(1)) -#define I2S_TX_FIFO_RESET_V 0x1 -#define I2S_TX_FIFO_RESET_S 1 -/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to reset transmitter*/ -#define I2S_TX_RESET (BIT(0)) -#define I2S_TX_RESET_M (BIT(0)) -#define I2S_TX_RESET_V 0x1 -#define I2S_TX_RESET_S 0 - -#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0028) -/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: Set this bit to enable receiver in Phillips standard mode*/ -#define I2S_RX_MSB_SHIFT (BIT(29)) -#define I2S_RX_MSB_SHIFT_M (BIT(29)) -#define I2S_RX_MSB_SHIFT_V 0x1 -#define I2S_RX_MSB_SHIFT_S 29 -/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ -/*description: The Rx bit number for each channel minus 1in TDM mode.*/ -#define I2S_RX_TDM_CHAN_BITS 0x0000001F -#define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S)) -#define I2S_RX_TDM_CHAN_BITS_V 0x1F -#define I2S_RX_TDM_CHAN_BITS_S 24 -/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ -/*description: I2S Rx half sample bits -1.*/ -#define I2S_RX_HALF_SAMPLE_BITS 0x0000003F -#define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S)) -#define I2S_RX_HALF_SAMPLE_BITS_V 0x3F -#define I2S_RX_HALF_SAMPLE_BITS_S 18 -/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ -/*description: Set the bits to configure bit length of I2S receiver channel.*/ -#define I2S_RX_BITS_MOD 0x0000001F -#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) -#define I2S_RX_BITS_MOD_V 0x1F -#define I2S_RX_BITS_MOD_S 13 -/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ -/*description: Bit clock configuration bits in receiver mode.*/ -#define I2S_RX_BCK_DIV_NUM 0x0000003F -#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) -#define I2S_RX_BCK_DIV_NUM_V 0x3F -#define I2S_RX_BCK_DIV_NUM_S 7 -/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ -#define I2S_RX_TDM_WS_WIDTH 0x0000007F -#define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S)) -#define I2S_RX_TDM_WS_WIDTH_V 0x7F -#define I2S_RX_TDM_WS_WIDTH_S 0 - -#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x002C) -/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: Set this bit to enable transmitter in Phillips standard mode*/ -#define I2S_TX_MSB_SHIFT (BIT(29)) -#define I2S_TX_MSB_SHIFT_M (BIT(29)) -#define I2S_TX_MSB_SHIFT_V 0x1 -#define I2S_TX_MSB_SHIFT_S 29 -/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ -/*description: The Tx bit number for each channel minus 1in TDM mode.*/ -#define I2S_TX_TDM_CHAN_BITS 0x0000001F -#define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S)) -#define I2S_TX_TDM_CHAN_BITS_V 0x1F -#define I2S_TX_TDM_CHAN_BITS_S 24 -/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ -/*description: I2S Tx half sample bits -1.*/ -#define I2S_TX_HALF_SAMPLE_BITS 0x0000003F -#define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S)) -#define I2S_TX_HALF_SAMPLE_BITS_V 0x3F -#define I2S_TX_HALF_SAMPLE_BITS_S 18 -/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ -/*description: Set the bits to configure bit length of I2S transmitter channel.*/ -#define I2S_TX_BITS_MOD 0x0000001F -#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) -#define I2S_TX_BITS_MOD_V 0x1F -#define I2S_TX_BITS_MOD_S 13 -/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ -/*description: Bit clock configuration bits in transmitter mode.*/ -#define I2S_TX_BCK_DIV_NUM 0x0000003F -#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) -#define I2S_TX_BCK_DIV_NUM_V 0x3F -#define I2S_TX_BCK_DIV_NUM_S 7 -/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ -#define I2S_TX_TDM_WS_WIDTH 0x0000007F -#define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S)) -#define I2S_TX_TDM_WS_WIDTH_V 0x7F -#define I2S_TX_TDM_WS_WIDTH_S 0 - -#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0030) -/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module - clock as I2S_MCLK_OUT.*/ -#define I2S_MCLK_SEL (BIT(29)) -#define I2S_MCLK_SEL_M (BIT(29)) -#define I2S_MCLK_SEL_V 0x1 -#define I2S_MCLK_SEL_S 29 -/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. - 3: I2S_MCLK_in.*/ -#define I2S_RX_CLK_SEL 0x00000003 -#define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S)) -#define I2S_RX_CLK_SEL_V 0x3 -#define I2S_RX_CLK_SEL_S 27 -/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: I2S Rx module clock enable signal.*/ -#define I2S_RX_CLK_ACTIVE (BIT(26)) -#define I2S_RX_CLK_ACTIVE_M (BIT(26)) -#define I2S_RX_CLK_ACTIVE_V 0x1 -#define I2S_RX_CLK_ACTIVE_S 26 -/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: Integral I2S clock divider value*/ -#define I2S_RX_CLKM_DIV_NUM 0x000000FF -#define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S)) -#define I2S_RX_CLKM_DIV_NUM_V 0xFF -#define I2S_RX_CLKM_DIV_NUM_S 0 - -#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0034) -/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable clk gate*/ -#define I2S_CLK_EN (BIT(29)) -#define I2S_CLK_EN_M (BIT(29)) -#define I2S_CLK_EN_V 0x1 -#define I2S_CLK_EN_S 29 -/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: - CLK160. 3: I2S_MCLK_in.*/ -#define I2S_TX_CLK_SEL 0x00000003 -#define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S)) -#define I2S_TX_CLK_SEL_V 0x3 -#define I2S_TX_CLK_SEL_S 27 -/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: I2S Tx module clock enable signal.*/ -#define I2S_TX_CLK_ACTIVE (BIT(26)) -#define I2S_TX_CLK_ACTIVE_M (BIT(26)) -#define I2S_TX_CLK_ACTIVE_V 0x1 -#define I2S_TX_CLK_ACTIVE_S 26 -/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). - There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ -#define I2S_TX_CLKM_DIV_NUM 0x000000FF -#define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S)) -#define I2S_TX_CLKM_DIV_NUM_V 0xFF -#define I2S_TX_CLKM_DIV_NUM_S 0 - -#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x0038) -/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > - a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ -#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) -#define I2S_RX_CLKM_DIV_YN1_M (BIT(27)) -#define I2S_RX_CLKM_DIV_YN1_V 0x1 -#define I2S_RX_CLKM_DIV_YN1_S 27 -/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For - b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ -#define I2S_RX_CLKM_DIV_X 0x000001FF -#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S)) -#define I2S_RX_CLKM_DIV_X_V 0x1FF -#define I2S_RX_CLKM_DIV_X_S 18 -/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b - > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ -#define I2S_RX_CLKM_DIV_Y 0x000001FF -#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S)) -#define I2S_RX_CLKM_DIV_Y_V 0x1FF -#define I2S_RX_CLKM_DIV_Y_S 9 -/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 - the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ -#define I2S_RX_CLKM_DIV_Z 0x000001FF -#define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S)) -#define I2S_RX_CLKM_DIV_Z_V 0x1FF -#define I2S_RX_CLKM_DIV_Z_S 0 - -#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x003C) -/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > - a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ -#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) -#define I2S_TX_CLKM_DIV_YN1_M (BIT(27)) -#define I2S_TX_CLKM_DIV_YN1_V 0x1 -#define I2S_TX_CLKM_DIV_YN1_S 27 -/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For - b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ -#define I2S_TX_CLKM_DIV_X 0x000001FF -#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S)) -#define I2S_TX_CLKM_DIV_X_V 0x1FF -#define I2S_TX_CLKM_DIV_X_S 18 -/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b - > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ -#define I2S_TX_CLKM_DIV_Y 0x000001FF -#define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S)) -#define I2S_TX_CLKM_DIV_Y_V 0x1FF -#define I2S_TX_CLKM_DIV_Y_S 9 -/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 - the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ -#define I2S_TX_CLKM_DIV_Z 0x000001FF -#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S)) -#define I2S_TX_CLKM_DIV_Z_V 0x1FF -#define I2S_TX_CLKM_DIV_Z_S 0 - -#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x040) -/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: I2S TX PDM Converter enable.*/ -#define I2S_PCM2PDM_CONV_EN (BIT(25)) -#define I2S_PCM2PDM_CONV_EN_M (BIT(25)) -#define I2S_PCM2PDM_CONV_EN_V 0x1 -#define I2S_PCM2PDM_CONV_EN_S 25 -/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: I2S TX PDM dac 2channel enable.*/ -#define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) -#define I2S_TX_PDM_DAC_MODE_EN_M (BIT(24)) -#define I2S_TX_PDM_DAC_MODE_EN_V 0x1 -#define I2S_TX_PDM_DAC_MODE_EN_S 24 -/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: I2S TX PDM dac mode enable.*/ -#define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) -#define I2S_TX_PDM_DAC_2OUT_EN_M (BIT(23)) -#define I2S_TX_PDM_DAC_2OUT_EN_V 0x1 -#define I2S_TX_PDM_DAC_2OUT_EN_S 23 -/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: I2S TX PDM sigmadelta dither value.*/ -#define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) -#define I2S_TX_PDM_SIGMADELTA_DITHER_M (BIT(22)) -#define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x1 -#define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 -/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: I2S TX PDM sigmadelta dither2 value.*/ -#define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) -#define I2S_TX_PDM_SIGMADELTA_DITHER2_M (BIT(21)) -#define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x1 -#define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 -/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */ -/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 -/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */ -/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ -#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) -#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_SINC_IN_SHIFT_S 17 -/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */ -/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ -#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) -#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_LP_IN_SHIFT_S 15 -/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ -/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ -#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) -#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_HP_IN_SHIFT_S 13 -/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */ -/*description: I2S TX PDM prescale for sigmadelta.*/ -#define I2S_TX_PDM_PRESCALE 0x000000FF -#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) -#define I2S_TX_PDM_PRESCALE_V 0xFF -#define I2S_TX_PDM_PRESCALE_S 5 -/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */ -/*description: I2S TX PDM OSR2 value.*/ -#define I2S_TX_PDM_SINC_OSR2 0x0000000F -#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) -#define I2S_TX_PDM_SINC_OSR2_V 0xF -#define I2S_TX_PDM_SINC_OSR2_S 1 -/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/ -#define I2S_TX_PDM_HP_BYPASS (BIT(0)) -#define I2S_TX_PDM_HP_BYPASS_M (BIT(0)) -#define I2S_TX_PDM_HP_BYPASS_V 0x1 -#define I2S_TX_PDM_HP_BYPASS_S 0 - -#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44) -/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */ -/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL -T12_0[2:0]).*/ -#define I2S_TX_IIR_HP_MULT12_0 0x00000007 -#define I2S_TX_IIR_HP_MULT12_0_M ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S)) -#define I2S_TX_IIR_HP_MULT12_0_V 0x7 -#define I2S_TX_IIR_HP_MULT12_0_S 23 -/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */ -/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL -T12_5[2:0]).*/ -#define I2S_TX_IIR_HP_MULT12_5 0x00000007 -#define I2S_TX_IIR_HP_MULT12_5_M ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S)) -#define I2S_TX_IIR_HP_MULT12_5_V 0x7 -#define I2S_TX_IIR_HP_MULT12_5_S 20 -/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */ -/*description: I2S TX PDM Fs.*/ -#define I2S_TX_PDM_FS 0x000003FF -#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) -#define I2S_TX_PDM_FS_V 0x3FF -#define I2S_TX_PDM_FS_S 10 -/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */ -/*description: I2S TX PDM Fp.*/ -#define I2S_TX_PDM_FP 0x000003FF -#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) -#define I2S_TX_PDM_FP_V 0x3FF -#define I2S_TX_PDM_FP_S 0 - -#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x050) -/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The total channel number of I2S TX TDM mode.*/ -#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F -#define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S)) -#define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF -#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 -/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN15_EN (BIT(15)) -#define I2S_RX_TDM_CHAN15_EN_M (BIT(15)) -#define I2S_RX_TDM_CHAN15_EN_V 0x1 -#define I2S_RX_TDM_CHAN15_EN_S 15 -/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN14_EN (BIT(14)) -#define I2S_RX_TDM_CHAN14_EN_M (BIT(14)) -#define I2S_RX_TDM_CHAN14_EN_V 0x1 -#define I2S_RX_TDM_CHAN14_EN_S 14 -/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN13_EN (BIT(13)) -#define I2S_RX_TDM_CHAN13_EN_M (BIT(13)) -#define I2S_RX_TDM_CHAN13_EN_V 0x1 -#define I2S_RX_TDM_CHAN13_EN_S 13 -/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN12_EN (BIT(12)) -#define I2S_RX_TDM_CHAN12_EN_M (BIT(12)) -#define I2S_RX_TDM_CHAN12_EN_V 0x1 -#define I2S_RX_TDM_CHAN12_EN_S 12 -/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN11_EN (BIT(11)) -#define I2S_RX_TDM_CHAN11_EN_M (BIT(11)) -#define I2S_RX_TDM_CHAN11_EN_V 0x1 -#define I2S_RX_TDM_CHAN11_EN_S 11 -/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN10_EN (BIT(10)) -#define I2S_RX_TDM_CHAN10_EN_M (BIT(10)) -#define I2S_RX_TDM_CHAN10_EN_V 0x1 -#define I2S_RX_TDM_CHAN10_EN_S 10 -/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN9_EN (BIT(9)) -#define I2S_RX_TDM_CHAN9_EN_M (BIT(9)) -#define I2S_RX_TDM_CHAN9_EN_V 0x1 -#define I2S_RX_TDM_CHAN9_EN_S 9 -/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: - Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_CHAN8_EN (BIT(8)) -#define I2S_RX_TDM_CHAN8_EN_M (BIT(8)) -#define I2S_RX_TDM_CHAN8_EN_V 0x1 -#define I2S_RX_TDM_CHAN8_EN_S 8 -/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) -#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) -#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 -/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) -#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) -#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 -/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) -#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) -#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 -/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) -#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) -#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 -/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) -#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) -#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 -/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) -#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) -#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 -/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) -#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) -#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 -/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. - 0: Disable just input 0 in this channel.*/ -#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) -#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) -#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1 -#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 - -#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0054) -/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM - + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ -#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) -#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) -#define I2S_TX_TDM_SKIP_MSK_EN_V 0x1 -#define I2S_TX_TDM_SKIP_MSK_EN_S 20 -/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: The total channel number minus 1 of I2S TX TDM mode.*/ -#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F -#define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S)) -#define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF -#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 -/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN15_EN (BIT(15)) -#define I2S_TX_TDM_CHAN15_EN_M (BIT(15)) -#define I2S_TX_TDM_CHAN15_EN_V 0x1 -#define I2S_TX_TDM_CHAN15_EN_S 15 -/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN14_EN (BIT(14)) -#define I2S_TX_TDM_CHAN14_EN_M (BIT(14)) -#define I2S_TX_TDM_CHAN14_EN_V 0x1 -#define I2S_TX_TDM_CHAN14_EN_S 14 -/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN13_EN (BIT(13)) -#define I2S_TX_TDM_CHAN13_EN_M (BIT(13)) -#define I2S_TX_TDM_CHAN13_EN_V 0x1 -#define I2S_TX_TDM_CHAN13_EN_S 13 -/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN12_EN (BIT(12)) -#define I2S_TX_TDM_CHAN12_EN_M (BIT(12)) -#define I2S_TX_TDM_CHAN12_EN_V 0x1 -#define I2S_TX_TDM_CHAN12_EN_S 12 -/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN11_EN (BIT(11)) -#define I2S_TX_TDM_CHAN11_EN_M (BIT(11)) -#define I2S_TX_TDM_CHAN11_EN_V 0x1 -#define I2S_TX_TDM_CHAN11_EN_S 11 -/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN10_EN (BIT(10)) -#define I2S_TX_TDM_CHAN10_EN_M (BIT(10)) -#define I2S_TX_TDM_CHAN10_EN_V 0x1 -#define I2S_TX_TDM_CHAN10_EN_S 10 -/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN9_EN (BIT(9)) -#define I2S_TX_TDM_CHAN9_EN_M (BIT(9)) -#define I2S_TX_TDM_CHAN9_EN_V 0x1 -#define I2S_TX_TDM_CHAN9_EN_S 9 -/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN8_EN (BIT(8)) -#define I2S_TX_TDM_CHAN8_EN_M (BIT(8)) -#define I2S_TX_TDM_CHAN8_EN_V 0x1 -#define I2S_TX_TDM_CHAN8_EN_S 8 -/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN7_EN (BIT(7)) -#define I2S_TX_TDM_CHAN7_EN_M (BIT(7)) -#define I2S_TX_TDM_CHAN7_EN_V 0x1 -#define I2S_TX_TDM_CHAN7_EN_S 7 -/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN6_EN (BIT(6)) -#define I2S_TX_TDM_CHAN6_EN_M (BIT(6)) -#define I2S_TX_TDM_CHAN6_EN_V 0x1 -#define I2S_TX_TDM_CHAN6_EN_S 6 -/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN5_EN (BIT(5)) -#define I2S_TX_TDM_CHAN5_EN_M (BIT(5)) -#define I2S_TX_TDM_CHAN5_EN_V 0x1 -#define I2S_TX_TDM_CHAN5_EN_S 5 -/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN4_EN (BIT(4)) -#define I2S_TX_TDM_CHAN4_EN_M (BIT(4)) -#define I2S_TX_TDM_CHAN4_EN_V 0x1 -#define I2S_TX_TDM_CHAN4_EN_S 4 -/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN3_EN (BIT(3)) -#define I2S_TX_TDM_CHAN3_EN_M (BIT(3)) -#define I2S_TX_TDM_CHAN3_EN_V 0x1 -#define I2S_TX_TDM_CHAN3_EN_S 3 -/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN2_EN (BIT(2)) -#define I2S_TX_TDM_CHAN2_EN_M (BIT(2)) -#define I2S_TX_TDM_CHAN2_EN_V 0x1 -#define I2S_TX_TDM_CHAN2_EN_S 2 -/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN1_EN (BIT(1)) -#define I2S_TX_TDM_CHAN1_EN_M (BIT(1)) -#define I2S_TX_TDM_CHAN1_EN_V 0x1 -#define I2S_TX_TDM_CHAN1_EN_S 1 -/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: - Disable just output 0 in this channel.*/ -#define I2S_TX_TDM_CHAN0_EN (BIT(0)) -#define I2S_TX_TDM_CHAN0_EN_M (BIT(0)) -#define I2S_TX_TDM_CHAN0_EN_V 0x1 -#define I2S_TX_TDM_CHAN0_EN_S 0 - -#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x0058) -/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_BCK_IN_DM 0x00000003 -#define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S)) -#define I2S_RX_BCK_IN_DM_V 0x3 -#define I2S_RX_BCK_IN_DM_S 28 -/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_WS_IN_DM 0x00000003 -#define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S)) -#define I2S_RX_WS_IN_DM_V 0x3 -#define I2S_RX_WS_IN_DM_S 24 -/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_BCK_OUT_DM 0x00000003 -#define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S)) -#define I2S_RX_BCK_OUT_DM_V 0x3 -#define I2S_RX_BCK_OUT_DM_S 20 -/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_WS_OUT_DM 0x00000003 -#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S)) -#define I2S_RX_WS_OUT_DM_V 0x3 -#define I2S_RX_WS_OUT_DM_S 16 -/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD3_IN_DM 0x00000003 -#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V)<<(I2S_RX_SD3_IN_DM_S)) -#define I2S_RX_SD3_IN_DM_V 0x3 -#define I2S_RX_SD3_IN_DM_S 12 -/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD2_IN_DM 0x00000003 -#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V)<<(I2S_RX_SD2_IN_DM_S)) -#define I2S_RX_SD2_IN_DM_V 0x3 -#define I2S_RX_SD2_IN_DM_S 8 -/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD1_IN_DM 0x00000003 -#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V)<<(I2S_RX_SD1_IN_DM_S)) -#define I2S_RX_SD1_IN_DM_V 0x3 -#define I2S_RX_SD1_IN_DM_S 4 -/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_RX_SD_IN_DM 0x00000003 -#define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S)) -#define I2S_RX_SD_IN_DM_V 0x3 -#define I2S_RX_SD_IN_DM_S 0 - -#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x005C) -/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_BCK_IN_DM 0x00000003 -#define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S)) -#define I2S_TX_BCK_IN_DM_V 0x3 -#define I2S_TX_BCK_IN_DM_S 28 -/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_WS_IN_DM 0x00000003 -#define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S)) -#define I2S_TX_WS_IN_DM_V 0x3 -#define I2S_TX_WS_IN_DM_S 24 -/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_BCK_OUT_DM 0x00000003 -#define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S)) -#define I2S_TX_BCK_OUT_DM_V 0x3 -#define I2S_TX_BCK_OUT_DM_S 20 -/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_WS_OUT_DM 0x00000003 -#define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S)) -#define I2S_TX_WS_OUT_DM_V 0x3 -#define I2S_TX_WS_OUT_DM_S 16 -/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: - delay by neg edge. 3: not used..*/ -#define I2S_TX_SD1_OUT_DM 0x00000003 -#define I2S_TX_SD1_OUT_DM_M ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S)) -#define I2S_TX_SD1_OUT_DM_V 0x3 -#define I2S_TX_SD1_OUT_DM_S 4 -/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used.*/ -#define I2S_TX_SD_OUT_DM 0x00000003 -#define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S)) -#define I2S_TX_SD_OUT_DM_V 0x3 -#define I2S_TX_SD_OUT_DM_S 0 - -#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) -/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: The enable bit for FIFO timeout*/ -#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) -#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) -#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 -#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 -/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: The bits are used to scale tick counter threshold. The tick counter - is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ -#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 -#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) -#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 -#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 -/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ -/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt - will be triggered when fifo hung counter is equal to this value*/ -#define I2S_LC_FIFO_TIMEOUT 0x000000FF -#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) -#define I2S_LC_FIFO_TIMEOUT_V 0xFF -#define I2S_LC_FIFO_TIMEOUT_S 0 - -#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0064) -/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */ -/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ -#define I2S_RX_EOF_NUM 0x00000FFF -#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) -#define I2S_RX_EOF_NUM_V 0xFFF -#define I2S_RX_EOF_NUM_S 0 - -#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068) -/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: the right channel or left channel put out constant value stored - in this register according to tx_chan_mod and reg_tx_msb_right*/ -#define I2S_SINGLE_DATA 0xFFFFFFFF -#define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S)) -#define I2S_SINGLE_DATA_V 0xFFFFFFFF -#define I2S_SINGLE_DATA_S 0 - -#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x006C) -/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/ -#define I2S_TX_IDLE (BIT(0)) -#define I2S_TX_IDLE_M (BIT(0)) -#define I2S_TX_IDLE_V 0x1 -#define I2S_TX_IDLE_S 0 - -#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x0080) -/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */ -/*description: Version control register*/ -#define I2S_DATE 0x0FFFFFFF -#define I2S_DATE_M ((I2S_DATE_V)<<(I2S_DATE_S)) -#define I2S_DATE_V 0xFFFFFFF -#define I2S_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_I2S_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/i2s_struct.h b/components/soc/esp32h4/include/soc/i2s_struct.h deleted file mode 100644 index fac2c8af11..0000000000 --- a/components/soc/esp32h4/include/soc/i2s_struct.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct i2s_dev_s { - uint32_t reserved_0; - uint32_t reserved_4; - uint32_t reserved_8; - union { - struct { - uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/ - uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/ - uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/ - uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/ - uint32_t reserved4: 28; /*Reserve*/ - }; - uint32_t val; - } int_clr; - uint32_t reserved_1c; - union { - struct { - uint32_t rx_reset: 1; /*Set this bit to reset receiver*/ - uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/ - uint32_t rx_start: 1; /*Set this bit to start receiving data*/ - uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/ - uint32_t reserved4: 1; /*Reserved*/ - uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/ - uint32_t reserved6: 1; - uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ - uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/ - uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/ - uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ - uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/ - uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ - uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ - uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ - uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ - uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/ - uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/ - uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/ - uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/ - uint32_t rx_sinc_dsr_16_en: 1; - uint32_t reserved23: 9; /*Reserve*/ - }; - uint32_t val; - } rx_conf; - union { - struct { - uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/ - uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/ - uint32_t tx_start: 1; /*Set this bit to start transmitting data*/ - uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/ - uint32_t reserved4: 1; /*Reserved*/ - uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/ - uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ - uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ - uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/ - uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ - uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ - uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ - uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ - uint32_t reserved14: 1; - uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ - uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ - uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ - uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/ - uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/ - uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/ - uint32_t reserved21: 3; /*Reserved*/ - uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/ - uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/ - uint32_t reserved28: 4; /*Reserved*/ - }; - uint32_t val; - } tx_conf; - union { - struct { - uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ - uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/ - uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/ - uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/ - uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/ - uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/ - uint32_t reserved30: 2; /*Reserved*/ - }; - uint32_t val; - } rx_conf1; - union { - struct { - uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ - uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/ - uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/ - uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/ - uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/ - uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/ - uint32_t reserved30: 2; /*Reserved*/ - }; - uint32_t val; - } tx_conf1; - union { - struct { - uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/ - uint32_t reserved8: 18; /*Reserved*/ - uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/ - uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ - uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/ - uint32_t reserved30: 2; /*Reserved*/ - }; - uint32_t val; - } rx_clkm_conf; - union { - struct { - uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ - uint32_t reserved8: 18; /*Reserved*/ - uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ - uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/ - uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ - uint32_t reserved30: 2; /*Reserved*/ - }; - uint32_t val; - } tx_clkm_conf; - union { - struct { - uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ - uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ - uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ - uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ - uint32_t reserved28: 4; /*Reserved*/ - }; - uint32_t val; - } rx_clkm_div_conf; - union { - struct { - uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ - uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ - uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ - uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ - uint32_t reserved28: 4; /*Reserved*/ - }; - uint32_t val; - } tx_clkm_div_conf; - union { - struct { - uint32_t tx_pdm_hp_bypass : 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/ - uint32_t tx_pdm_sinc_osr2 : 4; /*I2S TX PDM OSR2 value*/ - uint32_t tx_pdm_prescale : 8; /*I2S TX PDM prescale for sigmadelta*/ - uint32_t tx_pdm_hp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ - uint32_t tx_pdm_lp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ - uint32_t tx_pdm_sinc_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ - uint32_t tx_pdm_sigmadelta_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/ - uint32_t tx_pdm_sigmadelta_dither2 : 1; /*I2S TX PDM sigmadelta dither2 value*/ - uint32_t tx_pdm_sigmadelta_dither : 1; /*I2S TX PDM sigmadelta dither value*/ - uint32_t tx_pdm_dac_2out_en : 1; /*I2S TX PDM dac mode enable*/ - uint32_t tx_pdm_dac_mode_en : 1; /*I2S TX PDM dac 2channel enable*/ - uint32_t pcm2pdm_conv_en : 1; /*I2S TX PDM Converter enable*/ - uint32_t reserved26 : 6; /*Reserved*/ - }; - uint32_t val; - } tx_pcm2pdm_conf; - union { - struct { - uint32_t tx_pdm_fp : 10; /*I2S TX PDM Fp*/ - uint32_t tx_pdm_fs : 10; /*I2S TX PDM Fs*/ - uint32_t tx_iir_hp_mult12_5 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/ - uint32_t tx_iir_hp_mult12_0 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/ - uint32_t reserved26 : 6; /*Reserved*/ - }; - uint32_t val; - } tx_pcm2pdm_conf1; - uint32_t reserved_48; - uint32_t reserved_4c; - union { - struct { - uint32_t rx_tdm_pdm_chan0_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan1_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan2_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan3_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan4_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan5_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan6_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_pdm_chan7_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan8_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan9_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan10_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan11_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan12_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan13_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan14_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_chan15_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/ - uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/ - uint32_t reserved20: 12; /*Reserved*/ - }; - uint32_t val; - } rx_tdm_ctrl; - union { - struct { - uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ - uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/ - uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ - uint32_t reserved21: 11; /*Reserved*/ - }; - uint32_t val; - } tx_tdm_ctrl; - union { - struct { - uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved2: 2; - uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved6: 2; - uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved10: 2; - uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved14: 2; - uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved18: 2; - uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved22: 2; - uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved26: 2; - uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved30: 2; - }; - uint32_t val; - } rx_timing; - union { - struct { - uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved2: 14; /*Reserved*/ - uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved18: 2; - uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved22: 2; - uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved26: 2; - uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ - uint32_t reserved30: 2; - }; - uint32_t val; - } tx_timing; - union { - struct { - uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/ - uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ - uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/ - uint32_t reserved12: 20; /*Reserved*/ - }; - uint32_t val; - } lc_hung_conf; - union { - struct { - uint32_t rx_eof_num:12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ - uint32_t reserved12:20; /*Reserved*/ - }; - uint32_t val; - } rx_eof_num; - uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/ - union { - struct { - uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/ - uint32_t reserved1: 31; /*Reserved*/ - }; - uint32_t val; - } state; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - union { - struct { - uint32_t date: 28; /*Version control register*/ - uint32_t reserved28: 4; /*Reserved*/ - }; - uint32_t val; - } date; -} i2s_dev_t; -extern i2s_dev_t I2S0; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/interrupt_reg.h b/components/soc/esp32h4/include/soc/interrupt_reg.h deleted file mode 100644 index d4a6470275..0000000000 --- a/components/soc/esp32h4/include/soc/interrupt_reg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/interrupt_core0_reg.h" diff --git a/components/soc/esp32h4/include/soc/ledc_reg.h b/components/soc/esp32h4/include/soc/ledc_reg.h deleted file mode 100644 index 728371f1d5..0000000000 --- a/components/soc/esp32h4/include/soc/ledc_reg.h +++ /dev/null @@ -1,1218 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_LEDC_REG_H_ -#define _SOC_LEDC_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) -/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_RESET_LSCH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH0_M (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH0_V 0x1 -#define LEDC_OVF_CNT_RESET_LSCH0_S 16 -/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_LSCH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH0_M (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH0_V 0x1 -#define LEDC_OVF_CNT_EN_LSCH0_S 15 -/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_LSCH0 0x000003FF -#define LEDC_OVF_NUM_LSCH0_M ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S)) -#define LEDC_OVF_NUM_LSCH0_V 0x3FF -#define LEDC_OVF_NUM_LSCH0_S 5 -/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_PARA_UP_LSCH0 (BIT(4)) -#define LEDC_PARA_UP_LSCH0_M (BIT(4)) -#define LEDC_PARA_UP_LSCH0_V 0x1 -#define LEDC_PARA_UP_LSCH0_S 4 -/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_IDLE_LV_LSCH0 (BIT(3)) -#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH0_V 0x1 -#define LEDC_IDLE_LV_LSCH0_S 3 -/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH0_S 2 -/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define LEDC_TIMER_SEL_LSCH0 0x00000003 -#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) -#define LEDC_TIMER_SEL_LSCH0_V 0x3 -#define LEDC_TIMER_SEL_LSCH0_S 0 - -#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) -/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: */ -#define LEDC_HPOINT_LSCH0 0x00003FFF -#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) -#define LEDC_HPOINT_LSCH0_V 0x3FFF -#define LEDC_HPOINT_LSCH0_S 0 - -#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) -/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH0 0x0007FFFF -#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x7FFFF -#define LEDC_DUTY_LSCH0_S 0 - -#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) -/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_START_LSCH0 (BIT(31)) -#define LEDC_DUTY_START_LSCH0_M (BIT(31)) -#define LEDC_DUTY_START_LSCH0_V 0x1 -#define LEDC_DUTY_START_LSCH0_S 31 -/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_DUTY_INC_LSCH0 (BIT(30)) -#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH0_V 0x1 -#define LEDC_DUTY_INC_LSCH0_S 30 -/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_NUM_LSCH0 0x000003FF -#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) -#define LEDC_DUTY_NUM_LSCH0_V 0x3FF -#define LEDC_DUTY_NUM_LSCH0_S 20 -/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) -#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH0_S 10 -/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_SCALE_LSCH0 0x000003FF -#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) -#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH0_S 0 - -#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) -/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH0 0x0007FFFF -#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x7FFFF -#define LEDC_DUTY_LSCH0_S 0 - -#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) -/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_RESET_LSCH1 (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH1_M (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH1_V 0x1 -#define LEDC_OVF_CNT_RESET_LSCH1_S 16 -/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_LSCH1 (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH1_M (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH1_V 0x1 -#define LEDC_OVF_CNT_EN_LSCH1_S 15 -/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_LSCH1 0x000003FF -#define LEDC_OVF_NUM_LSCH1_M ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S)) -#define LEDC_OVF_NUM_LSCH1_V 0x3FF -#define LEDC_OVF_NUM_LSCH1_S 5 -/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_PARA_UP_LSCH1 (BIT(4)) -#define LEDC_PARA_UP_LSCH1_M (BIT(4)) -#define LEDC_PARA_UP_LSCH1_V 0x1 -#define LEDC_PARA_UP_LSCH1_S 4 -/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_IDLE_LV_LSCH1 (BIT(3)) -#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH1_V 0x1 -#define LEDC_IDLE_LV_LSCH1_S 3 -/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH1_S 2 -/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define LEDC_TIMER_SEL_LSCH1 0x00000003 -#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) -#define LEDC_TIMER_SEL_LSCH1_V 0x3 -#define LEDC_TIMER_SEL_LSCH1_S 0 - -#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) -/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: */ -#define LEDC_HPOINT_LSCH1 0x00003FFF -#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) -#define LEDC_HPOINT_LSCH1_V 0x3FFF -#define LEDC_HPOINT_LSCH1_S 0 - -#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) -/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH1 0x0007FFFF -#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x7FFFF -#define LEDC_DUTY_LSCH1_S 0 - -#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) -/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_START_LSCH1 (BIT(31)) -#define LEDC_DUTY_START_LSCH1_M (BIT(31)) -#define LEDC_DUTY_START_LSCH1_V 0x1 -#define LEDC_DUTY_START_LSCH1_S 31 -/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_DUTY_INC_LSCH1 (BIT(30)) -#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH1_V 0x1 -#define LEDC_DUTY_INC_LSCH1_S 30 -/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_NUM_LSCH1 0x000003FF -#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) -#define LEDC_DUTY_NUM_LSCH1_V 0x3FF -#define LEDC_DUTY_NUM_LSCH1_S 20 -/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) -#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH1_S 10 -/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_SCALE_LSCH1 0x000003FF -#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) -#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH1_S 0 - -#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) -/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH1 0x0007FFFF -#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x7FFFF -#define LEDC_DUTY_LSCH1_S 0 - -#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) -/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_RESET_LSCH2 (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH2_M (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH2_V 0x1 -#define LEDC_OVF_CNT_RESET_LSCH2_S 16 -/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_LSCH2 (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH2_M (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH2_V 0x1 -#define LEDC_OVF_CNT_EN_LSCH2_S 15 -/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_LSCH2 0x000003FF -#define LEDC_OVF_NUM_LSCH2_M ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S)) -#define LEDC_OVF_NUM_LSCH2_V 0x3FF -#define LEDC_OVF_NUM_LSCH2_S 5 -/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_PARA_UP_LSCH2 (BIT(4)) -#define LEDC_PARA_UP_LSCH2_M (BIT(4)) -#define LEDC_PARA_UP_LSCH2_V 0x1 -#define LEDC_PARA_UP_LSCH2_S 4 -/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_IDLE_LV_LSCH2 (BIT(3)) -#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH2_V 0x1 -#define LEDC_IDLE_LV_LSCH2_S 3 -/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH2_S 2 -/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define LEDC_TIMER_SEL_LSCH2 0x00000003 -#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) -#define LEDC_TIMER_SEL_LSCH2_V 0x3 -#define LEDC_TIMER_SEL_LSCH2_S 0 - -#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) -/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: */ -#define LEDC_HPOINT_LSCH2 0x00003FFF -#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) -#define LEDC_HPOINT_LSCH2_V 0x3FFF -#define LEDC_HPOINT_LSCH2_S 0 - -#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) -/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH2 0x0007FFFF -#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x7FFFF -#define LEDC_DUTY_LSCH2_S 0 - -#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) -/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_START_LSCH2 (BIT(31)) -#define LEDC_DUTY_START_LSCH2_M (BIT(31)) -#define LEDC_DUTY_START_LSCH2_V 0x1 -#define LEDC_DUTY_START_LSCH2_S 31 -/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_DUTY_INC_LSCH2 (BIT(30)) -#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH2_V 0x1 -#define LEDC_DUTY_INC_LSCH2_S 30 -/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_NUM_LSCH2 0x000003FF -#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) -#define LEDC_DUTY_NUM_LSCH2_V 0x3FF -#define LEDC_DUTY_NUM_LSCH2_S 20 -/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) -#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH2_S 10 -/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_SCALE_LSCH2 0x000003FF -#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) -#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH2_S 0 - -#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) -/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH2 0x0007FFFF -#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x7FFFF -#define LEDC_DUTY_LSCH2_S 0 - -#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) -/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_RESET_LSCH3 (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH3_M (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH3_V 0x1 -#define LEDC_OVF_CNT_RESET_LSCH3_S 16 -/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_LSCH3 (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH3_M (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH3_V 0x1 -#define LEDC_OVF_CNT_EN_LSCH3_S 15 -/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_LSCH3 0x000003FF -#define LEDC_OVF_NUM_LSCH3_M ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S)) -#define LEDC_OVF_NUM_LSCH3_V 0x3FF -#define LEDC_OVF_NUM_LSCH3_S 5 -/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_PARA_UP_LSCH3 (BIT(4)) -#define LEDC_PARA_UP_LSCH3_M (BIT(4)) -#define LEDC_PARA_UP_LSCH3_V 0x1 -#define LEDC_PARA_UP_LSCH3_S 4 -/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_IDLE_LV_LSCH3 (BIT(3)) -#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH3_V 0x1 -#define LEDC_IDLE_LV_LSCH3_S 3 -/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH3_S 2 -/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define LEDC_TIMER_SEL_LSCH3 0x00000003 -#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) -#define LEDC_TIMER_SEL_LSCH3_V 0x3 -#define LEDC_TIMER_SEL_LSCH3_S 0 - -#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) -/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: */ -#define LEDC_HPOINT_LSCH3 0x00003FFF -#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) -#define LEDC_HPOINT_LSCH3_V 0x3FFF -#define LEDC_HPOINT_LSCH3_S 0 - -#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) -/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH3 0x0007FFFF -#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x7FFFF -#define LEDC_DUTY_LSCH3_S 0 - -#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) -/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_START_LSCH3 (BIT(31)) -#define LEDC_DUTY_START_LSCH3_M (BIT(31)) -#define LEDC_DUTY_START_LSCH3_V 0x1 -#define LEDC_DUTY_START_LSCH3_S 31 -/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_DUTY_INC_LSCH3 (BIT(30)) -#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH3_V 0x1 -#define LEDC_DUTY_INC_LSCH3_S 30 -/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_NUM_LSCH3 0x000003FF -#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) -#define LEDC_DUTY_NUM_LSCH3_V 0x3FF -#define LEDC_DUTY_NUM_LSCH3_S 20 -/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) -#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH3_S 10 -/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_SCALE_LSCH3 0x000003FF -#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) -#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH3_S 0 - -#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) -/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH3 0x0007FFFF -#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x7FFFF -#define LEDC_DUTY_LSCH3_S 0 - -#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) -/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_RESET_LSCH4 (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH4_M (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH4_V 0x1 -#define LEDC_OVF_CNT_RESET_LSCH4_S 16 -/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_LSCH4 (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH4_M (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH4_V 0x1 -#define LEDC_OVF_CNT_EN_LSCH4_S 15 -/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_LSCH4 0x000003FF -#define LEDC_OVF_NUM_LSCH4_M ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S)) -#define LEDC_OVF_NUM_LSCH4_V 0x3FF -#define LEDC_OVF_NUM_LSCH4_S 5 -/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_PARA_UP_LSCH4 (BIT(4)) -#define LEDC_PARA_UP_LSCH4_M (BIT(4)) -#define LEDC_PARA_UP_LSCH4_V 0x1 -#define LEDC_PARA_UP_LSCH4_S 4 -/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_IDLE_LV_LSCH4 (BIT(3)) -#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH4_V 0x1 -#define LEDC_IDLE_LV_LSCH4_S 3 -/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH4_S 2 -/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define LEDC_TIMER_SEL_LSCH4 0x00000003 -#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) -#define LEDC_TIMER_SEL_LSCH4_V 0x3 -#define LEDC_TIMER_SEL_LSCH4_S 0 - -#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) -/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: */ -#define LEDC_HPOINT_LSCH4 0x00003FFF -#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) -#define LEDC_HPOINT_LSCH4_V 0x3FFF -#define LEDC_HPOINT_LSCH4_S 0 - -#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) -/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH4 0x0007FFFF -#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x7FFFF -#define LEDC_DUTY_LSCH4_S 0 - -#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) -/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_START_LSCH4 (BIT(31)) -#define LEDC_DUTY_START_LSCH4_M (BIT(31)) -#define LEDC_DUTY_START_LSCH4_V 0x1 -#define LEDC_DUTY_START_LSCH4_S 31 -/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_DUTY_INC_LSCH4 (BIT(30)) -#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH4_V 0x1 -#define LEDC_DUTY_INC_LSCH4_S 30 -/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_NUM_LSCH4 0x000003FF -#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) -#define LEDC_DUTY_NUM_LSCH4_V 0x3FF -#define LEDC_DUTY_NUM_LSCH4_S 20 -/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) -#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH4_S 10 -/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_SCALE_LSCH4 0x000003FF -#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) -#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH4_S 0 - -#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) -/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH4 0x0007FFFF -#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x7FFFF -#define LEDC_DUTY_LSCH4_S 0 - -#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) -/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_RESET_LSCH5 (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH5_M (BIT(16)) -#define LEDC_OVF_CNT_RESET_LSCH5_V 0x1 -#define LEDC_OVF_CNT_RESET_LSCH5_S 16 -/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_LSCH5 (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH5_M (BIT(15)) -#define LEDC_OVF_CNT_EN_LSCH5_V 0x1 -#define LEDC_OVF_CNT_EN_LSCH5_S 15 -/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_LSCH5 0x000003FF -#define LEDC_OVF_NUM_LSCH5_M ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S)) -#define LEDC_OVF_NUM_LSCH5_V 0x3FF -#define LEDC_OVF_NUM_LSCH5_S 5 -/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_PARA_UP_LSCH5 (BIT(4)) -#define LEDC_PARA_UP_LSCH5_M (BIT(4)) -#define LEDC_PARA_UP_LSCH5_V 0x1 -#define LEDC_PARA_UP_LSCH5_S 4 -/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_IDLE_LV_LSCH5 (BIT(3)) -#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH5_V 0x1 -#define LEDC_IDLE_LV_LSCH5_S 3 -/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH5_S 2 -/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define LEDC_TIMER_SEL_LSCH5 0x00000003 -#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) -#define LEDC_TIMER_SEL_LSCH5_V 0x3 -#define LEDC_TIMER_SEL_LSCH5_S 0 - -#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) -/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: */ -#define LEDC_HPOINT_LSCH5 0x00003FFF -#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) -#define LEDC_HPOINT_LSCH5_V 0x3FFF -#define LEDC_HPOINT_LSCH5_S 0 - -#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) -/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH5 0x0007FFFF -#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x7FFFF -#define LEDC_DUTY_LSCH5_S 0 - -#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) -/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_START_LSCH5 (BIT(31)) -#define LEDC_DUTY_START_LSCH5_M (BIT(31)) -#define LEDC_DUTY_START_LSCH5_V 0x1 -#define LEDC_DUTY_START_LSCH5_S 31 -/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_DUTY_INC_LSCH5 (BIT(30)) -#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH5_V 0x1 -#define LEDC_DUTY_INC_LSCH5_S 30 -/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_NUM_LSCH5 0x000003FF -#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) -#define LEDC_DUTY_NUM_LSCH5_V 0x3FF -#define LEDC_DUTY_NUM_LSCH5_S 20 -/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) -#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH5_S 10 -/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define LEDC_DUTY_SCALE_LSCH5 0x000003FF -#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) -#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH5_S 0 - -#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) -/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ -/*description: */ -#define LEDC_DUTY_LSCH5 0x0007FFFF -#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x7FFFF -#define LEDC_DUTY_LSCH5_S 0 - -#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x00a0) -/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_LSTIMER0_PARA_UP (BIT(25)) -#define LEDC_LSTIMER0_PARA_UP_M (BIT(25)) -#define LEDC_LSTIMER0_PARA_UP_V 0x1 -#define LEDC_LSTIMER0_PARA_UP_S 25 -/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_TICK_SEL_LSTIMER0 (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER0_M (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER0_V 0x1 -#define LEDC_TICK_SEL_LSTIMER0_S 24 -/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_LSTIMER0_RST (BIT(23)) -#define LEDC_LSTIMER0_RST_M (BIT(23)) -#define LEDC_LSTIMER0_RST_V 0x1 -#define LEDC_LSTIMER0_RST_S 23 -/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER0_PAUSE (BIT(22)) -#define LEDC_LSTIMER0_PAUSE_M (BIT(22)) -#define LEDC_LSTIMER0_PAUSE_V 0x1 -#define LEDC_LSTIMER0_PAUSE_S 22 -/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_LSTIMER0 0x0003FFFF -#define LEDC_CLK_DIV_LSTIMER0_M ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S)) -#define LEDC_CLK_DIV_LSTIMER0_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER0_S 4 -/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: */ -#define LEDC_LSTIMER0_DUTY_RES 0x0000000F -#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S)) -#define LEDC_LSTIMER0_DUTY_RES_V 0xF -#define LEDC_LSTIMER0_DUTY_RES_S 0 - -#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x00a4) -/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: */ -#define LEDC_LSTIMER0_CNT 0x00003FFF -#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) -#define LEDC_LSTIMER0_CNT_V 0x3FFF -#define LEDC_LSTIMER0_CNT_S 0 - -#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x00a8) -/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_LSTIMER1_PARA_UP (BIT(25)) -#define LEDC_LSTIMER1_PARA_UP_M (BIT(25)) -#define LEDC_LSTIMER1_PARA_UP_V 0x1 -#define LEDC_LSTIMER1_PARA_UP_S 25 -/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_TICK_SEL_LSTIMER1 (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER1_M (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER1_V 0x1 -#define LEDC_TICK_SEL_LSTIMER1_S 24 -/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_LSTIMER1_RST (BIT(23)) -#define LEDC_LSTIMER1_RST_M (BIT(23)) -#define LEDC_LSTIMER1_RST_V 0x1 -#define LEDC_LSTIMER1_RST_S 23 -/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER1_PAUSE (BIT(22)) -#define LEDC_LSTIMER1_PAUSE_M (BIT(22)) -#define LEDC_LSTIMER1_PAUSE_V 0x1 -#define LEDC_LSTIMER1_PAUSE_S 22 -/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_LSTIMER1 0x0003FFFF -#define LEDC_CLK_DIV_LSTIMER1_M ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S)) -#define LEDC_CLK_DIV_LSTIMER1_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER1_S 4 -/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: */ -#define LEDC_LSTIMER1_DUTY_RES 0x0000000F -#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S)) -#define LEDC_LSTIMER1_DUTY_RES_V 0xF -#define LEDC_LSTIMER1_DUTY_RES_S 0 - -#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x00aC) -/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: */ -#define LEDC_LSTIMER1_CNT 0x00003FFF -#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) -#define LEDC_LSTIMER1_CNT_V 0x3FFF -#define LEDC_LSTIMER1_CNT_S 0 - -#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x00b0) -/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_LSTIMER2_PARA_UP (BIT(25)) -#define LEDC_LSTIMER2_PARA_UP_M (BIT(25)) -#define LEDC_LSTIMER2_PARA_UP_V 0x1 -#define LEDC_LSTIMER2_PARA_UP_S 25 -/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_TICK_SEL_LSTIMER2 (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER2_M (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER2_V 0x1 -#define LEDC_TICK_SEL_LSTIMER2_S 24 -/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_LSTIMER2_RST (BIT(23)) -#define LEDC_LSTIMER2_RST_M (BIT(23)) -#define LEDC_LSTIMER2_RST_V 0x1 -#define LEDC_LSTIMER2_RST_S 23 -/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER2_PAUSE (BIT(22)) -#define LEDC_LSTIMER2_PAUSE_M (BIT(22)) -#define LEDC_LSTIMER2_PAUSE_V 0x1 -#define LEDC_LSTIMER2_PAUSE_S 22 -/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_LSTIMER2 0x0003FFFF -#define LEDC_CLK_DIV_LSTIMER2_M ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S)) -#define LEDC_CLK_DIV_LSTIMER2_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER2_S 4 -/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: */ -#define LEDC_LSTIMER2_DUTY_RES 0x0000000F -#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S)) -#define LEDC_LSTIMER2_DUTY_RES_V 0xF -#define LEDC_LSTIMER2_DUTY_RES_S 0 - -#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x00b4) -/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: */ -#define LEDC_LSTIMER2_CNT 0x00003FFF -#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) -#define LEDC_LSTIMER2_CNT_V 0x3FFF -#define LEDC_LSTIMER2_CNT_S 0 - -#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x00b8) -/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_LSTIMER3_PARA_UP (BIT(25)) -#define LEDC_LSTIMER3_PARA_UP_M (BIT(25)) -#define LEDC_LSTIMER3_PARA_UP_V 0x1 -#define LEDC_LSTIMER3_PARA_UP_S 25 -/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_TICK_SEL_LSTIMER3 (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER3_M (BIT(24)) -#define LEDC_TICK_SEL_LSTIMER3_V 0x1 -#define LEDC_TICK_SEL_LSTIMER3_S 24 -/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: */ -#define LEDC_LSTIMER3_RST (BIT(23)) -#define LEDC_LSTIMER3_RST_M (BIT(23)) -#define LEDC_LSTIMER3_RST_V 0x1 -#define LEDC_LSTIMER3_RST_S 23 -/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER3_PAUSE (BIT(22)) -#define LEDC_LSTIMER3_PAUSE_M (BIT(22)) -#define LEDC_LSTIMER3_PAUSE_V 0x1 -#define LEDC_LSTIMER3_PAUSE_S 22 -/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_LSTIMER3 0x0003FFFF -#define LEDC_CLK_DIV_LSTIMER3_M ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S)) -#define LEDC_CLK_DIV_LSTIMER3_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER3_S 4 -/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: */ -#define LEDC_LSTIMER3_DUTY_RES 0x0000000F -#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S)) -#define LEDC_LSTIMER3_DUTY_RES_V 0xF -#define LEDC_LSTIMER3_DUTY_RES_S 0 - -#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x00BC) -/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: */ -#define LEDC_LSTIMER3_CNT 0x00003FFF -#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) -#define LEDC_LSTIMER3_CNT_V 0x3FFF -#define LEDC_LSTIMER3_CNT_S 0 - -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x00C0) -/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 15 -/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 14 -/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 13 -/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 12 -/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 11 -/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 10 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 9 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 8 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 7 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 6 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 5 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 4 -/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_RAW_S 3 -/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_RAW_S 2 -/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_RAW_S 1 -/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_RAW_S 0 - -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x00c4) -/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_ST_S 15 -/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_ST_S 14 -/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_ST_S 13 -/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_ST_S 12 -/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_ST_S 11 -/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_ST_S 10 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 9 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 8 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 7 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 6 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 5 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 4 -/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ST_S 3 -/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ST_S 2 -/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ST_S 1 -/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ST_S 0 - -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xC8) -/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 15 -/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 14 -/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 13 -/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 12 -/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 11 -/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 10 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 9 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 8 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 7 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 6 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 5 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 4 -/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ENA_S 3 -/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ENA_S 2 -/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ENA_S 1 -/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ENA_S 0 - -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xCC) -/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 15 -/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 14 -/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 13 -/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 12 -/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 11 -/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 10 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: reg_duty_chng_end_lsch5_int_clr..*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 8 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(7)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 7 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(6)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 6 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(5)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 5 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(4)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 4 -/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(3)) -#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_CLR_S 3 -/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(2)) -#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_CLR_S 2 -/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(1)) -#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_CLR_S 1 -/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(0)) -#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_CLR_S 0 - -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0) -/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (BIT(31)) -#define LEDC_CLK_EN_V 0x1 -#define LEDC_CLK_EN_S 31 -/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define LEDC_APB_CLK_SEL 0x00000003 -#define LEDC_APB_CLK_SEL_M ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S)) -#define LEDC_APB_CLK_SEL_V 0x3 -#define LEDC_APB_CLK_SEL_S 0 - -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC) -/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */ -/*description: */ -#define LEDC_DATE 0xFFFFFFFF -#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) -#define LEDC_DATE_V 0xFFFFFFFF -#define LEDC_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_LEDC_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/ledc_struct.h b/components/soc/esp32h4/include/soc/ledc_struct.h deleted file mode 100644 index 503c7dd77a..0000000000 --- a/components/soc/esp32h4/include/soc/ledc_struct.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_LEDC_STRUCT_H_ -#define _SOC_LEDC_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct ledc_dev_s { - struct { - struct { - union { - struct { - uint32_t timer_sel: 2; - uint32_t sig_out_en: 1; - uint32_t idle_lv: 1; - uint32_t low_speed_update: 1; - uint32_t ovf_num: 10; - uint32_t ovf_cnt_en: 1; - uint32_t ovf_cnt_rst: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t hpoint: 14; - uint32_t reserved14: 18; - }; - uint32_t val; - } hpoint; - union { - struct { - uint32_t duty: 19; - uint32_t reserved19:13; - }; - uint32_t val; - } duty; - union { - struct { - uint32_t duty_scale: 10; - uint32_t duty_cycle: 10; - uint32_t duty_num: 10; - uint32_t duty_inc: 1; - uint32_t duty_start: 1; - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t duty_read: 19; - uint32_t reserved19: 13; - }; - uint32_t val; - } duty_rd; - } channel[6]; - } channel_group[1]; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - struct { - struct { - union { - struct { - uint32_t duty_resolution: 4; - uint32_t clock_divider: 18; - uint32_t pause: 1; - uint32_t rst: 1; - uint32_t reserved24: 1; - uint32_t low_speed_update: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t timer_cnt: 14; - uint32_t reserved14: 18; - }; - uint32_t val; - } value; - } timer[4]; - } timer_group[1]; - union { - struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t apb_clk_sel: 2; - uint32_t reserved2: 29; - uint32_t clk_en: 1; - }; - uint32_t val; - } conf; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t date: 32; - }; - uint32_t val; - } date; -} ledc_dev_t; -extern ledc_dev_t LEDC; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/soc/mmu.h b/components/soc/esp32h4/include/soc/mmu.h deleted file mode 100644 index 59b8820033..0000000000 --- a/components/soc/esp32h4/include/soc/mmu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/ext_mem_defs.h" -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Defined for flash mmap */ -#define SOC_MMU_REGIONS_COUNT 1 -#define SOC_MMU_PAGES_PER_REGION 128 -#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) -#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) -#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) -#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) -#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK -#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash -#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW -#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START -#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) -#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/nrx_reg.h b/components/soc/esp32h4/include/soc/nrx_reg.h deleted file mode 100644 index 2e5b56fdb8..0000000000 --- a/components/soc/esp32h4/include/soc/nrx_reg.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/soc.h" - -/* Some of the WiFi RX control registers. - * PU/PD fields defined here are used in sleep related functions. - */ - -#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) -#define NRX_CHAN_EST_FORCE_PU (BIT(7)) -#define NRX_CHAN_EST_FORCE_PU_M (BIT(7)) -#define NRX_CHAN_EST_FORCE_PU_V 1 -#define NRX_CHAN_EST_FORCE_PU_S 7 -#define NRX_CHAN_EST_FORCE_PD (BIT(6)) -#define NRX_CHAN_EST_FORCE_PD_M (BIT(6)) -#define NRX_CHAN_EST_FORCE_PD_V 1 -#define NRX_CHAN_EST_FORCE_PD_S 6 -#define NRX_RX_ROT_FORCE_PU (BIT(5)) -#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) -#define NRX_RX_ROT_FORCE_PU_V 1 -#define NRX_RX_ROT_FORCE_PU_S 5 -#define NRX_RX_ROT_FORCE_PD (BIT(4)) -#define NRX_RX_ROT_FORCE_PD_M (BIT(4)) -#define NRX_RX_ROT_FORCE_PD_V 1 -#define NRX_RX_ROT_FORCE_PD_S 4 -#define NRX_VIT_FORCE_PU (BIT(3)) -#define NRX_VIT_FORCE_PU_M (BIT(3)) -#define NRX_VIT_FORCE_PU_V 1 -#define NRX_VIT_FORCE_PU_S 3 -#define NRX_VIT_FORCE_PD (BIT(2)) -#define NRX_VIT_FORCE_PD_M (BIT(2)) -#define NRX_VIT_FORCE_PD_V 1 -#define NRX_VIT_FORCE_PD_S 2 -#define NRX_DEMAP_FORCE_PU (BIT(1)) -#define NRX_DEMAP_FORCE_PU_M (BIT(1)) -#define NRX_DEMAP_FORCE_PU_V 1 -#define NRX_DEMAP_FORCE_PU_S 1 -#define NRX_DEMAP_FORCE_PD (BIT(0)) -#define NRX_DEMAP_FORCE_PD_M (BIT(0)) -#define NRX_DEMAP_FORCE_PD_V 1 -#define NRX_DEMAP_FORCE_PD_S 0 diff --git a/components/soc/esp32h4/include/soc/periph_defs.h b/components/soc/esp32h4/include/soc/periph_defs.h deleted file mode 100644 index 352a320924..0000000000 --- a/components/soc/esp32h4/include/soc/periph_defs.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PERIPH_LEDC_MODULE = 0, - PERIPH_UART0_MODULE, - PERIPH_UART1_MODULE, - PERIPH_USB_DEVICE_MODULE, - PERIPH_I2C0_MODULE, - PERIPH_I2S1_MODULE, - PERIPH_TIMG0_MODULE, - PERIPH_TIMG1_MODULE, - PERIPH_UHCI0_MODULE, - PERIPH_RMT_MODULE, - PERIPH_SPI_MODULE, //SPI1 - PERIPH_SPI2_MODULE, //SPI2 - PERIPH_TWAI_MODULE, - PERIPH_RNG_MODULE, - PERIPH_WIFI_MODULE, - PERIPH_BT_MODULE, - PERIPH_WIFI_BT_COMMON_MODULE, - PERIPH_BT_BASEBAND_MODULE, - PERIPH_BT_LC_MODULE, - PERIPH_RSA_MODULE, - PERIPH_AES_MODULE, - PERIPH_SHA_MODULE, - PERIPH_ECC_MODULE, - PERIPH_HMAC_MODULE, - PERIPH_DS_MODULE, - PERIPH_GDMA_MODULE, - PERIPH_SYSTIMER_MODULE, - PERIPH_SARADC_MODULE, - PERIPH_TEMPSENSOR_MODULE, - PERIPH_ETM_MODULE, - PERIPH_MODEM_RPA_MODULE, - PERIPH_MODULE_MAX -} periph_module_t; - -typedef enum { - ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ - ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ - ETS_WIFI_PWR_INTR_SOURCE, /**< */ - ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ - ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ - ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ - ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ - ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ - ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ - ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ - ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ - ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ - ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ - ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ - ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/ - ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ - ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ - ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ - ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ - ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ - ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ - ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ - ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ - ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_TWAI_INTR_SOURCE, /**< interrupt of twai, level*/ - ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USJ, level*/ - ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ - ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ - ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ - ETS_TIMER1_INTR_SOURCE, - ETS_TIMER2_INTR_SOURCE, - ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/ - ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/ - ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/ - ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ - ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ - ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ - ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ - ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ - ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ - ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ - ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ - ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ - ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/ - ETS_DMA_CH1_INTR_SOURCE, /**< interrupt of general DMA channel 1, LEVEL*/ - ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/ - ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ - ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ - ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ - ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ - ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ - ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ - ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ - ETS_DMA_APBPERI_PMS_INTR_SOURCE, - ETS_CORE0_IRAM0_PMS_INTR_SOURCE, - ETS_CORE0_DRAM0_PMS_INTR_SOURCE, - ETS_CORE0_PIF_PMS_INTR_SOURCE, - ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE, - ETS_BAK_PMS_VIOLATE_INTR_SOURCE, - ETS_CACHE_CORE0_ACS_INTR_SOURCE, - ETS_TG3_TO_INTR_SOURCE, - ETS_TG3_WDT_INTR_SOURCE, - ETS_BLE_SEC_INTR_SOURCE, - ETS_IEEE802154MAC_INTR_SOURCE, - ETS_IEEE802154BB_INTR_SOURCE, - ETS_COEX_INTR_SOURCE, - ETS_RTC_BLE_INTR_SOURCE, - ETS_MAX_INTR_SOURCE, -} periph_interrput_t; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/reg_base.h b/components/soc/esp32h4/include/soc/reg_base.h deleted file mode 100644 index fc83c6d305..0000000000 --- a/components/soc/esp32h4/include/soc/reg_base.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 -#define DR_REG_MMU_TABLE 0x600c5000 - -#define DR_REG_ITAG_TABLE 0x600c6000 -#define DR_REG_DTAG_TABLE 0x600c8000 -#define DR_REG_ECC_MULT_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_GDMA_BASE 0x6003f000 - -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_FRC_TIMER_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 -#define DR_REG_HINF_BASE 0x6002B000 -#define DR_REG_UHCI1_BASE 0x6000C000 -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_BT_BASE 0x60011000 -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 -#define DR_REG_SLCHOST_BASE 0x60019000 -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_SLC_BASE 0x6002D000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x6001A000 -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 -#define DR_REG_PWM_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 -#define DR_REG_PWM2_BASE 0x6002F000 -#define DR_REG_PWM3_BASE 0x60030000 -#define DR_REG_SPI4_BASE 0x60037000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 -#define DR_REG_AES_XTS_BASE 0x600CC000 -#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000 -#define DR_REG_CLKRST_BASE 0x6004B000 diff --git a/components/soc/esp32h4/include/soc/regi2c_bbpll.h b/components/soc/esp32h4/include/soc/regi2c_bbpll.h deleted file mode 100644 index 56e31cd6b5..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_bbpll.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file regi2c_bbpll.h - * @brief Register definitions for digital PLL (BBPLL) - * - * This file lists register fields of BBPLL, located on an internal configuration - * bus. These definitions are used via macros defined in regi2c_ctrl.h, by - * rtc_clk_cpu_freq_set function in rtc_clk.c. - */ - -#define I2C_BBPLL 0x66 -#define I2C_BBPLL_HOSTID 0 - -#define I2C_BBPLL_IR_CAL_DELAY 0 -#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 -#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 - -#define I2C_BBPLL_IR_CAL_CK_DIV 0 -#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 -#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 - -#define I2C_BBPLL_IR_CAL_EXT_CAP 1 -#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 -#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 - -#define I2C_BBPLL_IR_CAL_ENX_CAP 1 -#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 -#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 - -#define I2C_BBPLL_IR_CAL_RSTB 1 -#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 -#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 - -#define I2C_BBPLL_IR_CAL_START 1 -#define I2C_BBPLL_IR_CAL_START_MSB 6 -#define I2C_BBPLL_IR_CAL_START_LSB 6 - -#define I2C_BBPLL_IR_CAL_UNSTOP 1 -#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 -#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 - -#define I2C_BBPLL_OC_REF_DIV 2 -#define I2C_BBPLL_OC_REF_DIV_MSB 3 -#define I2C_BBPLL_OC_REF_DIV_LSB 0 - -#define I2C_BBPLL_OC_DIV 3 -#define I2C_BBPLL_OC_DIV_MSB 5 -#define I2C_BBPLL_OC_DIV_LSB 0 - -#define I2C_BBPLL_OC_CHGP_DCUR 4 -#define I2C_BBPLL_OC_CHGP_DCUR_MSB 2 -#define I2C_BBPLL_OC_CHGP_DCUR_LSB 0 - -#define I2C_BBPLL_OC_BUFF_DCUR 4 -#define I2C_BBPLL_OC_BUFF_DCUR_MSB 5 -#define I2C_BBPLL_OC_BUFF_DCUR_LSB 3 - -#define I2C_BBPLL_OC_TSCHGP 4 -#define I2C_BBPLL_OC_TSCHGP_MSB 6 -#define I2C_BBPLL_OC_TSCHGP_LSB 6 - -#define I2C_BBPLL_OC_ENB_FCAL 4 -#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 -#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 - -#define I2C_BBPLL_OC_LPF_DR 5 -#define I2C_BBPLL_OC_LPF_DR_MSB 1 -#define I2C_BBPLL_OC_LPF_DR_LSB 0 - -#define I2C_BBPLL_OC_VCO_DCUR 5 -#define I2C_BBPLL_OC_VCO_DCUR_MSB 3 -#define I2C_BBPLL_OC_VCO_DCUR_LSB 2 - -#define I2C_BBPLL_OC_DHREF_SEL 5 -#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 -#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 - -#define I2C_BBPLL_OC_DLREF_SEL 5 -#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 -#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 - -#define I2C_BBPLL_OR_CAL_CAP 8 -#define I2C_BBPLL_OR_CAL_CAP_MSB 3 -#define I2C_BBPLL_OR_CAL_CAP_LSB 0 - -#define I2C_BBPLL_OR_CAL_UDF 8 -#define I2C_BBPLL_OR_CAL_UDF_MSB 4 -#define I2C_BBPLL_OR_CAL_UDF_LSB 4 - -#define I2C_BBPLL_OR_CAL_OVF 8 -#define I2C_BBPLL_OR_CAL_OVF_MSB 5 -#define I2C_BBPLL_OR_CAL_OVF_LSB 5 - -#define I2C_BBPLL_OR_CAL_END 8 -#define I2C_BBPLL_OR_CAL_END_MSB 6 -#define I2C_BBPLL_OR_CAL_END_LSB 6 - -#define I2C_BBPLL_OR_LOCK 8 -#define I2C_BBPLL_OR_LOCK_MSB 7 -#define I2C_BBPLL_OR_LOCK_LSB 7 - -#define I2C_BBPLL_DTEST 10 -#define I2C_BBPLL_DTEST_MSB 1 -#define I2C_BBPLL_DTEST_LSB 0 - -#define I2C_BBPLL_ENT_PLL 10 -#define I2C_BBPLL_ENT_PLL_MSB 2 -#define I2C_BBPLL_ENT_PLL_LSB 2 - -#define I2C_BBPLL_DIV_CPU 10 -#define I2C_BBPLL_DIV_CPU_MSB 3 -#define I2C_BBPLL_DIV_CPU_LSB 3 diff --git a/components/soc/esp32h4/include/soc/regi2c_bias.h b/components/soc/esp32h4/include/soc/regi2c_bias.h deleted file mode 100644 index 2d6b73a45e..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_bias.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file regi2c_bias.h - * @brief Register definitions for bias - * - * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by - * bootloader_hardware_init function in bootloader_esp32c3.c. - */ - -#define I2C_BIAS 0x6a -#define I2C_BIAS_HOSTID 0 - -#define I2C_BIAS_DREG_1P6 0 -#define I2C_BIAS_DREG_1P6_MSB 3 -#define I2C_BIAS_DREG_1P6_LSB 0 - -#define I2C_BIAS_DREG_0P8 0 -#define I2C_BIAS_DREG_0P8_MSB 7 -#define I2C_BIAS_DREG_0P8_LSB 4 - -#define I2C_BIAS_DREG_1P1_PVT 1 -#define I2C_BIAS_DREG_1P1_PVT_MSB 3 -#define I2C_BIAS_DREG_1P1_PVT_LSB 0 - -#define I2C_BIAS_DREG_1P2 1 -#define I2C_BIAS_DREG_1P2_MSB 7 -#define I2C_BIAS_DREG_1P2_LSB 4 - -#define I2C_BIAS_ENT_CPREG 2 -#define I2C_BIAS_ENT_CPREG_MSB 0 -#define I2C_BIAS_ENT_CPREG_LSB 0 - -#define I2C_BIAS_ENT_CGM 2 -#define I2C_BIAS_ENT_CGM_MSB 1 -#define I2C_BIAS_ENT_CGM_LSB 1 - -#define I2C_BIAS_CGM_BIAS 2 -#define I2C_BIAS_CGM_BIAS_MSB 3 -#define I2C_BIAS_CGM_BIAS_LSB 2 - -#define I2C_BIAS_DREF_IGM 2 -#define I2C_BIAS_DREF_IGM_MSB 4 -#define I2C_BIAS_DREF_IGM_LSB 4 - -#define I2C_BIAS_RC_DVREF 2 -#define I2C_BIAS_RC_DVREF_MSB 6 -#define I2C_BIAS_RC_DVREF_LSB 5 - -#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP 2 -#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_MSB 7 -#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_LSB 7 - -#define I2C_BIAS_RC_ENX 3 -#define I2C_BIAS_RC_ENX_MSB 0 -#define I2C_BIAS_RC_ENX_LSB 0 - -#define I2C_BIAS_RC_START 3 -#define I2C_BIAS_RC_START_MSB 1 -#define I2C_BIAS_RC_START_LSB 1 - -#define I2C_BIAS_RC_DCAP_EXT 3 -#define I2C_BIAS_RC_DCAP_EXT_MSB 7 -#define I2C_BIAS_RC_DCAP_EXT_LSB 2 - -#define I2C_BIAS_XPD_RC 4 -#define I2C_BIAS_XPD_RC_MSB 0 -#define I2C_BIAS_XPD_RC_LSB 0 - -#define I2C_BIAS_ENT_CONSTI 4 -#define I2C_BIAS_ENT_CONSTI_MSB 1 -#define I2C_BIAS_ENT_CONSTI_LSB 1 - -#define I2C_BIAS_XPD_ICX 4 -#define I2C_BIAS_XPD_ICX_MSB 2 -#define I2C_BIAS_XPD_ICX_LSB 2 - -#define I2C_BIAS_RC_RSTB 4 -#define I2C_BIAS_RC_RSTB_MSB 3 -#define I2C_BIAS_RC_RSTB_LSB 3 - -#define I2C_BIAS_RC_DIV 4 -#define I2C_BIAS_RC_DIV_MSB 7 -#define I2C_BIAS_RC_DIV_LSB 4 - -#define I2C_BIAS_RC_CAP 5 -#define I2C_BIAS_RC_CAP_MSB 5 -#define I2C_BIAS_RC_CAP_LSB 0 - -#define I2C_BIAS_RC_UD 5 -#define I2C_BIAS_RC_UD_MSB 6 -#define I2C_BIAS_RC_UD_LSB 6 - -#define I2C_BIAS_RC_LOCKB 5 -#define I2C_BIAS_RC_LOCKB_MSB 7 -#define I2C_BIAS_RC_LOCKB_LSB 7 - -#define I2C_BIAS_RC_CHG_COUNT 6 -#define I2C_BIAS_RC_CHG_COUNT_MSB 4 -#define I2C_BIAS_RC_CHG_COUNT_LSB 0 - -#define I2C_BIAS_XPD_CPREG 7 -#define I2C_BIAS_XPD_CPREG_MSB 0 -#define I2C_BIAS_XPD_CPREG_LSB 0 - -#define I2C_BIAS_XPD_CGM 7 -#define I2C_BIAS_XPD_CGM_MSB 1 -#define I2C_BIAS_XPD_CGM_LSB 1 - -#define I2C_BIAS_DTEST 7 -#define I2C_BIAS_DTEST_MSB 3 -#define I2C_BIAS_DTEST_LSB 2 - -#define I2C_BIAS_DRES12K 7 -#define I2C_BIAS_DRES12K_MSB 7 -#define I2C_BIAS_DRES12K_LSB 4 diff --git a/components/soc/esp32h4/include/soc/regi2c_brownout.h b/components/soc/esp32h4/include/soc/regi2c_brownout.h deleted file mode 100644 index 76c943b204..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_brownout.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file regi2c_brownout.h - * @brief Register definitions for brownout detector - * - * This file lists register fields of the brownout detector, located on an internal configuration - * bus. These definitions are used via macros defined in regi2c_ctrl.h. - */ - -#define I2C_BOD 0x61 -#define I2C_BOD_HOSTID 0 - -#define I2C_BOD_THRESHOLD 0x5 -#define I2C_BOD_THRESHOLD_MSB 2 -#define I2C_BOD_THRESHOLD_LSB 0 diff --git a/components/soc/esp32h4/include/soc/regi2c_defs.h b/components/soc/esp32h4/include/soc/regi2c_defs.h deleted file mode 100644 index 3199b89e38..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_defs.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -#include "esp_bit_defs.h" - -/* Analog function control register */ -#define I2C_MST_ANA_CONF0_REG 0x6000E040 -#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) -#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) -#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) - -#define ANA_CONFIG_REG 0x6000E044 -#define ANA_CONFIG_S (8) -#define ANA_CONFIG_M (0x3FF) - -#define ANA_I2C_SAR_FORCE_PD BIT(18) -#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ - -#define ANA_CONFIG2_REG 0x6000E048 -#define ANA_CONFIG2_M BIT(18) - -#define ANA_I2C_SAR_FORCE_PU BIT(16) diff --git a/components/soc/esp32h4/include/soc/regi2c_dig_reg.h b/components/soc/esp32h4/include/soc/regi2c_dig_reg.h deleted file mode 100644 index 4fd99f7df0..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_dig_reg.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file regi2c_dig_reg.h - * @brief Register definitions for digital to get rtc voltage & digital voltage - * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. - */ - -#define I2C_DIG_REG 0x6D -#define I2C_DIG_REG_HOSTID 0 - -#define I2C_DIG_REG_EXT_RTC_DREG 4 -#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4 -#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0 - -#define I2C_DIG_REG_ENX_RTC_DREG 4 -#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7 -#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7 - -#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5 -#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4 -#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0 - -#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP 5 -#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP_MSB 7 -#define I2C_DIG_REG_ENX_RTC_DREG_SLEEP_LSB 7 - -#define I2C_DIG_REG_EXT_DIG_DREG 6 -#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4 -#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0 - -#define I2C_DIG_REG_ENX_DIG_DREG 6 -#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7 -#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7 - -#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7 -#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4 -#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0 - -#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP 7 -#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP_MSB 7 -#define I2C_DIG_REG_ENX_DIG_DREG_SLEEP_LSB 7 - -#define I2C_DIG_REG_OR_EN_CONT_CAL 9 -#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7 -#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7 - -#define I2C_DIG_REG_XPD_RTC_REG 13 -#define I2C_DIG_REG_XPD_RTC_REG_MSB 2 -#define I2C_DIG_REG_XPD_RTC_REG_LSB 2 - -#define I2C_DIG_REG_XPD_DIG_REG 13 -#define I2C_DIG_REG_XPD_DIG_REG_MSB 3 -#define I2C_DIG_REG_XPD_DIG_REG_LSB 3 - -#define I2C_DIG_REG_SCK_DCAP 14 -#define I2C_DIG_REG_SCK_DCAP_MSB 7 -#define I2C_DIG_REG_SCK_DCAP_LSB 0 diff --git a/components/soc/esp32h4/include/soc/regi2c_lp_bias.h b/components/soc/esp32h4/include/soc/regi2c_lp_bias.h deleted file mode 100644 index d10669d34a..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_lp_bias.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file regi2c_lp_bias.h - * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. - * - * This file lists register fields of low power dbais, located on an internal configuration - * bus. These definitions are used via macros defined in regi2c_ctrl.h, by - * rtc_init function in rtc_init.c. - */ -#define I2C_ULP 0x61 -#define I2C_ULP_HOSTID 0 - -#define I2C_ULP_IR_RESETB 0 -#define I2C_ULP_IR_RESETB_MSB 0 -#define I2C_ULP_IR_RESETB_LSB 0 - -#define I2C_ULP_XPD_REG_SLP 0 -#define I2C_ULP_XPD_REG_SLP_MSB 1 -#define I2C_ULP_XPD_REG_SLP_LSB 1 - -#define I2C_ULP_DBIAS_SLP 0 -#define I2C_ULP_DBIAS_SLP_MSB 7 -#define I2C_ULP_DBIAS_SLP_LSB 4 - -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1 -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1 -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1 - -#define I2C_ULP_IR_FORCE_XPD_IPH 1 -#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2 -#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2 - -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1 -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3 -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3 - -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1 -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4 -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4 - -#define I2C_ULP_IR_ZOS_XPD 2 -#define I2C_ULP_IR_ZOS_XPD_MSB 0 -#define I2C_ULP_IR_ZOS_XPD_LSB 0 - -#define I2C_ULP_IR_ZOS_RSTB 2 -#define I2C_ULP_IR_ZOS_RSTB_MSB 1 -#define I2C_ULP_IR_ZOS_RSTB_LSB 1 - -#define I2C_ULP_IR_ZOS_RESTART 2 -#define I2C_ULP_IR_ZOS_RESTART_MSB 2 -#define I2C_ULP_IR_ZOS_RESTART_LSB 2 - -#define I2C_ULP_DTEST 3 -#define I2C_ULP_DTEST_MSB 1 -#define I2C_ULP_DTEST_LSB 0 - -#define I2C_ULP_ENT_BG 3 -#define I2C_ULP_ENT_BG_MSB 2 -#define I2C_ULP_ENT_BG_LSB 2 - -#define I2C_ULP_MODE_LVDET 3 -#define I2C_ULP_MODE_LVDET_MSB 3 -#define I2C_ULP_MODE_LVDET_LSB 3 - -#define I2C_ULP_DREF_LVDET 3 -#define I2C_ULP_DREF_LVDET_MSB 6 -#define I2C_ULP_DREF_LVDET_LSB 4 - -#define I2C_ULP_XPD_LVDET 3 -#define I2C_ULP_XPD_LVDET_MSB 7 -#define I2C_ULP_XPD_LVDET_LSB 7 - -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4 -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0 -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0 - -#define I2C_ULP_INT_XPD_XTAL_BUF 4 -#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1 -#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1 - -#define I2C_ULP_INT_XPD_RC_CK 4 -#define I2C_ULP_INT_XPD_RC_CK_MSB 2 -#define I2C_ULP_INT_XPD_RC_CK_LSB 2 - -#define I2C_ULP_XTAL_DPHASE 4 -#define I2C_ULP_XTAL_DPHASE_MSB 3 -#define I2C_ULP_XTAL_DPHASE_LSB 3 - -#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4 -#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4 -#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4 - -#define I2C_ULP_XTAL_RESTART_DC_CAL 4 -#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5 -#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5 - -#define I2C_ULP_XTAL_DAC 5 -#define I2C_ULP_XTAL_DAC_MSB 3 -#define I2C_ULP_XTAL_DAC_LSB 0 - -#define I2C_ULP_XTAL_DBLEED 6 -#define I2C_ULP_XTAL_DBLEED_MSB 4 -#define I2C_ULP_XTAL_DBLEED_LSB 0 - -#define I2C_ULP_XTAL_CAL_DONE 6 -#define I2C_ULP_XTAL_CAL_DONE_MSB 5 -#define I2C_ULP_XTAL_CAL_DONE_LSB 5 - -#define I2C_ULP_ZOS_DONE 6 -#define I2C_ULP_ZOS_DONE_MSB 6 -#define I2C_ULP_ZOS_DONE_LSB 6 diff --git a/components/soc/esp32h4/include/soc/regi2c_pmu.h b/components/soc/esp32h4/include/soc/regi2c_pmu.h deleted file mode 100644 index 24ddd77826..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_pmu.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define I2C_PMU 0x6d -#define I2C_PMU_HOSTID 0 - -#define I2C_PMU_THRES_HIGH_7_0 0 -#define I2C_PMU_THRES_HIGH_7_0_MSB 7 -#define I2C_PMU_THRES_HIGH_7_0_LSB 0 - -#define I2C_PMU_THRES_LOW_7_0 1 -#define I2C_PMU_THRES_LOW_7_0_MSB 7 -#define I2C_PMU_THRES_LOW_7_0_LSB 0 - -#define I2C_PMU_THRES_HIGH_11_8 2 -#define I2C_PMU_THRES_HIGH_11_8_MSB 3 -#define I2C_PMU_THRES_HIGH_11_8_LSB 0 - -#define I2C_PMU_THRES_LOW_11_8 2 -#define I2C_PMU_THRES_LOW_11_8_MSB 7 -#define I2C_PMU_THRES_LOW_11_8_LSB 4 - -#define I2C_PMU_PVT_DELAY_INIT 3 -#define I2C_PMU_PVT_DELAY_INIT_MSB 7 -#define I2C_PMU_PVT_DELAY_INIT_LSB 0 - -#define I2C_PMU_PVT_DELAY_COUNT 4 -#define I2C_PMU_PVT_DELAY_COUNT_MSB 5 -#define I2C_PMU_PVT_DELAY_COUNT_LSB 0 - -#define I2C_PMU_OR_EN_CONT_CAL 4 -#define I2C_PMU_OR_EN_CONT_CAL_MSB 7 -#define I2C_PMU_OR_EN_CONT_CAL_LSB 7 - -#define I2C_PMU_I2C_RTC_DREG 5 -#define I2C_PMU_I2C_RTC_DREG_MSB 4 -#define I2C_PMU_I2C_RTC_DREG_LSB 0 - -#define I2C_PMU_I2C_DIG_DREG 6 -#define I2C_PMU_I2C_DIG_DREG_MSB 4 -#define I2C_PMU_I2C_DIG_DREG_LSB 0 - -#define I2C_PMU_I2C_RTC_DREG_SLP 7 -#define I2C_PMU_I2C_RTC_DREG_SLP_MSB 3 -#define I2C_PMU_I2C_RTC_DREG_SLP_LSB 0 - -#define I2C_PMU_I2C_DIG_DREG_SLP 7 -#define I2C_PMU_I2C_DIG_DREG_SLP_MSB 7 -#define I2C_PMU_I2C_DIG_DREG_SLP_LSB 4 - -#define I2C_PMU_EN_I2C_RTC_DREG 10 -#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0 -#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0 - -#define I2C_PMU_EN_I2C_DIG_DREG 10 -#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1 -#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1 - -#define I2C_PMU_EN_I2C_RTC_DREG_SLP 10 -#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2 -#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2 - -#define I2C_PMU_EN_I2C_DIG_DREG_SLP 10 -#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3 -#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3 - -#define I2C_PMU_ENX_RTC_DREG 11 -#define I2C_PMU_ENX_RTC_DREG_MSB 0 -#define I2C_PMU_ENX_RTC_DREG_LSB 0 - -#define I2C_PMU_ENX_DIG_DREG 11 -#define I2C_PMU_ENX_DIG_DREG_MSB 1 -#define I2C_PMU_ENX_DIG_DREG_LSB 1 - -#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3 11 -#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_MSB 2 -#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_LSB 2 - -#define I2C_PMU_OR_XPD_RTC_REG 11 -#define I2C_PMU_OR_XPD_RTC_REG_MSB 4 -#define I2C_PMU_OR_XPD_RTC_REG_LSB 4 - -#define I2C_PMU_OR_XPD_DIG_REG 11 -#define I2C_PMU_OR_XPD_DIG_REG_MSB 5 -#define I2C_PMU_OR_XPD_DIG_REG_LSB 5 - -#define I2C_PMU_OR_PD_RTC_REG_SLP 11 -#define I2C_PMU_OR_PD_RTC_REG_SLP_MSB 6 -#define I2C_PMU_OR_PD_RTC_REG_SLP_LSB 6 - -#define I2C_PMU_OR_PD_DIG_REG_SLP 11 -#define I2C_PMU_OR_PD_DIG_REG_SLP_MSB 7 -#define I2C_PMU_OR_PD_DIG_REG_SLP_LSB 7 - -#define I2C_PMU_INT_DREG 12 -#define I2C_PMU_INT_DREG_MSB 4 -#define I2C_PMU_INT_DREG_LSB 0 - -#define I2C_PMU_O_UDF 12 -#define I2C_PMU_O_UDF_MSB 5 -#define I2C_PMU_O_UDF_LSB 5 - -#define I2C_PMU_O_OVF 12 -#define I2C_PMU_O_OVF_MSB 6 -#define I2C_PMU_O_OVF_LSB 6 - -#define I2C_PMU_O_UPDATE 12 -#define I2C_PMU_O_UPDATE_MSB 7 -#define I2C_PMU_O_UPDATE_LSB 7 - -#define I2C_PMU_PVT_COUNT 13 -#define I2C_PMU_PVT_COUNT_MSB 7 -#define I2C_PMU_PVT_COUNT_LSB 0 - -#define I2C_PMU_PVT_COUNT 14 -#define I2C_PMU_PVT_COUNT_MSB 3 -#define I2C_PMU_PVT_COUNT_LSB 0 - -#define I2C_PMU_IC_VGOOD_LVDET 14 -#define I2C_PMU_IC_VGOOD_LVDET_MSB 4 -#define I2C_PMU_IC_VGOOD_LVDET_LSB 4 - -#define I2C_PMU_IC_POWER_GOOD_DCDC 14 -#define I2C_PMU_IC_POWER_GOOD_DCDC_MSB 5 -#define I2C_PMU_IC_POWER_GOOD_DCDC_LSB 5 - -#define I2C_PMU_IC_VGOOD_DIGDET 14 -#define I2C_PMU_IC_VGOOD_DIGDET_MSB 6 -#define I2C_PMU_IC_VGOOD_DIGDET_LSB 6 - -#define I2C_PMU_OR_XPD_DCDC 15 -#define I2C_PMU_OR_XPD_DCDC_MSB 0 -#define I2C_PMU_OR_XPD_DCDC_LSB 0 - -#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC 15 -#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_MSB 1 -#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_LSB 1 - -#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC 15 -#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_MSB 2 -#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_LSB 2 - -#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC 15 -#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_MSB 3 -#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_LSB 3 - -#define I2C_PMU_OR_ENX_REG_DCDC 15 -#define I2C_PMU_OR_ENX_REG_DCDC_MSB 4 -#define I2C_PMU_OR_ENX_REG_DCDC_LSB 4 - -#define I2C_PMU_OR_UNLOCK_DCDC 15 -#define I2C_PMU_OR_UNLOCK_DCDC_MSB 5 -#define I2C_PMU_OR_UNLOCK_DCDC_LSB 5 - -#define I2C_PMU_OR_FORCE_LOCK_DCDC 15 -#define I2C_PMU_OR_FORCE_LOCK_DCDC_MSB 6 -#define I2C_PMU_OR_FORCE_LOCK_DCDC_LSB 6 - -#define I2C_PMU_OR_ENB_SLOW_CLK 15 -#define I2C_PMU_OR_ENB_SLOW_CLK_MSB 7 -#define I2C_PMU_OR_ENB_SLOW_CLK_LSB 7 - -#define I2C_PMU_OC_SCK_DCAP 16 -#define I2C_PMU_OC_SCK_DCAP_MSB 7 -#define I2C_PMU_OC_SCK_DCAP_LSB 0 - -#define I2C_PMU_OC_XPD_LVDET 17 -#define I2C_PMU_OC_XPD_LVDET_MSB 0 -#define I2C_PMU_OC_XPD_LVDET_LSB 0 - -#define I2C_PMU_OC_MODE_LVDET 17 -#define I2C_PMU_OC_MODE_LVDET_MSB 1 -#define I2C_PMU_OC_MODE_LVDET_LSB 1 - -#define I2C_PMU_OR_XPD_TRX 17 -#define I2C_PMU_OR_XPD_TRX_MSB 2 -#define I2C_PMU_OR_XPD_TRX_LSB 2 - -#define I2C_PMU_OR_EN_RESET_CHIP 17 -#define I2C_PMU_OR_EN_RESET_CHIP_MSB 3 -#define I2C_PMU_OR_EN_RESET_CHIP_LSB 3 - -#define I2C_PMU_OC_DREF_LVDET 17 -#define I2C_PMU_OC_DREF_LVDET_MSB 6 -#define I2C_PMU_OC_DREF_LVDET_LSB 4 - -#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE 17 -#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_MSB 7 -#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_LSB 7 - -#define I2C_PMU_DTEST 18 -#define I2C_PMU_DTEST_MSB 1 -#define I2C_PMU_DTEST_LSB 0 - -#define I2C_PMU_ENT_BIAS 18 -#define I2C_PMU_ENT_BIAS_MSB 2 -#define I2C_PMU_ENT_BIAS_LSB 2 - -#define I2C_PMU_ENT_VDD 18 -#define I2C_PMU_ENT_VDD_MSB 5 -#define I2C_PMU_ENT_VDD_LSB 3 - -#define I2C_PMU_EN_DMUX 18 -#define I2C_PMU_EN_DMUX_MSB 6 -#define I2C_PMU_EN_DMUX_LSB 6 - -#define I2C_PMU_WD_DISABLE 18 -#define I2C_PMU_WD_DISABLE_MSB 7 -#define I2C_PMU_WD_DISABLE_LSB 7 - -#define I2C_PMU_DTEST_DCDC 19 -#define I2C_PMU_DTEST_DCDC_MSB 0 -#define I2C_PMU_DTEST_DCDC_LSB 0 - -#define I2C_PMU_TESTEN_DCDC 19 -#define I2C_PMU_TESTEN_DCDC_MSB 1 -#define I2C_PMU_TESTEN_DCDC_LSB 1 - -#define I2C_PMU_ADD_DCDC 19 -#define I2C_PMU_ADD_DCDC_MSB 6 -#define I2C_PMU_ADD_DCDC_LSB 4 - -#define I2C_PMU_OR_POCPENB_DCDC 20 -#define I2C_PMU_OR_POCPENB_DCDC_MSB 0 -#define I2C_PMU_OR_POCPENB_DCDC_LSB 0 - -#define I2C_PMU_OR_SSTIME_DCDC 20 -#define I2C_PMU_OR_SSTIME_DCDC_MSB 1 -#define I2C_PMU_OR_SSTIME_DCDC_LSB 1 - -#define I2C_PMU_OR_CCM_DCDC 20 -#define I2C_PMU_OR_CCM_DCDC_MSB 2 -#define I2C_PMU_OR_CCM_DCDC_LSB 2 - -#define I2C_PMU_OR_VSET_LOW_DCDC 20 -#define I2C_PMU_OR_VSET_LOW_DCDC_MSB 7 -#define I2C_PMU_OR_VSET_LOW_DCDC_LSB 3 - -#define I2C_PMU_OR_FSW_DCDC 21 -#define I2C_PMU_OR_FSW_DCDC_MSB 2 -#define I2C_PMU_OR_FSW_DCDC_LSB 0 - -#define I2C_PMU_OR_DCMLEVEL_DCDC 21 -#define I2C_PMU_OR_DCMLEVEL_DCDC_MSB 4 -#define I2C_PMU_OR_DCMLEVEL_DCDC_LSB 3 - -#define I2C_PMU_OR_DCM2ENB_DCDC 21 -#define I2C_PMU_OR_DCM2ENB_DCDC_MSB 5 -#define I2C_PMU_OR_DCM2ENB_DCDC_LSB 5 - -#define I2C_PMU_OR_RAMP_DCDC 21 -#define I2C_PMU_OR_RAMP_DCDC_MSB 6 -#define I2C_PMU_OR_RAMP_DCDC_LSB 6 - -#define I2C_PMU_OR_RAMPLEVEL_DCDC 21 -#define I2C_PMU_OR_RAMPLEVEL_DCDC_MSB 7 -#define I2C_PMU_OR_RAMPLEVEL_DCDC_LSB 7 - -#define I2C_PMU_OR_VSET_HIGH_DCDC 22 -#define I2C_PMU_OR_VSET_HIGH_DCDC_MSB 4 -#define I2C_PMU_OR_VSET_HIGH_DCDC_LSB 0 - -#define I2C_PMU_OC_DEL_SSEND 22 -#define I2C_PMU_OC_DEL_SSEND_MSB 7 -#define I2C_PMU_OC_DEL_SSEND_LSB 5 - -#define I2C_PMU_OC_XPD_DIGDET 23 -#define I2C_PMU_OC_XPD_DIGDET_MSB 0 -#define I2C_PMU_OC_XPD_DIGDET_LSB 0 - -#define I2C_PMU_OC_MODE_DIGDET 23 -#define I2C_PMU_OC_MODE_DIGDET_MSB 1 -#define I2C_PMU_OC_MODE_DIGDET_LSB 1 - -#define I2C_PMU_OC_DREF_DIGDET 23 -#define I2C_PMU_OC_DREF_DIGDET_MSB 6 -#define I2C_PMU_OC_DREF_DIGDET_LSB 4 diff --git a/components/soc/esp32h4/include/soc/regi2c_saradc.h b/components/soc/esp32h4/include/soc/regi2c_saradc.h deleted file mode 100644 index 1c35fd61ef..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_saradc.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -/** - * @file regi2c_saradc.h - * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. - * - * This file lists register fields of SAR, located on an internal configuration - * bus. These definitions are used via macros defined in regi2c_ctrl.h, by - * function in adc_ll.h. - */ - -#define I2C_SAR_ADC 0X69 -#define I2C_SAR_ADC_HOSTID 0 - -#define ADC_SAR1_ENCAL_GND_ADDR 0x7 -#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 -#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 - -#define ADC_SAR2_ENCAL_GND_ADDR 0x7 -#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 -#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 - -#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 -#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 - -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 -#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 - -#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 -#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 -#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 - -#define ADC_SAR1_DREF_ADDR 0x2 -#define ADC_SAR1_DREF_ADDR_MSB 0x6 -#define ADC_SAR1_DREF_ADDR_LSB 0x4 - -#define ADC_SAR2_DREF_ADDR 0x5 -#define ADC_SAR2_DREF_ADDR_MSB 0x6 -#define ADC_SAR2_DREF_ADDR_LSB 0x4 - -#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 -#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 - -#define ADC_SARADC_DTEST_RTC_ADDR 0x7 -#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1 -#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0 - -#define ADC_SARADC_ENT_TSENS_ADDR 0x7 -#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2 -#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2 - -#define ADC_SARADC_ENT_RTC_ADDR 0x7 -#define ADC_SARADC_ENT_RTC_ADDR_MSB 3 -#define ADC_SARADC_ENT_RTC_ADDR_LSB 3 - -#define ADC_SARADC1_ENCAL_REF_ADDR 0x7 -#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4 -#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4 - -#define ADC_SARADC2_ENCAL_REF_ADDR 0x7 -#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6 -#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6 - -#define I2C_SARADC_TSENS_DAC 0x6 -#define I2C_SARADC_TSENS_DAC_MSB 3 -#define I2C_SARADC_TSENS_DAC_LSB 0 diff --git a/components/soc/esp32h4/include/soc/regi2c_ulp.h b/components/soc/esp32h4/include/soc/regi2c_ulp.h deleted file mode 100644 index 5751f01936..0000000000 --- a/components/soc/esp32h4/include/soc/regi2c_ulp.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define I2C_ULP 0x61 -#define I2C_ULP_HOSTID 0 - -#define I2C_ULP_IR_RESETB 0 -#define I2C_ULP_IR_RESETB_MSB 0 -#define I2C_ULP_IR_RESETB_LSB 0 - -#define I2C_ULP_XPD_REG_SLP 0 -#define I2C_ULP_XPD_REG_SLP_MSB 1 -#define I2C_ULP_XPD_REG_SLP_LSB 1 - -#define I2C_ULP_DBIAS_SLP 0 -#define I2C_ULP_DBIAS_SLP_MSB 7 -#define I2C_ULP_DBIAS_SLP_LSB 4 - -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1 -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1 -#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1 - -#define I2C_ULP_IR_FORCE_XPD_IPH 1 -#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2 -#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2 - -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1 -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3 -#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3 - -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1 -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4 -#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4 - -#define I2C_ULP_IR_ZOS_XPD 2 -#define I2C_ULP_IR_ZOS_XPD_MSB 0 -#define I2C_ULP_IR_ZOS_XPD_LSB 0 - -#define I2C_ULP_IR_ZOS_RSTB 2 -#define I2C_ULP_IR_ZOS_RSTB_MSB 1 -#define I2C_ULP_IR_ZOS_RSTB_LSB 1 - -#define I2C_ULP_IR_ZOS_RESTART 2 -#define I2C_ULP_IR_ZOS_RESTART_MSB 2 -#define I2C_ULP_IR_ZOS_RESTART_LSB 2 - -#define I2C_ULP_DTEST 3 -#define I2C_ULP_DTEST_MSB 1 -#define I2C_ULP_DTEST_LSB 0 - -#define I2C_ULP_ENT_BG 3 -#define I2C_ULP_ENT_BG_MSB 2 -#define I2C_ULP_ENT_BG_LSB 2 - -#define I2C_ULP_MODE_LVDET 3 -#define I2C_ULP_MODE_LVDET_MSB 3 -#define I2C_ULP_MODE_LVDET_LSB 3 - -#define I2C_ULP_DREF_LVDET 3 -#define I2C_ULP_DREF_LVDET_MSB 6 -#define I2C_ULP_DREF_LVDET_LSB 4 - -#define I2C_ULP_XPD_LVDET 3 -#define I2C_ULP_XPD_LVDET_MSB 7 -#define I2C_ULP_XPD_LVDET_LSB 7 - -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4 -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0 -#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0 - -#define I2C_ULP_INT_XPD_XTAL_BUF 4 -#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1 -#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1 - -#define I2C_ULP_INT_XPD_RC_CK 4 -#define I2C_ULP_INT_XPD_RC_CK_MSB 2 -#define I2C_ULP_INT_XPD_RC_CK_LSB 2 - -#define I2C_ULP_XTAL_DPHASE 4 -#define I2C_ULP_XTAL_DPHASE_MSB 3 -#define I2C_ULP_XTAL_DPHASE_LSB 3 - -#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4 -#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4 -#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4 - -#define I2C_ULP_XTAL_RESTART_DC_CAL 4 -#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5 -#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5 - -#define I2C_ULP_XTAL_DAC 5 -#define I2C_ULP_XTAL_DAC_MSB 3 -#define I2C_ULP_XTAL_DAC_LSB 0 - -#define I2C_ULP_XTAL_DBLEED 6 -#define I2C_ULP_XTAL_DBLEED_MSB 4 -#define I2C_ULP_XTAL_DBLEED_LSB 0 - -#define I2C_ULP_XTAL_CAL_DONE 6 -#define I2C_ULP_XTAL_CAL_DONE_MSB 5 -#define I2C_ULP_XTAL_CAL_DONE_LSB 5 - -#define I2C_ULP_ZOS_DONE 6 -#define I2C_ULP_ZOS_DONE_MSB 6 -#define I2C_ULP_ZOS_DONE_LSB 6 diff --git a/components/soc/esp32h4/include/soc/reset_reasons.h b/components/soc/esp32h4/include/soc/reset_reasons.h deleted file mode 100644 index e2a8afd11f..0000000000 --- a/components/soc/esp32h4/include/soc/reset_reasons.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -//+-----------------------------------------------Terminology---------------------------------------------+ -//| | -//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | -//| | -//| Core Reset: Reset the whole digital system except RTC sub-system | -//| | -//| System Reset: Reset the whole digital system, including RTC sub-system | -//| | -//| Chip Reset: Reset the whole chip, including the analog part | -//| | -//+-------------------------------------------------------------------------------------------------------+ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} - * @note refer to TRM: chapter - */ -typedef enum { - RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset - RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip - RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip - RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST - RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core - RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core - RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core - RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core - RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 - RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST - RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 - RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core - RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module - RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 - RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module - RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module - RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core - RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core - RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core - RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core - RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 -} soc_reset_reason_t; - - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/rmt_reg.h b/components/soc/esp32h4/include/soc/rmt_reg.h deleted file mode 100644 index 106fc78649..0000000000 --- a/components/soc/esp32h4/include/soc/rmt_reg.h +++ /dev/null @@ -1,1132 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include "soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) - -#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) - -#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) - -#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) - -#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0010) -/* RMT_CONF_UPDATE_CH0 : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH0 (BIT(24)) -#define RMT_CONF_UPDATE_CH0_M (BIT(24)) -#define RMT_CONF_UPDATE_CH0_V 0x1 -#define RMT_CONF_UPDATE_CH0_S 24 -/* RMT_AFIFO_RST_CH0 : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH0 (BIT(23)) -#define RMT_AFIFO_RST_CH0_M (BIT(23)) -#define RMT_AFIFO_RST_CH0_V 0x1 -#define RMT_AFIFO_RST_CH0_S 23 -/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_V 0x1 -#define RMT_CARRIER_OUT_LV_CH0_S 22 -/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH0 (BIT(21)) -#define RMT_CARRIER_EN_CH0_M (BIT(21)) -#define RMT_CARRIER_EN_CH0_V 0x1 -#define RMT_CARRIER_EN_CH0_S 21 -/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_V 0x1 -#define RMT_CARRIER_EFF_EN_CH0_S 20 -/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH0 0x00000007 -#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) -#define RMT_MEM_SIZE_CH0_V 0x7 -#define RMT_MEM_SIZE_CH0_S 16 -/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH0 0x000000FF -#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) -#define RMT_DIV_CNT_CH0_V 0xFF -#define RMT_DIV_CNT_CH0_S 8 -/* RMT_TX_STOP_CH0 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH0 (BIT(7)) -#define RMT_TX_STOP_CH0_M (BIT(7)) -#define RMT_TX_STOP_CH0_V 0x1 -#define RMT_TX_STOP_CH0_S 7 -/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_V 0x1 -#define RMT_IDLE_OUT_EN_CH0_S 6 -/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_V 0x1 -#define RMT_IDLE_OUT_LV_CH0_S 5 -/* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH0_S 4 -/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_V 0x1 -#define RMT_TX_CONTI_MODE_CH0_S 3 -/* RMT_APB_MEM_RST_CH0 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH0 (BIT(2)) -#define RMT_APB_MEM_RST_CH0_M (BIT(2)) -#define RMT_APB_MEM_RST_CH0_V 0x1 -#define RMT_APB_MEM_RST_CH0_S 2 -/* RMT_MEM_RD_RST_CH0 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH0 (BIT(1)) -#define RMT_MEM_RD_RST_CH0_M (BIT(1)) -#define RMT_MEM_RD_RST_CH0_V 0x1 -#define RMT_MEM_RD_RST_CH0_S 1 -/* RMT_TX_START_CH0 : WT ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (BIT(0)) -#define RMT_TX_START_CH0_V 0x1 -#define RMT_TX_START_CH0_S 0 - -#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0014) -/* RMT_CONF_UPDATE_CH1 : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH1 (BIT(24)) -#define RMT_CONF_UPDATE_CH1_M (BIT(24)) -#define RMT_CONF_UPDATE_CH1_V 0x1 -#define RMT_CONF_UPDATE_CH1_S 24 -/* RMT_AFIFO_RST_CH1 : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH1 (BIT(23)) -#define RMT_AFIFO_RST_CH1_M (BIT(23)) -#define RMT_AFIFO_RST_CH1_V 0x1 -#define RMT_AFIFO_RST_CH1_S 23 -/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_V 0x1 -#define RMT_CARRIER_OUT_LV_CH1_S 22 -/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH1 (BIT(21)) -#define RMT_CARRIER_EN_CH1_M (BIT(21)) -#define RMT_CARRIER_EN_CH1_V 0x1 -#define RMT_CARRIER_EN_CH1_S 21 -/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_V 0x1 -#define RMT_CARRIER_EFF_EN_CH1_S 20 -/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH1 0x00000007 -#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) -#define RMT_MEM_SIZE_CH1_V 0x7 -#define RMT_MEM_SIZE_CH1_S 16 -/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH1 0x000000FF -#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) -#define RMT_DIV_CNT_CH1_V 0xFF -#define RMT_DIV_CNT_CH1_S 8 -/* RMT_TX_STOP_CH1 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_STOP_CH1 (BIT(7)) -#define RMT_TX_STOP_CH1_M (BIT(7)) -#define RMT_TX_STOP_CH1_V 0x1 -#define RMT_TX_STOP_CH1_S 7 -/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_V 0x1 -#define RMT_IDLE_OUT_EN_CH1_S 6 -/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_V 0x1 -#define RMT_IDLE_OUT_LV_CH1_S 5 -/* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH1_S 4 -/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_V 0x1 -#define RMT_TX_CONTI_MODE_CH1_S 3 -/* RMT_APB_MEM_RST_CH1 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH1 (BIT(2)) -#define RMT_APB_MEM_RST_CH1_M (BIT(2)) -#define RMT_APB_MEM_RST_CH1_V 0x1 -#define RMT_APB_MEM_RST_CH1_S 2 -/* RMT_MEM_RD_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RD_RST_CH1 (BIT(1)) -#define RMT_MEM_RD_RST_CH1_M (BIT(1)) -#define RMT_MEM_RD_RST_CH1_V 0x1 -#define RMT_MEM_RD_RST_CH1_S 1 -/* RMT_TX_START_CH1 : WT ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_TX_START_CH1 (BIT(0)) -#define RMT_TX_START_CH1_M (BIT(0)) -#define RMT_TX_START_CH1_V 0x1 -#define RMT_TX_START_CH1_S 0 - -#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0018) -/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH2_V 0x1 -#define RMT_CARRIER_OUT_LV_CH2_S 29 -/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH2 (BIT(28)) -#define RMT_CARRIER_EN_CH2_M (BIT(28)) -#define RMT_CARRIER_EN_CH2_V 0x1 -#define RMT_CARRIER_EN_CH2_S 28 -/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[25:23] ;default: 3'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH2 0x00000007 -#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) -#define RMT_MEM_SIZE_CH2_V 0x7 -#define RMT_MEM_SIZE_CH2_S 23 -/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH2 0x00007FFF -#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) -#define RMT_IDLE_THRES_CH2_V 0x7FFF -#define RMT_IDLE_THRES_CH2_S 8 -/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH2 0x000000FF -#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) -#define RMT_DIV_CNT_CH2_V 0xFF -#define RMT_DIV_CNT_CH2_S 0 - -#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x001c) -/* RMT_CONF_UPDATE_CH2 : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH2 (BIT(15)) -#define RMT_CONF_UPDATE_CH2_M (BIT(15)) -#define RMT_CONF_UPDATE_CH2_V 0x1 -#define RMT_CONF_UPDATE_CH2_S 15 -/* RMT_AFIFO_RST_CH2 : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH2 (BIT(14)) -#define RMT_AFIFO_RST_CH2_M (BIT(14)) -#define RMT_AFIFO_RST_CH2_V 0x1 -#define RMT_AFIFO_RST_CH2_S 14 -/* RMT_MEM_RX_WRAP_EN_CH2 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH2_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH2_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH2_S 13 -/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH2 0x000000FF -#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) -#define RMT_RX_FILTER_THRES_CH2_V 0xFF -#define RMT_RX_FILTER_THRES_CH2_S 5 -/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH2 (BIT(4)) -#define RMT_RX_FILTER_EN_CH2_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH2_V 0x1 -#define RMT_RX_FILTER_EN_CH2_S 4 -/* RMT_MEM_OWNER_CH2 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH2 (BIT(3)) -#define RMT_MEM_OWNER_CH2_M (BIT(3)) -#define RMT_MEM_OWNER_CH2_V 0x1 -#define RMT_MEM_OWNER_CH2_S 3 -/* RMT_APB_MEM_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH2 (BIT(2)) -#define RMT_APB_MEM_RST_CH2_M (BIT(2)) -#define RMT_APB_MEM_RST_CH2_V 0x1 -#define RMT_APB_MEM_RST_CH2_S 2 -/* RMT_MEM_WR_RST_CH2 : WT ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH2 (BIT(1)) -#define RMT_MEM_WR_RST_CH2_M (BIT(1)) -#define RMT_MEM_WR_RST_CH2_V 0x1 -#define RMT_MEM_WR_RST_CH2_S 1 -/* RMT_RX_EN_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH2 (BIT(0)) -#define RMT_RX_EN_CH2_M (BIT(0)) -#define RMT_RX_EN_CH2_V 0x1 -#define RMT_RX_EN_CH2_S 0 - -#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0020) -/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH3_V 0x1 -#define RMT_CARRIER_OUT_LV_CH3_S 29 -/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: */ -#define RMT_CARRIER_EN_CH3 (BIT(28)) -#define RMT_CARRIER_EN_CH3_M (BIT(28)) -#define RMT_CARRIER_EN_CH3_V 0x1 -#define RMT_CARRIER_EN_CH3_S 28 -/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[25:23] ;default: 3'h1 ; */ -/*description: */ -#define RMT_MEM_SIZE_CH3 0x00000007 -#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) -#define RMT_MEM_SIZE_CH3_V 0x7 -#define RMT_MEM_SIZE_CH3_S 23 -/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: */ -#define RMT_IDLE_THRES_CH3 0x00007FFF -#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) -#define RMT_IDLE_THRES_CH3_V 0x7FFF -#define RMT_IDLE_THRES_CH3_S 8 -/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: */ -#define RMT_DIV_CNT_CH3 0x000000FF -#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) -#define RMT_DIV_CNT_CH3_V 0xFF -#define RMT_DIV_CNT_CH3_S 0 - -#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x0024) -/* RMT_CONF_UPDATE_CH3 : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CONF_UPDATE_CH3 (BIT(15)) -#define RMT_CONF_UPDATE_CH3_M (BIT(15)) -#define RMT_CONF_UPDATE_CH3_V 0x1 -#define RMT_CONF_UPDATE_CH3_S 15 -/* RMT_AFIFO_RST_CH3 : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RMT_AFIFO_RST_CH3 (BIT(14)) -#define RMT_AFIFO_RST_CH3_M (BIT(14)) -#define RMT_AFIFO_RST_CH3_V 0x1 -#define RMT_AFIFO_RST_CH3_S 14 -/* RMT_MEM_RX_WRAP_EN_CH3 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH3_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH3_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH3_S 13 -/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: */ -#define RMT_RX_FILTER_THRES_CH3 0x000000FF -#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) -#define RMT_RX_FILTER_THRES_CH3_V 0xFF -#define RMT_RX_FILTER_THRES_CH3_S 5 -/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_RX_FILTER_EN_CH3 (BIT(4)) -#define RMT_RX_FILTER_EN_CH3_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH3_V 0x1 -#define RMT_RX_FILTER_EN_CH3_S 4 -/* RMT_MEM_OWNER_CH3 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define RMT_MEM_OWNER_CH3 (BIT(3)) -#define RMT_MEM_OWNER_CH3_M (BIT(3)) -#define RMT_MEM_OWNER_CH3_V 0x1 -#define RMT_MEM_OWNER_CH3_S 3 -/* RMT_APB_MEM_RST_CH3 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RST_CH3 (BIT(2)) -#define RMT_APB_MEM_RST_CH3_M (BIT(2)) -#define RMT_APB_MEM_RST_CH3_V 0x1 -#define RMT_APB_MEM_RST_CH3_S 2 -/* RMT_MEM_WR_RST_CH3 : WT ;bitpos:[1] ;default: 1'h0 ; */ -/*description: */ -#define RMT_MEM_WR_RST_CH3 (BIT(1)) -#define RMT_MEM_WR_RST_CH3_M (BIT(1)) -#define RMT_MEM_WR_RST_CH3_V 0x1 -#define RMT_MEM_WR_RST_CH3_S 1 -/* RMT_RX_EN_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_RX_EN_CH3 (BIT(0)) -#define RMT_RX_EN_CH3_M (BIT(0)) -#define RMT_RX_EN_CH3_V 0x1 -#define RMT_RX_EN_CH3_S 0 - -#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0028) -/* RMT_APB_MEM_RADDR_CH0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH0 0x000000FF -#define RMT_APB_MEM_RADDR_CH0_M ((RMT_APB_MEM_RADDR_CH0_V)<<(RMT_APB_MEM_RADDR_CH0_S)) -#define RMT_APB_MEM_RADDR_CH0_V 0xFF -#define RMT_APB_MEM_RADDR_CH0_S 24 -/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(23)) -#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(23)) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH0_S 23 -/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH0 (BIT(22)) -#define RMT_MEM_EMPTY_CH0_M (BIT(22)) -#define RMT_MEM_EMPTY_CH0_V 0x1 -#define RMT_MEM_EMPTY_CH0_S 22 -/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH0 (BIT(21)) -#define RMT_APB_MEM_RD_ERR_CH0_M (BIT(21)) -#define RMT_APB_MEM_RD_ERR_CH0_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH0_S 21 -/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH0 0x000001FF -#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V)<<(RMT_APB_MEM_WADDR_CH0_S)) -#define RMT_APB_MEM_WADDR_CH0_V 0x1FF -#define RMT_APB_MEM_WADDR_CH0_S 12 -/* RMT_STATE_CH0 : RO ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH0 0x00000007 -#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S)) -#define RMT_STATE_CH0_V 0x7 -#define RMT_STATE_CH0_S 9 -/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH0 0x000001FF -#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S)) -#define RMT_MEM_RADDR_EX_CH0_V 0x1FF -#define RMT_MEM_RADDR_EX_CH0_S 0 - -#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x002c) -/* RMT_APB_MEM_RADDR_CH1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH1 0x000000FF -#define RMT_APB_MEM_RADDR_CH1_M ((RMT_APB_MEM_RADDR_CH1_V)<<(RMT_APB_MEM_RADDR_CH1_S)) -#define RMT_APB_MEM_RADDR_CH1_V 0xFF -#define RMT_APB_MEM_RADDR_CH1_S 24 -/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WR_ERR_CH1 (BIT(23)) -#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(23)) -#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH1_S 23 -/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_EMPTY_CH1 (BIT(22)) -#define RMT_MEM_EMPTY_CH1_M (BIT(22)) -#define RMT_MEM_EMPTY_CH1_V 0x1 -#define RMT_MEM_EMPTY_CH1_S 22 -/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH1 (BIT(21)) -#define RMT_APB_MEM_RD_ERR_CH1_M (BIT(21)) -#define RMT_APB_MEM_RD_ERR_CH1_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH1_S 21 -/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ -/*description: */ -#define RMT_APB_MEM_WADDR_CH1 0x000001FF -#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V)<<(RMT_APB_MEM_WADDR_CH1_S)) -#define RMT_APB_MEM_WADDR_CH1_V 0x1FF -#define RMT_APB_MEM_WADDR_CH1_S 12 -/* RMT_STATE_CH1 : RO ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH1 0x00000007 -#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S)) -#define RMT_STATE_CH1_V 0x7 -#define RMT_STATE_CH1_S 9 -/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: */ -#define RMT_MEM_RADDR_EX_CH1 0x000001FF -#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S)) -#define RMT_MEM_RADDR_EX_CH1_V 0x1FF -#define RMT_MEM_RADDR_EX_CH1_S 0 - -#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0030) -/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH2_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH2_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH2_S 27 -/* RMT_MEM_FULL_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH2 (BIT(26)) -#define RMT_MEM_FULL_CH2_M (BIT(26)) -#define RMT_MEM_FULL_CH2_V 0x1 -#define RMT_MEM_FULL_CH2_S 26 -/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH2 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH2_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH2_V 0x1 -#define RMT_MEM_OWNER_ERR_CH2_S 25 -/* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH2 0x00000007 -#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S)) -#define RMT_STATE_CH2_V 0x7 -#define RMT_STATE_CH2_S 22 -/* RMT_APB_MEM_RADDR_CH2 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH2 0x000001FF -#define RMT_APB_MEM_RADDR_CH2_M ((RMT_APB_MEM_RADDR_CH2_V)<<(RMT_APB_MEM_RADDR_CH2_S)) -#define RMT_APB_MEM_RADDR_CH2_V 0x1FF -#define RMT_APB_MEM_RADDR_CH2_S 12 -/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH2 0x000001FF -#define RMT_MEM_WADDR_EX_CH2_M ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S)) -#define RMT_MEM_WADDR_EX_CH2_V 0x1FF -#define RMT_MEM_WADDR_EX_CH2_S 0 - -#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x0034) -/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH3_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH3_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH3_S 27 -/* RMT_MEM_FULL_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FULL_CH3 (BIT(26)) -#define RMT_MEM_FULL_CH3_M (BIT(26)) -#define RMT_MEM_FULL_CH3_V 0x1 -#define RMT_MEM_FULL_CH3_S 26 -/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_OWNER_ERR_CH3 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH3_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH3_V 0x1 -#define RMT_MEM_OWNER_ERR_CH3_S 25 -/* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: */ -#define RMT_STATE_CH3 0x00000007 -#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S)) -#define RMT_STATE_CH3_V 0x7 -#define RMT_STATE_CH3_S 22 -/* RMT_APB_MEM_RADDR_CH3 : RO ;bitpos:[20:12] ;default: 9'b0 ; */ -/*description: */ -#define RMT_APB_MEM_RADDR_CH3 0x000001FF -#define RMT_APB_MEM_RADDR_CH3_M ((RMT_APB_MEM_RADDR_CH3_V)<<(RMT_APB_MEM_RADDR_CH3_S)) -#define RMT_APB_MEM_RADDR_CH3_V 0x1FF -#define RMT_APB_MEM_RADDR_CH3_S 12 -/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: */ -#define RMT_MEM_WADDR_EX_CH3 0x000001FF -#define RMT_MEM_WADDR_EX_CH3_M ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S)) -#define RMT_MEM_WADDR_EX_CH3_V 0x1FF -#define RMT_MEM_WADDR_EX_CH3_S 0 - -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x0038) -/* RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH1_TX_LOOP_INT_RAW_S 13 -/* RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH0_TX_LOOP_INT_RAW_S 12 -/* RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 11 -/* RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 -/* RMT_CH3_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_RAW (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_V 0x1 -#define RMT_CH3_ERR_INT_RAW_S 7 -/* RMT_CH2_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_RAW (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_V 0x1 -#define RMT_CH2_ERR_INT_RAW_S 6 -/* RMT_CH1_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_RAW (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_V 0x1 -#define RMT_CH1_ERR_INT_RAW_S 5 -/* RMT_CH0_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_RAW (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_V 0x1 -#define RMT_CH0_ERR_INT_RAW_S 4 -/* RMT_CH3_RX_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_END_INT_RAW (BIT(3)) -#define RMT_CH3_RX_END_INT_RAW_M (BIT(3)) -#define RMT_CH3_RX_END_INT_RAW_V 0x1 -#define RMT_CH3_RX_END_INT_RAW_S 3 -/* RMT_CH2_RX_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_END_INT_RAW (BIT(2)) -#define RMT_CH2_RX_END_INT_RAW_M (BIT(2)) -#define RMT_CH2_RX_END_INT_RAW_V 0x1 -#define RMT_CH2_RX_END_INT_RAW_S 2 -/* RMT_CH1_TX_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_RAW (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_V 0x1 -#define RMT_CH1_TX_END_INT_RAW_S 1 -/* RMT_CH0_TX_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_RAW (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_V 0x1 -#define RMT_CH0_TX_END_INT_RAW_S 0 - -#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x003c) -/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ST_S 13 -/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ST_S 12 -/* RMT_CH3_RX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_ST_M (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH3_RX_THR_EVENT_INT_ST_S 11 -/* RMT_CH2_RX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_ST_M (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH2_RX_THR_EVENT_INT_ST_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 -/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_ST (BIT(7)) -#define RMT_CH3_ERR_INT_ST_M (BIT(7)) -#define RMT_CH3_ERR_INT_ST_V 0x1 -#define RMT_CH3_ERR_INT_ST_S 7 -/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_ST (BIT(6)) -#define RMT_CH2_ERR_INT_ST_M (BIT(6)) -#define RMT_CH2_ERR_INT_ST_V 0x1 -#define RMT_CH2_ERR_INT_ST_S 6 -/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_ST (BIT(5)) -#define RMT_CH1_ERR_INT_ST_M (BIT(5)) -#define RMT_CH1_ERR_INT_ST_V 0x1 -#define RMT_CH1_ERR_INT_ST_S 5 -/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_ST (BIT(4)) -#define RMT_CH0_ERR_INT_ST_M (BIT(4)) -#define RMT_CH0_ERR_INT_ST_V 0x1 -#define RMT_CH0_ERR_INT_ST_S 4 -/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_END_INT_ST (BIT(3)) -#define RMT_CH3_RX_END_INT_ST_M (BIT(3)) -#define RMT_CH3_RX_END_INT_ST_V 0x1 -#define RMT_CH3_RX_END_INT_ST_S 3 -/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_END_INT_ST (BIT(2)) -#define RMT_CH2_RX_END_INT_ST_M (BIT(2)) -#define RMT_CH2_RX_END_INT_ST_V 0x1 -#define RMT_CH2_RX_END_INT_ST_S 2 -/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_ST (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_V 0x1 -#define RMT_CH1_TX_END_INT_ST_S 1 -/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_ST (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_V 0x1 -#define RMT_CH0_TX_END_INT_ST_S 0 - -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x0040) -/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ENA_S 13 -/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ENA_S 12 -/* RMT_CH3_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 11 -/* RMT_CH2_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 -/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_ENA (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_V 0x1 -#define RMT_CH3_ERR_INT_ENA_S 7 -/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_ENA (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_V 0x1 -#define RMT_CH2_ERR_INT_ENA_S 6 -/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_ENA (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_V 0x1 -#define RMT_CH1_ERR_INT_ENA_S 5 -/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_ENA (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_V 0x1 -#define RMT_CH0_ERR_INT_ENA_S 4 -/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_END_INT_ENA (BIT(3)) -#define RMT_CH3_RX_END_INT_ENA_M (BIT(3)) -#define RMT_CH3_RX_END_INT_ENA_V 0x1 -#define RMT_CH3_RX_END_INT_ENA_S 3 -/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_END_INT_ENA (BIT(2)) -#define RMT_CH2_RX_END_INT_ENA_M (BIT(2)) -#define RMT_CH2_RX_END_INT_ENA_V 0x1 -#define RMT_CH2_RX_END_INT_ENA_S 2 -/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_ENA (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_V 0x1 -#define RMT_CH1_TX_END_INT_ENA_S 1 -/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_ENA (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_V 0x1 -#define RMT_CH0_TX_END_INT_ENA_S 0 - -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x0044) -/* RMT_CH1_TX_LOOP_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH1_TX_LOOP_INT_CLR_S 13 -/* RMT_CH0_TX_LOOP_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH0_TX_LOOP_INT_CLR_S 12 -/* RMT_CH3_RX_THR_EVENT_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (BIT(11)) -#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 11 -/* RMT_CH2_RX_THR_EVENT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (BIT(10)) -#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 -/* RMT_CH3_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_ERR_INT_CLR (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_V 0x1 -#define RMT_CH3_ERR_INT_CLR_S 7 -/* RMT_CH2_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_ERR_INT_CLR (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_V 0x1 -#define RMT_CH2_ERR_INT_CLR_S 6 -/* RMT_CH1_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_ERR_INT_CLR (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_V 0x1 -#define RMT_CH1_ERR_INT_CLR_S 5 -/* RMT_CH0_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_ERR_INT_CLR (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_V 0x1 -#define RMT_CH0_ERR_INT_CLR_S 4 -/* RMT_CH3_RX_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH3_RX_END_INT_CLR (BIT(3)) -#define RMT_CH3_RX_END_INT_CLR_M (BIT(3)) -#define RMT_CH3_RX_END_INT_CLR_V 0x1 -#define RMT_CH3_RX_END_INT_CLR_S 3 -/* RMT_CH2_RX_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH2_RX_END_INT_CLR (BIT(2)) -#define RMT_CH2_RX_END_INT_CLR_M (BIT(2)) -#define RMT_CH2_RX_END_INT_CLR_V 0x1 -#define RMT_CH2_RX_END_INT_CLR_S 2 -/* RMT_CH1_TX_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH1_TX_END_INT_CLR (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_V 0x1 -#define RMT_CH1_TX_END_INT_CLR_S 1 -/* RMT_CH0_TX_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_CH0_TX_END_INT_CLR (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_V 0x1 -#define RMT_CH0_TX_END_INT_CLR_S 0 - -#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0048) -/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFF -#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) -#define RMT_CARRIER_HIGH_CH0_V 0xFFFF -#define RMT_CARRIER_HIGH_CH0_S 16 -/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH0 0x0000FFFF -#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) -#define RMT_CARRIER_LOW_CH0_V 0xFFFF -#define RMT_CARRIER_LOW_CH0_S 0 - -#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x004c) -/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_CH1 0x0000FFFF -#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) -#define RMT_CARRIER_HIGH_CH1_V 0xFFFF -#define RMT_CARRIER_HIGH_CH1_S 16 -/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: */ -#define RMT_CARRIER_LOW_CH1 0x0000FFFF -#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) -#define RMT_CARRIER_LOW_CH1_V 0xFFFF -#define RMT_CARRIER_LOW_CH1_S 0 - -#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0050) -/* RMT_CARRIER_HIGH_THRES_CH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH2_M ((RMT_CARRIER_HIGH_THRES_CH2_V)<<(RMT_CARRIER_HIGH_THRES_CH2_S)) -#define RMT_CARRIER_HIGH_THRES_CH2_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH2_S 16 -/* RMT_CARRIER_LOW_THRES_CH2 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH2_M ((RMT_CARRIER_LOW_THRES_CH2_V)<<(RMT_CARRIER_LOW_THRES_CH2_S)) -#define RMT_CARRIER_LOW_THRES_CH2_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH2_S 0 - -#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0054) -/* RMT_CARRIER_HIGH_THRES_CH3 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH3_M ((RMT_CARRIER_HIGH_THRES_CH3_V)<<(RMT_CARRIER_HIGH_THRES_CH3_S)) -#define RMT_CARRIER_HIGH_THRES_CH3_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH3_S 16 -/* RMT_CARRIER_LOW_THRES_CH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH3_M ((RMT_CARRIER_LOW_THRES_CH3_V)<<(RMT_CARRIER_LOW_THRES_CH3_S)) -#define RMT_CARRIER_LOW_THRES_CH3_V 0xFFFF -#define RMT_CARRIER_LOW_THRES_CH3_S 0 - -#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x0058) -/* RMT_LOOP_COUNT_RESET_CH0 : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH0_S 20 -/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 -/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH0 0x000003FF -#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V)<<(RMT_TX_LOOP_NUM_CH0_S)) -#define RMT_TX_LOOP_NUM_CH0_V 0x3FF -#define RMT_TX_LOOP_NUM_CH0_S 9 -/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH0 0x000001FF -#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) -#define RMT_TX_LIM_CH0_V 0x1FF -#define RMT_TX_LIM_CH0_S 0 - -#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x005c) -/* RMT_LOOP_COUNT_RESET_CH1 : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH1_S 20 -/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH1_S 19 -/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: */ -#define RMT_TX_LOOP_NUM_CH1 0x000003FF -#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V)<<(RMT_TX_LOOP_NUM_CH1_S)) -#define RMT_TX_LOOP_NUM_CH1_V 0x3FF -#define RMT_TX_LOOP_NUM_CH1_S 9 -/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_TX_LIM_CH1 0x000001FF -#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) -#define RMT_TX_LIM_CH1_V 0x1FF -#define RMT_TX_LIM_CH1_S 0 - -#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x0060) -/* RMT_RX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH2 0x000001FF -#define RMT_RX_LIM_CH2_M ((RMT_RX_LIM_CH2_V)<<(RMT_RX_LIM_CH2_S)) -#define RMT_RX_LIM_CH2_V 0x1FF -#define RMT_RX_LIM_CH2_S 0 - -#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x0064) -/* RMT_RX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: */ -#define RMT_RX_LIM_CH3 0x000001FF -#define RMT_RX_LIM_CH3_M ((RMT_RX_LIM_CH3_V)<<(RMT_RX_LIM_CH3_S)) -#define RMT_RX_LIM_CH3_V 0x1FF -#define RMT_RX_LIM_CH3_S 0 - -#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x0068) -/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 -/* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */ -/*description: */ -#define RMT_SCLK_ACTIVE (BIT(26)) -#define RMT_SCLK_ACTIVE_M (BIT(26)) -#define RMT_SCLK_ACTIVE_V 0x1 -#define RMT_SCLK_ACTIVE_S 26 -/* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */ -/*description: */ -#define RMT_SCLK_SEL 0x00000003 -#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V)<<(RMT_SCLK_SEL_S)) -#define RMT_SCLK_SEL_V 0x3 -#define RMT_SCLK_SEL_S 24 -/* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */ -/*description: */ -#define RMT_SCLK_DIV_B 0x0000003F -#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V)<<(RMT_SCLK_DIV_B_S)) -#define RMT_SCLK_DIV_B_V 0x3F -#define RMT_SCLK_DIV_B_S 18 -/* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */ -/*description: */ -#define RMT_SCLK_DIV_A 0x0000003F -#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V)<<(RMT_SCLK_DIV_A_S)) -#define RMT_SCLK_DIV_A_V 0x3F -#define RMT_SCLK_DIV_A_S 12 -/* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */ -/*description: */ -#define RMT_SCLK_DIV_NUM 0x000000FF -#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V)<<(RMT_SCLK_DIV_NUM_S)) -#define RMT_SCLK_DIV_NUM_V 0xFF -#define RMT_SCLK_DIV_NUM_S 4 -/* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FORCE_PU (BIT(3)) -#define RMT_MEM_FORCE_PU_M (BIT(3)) -#define RMT_MEM_FORCE_PU_V 0x1 -#define RMT_MEM_FORCE_PU_S 3 -/* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_FORCE_PD (BIT(2)) -#define RMT_MEM_FORCE_PD_M (BIT(2)) -#define RMT_MEM_FORCE_PD_V 0x1 -#define RMT_MEM_FORCE_PD_S 2 -/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_CLK_FORCE_ON (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_V 0x1 -#define RMT_MEM_CLK_FORCE_ON_S 1 -/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define RMT_APB_FIFO_MASK (BIT(0)) -#define RMT_APB_FIFO_MASK_M (BIT(0)) -#define RMT_APB_FIFO_MASK_V 0x1 -#define RMT_APB_FIFO_MASK_S 0 - -#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x006c) -/* RMT_TX_SIM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_EN (BIT(2)) -#define RMT_TX_SIM_EN_M (BIT(2)) -#define RMT_TX_SIM_EN_V 0x1 -#define RMT_TX_SIM_EN_S 2 -/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH1 (BIT(1)) -#define RMT_TX_SIM_CH1_M (BIT(1)) -#define RMT_TX_SIM_CH1_V 0x1 -#define RMT_TX_SIM_CH1_S 1 -/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_TX_SIM_CH0 (BIT(0)) -#define RMT_TX_SIM_CH0_M (BIT(0)) -#define RMT_TX_SIM_CH0_V 0x1 -#define RMT_TX_SIM_CH0_S 0 - -#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x0070) -/* RMT_REF_CNT_RST_CH3 : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH3 (BIT(3)) -#define RMT_REF_CNT_RST_CH3_M (BIT(3)) -#define RMT_REF_CNT_RST_CH3_V 0x1 -#define RMT_REF_CNT_RST_CH3_S 3 -/* RMT_REF_CNT_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH2 (BIT(2)) -#define RMT_REF_CNT_RST_CH2_M (BIT(2)) -#define RMT_REF_CNT_RST_CH2_V 0x1 -#define RMT_REF_CNT_RST_CH2_S 2 -/* RMT_REF_CNT_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH1 (BIT(1)) -#define RMT_REF_CNT_RST_CH1_M (BIT(1)) -#define RMT_REF_CNT_RST_CH1_V 0x1 -#define RMT_REF_CNT_RST_CH1_S 1 -/* RMT_REF_CNT_RST_CH0 : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RMT_REF_CNT_RST_CH0 (BIT(0)) -#define RMT_REF_CNT_RST_CH0_M (BIT(0)) -#define RMT_REF_CNT_RST_CH0_V 0x1 -#define RMT_REF_CNT_RST_CH0_S 0 - -#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00cc) -/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006231 ; */ -/*description: */ -#define RMT_DATE 0x0FFFFFFF -#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) -#define RMT_DATE_V 0xFFFFFFF -#define RMT_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/rmt_struct.h b/components/soc/esp32h4/include/soc/rmt_struct.h deleted file mode 100644 index 14550622f7..0000000000 --- a/components/soc/esp32h4/include/soc/rmt_struct.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct rmt_dev_t { - volatile uint32_t data_ch[4]; - volatile union { - struct { - uint32_t tx_start: 1; - uint32_t mem_rd_rst: 1; - uint32_t mem_rst: 1; - uint32_t tx_conti_mode: 1; - uint32_t mem_tx_wrap_en: 1; - uint32_t idle_out_lv: 1; - uint32_t idle_out_en: 1; - uint32_t tx_stop: 1; - uint32_t div_cnt: 8; - uint32_t mem_size: 3; - uint32_t reserved19: 1; - uint32_t carrier_eff_en: 1; - uint32_t carrier_en: 1; - uint32_t carrier_out_lv: 1; - uint32_t afifo_rst: 1; - uint32_t conf_update: 1; - uint32_t reserved25: 7; - }; - uint32_t val; - } tx_conf[2]; - volatile struct { - union { - struct { - uint32_t div_cnt: 8; - uint32_t idle_thres: 15; - uint32_t mem_size: 3; - uint32_t reserved26: 2; - uint32_t carrier_en: 1; - uint32_t carrier_out_lv: 1; - uint32_t reserved30: 2; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t rx_en: 1; - uint32_t mem_wr_rst: 1; - uint32_t mem_rst: 1; - uint32_t mem_owner: 1; - uint32_t rx_filter_en: 1; - uint32_t rx_filter_thres: 8; - uint32_t mem_rx_wrap_en: 1; - uint32_t afifo_rst: 1; - uint32_t conf_update: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } conf1; - } rx_conf[2]; - volatile union { - struct { - uint32_t mem_raddr_ex: 9; - uint32_t state: 3; - uint32_t waddr: 9; - uint32_t mem_rd_err: 1; - uint32_t mem_empty: 1; - uint32_t mem_wr_err: 1; - uint32_t raddr: 8; - }; - uint32_t val; - } tx_status[2]; - volatile union { - struct { - uint32_t mem_waddr_ex: 9; - uint32_t reserved9: 3; - uint32_t mem_raddr: 9; - uint32_t reserved21: 1; - uint32_t state: 3; - uint32_t mem_owner_err: 1; - uint32_t mem_full: 1; - uint32_t mem_rd_err: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } rx_status[2]; - volatile union { - struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_rx_end: 1; - uint32_t ch3_rx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_rx_thr_event: 1; - uint32_t ch3_rx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t reserved14: 18; - }; - uint32_t val; - } int_raw; - volatile union { - struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_rx_end: 1; - uint32_t ch3_rx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_rx_thr_event: 1; - uint32_t ch3_rx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t reserved14: 18; - }; - uint32_t val; - } int_st; - volatile union { - struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_rx_end: 1; - uint32_t ch3_rx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_rx_thr_event: 1; - uint32_t ch3_rx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t reserved14: 18; - }; - uint32_t val; - } int_ena; - volatile union { - struct { - uint32_t ch0_tx_end: 1; - uint32_t ch1_tx_end: 1; - uint32_t ch2_rx_end: 1; - uint32_t ch3_rx_end: 1; - uint32_t ch0_err: 1; - uint32_t ch1_err: 1; - uint32_t ch2_err: 1; - uint32_t ch3_err: 1; - uint32_t ch0_tx_thr_event: 1; - uint32_t ch1_tx_thr_event: 1; - uint32_t ch2_rx_thr_event: 1; - uint32_t ch3_rx_thr_event: 1; - uint32_t ch0_tx_loop: 1; - uint32_t ch1_tx_loop: 1; - uint32_t reserved14: 18; - }; - uint32_t val; - } int_clr; - volatile union { - struct { - uint32_t low: 16; - uint32_t high: 16; - }; - uint32_t val; - } tx_carrier[2]; - volatile union { - struct { - uint32_t low_thres: 16; - uint32_t high_thres: 16; - }; - uint32_t val; - } rx_carrier[2]; - volatile union { - struct { - uint32_t limit: 9; - uint32_t tx_loop_num: 10; - uint32_t tx_loop_cnt_en: 1; - uint32_t loop_count_reset: 1; - uint32_t reserved21: 11; - }; - uint32_t val; - } tx_lim[2]; - volatile union { - struct { - uint32_t rx_lim: 9; - uint32_t reserved9: 23; - }; - uint32_t val; - } rx_lim[2]; - volatile union { - struct { - uint32_t fifo_mask: 1; - uint32_t mem_clk_force_on: 1; - uint32_t mem_force_pd: 1; - uint32_t mem_force_pu: 1; - uint32_t sclk_div_num: 8; - uint32_t sclk_div_a: 6; - uint32_t sclk_div_b: 6; - uint32_t sclk_sel: 2; - uint32_t sclk_active: 1; - uint32_t reserved27: 4; - uint32_t clk_en: 1; - }; - uint32_t val; - } sys_conf; - volatile union { - struct { - uint32_t ch0: 1; - uint32_t ch1: 1; - uint32_t en: 1; - uint32_t reserved3: 29; - }; - uint32_t val; - } tx_sim; - volatile union { - struct { - uint32_t ch0: 1; - uint32_t ch1: 1; - uint32_t ch2: 1; - uint32_t ch3: 1; - uint32_t reserved4: 28; - }; - uint32_t val; - } ref_cnt_rst; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - volatile union { - struct { - uint32_t date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } date; -} rmt_dev_t; - -extern rmt_dev_t RMT; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/rtc.h b/components/soc/esp32h4/include/soc/rtc.h deleted file mode 100644 index 338252d5f0..0000000000 --- a/components/soc/esp32h4/include/soc/rtc.h +++ /dev/null @@ -1,918 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include -#include -#include "soc/soc.h" -#include "soc/clk_tree_defs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @file rtc.h - * @brief Low-level RTC power, clock, and sleep functions. - * - * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. - * RTC_CNTL peripheral handles many functions: - * - enables/disables clocks and power to various parts of the chip; this is - * done using direct register access (forcing power up or power down) or by - * allowing state machines to control power and clocks automatically - * - handles sleep and wakeup functions - * - maintains a 48-bit counter which can be used for timekeeping - * - * These functions are not thread safe, and should not be viewed as high level - * APIs. For example, while this file provides a function which can switch - * CPU frequency, this function is on its own is not sufficient to implement - * frequency switching in ESP-IDF context: some coordination with RTOS, - * peripheral drivers, and WiFi/BT stacks is also required. - * - * These functions will normally not be used in applications directly. - * ESP-IDF provides, or will provide, drivers and other facilities to use - * RTC subsystem functionality. - * - * The functions are loosely split into the following groups: - * - rtc_clk: clock switching, calibration - * - rtc_time: reading RTC counter, conversion between counter values and time - * - rtc_sleep: entry into sleep modes - * - rtc_init: initialization - */ - -#define MHZ (1000000) - -#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) -#define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) -#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) - -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, - * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. - * Valid if RTC_CNTL_DBG_ATTEN is 0. - */ -#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias -#define RTC_CNTL_DBIAS_1V00 0 -#define RTC_CNTL_DBIAS_1V05 4 -#define RTC_CNTL_DBIAS_1V10 5 -#define RTC_CNTL_DBIAS_1V15 6 -#define RTC_CNTL_DBIAS_1V20 7 -#define RTC_CNTL_DBIAS_DEFAULT 8 -/* The value of 1V00 can be adjusted between 0~3*/ - - -/* dcdc mode - */ -#define RTC_CNTL_DCDC_TRX_MODE 0b100 -#define RTC_CNTL_DCDC_LSLP_MODE 0b110 -#define RTC_CNTL_DCDC_DSLP_MODE 0b101 -#define RTC_CNTL_DCDC_FREQ_DEFAULT 3 - -#define DCDC_SLP_TRX_MODE 0 -#define DCDC_SLP_LSLP_MODE 1 -#define DCDC_SLP_DSLP_MODE 2 - -#define RTC_CNTL_DIG_DBIAS_0V85 0 -#define RTC_CNTL_DIG_DBIAS_0V90 1 -#define RTC_CNTL_DIG_DBIAS_0V95 2 -#define RTC_CNTL_DIG_DBIAS_1V00 3 -#define RTC_CNTL_DIG_DBIAS_1V05 4 -#define RTC_CNTL_DIG_DBIAS_1V10 5 -#define RTC_CNTL_DIG_DBIAS_1V15 6 -#define RTC_CNTL_DIG_DBIAS_1V20 7 - -/* Delays for various clock sources to be enabled/switched. - * All values are in microseconds. - */ -#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 -#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 -#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 - -/* Core voltage (to be supported) */ -#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 -#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 -#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 - -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 -#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 - -#define RTC_CNTL_CK8M_DFREQ_DEFAULT 600 -#define RTC_CNTL_SCK_DCAP_DEFAULT 128 - - -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) -#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) -#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) -#define RTC_CNTL_MIN_SLP_VAL_MIN (2) - -/* -set sleep_init default param -*/ -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 - -/** - * @brief Possible main XTAL frequency values. - * - * Enum values should be equal to frequency in MHz. - */ -typedef enum { - RTC_XTAL_FREQ_32M = 32, -} rtc_xtal_freq_t; - -/** - * @brief CPU clock configuration structure - */ -typedef struct rtc_cpu_freq_config_s { - soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived - uint32_t source_freq_mhz; //!< Source clock frequency - uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div - uint32_t freq_mhz; //!< CPU clock frequency -} rtc_cpu_freq_config_t; - -#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal - -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - -/** - * @brief Clock source to be calibrated using rtc_clk_cal function - */ -typedef enum { - RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK - RTC_CAL_RC32K = 1, //!< Internal 32 kHz RC oscillator - RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL -} rtc_cal_sel_t; - -/** - * Initialization parameters for rtc_clk_init - */ -typedef struct { - rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency - uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz - soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose - soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose - uint32_t clk_rtc_clk_div : 8; - uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) - uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) - uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) - uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h4 (default 0: xtal_32M) -} rtc_clk_config_t; - -/** - * Default initializer for rtc_clk_config_t - */ -#define RTC_CLK_CONFIG_DEFAULT() { \ - .xtal_freq = CONFIG_XTAL_FREQ, \ - .cpu_freq_mhz = 32, \ - .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ - .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ - .clk_rtc_clk_div = 1, \ - .clk_8m_clk_div = 1, \ - .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ - .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ - .root_clk_slt = 0, \ -} - -typedef struct { - uint16_t wifi_powerup_cycles : 7; - uint16_t wifi_wait_cycles : 9; - uint16_t bt_powerup_cycles : 7; - uint16_t bt_wait_cycles : 9; - uint16_t cpu_top_powerup_cycles : 7; - uint16_t cpu_top_wait_cycles : 9; - uint16_t dg_wrap_powerup_cycles : 7; - uint16_t dg_wrap_wait_cycles : 9; - uint16_t dg_peri_powerup_cycles : 7; - uint16_t dg_peri_wait_cycles : 9; -} rtc_init_config_t; - -#define RTC_INIT_CONFIG_DEFAULT() { \ - .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ - .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ - .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ - .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ - .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ - .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ -} - -void rtc_clk_divider_set(uint32_t div); - -void rtc_clk_8m_divider_set(uint32_t div); - -/** - * Initialize clocks and set CPU frequency - * - * @param cfg clock configuration as rtc_clk_config_t - */ -void rtc_clk_init(rtc_clk_config_t cfg); - -/** - * @brief Get main XTAL frequency - * - * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to - * rtc_clk_init function - * - * @return XTAL frequency, one of rtc_xtal_freq_t - */ -rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); - -/** - * @brief Update XTAL frequency - * - * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored - * after startup. - * - * @param xtal_freq New frequency value - */ -void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); - -/** - * @brief Enable or disable 32 kHz XTAL oscillator - * @param en true to enable, false to disable - */ -void rtc_clk_32k_enable(bool en); - -/** - * @brief Configure 32 kHz XTAL oscillator to accept external clock signal - */ -void rtc_clk_32k_enable_external(void); - -/** - * @brief Get the state of 32k XTAL oscillator - * @return true if 32k XTAL oscillator has been enabled - */ -bool rtc_clk_32k_enabled(void); - -/** - * @brief Enable 32k oscillator, configuring it for fast startup time. - * Note: to achieve higher frequency stability, rtc_clk_32k_enable function - * must be called one the 32k XTAL oscillator has started up. This function - * will initially disable the 32k XTAL oscillator, so it should not be called - * when the system is using 32k XTAL as RTC_SLOW_CLK. - * - * @param cycle Number of 32kHz cycles to bootstrap external crystal. - * If 0, no square wave will be used to bootstrap crystal oscillation. - */ -void rtc_clk_32k_bootstrap(uint32_t cycle); - -/** - * @brief Enable or disable 32 kHz internal rc oscillator - * @param en true to enable, false to disable - */ -void rtc_clk_rc32k_enable(bool enable); - -/** - * @brief Enable or disable 8 MHz internal oscillator - * - * Output from 8 MHz internal oscillator is passed into a configurable - * divider, which by default divides the input clock frequency by 256. - * Output of the divider may be used as RTC_SLOW_CLK source. - * Output of the divider is referred to in register descriptions and code as - * 8md256 or simply d256. Divider values other than 256 may be configured, but - * this facility is not currently needed, so is not exposed in the code. - * - * When 8MHz/256 divided output is not needed, the divider should be disabled - * to reduce power consumption. - * - * @param clk_8m_en true to enable 8MHz generator - * @param d256_en true to enable /256 divider - */ -void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); - -/** - * @brief Get the state of 8 MHz internal oscillator - * @return true if the oscillator is enabled - */ -bool rtc_clk_8m_enabled(void); - -/** - * @brief Get the state of /256 divider which is applied to 8MHz clock - * @return true if the divided output is enabled - */ -bool rtc_clk_8md256_enabled(void); - -/** - * @brief Select source for RTC_SLOW_CLK - * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) - */ -void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); - -/** - * @brief Get the RTC_SLOW_CLK source - * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) - */ -soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); - -/** - * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000 - * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 - * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~33000 - * - * rtc_clk_cal function can be used to get more precise value by comparing - * RTC_SLOW_CLK frequency to the frequency of main XTAL. - * - * @return RTC_SLOW_CLK frequency, in Hz - */ -uint32_t rtc_clk_slow_freq_get_hz(void); - -/** - * @brief Select source for RTC_FAST_CLK - * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) - */ -void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); - -/** - * @brief Get the RTC_FAST_CLK source - * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) - */ -soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); - -/** - * @brief Get CPU frequency config for a given frequency - * @param freq_mhz Frequency in MHz - * @param[out] out_config Output, CPU frequency configuration structure - * @return true if frequency can be obtained, false otherwise - */ -bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); - -/** - * @brief Switch CPU frequency - * - * This function sets CPU frequency according to the given configuration - * structure. It enables PLLs, if necessary. - * - * @note This function in not intended to be called by applications in FreeRTOS - * environment. This is because it does not adjust various timers based on the - * new CPU frequency. - * - * @param config CPU frequency configuration structure - */ -void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); - -/** - * @brief Switch CPU frequency (optimized for speed) - * - * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. - * It works faster because it does not disable PLLs when switching from PLL to - * XTAL and does not enabled them when switching back. If PLL is not already - * enabled when this function is called to switch from XTAL to PLL frequency, - * or the PLL which is enabled is the wrong one, this function will fall back - * to calling rtc_clk_cpu_freq_set_config. - * - * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, - * so it is less safe to use it e.g. from a panic handler (when memory might - * be corrupted). - * - * @note This function in not intended to be called by applications in FreeRTOS - * environment. This is because it does not adjust various timers based on the - * new CPU frequency. - * - * @param config CPU frequency configuration structure - */ -void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); - -/** - * @brief Get the currently used CPU frequency configuration - * @param[out] out_config Output, CPU frequency configuration structure - */ -void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); - -/** - * @brief Switch CPU clock source to XTAL - * - * Short form for filling in rtc_cpu_freq_config_t structure and calling - * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. - * Assumes that XTAL frequency has been determined — don't call in startup code. - */ -void rtc_clk_cpu_freq_set_xtal(void); - -/** - * @brief Store new APB frequency value into RTC_APB_FREQ_REG - * - * This function doesn't change any hardware clocks. - * - * Functions which perform frequency switching and change APB frequency call - * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG - * (one of RTC general purpose retention registers). This should not normally - * be called from application code. - * - * @param apb_freq new APB frequency, in Hz - */ -void rtc_clk_apb_freq_update(uint32_t apb_freq); - -/** - * @brief Get the current stored APB frequency. - * @return The APB frequency value computed from upstream, in Hz. - */ -uint32_t rtc_clk_apb_freq_get(void); - -void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div); - -uint32_t rtc_clk_select_root_clk(soc_cpu_clk_src_t cpu_clk_src); - -uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); - -/** - * @brief Measure RTC slow clock's period, based on main XTAL frequency - * - * This function will time out and return 0 if the time for the given number - * of cycles to be counted exceeds the expected time twice. This may happen if - * 32k XTAL is being calibrated, but the oscillator has not started up (due to - * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). - * - * @note When 32k CLK is being calibrated, this function will check the accuracy - * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if - * the check fails, then consider this an invalid 32k clock and return 0. This - * check can filter some jamming signal. - * - * @param cal_clk clock to be measured - * @param slow_clk_cycles number of slow clock cycles to average - * @return average slow clock period in microseconds, Q13.19 fixed point format, - * or 0 if calibration has timed out - */ -uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); - -/** - * @brief Measure ratio between XTAL frequency and RTC slow clock frequency - * @param cal_clk slow clock to be measured - * @param slow_clk_cycles number of slow clock cycles to average - * @return average ratio between XTAL frequency and slow clock frequency, - * Q13.19 fixed point format, or 0 if calibration has timed out. - */ -uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); - -/** - * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles - * @param time_in_us Time interval in microseconds - * @param slow_clk_period Period of slow clock in microseconds, Q13.19 - * fixed point format (as returned by rtc_slowck_cali). - * @return number of slow clock cycles - */ -uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); - -/** - * @brief Convert time interval from RTC_SLOW_CLK to microseconds - * @param time_in_us Time interval in RTC_SLOW_CLK cycles - * @param slow_clk_period Period of slow clock in microseconds, Q13.19 - * fixed point format (as returned by rtc_slowck_cali). - * @return time interval in microseconds - */ -uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); - -/** - * @brief Get current value of RTC counter - * - * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK - * cycles. Counter value is not writable by software. The value is not adjusted - * when switching to a different RTC_SLOW_CLK source. - * - * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute - * - * @return current value of RTC counter - */ -uint64_t rtc_time_get(void); - -/** - * @brief Busy loop until next RTC_SLOW_CLK cycle - * - * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. - * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return - * one RTC_SLOW_CLK cycle later. - */ -void rtc_clk_wait_for_slow_cycle(void); - -/** - * @brief Enable the rtc digital 8M clock - * - * This function is used to enable the digital rtc 8M clock to support peripherals. - * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. - */ -void rtc_dig_clk8m_enable(void); - -/** - * @brief Disable the rtc digital 8M clock - * - * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. - */ -void rtc_dig_clk8m_disable(void); - -/** - * @brief Get whether the rtc digital 8M clock is enabled - */ -bool rtc_dig_8m_enabled(void); - -/** - * @brief Calculate the real clock value after the clock calibration - * - * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` - * @return Frequency of the clock in Hz - */ -uint32_t rtc_clk_freq_cal(uint32_t cal_val); - -/** - * @brief Power down flags for rtc_sleep_pd function - */ -typedef struct { - uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep - uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep - uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep - uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep - uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep - uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep - uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep - uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep - uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep -} rtc_sleep_pu_config_t; - -/** - * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value - */ -#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ - .dig_fpu = (val), \ - .rtc_fpu = (val), \ - .cpu_fpu = (val), \ - .i2s_fpu = (val), \ - .bb_fpu = (val), \ - .nrx_fpu = (val), \ - .fe_fpu = (val), \ - .sram_fpu = (val), \ - .rom_ram_fpu = (val), \ -} - -void rtc_sleep_pu(rtc_sleep_pu_config_t cfg); - -/** - * @brief sleep configuration for rtc_sleep_init function - */ -typedef struct { - uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) - uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) - uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory - uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory - uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals - uint32_t dig_ret_pd_en : 1; //!< power down dig_ret - uint32_t bt_pd_en : 1; //!< power down BT - uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. - uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator - uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals - uint32_t deep_slp : 1; //!< power down digital domain - uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode - uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode - uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode - uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode - uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode - uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode - uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode - uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator - uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep - uint32_t deep_slp_reject : 1; //!< enable deep sleep reject - uint32_t light_slp_reject : 1; //!< enable light sleep reject -} rtc_sleep_config_t; - -#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) -#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals -#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory -#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory -#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU -#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator -#define RTC_SLEEP_PD_DIG_RET BIT(6) //!< Power down WIFI -#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT -#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart -#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals -#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator -#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL - -//These flags are not power domains, but will affect some sleep parameters -#define RTC_SLEEP_DIG_USE_8M BIT(16) -#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) -#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature - -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); - -/** - * @brief Prepare the chip to enter sleep mode - * - * This function configures various power control state machines to handle - * entry into light sleep or deep sleep mode, switches APB and CPU clock source - * (usually to XTAL), and sets bias voltages for digital and RTC power domains. - * - * This function does not actually enter sleep mode; this is done using - * rtc_sleep_start function. Software may do some other actions between - * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure - * wakeup sources. - * @param cfg sleep mode configuration - */ -void rtc_sleep_init(rtc_sleep_config_t cfg); - -/** - * @brief Low level initialize for rtc state machine waiting cycles after waking up - * - * This function configures the cycles chip need to wait for internal 8MHz - * oscillator and external 40MHz crystal. As we configure fixed time for waiting - * crystal, we need to pass period to calculate cycles. Now this function only - * used in lightsleep mode. - * - * @param slowclk_period re-calibrated slow clock period - */ -void rtc_sleep_low_init(uint32_t slowclk_period); - -#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup -#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup -#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only) -#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) -#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) -#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) -#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) -#define RTC_USB_TRIG_EN BIT(14) -#define RTC_BROWNOUT_DET_TRIG_EN BIT(16) - -/** - * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip - */ -#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN | \ - RTC_TIMER_TRIG_EN | \ - RTC_WIFI_TRIG_EN | \ - RTC_UART0_TRIG_EN | \ - RTC_UART1_TRIG_EN | \ - RTC_BT_TRIG_EN | \ - RTC_XTAL32K_DEAD_TRIG_EN | \ - RTC_USB_TRIG_EN | \ - RTC_BROWNOUT_DET_TRIG_EN) - -/** - * @brief Enter deep or light sleep mode - * - * This function enters the sleep mode previously configured using rtc_sleep_init - * function. Before entering sleep, software should configure wake up sources - * appropriately (set up GPIO wakeup registers, timer wakeup registers, - * and so on). - * - * If deep sleep mode was configured using rtc_sleep_init, and sleep is not - * rejected by hardware (based on reject_opt flags), this function never returns. - * When the chip wakes up from deep sleep, CPU is reset and execution starts - * from ROM bootloader. - * - * If light sleep mode was configured using rtc_sleep_init, this function - * returns on wakeup, or if sleep is rejected by hardware. - * - * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags - * combined with OR) - * @param reject_opt bit mask of sleep reject reasons: - * - RTC_CNTL_GPIO_REJECT_EN - * - RTC_CNTL_SDIO_REJECT_EN - * These flags are used to prevent entering sleep when e.g. - * an external host is communicating via SDIO slave - * @return non-zero if sleep was rejected by hardware - */ -uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); - -/** - * @brief Enter deep sleep mode - * - * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value - * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake - * stub is valid to execute (if a wake address is set). - * - * No RAM is accessed while calculating the CRC and going into deep sleep, which makes - * this function safe to use even if the caller's stack is in RTC FAST memory. - * - * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will - * have the same effect and takes less time as CRC calculation is skipped. - * - * @note This function should only be called after rtc_sleep_init() has been called to - * configure the system for deep sleep. - * - * @param wakeup_opt - same as for rtc_sleep_start - * @param reject_opt - same as for rtc_sleep_start - * - * @return non-zero if sleep was rejected by hardware - */ -uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); - -/** - * RTC power and clock control initialization settings - */ -typedef struct { - uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready - uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready - uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready - uint32_t clkctl_init : 1; //!< Perform clock control related initialization - uint32_t pwrctl_init : 1; //!< Perform power control related initialization - uint32_t xtal_fpu : 1; - uint32_t bbpll_fpu : 1; - uint32_t cpu_waiti_clk_gate : 1; - uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise. - uint32_t pmu_ctl : 1; -} rtc_config_t; - -/** - * Default initializer of rtc_config_t. - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use). - */ -#define RTC_CONFIG_DEFAULT() {\ - .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ - .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ - .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ - .clkctl_init = 1, \ - .pwrctl_init = 1, \ - .xtal_fpu = 0, \ - .bbpll_fpu = 0, \ - .cpu_waiti_clk_gate = 1, \ - .cali_ocode = 0, \ - .pmu_ctl = 1\ -} -typedef struct { - /* data */ - uint32_t or_en_cont_cal : 1; //!< default:0 rtc_init:0 pvt can be enable by either this register or digital -- if_en_cont_cal - uint32_t enx_rtc_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure rtc regulator voltage level instead of pvt result -- int_dreg - uint32_t enx_dig_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure dig regulator voltage level instead of pvt result -- int_dreg - uint32_t en_i2c_rtc_dreg : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg; 0: if_rtc_dreg - uint32_t en_i2c_dig_dreg : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg; 0: if_dig_dreg - uint32_t en_i2c_rtc_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg_slp; 0: if_rtc_dreg_slp - uint32_t en_i2c_dig_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg_slp; 0: if_dig_dreg_slp - uint32_t or_xpd_rtc_slave_3p3 : 1; //!< default:1 rtc_init:0 to turn off rtc slave, which is only required before DCDC running - uint32_t or_xpd_rtc_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_rtc_reg - uint32_t or_xpd_dig_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dig_reg - uint32_t or_pd_rtc_reg_slp : 1; //!< default:0 rtc_init:1 configure this i2c to control rtc_sleep_regulator on off, no coressponding digital control signal - uint32_t or_pd_dig_reg_slp : 1; //!< default:0 rtc_init:0 default value 0 puts dig_sleep_regulator controlled by digital -- if_xpd_dig_reg_slp - uint32_t or_xpd_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dcdc - uint32_t or_disalbe_deep_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_deep_sleep_dcdc - uint32_t or_disalbe_light_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_light_sleep_dcdc - uint32_t or_enalbe_trx_mode_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_trx_mode_dcdc - uint32_t or_enx_reg_dcdc : 1; //!< default:0 rtc_init:1 handover dcdc configuration registers to digital control signals, including popenb, sstime, ccm, vset, fsw, dcmlevel, dcm2enb, ramp, ramplevel - uint32_t or_unlock_dcdc : 1; //!< default:0 rtc_init:0 not used in this version of silicon, can be unleashed if metal change if_vgood_lock_dcdc signal to high - uint32_t or_force_lock_dcdc : 1; //!< default:0 rtc_init:0 dcdc will be locked and shut-off if this register sets to 1 - uint32_t or_enb_slow_clk : 1; //!< default:0 rtc_init:1 handover slow clock control to digital -- if_enb_slow_clk - uint32_t or_xpd_trx : 1; //!< default:1 rtc_init:0 handover trx control to digital -- if_xpd_trx - uint32_t or_en_reset_chip : 1; //!< default:0 rtc_init:1 handover reset chip control to digital -- if_reset_chip - uint32_t or_force_xpd_reg_slave : 1; //!< default:0 rtc_init:1 set this reg to 1 after DCDC ready, to have rtc & dig slave control independent of DCDC status -} pmu_config_t; - -#define PMU_CONFIG_DEFAULT() {\ - .or_en_cont_cal = 0, \ - .enx_rtc_dreg = 1, \ - .enx_dig_dreg = 1, \ - .en_i2c_rtc_dreg = 0, \ - .en_i2c_dig_dreg = 0, \ - .en_i2c_rtc_dreg_slp = 0, \ - .en_i2c_dig_dreg_slp = 0, \ - .or_xpd_rtc_slave_3p3 = 0, \ - .or_xpd_rtc_reg = 0, \ - .or_xpd_dig_reg = 0, \ - .or_pd_rtc_reg_slp = 0, \ - .or_pd_dig_reg_slp = 0, \ - .or_xpd_dcdc = 0, \ - .or_disalbe_deep_sleep_dcdc = 0, \ - .or_disalbe_light_sleep_dcdc = 0, \ - .or_enalbe_trx_mode_dcdc = 0, \ - .or_enx_reg_dcdc = 1, \ - .or_unlock_dcdc = 0, \ - .or_force_lock_dcdc = 0, \ - .or_xpd_trx = 0, \ - .or_en_reset_chip = 1, \ - .or_force_xpd_reg_slave = 1\ -} - -typedef struct { - uint32_t swt_idle: 1; //!< If 1, swt_idle is sleep mode ; if 0, swt_idle is active mode - uint32_t swt_monitor: 1; //!< If 1, swt_monitor is sleep mode ; if 0, swt_monitor is active mode - uint32_t swt_slp: 1; //!< If 1, swt_slp is sleep mode ; if 0, swt_slp is active mode -} dbias_swt_cfg_t; - -#define DBIAS_SWITCH_CONFIG_DEFAULT(){\ - .swt_idle = 0, \ - .swt_monitor = 1, \ - .swt_slp = 1\ -} - -typedef struct { - /* data */ - uint32_t dig_regul0_en: 1; //!< If 1, dig_regulator0 is ctl by fsm; if 0, dig_regulator0 force pd. - uint32_t dig_regul1_en: 1; //!< If 1, dig_regulator1 is ctl by fsm; if 0, dig_regulator1 force pd. - uint32_t rtc_regul0_en: 1; //!< If 1, rtc_regulator0 is ctl by fsm; if 0, rtc_regulator0 force pd. -} regulator_cfg_t; - -#define REGULATOR_SET_DEFAULT(){\ - .dig_regul0_en = 1, \ - .dig_regul1_en = 1, \ - .rtc_regul0_en = 1, \ -} - -/** -* Initialize RTC clock and power control related functions -* @param cfg configuration options as rtc_config_t -*/ -void rtc_init(rtc_config_t cfg); - -/** - * Regulator config - */ -typedef struct { - uint32_t dig_source : 1; - uint32_t dig_active_dbias : 5; - uint32_t dig_slp_dbias : 5; - uint32_t rtc_source : 1; - uint32_t rtc_active_dbias : 5; - uint32_t rtc_slp_dbias : 5; -} regulator_config_t; - -#define REGULATOR0_CONFIG_DEFAULT() {\ - .dig_source = 0, \ - .dig_active_dbias = 20, \ - .dig_slp_dbias = 8, \ - .rtc_source = 0, \ - .rtc_active_dbias = 20, \ - .rtc_slp_dbias = 8 \ -} -#define REGULATOR1_CONFIG_DEFAULT() {\ - .dig_source = 1, \ - .dig_active_dbias = 15, \ - .dig_slp_dbias = 8, \ - .rtc_source = 1, \ - .rtc_active_dbias = 15, \ - .rtc_slp_dbias = 8 \ -} - - -// -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- -// **WARNING**: The following are only for backwards compatibility. -// Please use the declarations in soc/clk_tree_defs.h instead. -/** - * @brief CPU clock source - */ -typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; -#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL -#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (96M) -#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 8M RTC oscillator -#define RTC_CPU_FREQ_SRC_XTAL_D2 SOC_CPU_CLK_SRC_XTAL_D2 //!< XTAL/2 - -/** - * @brief RTC SLOW_CLK frequency values - */ -typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; -#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator -#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL -#define RTC_SLOW_FREQ_RC32K SOC_RTC_SLOW_CLK_SRC_RC32K //!< Internal 32 KHz RC oscillator - -/** - * @brief RTC FAST_CLK frequency values - */ -typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; -#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 -#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator - -/* Alias of frequency related macros */ -#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX -#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX -#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX -#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX -#define RTC_SLOW_CLK_FREQ_RC32 SOC_CLK_RC32K_FREQ_APPROX - -/* Alias of deprecated function names */ -#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) -#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() -#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) -#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/rtc_i2c_reg.h b/components/soc/esp32h4/include/soc/rtc_i2c_reg.h deleted file mode 100644 index efbe904b4e..0000000000 --- a/components/soc/esp32h4/include/soc/rtc_i2c_reg.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_RTC_I2C_REG_H_ -#define _SOC_RTC_I2C_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) -/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 0*/ -#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) -#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_LOW_PERIOD_S 0 - -#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004) -/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: rtc i2c reg clk gating*/ -#define RTC_I2C_CLK_EN (BIT(31)) -#define RTC_I2C_CLK_EN_M (BIT(31)) -#define RTC_I2C_CLK_EN_V 0x1 -#define RTC_I2C_CLK_EN_S 31 -/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: rtc i2c sw reset*/ -#define RTC_I2C_RESET (BIT(30)) -#define RTC_I2C_RESET_M (BIT(30)) -#define RTC_I2C_RESET_V 0x1 -#define RTC_I2C_RESET_S 30 -/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 -#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 -/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: receive lsb first*/ -#define RTC_I2C_RX_LSB_FIRST (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_V 0x1 -#define RTC_I2C_RX_LSB_FIRST_S 5 -/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: transit lsb first*/ -#define RTC_I2C_TX_LSB_FIRST (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_V 0x1 -#define RTC_I2C_TX_LSB_FIRST_S 4 -/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: force start*/ -#define RTC_I2C_TRANS_START (BIT(3)) -#define RTC_I2C_TRANS_START_M (BIT(3)) -#define RTC_I2C_TRANS_START_V 0x1 -#define RTC_I2C_TRANS_START_S 3 -/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1=master 0=slave*/ -#define RTC_I2C_MS_MODE (BIT(2)) -#define RTC_I2C_MS_MODE_M (BIT(2)) -#define RTC_I2C_MS_MODE_V 0x1 -#define RTC_I2C_MS_MODE_S 2 -/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: 1=push pull 0=open drain*/ -#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_V 0x1 -#define RTC_I2C_SCL_FORCE_OUT_S 1 -/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1=push pull 0=open drain*/ -#define RTC_I2C_SDA_FORCE_OUT (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_V 0x1 -#define RTC_I2C_SDA_FORCE_OUT_S 0 - -#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008) -/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: scl last status*/ -#define RTC_I2C_SCL_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S)) -#define RTC_I2C_SCL_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_STATE_LAST_S 28 -/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: i2c last main status*/ -#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S)) -#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 -/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: shifter content*/ -#define RTC_I2C_SHIFT 0x000000FF -#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S)) -#define RTC_I2C_SHIFT_V 0xFF -#define RTC_I2C_SHIFT_S 16 -/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: which operation is working*/ -#define RTC_I2C_OP_CNT 0x00000003 -#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S)) -#define RTC_I2C_OP_CNT_V 0x3 -#define RTC_I2C_OP_CNT_S 6 -/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: One byte transit done*/ -#define RTC_I2C_BYTE_TRANS (BIT(5)) -#define RTC_I2C_BYTE_TRANS_M (BIT(5)) -#define RTC_I2C_BYTE_TRANS_V 0x1 -#define RTC_I2C_BYTE_TRANS_S 5 -/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: slave reg sub address*/ -#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 -#define RTC_I2C_SLAVE_ADDRESSED_S 4 -/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: bus is busy*/ -#define RTC_I2C_BUS_BUSY (BIT(3)) -#define RTC_I2C_BUS_BUSY_M (BIT(3)) -#define RTC_I2C_BUS_BUSY_V 0x1 -#define RTC_I2C_BUS_BUSY_S 3 -/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: arbitration is lost*/ -#define RTC_I2C_ARB_LOST (BIT(2)) -#define RTC_I2C_ARB_LOST_M (BIT(2)) -#define RTC_I2C_ARB_LOST_V 0x1 -#define RTC_I2C_ARB_LOST_S 2 -/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: slave read or write*/ -#define RTC_I2C_SLAVE_RW (BIT(1)) -#define RTC_I2C_SLAVE_RW_M (BIT(1)) -#define RTC_I2C_SLAVE_RW_V 0x1 -#define RTC_I2C_SLAVE_RW_S 1 -/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: ack response*/ -#define RTC_I2C_ACK_REC (BIT(0)) -#define RTC_I2C_ACK_REC_M (BIT(0)) -#define RTC_I2C_ACK_REC_V 0x1 -#define RTC_I2C_ACK_REC_S 0 - -#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c) -/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ -/*description: time out threshold*/ -#define RTC_I2C_TIMEOUT 0x000FFFFF -#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) -#define RTC_I2C_TIMEOUT_V 0xFFFFF -#define RTC_I2C_TIMEOUT_S 0 - -#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010) -/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c 10bit mode enable*/ -#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_V 0x1 -#define RTC_I2C_ADDR_10BIT_EN_S 31 -/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: slave address*/ -#define RTC_I2C_SLAVE_ADDR 0x00007FFF -#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) -#define RTC_I2C_SLAVE_ADDR_V 0x7FFF -#define RTC_I2C_SLAVE_ADDR_S 0 - -#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014) -/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 1*/ -#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) -#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_S 0 - -#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018) -/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ -/*description: time period for SDA to toggle after SCL goes low*/ -#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF -#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S)) -#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF -#define RTC_I2C_SDA_DUTY_NUM_S 0 - -#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c) -/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to toggle after I2C start is triggered*/ -#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) -#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_START_PERIOD_S 0 - -#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020) -/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to stop after I2C end is triggered*/ -#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) -#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_STOP_PERIOD_S 0 - -#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024) -/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: clear detect start interrupt*/ -#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 -#define RTC_I2C_DETECT_START_INT_CLR_S 8 -/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: clear transit load data complete interrupt*/ -#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_TX_DATA_INT_CLR_S 7 -/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: clear receive data interrupt*/ -#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_RX_DATA_INT_CLR_S 6 -/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: clear ack error interrupt*/ -#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 -#define RTC_I2C_ACK_ERR_INT_CLR_S 5 -/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: clear time out interrupt*/ -#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 -#define RTC_I2C_TIMEOUT_INT_CLR_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: clear transit complete interrupt*/ -#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: clear master transit complete interrupt*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear arbitration lost interrupt*/ -#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: clear slave transit complete interrupt*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 - -#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028) -/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt raw*/ -#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 -#define RTC_I2C_DETECT_START_INT_RAW_S 8 -/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt raw*/ -#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_TX_DATA_INT_RAW_S 7 -/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt raw*/ -#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_RX_DATA_INT_RAW_S 6 -/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt raw*/ -#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 -#define RTC_I2C_ACK_ERR_INT_RAW_S 5 -/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt raw*/ -#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 -#define RTC_I2C_TIMEOUT_INT_RAW_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt raw*/ -#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt raw*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt raw*/ -#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt raw*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 - -#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c) -/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt state*/ -#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_V 0x1 -#define RTC_I2C_DETECT_START_INT_ST_S 8 -/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt state*/ -#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_V 0x1 -#define RTC_I2C_TX_DATA_INT_ST_S 7 -/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt state*/ -#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_V 0x1 -#define RTC_I2C_RX_DATA_INT_ST_S 6 -/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt state*/ -#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ST_S 5 -/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt state*/ -#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ST_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt state*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt state*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt state*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt state*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 - -#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030) -/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable detect start interrupt*/ -#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 -#define RTC_I2C_DETECT_START_INT_ENA_S 8 -/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable transit data interrupt*/ -#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_TX_DATA_INT_ENA_S 7 -/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable receive data interrupt*/ -#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_RX_DATA_INT_ENA_S 6 -/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable eack error interrupt*/ -#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ENA_S 5 -/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable time out interrupt*/ -#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ENA_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable transit complete interrupt*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable master transit complete interrupt*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable arbitration lost interrupt*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable slave transit complete interrupt*/ -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 - -#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034) -/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c done*/ -#define RTC_I2C_DONE (BIT(31)) -#define RTC_I2C_DONE_M (BIT(31)) -#define RTC_I2C_DONE_V 0x1 -#define RTC_I2C_DONE_S 31 -/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: data sent by slave*/ -#define RTC_I2C_SLAVE_TX_DATA 0x000000FF -#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S)) -#define RTC_I2C_SLAVE_TX_DATA_V 0xFF -#define RTC_I2C_SLAVE_TX_DATA_S 8 -/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: data received*/ -#define RTC_I2C_RDATA 0x000000FF -#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S)) -#define RTC_I2C_RDATA_V 0xFF -#define RTC_I2C_RDATA_S 0 - -#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038) -/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command0_done*/ -#define RTC_I2C_COMMAND0_DONE (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_V 0x1 -#define RTC_I2C_COMMAND0_DONE_S 31 -/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command0*/ -#define RTC_I2C_COMMAND0 0x00003FFF -#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S)) -#define RTC_I2C_COMMAND0_V 0x3FFF -#define RTC_I2C_COMMAND0_S 0 - -#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c) -/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command1_done*/ -#define RTC_I2C_COMMAND1_DONE (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_V 0x1 -#define RTC_I2C_COMMAND1_DONE_S 31 -/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command1*/ -#define RTC_I2C_COMMAND1 0x00003FFF -#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S)) -#define RTC_I2C_COMMAND1_V 0x3FFF -#define RTC_I2C_COMMAND1_S 0 - -#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040) -/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command2_done*/ -#define RTC_I2C_COMMAND2_DONE (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_V 0x1 -#define RTC_I2C_COMMAND2_DONE_S 31 -/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ -/*description: command2*/ -#define RTC_I2C_COMMAND2 0x00003FFF -#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S)) -#define RTC_I2C_COMMAND2_V 0x3FFF -#define RTC_I2C_COMMAND2_S 0 - -#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044) -/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command3_done*/ -#define RTC_I2C_COMMAND3_DONE (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_V 0x1 -#define RTC_I2C_COMMAND3_DONE_S 31 -/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command3*/ -#define RTC_I2C_COMMAND3 0x00003FFF -#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S)) -#define RTC_I2C_COMMAND3_V 0x3FFF -#define RTC_I2C_COMMAND3_S 0 - -#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048) -/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command4_done*/ -#define RTC_I2C_COMMAND4_DONE (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_V 0x1 -#define RTC_I2C_COMMAND4_DONE_S 31 -/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command4*/ -#define RTC_I2C_COMMAND4 0x00003FFF -#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S)) -#define RTC_I2C_COMMAND4_V 0x3FFF -#define RTC_I2C_COMMAND4_S 0 - -#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c) -/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command5_done*/ -#define RTC_I2C_COMMAND5_DONE (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_V 0x1 -#define RTC_I2C_COMMAND5_DONE_S 31 -/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command5*/ -#define RTC_I2C_COMMAND5 0x00003FFF -#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S)) -#define RTC_I2C_COMMAND5_V 0x3FFF -#define RTC_I2C_COMMAND5_S 0 - -#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050) -/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command6_done*/ -#define RTC_I2C_COMMAND6_DONE (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_V 0x1 -#define RTC_I2C_COMMAND6_DONE_S 31 -/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command6*/ -#define RTC_I2C_COMMAND6 0x00003FFF -#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S)) -#define RTC_I2C_COMMAND6_V 0x3FFF -#define RTC_I2C_COMMAND6_S 0 - -#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054) -/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command7_done*/ -#define RTC_I2C_COMMAND7_DONE (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_V 0x1 -#define RTC_I2C_COMMAND7_DONE_S 31 -/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ -/*description: command7*/ -#define RTC_I2C_COMMAND7 0x00003FFF -#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S)) -#define RTC_I2C_COMMAND7_V 0x3FFF -#define RTC_I2C_COMMAND7_S 0 - -#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058) -/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command8_done*/ -#define RTC_I2C_COMMAND8_DONE (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_V 0x1 -#define RTC_I2C_COMMAND8_DONE_S 31 -/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command8*/ -#define RTC_I2C_COMMAND8 0x00003FFF -#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S)) -#define RTC_I2C_COMMAND8_V 0x3FFF -#define RTC_I2C_COMMAND8_S 0 - -#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c) -/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command9_done*/ -#define RTC_I2C_COMMAND9_DONE (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_V 0x1 -#define RTC_I2C_COMMAND9_DONE_S 31 -/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command9*/ -#define RTC_I2C_COMMAND9 0x00003FFF -#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S)) -#define RTC_I2C_COMMAND9_V 0x3FFF -#define RTC_I2C_COMMAND9_S 0 - -#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060) -/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command10_done*/ -#define RTC_I2C_COMMAND10_DONE (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_V 0x1 -#define RTC_I2C_COMMAND10_DONE_S 31 -/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command10*/ -#define RTC_I2C_COMMAND10 0x00003FFF -#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S)) -#define RTC_I2C_COMMAND10_V 0x3FFF -#define RTC_I2C_COMMAND10_S 0 - -#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064) -/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command11_done*/ -#define RTC_I2C_COMMAND11_DONE (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_V 0x1 -#define RTC_I2C_COMMAND11_DONE_S 31 -/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command11*/ -#define RTC_I2C_COMMAND11 0x00003FFF -#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S)) -#define RTC_I2C_COMMAND11_V 0x3FFF -#define RTC_I2C_COMMAND11_S 0 - -#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068) -/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command12_done*/ -#define RTC_I2C_COMMAND12_DONE (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_V 0x1 -#define RTC_I2C_COMMAND12_DONE_S 31 -/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command12*/ -#define RTC_I2C_COMMAND12 0x00003FFF -#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S)) -#define RTC_I2C_COMMAND12_V 0x3FFF -#define RTC_I2C_COMMAND12_S 0 - -#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c) -/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command13_done*/ -#define RTC_I2C_COMMAND13_DONE (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_V 0x1 -#define RTC_I2C_COMMAND13_DONE_S 31 -/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command13*/ -#define RTC_I2C_COMMAND13 0x00003FFF -#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S)) -#define RTC_I2C_COMMAND13_V 0x3FFF -#define RTC_I2C_COMMAND13_S 0 - -#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070) -/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command14_done*/ -#define RTC_I2C_COMMAND14_DONE (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_V 0x1 -#define RTC_I2C_COMMAND14_DONE_S 31 -/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command14*/ -#define RTC_I2C_COMMAND14 0x00003FFF -#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S)) -#define RTC_I2C_COMMAND14_V 0x3FFF -#define RTC_I2C_COMMAND14_S 0 - -#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074) -/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command15_done*/ -#define RTC_I2C_COMMAND15_DONE (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_V 0x1 -#define RTC_I2C_COMMAND15_DONE_S 31 -/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command15*/ -#define RTC_I2C_COMMAND15 0x00003FFF -#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S)) -#define RTC_I2C_COMMAND15_V 0x3FFF -#define RTC_I2C_COMMAND15_S 0 - -#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) -/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ -/*description: */ -#define RTC_I2C_DATE 0x0FFFFFFF -#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) -#define RTC_I2C_DATE_V 0xFFFFFFF -#define RTC_I2C_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_RTC_I2C_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/rtc_i2c_struct.h b/components/soc/esp32h4/include/soc/rtc_i2c_struct.h deleted file mode 100644 index 69ea0c0b00..0000000000 --- a/components/soc/esp32h4/include/soc/rtc_i2c_struct.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_RTC_I2C_STRUCT_H_ -#define _SOC_RTC_I2C_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct rtc_i2c_dev_s { - union { - struct { - uint32_t period: 20; /*time period that scl = 0*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_low; - union { - struct { - uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/ - uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/ - uint32_t ms_mode: 1; /*1=master 0=slave*/ - uint32_t trans_start: 1; /*force start*/ - uint32_t tx_lsb_first: 1; /*transit lsb first*/ - uint32_t rx_lsb_first: 1; /*receive lsb first*/ - uint32_t reserved6: 23; - uint32_t i2c_ctrl_clk_gate_en: 1; - uint32_t i2c_reset: 1; /*rtc i2c sw reset*/ - uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t ack_rec: 1; /*ack response*/ - uint32_t slave_rw: 1; /*slave read or write*/ - uint32_t arb_lost: 1; /*arbitration is lost*/ - uint32_t bus_busy: 1; /*bus is busy*/ - uint32_t slave_addressed: 1; /*slave reg sub address*/ - uint32_t byte_trans: 1; /*One byte transit done*/ - uint32_t op_cnt: 2; /*which operation is working*/ - uint32_t reserved8: 8; - uint32_t shift: 8; /*shifter content*/ - uint32_t scl_main_state_last: 3; /*i2c last main status*/ - uint32_t reserved27: 1; - uint32_t scl_state_last: 3; /*scl last status*/ - uint32_t reserved31: 1; - }; - uint32_t val; - } status; - union { - struct { - uint32_t time_out: 20; /*time out threshold*/ - uint32_t reserved20:12; - }; - uint32_t val; - } timeout; - union { - struct { - uint32_t addr: 15; /*slave address*/ - uint32_t reserved15: 16; - uint32_t en_10bit: 1; /*i2c 10bit mode enable*/ - }; - uint32_t val; - } slave_addr; - union { - struct { - uint32_t period: 20; /*time period that scl = 1*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_high; - union { - struct { - uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } sda_duty; - union { - struct { - uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_start_period; - union { - struct { - uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } scl_stop_period; - union { - struct { - uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/ - uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/ - uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/ - uint32_t trans_complete: 1; /*clear transit complete interrupt*/ - uint32_t time_out: 1; /*clear time out interrupt*/ - uint32_t ack_err: 1; /*clear ack error interrupt*/ - uint32_t rx_data: 1; /*clear receive data interrupt*/ - uint32_t tx_data: 1; /*clear transit load data complete interrupt*/ - uint32_t detect_start: 1; /*clear detect start interrupt*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/ - uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/ - uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/ - uint32_t trans_complete: 1; /*transit complete interrupt raw*/ - uint32_t time_out: 1; /*time out interrupt raw*/ - uint32_t ack_err: 1; /*ack error interrupt raw*/ - uint32_t rx_data: 1; /*receive data interrupt raw*/ - uint32_t tx_data: 1; /*transit data interrupt raw*/ - uint32_t detect_start: 1; /*detect start interrupt raw*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/ - uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/ - uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/ - uint32_t trans_complete: 1; /*transit complete interrupt state*/ - uint32_t time_out: 1; /*time out interrupt state*/ - uint32_t ack_err: 1; /*ack error interrupt state*/ - uint32_t rx_data: 1; /*receive data interrupt state*/ - uint32_t tx_data: 1; /*transit data interrupt state*/ - uint32_t detect_start: 1; /*detect start interrupt state*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/ - uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/ - uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/ - uint32_t trans_complete: 1; /*enable transit complete interrupt*/ - uint32_t time_out: 1; /*enable time out interrupt*/ - uint32_t ack_err: 1; /*enable eack error interrupt*/ - uint32_t rx_data: 1; /*enable receive data interrupt*/ - uint32_t tx_data: 1; /*enable transit data interrupt*/ - uint32_t detect_start: 1; /*enable detect start interrupt*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t i2c_rdata: 8; /*data received*/ - uint32_t slave_tx_data: 8; /*data sent by slave*/ - uint32_t reserved16: 15; - uint32_t i2c_done: 1; /*i2c done*/ - }; - uint32_t val; - } fifo_data; - union { - struct { - uint32_t command0: 14; /*command0*/ - uint32_t reserved14: 17; - uint32_t done: 1; /*command0_done*/ - }; - uint32_t val; - } command[16]; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t i2c_date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } date; -} rtc_i2c_dev_t; -extern rtc_i2c_dev_t RTC_I2C; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_RTC_I2C_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/soc/soc.h b/components/soc/esp32h4/include/soc/soc.h deleted file mode 100644 index 5e94c41c8a..0000000000 --- a/components/soc/esp32h4/include/soc/soc.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#ifndef __ASSEMBLER__ -#include -#include "esp_assert.h" -#endif - -#include "esp_bit_defs.h" -#include "reg_base.h" - -#define PRO_CPU_NUM (0) - -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) - -//Registers Operation {{ -#define ETS_UNCACHED_ADDR(addr) (addr) -#define ETS_CACHED_ADDR(addr) (addr) - -#ifndef __ASSEMBLER__ - -//write value to register -#define REG_WRITE(_r, _v) do { \ - (*(volatile uint32_t *)(_r)) = (_v); \ - } while(0) - -//read value from register -#define REG_READ(_r) ({ \ - (*(volatile uint32_t *)(_r)); \ - }) - -//get bit or get bits from register -#define REG_GET_BIT(_r, _b) ({ \ - (*(volatile uint32_t*)(_r) & (_b)); \ - }) - -//set bit or set bits to register -#define REG_SET_BIT(_r, _b) do { \ - *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ - } while(0) - -//clear bit or clear bits of register -#define REG_CLR_BIT(_r, _b) do { \ - *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ - } while(0) - -//set bits of register controlled by mask -#define REG_SET_BITS(_r, _b, _m) do { \ - *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ - } while(0) - -//get field from register, uses field _S & _V to determine mask -#define REG_GET_FIELD(_r, _f) ({ \ - ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ - }) - -//set field of a register from variable, uses field _S & _V to determine mask -#define REG_SET_FIELD(_r, _f, _v) do { \ - REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ - } while(0) - -//get field value from a variable, used when _f is not left shifted by _f##_S -#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) - -//get field value from a variable, used when _f is left shifted by _f##_S -#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) - -//set field value to a variable, used when _f is not left shifted by _f##_S -#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) - -//set field value to a variable, used when _f is left shifted by _f##_S -#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) - -//generate a value from a field value, used when _f is not left shifted by _f##_S -#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) - -//generate a value from a field value, used when _f is left shifted by _f##_S -#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) - -//read value from register -#define READ_PERI_REG(addr) ({ \ - (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ - }) - -//write value to register -#define WRITE_PERI_REG(addr, val) do { \ - (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ - } while(0) - -//clear bits of register controlled by mask -#define CLEAR_PERI_REG_MASK(reg, mask) do { \ - WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ - } while(0) - -//set bits of register controlled by mask -#define SET_PERI_REG_MASK(reg, mask) do { \ - WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ - } while(0) - -//get bits of register controlled by mask -#define GET_PERI_REG_MASK(reg, mask) ({ \ - (READ_PERI_REG(reg) & (mask)); \ - }) - -//get bits of register controlled by highest bit and lowest bit -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ - ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ - }) - -//set bits of register controlled by mask and shift -#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ - WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ - } while(0) - -//get field of register -#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ - ((READ_PERI_REG(reg)>>(shift))&(mask)); \ - }) - -#endif /* !__ASSEMBLER__ */ -//}} - -//Periheral Clock {{ -#define APB_CLK_FREQ_ROM ( 32*1000000 ) -#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define EFUSE_CLK_FREQ_ROM ( 20*1000000) -#define CPU_CLK_FREQ_MHZ_BTLD (64) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration -#define CPU_CLK_FREQ APB_CLK_FREQ -#if CONFIG_IDF_ENV_FPGA -#define APB_CLK_FREQ ( 32*1000000 ) -#else -#define APB_CLK_FREQ ( 48*1000000 ) //ESP32H4-TODO: IDF-3786 -#endif -#define REF_CLK_FREQ ( 1000000 ) -#define XTAL_CLK_FREQ (32*1000000) -#define UART_CLK_FREQ APB_CLK_FREQ -#define WDT_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 -#define SPI_CLK_DIV 4 -#define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 0 -//}} - -/* Overall memory map */ -#define SOC_DROM_LOW 0x3C000000 -#define SOC_DROM_HIGH 0x3C800000 -#define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH 0x42800000 -#define SOC_IROM_MASK_LOW 0x40000000 -#define SOC_IROM_MASK_HIGH 0x40060000 -#define SOC_DROM_MASK_LOW 0x3FF00000 -#define SOC_DROM_MASK_HIGH 0x3FF20000 -#define SOC_IRAM_LOW 0x4037C000 -#define SOC_IRAM_HIGH 0x403E0000 -#define SOC_DRAM_LOW 0x3FC80000 -#define SOC_DRAM_HIGH 0x3FCE0000 -#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H4 only has RTC slow memory -#define SOC_RTC_IRAM_HIGH 0x50002000 -#define SOC_RTC_DRAM_LOW 0x50000000 -#define SOC_RTC_DRAM_HIGH 0x50002000 -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50002000 - -//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. -#define SOC_DIRAM_IRAM_LOW 0x40380000 -#define SOC_DIRAM_IRAM_HIGH 0x403E0000 -#define SOC_DIRAM_DRAM_LOW 0x3FC80000 -#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 - -#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) -#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) -#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) - -// Region of memory accessible via DMA. See esp_ptr_dma_capable(). -#define SOC_DMA_LOW 0x3FC80000 -#define SOC_DMA_HIGH 0x3FCE0000 - -// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). -#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC80000 -#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 - -//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs -//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). -#define SOC_MEM_INTERNAL_LOW 0x3FC80000 -#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 - -#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space - -// Region of address space that holds peripherals -#define SOC_PERIPHERAL_LOW 0x60000000 -#define SOC_PERIPHERAL_HIGH 0x60100000 - -// Debug region, not used by software -#define SOC_DEBUG_LOW 0x20000000 -#define SOC_DEBUG_HIGH 0x28000000 - -// Start (highest address) of ROM boot stack, only relevant during early boot -#define SOC_ROM_STACK_START 0x3fcdf120 -#define SOC_ROM_STACK_SIZE 0x2000 - -//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. -//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. - -//CPU0 Interrupt number reserved in riscv/vector.S, not touch this. -#define ETS_T1_WDT_INUM 24 -#define ETS_CACHEERR_INUM 25 -#define ETS_MEMPROT_ERR_INUM 26 -//CPU0 Max valid interrupt number -#define ETS_MAX_INUM 31 - -//CPU0 Interrupt number used in ROM, should be cancelled in SDK -#define ETS_SLC_INUM 1 -#define ETS_UART0_INUM 5 -#define ETS_UART1_INUM 5 -#define ETS_SPI2_INUM 1 -//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. -#define ETS_GPIO_INUM 4 - -//Other interrupt number should be managed by the user - -//Invalid interrupt for number interrupt matrix -#define ETS_INVALID_INUM 0 - -//Interrupt medium level, used for INT WDT for example -#define SOC_INTERRUPT_LEVEL_MEDIUM 4 - -// Interrupt number for the Interrupt watchdog -#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h deleted file mode 100644 index 46a28eea78..0000000000 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -// The long term plan is to have a single soc_caps.h for each peripheral. -// During the refactoring and multichip support development process, we -// seperate these information into periph_caps.h for each peripheral and -// include them here. - -/* - * These defines are parsed and imported as kconfig variables via the script - * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` - * - * If this file is changed the script will automatically run the script - * and generate the kconfig variables as part of the pre-commit hooks. - * - * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32h4/include/soc/'` - * - * For more information see `tools/gen_soc_caps_kconfig/README.md` - * -*/ - -#pragma once - -#ifdef __has_include -# if __has_include("sdkconfig.h") -# include "sdkconfig.h" -# else -# warning Chip version cannot be determined. Default chip to ESP32H4_BETA_VERSION_1. -# define CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 1 -# endif -#endif - -/*-------------------------- COMMON CAPS ---------------------------------------*/ -#define SOC_ADC_SUPPORTED 1 -#define SOC_DEDICATED_GPIO_SUPPORTED 1 -#define SOC_UART_SUPPORTED 1 -#define SOC_GDMA_SUPPORTED 1 -#define SOC_GPTIMER_SUPPORTED 1 -#define SOC_BT_SUPPORTED 1 -#define SOC_IEEE802154_SUPPORTED 1 -#define SOC_IEEE802154_BLE_ONLY 1 -#define SOC_ASYNC_MEMCPY_SUPPORTED 1 -#define SOC_USB_SERIAL_JTAG_SUPPORTED 1 -#define SOC_SUPPORTS_SECURE_DL_MODE 1 -#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 -#define SOC_TEMP_SENSOR_SUPPORTED 1 -#define SOC_RTC_FAST_MEM_SUPPORTED 1 -#define SOC_RTC_MEM_SUPPORTED 1 -#define SOC_I2S_SUPPORTED 1 -#define SOC_RMT_SUPPORTED 1 -#define SOC_SDM_SUPPORTED 1 -#define SOC_GPSPI_SUPPORTED 1 -#define SOC_LEDC_SUPPORTED 1 -#define SOC_I2C_SUPPORTED 1 -#define SOC_SYSTIMER_SUPPORTED 1 -#define SOC_AES_SUPPORTED 1 -#define SOC_MPI_SUPPORTED 1 -#define SOC_SHA_SUPPORTED 1 -#define SOC_HMAC_SUPPORTED 1 -#define SOC_DIG_SIGN_SUPPORTED 1 -#define SOC_ECC_SUPPORTED 1 -#define SOC_FLASH_ENC_SUPPORTED 1 -#define SOC_SECURE_BOOT_SUPPORTED 1 -#define SOC_BOD_SUPPORTED 1 - -/*-------------------------- XTAL CAPS ---------------------------------------*/ -#define SOC_XTAL_SUPPORT_32M 1 - -/*-------------------------- AES CAPS -----------------------------------------*/ -#define SOC_AES_SUPPORT_DMA (1) - -/* Has a centralized DMA, which is shared with all peripherals */ -#define SOC_AES_GDMA (1) - -#define SOC_AES_SUPPORT_AES_128 (1) -#define SOC_AES_SUPPORT_AES_256 (1) - -/*-------------------------- ADC CAPS -------------------------------*/ -/*!< SAR ADC Module*/ -#define SOC_ADC_DIG_CTRL_SUPPORTED 1 -#define SOC_ADC_ARBITER_SUPPORTED 1 -#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 -#define SOC_ADC_MONITOR_SUPPORTED 1 -#define SOC_ADC_DMA_SUPPORTED 1 -#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) ((UNIT == 0) ? 1 : 0) //Digital controller supported ADC unit -#define SOC_ADC_PERIPH_NUM (1U) -#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5) -#define SOC_ADC_MAX_CHANNEL_NUM (5) -#define SOC_ADC_ATTEN_NUM (4) - -/*!< Digital */ -#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) -#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ -#define SOC_ADC_DIGI_MIN_BITWIDTH (12) -#define SOC_ADC_DIGI_MAX_BITWIDTH (12) -#define SOC_ADC_DIGI_RESULT_BYTES (4) -#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) -#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) -#define SOC_ADC_DIGI_MONITOR_NUM (2) -/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */ -#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 -#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 - -/*!< RTC */ -#define SOC_ADC_RTC_MIN_BITWIDTH (12) -#define SOC_ADC_RTC_MAX_BITWIDTH (12) - -/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ -#define SOC_APB_BACKUP_DMA (1) - -/*-------------------------- BROWNOUT CAPS -----------------------------------*/ -#define SOC_BROWNOUT_RESET_SUPPORTED 1 - -/*-------------------------- CACHE CAPS --------------------------------------*/ -#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data - -/*-------------------------- CPU CAPS ----------------------------------------*/ -#define SOC_CPU_CORES_NUM (1U) -#define SOC_CPU_INTR_NUM 32 -#define SOC_CPU_HAS_FLEXIBLE_INTC 1 - -#define SOC_CPU_BREAKPOINTS_NUM 8 -#define SOC_CPU_WATCHPOINTS_NUM 8 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes - -/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ -/** The maximum length of a Digital Signature in bits. */ -#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) - -/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ -#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) - -/** Maximum wait time for DS parameter decryption key. If overdue, then key error. - See TRM DS chapter for more details */ -#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) - -/*-------------------------- GDMA CAPS -------------------------------------*/ -#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups -#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group -#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number - -/*-------------------------- GPIO CAPS ---------------------------------------*/ -// ESP32-H4 has 1 GPIO peripheral -#define SOC_GPIO_PORT 1U -#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1 - -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -#define SOC_GPIO_PIN_COUNT (41) -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -#define SOC_GPIO_PIN_COUNT (26) -#endif - -// Target has no full RTC IO subsystem, GPIO0~5(7~12) remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) - -// Force hold is a new function of ESP32-H4 -#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// GPIO0~5 on ESP32H4Beta1 / GPIO7~12 on ESP32H4Beta2 can support chip deep sleep wakeup -#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) - -#define SOC_GPIO_VALID_GPIO_MASK ((1ULL<> 3) -#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) - -#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) - -/*-------------------------- RTCIO CAPS --------------------------------------*/ -/* No dedicated RTCIO subsystem on ESP32-H4. RTC functions are still supported - * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ -#define SOC_RTCIO_PIN_COUNT (0U) - -/*--------------------------- RSA CAPS ---------------------------------------*/ -#define SOC_RSA_MAX_BIT_LEN (3072) - -/*--------------------------- SHA CAPS ---------------------------------------*/ - -/* Max amount of bytes in a single DMA operation is 4095, - for SHA this means that the biggest safe amount of bytes is - 31 blocks of 128 bytes = 3968 -*/ -#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) -#define SOC_SHA_SUPPORT_DMA (1) - -/* The SHA engine is able to resume hashing from a user */ -#define SOC_SHA_SUPPORT_RESUME (1) - -/* Has a centralized DMA, which is shared with all peripherals */ -#define SOC_SHA_GDMA (1) - -/* Supported HW algorithms */ -#define SOC_SHA_SUPPORT_SHA1 (1) -#define SOC_SHA_SUPPORT_SHA224 (1) -#define SOC_SHA_SUPPORT_SHA256 (1) - -/*-------------------------- Sigma Delta Modulator CAPS -----------------*/ -#define SOC_SDM_GROUPS 1U -#define SOC_SDM_CHANNELS_PER_GROUP 4 -#define SOC_SDM_CLK_SUPPORT_APB 1 - -/*-------------------------- SPI CAPS ----------------------------------------*/ -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_PERIPH_CS_NUM(i) 6 -#define SOC_SPI_MAX_CS_NUM 6 - -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 - -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 -#define SOC_SPI_SUPPORT_CLK_AHB 1 -#define SOC_SPI_SUPPORT_CLK_XTAL 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) - -// Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1 - -#define SOC_MEMSPI_IS_INDEPENDENT 1 -#define SOC_SPI_MAX_PRE_DIVIDER 16 - -/*-------------------------- SPI MEM CAPS ---------------------------------------*/ -#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) -#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) -#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) -#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) -#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) -#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) -#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1) -#define SOC_SPI_MEM_SUPPORT_WRAP (1) - -#define SOC_MEMSPI_SRC_FREQ_48M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_24M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_12M_SUPPORTED 1 - -/*-------------------------- SYSTIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 -#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) - -/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ -#define SOC_TIMER_GROUPS (2) -#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) -#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) -#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) -#define SOC_TIMER_GROUP_SUPPORT_AHB (1) -#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) - -/*-------------------------- TWAI CAPS ---------------------------------------*/ -#define SOC_TWAI_CONTROLLER_NUM 1UL -#define SOC_TWAI_CLK_SUPPORT_APB 1 -#define SOC_TWAI_BRP_MIN 2 -#define SOC_TWAI_BRP_MAX 16384 -#define SOC_TWAI_SUPPORTS_RX_STATUS 1 - -/*-------------------------- eFuse CAPS----------------------------*/ -#define SOC_EFUSE_DIS_PAD_JTAG 1 -#define SOC_EFUSE_DIS_USB_JTAG 1 -#define SOC_EFUSE_DIS_DIRECT_BOOT 1 -#define SOC_EFUSE_SOFT_DIS_JTAG 1 -#define SOC_EFUSE_DIS_ICACHE 1 -#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // AES-XTS key purpose not supported for this block - -/*-------------------------- Secure Boot CAPS----------------------------*/ -#define SOC_SECURE_BOOT_V2_RSA 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 -#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 -#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 - -/*-------------------------- Flash Encryption CAPS----------------------------*/ -#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) -#define SOC_FLASH_ENCRYPTION_XTS_AES 1 -#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 - -/*-------------------------- UART CAPS ---------------------------------------*/ -// ESP32-H4 has 2 UARTs -#define SOC_UART_NUM (2) -#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ -#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ -#define SOC_UART_SUPPORT_AHB_CLK (1) /*!< Support AHB as the clock source */ -#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ -#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ - -// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled -#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) - -/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ -#define SOC_COEX_HW_PTI (1) - -/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ -#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) - -/*-------------------------- Power Management CAPS ----------------------------*/ -#define SOC_PM_SUPPORT_BT_WAKEUP (1) -#define SOC_PM_SUPPORT_CPU_PD (1) -#define SOC_PM_SUPPORT_BT_PD (1) -#define SOC_PM_SUPPORT_RC_FAST_PD (1) - -#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*! -#ifdef __cplusplus -extern "C" { -#endif - -/** Configuration Register */ -/** Type of conf register - * SYSTIMER_CONF. - */ -typedef union { - struct { - /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; - * systimer clock force on - */ - uint32_t systimer_clk_fo: 1; - uint32_t reserved_1: 21; - /** target2_work_en : R/W; bitpos: [22]; default: 0; - * target2 work enable - */ - uint32_t target2_work_en: 1; - /** target1_work_en : R/W; bitpos: [23]; default: 0; - * target1 work enable - */ - uint32_t target1_work_en: 1; - /** target0_work_en : R/W; bitpos: [24]; default: 0; - * target0 work enable - */ - uint32_t target0_work_en: 1; - /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; - * If timer unit1 is stalled when core1 stalled - */ - uint32_t timer_unit1_core1_stall_en: 1; - /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; - * If timer unit1 is stalled when core0 stalled - */ - uint32_t timer_unit1_core0_stall_en: 1; - /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; - * If timer unit0 is stalled when core1 stalled - */ - uint32_t timer_unit0_core1_stall_en: 1; - /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; - * If timer unit0 is stalled when core0 stalled - */ - uint32_t timer_unit0_core0_stall_en: 1; - /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; - * timer unit1 work enable - */ - uint32_t timer_unit1_work_en: 1; - /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; - * timer unit0 work enable - */ - uint32_t timer_unit0_work_en: 1; - /** clk_en : R/W; bitpos: [31]; default: 0; - * register file clk gating - */ - uint32_t clk_en: 1; - }; - uint32_t val; -} systimer_conf_reg_t; - -/** Type of unit_op register - * SYSTIMER_UNIT_OP. - */ -typedef union { - struct { - uint32_t reserved_0: 29; - /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; - * reg_timer_unit0_value_valid - */ - uint32_t timer_unit_value_valid: 1; - /** timer_unit_update : WT; bitpos: [30]; default: 0; - * update timer_unit0 - */ - uint32_t timer_unit_update: 1; - uint32_t reserved31: 1; - }; - uint32_t val; -} systimer_unit_op_reg_t; - -/** Type of unit_load register - * SYSTIMER_UNIT_LOAD - */ -typedef struct { - union { - struct { - /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; - * timer unit load high 32 bit - */ - uint32_t timer_unit_load_hi: 20; - uint32_t reserved20: 12; - }; - uint32_t val; - } hi; - union { - struct { - /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; - * timer unit load low 32 bit - */ - uint32_t timer_unit_load_lo: 32; - }; - uint32_t val; - } lo; -} systimer_unit_load_val_reg_t; - -/** Type of target register - * SYSTIMER_TARGET. - */ -typedef struct { - union { - struct { - /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; - * timer target high 32 bit - */ - uint32_t timer_target_hi: 20; - uint32_t reserved20: 12; - }; - uint32_t val; - } hi; - union { - struct { - /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; - * timer target low 32 bit - */ - uint32_t timer_target_lo: 32; - }; - uint32_t val; - } lo; -} systimer_target_val_reg_t; - -/** Type of target_conf register - * SYSTIMER_TARGET_CONF. - */ -typedef union { - struct { - /** target_period : R/W; bitpos: [25:0]; default: 0; - * target period - */ - uint32_t target_period: 26; - uint32_t reserved_26: 4; - /** target_period_mode : R/W; bitpos: [30]; default: 0; - * Set target to period mode - */ - uint32_t target_period_mode: 1; - /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ - uint32_t target_timer_unit_sel: 1; - }; - uint32_t val; -} systimer_target_conf_reg_t; - -/** Type of unit_value_hi register - * SYSTIMER_UNIT_VALUE_HI. - */ -typedef struct { - union { - struct { - /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; - * timer read value high 20bit - */ - uint32_t timer_unit_value_hi: 20; - uint32_t reserved20: 12; - }; - uint32_t val; - } hi; - union { - struct { - /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; - * timer read value low 32bit - */ - uint32_t timer_unit_value_lo: 32; - }; - uint32_t val; - } lo; -} systimer_unit_value_reg_t; - -/** Type of comp_load register - * SYSTIMER_COMP_LOAD. - */ -typedef union { - struct { - /** timer_comp_load : WT; bitpos: [0]; default: 0; - * timer comp load value - */ - uint32_t timer_comp_load: 1; - uint32_t reserved1: 31; - }; - uint32_t val; -} systimer_comp_load_reg_t; - -/** Type of unit_load register - * SYSTIMER_UNIT_LOAD. - */ -typedef union { - struct { - /** timer_unit_load : WT; bitpos: [0]; default: 0; - * timer unit load value - */ - uint32_t timer_unit_load: 1; - uint32_t reserved1: 31; - }; - uint32_t val; -} systimer_unit_load_reg_t; - -/** Interrupt Register */ -/** Type of int_ena register - * SYSTIMER_INT_ENA. - */ -typedef union { - struct { - /** target0_int_ena : R/W; bitpos: [0]; default: 0; - * interupt0 enable - */ - uint32_t target0_int_ena: 1; - /** target1_int_ena : R/W; bitpos: [1]; default: 0; - * interupt1 enable - */ - uint32_t target1_int_ena: 1; - /** target2_int_ena : R/W; bitpos: [2]; default: 0; - * interupt2 enable - */ - uint32_t target2_int_ena: 1; - uint32_t reserved3: 29; - }; - uint32_t val; -} systimer_int_ena_reg_t; - -/** Type of int_raw register - * SYSTIMER_INT_RAW. - */ -typedef union { - struct { - /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * interupt0 raw - */ - uint32_t target0_int_raw: 1; - /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * interupt1 raw - */ - uint32_t target1_int_raw: 1; - /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * interupt2 raw - */ - uint32_t target2_int_raw: 1; - uint32_t reserved3: 29; - }; - uint32_t val; -} systimer_int_raw_reg_t; - -/** Type of int_clr register - * SYSTIMER_INT_CLR. - */ -typedef union { - struct { - /** target0_int_clr : WT; bitpos: [0]; default: 0; - * interupt0 clear - */ - uint32_t target0_int_clr: 1; - /** target1_int_clr : WT; bitpos: [1]; default: 0; - * interupt1 clear - */ - uint32_t target1_int_clr: 1; - /** target2_int_clr : WT; bitpos: [2]; default: 0; - * interupt2 clear - */ - uint32_t target2_int_clr: 1; - uint32_t reserved3: 29; - }; - uint32_t val; -} systimer_int_clr_reg_t; - -/** Type of int_st register - * SYSTIMER_INT_ST. - */ -typedef union { - struct { - /** target0_int_st : RO; bitpos: [0]; default: 0; - * reg_target0_int_st - */ - uint32_t target0_int_st: 1; - /** target1_int_st : RO; bitpos: [1]; default: 0; - * reg_target1_int_st - */ - uint32_t target1_int_st: 1; - /** target2_int_st : RO; bitpos: [2]; default: 0; - * reg_target2_int_st - */ - uint32_t target2_int_st: 1; - uint32_t reserved3: 29; - }; - uint32_t val; -} systimer_int_st_reg_t; - - -/** Version Register */ -/** Type of date register - * SYSTIMER_DATE. - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 33579377; - * reg_date - */ - uint32_t date: 32; - }; - uint32_t val; -} systimer_date_reg_t; - - -typedef struct systimer_dev_t { - volatile systimer_conf_reg_t conf; - volatile systimer_unit_op_reg_t unit_op[2]; - volatile systimer_unit_load_val_reg_t unit_load_val[2]; - volatile systimer_target_val_reg_t target_val[3]; - volatile systimer_target_conf_reg_t target_conf[3]; - volatile systimer_unit_value_reg_t unit_val[2]; - volatile systimer_comp_load_reg_t comp_load[3]; - volatile systimer_unit_load_reg_t unit_load[2]; - volatile systimer_int_ena_reg_t int_ena; - volatile systimer_int_raw_reg_t int_raw; - volatile systimer_int_clr_reg_t int_clr; - volatile systimer_int_st_reg_t int_st; - uint32_t reserved_074; - uint32_t reserved_078; - uint32_t reserved_07c; - uint32_t reserved_080; - uint32_t reserved_084; - uint32_t reserved_088; - uint32_t reserved_08c; - uint32_t reserved_090; - uint32_t reserved_094; - uint32_t reserved_098; - uint32_t reserved_09c; - uint32_t reserved_0a0; - uint32_t reserved_0a4; - uint32_t reserved_0a8; - uint32_t reserved_0ac; - uint32_t reserved_0b0; - uint32_t reserved_0b4; - uint32_t reserved_0b8; - uint32_t reserved_0bc; - uint32_t reserved_0c0; - uint32_t reserved_0c4; - uint32_t reserved_0c8; - uint32_t reserved_0cc; - uint32_t reserved_0d0; - uint32_t reserved_0d4; - uint32_t reserved_0d8; - uint32_t reserved_0dc; - uint32_t reserved_0e0; - uint32_t reserved_0e4; - uint32_t reserved_0e8; - uint32_t reserved_0ec; - uint32_t reserved_0f0; - uint32_t reserved_0f4; - uint32_t reserved_0f8; - volatile systimer_date_reg_t date; -} systimer_dev_t; - -extern systimer_dev_t SYSTIMER; - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/timer_group_reg.h b/components/soc/esp32h4/include/soc/timer_group_reg.h deleted file mode 100644 index f92a355c66..0000000000 --- a/components/soc/esp32h4/include/soc/timer_group_reg.h +++ /dev/null @@ -1,580 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i) - -/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ -#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 - -/* Possible values for TIMG_WDT_STGx */ -#define TIMG_WDT_STG_SEL_OFF 0 -#define TIMG_WDT_STG_SEL_INT 1 -#define TIMG_WDT_STG_SEL_RESET_CPU 2 -#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 - -/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */ -#define TIMG_WDT_RESET_LENGTH_100_NS 0 -#define TIMG_WDT_RESET_LENGTH_200_NS 1 -#define TIMG_WDT_RESET_LENGTH_300_NS 2 -#define TIMG_WDT_RESET_LENGTH_400_NS 3 -#define TIMG_WDT_RESET_LENGTH_500_NS 4 -#define TIMG_WDT_RESET_LENGTH_800_NS 5 -#define TIMG_WDT_RESET_LENGTH_1600_NS 6 -#define TIMG_WDT_RESET_LENGTH_3200_NS 7 - -/** TIMG_T0CONFIG_REG register - * Timer 0 configuration register - */ -#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0) -/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; - * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source - * clock of timer group. - */ -#define TIMG_T0_USE_XTAL (BIT(9)) -#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) -#define TIMG_T0_USE_XTAL_V 0x00000001U -#define TIMG_T0_USE_XTAL_S 9 -/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0; - * When set, the alarm is enabled. This bit is automatically cleared once an - * alarm occurs. - */ -#define TIMG_T0_ALARM_EN (BIT(10)) -#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) -#define TIMG_T0_ALARM_EN_V 0x00000001U -#define TIMG_T0_ALARM_EN_S 10 -/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0; - * When set, Timer 0 's clock divider counter will be reset. - */ -#define TIMG_T0_DIVCNT_RST (BIT(12)) -#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S) -#define TIMG_T0_DIVCNT_RST_V 0x00000001U -#define TIMG_T0_DIVCNT_RST_S 12 -/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; - * Timer 0 clock (T0_clk) prescaler value. - */ -#define TIMG_T0_DIVIDER 0x0000FFFFU -#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) -#define TIMG_T0_DIVIDER_V 0x0000FFFFU -#define TIMG_T0_DIVIDER_S 13 -/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; - * When set, timer 0 auto-reload at alarm is enabled. - */ -#define TIMG_T0_AUTORELOAD (BIT(29)) -#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) -#define TIMG_T0_AUTORELOAD_V 0x00000001U -#define TIMG_T0_AUTORELOAD_S 29 -/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; - * When set, the timer 0 time-base counter will increment every clock tick. When - * cleared, the timer 0 time-base counter will decrement. - */ -#define TIMG_T0_INCREASE (BIT(30)) -#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) -#define TIMG_T0_INCREASE_V 0x00000001U -#define TIMG_T0_INCREASE_S 30 -/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0; - * When set, the timer 0 time-base counter is enabled. - */ -#define TIMG_T0_EN (BIT(31)) -#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) -#define TIMG_T0_EN_V 0x00000001U -#define TIMG_T0_EN_S 31 - -/** TIMG_T0LO_REG register - * Timer 0 current value, low 32 bits - */ -#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4) -/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; - * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter - * of timer 0 can be read here. - */ -#define TIMG_T0_LO 0xFFFFFFFFU -#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) -#define TIMG_T0_LO_V 0xFFFFFFFFU -#define TIMG_T0_LO_S 0 - -/** TIMG_T0HI_REG register - * Timer $x current value, high 22 bits - */ -#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8) -/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0; - * After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter - * of timer $x can be read here. - */ -#define TIMG_T0_HI 0x003FFFFFU -#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) -#define TIMG_T0_HI_V 0x003FFFFFU -#define TIMG_T0_HI_S 0 - -/** TIMG_T0UPDATE_REG register - * Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG - */ -#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc) -/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0; - * After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched. - */ -#define TIMG_T0_UPDATE (BIT(31)) -#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) -#define TIMG_T0_UPDATE_V 0x00000001U -#define TIMG_T0_UPDATE_S 31 - -/** TIMG_T0ALARMLO_REG register - * Timer $x alarm value, low 32 bits - */ -#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10) -/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; - * Timer $x alarm trigger time-base counter value, low 32 bits. - */ -#define TIMG_T0_ALARM_LO 0xFFFFFFFFU -#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) -#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU -#define TIMG_T0_ALARM_LO_S 0 - -/** TIMG_T0ALARMHI_REG register - * Timer $x alarm value, high bits - */ -#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14) -/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0; - * Timer $x alarm trigger time-base counter value, high 22 bits. - */ -#define TIMG_T0_ALARM_HI 0x003FFFFFU -#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) -#define TIMG_T0_ALARM_HI_V 0x003FFFFFU -#define TIMG_T0_ALARM_HI_S 0 - -/** TIMG_T0LOADLO_REG register - * Timer $x reload value, low 32 bits - */ -#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18) -/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * Low 32 bits of the value that a reload will load onto timer $x time-base - * Counter. - */ -#define TIMG_T0_LOAD_LO 0xFFFFFFFFU -#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) -#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU -#define TIMG_T0_LOAD_LO_S 0 - -/** TIMG_T0LOADHI_REG register - * Timer $x reload value, high 22 bits - */ -#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c) -/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0; - * High 22 bits of the value that a reload will load onto timer $x time-base - * counter. - */ -#define TIMG_T0_LOAD_HI 0x003FFFFFU -#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) -#define TIMG_T0_LOAD_HI_V 0x003FFFFFU -#define TIMG_T0_LOAD_HI_S 0 - -/** TIMG_T0LOAD_REG register - * Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG - */ -#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20) -/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0; - * - * Write any value to trigger a timer $x time-base counter reload. - */ -#define TIMG_T0_LOAD 0xFFFFFFFFU -#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) -#define TIMG_T0_LOAD_V 0xFFFFFFFFU -#define TIMG_T0_LOAD_S 0 - -/** TIMG_WDTCONFIG0_REG register - * Watchdog timer configuration register - */ -#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48) -/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; - * WDT reset CPU enable. - */ -#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) -#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) -#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U -#define TIMG_WDT_APPCPU_RESET_EN_S 12 -/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; - * WDT reset CPU enable. - */ -#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) -#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) -#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U -#define TIMG_WDT_PROCPU_RESET_EN_S 13 -/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; - * When set, Flash boot protection is enabled. - */ -#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) -#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) -#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U -#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 -/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; - * System reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ -#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U -#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) -#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U -#define TIMG_WDT_SYS_RESET_LENGTH_S 15 -/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; - * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ -#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U -#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) -#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U -#define TIMG_WDT_CPU_RESET_LENGTH_S 18 -/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0; - * choose WDT clock:0-apb_clk; 1-xtal_clk. - */ -#define TIMG_WDT_USE_XTAL (BIT(21)) -#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S) -#define TIMG_WDT_USE_XTAL_V 0x00000001U -#define TIMG_WDT_USE_XTAL_S 21 -/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0; - * update the WDT configuration registers - */ -#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) -#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S) -#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U -#define TIMG_WDT_CONF_UPDATE_EN_S 22 -/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; - * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG3 0x00000003U -#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) -#define TIMG_WDT_STG3_V 0x00000003U -#define TIMG_WDT_STG3_S 23 -/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; - * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG2 0x00000003U -#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) -#define TIMG_WDT_STG2_V 0x00000003U -#define TIMG_WDT_STG2_S 25 -/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; - * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG1 0x00000003U -#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) -#define TIMG_WDT_STG1_V 0x00000003U -#define TIMG_WDT_STG1_S 27 -/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; - * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ -#define TIMG_WDT_STG0 0x00000003U -#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) -#define TIMG_WDT_STG0_V 0x00000003U -#define TIMG_WDT_STG0_S 29 -/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; - * When set, MWDT is enabled. - */ -#define TIMG_WDT_EN (BIT(31)) -#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) -#define TIMG_WDT_EN_V 0x00000001U -#define TIMG_WDT_EN_S 31 - -/** TIMG_WDTCONFIG1_REG register - * Watchdog timer prescaler register - */ -#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c) -/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0; - * When set, WDT 's clock divider counter will be reset. - */ -#define TIMG_WDT_DIVCNT_RST (BIT(0)) -#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S) -#define TIMG_WDT_DIVCNT_RST_V 0x00000001U -#define TIMG_WDT_DIVCNT_RST_S 0 -/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1; - * MWDT clock prescaler value. MWDT clock period = 12.5 ns * - * TIMG_WDT_CLK_PRESCALE. - */ -#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU -#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S) -#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU -#define TIMG_WDT_CLK_PRESCALE_S 16 - -/** TIMG_WDTCONFIG2_REG register - * Watchdog timer stage 0 timeout value - */ -#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50) -/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; - * Stage 0 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) -#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG0_HOLD_S 0 - -/** TIMG_WDTCONFIG3_REG register - * Watchdog timer stage 1 timeout value - */ -#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54) -/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; - * Stage 1 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) -#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG1_HOLD_S 0 - -/** TIMG_WDTCONFIG4_REG register - * Watchdog timer stage 2 timeout value - */ -#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58) -/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; - * Stage 2 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) -#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG2_HOLD_S 0 - -/** TIMG_WDTCONFIG5_REG register - * Watchdog timer stage 3 timeout value - */ -#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c) -/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; - * Stage 3 timeout value, in MWDT clock cycles. - */ -#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU -#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) -#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU -#define TIMG_WDT_STG3_HOLD_S 0 - -/** TIMG_WDTFEED_REG register - * Write to feed the watchdog timer - */ -#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60) -/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0; - * Write any value to feed the MWDT. (WO) - */ -#define TIMG_WDT_FEED 0xFFFFFFFFU -#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) -#define TIMG_WDT_FEED_V 0xFFFFFFFFU -#define TIMG_WDT_FEED_S 0 - -/** TIMG_WDTWPROTECT_REG register - * Watchdog write protect register - */ -#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64) -/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; - * If the register contains a different value than its reset value, write - * protection is enabled. - */ -#define TIMG_WDT_WKEY 0xFFFFFFFFU -#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) -#define TIMG_WDT_WKEY_V 0xFFFFFFFFU -#define TIMG_WDT_WKEY_S 0 - -/** TIMG_RTCCALICFG_REG register - * RTC calibration configure register - */ -#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68) -/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; - * Reserved - */ -#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) -#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) -#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U -#define TIMG_RTC_CALI_START_CYCLING_S 12 -/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1; - * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - */ -#define TIMG_RTC_CALI_CLK_SEL 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) -#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U -#define TIMG_RTC_CALI_CLK_SEL_S 13 -/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; - * Reserved - */ -#define TIMG_RTC_CALI_RDY (BIT(15)) -#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) -#define TIMG_RTC_CALI_RDY_V 0x00000001U -#define TIMG_RTC_CALI_RDY_S 15 -/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; - * Reserved - */ -#define TIMG_RTC_CALI_MAX 0x00007FFFU -#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) -#define TIMG_RTC_CALI_MAX_V 0x00007FFFU -#define TIMG_RTC_CALI_MAX_S 16 -/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; - * Reserved - */ -#define TIMG_RTC_CALI_START (BIT(31)) -#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) -#define TIMG_RTC_CALI_START_V 0x00000001U -#define TIMG_RTC_CALI_START_S 31 - -/** TIMG_RTCCALICFG1_REG register - * RTC calibration configure1 register - */ -#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c) -/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; - * Reserved - */ -#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 -/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; - * Reserved - */ -#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU -#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) -#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU -#define TIMG_RTC_CALI_VALUE_S 7 - -/** TIMG_INT_ENA_TIMERS_REG register - * Interrupt enable bits - */ -#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70) -/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_ENA (BIT(0)) -#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) -#define TIMG_T0_INT_ENA_V 0x00000001U -#define TIMG_T0_INT_ENA_S 0 -/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_ENA (BIT(1)) -#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) -#define TIMG_WDT_INT_ENA_V 0x00000001U -#define TIMG_WDT_INT_ENA_S 1 - -/** TIMG_INT_RAW_TIMERS_REG register - * Raw interrupt status - */ -#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74) -/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_RAW (BIT(0)) -#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) -#define TIMG_T0_INT_RAW_V 0x00000001U -#define TIMG_T0_INT_RAW_S 0 -/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status bit for the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_RAW (BIT(1)) -#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) -#define TIMG_WDT_INT_RAW_V 0x00000001U -#define TIMG_WDT_INT_RAW_S 1 - -/** TIMG_INT_ST_TIMERS_REG register - * Masked interrupt status - */ -#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78) -/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_ST (BIT(0)) -#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) -#define TIMG_T0_INT_ST_V 0x00000001U -#define TIMG_T0_INT_ST_S 0 -/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_ST (BIT(1)) -#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) -#define TIMG_WDT_INT_ST_V 0x00000001U -#define TIMG_WDT_INT_ST_S 1 - -/** TIMG_INT_CLR_TIMERS_REG register - * Interrupt clear bits - */ -#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c) -/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the TIMG_T$x_INT interrupt. - */ -#define TIMG_T0_INT_CLR (BIT(0)) -#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) -#define TIMG_T0_INT_CLR_V 0x00000001U -#define TIMG_T0_INT_CLR_S 0 -/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the TIMG_WDT_INT interrupt. - */ -#define TIMG_WDT_INT_CLR (BIT(1)) -#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) -#define TIMG_WDT_INT_CLR_V 0x00000001U -#define TIMG_WDT_INT_CLR_S 1 - -/** TIMG_RTCCALICFG2_REG register - * Timer group calibration register - */ -#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80) -/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; - * RTC calibration timeout indicator - */ -#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) -#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) -#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U -#define TIMG_RTC_CALI_TIMEOUT_S 0 -/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; - * Cycles that release calibration timeout reset - */ -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 -/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; - * Threshold value for the RTC calibration timer. If the calibration timer's value - * exceeds this threshold, a timeout is triggered. - */ -#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU -#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) -#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU -#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 - -/** TIMG_NTIMERS_DATE_REG register - * Timer version control register - */ -#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8) -/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409; - * Timer version control register - */ -#define TIMG_NTIMGS_DATE 0x0FFFFFFFU -#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S) -#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU -#define TIMG_NTIMGS_DATE_S 0 - -/** TIMG_REGCLK_REG register - * Timer group clock gate register - */ -#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc) -/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1; - * enable WDT's clock - */ -#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) -#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S) -#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U -#define TIMG_WDT_CLK_IS_ACTIVE_S 29 -/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1; - * enable Timer $x's clock - */ -#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) -#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S) -#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U -#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 -/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; - * Register clock gate signal. 1: Registers can be read and written to by software. 0: - * Registers can not be read or written to by software. - */ -#define TIMG_CLK_EN (BIT(31)) -#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) -#define TIMG_CLK_EN_V 0x00000001U -#define TIMG_CLK_EN_S 31 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/timer_group_struct.h b/components/soc/esp32h4/include/soc/timer_group_struct.h deleted file mode 100644 index 6d460adc19..0000000000 --- a/components/soc/esp32h4/include/soc/timer_group_struct.h +++ /dev/null @@ -1,561 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: T0 Control and configuration registers */ -/** Type of txconfig register - * Timer x configuration register - */ -typedef union { - struct { - uint32_t reserved_0: 9; - /** tx_use_xtal : R/W; bitpos: [9]; default: 0; - * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source - * clock of timer group. - */ - uint32_t tx_use_xtal: 1; - /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0; - * When set, the alarm is enabled. This bit is automatically cleared once an - * alarm occurs. - */ - uint32_t tx_alarm_en: 1; - uint32_t reserved_11: 1; - /** tx_divcnt_rst : WT; bitpos: [12]; default: 0; - * When set, Timer x 's clock divider counter will be reset. - */ - uint32_t tx_divcnt_rst: 1; - /** tx_divider : R/W; bitpos: [28:13]; default: 1; - * Timer x clock (Tx_clk) prescaler value. - */ - uint32_t tx_divider: 16; - /** tx_autoreload : R/W; bitpos: [29]; default: 1; - * When set, timer x auto-reload at alarm is enabled. - */ - uint32_t tx_autoreload: 1; - /** tx_increase : R/W; bitpos: [30]; default: 1; - * When set, the timer x time-base counter will increment every clock tick. When - * cleared, the timer x time-base counter will decrement. - */ - uint32_t tx_increase: 1; - /** tx_en : R/W; bitpos: [31]; default: 0; - * When set, the timer x time-base counter is enabled. - */ - uint32_t tx_en: 1; - }; - uint32_t val; -} timg_txconfig_reg_t; - -/** Type of txlo register - * Timer x current value, low 32 bits - */ -typedef union { - struct { - /** tx_lo : RO; bitpos: [31:0]; default: 0; - * After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter - * of timer x can be read here. - */ - uint32_t tx_lo: 32; - }; - uint32_t val; -} timg_txlo_reg_t; - -/** Type of txhi register - * Timer $x current value, high 22 bits - */ -typedef union { - struct { - /** tx_hi : RO; bitpos: [21:0]; default: 0; - * After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter - * of timer $x can be read here. - */ - uint32_t tx_hi: 22; - uint32_t reserved_22: 10; - }; - uint32_t val; -} timg_txhi_reg_t; - -/** Type of txupdate register - * Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG - */ -typedef union { - struct { - uint32_t reserved_0: 31; - /** tx_update : R/W/SC; bitpos: [31]; default: 0; - * After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched. - */ - uint32_t tx_update: 1; - }; - uint32_t val; -} timg_txupdate_reg_t; - -/** Type of txalarmlo register - * Timer $x alarm value, low 32 bits - */ -typedef union { - struct { - /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0; - * Timer $x alarm trigger time-base counter value, low 32 bits. - */ - uint32_t tx_alarm_lo: 32; - }; - uint32_t val; -} timg_txalarmlo_reg_t; - -/** Type of txalarmhi register - * Timer $x alarm value, high bits - */ -typedef union { - struct { - /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0; - * Timer $x alarm trigger time-base counter value, high 22 bits. - */ - uint32_t tx_alarm_hi: 22; - uint32_t reserved_22: 10; - }; - uint32_t val; -} timg_txalarmhi_reg_t; - -/** Type of txloadlo register - * Timer $x reload value, low 32 bits - */ -typedef union { - struct { - /** tx_load_lo : R/W; bitpos: [31:0]; default: 0; - * Low 32 bits of the value that a reload will load onto timer $x time-base - * Counter. - */ - uint32_t tx_load_lo: 32; - }; - uint32_t val; -} timg_txloadlo_reg_t; - -/** Type of txloadhi register - * Timer $x reload value, high 22 bits - */ -typedef union { - struct { - /** tx_load_hi : R/W; bitpos: [21:0]; default: 0; - * High 22 bits of the value that a reload will load onto timer $x time-base - * counter. - */ - uint32_t tx_load_hi: 22; - uint32_t reserved_22: 10; - }; - uint32_t val; -} timg_txloadhi_reg_t; - -/** Type of txload register - * Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG - */ -typedef union { - struct { - /** tx_load : WT; bitpos: [31:0]; default: 0; - * - * Write any value to trigger a timer $x time-base counter reload. - */ - uint32_t tx_load: 32; - }; - uint32_t val; -} timg_txload_reg_t; - - -/** Group: WDT Control and configuration registers */ -/** Type of wdtconfig0 register - * Watchdog timer configuration register - */ -typedef union { - struct { - uint32_t reserved_0: 12; - /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0; - * WDT reset CPU enable. - */ - uint32_t wdt_appcpu_reset_en: 1; - /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0; - * WDT reset CPU enable. - */ - uint32_t wdt_procpu_reset_en: 1; - /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1; - * When set, Flash boot protection is enabled. - */ - uint32_t wdt_flashboot_mod_en: 1; - /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1; - * System reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ - uint32_t wdt_sys_reset_length: 3; - /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1; - * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, - * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - */ - uint32_t wdt_cpu_reset_length: 3; - /** wdt_use_xtal : R/W; bitpos: [21]; default: 0; - * choose WDT clock:0-apb_clk; 1-xtal_clk. - */ - uint32_t wdt_use_xtal: 1; - /** wdt_conf_update_en : WT; bitpos: [22]; default: 0; - * update the WDT configuration registers - */ - uint32_t wdt_conf_update_en: 1; - /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0; - * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg3: 2; - /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0; - * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg2: 2; - /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0; - * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg1: 2; - /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0; - * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - */ - uint32_t wdt_stg0: 2; - /** wdt_en : R/W; bitpos: [31]; default: 0; - * When set, MWDT is enabled. - */ - uint32_t wdt_en: 1; - }; - uint32_t val; -} timg_wdtconfig0_reg_t; - -/** Type of wdtconfig1 register - * Watchdog timer prescaler register - */ -typedef union { - struct { - /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0; - * When set, WDT 's clock divider counter will be reset. - */ - uint32_t wdt_divcnt_rst: 1; - uint32_t reserved_1: 15; - /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1; - * MWDT clock prescaler value. MWDT clock period = 12.5 ns * - * TIMG_WDT_CLK_PRESCALE. - */ - uint32_t wdt_clk_prescale: 16; - }; - uint32_t val; -} timg_wdtconfig1_reg_t; - -/** Type of wdtconfig2 register - * Watchdog timer stage 0 timeout value - */ -typedef union { - struct { - /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000; - * Stage 0 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg0_hold: 32; - }; - uint32_t val; -} timg_wdtconfig2_reg_t; - -/** Type of wdtconfig3 register - * Watchdog timer stage 1 timeout value - */ -typedef union { - struct { - /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727; - * Stage 1 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg1_hold: 32; - }; - uint32_t val; -} timg_wdtconfig3_reg_t; - -/** Type of wdtconfig4 register - * Watchdog timer stage 2 timeout value - */ -typedef union { - struct { - /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575; - * Stage 2 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg2_hold: 32; - }; - uint32_t val; -} timg_wdtconfig4_reg_t; - -/** Type of wdtconfig5 register - * Watchdog timer stage 3 timeout value - */ -typedef union { - struct { - /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575; - * Stage 3 timeout value, in MWDT clock cycles. - */ - uint32_t wdt_stg3_hold: 32; - }; - uint32_t val; -} timg_wdtconfig5_reg_t; - -/** Type of wdtfeed register - * Write to feed the watchdog timer - */ -typedef union { - struct { - /** wdt_feed : WT; bitpos: [31:0]; default: 0; - * Write any value to feed the MWDT. (WO) - */ - uint32_t wdt_feed: 32; - }; - uint32_t val; -} timg_wdtfeed_reg_t; - -/** Type of wdtwprotect register - * Watchdog write protect register - */ -typedef union { - struct { - /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065; - * If the register contains a different value than its reset value, write - * protection is enabled. - */ - uint32_t wdt_wkey: 32; - }; - uint32_t val; -} timg_wdtwprotect_reg_t; - - -/** Group: RTC CALI Control and configuration registers */ -/** Type of rtccalicfg register - * RTC calibration configure register - */ -typedef union { - struct { - uint32_t reserved_0: 12; - /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1; - * Reserved - */ - uint32_t rtc_cali_start_cycling: 1; - /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1; - * 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - */ - uint32_t rtc_cali_clk_sel: 2; - /** rtc_cali_rdy : RO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t rtc_cali_rdy: 1; - /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1; - * Reserved - */ - uint32_t rtc_cali_max: 15; - /** rtc_cali_start : R/W; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t rtc_cali_start: 1; - }; - uint32_t val; -} timg_rtccalicfg_reg_t; - -/** Type of rtccalicfg1 register - * RTC calibration configure1 register - */ -typedef union { - struct { - /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0; - * Reserved - */ - uint32_t rtc_cali_cycling_data_vld: 1; - uint32_t reserved_1: 6; - /** rtc_cali_value : RO; bitpos: [31:7]; default: 0; - * Reserved - */ - uint32_t rtc_cali_value: 25; - }; - uint32_t val; -} timg_rtccalicfg1_reg_t; - -/** Type of rtccalicfg2 register - * Timer group calibration register - */ -typedef union { - struct { - /** rtc_cali_timeout : RO; bitpos: [0]; default: 0; - * RTC calibration timeout indicator - */ - uint32_t rtc_cali_timeout: 1; - uint32_t reserved_1: 2; - /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3; - * Cycles that release calibration timeout reset - */ - uint32_t rtc_cali_timeout_rst_cnt: 4; - /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431; - * Threshold value for the RTC calibration timer. If the calibration timer's value - * exceeds this threshold, a timeout is triggered. - */ - uint32_t rtc_cali_timeout_thres: 25; - }; - uint32_t val; -} timg_rtccalicfg2_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_ena_timers register - * Interrupt enable bits - */ -typedef union { - struct { - /** t0_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_ena: 1; - /** wdt_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_ena: 1; - uint32_t reserved_2: 30; - }; - uint32_t val; -} timg_int_ena_timers_reg_t; - -/** Type of int_raw_timers register - * Raw interrupt status - */ -typedef union { - struct { - /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_raw: 1; - /** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status bit for the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_raw: 1; - uint32_t reserved_2: 30; - }; - uint32_t val; -} timg_int_raw_timers_reg_t; - -/** Type of int_st_timers register - * Masked interrupt status - */ -typedef union { - struct { - /** t0_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_st: 1; - /** wdt_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_st: 1; - uint32_t reserved_2: 30; - }; - uint32_t val; -} timg_int_st_timers_reg_t; - -/** Type of int_clr_timers register - * Interrupt clear bits - */ -typedef union { - struct { - /** t0_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the TIMG_T$x_INT interrupt. - */ - uint32_t t0_int_clr: 1; - /** wdt_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the TIMG_WDT_INT interrupt. - */ - uint32_t wdt_int_clr: 1; - uint32_t reserved_2: 30; - }; - uint32_t val; -} timg_int_clr_timers_reg_t; - - -/** Group: Version register */ -/** Type of ntimers_date register - * Timer version control register - */ -typedef union { - struct { - /** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409; - * Timer version control register - */ - uint32_t ntimgs_date: 28; - uint32_t reserved_28: 4; - }; - uint32_t val; -} timg_ntimers_date_reg_t; - - -/** Group: Clock configuration registers */ -/** Type of regclk register - * Timer group clock gate register - */ -typedef union { - struct { - uint32_t reserved_0: 29; - /** wdt_clk_is_active : R/W; bitpos: [29]; default: 1; - * enable WDT's clock - */ - uint32_t wdt_clk_is_active: 1; - /** timer_clk_is_active : R/W; bitpos: [30]; default: 1; - * enable Timer $x's clock - */ - uint32_t timer_clk_is_active: 1; - /** clk_en : R/W; bitpos: [31]; default: 0; - * Register clock gate signal. 1: Registers can be read and written to by software. 0: - * Registers can not be read or written to by software. - */ - uint32_t clk_en: 1; - }; - uint32_t val; -} timg_regclk_reg_t; - -typedef struct { - volatile timg_txconfig_reg_t config; - volatile timg_txlo_reg_t lo; - volatile timg_txhi_reg_t hi; - volatile timg_txupdate_reg_t update; - volatile timg_txalarmlo_reg_t alarmlo; - volatile timg_txalarmhi_reg_t alarmhi; - volatile timg_txloadlo_reg_t loadlo; - volatile timg_txloadhi_reg_t loadhi; - volatile timg_txload_reg_t load; -} timg_hwtimer_reg_t; - -typedef struct timg_dev_t { - volatile timg_hwtimer_reg_t hw_timer[1]; - uint32_t reserved_024[9]; - volatile timg_wdtconfig0_reg_t wdtconfig0; - volatile timg_wdtconfig1_reg_t wdtconfig1; - volatile timg_wdtconfig2_reg_t wdtconfig2; - volatile timg_wdtconfig3_reg_t wdtconfig3; - volatile timg_wdtconfig4_reg_t wdtconfig4; - volatile timg_wdtconfig5_reg_t wdtconfig5; - volatile timg_wdtfeed_reg_t wdtfeed; - volatile timg_wdtwprotect_reg_t wdtwprotect; - volatile timg_rtccalicfg_reg_t rtccalicfg; - volatile timg_rtccalicfg1_reg_t rtccalicfg1; - volatile timg_int_ena_timers_reg_t int_ena_timers; - volatile timg_int_raw_timers_reg_t int_raw_timers; - volatile timg_int_st_timers_reg_t int_st_timers; - volatile timg_int_clr_timers_reg_t int_clr_timers; - volatile timg_rtccalicfg2_reg_t rtccalicfg2; - uint32_t reserved_084[29]; - volatile timg_ntimers_date_reg_t ntimers_date; - volatile timg_regclk_reg_t regclk; -} timg_dev_t; - -extern timg_dev_t TIMERG0; -extern timg_dev_t TIMERG1; - -#ifndef __cplusplus -_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32h4/include/soc/uart_channel.h b/components/soc/esp32h4/include/soc/uart_channel.h deleted file mode 100644 index 7de5eb88c0..0000000000 --- a/components/soc/esp32h4/include/soc/uart_channel.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32H4. - -#ifndef _SOC_UART_CHANNEL_H -#define _SOC_UART_CHANNEL_H - -#include "sdkconfig.h" - -//UART channels -#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1 -#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21 -#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 20 - -#define UART_TXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL -#define UART_RXD_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL - -#elif CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_2 -#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 22 -#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0 -#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 21 - -#define UART_TXD_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL -#define UART_RXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL -#endif - -#endif diff --git a/components/soc/esp32h4/include/soc/uart_pins.h b/components/soc/esp32h4/include/soc/uart_pins.h deleted file mode 100644 index 7e9ad2ddaa..0000000000 --- a/components/soc/esp32h4/include/soc/uart_pins.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc/io_mux_reg.h" - -/* Specify the number of pins for UART */ -#define SOC_UART_PINS_COUNT (4) - -/* Specify the GPIO pin number for each UART signal in the IOMUX */ -#define U0RXD_GPIO_NUM 20 -#define U0TXD_GPIO_NUM 21 -#define U0RTS_GPIO_NUM (-1) -#define U0CTS_GPIO_NUM (-1) - -#define U1RXD_GPIO_NUM (-1) -#define U1TXD_GPIO_NUM (-1) -#define U1RTS_GPIO_NUM (-1) -#define U1CTS_GPIO_NUM (-1) - -/* The following defines are necessary for reconfiguring the UART - * to use IOMUX, at runtime. */ -#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD) -#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD) -/* No func for the following pins, they shall not be used */ -#define U0RTS_MUX_FUNC (-1) -#define U0CTS_MUX_FUNC (-1) -/* Same goes for UART1 */ -#define U1TXD_MUX_FUNC (-1) -#define U1RXD_MUX_FUNC (-1) -#define U1RTS_MUX_FUNC (-1) -#define U1CTS_MUX_FUNC (-1) diff --git a/components/soc/esp32h4/include/soc/uart_reg.h b/components/soc/esp32h4/include/soc/uart_reg.h deleted file mode 100644 index 0d31cf34dc..0000000000 --- a/components/soc/esp32h4/include/soc/uart_reg.h +++ /dev/null @@ -1,1250 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_UART_REG_H_ -#define _SOC_UART_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) -/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: UART $n accesses FIFO via this register.*/ -#define UART_RXFIFO_RD_BYTE 0x000000FF -#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) -#define UART_RXFIFO_RD_BYTE_V 0xFF -#define UART_RXFIFO_RD_BYTE_S 0 - -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) -/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when input rxd edge - changes more times than what reg_active_threshold specifies in light sleeping mode.*/ -#define UART_WAKEUP_INT_RAW (BIT(19)) -#define UART_WAKEUP_INT_RAW_M (BIT(19)) -#define UART_WAKEUP_INT_RAW_V 0x1 -#define UART_WAKEUP_INT_RAW_S 19 -/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the configured at_cmd char.*/ -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 -/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when detects a clash - between transmitter and receiver in rs485 mode.*/ -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_V 0x1 -#define UART_RS485_CLASH_INT_RAW_S 17 -/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - a data frame error from the echo of transmitter in rs485 mode.*/ -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 -#define UART_RS485_FRM_ERR_INT_RAW_S 16 -/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - a parity error from the echo of transmitter in rs485 mode.*/ -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 -/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter has - send out all data in FIFO.*/ -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (BIT(14)) -#define UART_TX_DONE_INT_RAW_V 0x1 -#define UART_TX_DONE_INT_RAW_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter has - kept the shortest duration after sending the last data.*/ -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 -/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter completes - sending NULL characters after all data in Tx-FIFO are sent.*/ -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_DONE_INT_RAW_S 12 -/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - a glitch in the middle of a start bit.*/ -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_V 0x1 -#define UART_GLITCH_DET_INT_RAW_S 11 -/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - Xoff char when uart_sw_flow_con_en is set to 1.*/ -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (BIT(10)) -#define UART_SW_XOFF_INT_RAW_V 0x1 -#define UART_SW_XOFF_INT_RAW_S 10 -/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver recevies - Xon char when uart_sw_flow_con_en is set to 1.*/ -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (BIT(9)) -#define UART_SW_XON_INT_RAW_V 0x1 -#define UART_SW_XON_INT_RAW_S 9 -/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver takes - more time than rx_tout_thrhd to receive a byte.*/ -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 -#define UART_RXFIFO_TOUT_INT_RAW_S 8 -/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - a 0 after the stop bit.*/ -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (BIT(7)) -#define UART_BRK_DET_INT_RAW_V 0x1 -#define UART_BRK_DET_INT_RAW_S 7 -/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the edge change of CTSn signal.*/ -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (BIT(6)) -#define UART_CTS_CHG_INT_RAW_V 0x1 -#define UART_CTS_CHG_INT_RAW_S 6 -/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the edge change of DSRn signal.*/ -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (BIT(5)) -#define UART_DSR_CHG_INT_RAW_V 0x1 -#define UART_DSR_CHG_INT_RAW_S 5 -/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - more data than the FIFO can store.*/ -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_V 0x1 -#define UART_RXFIFO_OVF_INT_RAW_S 4 -/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - a data frame error .*/ -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (BIT(3)) -#define UART_FRM_ERR_INT_RAW_V 0x1 -#define UART_FRM_ERR_INT_RAW_S 3 -/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - a parity error in the data.*/ -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_V 0x1 -#define UART_PARITY_ERR_INT_RAW_S 2 -/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */ -/*description: This interrupt raw bit turns to high level when the amount of - data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/ -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 -/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - more data than what rxfifo_full_thrhd specifies.*/ -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_V 0x1 -#define UART_RXFIFO_FULL_INT_RAW_S 0 - -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) -/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena - is set to 1.*/ -#define UART_WAKEUP_INT_ST (BIT(19)) -#define UART_WAKEUP_INT_ST_M (BIT(19)) -#define UART_WAKEUP_INT_ST_V 0x1 -#define UART_WAKEUP_INT_ST_S 19 -/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena - is set to 1.*/ -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 -/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena - is set to 1.*/ -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (BIT(17)) -#define UART_RS485_CLASH_INT_ST_V 0x1 -#define UART_RS485_CLASH_INT_ST_S 17 -/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena - is set to 1.*/ -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_V 0x1 -#define UART_RS485_FRM_ERR_INT_ST_S 16 -/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena - is set to 1.*/ -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ST_S 15 -/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (BIT(14)) -#define UART_TX_DONE_INT_ST_V 0x1 -#define UART_TX_DONE_INT_ST_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - is set to 1.*/ -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 -/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena - is set to 1.*/ -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_DONE_INT_ST_S 12 -/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena - is set to 1.*/ -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (BIT(11)) -#define UART_GLITCH_DET_INT_ST_V 0x1 -#define UART_GLITCH_DET_INT_ST_S 11 -/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (BIT(10)) -#define UART_SW_XOFF_INT_ST_V 0x1 -#define UART_SW_XOFF_INT_ST_S 10 -/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (BIT(9)) -#define UART_SW_XON_INT_ST_V 0x1 -#define UART_SW_XON_INT_ST_S 9 -/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena - is set to 1.*/ -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_V 0x1 -#define UART_RXFIFO_TOUT_INT_ST_S 8 -/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (BIT(7)) -#define UART_BRK_DET_INT_ST_V 0x1 -#define UART_BRK_DET_INT_ST_S 7 -/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (BIT(6)) -#define UART_CTS_CHG_INT_ST_V 0x1 -#define UART_CTS_CHG_INT_ST_S 6 -/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (BIT(5)) -#define UART_DSR_CHG_INT_ST_V 0x1 -#define UART_DSR_CHG_INT_ST_S 5 -/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena - is set to 1.*/ -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_V 0x1 -#define UART_RXFIFO_OVF_INT_ST_S 4 -/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/ -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (BIT(3)) -#define UART_FRM_ERR_INT_ST_V 0x1 -#define UART_FRM_ERR_INT_ST_S 3 -/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena - is set to 1.*/ -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (BIT(2)) -#define UART_PARITY_ERR_INT_ST_V 0x1 -#define UART_PARITY_ERR_INT_ST_S 2 -/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena - is set to 1.*/ -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ST_S 1 -/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena - is set to 1.*/ -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_V 0x1 -#define UART_RXFIFO_FULL_INT_ST_S 0 - -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) -/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the enable bit for uart_wakeup_int_st register.*/ -#define UART_WAKEUP_INT_ENA (BIT(19)) -#define UART_WAKEUP_INT_ENA_M (BIT(19)) -#define UART_WAKEUP_INT_ENA_V 0x1 -#define UART_WAKEUP_INT_ENA_S 19 -/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 -/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_clash_int_st register.*/ -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_V 0x1 -#define UART_RS485_CLASH_INT_ENA_S 17 -/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_parity_err_int_st register.*/ -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 -#define UART_RS485_FRM_ERR_INT_ENA_S 16 -/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_parity_err_int_st register.*/ -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 -/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_done_int_st register.*/ -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (BIT(14)) -#define UART_TX_DONE_INT_ENA_V 0x1 -#define UART_TX_DONE_INT_ENA_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 -/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_brk_done_int_st register.*/ -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_DONE_INT_ENA_S 12 -/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This is the enable bit for glitch_det_int_st register.*/ -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_V 0x1 -#define UART_GLITCH_DET_INT_ENA_S 11 -/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the enable bit for sw_xoff_int_st register.*/ -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (BIT(10)) -#define UART_SW_XOFF_INT_ENA_V 0x1 -#define UART_SW_XOFF_INT_ENA_S 10 -/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This is the enable bit for sw_xon_int_st register.*/ -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (BIT(9)) -#define UART_SW_XON_INT_ENA_V 0x1 -#define UART_SW_XON_INT_ENA_S 9 -/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_tout_int_st register.*/ -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 -#define UART_RXFIFO_TOUT_INT_ENA_S 8 -/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the enable bit for brk_det_int_st register.*/ -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (BIT(7)) -#define UART_BRK_DET_INT_ENA_V 0x1 -#define UART_BRK_DET_INT_ENA_S 7 -/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the enable bit for cts_chg_int_st register.*/ -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (BIT(6)) -#define UART_CTS_CHG_INT_ENA_V 0x1 -#define UART_CTS_CHG_INT_ENA_S 6 -/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the enable bit for dsr_chg_int_st register.*/ -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (BIT(5)) -#define UART_DSR_CHG_INT_ENA_V 0x1 -#define UART_DSR_CHG_INT_ENA_S 5 -/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_V 0x1 -#define UART_RXFIFO_OVF_INT_ENA_S 4 -/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the enable bit for frm_err_int_st register.*/ -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (BIT(3)) -#define UART_FRM_ERR_INT_ENA_V 0x1 -#define UART_FRM_ERR_INT_ENA_S 3 -/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the enable bit for parity_err_int_st register.*/ -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_V 0x1 -#define UART_PARITY_ERR_INT_ENA_S 2 -/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the enable bit for txfifo_empty_int_st register.*/ -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 -/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_full_int_st register.*/ -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_V 0x1 -#define UART_RXFIFO_FULL_INT_ENA_S 0 - -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) -/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear the uart_wakeup_int_raw interrupt.*/ -#define UART_WAKEUP_INT_CLR (BIT(19)) -#define UART_WAKEUP_INT_CLR_M (BIT(19)) -#define UART_WAKEUP_INT_CLR_V 0x1 -#define UART_WAKEUP_INT_CLR_S 19 -/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 -/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_V 0x1 -#define UART_RS485_CLASH_INT_CLR_S 17 -/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 -#define UART_RS485_FRM_ERR_INT_CLR_S 16 -/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 -/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (BIT(14)) -#define UART_TX_DONE_INT_CLR_V 0x1 -#define UART_TX_DONE_INT_CLR_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 -/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_DONE_INT_CLR_S 12 -/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_V 0x1 -#define UART_GLITCH_DET_INT_CLR_S 11 -/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the sw_xoff_int_raw interrupt.*/ -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (BIT(10)) -#define UART_SW_XOFF_INT_CLR_V 0x1 -#define UART_SW_XOFF_INT_CLR_S 10 -/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (BIT(9)) -#define UART_SW_XON_INT_CLR_V 0x1 -#define UART_SW_XON_INT_CLR_S 9 -/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 -#define UART_RXFIFO_TOUT_INT_CLR_S 8 -/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (BIT(7)) -#define UART_BRK_DET_INT_CLR_V 0x1 -#define UART_BRK_DET_INT_CLR_S 7 -/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (BIT(6)) -#define UART_CTS_CHG_INT_CLR_V 0x1 -#define UART_CTS_CHG_INT_CLR_S 6 -/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (BIT(5)) -#define UART_DSR_CHG_INT_CLR_V 0x1 -#define UART_DSR_CHG_INT_CLR_S 5 -/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_V 0x1 -#define UART_RXFIFO_OVF_INT_CLR_S 4 -/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear frm_err_int_raw interrupt.*/ -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (BIT(3)) -#define UART_FRM_ERR_INT_CLR_V 0x1 -#define UART_FRM_ERR_INT_CLR_S 3 -/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear parity_err_int_raw interrupt.*/ -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_V 0x1 -#define UART_PARITY_ERR_INT_CLR_S 2 -/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 -/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_V 0x1 -#define UART_RXFIFO_FULL_INT_CLR_S 0 - -#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) -/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: The decimal part of the frequency divider factor.*/ -#define UART_CLKDIV_FRAG 0x0000000F -#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) -#define UART_CLKDIV_FRAG_V 0xF -#define UART_CLKDIV_FRAG_S 20 -/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */ -/*description: The integral part of the frequency divider factor.*/ -#define UART_CLKDIV 0x00000FFF -#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) -#define UART_CLKDIV_V 0xFFF -#define UART_CLKDIV_S 0 - -#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) -/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enable Rx signal filter.*/ -#define UART_GLITCH_FILT_EN (BIT(8)) -#define UART_GLITCH_FILT_EN_M (BIT(8)) -#define UART_GLITCH_FILT_EN_V 0x1 -#define UART_GLITCH_FILT_EN_S 8 -/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */ -/*description: when input pulse width is lower than this value the pulse is ignored.*/ -#define UART_GLITCH_FILT 0x000000FF -#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) -#define UART_GLITCH_FILT_V 0xFF -#define UART_GLITCH_FILT_S 0 - -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) -/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */ -/*description: This bit represents the level of the internal uart txd signal.*/ -#define UART_TXD (BIT(31)) -#define UART_TXD_M (BIT(31)) -#define UART_TXD_V 0x1 -#define UART_TXD_S 31 -/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This bit represents the level of the internal uart rts signal.*/ -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (BIT(30)) -#define UART_RTSN_V 0x1 -#define UART_RTSN_S 30 -/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit represents the level of the internal uart dtr signal.*/ -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (BIT(29)) -#define UART_DTRN_V 0x1 -#define UART_DTRN_S 29 -/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */ -/*description: Stores the byte number of data in Tx-FIFO.*/ -#define UART_TXFIFO_CNT 0x000003FF -#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) -#define UART_TXFIFO_CNT_V 0x3FF -#define UART_TXFIFO_CNT_S 16 -/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */ -/*description: This register represent the level value of the internal uart rxd signal.*/ -#define UART_RXD (BIT(15)) -#define UART_RXD_M (BIT(15)) -#define UART_RXD_V 0x1 -#define UART_RXD_S 15 -/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */ -/*description: This register represent the level value of the internal uart cts signal.*/ -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (BIT(14)) -#define UART_CTSN_V 0x1 -#define UART_CTSN_S 14 -/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The register represent the level value of the internal uart dsr signal.*/ -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (BIT(13)) -#define UART_DSRN_V 0x1 -#define UART_DSRN_S 13 -/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: Stores the byte number of valid data in Rx-FIFO.*/ -#define UART_RXFIFO_CNT 0x000003FF -#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) -#define UART_RXFIFO_CNT_V 0x3FF -#define UART_RXFIFO_CNT_S 0 - -#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) -/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */ -/*description: UART memory clock gate enable signal.*/ -#define UART_MEM_CLK_EN (BIT(28)) -#define UART_MEM_CLK_EN_M (BIT(28)) -#define UART_MEM_CLK_EN_V 0x1 -#define UART_MEM_CLK_EN_S 28 -/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This is the enable bit for detecting baudrate.*/ -#define UART_AUTOBAUD_EN (BIT(27)) -#define UART_AUTOBAUD_EN_M (BIT(27)) -#define UART_AUTOBAUD_EN_V 0x1 -#define UART_AUTOBAUD_EN_S 27 -/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. - 1'h0: Receiver stores the data even if the received data is wrong.*/ -#define UART_ERR_WR_MASK (BIT(26)) -#define UART_ERR_WR_MASK_M (BIT(26)) -#define UART_ERR_WR_MASK_V 0x1 -#define UART_ERR_WR_MASK_S 26 -/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when - application writes registers.*/ -#define UART_CLK_EN (BIT(25)) -#define UART_CLK_EN_M (BIT(25)) -#define UART_CLK_EN_V 0x1 -#define UART_CLK_EN_S 25 -/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart dtr signal.*/ -#define UART_DTR_INV (BIT(24)) -#define UART_DTR_INV_M (BIT(24)) -#define UART_DTR_INV_V 0x1 -#define UART_DTR_INV_S 24 -/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart rts signal.*/ -#define UART_RTS_INV (BIT(23)) -#define UART_RTS_INV_M (BIT(23)) -#define UART_RTS_INV_V 0x1 -#define UART_RTS_INV_S 23 -/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart txd signal.*/ -#define UART_TXD_INV (BIT(22)) -#define UART_TXD_INV_M (BIT(22)) -#define UART_TXD_INV_V 0x1 -#define UART_TXD_INV_S 22 -/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart dsr signal.*/ -#define UART_DSR_INV (BIT(21)) -#define UART_DSR_INV_M (BIT(21)) -#define UART_DSR_INV_V 0x1 -#define UART_DSR_INV_S 21 -/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart cts signal.*/ -#define UART_CTS_INV (BIT(20)) -#define UART_CTS_INV_M (BIT(20)) -#define UART_CTS_INV_V 0x1 -#define UART_CTS_INV_S 20 -/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart rxd signal.*/ -#define UART_RXD_INV (BIT(19)) -#define UART_RXD_INV_M (BIT(19)) -#define UART_RXD_INV_V 0x1 -#define UART_RXD_INV_S 19 -/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: Set this bit to reset the uart transmit-FIFO.*/ -#define UART_TXFIFO_RST (BIT(18)) -#define UART_TXFIFO_RST_M (BIT(18)) -#define UART_TXFIFO_RST_V 0x1 -#define UART_TXFIFO_RST_S 18 -/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Set this bit to reset the uart receive-FIFO.*/ -#define UART_RXFIFO_RST (BIT(17)) -#define UART_RXFIFO_RST_M (BIT(17)) -#define UART_RXFIFO_RST_V 0x1 -#define UART_RXFIFO_RST_S 17 -/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit to enable IrDA protocol.*/ -#define UART_IRDA_EN (BIT(16)) -#define UART_IRDA_EN_M (BIT(16)) -#define UART_IRDA_EN_V 0x1 -#define UART_IRDA_EN_S 16 -/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable flow control function for transmitter.*/ -#define UART_TX_FLOW_EN (BIT(15)) -#define UART_TX_FLOW_EN_M (BIT(15)) -#define UART_TX_FLOW_EN_V 0x1 -#define UART_TX_FLOW_EN_S 15 -/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable uart loopback test mode.*/ -#define UART_LOOPBACK (BIT(14)) -#define UART_LOOPBACK_M (BIT(14)) -#define UART_LOOPBACK_V 0x1 -#define UART_LOOPBACK_S 14 -/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to invert the level of IrDA receiver.*/ -#define UART_IRDA_RX_INV (BIT(13)) -#define UART_IRDA_RX_INV_M (BIT(13)) -#define UART_IRDA_RX_INV_V 0x1 -#define UART_IRDA_RX_INV_S 13 -/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to invert the level of IrDA transmitter.*/ -#define UART_IRDA_TX_INV (BIT(12)) -#define UART_IRDA_TX_INV_M (BIT(12)) -#define UART_IRDA_TX_INV_V 0x1 -#define UART_IRDA_TX_INV_S 12 -/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. - 1'h0: Set IrDA transmitter's 11th bit to 0.*/ -#define UART_IRDA_WCTL (BIT(11)) -#define UART_IRDA_WCTL_M (BIT(11)) -#define UART_IRDA_WCTL_V 0x1 -#define UART_IRDA_WCTL_S 11 -/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the start enable bit for IrDA transmitter.*/ -#define UART_IRDA_TX_EN (BIT(10)) -#define UART_IRDA_TX_EN_M (BIT(10)) -#define UART_IRDA_TX_EN_V 0x1 -#define UART_IRDA_TX_EN_S 10 -/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to enable IrDA loopback mode.*/ -#define UART_IRDA_DPLX (BIT(9)) -#define UART_IRDA_DPLX_M (BIT(9)) -#define UART_IRDA_DPLX_V 0x1 -#define UART_IRDA_DPLX_S 9 -/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enbale transmitter to send NULL when the process - of sending data is done.*/ -#define UART_TXD_BRK (BIT(8)) -#define UART_TXD_BRK_M (BIT(8)) -#define UART_TXD_BRK_V 0x1 -#define UART_TXD_BRK_S 8 -/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This register is used to configure the software dtr signal which - is used in software flow control.*/ -#define UART_SW_DTR (BIT(7)) -#define UART_SW_DTR_M (BIT(7)) -#define UART_SW_DTR_V 0x1 -#define UART_SW_DTR_S 7 -/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register is used to configure the software rts signal which - is used in software flow control.*/ -#define UART_SW_RTS (BIT(6)) -#define UART_SW_RTS_M (BIT(6)) -#define UART_SW_RTS_V 0x1 -#define UART_SW_RTS_S 6 -/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ -/*description: This register is used to set the length of stop bit.*/ -#define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) -#define UART_STOP_BIT_NUM_V 0x3 -#define UART_STOP_BIT_NUM_S 4 -/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ -/*description: This register is used to set the length of data.*/ -#define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) -#define UART_BIT_NUM_V 0x3 -#define UART_BIT_NUM_S 2 -/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable uart parity check.*/ -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (BIT(1)) -#define UART_PARITY_EN_V 0x1 -#define UART_PARITY_EN_S 1 -/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register is used to configure the parity check mode.*/ -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (BIT(0)) -#define UART_PARITY_V 0x1 -#define UART_PARITY_S 0 - -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) -/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This is the enble bit for uart receiver's timeout function.*/ -#define UART_RX_TOUT_EN (BIT(21)) -#define UART_RX_TOUT_EN_M (BIT(21)) -#define UART_RX_TOUT_EN_V 0x1 -#define UART_RX_TOUT_EN_S 21 -/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This is the flow enable bit for UART receiver.*/ -#define UART_RX_FLOW_EN (BIT(20)) -#define UART_RX_FLOW_EN_M (BIT(20)) -#define UART_RX_FLOW_EN_V 0x1 -#define UART_RX_FLOW_EN_S 20 -/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ -#define UART_RX_TOUT_FLOW_DIS (BIT(19)) -#define UART_RX_TOUT_FLOW_DIS_M (BIT(19)) -#define UART_RX_TOUT_FLOW_DIS_V 0x1 -#define UART_RX_TOUT_FLOW_DIS_S 19 -/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: Disable UART Rx data overflow detect.*/ -#define UART_DIS_RX_DAT_OVF (BIT(18)) -#define UART_DIS_RX_DAT_OVF_M (BIT(18)) -#define UART_DIS_RX_DAT_OVF_V 0x1 -#define UART_DIS_RX_DAT_OVF_S 18 -/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */ -/*description: It will produce txfifo_empty_int interrupt when the data amount - in Tx-FIFO is less than this register value.*/ -#define UART_TXFIFO_EMPTY_THRHD 0x000001FF -#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) -#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF -#define UART_TXFIFO_EMPTY_THRHD_S 9 -/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */ -/*description: It will produce rxfifo_full_int interrupt when receiver receives - more data than this register value.*/ -#define UART_RXFIFO_FULL_THRHD 0x000001FF -#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) -#define UART_RXFIFO_FULL_THRHD_V 0x1FF -#define UART_RXFIFO_FULL_THRHD_S 0 - -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) -/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: This register stores the value of the minimum duration time of - the low level pulse. It is used in baud rate-detect process.*/ -#define UART_LOWPULSE_MIN_CNT 0x00000FFF -#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) -#define UART_LOWPULSE_MIN_CNT_V 0xFFF -#define UART_LOWPULSE_MIN_CNT_S 0 - -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) -/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: This register stores the value of the maxinum duration time - for the high level pulse. It is used in baud rate-detect process.*/ -#define UART_HIGHPULSE_MIN_CNT 0x00000FFF -#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) -#define UART_HIGHPULSE_MIN_CNT_V 0xFFF -#define UART_HIGHPULSE_MIN_CNT_S 0 - -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) -/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register stores the count of rxd edge change. It is used - in baud rate-detect process.*/ -#define UART_RXD_EDGE_CNT 0x000003FF -#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) -#define UART_RXD_EDGE_CNT_V 0x3FF -#define UART_RXD_EDGE_CNT_S 0 - -#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) -/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to send Xoff char. It is cleared by hardware automatically.*/ -#define UART_SEND_XOFF (BIT(5)) -#define UART_SEND_XOFF_M (BIT(5)) -#define UART_SEND_XOFF_V 0x1 -#define UART_SEND_XOFF_S 5 -/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to send Xon char. It is cleared by hardware automatically.*/ -#define UART_SEND_XON (BIT(4)) -#define UART_SEND_XON_M (BIT(4)) -#define UART_SEND_XON_V 0x1 -#define UART_SEND_XON_S 4 -/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to stop the transmitter from sending data.*/ -#define UART_FORCE_XOFF (BIT(3)) -#define UART_FORCE_XOFF_M (BIT(3)) -#define UART_FORCE_XOFF_V 0x1 -#define UART_FORCE_XOFF_S 3 -/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable the transmitter to go on sending data.*/ -#define UART_FORCE_XON (BIT(2)) -#define UART_FORCE_XON_M (BIT(2)) -#define UART_FORCE_XON_V 0x1 -#define UART_FORCE_XON_S 2 -/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to remove flow control char from the received data.*/ -#define UART_XONOFF_DEL (BIT(1)) -#define UART_XONOFF_DEL_M (BIT(1)) -#define UART_XONOFF_DEL_V 0x1 -#define UART_XONOFF_DEL_S 1 -/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable software flow control. It is used with - register sw_xon or sw_xoff.*/ -#define UART_SW_FLOW_CON_EN (BIT(0)) -#define UART_SW_FLOW_CON_EN_M (BIT(0)) -#define UART_SW_FLOW_CON_EN_V 0x1 -#define UART_SW_FLOW_CON_EN_S 0 - -#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) -/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: The uart is activated from light sleeping mode when the input - rxd edge changes more times than this register value.*/ -#define UART_ACTIVE_THRESHOLD 0x000003FF -#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) -#define UART_ACTIVE_THRESHOLD_V 0x3FF -#define UART_ACTIVE_THRESHOLD_S 0 - -#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3C) -/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */ -/*description: This register stores the Xoff flow control char.*/ -#define UART_XOFF_CHAR 0x000000FF -#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) -#define UART_XOFF_CHAR_V 0xFF -#define UART_XOFF_CHAR_S 9 -/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */ -/*description: When the data amount in Rx-FIFO is more than this register value - with uart_sw_flow_con_en set to 1 it will send a Xoff char.*/ -#define UART_XOFF_THRESHOLD 0x000001FF -#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) -#define UART_XOFF_THRESHOLD_V 0x1FF -#define UART_XOFF_THRESHOLD_S 0 - -#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) -/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */ -/*description: This register stores the Xon flow control char.*/ -#define UART_XON_CHAR 0x000000FF -#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) -#define UART_XON_CHAR_V 0xFF -#define UART_XON_CHAR_S 9 -/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: When the data amount in Rx-FIFO is less than this register value - with uart_sw_flow_con_en set to 1 it will send a Xon char.*/ -#define UART_XON_THRESHOLD 0x000001FF -#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) -#define UART_XON_THRESHOLD_V 0x1FF -#define UART_XON_THRESHOLD_S 0 - -#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) -/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */ -/*description: This register is used to configure the number of 0 to be sent - after the process of sending data is done. It is active when txd_brk is set to 1.*/ -#define UART_TX_BRK_NUM 0x000000FF -#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) -#define UART_TX_BRK_NUM_V 0xFF -#define UART_TX_BRK_NUM_S 0 - -#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48) -/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ -/*description: This register is used to configure the duration time between transfers.*/ -#define UART_TX_IDLE_NUM 0x000003FF -#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) -#define UART_TX_IDLE_NUM_V 0x3FF -#define UART_TX_IDLE_NUM_S 10 -/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ -/*description: It will produce frame end signal when receiver takes more time - to receive one byte data than this register value.*/ -#define UART_RX_IDLE_THRHD 0x000003FF -#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) -#define UART_RX_IDLE_THRHD_V 0x3FF -#define UART_RX_IDLE_THRHD_S 0 - -#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c) -/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ -/*description: This register is used to delay the transmitter's internal data signal.*/ -#define UART_RS485_TX_DLY_NUM 0x0000000F -#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) -#define UART_RS485_TX_DLY_NUM_V 0xF -#define UART_RS485_TX_DLY_NUM_S 6 -/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This register is used to delay the receiver's internal data signal.*/ -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (BIT(5)) -#define UART_RS485_RX_DLY_NUM_V 0x1 -#define UART_RS485_RX_DLY_NUM_S 5 -/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/ -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (BIT(4)) -#define UART_RS485RXBY_TX_EN_V 0x1 -#define UART_RS485RXBY_TX_EN_S 4 -/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable receiver could receive data when the transmitter - is transmitting data in rs485 mode.*/ -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (BIT(3)) -#define UART_RS485TX_RX_EN_V 0x1 -#define UART_RS485TX_RX_EN_S 3 -/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to delay the stop bit by 1 bit.*/ -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (BIT(2)) -#define UART_DL1_EN_V 0x1 -#define UART_DL1_EN_S 2 -/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to delay the stop bit by 1 bit.*/ -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (BIT(1)) -#define UART_DL0_EN_V 0x1 -#define UART_DL0_EN_S 1 -/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to choose the rs485 mode.*/ -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (BIT(0)) -#define UART_RS485_EN_V 0x1 -#define UART_RS485_EN_S 0 - -#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) -/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ -/*description: This register is used to configure the idle duration time before - the first at_cmd is received by receiver.*/ -#define UART_PRE_IDLE_NUM 0x0000FFFF -#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) -#define UART_PRE_IDLE_NUM_V 0xFFFF -#define UART_PRE_IDLE_NUM_S 0 - -#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) -/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ -/*description: This register is used to configure the duration time between - the last at_cmd and the next data.*/ -#define UART_POST_IDLE_NUM 0x0000FFFF -#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) -#define UART_POST_IDLE_NUM_V 0xFFFF -#define UART_POST_IDLE_NUM_S 0 - -#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) -/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */ -/*description: This register is used to configure the duration time between the at_cmd chars.*/ -#define UART_RX_GAP_TOUT 0x0000FFFF -#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) -#define UART_RX_GAP_TOUT_V 0xFFFF -#define UART_RX_GAP_TOUT_S 0 - -#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c) -/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ -/*description: This register is used to configure the num of continuous at_cmd - chars received by receiver.*/ -#define UART_CHAR_NUM 0x000000FF -#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) -#define UART_CHAR_NUM_V 0xFF -#define UART_CHAR_NUM_S 8 -/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ -/*description: This register is used to configure the content of at_cmd char.*/ -#define UART_AT_CMD_CHAR 0x000000FF -#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) -#define UART_AT_CMD_CHAR_V 0xFF -#define UART_AT_CMD_CHAR_S 0 - -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) -/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to force power up UART memory.*/ -#define UART_MEM_FORCE_PU (BIT(27)) -#define UART_MEM_FORCE_PU_M (BIT(27)) -#define UART_MEM_FORCE_PU_V 0x1 -#define UART_MEM_FORCE_PU_S 27 -/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to force power down UART memory.*/ -#define UART_MEM_FORCE_PD (BIT(26)) -#define UART_MEM_FORCE_PD_M (BIT(26)) -#define UART_MEM_FORCE_PD_V 0x1 -#define UART_MEM_FORCE_PD_S 26 -/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */ -/*description: This register is used to configure the threshold time that receiver - takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/ -#define UART_RX_TOUT_THRHD 0x000003FF -#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) -#define UART_RX_TOUT_THRHD_V 0x3FF -#define UART_RX_TOUT_THRHD_S 16 -/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */ -/*description: This register is used to configure the maximum amount of data - that can be received when hardware flow control works.*/ -#define UART_RX_FLOW_THRHD 0x000001FF -#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) -#define UART_RX_FLOW_THRHD_V 0x1FF -#define UART_RX_FLOW_THRHD_S 7 -/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */ -/*description: This register is used to configure the amount of mem allocated - for transmit-FIFO. The default number is 128 bytes.*/ -#define UART_TX_SIZE 0x00000007 -#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) -#define UART_TX_SIZE_V 0x7 -#define UART_TX_SIZE_S 4 -/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */ -/*description: This register is used to configure the amount of mem allocated - for receive-FIFO. The default number is 128 bytes.*/ -#define UART_RX_SIZE 0x00000007 -#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) -#define UART_RX_SIZE_V 0x7 -#define UART_RX_SIZE_S 1 - -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) -/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */ -/*description: This register stores the offset address in Tx-FIFO when Tx-FSM - reads data via Tx-FIFO_Ctrl.*/ -#define UART_TX_RADDR 0x000003FF -#define UART_TX_RADDR_M ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S)) -#define UART_TX_RADDR_V 0x3FF -#define UART_TX_RADDR_S 11 -/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register stores the offset address in Tx-FIFO when software - writes Tx-FIFO via APB.*/ -#define UART_APB_TX_WADDR 0x000003FF -#define UART_APB_TX_WADDR_M ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S)) -#define UART_APB_TX_WADDR_V 0x3FF -#define UART_APB_TX_WADDR_S 0 - -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) -/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */ -/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl - writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/ -#define UART_RX_WADDR 0x000003FF -#define UART_RX_WADDR_M ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S)) -#define UART_RX_WADDR_V 0x3FF -#define UART_RX_WADDR_S 11 -/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */ -/*description: This register stores the offset address in RX-FIFO when software - reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/ -#define UART_APB_RX_RADDR 0x000003FF -#define UART_APB_RX_RADDR_M ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S)) -#define UART_APB_RX_RADDR_V 0x3FF -#define UART_APB_RX_RADDR_S 0 - -#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) -/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: This is the status register of transmitter.*/ -#define UART_ST_UTX_OUT 0x0000000F -#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) -#define UART_ST_UTX_OUT_V 0xF -#define UART_ST_UTX_OUT_S 4 -/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: This is the status register of receiver.*/ -#define UART_ST_URX_OUT 0x0000000F -#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) -#define UART_ST_URX_OUT_V 0xF -#define UART_ST_URX_OUT_S 0 - -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) -/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: This register stores the minimal input clock count between two - positive edges. It is used in boudrate-detect process.*/ -#define UART_POSEDGE_MIN_CNT 0x00000FFF -#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) -#define UART_POSEDGE_MIN_CNT_V 0xFFF -#define UART_POSEDGE_MIN_CNT_S 0 - -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) -/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ -/*description: This register stores the minimal input clock count between two - negative edges. It is used in boudrate-detect process.*/ -#define UART_NEGEDGE_MIN_CNT 0x00000FFF -#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) -#define UART_NEGEDGE_MIN_CNT_V 0xFFF -#define UART_NEGEDGE_MIN_CNT_S 0 - -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78) -/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Write 1 then write 0 to this bit reset UART Rx.*/ -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (BIT(27)) -#define UART_RX_RST_CORE_V 0x1 -#define UART_RX_RST_CORE_S 27 -/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Write 1 then write 0 to this bit reset UART Tx.*/ -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (BIT(26)) -#define UART_TX_RST_CORE_V 0x1 -#define UART_TX_RST_CORE_S 26 -/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: Set this bit to enable UART Rx clock.*/ -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (BIT(25)) -#define UART_RX_SCLK_EN_V 0x1 -#define UART_RX_SCLK_EN_S 25 -/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: Set this bit to enable UART Tx clock.*/ -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (BIT(24)) -#define UART_TX_SCLK_EN_V 0x1 -#define UART_TX_SCLK_EN_S 24 -/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Write 1 then write 0 to this bit reset UART Tx/Rx.*/ -#define UART_RST_CORE (BIT(23)) -#define UART_RST_CORE_M (BIT(23)) -#define UART_RST_CORE_V 0x1 -#define UART_RST_CORE_S 23 -/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: Set this bit to enable UART Tx/Rx clock.*/ -#define UART_SCLK_EN (BIT(22)) -#define UART_SCLK_EN_M (BIT(22)) -#define UART_SCLK_EN_V 0x1 -#define UART_SCLK_EN_S 22 -/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */ -/*description: UART clock source select. 1: 80Mhz 2: 8Mhz 3: XTAL.*/ -#define UART_SCLK_SEL 0x00000003 -#define UART_SCLK_SEL_M ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S)) -#define UART_SCLK_SEL_V 0x3 -#define UART_SCLK_SEL_S 20 -/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */ -/*description: The integral part of the frequency divider factor.*/ -#define UART_SCLK_DIV_NUM 0x000000FF -#define UART_SCLK_DIV_NUM_M ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S)) -#define UART_SCLK_DIV_NUM_V 0xFF -#define UART_SCLK_DIV_NUM_S 12 -/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */ -/*description: The numerator of the frequency divider factor.*/ -#define UART_SCLK_DIV_A 0x0000003F -#define UART_SCLK_DIV_A_M ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S)) -#define UART_SCLK_DIV_A_V 0x3F -#define UART_SCLK_DIV_A_S 6 -/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ -/*description: The denominator of the frequency divider factor.*/ -#define UART_SCLK_DIV_B 0x0000003F -#define UART_SCLK_DIV_B_M ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S)) -#define UART_SCLK_DIV_B_V 0x3F -#define UART_SCLK_DIV_B_S 0 - -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c) -/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */ -/*description: This is the version register.*/ -#define UART_DATE 0xFFFFFFFF -#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) -#define UART_DATE_V 0xFFFFFFFF -#define UART_DATE_S 0 - -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) -/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Software write 1 would synchronize registers into UART Core clock - domain and would be cleared by hardware after synchronization is done.*/ -#define UART_UPDATE (BIT(31)) -#define UART_UPDATE_M (BIT(31)) -#define UART_UPDATE_V 0x1 -#define UART_UPDATE_S 31 -/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This bit used to select synchronize mode. 1: Registers are auto - synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers software needs to write 1 to UART_REG_UPDATE to synchronize registers.*/ -#define UART_HIGH_SPEED (BIT(30)) -#define UART_HIGH_SPEED_M (BIT(30)) -#define UART_HIGH_SPEED_V 0x1 -#define UART_HIGH_SPEED_S 30 -/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */ -/*description: This register is used to configure the uart_id.*/ -#define UART_ID 0x3FFFFFFF -#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) -#define UART_ID_V 0x3FFFFFFF -#define UART_ID_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_UART_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/uart_struct.h b/components/soc/esp32h4/include/soc/uart_struct.h deleted file mode 100644 index eec9703406..0000000000 --- a/components/soc/esp32h4/include/soc/uart_struct.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_UART_STRUCT_H_ -#define _SOC_UART_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct uart_dev_s { - union { - struct { - uint32_t rw_byte; /*a*/ - }; - uint32_t val; - } ahb_fifo; - union { - struct { - uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/ - uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/ - uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/ - uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/ - uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/ - uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/ - uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/ - uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/ - uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/ - uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/ - uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/ - uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.*/ - uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.*/ - uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/ - uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/ - uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/ - uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/ - uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/ - uint32_t wakeup: 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/ - uint32_t reserved20: 12; /*Reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ - uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ - uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ - uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/ - uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ - uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ - uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ - uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ - uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ - uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ - uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ - uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ - uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ - uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ - uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ - uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ - uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ - uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ - uint32_t wakeup: 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/ - uint32_t reserved20: 12; /*Reserved*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t txfifo_empty: 1; /*This is the enable bit for txfifo_empty_int_st register.*/ - uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ - uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ - uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ - uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ - uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ - uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ - uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ - uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ - uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ - uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ - uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ - uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ - uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ - uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ - uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ - uint32_t wakeup: 1; /*This is the enable bit for uart_wakeup_int_st register.*/ - uint32_t reserved20: 12; /*Reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ - uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ - uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ - uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ - uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ - uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ - uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ - uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ - uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ - uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/ - uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ - uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ - uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ - uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ - uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ - uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ - uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ - uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ - uint32_t wakeup: 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/ - uint32_t reserved20: 12; /*Reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t div_int: 12; /*The integral part of the frequency divider factor.*/ - uint32_t reserved12: 8; - uint32_t div_frag: 4; /*The decimal part of the frequency divider factor.*/ - uint32_t reserved24: 8; /*Reserved*/ - }; - uint32_t val; - } clk_div; - union { - struct { - uint32_t glitch_filt: 8; /*when input pulse width is lower than this value the pulse is ignored.*/ - uint32_t glitch_filt_en: 1; /*Set this bit to enable Rx signal filter.*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } rx_filt; - union { - struct { - uint32_t rxfifo_cnt:10; /*Stores the byte number of valid data in Rx-FIFO.*/ - uint32_t reserved10: 3; - uint32_t dsrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ - uint32_t ctsn: 1; /*This register represent the level value of the internal uart cts signal.*/ - uint32_t rxd: 1; /*This register represent the level value of the internal uart rxd signal.*/ - uint32_t txfifo_cnt:10; /*Stores the byte number of data in Tx-FIFO.*/ - uint32_t reserved26: 3; /*Reserved*/ - uint32_t dtrn: 1; /*This bit represents the level of the internal uart dtr signal.*/ - uint32_t rtsn: 1; /*This bit represents the level of the internal uart rts signal.*/ - uint32_t txd: 1; /*This bit represents the level of the internal uart txd signal.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t parity: 1; /*This register is used to configure the parity check mode.*/ - uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ - uint32_t bit_num: 2; /*This register is used to set the length of data.*/ - uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit.*/ - uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ - uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/ - uint32_t txd_brk: 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/ - uint32_t irda_dplx: 1; /*Set this bit to enable IrDA loopback mode.*/ - uint32_t irda_tx_en: 1; /*This is the start enable bit for IrDA transmitter.*/ - uint32_t irda_wctl: 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/ - uint32_t irda_tx_inv: 1; /*Set this bit to invert the level of IrDA transmitter.*/ - uint32_t irda_rx_inv: 1; /*Set this bit to invert the level of IrDA receiver.*/ - uint32_t loopback: 1; /*Set this bit to enable uart loopback test mode.*/ - uint32_t tx_flow_en: 1; /*Set this bit to enable flow control function for transmitter.*/ - uint32_t irda_en: 1; /*Set this bit to enable IrDA protocol.*/ - uint32_t rxfifo_rst: 1; /*Set this bit to reset the uart receive-FIFO.*/ - uint32_t txfifo_rst: 1; /*Set this bit to reset the uart transmit-FIFO.*/ - uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ - uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ - uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ - uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ - uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ - uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ - uint32_t clk_en: 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/ - uint32_t err_wr_mask: 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/ - uint32_t autobaud_en: 1; /*This is the enable bit for detecting baudrate.*/ - uint32_t mem_clk_en: 1; /*UART memory clock gate enable signal.*/ - uint32_t reserved29: 3; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t rxfifo_full_thrhd: 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/ - uint32_t txfifo_empty_thrhd: 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/ - uint32_t dis_rx_dat_ovf: 1; /*Disable UART Rx data overflow detect.*/ - uint32_t rx_tout_flow_dis: 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/ - uint32_t rx_flow_en: 1; /*This is the flow enable bit for UART receiver.*/ - uint32_t rx_tout_en: 1; /*This is the enble bit for uart receiver's timeout function.*/ - uint32_t reserved22: 10; - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t min_cnt: 12; /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/ - uint32_t reserved12: 20; /*Reserved*/ - }; - uint32_t val; - } lowpulse; - union { - struct { - uint32_t min_cnt: 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/ - uint32_t reserved12: 20; /*Reserved*/ - }; - uint32_t val; - } highpulse; - union { - struct { - uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/ - uint32_t reserved10: 22; /*Reserved*/ - }; - uint32_t val; - } rxd_cnt; - union { - struct { - uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/ - uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ - uint32_t force_xon: 1; /*Set this bit to enable the transmitter to go on sending data.*/ - uint32_t force_xoff: 1; /*Set this bit to stop the transmitter from sending data.*/ - uint32_t send_xon: 1; /*Set this bit to send Xon char. It is cleared by hardware automatically.*/ - uint32_t send_xoff: 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/ - uint32_t reserved6: 26; /*Reserved*/ - }; - uint32_t val; - } flow_conf; - union { - struct { - uint32_t active_threshold:10; /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/ - uint32_t reserved10: 22; /*Reserved*/ - }; - uint32_t val; - } sleep_conf; - union { - struct { - uint32_t xoff_threshold: 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char.*/ - uint32_t xoff_char: 8; /*This register stores the Xoff flow control char.*/ - uint32_t reserved17: 15; /*Reserved*/ - }; - uint32_t val; - } swfc_conf0; - union { - struct { - uint32_t xon_threshold: 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char.*/ - uint32_t xon_char: 8; /*This register stores the Xon flow control char.*/ - uint32_t reserved17: 15; /*Reserved*/ - }; - uint32_t val; - } swfc_conf1; - union { - struct { - uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/ - uint32_t reserved8: 24; - }; - uint32_t val; - } txbrk_conf; - union { - struct { - uint32_t rx_idle_thrhd:10; /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/ - uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ - uint32_t reserved20: 12; /*Reserved*/ - }; - uint32_t val; - } idle_conf; - union { - struct { - uint32_t en: 1; /*Set this bit to choose the rs485 mode.*/ - uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t tx_rx_en: 1; /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.*/ - uint32_t rx_busy_tx_en: 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/ - uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ - uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ - uint32_t reserved10: 22; /*Reserved*/ - }; - uint32_t val; - } rs485_conf; - union { - struct { - uint32_t pre_idle_num:16; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver.*/ - uint32_t reserved16: 16; /*Reserved*/ - }; - uint32_t val; - } at_cmd_precnt; - union { - struct { - uint32_t post_idle_num:16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/ - uint32_t reserved16: 16; /*Reserved*/ - }; - uint32_t val; - } at_cmd_postcnt; - union { - struct { - uint32_t rx_gap_tout:16; /*This register is used to configure the duration time between the at_cmd chars.*/ - uint32_t reserved16: 16; /*Reserved*/ - }; - uint32_t val; - } at_cmd_gaptout; - union { - struct { - uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ - uint32_t char_num: 8; /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/ - uint32_t reserved16: 16; /*Reserved*/ - }; - uint32_t val; - } at_cmd_char; - union { - struct { - uint32_t reserved0: 1; - uint32_t rx_size: 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/ - uint32_t tx_size: 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/ - uint32_t rx_flow_thrhd: 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/ - uint32_t rx_tout_thrhd:10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/ - uint32_t force_pd: 1; /*Set this bit to force power down UART memory.*/ - uint32_t force_pu: 1; /*Set this bit to force power up UART memory.*/ - uint32_t reserved28: 4; - }; - uint32_t val; - } mem_conf; - union { - struct { - uint32_t apb_tx_waddr:10; /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/ - uint32_t reserved10: 1; /*Reserved*/ - uint32_t tx_raddr: 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/ - uint32_t reserved21: 11; /*Reserved*/ - }; - uint32_t val; - } mem_tx_status; - union { - struct { - uint32_t apb_rx_raddr:10; /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/ - uint32_t reserved10: 1; /*Reserved*/ - uint32_t rx_waddr: 10; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/ - uint32_t reserved21: 11; /*Reserved*/ - }; - uint32_t val; - } mem_rx_status; - union { - struct { - uint32_t st_urx_out: 4; /*This is the status register of receiver.*/ - uint32_t st_utx_out: 4; /*This is the status register of transmitter.*/ - uint32_t reserved8: 24; /*Reserved*/ - }; - uint32_t val; - } fsm_status; - union { - struct { - uint32_t min_cnt: 12; /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/ - uint32_t reserved12: 20; /*Reserved*/ - }; - uint32_t val; - } pospulse; - union { - struct { - uint32_t min_cnt: 12; /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/ - uint32_t reserved12: 20; /*Reserved*/ - }; - uint32_t val; - } negpulse; - union { - struct { - uint32_t sclk_div_b: 6; /*The denominator of the frequency divider factor.*/ - uint32_t sclk_div_a: 6; /*The numerator of the frequency divider factor.*/ - uint32_t sclk_div_num: 8; /*The integral part of the frequency divider factor.*/ - uint32_t sclk_sel: 2; /*UART clock source select. 1: 80Mhz 2: 8Mhz 3: XTAL.*/ - uint32_t sclk_en: 1; /*Set this bit to enable UART Tx/Rx clock.*/ - uint32_t rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx/Rx.*/ - uint32_t tx_sclk_en: 1; /*Set this bit to enable UART Tx clock.*/ - uint32_t rx_sclk_en: 1; /*Set this bit to enable UART Rx clock.*/ - uint32_t tx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx.*/ - uint32_t rx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Rx.*/ - uint32_t reserved28: 4; - }; - uint32_t val; - } clk_conf; - uint32_t date; /*UART Version register*/ - union { - struct { - uint32_t id : 30; /*This register is used to configure the uart_id.*/ - uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */ - uint32_t update : 1; /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/ - }; - uint32_t val; - } id; -} uart_dev_t; -extern uart_dev_t UART0; -extern uart_dev_t UART1; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_UART_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/soc/uhci_reg.h b/components/soc/esp32h4/include/soc/uhci_reg.h deleted file mode 100644 index 7945e9fc05..0000000000 --- a/components/soc/esp32h4/include/soc/uhci_reg.h +++ /dev/null @@ -1,740 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_UHCI_REG_H_ -#define _SOC_UHCI_REG_H_ - -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif -#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) -/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: If this bit is set to 1 UHCI will end payload receive process - when NULL frame is received by UART.*/ -#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) -#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12)) -#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 -#define UHCI_UART_RX_BRK_EOF_EN_S 12 -/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 1'b1: Force clock on for register. 1'b0: Support clock only when - application writes registers.*/ -#define UHCI_CLK_EN (BIT(11)) -#define UHCI_CLK_EN_M (BIT(11)) -#define UHCI_CLK_EN_V 0x1 -#define UHCI_CLK_EN_S 11 -/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: Set this bit to enable data integrity checking by appending a - 16 bit CCITT-CRC to end of the payload.*/ -#define UHCI_ENCODE_CRC_EN (BIT(10)) -#define UHCI_ENCODE_CRC_EN_M (BIT(10)) -#define UHCI_ENCODE_CRC_EN_V 0x1 -#define UHCI_ENCODE_CRC_EN_S 10 -/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: If this bit is set to 1 UHCI decoder receiving payload data - is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/ -#define UHCI_LEN_EOF_EN (BIT(9)) -#define UHCI_LEN_EOF_EN_M (BIT(9)) -#define UHCI_LEN_EOF_EN_V 0x1 -#define UHCI_LEN_EOF_EN_S 9 -/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: If this bit is set to 1 UHCI will end the payload receiving - process when UART has been in idle state.*/ -#define UHCI_UART_IDLE_EOF_EN (BIT(8)) -#define UHCI_UART_IDLE_EOF_EN_M (BIT(8)) -#define UHCI_UART_IDLE_EOF_EN_V 0x1 -#define UHCI_UART_IDLE_EOF_EN_S 8 -/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/ -#define UHCI_CRC_REC_EN (BIT(7)) -#define UHCI_CRC_REC_EN_M (BIT(7)) -#define UHCI_CRC_REC_EN_V 0x1 -#define UHCI_CRC_REC_EN_S 7 -/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Set this bit to encode the data packet with a formatting header.*/ -#define UHCI_HEAD_EN (BIT(6)) -#define UHCI_HEAD_EN_M (BIT(6)) -#define UHCI_HEAD_EN_V 0x1 -#define UHCI_HEAD_EN_S 6 -/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: Set this bit to separate the data frame using a special char.*/ -#define UHCI_SEPER_EN (BIT(5)) -#define UHCI_SEPER_EN_M (BIT(5)) -#define UHCI_SEPER_EN_V 0x1 -#define UHCI_SEPER_EN_S 5 -/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to link up HCI and UART1.*/ -#define UHCI_UART1_CE (BIT(3)) -#define UHCI_UART1_CE_M (BIT(3)) -#define UHCI_UART1_CE_V 0x1 -#define UHCI_UART1_CE_S 3 -/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to link up HCI and UART0.*/ -#define UHCI_UART0_CE (BIT(2)) -#define UHCI_UART0_CE_M (BIT(2)) -#define UHCI_UART0_CE_V 0x1 -#define UHCI_UART0_CE_S 2 -/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Write 1 then write 0 to this bit to reset encode state machine.*/ -#define UHCI_RX_RST (BIT(1)) -#define UHCI_RX_RST_M (BIT(1)) -#define UHCI_RX_RST_V 0x1 -#define UHCI_RX_RST_S 1 -/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Write 1 then write 0 to this bit to reset decode state machine.*/ -#define UHCI_TX_RST (BIT(0)) -#define UHCI_TX_RST_M (BIT(0)) -#define UHCI_TX_RST_V 0x1 -#define UHCI_TX_RST_S 0 - -#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) -/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Soft control int raw bit.*/ -#define UHCI_APP_CTRL1_INT_RAW (BIT(8)) -#define UHCI_APP_CTRL1_INT_RAW_M (BIT(8)) -#define UHCI_APP_CTRL1_INT_RAW_V 0x1 -#define UHCI_APP_CTRL1_INT_RAW_S 8 -/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Soft control int raw bit.*/ -#define UHCI_APP_CTRL0_INT_RAW (BIT(7)) -#define UHCI_APP_CTRL0_INT_RAW_M (BIT(7)) -#define UHCI_APP_CTRL0_INT_RAW_V 0x1 -#define UHCI_APP_CTRL0_INT_RAW_S 7 -/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit. Triggered when there are some - errors in EOF in the*/ -#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1 -#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6 -/* UHCI_SEND_A_Q_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_A_Q_INT_RAW (BIT(5)) -#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_RAW_V 0x1 -#define UHCI_SEND_A_Q_INT_RAW_S 5 -/* UHCI_SEND_S_Q_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_S_Q_INT_RAW (BIT(4)) -#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_RAW_V 0x1 -#define UHCI_SEND_S_Q_INT_RAW_S 4 -/* UHCI_TX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_HUNG_INT_RAW (BIT(3)) -#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) -#define UHCI_TX_HUNG_INT_RAW_V 0x1 -#define UHCI_TX_HUNG_INT_RAW_S 3 -/* UHCI_RX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_HUNG_INT_RAW (BIT(2)) -#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) -#define UHCI_RX_HUNG_INT_RAW_V 0x1 -#define UHCI_RX_HUNG_INT_RAW_S 2 -/* UHCI_TX_START_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_START_INT_RAW (BIT(1)) -#define UHCI_TX_START_INT_RAW_M (BIT(1)) -#define UHCI_TX_START_INT_RAW_V 0x1 -#define UHCI_TX_START_INT_RAW_S 1 -/* UHCI_RX_START_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_START_INT_RAW (BIT(0)) -#define UHCI_RX_START_INT_RAW_M (BIT(0)) -#define UHCI_RX_START_INT_RAW_V 0x1 -#define UHCI_RX_START_INT_RAW_S 0 - -#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) -/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_APP_CTRL1_INT_ST (BIT(8)) -#define UHCI_APP_CTRL1_INT_ST_M (BIT(8)) -#define UHCI_APP_CTRL1_INT_ST_V 0x1 -#define UHCI_APP_CTRL1_INT_ST_S 8 -/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_APP_CTRL0_INT_ST (BIT(7)) -#define UHCI_APP_CTRL0_INT_ST_M (BIT(7)) -#define UHCI_APP_CTRL0_INT_ST_V 0x1 -#define UHCI_APP_CTRL0_INT_ST_S 7 -/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1 -#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6 -/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_A_Q_INT_ST (BIT(5)) -#define UHCI_SEND_A_Q_INT_ST_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_ST_V 0x1 -#define UHCI_SEND_A_Q_INT_ST_S 5 -/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_S_Q_INT_ST (BIT(4)) -#define UHCI_SEND_S_Q_INT_ST_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_ST_V 0x1 -#define UHCI_SEND_S_Q_INT_ST_S 4 -/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_HUNG_INT_ST (BIT(3)) -#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) -#define UHCI_TX_HUNG_INT_ST_V 0x1 -#define UHCI_TX_HUNG_INT_ST_S 3 -/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_HUNG_INT_ST (BIT(2)) -#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) -#define UHCI_RX_HUNG_INT_ST_V 0x1 -#define UHCI_RX_HUNG_INT_ST_S 2 -/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_START_INT_ST (BIT(1)) -#define UHCI_TX_START_INT_ST_M (BIT(1)) -#define UHCI_TX_START_INT_ST_V 0x1 -#define UHCI_TX_START_INT_ST_S 1 -/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_START_INT_ST (BIT(0)) -#define UHCI_RX_START_INT_ST_M (BIT(0)) -#define UHCI_RX_START_INT_ST_V 0x1 -#define UHCI_RX_START_INT_ST_S 0 - -#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) -/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_APP_CTRL1_INT_ENA (BIT(8)) -#define UHCI_APP_CTRL1_INT_ENA_M (BIT(8)) -#define UHCI_APP_CTRL1_INT_ENA_V 0x1 -#define UHCI_APP_CTRL1_INT_ENA_S 8 -/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_APP_CTRL0_INT_ENA (BIT(7)) -#define UHCI_APP_CTRL0_INT_ENA_M (BIT(7)) -#define UHCI_APP_CTRL0_INT_ENA_V 0x1 -#define UHCI_APP_CTRL0_INT_ENA_S 7 -/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1 -#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6 -/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_A_Q_INT_ENA (BIT(5)) -#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_ENA_V 0x1 -#define UHCI_SEND_A_Q_INT_ENA_S 5 -/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_S_Q_INT_ENA (BIT(4)) -#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_ENA_V 0x1 -#define UHCI_SEND_S_Q_INT_ENA_S 4 -/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_HUNG_INT_ENA (BIT(3)) -#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) -#define UHCI_TX_HUNG_INT_ENA_V 0x1 -#define UHCI_TX_HUNG_INT_ENA_S 3 -/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_HUNG_INT_ENA (BIT(2)) -#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) -#define UHCI_RX_HUNG_INT_ENA_V 0x1 -#define UHCI_RX_HUNG_INT_ENA_S 2 -/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_START_INT_ENA (BIT(1)) -#define UHCI_TX_START_INT_ENA_M (BIT(1)) -#define UHCI_TX_START_INT_ENA_V 0x1 -#define UHCI_TX_START_INT_ENA_S 1 -/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_START_INT_ENA (BIT(0)) -#define UHCI_RX_START_INT_ENA_M (BIT(0)) -#define UHCI_RX_START_INT_ENA_V 0x1 -#define UHCI_RX_START_INT_ENA_S 0 - -#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) -/* UHCI_APP_CTRL1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_APP_CTRL1_INT_CLR (BIT(8)) -#define UHCI_APP_CTRL1_INT_CLR_M (BIT(8)) -#define UHCI_APP_CTRL1_INT_CLR_V 0x1 -#define UHCI_APP_CTRL1_INT_CLR_S 8 -/* UHCI_APP_CTRL0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_APP_CTRL0_INT_CLR (BIT(7)) -#define UHCI_APP_CTRL0_INT_CLR_M (BIT(7)) -#define UHCI_APP_CTRL0_INT_CLR_V 0x1 -#define UHCI_APP_CTRL0_INT_CLR_S 7 -/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6)) -#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1 -#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6 -/* UHCI_SEND_A_Q_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_A_Q_INT_CLR (BIT(5)) -#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5)) -#define UHCI_SEND_A_Q_INT_CLR_V 0x1 -#define UHCI_SEND_A_Q_INT_CLR_S 5 -/* UHCI_SEND_S_Q_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SEND_S_Q_INT_CLR (BIT(4)) -#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4)) -#define UHCI_SEND_S_Q_INT_CLR_V 0x1 -#define UHCI_SEND_S_Q_INT_CLR_S 4 -/* UHCI_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_HUNG_INT_CLR (BIT(3)) -#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) -#define UHCI_TX_HUNG_INT_CLR_V 0x1 -#define UHCI_TX_HUNG_INT_CLR_S 3 -/* UHCI_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_HUNG_INT_CLR (BIT(2)) -#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) -#define UHCI_RX_HUNG_INT_CLR_V 0x1 -#define UHCI_RX_HUNG_INT_CLR_S 2 -/* UHCI_TX_START_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_START_INT_CLR (BIT(1)) -#define UHCI_TX_START_INT_CLR_M (BIT(1)) -#define UHCI_TX_START_INT_CLR_V 0x1 -#define UHCI_TX_START_INT_CLR_S 1 -/* UHCI_RX_START_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_START_INT_CLR (BIT(0)) -#define UHCI_RX_START_INT_CLR_M (BIT(0)) -#define UHCI_RX_START_INT_CLR_V 0x1 -#define UHCI_RX_START_INT_CLR_S 0 - -#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14) -/* UHCI_SW_START : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SW_START (BIT(8)) -#define UHCI_SW_START_M (BIT(8)) -#define UHCI_SW_START_V 0x1 -#define UHCI_SW_START_S 8 -/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_WAIT_SW_START (BIT(7)) -#define UHCI_WAIT_SW_START_M (BIT(7)) -#define UHCI_WAIT_SW_START_V 0x1 -#define UHCI_WAIT_SW_START_S 7 -/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_TX_ACK_NUM_RE (BIT(5)) -#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) -#define UHCI_TX_ACK_NUM_RE_V 0x1 -#define UHCI_TX_ACK_NUM_RE_S 5 -/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_TX_CHECK_SUM_RE (BIT(4)) -#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) -#define UHCI_TX_CHECK_SUM_RE_V 0x1 -#define UHCI_TX_CHECK_SUM_RE_S 4 -/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SAVE_HEAD (BIT(3)) -#define UHCI_SAVE_HEAD_M (BIT(3)) -#define UHCI_SAVE_HEAD_V 0x1 -#define UHCI_SAVE_HEAD_S 3 -/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_CRC_DISABLE (BIT(2)) -#define UHCI_CRC_DISABLE_M (BIT(2)) -#define UHCI_CRC_DISABLE_V 0x1 -#define UHCI_CRC_DISABLE_S 2 -/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_CHECK_SEQ_EN (BIT(1)) -#define UHCI_CHECK_SEQ_EN_M (BIT(1)) -#define UHCI_CHECK_SEQ_EN_V 0x1 -#define UHCI_CHECK_SEQ_EN_S 1 -/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_CHECK_SUM_EN (BIT(0)) -#define UHCI_CHECK_SUM_EN_M (BIT(0)) -#define UHCI_CHECK_SUM_EN_V 0x1 -#define UHCI_CHECK_SUM_EN_S 0 - -#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18) -/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: a*/ -#define UHCI_DECODE_STATE 0x00000007 -#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S)) -#define UHCI_DECODE_STATE_V 0x7 -#define UHCI_DECODE_STATE_S 3 -/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: a*/ -#define UHCI_RX_ERR_CAUSE 0x00000007 -#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S)) -#define UHCI_RX_ERR_CAUSE_V 0x7 -#define UHCI_RX_ERR_CAUSE_S 0 - -#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1C) -/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: a*/ -#define UHCI_ENCODE_STATE 0x00000007 -#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S)) -#define UHCI_ENCODE_STATE_V 0x7 -#define UHCI_ENCODE_STATE_S 0 - -#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20) -/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_13_ESC_EN (BIT(7)) -#define UHCI_RX_13_ESC_EN_M (BIT(7)) -#define UHCI_RX_13_ESC_EN_V 0x1 -#define UHCI_RX_13_ESC_EN_S 7 -/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_RX_11_ESC_EN (BIT(6)) -#define UHCI_RX_11_ESC_EN_M (BIT(6)) -#define UHCI_RX_11_ESC_EN_V 0x1 -#define UHCI_RX_11_ESC_EN_S 6 -/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_RX_DB_ESC_EN (BIT(5)) -#define UHCI_RX_DB_ESC_EN_M (BIT(5)) -#define UHCI_RX_DB_ESC_EN_V 0x1 -#define UHCI_RX_DB_ESC_EN_S 5 -/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_RX_C0_ESC_EN (BIT(4)) -#define UHCI_RX_C0_ESC_EN_M (BIT(4)) -#define UHCI_RX_C0_ESC_EN_V 0x1 -#define UHCI_RX_C0_ESC_EN_S 4 -/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_13_ESC_EN (BIT(3)) -#define UHCI_TX_13_ESC_EN_M (BIT(3)) -#define UHCI_TX_13_ESC_EN_V 0x1 -#define UHCI_TX_13_ESC_EN_S 3 -/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_TX_11_ESC_EN (BIT(2)) -#define UHCI_TX_11_ESC_EN_M (BIT(2)) -#define UHCI_TX_11_ESC_EN_V 0x1 -#define UHCI_TX_11_ESC_EN_S 2 -/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_TX_DB_ESC_EN (BIT(1)) -#define UHCI_TX_DB_ESC_EN_M (BIT(1)) -#define UHCI_TX_DB_ESC_EN_V 0x1 -#define UHCI_TX_DB_ESC_EN_S 1 -/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_TX_C0_ESC_EN (BIT(0)) -#define UHCI_TX_C0_ESC_EN_M (BIT(0)) -#define UHCI_TX_C0_ESC_EN_V 0x1 -#define UHCI_TX_C0_ESC_EN_S 0 - -#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) -/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) -#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) -#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 -#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 -/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: a*/ -#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 -#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S)) -#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 -#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 -/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ -/*description: a*/ -#define UHCI_RXFIFO_TIMEOUT 0x000000FF -#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S)) -#define UHCI_RXFIFO_TIMEOUT_V 0xFF -#define UHCI_RXFIFO_TIMEOUT_S 12 -/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) -#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) -#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 -#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 -/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: a*/ -#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 -#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S)) -#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 -#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 -/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ -/*description: a*/ -#define UHCI_TXFIFO_TIMEOUT 0x000000FF -#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S)) -#define UHCI_TXFIFO_TIMEOUT_V 0xFF -#define UHCI_TXFIFO_TIMEOUT_S 0 - -#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28) -/* UHCI_ACK_NUM_LOAD : WT ;bitpos:[3] ;default: 1'b1 ; */ -/*description: a*/ -#define UHCI_ACK_NUM_LOAD (BIT(3)) -#define UHCI_ACK_NUM_LOAD_M (BIT(3)) -#define UHCI_ACK_NUM_LOAD_V 0x1 -#define UHCI_ACK_NUM_LOAD_S 3 -/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: */ -#define UHCI_ACK_NUM 0x00000007 -#define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S)) -#define UHCI_ACK_NUM_V 0x7 -#define UHCI_ACK_NUM_S 0 - -#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2C) -/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_RX_HEAD 0xFFFFFFFF -#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S)) -#define UHCI_RX_HEAD_V 0xFFFFFFFF -#define UHCI_RX_HEAD_S 0 - -#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30) -/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_ALWAYS_SEND_EN (BIT(7)) -#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) -#define UHCI_ALWAYS_SEND_EN_V 0x1 -#define UHCI_ALWAYS_SEND_EN_S 7 -/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ -/*description: a*/ -#define UHCI_ALWAYS_SEND_NUM 0x00000007 -#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S)) -#define UHCI_ALWAYS_SEND_NUM_V 0x7 -#define UHCI_ALWAYS_SEND_NUM_S 4 -/* UHCI_SINGLE_SEND_EN : R/W/SC ;bitpos:[3] ;default: 1'b0 ; */ -/*description: a*/ -#define UHCI_SINGLE_SEND_EN (BIT(3)) -#define UHCI_SINGLE_SEND_EN_M (BIT(3)) -#define UHCI_SINGLE_SEND_EN_V 0x1 -#define UHCI_SINGLE_SEND_EN_S 3 -/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: a*/ -#define UHCI_SINGLE_SEND_NUM 0x00000007 -#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S)) -#define UHCI_SINGLE_SEND_NUM_V 0x7 -#define UHCI_SINGLE_SEND_NUM_S 0 - -#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34) -/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S)) -#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD0_S 0 - -#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38) -/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S)) -#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q0_WORD1_S 0 - -#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3C) -/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S)) -#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD0_S 0 - -#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40) -/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S)) -#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q1_WORD1_S 0 - -#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44) -/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S)) -#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD0_S 0 - -#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48) -/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S)) -#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q2_WORD1_S 0 - -#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4C) -/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S)) -#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD0_S 0 - -#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50) -/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S)) -#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q3_WORD1_S 0 - -#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54) -/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S)) -#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD0_S 0 - -#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58) -/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S)) -#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q4_WORD1_S 0 - -#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5C) -/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S)) -#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD0_S 0 - -#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60) -/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S)) -#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q5_WORD1_S 0 - -#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64) -/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S)) -#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD0_S 0 - -#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68) -/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: a*/ -#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S)) -#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF -#define UHCI_SEND_Q6_WORD1_S 0 - -#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6C) -/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ -/*description: a*/ -#define UHCI_SEPER_ESC_CHAR1 0x000000FF -#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S)) -#define UHCI_SEPER_ESC_CHAR1_V 0xFF -#define UHCI_SEPER_ESC_CHAR1_S 16 -/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: a*/ -#define UHCI_SEPER_ESC_CHAR0 0x000000FF -#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S)) -#define UHCI_SEPER_ESC_CHAR0_V 0xFF -#define UHCI_SEPER_ESC_CHAR0_S 8 -/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ -/*description: a*/ -#define UHCI_SEPER_CHAR 0x000000FF -#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S)) -#define UHCI_SEPER_CHAR_V 0xFF -#define UHCI_SEPER_CHAR_S 0 - -#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70) -/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ -/*description: a*/ -#define UHCI_ESC_SEQ0_CHAR1 0x000000FF -#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S)) -#define UHCI_ESC_SEQ0_CHAR1_V 0xFF -#define UHCI_ESC_SEQ0_CHAR1_S 16 -/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: a*/ -#define UHCI_ESC_SEQ0_CHAR0 0x000000FF -#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S)) -#define UHCI_ESC_SEQ0_CHAR0_V 0xFF -#define UHCI_ESC_SEQ0_CHAR0_S 8 -/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ -/*description: a*/ -#define UHCI_ESC_SEQ0 0x000000FF -#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S)) -#define UHCI_ESC_SEQ0_V 0xFF -#define UHCI_ESC_SEQ0_S 0 - -#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74) -/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ -/*description: a*/ -#define UHCI_ESC_SEQ1_CHAR1 0x000000FF -#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S)) -#define UHCI_ESC_SEQ1_CHAR1_V 0xFF -#define UHCI_ESC_SEQ1_CHAR1_S 16 -/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: a*/ -#define UHCI_ESC_SEQ1_CHAR0 0x000000FF -#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S)) -#define UHCI_ESC_SEQ1_CHAR0_V 0xFF -#define UHCI_ESC_SEQ1_CHAR0_S 8 -/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ -/*description: a*/ -#define UHCI_ESC_SEQ1 0x000000FF -#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S)) -#define UHCI_ESC_SEQ1_V 0xFF -#define UHCI_ESC_SEQ1_S 0 - -#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78) -/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ -/*description: a*/ -#define UHCI_ESC_SEQ2_CHAR1 0x000000FF -#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S)) -#define UHCI_ESC_SEQ2_CHAR1_V 0xFF -#define UHCI_ESC_SEQ2_CHAR1_S 16 -/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ -/*description: a*/ -#define UHCI_ESC_SEQ2_CHAR0 0x000000FF -#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S)) -#define UHCI_ESC_SEQ2_CHAR0_V 0xFF -#define UHCI_ESC_SEQ2_CHAR0_S 8 -/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ -/*description: a*/ -#define UHCI_ESC_SEQ2 0x000000FF -#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S)) -#define UHCI_ESC_SEQ2_V 0xFF -#define UHCI_ESC_SEQ2_S 0 - -#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7C) -/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ -/*description: a*/ -#define UHCI_PKT_THRS 0x00001FFF -#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S)) -#define UHCI_PKT_THRS_V 0x1FFF -#define UHCI_PKT_THRS_S 0 - -#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80) -/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007170 ; */ -/*description: a*/ -#define UHCI_DATE 0xFFFFFFFF -#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S)) -#define UHCI_DATE_V 0xFFFFFFFF -#define UHCI_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_UHCI_REG_H_ */ diff --git a/components/soc/esp32h4/include/soc/uhci_struct.h b/components/soc/esp32h4/include/soc/uhci_struct.h deleted file mode 100644 index ee020cb702..0000000000 --- a/components/soc/esp32h4/include/soc/uhci_struct.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _SOC_UHCI_STRUCT_H_ -#define _SOC_UHCI_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct uhci_dev_s { - union { - struct { - uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/ - uint32_t rx_rst: 1; /*Write 1 then write 0 to this bit to reset encode state machine.*/ - uint32_t uart0_ce: 1; /*Set this bit to link up HCI and UART0.*/ - uint32_t uart1_ce: 1; /*Set this bit to link up HCI and UART1.*/ - uint32_t reserved4: 1; - uint32_t seper_en: 1; /*Set this bit to separate the data frame using a special char.*/ - uint32_t head_en: 1; /*Set this bit to encode the data packet with a formatting header.*/ - uint32_t crc_rec_en: 1; /*Set this bit to enable UHCI to receive the 16 bit CRC.*/ - uint32_t uart_idle_eof_en: 1; /*If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.*/ - uint32_t len_eof_en: 1; /*If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/ - uint32_t encode_crc_en: 1; /*Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.*/ - uint32_t clk_en: 1; /*1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.*/ - uint32_t uart_rx_brk_eof_en: 1; /*If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.*/ - uint32_t reserved13: 19; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t rx_start: 1; /*a*/ - uint32_t tx_start: 1; /*a*/ - uint32_t rx_hung: 1; /*a*/ - uint32_t tx_hung: 1; /*a*/ - uint32_t send_s_q: 1; /*a*/ - uint32_t send_a_q: 1; /*a*/ - uint32_t outlink_eof_err: 1; /*This is the interrupt raw bit. Triggered when there are some errors in EOF in the*/ - uint32_t app_ctrl0: 1; /*Soft control int raw bit.*/ - uint32_t app_ctrl1: 1; /*Soft control int raw bit.*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t rx_start: 1; /*a*/ - uint32_t tx_start: 1; /*a*/ - uint32_t rx_hung: 1; /*a*/ - uint32_t tx_hung: 1; /*a*/ - uint32_t send_s_q: 1; /*a*/ - uint32_t send_a_q: 1; /*a*/ - uint32_t outlink_eof_err: 1; /*a*/ - uint32_t app_ctrl0: 1; /*a*/ - uint32_t app_ctrl1: 1; /*a*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t rx_start: 1; /*a*/ - uint32_t tx_start: 1; /*a*/ - uint32_t rx_hung: 1; /*a*/ - uint32_t tx_hung: 1; /*a*/ - uint32_t send_s_q: 1; /*a*/ - uint32_t send_a_q: 1; /*a*/ - uint32_t outlink_eof_err: 1; /*a*/ - uint32_t app_ctrl0: 1; /*a*/ - uint32_t app_ctrl1: 1; /*a*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t rx_start: 1; /*a*/ - uint32_t tx_start: 1; /*a*/ - uint32_t rx_hung: 1; /*a*/ - uint32_t tx_hung: 1; /*a*/ - uint32_t send_s_q: 1; /*a*/ - uint32_t send_a_q: 1; /*a*/ - uint32_t outlink_eof_err: 1; /*a*/ - uint32_t app_ctrl0: 1; /*a*/ - uint32_t app_ctrl1: 1; /*a*/ - uint32_t reserved9: 23; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t check_sum_en: 1; /*a*/ - uint32_t check_seq_en: 1; /*a*/ - uint32_t crc_disable: 1; /*a*/ - uint32_t save_head: 1; /*a*/ - uint32_t tx_check_sum_re: 1; /*a*/ - uint32_t tx_ack_num_re: 1; /*a*/ - uint32_t reserved6: 1; - uint32_t wait_sw_start: 1; /*a*/ - uint32_t sw_start: 1; /*a*/ - uint32_t reserved9: 12; - uint32_t reserved21: 11; - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t rx_err_cause: 3; /*a*/ - uint32_t decode_state: 3; /*a*/ - uint32_t reserved6: 26; - }; - uint32_t val; - } state0; - union { - struct { - uint32_t encode_state: 3; /*a*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } state1; - union { - struct { - uint32_t tx_c0_esc_en: 1; /*a*/ - uint32_t tx_db_esc_en: 1; /*a*/ - uint32_t tx_11_esc_en: 1; /*a*/ - uint32_t tx_13_esc_en: 1; /*a*/ - uint32_t rx_c0_esc_en: 1; /*a*/ - uint32_t rx_db_esc_en: 1; /*a*/ - uint32_t rx_11_esc_en: 1; /*a*/ - uint32_t rx_13_esc_en: 1; /*a*/ - uint32_t reserved8: 24; - }; - uint32_t val; - } escape_conf; - union { - struct { - uint32_t txfifo_timeout: 8; /*a*/ - uint32_t txfifo_timeout_shift: 3; /*a*/ - uint32_t txfifo_timeout_ena: 1; /*a*/ - uint32_t rxfifo_timeout: 8; /*a*/ - uint32_t rxfifo_timeout_shift: 3; /*a*/ - uint32_t rxfifo_timeout_ena: 1; /*a*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } hung_conf; - union { - struct { - uint32_t ack_num: 3; - uint32_t ack_num_load: 1; /*a*/ - uint32_t reserved4: 28; - }; - uint32_t val; - } ack_num; - uint32_t rx_head; /*a*/ - union { - struct { - uint32_t single_send_num: 3; /*a*/ - uint32_t single_send_en: 1; /*a*/ - uint32_t always_send_num: 3; /*a*/ - uint32_t always_send_en: 1; /*a*/ - uint32_t reserved8: 24; - }; - uint32_t val; - } quick_sent; - struct { - uint32_t w_data[2]; /*a*/ - } q_data[7]; - union { - struct { - uint32_t seper_char: 8; /*a*/ - uint32_t seper_esc_char0: 8; /*a*/ - uint32_t seper_esc_char1: 8; /*a*/ - uint32_t reserved24: 8; /*a*/ - }; - uint32_t val; - } esc_conf0; - union { - struct { - uint32_t seq0: 8; /*a*/ - uint32_t seq0_char0: 8; /*a*/ - uint32_t seq0_char1: 8; /*a*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } esc_conf1; - union { - struct { - uint32_t seq1: 8; /*a*/ - uint32_t seq1_char0: 8; /*a*/ - uint32_t seq1_char1: 8; /*a*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } esc_conf2; - union { - struct { - uint32_t seq2: 8; /*a*/ - uint32_t seq2_char0: 8; /*a*/ - uint32_t seq2_char1: 8; /*a*/ - uint32_t reserved24: 8; - }; - uint32_t val; - } esc_conf3; - union { - struct { - uint32_t thrs: 13; /*a*/ - uint32_t reserved13:19; - }; - uint32_t val; - } pkt_thres; - uint32_t date; /*a*/ -} uhci_dev_t; -extern uhci_dev_t UHCI0; -extern uhci_dev_t UHCI1; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_UHCI_STRUCT_H_ */ diff --git a/components/soc/esp32h4/include/soc/wdev_reg.h b/components/soc/esp32h4/include/soc/wdev_reg.h deleted file mode 100644 index 755fd25f74..0000000000 --- a/components/soc/esp32h4/include/soc/wdev_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include "soc.h" - -/* Hardware random number generator register */ -#define WDEV_RND_REG 0x600260b0 diff --git a/components/soc/esp32h4/interrupts.c b/components/soc/esp32h4/interrupts.c deleted file mode 100644 index a0c5ab020e..0000000000 --- a/components/soc/esp32h4/interrupts.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/interrupts.h" - -const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { - [0] = "WIFI_MAC", - [1] = "WIFI_NMI", - [2] = "WIFI_PWR", - [3] = "WIFI_BB", - [4] = "BT_MAC", - [5] = "BT_BB", - [6] = "BT_BB_NMI", - [7] = "RWBT", - [8] = "RWBLE", - [9] = "RWBT_NMI", - [10] = "RWBLE_NMI", - [11] = "I2C", - [12] = "SLC0", - [13] = "SLC1", - [14] = "APB_CTRL", - [15] = "UHCI0", - [16] = "GPIO", - [17] = "GPIO_NMI", - [18] = "SPI1", - [19] = "SPI2", - [20] = "I2S1", - [21] = "UART0", - [22] = "UART1", - [23] = "LEDC", - [24] = "EFUSE", - [25] = "TWAI", - [26] = "USB", - [27] = "RTC_CORE", - [28] = "RMT", - [29] = "I2C_EXT0", - [30] = "TIMER1", - [31] = "TIMER2", - [32] = "TG0_T0_LEVEL", - [33] = "TG0_WDT_LEVEL", - [34] = "TG1_T0_LEVEL", - [35] = "TG1_WDT_LEVEL", - [36] = "CACHE_IA", - [37] = "SYSTIMER_TARGET0_EDGE", - [38] = "SYSTIMER_TARGET1_EDGE", - [39] = "SYSTIMER_TARGET2_EDGE", - [40] = "SPI_MEM_REJECT_CACHE", - [41] = "ICACHE_PRELOAD0", - [42] = "ICACHE_SYNC0", - [43] = "APB_ADC", - [44] = "DMA_CH0", - [45] = "DMA_CH1", - [46] = "DMA_CH2", - [47] = "RSA", - [48] = "AES", - [49] = "SHA", - [50] = "ETS_FROM_CPU_INTR0", - [51] = "ETS_FROM_CPU_INTR1", - [52] = "ETS_FROM_CPU_INTR2", - [53] = "ETS_FROM_CPU_INTR3", - [54] = "ETS_ASSIST_DEBUG", - [55] = "ETS_DMA_APBPERI_PMS", - [56] = "ETS_CORE0_IRAM0_PMS", - [57] = "ETS_CORE0_DRAM0_PMS", - [58] = "ETS_CORE0_PIF_PMS", - [59] = "ETS_CORE0_PIF_PMS_SIZE", - [60] = "ETS_BAK_PMS_VIOLATE", - [61] = "ETS_CACHE_CORE0_ACS", -}; diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld deleted file mode 100644 index 73c2a1175e..0000000000 --- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld +++ /dev/null @@ -1,37 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -PROVIDE ( UART0 = 0x60000000 ); -PROVIDE ( UART1 = 0x60010000 ); -PROVIDE ( SPIMEM1 = 0x60002000 ); -PROVIDE ( SPIMEM0 = 0x60003000 ); -PROVIDE ( GPIO = 0x60004000 ); -PROVIDE ( SDM = 0x60004f00 ); -PROVIDE ( RTCCNTL = 0x60008000 ); -PROVIDE ( RTCIO = 0x60008400 ); -PROVIDE ( HINF = 0x6000B000 ); -PROVIDE ( I2S0 = 0x6002d000 ); -PROVIDE ( I2C0 = 0x60013000 ); -PROVIDE ( UHCI0 = 0x60014000 ); -PROVIDE ( UHCI1 = 0x6000c000 ); -PROVIDE ( HOST = 0x60015000 ); -PROVIDE ( RMT = 0x60016000 ); -PROVIDE ( RMTMEM = 0x60016400 ); -PROVIDE ( PCNT = 0x60017000 ); -PROVIDE ( SLC = 0x60018000 ); -PROVIDE ( LEDC = 0x60019000 ); -PROVIDE ( EFUSE = 0x6001A000 ); -PROVIDE ( TIMERG0 = 0x6001F000 ); -PROVIDE ( TIMERG1 = 0x60020000 ); -PROVIDE ( SYSTIMER = 0x60023000 ); -PROVIDE ( GPSPI2 = 0x60024000 ); -PROVIDE ( GPSPI3 = 0x60025000 ); -PROVIDE ( SYSCON = 0x60026000 ); -PROVIDE ( TWAI = 0x6002B000 ); -PROVIDE ( GPSPI4 = 0x60037000 ); -PROVIDE ( APB_SARADC = 0x60040000 ); -PROVIDE ( USB_SERIAL_JTAG = 0x60043000 ); -PROVIDE ( GDMA = 0x6003F000 ); -PROVIDE ( IEEE802154 = 0x60047000 ); diff --git a/components/soc/esp32h4/ledc_periph.c b/components/soc/esp32h4/ledc_periph.c deleted file mode 100644 index a401e1f80a..0000000000 --- a/components/soc/esp32h4/ledc_periph.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/ledc_periph.h" -#include "soc/gpio_sig_map.h" - -/* - Bunch of constants for every LEDC peripheral: GPIO signals -*/ -const ledc_signal_conn_t ledc_periph_signal[1] = { - { - .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, - } -}; diff --git a/components/soc/esp32h4/rmt_periph.c b/components/soc/esp32h4/rmt_periph.c deleted file mode 100644 index 0369d0f200..0000000000 --- a/components/soc/esp32h4/rmt_periph.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/rmt_periph.h" -#include "soc/gpio_sig_map.h" - -const rmt_signal_conn_t rmt_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { - [0] = { - .tx_sig = RMT_SIG_OUT0_IDX, - .rx_sig = -1 - }, - [1] = { - .tx_sig = RMT_SIG_OUT1_IDX, - .rx_sig = -1 - }, - [2] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN0_IDX - }, - [3] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN1_IDX - }, - } - } - } -}; diff --git a/components/soc/esp32h4/sdm_periph.c b/components/soc/esp32h4/sdm_periph.c deleted file mode 100644 index f52b1758a8..0000000000 --- a/components/soc/esp32h4/sdm_periph.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/sdm_periph.h" -#include "soc/gpio_sig_map.h" - -const sigma_delta_signal_conn_t sigma_delta_periph_signals = { - .channels = { - [0] = { - GPIO_SD0_OUT_IDX - }, - [1] = { - GPIO_SD1_OUT_IDX - }, - [2] = { - GPIO_SD2_OUT_IDX - }, - [3] = { - GPIO_SD3_OUT_IDX - } - } -}; diff --git a/components/soc/esp32h4/spi_periph.c b/components/soc/esp32h4/spi_periph.c deleted file mode 100644 index ce1c5c9af9..0000000000 --- a/components/soc/esp32h4/spi_periph.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/spi_periph.h" -#include "stddef.h" - -/* - Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc -*/ -const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { - { - .spiclk_out = SPICLK_OUT_MUX_IDX, - .spiclk_in = 0,/* SPI clock is not an input signal*/ - .spid_out = SPID_OUT_IDX, - .spiq_out = SPIQ_OUT_IDX, - .spiwp_out = SPIWP_OUT_IDX, - .spihd_out = SPIHD_OUT_IDX, - .spid_in = SPID_IN_IDX, - .spiq_in = SPIQ_IN_IDX, - .spiwp_in = SPIWP_IN_IDX, - .spihd_in = SPIHD_IN_IDX, - .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ - .spics_in = 0,/* SPI cs is not an input signal*/ - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, - .irq = ETS_SPI1_INTR_SOURCE, - .irq_dma = -1, - .module = PERIPH_SPI_MODULE, - .hw = (spi_dev_t *) &SPIMEM1, - .func = SPI_FUNC_NUM, - }, { - .spiclk_out = FSPICLK_OUT_IDX, - .spiclk_in = FSPICLK_IN_IDX, - .spid_out = FSPID_OUT_IDX, - .spiq_out = FSPIQ_OUT_IDX, - .spiwp_out = FSPIWP_OUT_IDX, - .spihd_out = FSPIHD_OUT_IDX, - .spid_in = FSPID_IN_IDX, - .spiq_in = FSPIQ_IN_IDX, - .spiwp_in = FSPIWP_IN_IDX, - .spihd_in = FSPIHD_IN_IDX, - .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX}, - .spics_in = FSPICS0_IN_IDX, - .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS, - .irq = ETS_SPI2_INTR_SOURCE, - .irq_dma = -1, - .module = PERIPH_SPI2_MODULE, - .hw = &GPSPI2, - .func = SPI2_FUNC_NUM, - } -}; diff --git a/components/soc/esp32h4/temperature_sensor_periph.c b/components/soc/esp32h4/temperature_sensor_periph.c deleted file mode 100644 index e75c60b317..0000000000 --- a/components/soc/esp32h4/temperature_sensor_periph.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/temperature_sensor_periph.h" - -const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = { - /*Offset reg_val min max error */ - {-2, 5, 50, 125, 3}, - {-1, 7, 20, 100, 2}, - { 0, 15, -10, 80, 1}, - { 1, 11, -30, 50, 2}, - { 2, 10, -40, 20, 3}, -}; diff --git a/components/soc/esp32h4/timer_periph.c b/components/soc/esp32h4/timer_periph.c deleted file mode 100644 index e2be270b18..0000000000 --- a/components/soc/esp32h4/timer_periph.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/timer_periph.h" - -const timer_group_signal_conn_t timer_group_periph_signals = { - .groups = { - [0] = { - .module = PERIPH_TIMG0_MODULE, - .timer_irq_id = { - [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE, - } - }, - [1] = { - .module = PERIPH_TIMG1_MODULE, - .timer_irq_id = { - [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE, - } - } - } -}; diff --git a/components/soc/esp32h4/uart_periph.c b/components/soc/esp32h4/uart_periph.c deleted file mode 100644 index a23ff14937..0000000000 --- a/components/soc/esp32h4/uart_periph.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "soc/uart_periph.h" - -/* - Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc -*/ -const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { - { - .pins = { - [SOC_UART_TX_PIN_IDX] = { - .default_gpio = U0TXD_GPIO_NUM, - .iomux_func = U0TXD_MUX_FUNC, - .input = 0, - .signal = U0TXD_OUT_IDX, - }, - - [SOC_UART_RX_PIN_IDX] = { - .default_gpio = U0RXD_GPIO_NUM, - .iomux_func = U0RXD_MUX_FUNC, - .input = 1, - .signal = U0RXD_IN_IDX, - }, - - [SOC_UART_RTS_PIN_IDX] = { - .default_gpio = U0RTS_GPIO_NUM, - .iomux_func = U0RTS_MUX_FUNC, - .input = 0, - .signal = U0RTS_OUT_IDX, - }, - - [SOC_UART_CTS_PIN_IDX] = { - .default_gpio = U0CTS_GPIO_NUM, - .iomux_func = U0CTS_MUX_FUNC, - .input = 1, - .signal = U0CTS_IN_IDX, - } - }, - .irq = ETS_UART0_INTR_SOURCE, - .module = PERIPH_UART0_MODULE, - }, - - { - .pins = { - [SOC_UART_TX_PIN_IDX] = { - .default_gpio = U1TXD_GPIO_NUM, - .iomux_func = U1TXD_MUX_FUNC, - .input = 0, - .signal = U1TXD_OUT_IDX, - }, - - [SOC_UART_RX_PIN_IDX] = { - .default_gpio = U1RXD_GPIO_NUM, - .iomux_func = U1RXD_MUX_FUNC, - .input = 1, - .signal = U1RXD_IN_IDX, - }, - - [SOC_UART_RTS_PIN_IDX] = { - .default_gpio = U1RTS_GPIO_NUM, - .iomux_func = U1RTS_MUX_FUNC, - .input = 0, - .signal = U1RTS_OUT_IDX, - }, - - [SOC_UART_CTS_PIN_IDX] = { - .default_gpio = U1CTS_GPIO_NUM, - .iomux_func = U1CTS_MUX_FUNC, - .input = 1, - .signal = U1CTS_IN_IDX, - }, - }, - .irq = ETS_UART1_INTR_SOURCE, - .module = PERIPH_UART1_MODULE, - }, -}; diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index 8079bd4630..f91817d69b 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -27,10 +27,6 @@ #include "esp32c3/rom/cache.h" #include "soc/extmem_reg.h" #include "soc/ext_mem_defs.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/cache.h" -#include "soc/extmem_reg.h" -#include "soc/ext_mem_defs.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" #include "soc/extmem_reg.h" @@ -390,7 +386,7 @@ void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state) icache_state = Cache_Suspend_ICache() << 16; dcache_state = Cache_Suspend_DCache(); *saved_state = icache_state | dcache_state; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 uint32_t icache_state; icache_state = Cache_Suspend_ICache() << 16; *saved_state = icache_state; @@ -421,7 +417,7 @@ void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state) #elif CONFIG_IDF_TARGET_ESP32S3 Cache_Resume_DCache(saved_state & 0xffff); Cache_Resume_ICache(saved_state >> 16); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 Cache_Resume_ICache(saved_state >> 16); #elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 Cache_Resume_ICache(saved_state); @@ -438,7 +434,7 @@ IRAM_ATTR bool spi_flash_cache_enabled(void) #endif #elif CONFIG_IDF_TARGET_ESP32S2 bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); -#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0); #elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 bool result = s_cache_enabled; @@ -555,7 +551,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable int i; bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true; uint32_t drom0_in_icache = 1;//always 1 in esp32s2 -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 drom0_in_icache = 0; #endif @@ -942,7 +938,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable } #endif -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache) { @@ -983,7 +979,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable) } return ESP_OK; } -#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid) { diff --git a/components/spi_flash/esp32h4/Kconfig.soc_caps.in b/components/spi_flash/esp32h4/Kconfig.soc_caps.in deleted file mode 100644 index d1744a6196..0000000000 --- a/components/spi_flash/esp32h4/Kconfig.soc_caps.in +++ /dev/null @@ -1,32 +0,0 @@ -##################################################### -# This file is auto-generated from SoC caps -# using gen_soc_caps_kconfig.py, do not edit manually -##################################################### - -config SPI_FLASH_VENDOR_XMC_SUPPORTED - bool - default y - -config SPI_FLASH_VENDOR_GD_SUPPORTED - bool - default y - -config SPI_FLASH_VENDOR_ISSI_SUPPORTED - bool - default y - -config SPI_FLASH_VENDOR_MXIC_SUPPORTED - bool - default y - -config SPI_FLASH_VENDOR_WINBOND_SUPPORTED - bool - default y - -config SPI_FLASH_VENDOR_BOYA_SUPPORTED - bool - default y - -config SPI_FLASH_VENDOR_TH_SUPPORTED - bool - default y diff --git a/components/spi_flash/esp32h4/flash_vendor_caps.h b/components/spi_flash/esp32h4/flash_vendor_caps.h deleted file mode 100644 index 88b64fdba4..0000000000 --- a/components/spi_flash/esp32h4/flash_vendor_caps.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_GD_SUPPORTED (1) -#define SPI_FLASH_VENDOR_ISSI_SUPPORTED (1) -#define SPI_FLASH_VENDOR_MXIC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_WINBOND_SUPPORTED (1) -#define SPI_FLASH_VENDOR_BOYA_SUPPORTED (1) -#define SPI_FLASH_VENDOR_TH_SUPPORTED (1) diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index a8a6d8ab70..eb56116fef 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -137,26 +137,6 @@ esp_flash_t *esp_flash_default_chip = NULL; .cs_setup = 1,\ } #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/efuse.h" -#if !CONFIG_SPI_FLASH_AUTO_SUSPEND -#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ - .host_id = SPI1_HOST,\ - .freq_mhz = DEFAULT_FLASH_SPEED, \ - .cs_num = 0, \ - .iomux = true, \ - .input_delay_ns = 0,\ -} -#else -#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ - .host_id = SPI1_HOST,\ - .freq_mhz = DEFAULT_FLASH_SPEED, \ - .cs_num = 0, \ - .iomux = true, \ - .input_delay_ns = 0,\ - .auto_sus_en = true,\ -} -#endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND #endif static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux, int cs_id) diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index fa6c945936..c65547d18a 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -37,8 +37,6 @@ #include "esp32s3/opi_flash_private.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index a6d0de8e07..b912460c42 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -20,9 +20,6 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" -#include "esp32h4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" #include "esp32c2/rom/cache.h" @@ -43,7 +40,7 @@ typedef struct { } spi_noos_arg_t; static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 typedef struct { uint32_t icache_autoload; } spi_noos_arg_t; @@ -60,7 +57,7 @@ static IRAM_ATTR esp_err_t start(void *arg) spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); spi_arg->dcache_autoload = Cache_Suspend_DCache(); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 spi_noos_arg_t *spi_arg = arg; spi_arg->icache_autoload = Cache_Suspend_ICache(); #endif @@ -77,7 +74,7 @@ static IRAM_ATTR esp_err_t end(void *arg) Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); Cache_Resume_DCache(spi_arg->dcache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 spi_noos_arg_t *spi_arg = arg; Cache_Invalidate_ICache_All(); Cache_Resume_ICache(spi_arg->icache_autoload); diff --git a/components/spi_flash/test/test_cache_disabled.c b/components/spi_flash/test/test_cache_disabled.c index 5ca6f3c2b3..78a1f439a8 100644 --- a/components/spi_flash/test/test_cache_disabled.c +++ b/components/spi_flash/test/test_cache_disabled.c @@ -85,7 +85,7 @@ static void IRAM_ATTR cache_access_test_func(void* arg) #if CONFIG_IDF_TARGET_ESP32 #define CACHE_ERROR_REASON "Cache disabled,SW_RESET" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST" #elif CONFIG_IDF_TARGET_ESP32S3 #define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST" diff --git a/components/spi_flash/test/test_esp_flash.c b/components/spi_flash/test/test_esp_flash.c index f29c276f4d..764b4f42e0 100644 --- a/components/spi_flash/test/test_esp_flash.c +++ b/components/spi_flash/test/test_esp_flash.c @@ -32,8 +32,6 @@ #include "esp32s3/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" #endif diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c index a104830c50..814c9a5d72 100644 --- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c +++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c @@ -38,8 +38,6 @@ #include "esp32s3/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/wpa_supplicant/src/utils/includes.h b/components/wpa_supplicant/src/utils/includes.h index 8ca7fe32c2..368a0fe0ce 100644 --- a/components/wpa_supplicant/src/utils/includes.h +++ b/components/wpa_supplicant/src/utils/includes.h @@ -69,8 +69,6 @@ #include "esp32c3/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/ets_sys.h" -#elif CONFIG_IDF_TARGET_ESP32H4 -#include "esp32h4/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/ets_sys.h" #elif CONFIG_IDF_TARGET_ESP32H2 diff --git a/conftest.py b/conftest.py index 2a37a8b3d5..baad264ce3 100644 --- a/conftest.py +++ b/conftest.py @@ -50,7 +50,7 @@ except ImportError: import common_test_methods # noqa: F401 SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2'] -PREVIEW_TARGETS = ['esp32h4'] # this PREVIEW_TARGETS excludes 'linux' target +PREVIEW_TARGETS: List[str] = [] # this PREVIEW_TARGETS excludes 'linux' target DEFAULT_SDKCONFIG = 'default' TARGET_MARKERS = { @@ -60,14 +60,13 @@ TARGET_MARKERS = { 'esp32c3': 'support esp32c3 target', 'esp32c2': 'support esp32c2 target', 'esp32c6': 'support esp32c6 target', - 'esp32h4': 'support esp32h4 target', 'esp32h2': 'support esp32h2 target', 'linux': 'support linux target', } SPECIAL_MARKERS = { 'supported_targets': "support all officially announced supported targets ('esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6')", - 'preview_targets': "support all preview targets ('esp32h4')", + 'preview_targets': "support all preview targets ('none')", 'all_targets': 'support all targets, including supported ones and preview ones', 'temp_skip_ci': 'temp skip tests for specified targets only in ci', 'temp_skip': 'temp skip tests for specified targets both in ci and locally', diff --git a/docs/doxygen/Doxyfile_esp32h4 b/docs/doxygen/Doxyfile_esp32h4 deleted file mode 100644 index 910f295a01..0000000000 --- a/docs/doxygen/Doxyfile_esp32h4 +++ /dev/null @@ -1 +0,0 @@ -INPUT += \ diff --git a/docs/en/api-guides/openthread.rst b/docs/en/api-guides/openthread.rst index 85c35c8dc3..ceb12fc463 100644 --- a/docs/en/api-guides/openthread.rst +++ b/docs/en/api-guides/openthread.rst @@ -11,12 +11,12 @@ OpenThread can run under the following modes on Espressif chips: Standalone node +++++++++++++++ -The full OpenThread stack and the application layer runs on the same chip. This mode is available on chips with 15.4 radio such as ESP32-H4. +The full OpenThread stack and the application layer runs on the same chip. This mode is available on chips with 15.4 radio such as {IDF_TARGET}. Radio Co-Processor (RCP) ++++++++++++++++++++++++ -The chip will be connected to another host running the OpenThread IP stack. It will send and received 15.4 packets on behalf of the host. This mode is available on chips with 15.4 radio such as ESP32-H4. The underlying transport between the chip and the host can be SPI or UART. For sake of latency, we recommend to use SPI as the underlying transport. +The chip will be connected to another host running the OpenThread IP stack. It will send and received 15.4 packets on behalf of the host. This mode is available on chips with 15.4 radio such as {IDF_TARGET}. The underlying transport between the chip and the host can be SPI or UART. For sake of latency, we recommend to use SPI as the underlying transport. OpenThread host +++++++++++++++ @@ -38,8 +38,8 @@ For chips without 15.4 radio, it can be connected to an RCP and run OpenThread u # node labels HOST_NODE [label="OpenThread \nhost\n(ESP32)", fontsize=14]; - RCP [label="Radio \nCo-Processor\n(ESP32-H4)", fontsize=14]; - STANDALONE [label="Standalone \nnode\n (ESP32-H4)", fontsize=14]; + RCP [label="Radio \nCo-Processor\n(ESP32-H2)", fontsize=14]; + STANDALONE [label="Standalone \nnode\n (ESP32-H2)", fontsize=14]; # node connections + labels RCP -> STANDALONE [label="15.4 radio", dir=both, style=dashed]; diff --git a/docs/en/api-reference/peripherals/adc_calibration.rst b/docs/en/api-reference/peripherals/adc_calibration.rst index e984cb3f1a..78dcaead03 100644 --- a/docs/en/api-reference/peripherals/adc_calibration.rst +++ b/docs/en/api-reference/peripherals/adc_calibration.rst @@ -119,7 +119,7 @@ For those users who use their custom ADC calibration schemes, you could either m ESP_ERROR_CHECK(adc_cali_delete_scheme_curve_fitting(handle)); -.. only:: esp32h4 +.. only:: esp32h2 There is no supported calibration scheme yet. diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst index 63e1fd8152..cd2e99d765 100644 --- a/docs/en/api-reference/peripherals/adc_continuous.rst +++ b/docs/en/api-reference/peripherals/adc_continuous.rst @@ -1,7 +1,7 @@ Analog to Digital Converter (ADC) Continuous Mode Driver ======================================================== -{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h4="one"} +{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one"} Introduction ------------ diff --git a/docs/en/api-reference/peripherals/adc_oneshot.rst b/docs/en/api-reference/peripherals/adc_oneshot.rst index 565ade5b7c..b75e9ee451 100644 --- a/docs/en/api-reference/peripherals/adc_oneshot.rst +++ b/docs/en/api-reference/peripherals/adc_oneshot.rst @@ -1,7 +1,7 @@ Analog to Digital Converter (ADC) Oneshot Mode Driver ===================================================== -{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h4="one"} +{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one"} Introduction ------------ diff --git a/docs/en/api-reference/peripherals/clk_tree.rst b/docs/en/api-reference/peripherals/clk_tree.rst index fe085b03bd..30284152fa 100644 --- a/docs/en/api-reference/peripherals/clk_tree.rst +++ b/docs/en/api-reference/peripherals/clk_tree.rst @@ -5,7 +5,7 @@ Clock Tree {IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5"} -{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32", esp32h2="32"} +{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h2="32"} {IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"} @@ -36,7 +36,7 @@ Root clocks generate reliable clock signals. These clock signals then pass throu The ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK. The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK. - + .. only:: not SOC_CLK_RC_FAST_D256_SUPPORTED and SOC_CLK_RC_FAST_SUPPORT_CALIBRATION The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. diff --git a/docs/en/api-reference/peripherals/i2s.rst b/docs/en/api-reference/peripherals/i2s.rst index dffb906c42..522f77b6fe 100644 --- a/docs/en/api-reference/peripherals/i2s.rst +++ b/docs/en/api-reference/peripherals/i2s.rst @@ -70,11 +70,11 @@ Clock Source - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_DEFAULT`: Default PLL clock. -.. only:: not esp32h4 +.. only:: not esp32h2 - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock. -.. only:: esp32h4 +.. only:: esp32h2 - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock. diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index 14bfa88106..2671ad2e8c 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -189,25 +189,6 @@ The source clock can also limit the PWM frequency. The higher the source clock f - 32 MHz - Dynamic Frequency Scaling compatible -.. only:: esp32h4 - - .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks - :widths: 15 15 30 - :header-rows: 1 - - * - Clock name - - Clock freq - - Clock capabilities - * - APB_CLK - - 96 MHz - - / - * - RC_FAST_CLK - - ~8 MHz - - Dynamic Frequency Scaling compatible, Light sleep compatible - * - XTAL_CLK - - 32 MHz - - Dynamic Frequency Scaling compatible - .. note:: .. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION diff --git a/docs/en/migration-guides/release-5.x/5.0/removed-components.rst b/docs/en/migration-guides/release-5.x/5.0/removed-components.rst index 5b587a4c00..7ba898ab4b 100644 --- a/docs/en/migration-guides/release-5.x/5.0/removed-components.rst +++ b/docs/en/migration-guides/release-5.x/5.0/removed-components.rst @@ -57,4 +57,4 @@ The targets components are no longer necessary after refactoring and have been r * ``esp32s3`` * ``esp32c2`` * ``esp32c3`` - * ``esp32h4`` + * ``esp32h2`` diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index de36e013a6..ac03bc05ed 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -189,25 +189,6 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - 32 MHz - 支持动态调频（DFS）功能 -.. only:: esp32h4 - - .. list-table:: {IDF_TARGET_NAME} LEDC 时钟源特性 - :widths: 10 10 30 - :header-rows: 1 - - * - 时钟名称 - - 时钟频率 - - 时钟功能 - * - APB_CLK - - 96 MHz - - / - * - RC_FAST_CLK - - ~8 MHz - - 支持动态调频（DFS）功能，支持Light-sleep模式 - * - XTAL_CLK - - 32 MHz - - 支持动态调频（DFS）功能 - .. note:: .. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION diff --git a/docs/zh_CN/migration-guides/release-5.x/5.0/removed-components.rst b/docs/zh_CN/migration-guides/release-5.x/5.0/removed-components.rst index 9e3d103e8c..12c4370fa2 100644 --- a/docs/zh_CN/migration-guides/release-5.x/5.0/removed-components.rst +++ b/docs/zh_CN/migration-guides/release-5.x/5.0/removed-components.rst @@ -57,4 +57,4 @@ IDF v4.x 版本中已不再使用以下组件，这些组件已弃用： * ``esp32s3`` * ``esp32c2`` * ``esp32c3`` - * ``esp32h4`` + * ``esp32h2`` diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml index 06c76d42ba..a934695505 100644 --- a/examples/bluetooth/.build-test-rules.yml +++ b/examples/bluetooth/.build-test-rules.yml @@ -2,31 +2,31 @@ examples/bluetooth/bluedroid/ble: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet examples/bluetooth/bluedroid/ble_50: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet examples/bluetooth/bluedroid/ble_50/multi-adv: enable: - - if: IDF_TARGET in ["esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet @@ -44,11 +44,11 @@ examples/bluetooth/bluedroid/coex/a2dp_gatts_coex: examples/bluetooth/bluedroid/coex/gattc_gatts_coex: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6", "esp32h2"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6", "esp32h2"] temporary: true reason: The runner doesn't support yet @@ -58,7 +58,7 @@ examples/bluetooth/blufi: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -68,7 +68,7 @@ examples/bluetooth/esp_ble_mesh: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -78,7 +78,7 @@ examples/bluetooth/esp_ble_mesh/aligenie_demo: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -88,7 +88,7 @@ examples/bluetooth/esp_ble_mesh/ble_mesh_coex_test: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -138,23 +138,23 @@ examples/bluetooth/nimble: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_l2cap_coc: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2" , "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2" , "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_multi_adv: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32h4", "esp32s3"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3"] temporary: true reason: the other targets are not tested yet disable_test: @@ -164,61 +164,61 @@ examples/bluetooth/nimble/ble_multi_adv: examples/bluetooth/nimble/ble_periodic_adv: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_periodic_sync: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_phy: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32h4", "esp32s3" ] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/ble_spp: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32h4", "esp32s3" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/blecent: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/blehr: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -228,17 +228,17 @@ examples/bluetooth/nimble/blemesh: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet examples/bluetooth/nimble/bleprph: enable: - - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2", "esp32h4" ] + - if: IDF_TARGET in ["esp32", "esp32c2", "esp32c3", "esp32c6" , "esp32s3", "esp32h2" ] temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h2", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -248,7 +248,7 @@ examples/bluetooth/nimble/bleprph_wifi_coex: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet @@ -258,6 +258,6 @@ examples/bluetooth/nimble/hci: temporary: true reason: the other targets are not tested yet disable_test: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4", "esp32s3", "esp32c6"] + - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32s3", "esp32c6"] temporary: true reason: The runner doesn't support yet diff --git a/examples/bluetooth/bluedroid/ble/ble_ancs/README.md b/examples/bluetooth/bluedroid/ble/ble_ancs/README.md index 40e05711c2..8b10feb42e 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ancs/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_ancs/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE ANCS Example @@ -28,7 +28,7 @@ All these characteristics require authorization for access. ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 deleted file mode 100644 index f72ed64fd0..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_ancs/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,8 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md index f074d148ab..2a68837a19 100644 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE Compatibility Test Example @@ -23,7 +23,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md b/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md index 0539a5542f..116c866cea 100644 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_eddystone/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Eddystone Example @@ -20,7 +20,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md index ac7665365c..ee29a3a354 100644 --- a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE HID Example @@ -23,7 +23,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md b/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md index 8b8d9f6f38..3292da3322 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF iBeacon demo diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md b/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md index 4975ee3d54..1f592e56ee 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF SPP GATT CLIENT demo diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_spp_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md b/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md index 8641951a86..e05a0c73a8 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | ## ESP-IDF GATT SERVER SPP Example @@ -15,7 +15,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-S3/ESP32-C2/ESP32-H4 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-S3/ESP32-C2/ESP32-H2 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_spp_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md index 85a88ff79c..2db13d9e46 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE throughput GATT CLIENT Test @@ -27,7 +27,7 @@ please set: `idf.py menuconfig --> Component config --> Example 'GATT CLIENT THR ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md index 57010cde2d..4bd56e2fea 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE throughput GATT SERVER Test @@ -26,7 +26,7 @@ please set: `idf.py menuconfig --> Component config --> Example 'GATT CLIENT THR ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with supported SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/README.md b/examples/bluetooth/bluedroid/ble/gatt_client/README.md index 3cd6b4650e..f7962c3ef8 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_client/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Client Example @@ -21,7 +21,7 @@ Please, check this [tutorial](tutorial/Gatt_Client_Example_Walkthrough.md) for m ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md b/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md index 593907bc76..dbc54c0b85 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Client Example @@ -24,7 +24,7 @@ Please, check this [tutorial](tutorial/Gatt_Security_Client_Example_Walkthrough. ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md b/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md index 8206d2711c..0c9904ca7b 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Server Example @@ -23,7 +23,7 @@ There are some important points for this demo: ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 Soc (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 Soc (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/README.md b/examples/bluetooth/bluedroid/ble/gatt_server/README.md index bf44eec10f..e75dbbe843 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Server Example @@ -23,7 +23,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md index e43019e555..9da98027db 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Server Service Table Example @@ -17,7 +17,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-H4/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-H2/ESP32-C2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md index 424c6acfd5..576feac667 100644 --- a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md +++ b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Client Multi Connection Example @@ -21,7 +21,7 @@ The code can be modified to connect to more devices (up to 4 devices by default) ### Hardware Required -* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H4/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) +* A development board with ESP32/ESP32-C3/ESP32-C2/ESP32-H2/ESP32-S3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 54a1d267df..0000000000 --- a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set -CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y -# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md index 67e933dde7..bbe23c5089 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Client Example @@ -26,7 +26,7 @@ Please, check this [tutorial](tutorial/ble50_security_client_Example_Walkthrough ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3 SoC, ESP32-C2/ESP32-H4 SoC and BT5.0 supported chip (e.g., ESP32-C3-DevKitC-1 etc.) +* A development board with ESP32-C3 SoC, ESP32-S3 SoC, ESP32-C2/ESP32-H2 SoC and BT5.0 supported chip (e.g., ESP32-C3-DevKitC-1 etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md index 39e0851b9d..4feedb799c 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE50 Security Server Example @@ -24,7 +24,7 @@ There are some important points for this demo: ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2/ESP32-H4 SoC and BLE5.0 supoorted chips. (e.g., ESP32-C3-DevKitC-1, etc.) +* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2/ESP32-H2 SoC and BLE5.0 supoorted chips. (e.g., ESP32-C3-DevKitC-1, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md b/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md index e3c5f35c99..a9938f5ad1 100644 --- a/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md +++ b/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | #ESP-IDF Multi Adv Example @@ -17,7 +17,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H4/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) +* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H2/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/multi-adv/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md index 9c561bac2a..250886bcc7 100644 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md +++ b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP_IDF Periodic Adv Example @@ -21,7 +21,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H4 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) +* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H2 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_adv/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md index 74a3fad22f..3fa038f99e 100644 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md +++ b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Periodic Sync Example @@ -19,7 +19,7 @@ idf.py set-target ### Hardware Required -* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H4 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) +* A development board with ESP32-C3 SoC, ESP32-S3, ESP32-C2, ESP32-H2 and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC-1, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 b/examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 7567c5ab84..0000000000 --- a/examples/bluetooth/bluedroid/ble_50/peroidic_sync/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,7 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md index 886dd7e17c..a79a893887 100644 --- a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md +++ b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | ESP-IDF Gattc and Gatts Coexistence example ============================================== diff --git a/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c index 9b8bd3fdc8..cf6252a59d 100644 --- a/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c +++ b/examples/bluetooth/esp_ble_mesh/ble_mesh_console/main/ble_mesh_console_main.c @@ -63,8 +63,6 @@ void app_main(void) repl_config.prompt = "esp32c3>"; #elif CONFIG_IDF_TARGET_ESP32S3 repl_config.prompt = "esp32s3>"; -#elif CONFIG_IDF_TARGET_ESP32H4 - repl_config.prompt = "esp32h4>"; #else repl_config.prompt = "esp32>"; #endif diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md index 7fdfb503b4..56b4588316 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Central L2CAP COC Example diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md index 1d8aafbde0..c40df5ee0f 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Central L2CAP COC Example diff --git a/examples/bluetooth/nimble/ble_multi_adv/README.md b/examples/bluetooth/nimble/ble_multi_adv/README.md index 48bebaf34a..780c5a23df 100644 --- a/examples/bluetooth/nimble/ble_multi_adv/README.md +++ b/examples/bluetooth/nimble/ble_multi_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Multi Adv Example @@ -34,7 +34,7 @@ To configure number of advertising instances: ### Hardware Required -* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H4/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) +* A development board with ESP32-C3 SoC,ESP32-S3/ESP32-H2/ESP32-C2 SoC and BLE5.0 supported chips (e.g., ESP32-C3-DevKitC, etc.) * A USB cable for Power supply and programming See [Development Boards](https://www.espressif.com/en/products/devkits) for more information about it. diff --git a/examples/bluetooth/nimble/ble_periodic_adv/README.md b/examples/bluetooth/nimble/ble_periodic_adv/README.md index 2ca24cdbe3..60873a4e34 100644 --- a/examples/bluetooth/nimble/ble_periodic_adv/README.md +++ b/examples/bluetooth/nimble/ble_periodic_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Periodic Advertiser Example @@ -30,7 +30,7 @@ idf.py set-target ### Configure the project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig @@ -60,9 +60,9 @@ I (353) system_api: read default base MAC address from EFUSE I (353) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:14:8e I (363) NimBLE_BLE_PERIODIC_ADV: BLE Host Task Started -I (373) NimBLE: Device Address: +I (373) NimBLE: Device Address: I (373) NimBLE: d0:42:3a:95:84:05 -I (373) NimBLE: +I (373) NimBLE: I (383) NimBLE: instance 1 started (periodic) ``` diff --git a/examples/bluetooth/nimble/ble_periodic_sync/README.md b/examples/bluetooth/nimble/ble_periodic_sync/README.md index 2977d607bf..c8e2d3aff4 100644 --- a/examples/bluetooth/nimble/ble_periodic_sync/README.md +++ b/examples/bluetooth/nimble/ble_periodic_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Periodic Sync Example @@ -37,7 +37,7 @@ See [Development Boards](https://www.espressif.com/en/products/devkits) for more ### Configure the Project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig @@ -67,15 +67,15 @@ I (351) system_api: read default base MAC address from EFUSE I (351) BTDM_INIT: Bluetooth MAC: 84:f7:03:08:14:8e I (361) NimBLE_BLE_PERIODIC_SYNC: BLE Host Task Started -I (941) NimBLE: Periodic sync event : +I (941) NimBLE: Periodic sync event : -I (941) NimBLE: Periodic adv report event: +I (941) NimBLE: Periodic adv report event: -I (4241) NimBLE: Periodic adv report event: +I (4241) NimBLE: Periodic adv report event: -I (7541) NimBLE: Periodic adv report event: +I (7541) NimBLE: Periodic adv report event: -I (10841) NimBLE: Periodic adv report event: +I (10841) NimBLE: Periodic adv report event: ``` diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md index b41cc01cf2..72d297a8b7 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Central PHY Example diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md index d723a212d1..687b7c8a95 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral PHY Example diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/README.md b/examples/bluetooth/nimble/ble_spp/spp_client/README.md index 047ec3e5f2..f517ab9e55 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/README.md +++ b/examples/bluetooth/nimble/ble_spp/spp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE SPP central example @@ -108,7 +108,7 @@ I (487) NimBLE_SPP_BLE_CENT: BLE Host Task Started GAP procedure initiated: stop advertising. GAP procedure initiated: discovery; own_addr_type=0 filter_policy=0 passive=1 limited=0 filter_duplicates=1 duration=forever GAP procedure initiated: connect; peer_addr_type=0 peer_addr=7c:df:a1:40:3e:fa scan_itvl=16 scan_window=16 itvl_min=24 itvl_max=40 latency=0 supervision_timeout=256 min_ce_len=0 max_ce_len=0 own_addr_type=0 -Connection established +Connection established GATT procedure initiated: discover all services GATT procedure initiated: discover all characteristics; start_handle=1 end_handle=5 GATT procedure initiated: discover all characteristics; start_handle=6 end_handle=9 diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/README.md b/examples/bluetooth/nimble/ble_spp/spp_server/README.md index 38775429f3..e206735eed 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/README.md +++ b/examples/bluetooth/nimble/ble_spp/spp_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE SPP peripheral example @@ -106,7 +106,7 @@ GAP procedure initiated: advertise; disc_mode=2 adv_channel_map=0 own_addr_type= connection established; status=0 handle=1 our_ota_addr_type=0 our_ota_addr=7c:df:a1:40:3e:fa our_id_addr_type=0 our_id_addr=7c:df:a1:40:3e:fa peer_ota_addr_type=0 peer_ota_addr=7c:df:a1:c2:19:92 peer_id_addr_type=0 peer_id_addr=7c:df:a1:c2:19:92 conn_itvl=40 conn_latency=0 supervision_timeout=256 encrypted=0 authenticated=0 bonded=0 I (6924) NimBLE_SPP_BLE_PRPH: Data received in write event,conn_handle = 1,attr_handle = 11 -1b5b41I +1b5b41I (10824) NimBLE_SPP_BLE_PRPH: Notification sent successfully ``` diff --git a/examples/bluetooth/nimble/blecent/README.md b/examples/bluetooth/nimble/blecent/README.md index e1026bf6c3..32bd991fcf 100644 --- a/examples/bluetooth/nimble/blecent/README.md +++ b/examples/bluetooth/nimble/blecent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Central Example @@ -31,7 +31,7 @@ This example aims at understanding BLE service discovery, connection, encryption To test this demo, use any BLE GATT server app that advertises support for the Alert Notification service (0x1811) and includes it in the GATT database. -A Python based utility `blecent_test.py` is also provided (which will run as a BLE GATT server) and can be used to test this example. +A Python based utility `blecent_test.py` is also provided (which will run as a BLE GATT server) and can be used to test this example. Note : @@ -55,7 +55,7 @@ See [Development Boards](https://www.espressif.com/en/products/devkits) for more ### Configure the Project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig diff --git a/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 1587bd33f2..0000000000 --- a/examples/bluetooth/nimble/blecent/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_ESPTOOLPY_FLASHMODE_QIO=y -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_EXT_ADV=y -CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/nimble/blehr/README.md b/examples/bluetooth/nimble/blehr/README.md index 91ac4bf59f..92dc5fdf62 100644 --- a/examples/bluetooth/nimble/blehr/README.md +++ b/examples/bluetooth/nimble/blehr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Heart Rate Measurement Example @@ -13,7 +13,7 @@ This example aims at understanding notification subscriptions and sending notifi To test this demo, any BLE scanner app can be used. -A Python based utility `blehr_test.py` is also provided (which will run as a BLE GATT Client) and can be used to test this example. +A Python based utility `blehr_test.py` is also provided (which will run as a BLE GATT Client) and can be used to test this example. Note : diff --git a/examples/bluetooth/nimble/bleprph/README.md b/examples/bluetooth/nimble/bleprph/README.md index 07cf4fda74..9692af72b0 100644 --- a/examples/bluetooth/nimble/bleprph/README.md +++ b/examples/bluetooth/nimble/bleprph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral Example @@ -34,7 +34,7 @@ idf.py set-target ### Configure the project -Open the project configuration menu: +Open the project configuration menu: ```bash idf.py menuconfig diff --git a/examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 deleted file mode 100644 index 3e24e0e3cf..0000000000 --- a/examples/bluetooth/nimble/bleprph/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,8 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE=70 -CONFIG_BT_NIMBLE_EXT_ADV=y diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 deleted file mode 100644 index a6723d3f65..0000000000 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_ESPTOOLPY_FLASHMODE_QIO=y -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_USE_ESP_TIMER=n -CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 deleted file mode 100644 index a6723d3f65..0000000000 --- a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/sdkconfig.defaults.esp32h4 +++ /dev/null @@ -1,10 +0,0 @@ -# This file was generated using idf.py save-defconfig. It can be edited manually. -# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration -# -CONFIG_IDF_TARGET="esp32h4" -CONFIG_ESPTOOLPY_FLASHMODE_QIO=y -CONFIG_BT_ENABLED=y -CONFIG_BT_NIMBLE_ENABLED=y -CONFIG_BT_NIMBLE_USE_ESP_TIMER=n -CONFIG_ESP32H4_RTC_CLK_SRC_EXT_CRYS=y -CONFIG_ESP32H4_RTC_CLK_CAL_CYCLES=576 diff --git a/examples/build_system/cmake/idf_as_lib/CMakeLists.txt b/examples/build_system/cmake/idf_as_lib/CMakeLists.txt index 6409d4a6bc..353c6cfb59 100644 --- a/examples/build_system/cmake/idf_as_lib/CMakeLists.txt +++ b/examples/build_system/cmake/idf_as_lib/CMakeLists.txt @@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.16) project(idf_as_lib C) -set(targets "esp32" "esp32s2" "esp32s3" "esp32c3" "esp32h4" "esp32c2" "esp32c6" "esp32h2") +set(targets "esp32" "esp32s2" "esp32s3" "esp32c3" "esp32c2" "esp32c6" "esp32h2") if("${TARGET}" IN_LIST targets) # Include for ESP-IDF build system functions diff --git a/examples/build_system/cmake/idf_as_lib/README.md b/examples/build_system/cmake/idf_as_lib/README.md index bd291059bb..0cc5619a9f 100644 --- a/examples/build_system/cmake/idf_as_lib/README.md +++ b/examples/build_system/cmake/idf_as_lib/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Using ESP-IDF in Custom CMake Projects diff --git a/examples/build_system/cmake/idf_as_lib/build-esp32h4.sh b/examples/build_system/cmake/idf_as_lib/build-esp32h4.sh deleted file mode 120000 index c07a74de4f..0000000000 --- a/examples/build_system/cmake/idf_as_lib/build-esp32h4.sh +++ /dev/null @@ -1 +0,0 @@ -build.sh \ No newline at end of file diff --git a/examples/build_system/cmake/idf_as_lib/run-esp32h4.sh b/examples/build_system/cmake/idf_as_lib/run-esp32h4.sh deleted file mode 120000 index cde8585ed4..0000000000 --- a/examples/build_system/cmake/idf_as_lib/run-esp32h4.sh +++ /dev/null @@ -1 +0,0 @@ -run-esp32.sh \ No newline at end of file diff --git a/examples/common_components/env_caps/esp32h4/Kconfig.env_caps b/examples/common_components/env_caps/esp32h4/Kconfig.env_caps deleted file mode 100644 index 193652111b..0000000000 --- a/examples/common_components/env_caps/esp32h4/Kconfig.env_caps +++ /dev/null @@ -1,15 +0,0 @@ -config ENV_GPIO_RANGE_MIN - int - default 0 - -config ENV_GPIO_RANGE_MAX - int - default 25 - -config ENV_GPIO_IN_RANGE_MAX - int - default ENV_GPIO_RANGE_MAX - -config ENV_GPIO_OUT_RANGE_MAX - int - default ENV_GPIO_RANGE_MAX diff --git a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild index 9e84fb73ec..a3d7b9cf22 100644 --- a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild +++ b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild @@ -142,7 +142,7 @@ menu "Example Ethernet Configuration" default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 4 if IDF_TARGET_ESP32H4 + default 4 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI SCLK. @@ -152,7 +152,7 @@ menu "Example Ethernet Configuration" default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 5 if IDF_TARGET_ESP32H4 + default 5 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MOSI. @@ -162,14 +162,14 @@ menu "Example Ethernet Configuration" default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 0 if IDF_TARGET_ESP32H4 + default 0 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MISO. config EXAMPLE_ETH_SPI_CLOCK_MHZ int "SPI clock speed (MHz)" range 5 80 - default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4 + default 12 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 default 36 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 help Set the clock speed (MHz) of SPI interface. @@ -179,7 +179,7 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 - default 1 if IDF_TARGET_ESP32H4 + default 1 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI CS0, i.e. Chip Select associated with the first SPI Eth module). @@ -191,7 +191,7 @@ menu "Example Ethernet Configuration" default 7 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 8 if IDF_TARGET_ESP32C3 default 3 if IDF_TARGET_ESP32C2 - default 11 if IDF_TARGET_ESP32H4 + default 11 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI CS1, i.e. Chip Select associated with the second SPI Eth module. @@ -200,7 +200,7 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 - default 9 if IDF_TARGET_ESP32H4 + default 9 if IDF_TARGET_ESP32H2 help Set the GPIO number used by the first SPI Ethernet module interrupt line. @@ -210,7 +210,7 @@ menu "Example Ethernet Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 33 if IDF_TARGET_ESP32 default 5 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 - default 10 if IDF_TARGET_ESP32H4 + default 10 if IDF_TARGET_ESP32H2 help Set the GPIO number used by the second SPI Ethernet module interrupt line. diff --git a/examples/ethernet/enc28j60/main/Kconfig.projbuild b/examples/ethernet/enc28j60/main/Kconfig.projbuild index 9223777db2..c33f4b97e7 100644 --- a/examples/ethernet/enc28j60/main/Kconfig.projbuild +++ b/examples/ethernet/enc28j60/main/Kconfig.projbuild @@ -15,7 +15,7 @@ menu "Example Configuration" default 14 if IDF_TARGET_ESP32 default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 6 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 4 if IDF_TARGET_ESP32H4 + default 4 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI SCLK. @@ -25,7 +25,7 @@ menu "Example Configuration" default 13 if IDF_TARGET_ESP32 default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 7 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 5 if IDF_TARGET_ESP32H4 + default 5 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MOSI. @@ -35,7 +35,7 @@ menu "Example Configuration" default 12 if IDF_TARGET_ESP32 default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 default 2 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2 - default 0 if IDF_TARGET_ESP32H4 + default 0 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI MISO. @@ -44,7 +44,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX default 15 if IDF_TARGET_ESP32 default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2 - default 1 if IDF_TARGET_ESP32H4 + default 1 if IDF_TARGET_ESP32H2 help Set the GPIO number used by SPI CS. @@ -60,7 +60,7 @@ menu "Example Configuration" range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX default 4 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 4 if IDF_TARGET_ESP32C2 - default 9 if IDF_TARGET_ESP32H4 + default 9 if IDF_TARGET_ESP32H2 help Set the GPIO number used by ENC28J60 interrupt. diff --git a/examples/get-started/.build-test-rules.yml b/examples/get-started/.build-test-rules.yml index ec68aa7b20..0972e4ceca 100644 --- a/examples/get-started/.build-test-rules.yml +++ b/examples/get-started/.build-test-rules.yml @@ -2,4 +2,4 @@ examples/get-started/hello_world: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32h4"] # preview targets + - if: INCLUDE_DEFAULT == 1 diff --git a/examples/get-started/hello_world/README.md b/examples/get-started/hello_world/README.md index e7b9054386..f400cbda43 100644 --- a/examples/get-started/hello_world/README.md +++ b/examples/get-started/hello_world/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Hello World Example diff --git a/examples/openthread/README.md b/examples/openthread/README.md index ae0709fca7..1c7728835e 100644 --- a/examples/openthread/README.md +++ b/examples/openthread/README.md @@ -6,8 +6,8 @@ See the [README.md](../README.md) file in the upper level [examples](../) direct In this folder, it contains following OpenThread examples: -* [ot_cli](ot_cli) is an OpenThread Command Line example, in addition to the features listed in [OpenThread CLI](https://github.com/openthread/openthread/blob/master/src/cli/README.md), it supports some additional features such as TCP, UDP and Iperf over lwIP. It runs on an 802.15.4 SoC like ESP32-H4. +* [ot_cli](ot_cli) is an OpenThread Command Line example, in addition to the features listed in [OpenThread CLI](https://github.com/openthread/openthread/blob/master/src/cli/README.md), it supports some additional features such as TCP, UDP and Iperf over lwIP. It runs on an 802.15.4 SoC like ESP32-H2. -* [ot_rcp](ot_rcp) is an [OpenThread RCP](https://openthread.io/platforms/co-processor) example. It runs on an 802.15.4 SoC like ESP32-H4, to extend 802.15.4 radio. +* [ot_rcp](ot_rcp) is an [OpenThread RCP](https://openthread.io/platforms/co-processor) example. It runs on an 802.15.4 SoC like ESP32-H2, to extend 802.15.4 radio. -* [ot_br](ot_br) is an [OpenThread Border Router](https://openthread.io/guides/border-router) example. It runs on a Wi-Fi SoC such as ESP32, ESP32-C3 and ESP32-S3. It needs an 802.15.4 SoC like ESP32-H4 running [ot_rcp](ot_rcp) example to provide 802.15.4 radio. +* [ot_br](ot_br) is an [OpenThread Border Router](https://openthread.io/guides/border-router) example. It runs on a Wi-Fi SoC such as ESP32, ESP32-C3 and ESP32-S3. It needs an 802.15.4 SoC like ESP32-H2 running [ot_rcp](ot_rcp) example to provide 802.15.4 radio. diff --git a/examples/openthread/ot_cli/sdkconfig.defaults b/examples/openthread/ot_cli/sdkconfig.defaults index cfc1abd08c..9ea24974eb 100644 --- a/examples/openthread/ot_cli/sdkconfig.defaults +++ b/examples/openthread/ot_cli/sdkconfig.defaults @@ -19,7 +19,7 @@ CONFIG_PARTITION_TABLE_MD5=y # # mbedTLS # -# ESP32H4-TODO: enable HW acceleration +# ESP32H2-TODO: enable HW acceleration CONFIG_MBEDTLS_HARDWARE_AES=n CONFIG_MBEDTLS_HARDWARE_MPI=n CONFIG_MBEDTLS_HARDWARE_SHA=n diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml index 28b1931547..0774976cec 100644 --- a/examples/peripherals/.build-test-rules.yml +++ b/examples/peripherals/.build-test-rules.yml @@ -277,7 +277,7 @@ examples/peripherals/twai/twai_self_test: examples/peripherals/uart/uart_echo_rs485: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "esp32h4" + - if: INCLUDE_DEFAULT == 1 examples/peripherals/usb: disable: diff --git a/examples/peripherals/gpio/generic_gpio/README.md b/examples/peripherals/gpio/generic_gpio/README.md index 8634661f61..2070fd10ac 100644 --- a/examples/peripherals/gpio/generic_gpio/README.md +++ b/examples/peripherals/gpio/generic_gpio/README.md @@ -25,7 +25,7 @@ This test code shows how to configure GPIO and how to use it with interruption. | | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 | | ---------------------- | -------------------- | -------------------- | ------------------- | ------------------- | -| ESP32C2/ESP32H2/ESP32H4| 8 | 9 | 4 | 5 | +| ESP32C2/ESP32H2 | 8 | 9 | 4 | 5 | | All other chips | 18 | 19 | 4 | 5 | ## How to use example diff --git a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild index 17b7d341a2..511b47633b 100644 --- a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild +++ b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild @@ -5,7 +5,7 @@ menu "Example Configuration" config GPIO_OUTPUT_0 int "GPIO output pin 0" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H2 + default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 default 18 help GPIO pin number to be used as GPIO_OUTPUT_IO_0. @@ -13,7 +13,7 @@ menu "Example Configuration" config GPIO_OUTPUT_1 int "GPIO output pin 1" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H2 + default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 default 19 help GPIO pin number to be used as GPIO_OUTPUT_IO_1. diff --git a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c index b8090f0b80..1ef2491e6e 100644 --- a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c +++ b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c @@ -20,8 +20,8 @@ * This test code shows how to configure gpio and how to use gpio interrupt. * * GPIO status: - * GPIO18: output (ESP32C2/ESP32H2/ESP32H4 uses GPIO8 as the second output pin) - * GPIO19: output (ESP32C2/ESP32H2/ESP32H4 uses GPIO9 as the second output pin) + * GPIO18: output (ESP32C2/ESP32H2 uses GPIO8 as the second output pin) + * GPIO19: output (ESP32C2/ESP32H2 uses GPIO9 as the second output pin) * GPIO4: input, pulled up, interrupt from rising edge and falling edge * GPIO5: input, pulled up, interrupt from rising edge. * diff --git a/examples/peripherals/i2c/i2c_self_test/README.md b/examples/peripherals/i2c/i2c_self_test/README.md index 2f787d36f0..f5619a732f 100644 --- a/examples/peripherals/i2c/i2c_self_test/README.md +++ b/examples/peripherals/i2c/i2c_self_test/README.md @@ -44,15 +44,15 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE **Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors. -#### Pin Assignment(esp32s3): +#### Pin Assignment(esp32s3, esp32h2): **Note:** The following pin assignments are used by default, you can change these in the `menuconfig` . -| | SDA | SCL | -| ------------------------- | ------ | ------ | -| ESP32-S3 I2C Master | GPIO1 | GPIO2 | -| ESP32-S3 I2C Slave | GPIO4 | GPIO5 | -| BH1750 Sensor | SDA | SCL | +| | SDA | SCL | +| ---------------------------------- | ------ | ------ | +| ESP32-S3/ESP32-H2 I2C Master | GPIO1 | GPIO2 | +| ESP32-S3/ESP32-H2 I2C Slave | GPIO4 | GPIO5 | +| BH1750 Sensor | SDA | SCL | - slave: - GPIO4 is assigned as the data signal of I2C slave port @@ -68,13 +68,13 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE **Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors. -#### Pin Assignment(esp32c3, esp32c2, esp32h4): +#### Pin Assignment(esp32c3, esp32c2): **Note:** The following pin assignments are used by default, you can change these in the `menuconfig` . | | SDA | SCL | | ------------------------------------------- | ------ | ------ | -| ESP32-C3/ESP32-C2/ESP32-H4 I2C Master(Slave)| GPIO5 | GPIO6 | +| ESP32-C3/ESP32-C2 I2C Master(Slave) | GPIO5 | GPIO6 | | BH1750 Sensor | SDA | SCL | - master: @@ -84,7 +84,7 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE - Connection: - connect SDA/SCL of BH1750 sensor to GPIO5/GPIO6 -**Note:** There is only one i2c device on ESP32-C3/ESP32-C2/ESP32-H4, so it is not possible to perform any ESP32/ESP32-S2 self-test example from this repo. However it is possible to test I2C with external devices. If you find anything wrong with your device, please try connecting external pull-up resistors. +**Note:** There is only one i2c device on ESP32-C3/ESP32-C2, so it is not possible to perform any ESP32/ESP32-S2 self-test example from this repo. However it is possible to test I2C with external devices. If you find anything wrong with your device, please try connecting external pull-up resistors. ### Configure the project diff --git a/examples/peripherals/i2c/i2c_tools/README.md b/examples/peripherals/i2c/i2c_tools/README.md index bab2d3e3a4..e40d4b0e98 100644 --- a/examples/peripherals/i2c/i2c_tools/README.md +++ b/examples/peripherals/i2c/i2c_tools/README.md @@ -34,7 +34,7 @@ To run this example, you should have any ESP32, ESP32-S and ESP32-C based develo | ESP32-S3 I2C Master | GPIO1 | GPIO2 | GND | GND | 3.3V | | ESP32-C3 I2C Master | GPIO5 | GPIO6 | GND | GND | 3.3V | | ESP32-C2 I2C Master | GPIO5 | GPIO6 | GND | GND | 3.3V | -| ESP32-H4 I2C Master | GPIO5 | GPIO6 | GND | GND | 3.3V | +| ESP32-H2 I2C Master | GPIO1 | GPIO2 | GND | GND | 3.3V | | Sensor | SDA | SCL | GND | WAK | VCC | **Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors. diff --git a/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c b/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c index 9ca94a61fa..793aa3a38d 100644 --- a/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c +++ b/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c @@ -31,7 +31,7 @@ static const char *TAG = "cmd_i2ctools"; #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2 static gpio_num_t i2c_gpio_sda = 1; static gpio_num_t i2c_gpio_scl = 2; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 static gpio_num_t i2c_gpio_sda = 5; static gpio_num_t i2c_gpio_scl = 6; #else diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md index e1663ead05..bbfcf8f9f4 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md @@ -55,7 +55,7 @@ For more details, see [ES8311 datasheet](http://www.everest-semi.com/pdf/ES8311% │ GND├───────────┤GND │ └─────────────────┘ └──────────────────────────┘ ``` -Note: Since ESP32-C3 & ESP32-H4 board does not have GPIO 16/17, you can use other available GPIOs instead. In this example, we set GPIO 6/7 as I2C pins for ESP32-C3 & ESP32-H4 and GPIO 16/17 for other chips, same as GPIO 18/19, we use GPIO 2/3 instead. +Note: Since ESP32-C3 & ESP32-H2 board does not have GPIO 16/17, you can use other available GPIOs instead. In this example, we set GPIO 6/7 as I2C pins for ESP32-C3 and GPIO 8/9 ESP32-H2 and GPIO 16/17 for other chips, same as GPIO 18/19, we use GPIO 2/3 instead. ### Dependency @@ -73,13 +73,13 @@ If the dependency is added, you can check `idf_component.yml` for more detail. W ``` idf.py menuconfig ``` -You can find configurations for this example in 'Example Configutation' tag. +You can find configurations for this example in 'Example Configuration' tag. * In 'Example mode' subtag, you can set the example mode to 'music' or 'echo'. You can hear a piece of music in 'music' mode and echo the sound sampled by mic in 'echo' mode. You can also customize you own music to play as shown below. * In 'Set MIC gain' subtag, you can set the mic gain for echo mode. -* In 'Voice volume', you can set the volum between 0 to 100. +* In 'Voice volume', you can set the volume between 0 to 100. * In 'Enable Board Support Package (BSP) support' you can enable support for BSP. You can pick specific BSP in [idf_component.yml](main/idf_component.yml). diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h index bf75995fce..72835af592 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h @@ -26,6 +26,9 @@ #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #define I2C_SCL_IO (GPIO_NUM_16) #define I2C_SDA_IO (GPIO_NUM_17) +#elif CONFIG_IDF_TARGET_ESP32H2 +#define I2C_SCL_IO (GPIO_NUM_8) +#define I2C_SDA_IO (GPIO_NUM_9) #else #define I2C_SCL_IO (GPIO_NUM_6) #define I2C_SDA_IO (GPIO_NUM_7) diff --git a/examples/peripherals/spi_slave/receiver/main/app_main.c b/examples/peripherals/spi_slave/receiver/main/app_main.c index d34ef3e205..b6c7c30802 100644 --- a/examples/peripherals/spi_slave/receiver/main/app_main.c +++ b/examples/peripherals/spi_slave/receiver/main/app_main.c @@ -41,7 +41,7 @@ Pins in use. The SPI Master can use the GPIO mux, so feel free to change these i #define GPIO_SCLK 15 #define GPIO_CS 14 -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #define GPIO_HANDSHAKE 3 #define GPIO_MOSI 7 #define GPIO_MISO 2 diff --git a/examples/peripherals/spi_slave/sender/main/app_main.c b/examples/peripherals/spi_slave/sender/main/app_main.c index 82559d5b70..ef0bc18aff 100644 --- a/examples/peripherals/spi_slave/sender/main/app_main.c +++ b/examples/peripherals/spi_slave/sender/main/app_main.c @@ -42,7 +42,7 @@ Pins in use. The SPI Master can use the GPIO mux, so feel free to change these i #define GPIO_SCLK 15 #define GPIO_CS 14 -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #define GPIO_HANDSHAKE 3 #define GPIO_MOSI 7 #define GPIO_MISO 2 diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c index 0dbc4b7d92..eb20b9818a 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/main/app_main.c @@ -21,7 +21,7 @@ #define GPIO_SCLK 12 #define GPIO_CS 10 -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #define GPIO_MOSI 7 #define GPIO_MISO 2 #define GPIO_SCLK 6 diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c index 3384a5a67e..b4345efdef 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c @@ -22,7 +22,7 @@ #define GPIO_SCLK 12 #define GPIO_CS 10 -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 #define GPIO_MOSI 7 #define GPIO_MISO 2 #define GPIO_SCLK 6 diff --git a/examples/peripherals/uart/uart_echo_rs485/README.md b/examples/peripherals/uart/uart_echo_rs485/README.md index 7e2faab0c5..a3f749ddf1 100644 --- a/examples/peripherals/uart/uart_echo_rs485/README.md +++ b/examples/peripherals/uart/uart_echo_rs485/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # UART RS485 Echo Example diff --git a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c b/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c index dab15b180e..ea5667e0b5 100644 --- a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c +++ b/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c @@ -22,7 +22,7 @@ #include "esp_system.h" #include "soc/spi_pins.h" -// h4 and c2 will not support external flash +// h2 and c2 will not support external flash #define EXAMPLE_FLASH_FREQ_MHZ 40 static const char *TAG = "example"; diff --git a/examples/storage/semihost_vfs/README.md b/examples/storage/semihost_vfs/README.md index bfd840dc3d..28c5b3a42d 100644 --- a/examples/storage/semihost_vfs/README.md +++ b/examples/storage/semihost_vfs/README.md @@ -73,7 +73,7 @@ openocd -c "set ESP_SEMIHOST_BASEDIR %IDF_PATH%/examples/storage/semihost_vfs/da The above command will set `ESP_SEMIHOST_BASEDIR` variable to `examples/storage/semihost_vfs/data` subdirectory of ESP-IDF. With that, it is not necessary to run OpenOCD from that specific directory. -> Note: This feature is not available for RISC-V based SoCs (ESP32-C3, ESP32-H4). To set the semihosting base directory, change into the required directory before running `openocd` command. +> Note: This feature is not available for RISC-V based SoCs (ESP32-C3, ESP32-H2). To set the semihosting base directory, change into the required directory before running `openocd` command. ## Example output diff --git a/examples/system/console/advanced/components/cmd_system/cmd_system.c b/examples/system/console/advanced/components/cmd_system/cmd_system.c index d4e3dfef91..58b94a5970 100644 --- a/examples/system/console/advanced/components/cmd_system/cmd_system.c +++ b/examples/system/console/advanced/components/cmd_system/cmd_system.c @@ -87,8 +87,8 @@ static int get_version(int argc, char **argv) case CHIP_ESP32C3: model = "ESP32-C3"; break; - case CHIP_ESP32H4: - model = "ESP32-H4"; + case CHIP_ESP32H2: + model = "ESP32-H2"; break; case CHIP_ESP32C2: model = "ESP32-C2"; diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index 5e1cdbb36b..97793a8209 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -60,11 +60,11 @@ menu "Example Configuration" config EXAMPLE_GPIO_WAKEUP_PIN int "Enable wakeup from GPIO" - default 0 if !IDF_TARGET_ESP32H4_BETA_VERSION_2 - default 7 if IDF_TARGET_ESP32H4_BETA_VERSION_2 + default 0 if !IDF_TARGET_ESP32H2 + default 7 if IDF_TARGET_ESP32H2 range 0 7 if IDF_TARGET_ESP32C6 - range 0 5 if !IDF_TARGET_ESP32H4_BETA_VERSION_2 - range 7 12 if IDF_TARGET_ESP32H4_BETA_VERSION_2 + range 7 14 if IDF_TARGET_ESP32H2 + range 0 5 if !IDF_TARGET_ESP32C6 && !IDF_TARGET_ESP32H2 config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL bool "Enable GPIO high-level wakeup" diff --git a/examples/system/esp_timer/sdkconfig.ci.rtc b/examples/system/esp_timer/sdkconfig.ci.rtc index f0f3c7eae2..0b0237ec75 100644 --- a/examples/system/esp_timer/sdkconfig.ci.rtc +++ b/examples/system/esp_timer/sdkconfig.ci.rtc @@ -7,4 +7,3 @@ CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC=y CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC=y CONFIG_ESP32C2_TIME_SYSCALL_USE_RTC=y CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC=y -CONFIG_ESP32H4_TIME_SYSCALL_USE_RTC=y diff --git a/examples/system/gcov/main/Kconfig.projbuild b/examples/system/gcov/main/Kconfig.projbuild index 8b3d5d4d8a..a5ff55cf83 100644 --- a/examples/system/gcov/main/Kconfig.projbuild +++ b/examples/system/gcov/main/Kconfig.projbuild @@ -5,7 +5,7 @@ menu "Example Configuration" config BLINK_GPIO int "Blink GPIO number" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 8 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32C2 + default 8 if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C2 default 18 if IDF_TARGET_ESP32S2 default 48 if IDF_TARGET_ESP32S3 default 5 diff --git a/examples/system/light_sleep/main/gpio_wakeup.c b/examples/system/light_sleep/main/gpio_wakeup.c index d60ec0e380..a4e86386de 100644 --- a/examples/system/light_sleep/main/gpio_wakeup.c +++ b/examples/system/light_sleep/main/gpio_wakeup.c @@ -12,7 +12,7 @@ /* Most development boards have "boot" button attached to GPIO0. * You can also change this to another pin. */ -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H4 \ +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 \ || CONFIG_IDF_TARGET_ESP32C6 #define BOOT_BUTTON_NUM 9 #else diff --git a/examples/zigbee/light_sample/README.md b/examples/zigbee/light_sample/README.md index 4534f278f4..2ef76b5b03 100644 --- a/examples/zigbee/light_sample/README.md +++ b/examples/zigbee/light_sample/README.md @@ -6,7 +6,7 @@ The folder contains examples demonstrating Zigbee Coordinator and End-Device roles -* [HA_on_off_light](HA_on_off_light) is a standard HA on-off light bulb example demonstrating Zigbee End-device. It provides a simple on/off condition for a Zigbee light. It runs on an 802.15.4 SoC like ESP32-H4. For more details see the example readme file. +* [HA_on_off_light](HA_on_off_light) is a standard HA on-off light bulb example demonstrating Zigbee End-device. It provides a simple on/off condition for a Zigbee light. It runs on an 802.15.4 SoC like ESP32-H2. For more details see the example readme file. -* [HA_on_off_switch](HA_on_off_switch) is a standard HA on-off switch example demonstrating Zigbee Coordinator role. It provides an on/off toggle to control a Zigbee HA on off light. It runs on an 802.15.4 SoC like ESP32-H4. For more details to see the example readme file. +* [HA_on_off_switch](HA_on_off_switch) is a standard HA on-off switch example demonstrating Zigbee Coordinator role. It provides an on/off toggle to control a Zigbee HA on off light. It runs on an 802.15.4 SoC like ESP32-H2. For more details to see the example readme file. diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh index 4e9cb82e12..8f268f5530 100755 --- a/tools/ci/build_template_app.sh +++ b/tools/ci/build_template_app.sh @@ -64,7 +64,7 @@ build_stage2() { --build-log ${BUILD_LOG_CMAKE} \ --size-file size.json \ --collect-size-info size_info.txt \ - --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2 # add esp32h4 back after IDF-5541 + --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2 } build_stage1() { @@ -78,7 +78,7 @@ build_stage1() { --build-log ${BUILD_LOG_CMAKE} \ --size-file size.json \ --collect-size-info size_info.txt \ - --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32h4,esp32c6,esp32h2 + --default-build-targets esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2 } # Default arguments diff --git a/tools/ci/check_build_test_rules.py b/tools/ci/check_build_test_rules.py index 9b66c74d86..3823148aa9 100755 --- a/tools/ci/check_build_test_rules.py +++ b/tools/ci/check_build_test_rules.py @@ -29,7 +29,6 @@ USUAL_TO_FORMAL = { 'esp32s2': 'ESP32-S2', 'esp32s3': 'ESP32-S3', 'esp32c3': 'ESP32-C3', - 'esp32h4': 'ESP32-H4', 'esp32c2': 'ESP32-C2', 'esp32c6': 'ESP32-C6', 'esp32h2': 'ESP32-H2', @@ -41,7 +40,6 @@ FORMAL_TO_USUAL = { 'ESP32-S2': 'esp32s2', 'ESP32-S3': 'esp32s3', 'ESP32-C3': 'esp32c3', - 'ESP32-H4': 'esp32h4', 'ESP32-C2': 'esp32c2', 'ESP32-C6': 'esp32c6', 'ESP32-H2': 'esp32h2', @@ -221,7 +219,7 @@ def check_test_scripts( # { # app_dir: { # 'script_path': 'path/to/script', - # 'targets': ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32h4', 'esp32c2', 'linux'], + # 'targets': ['esp32', 'esp32s2', 'esp32s3', 'esp32c3', 'esp32c2', 'linux'], # } # } def check_enable_test( diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index b2a06e8e5a..25cbc39b67 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -106,7 +106,6 @@ components/esp_rom/include/esp32/rom/rtc.h components/esp_rom/include/esp32c3/rom/rtc.h components/esp_rom/include/esp32s2/rom/rtc.h components/esp_rom/include/esp32s3/rom/rtc.h -components/esp_rom/include/esp32h4/rom/rtc.h components/esp_rom/include/esp32c2/rom/rtc.h components/esp_rom/include/esp32c6/rom/rtc.h components/esp_rom/include/esp32h2/rom/rtc.h diff --git a/tools/ci/executable-list.txt b/tools/ci/executable-list.txt index 2b4086931c..fe2756c72a 100644 --- a/tools/ci/executable-list.txt +++ b/tools/ci/executable-list.txt @@ -31,14 +31,12 @@ docs/check_lang_folder_sync.sh examples/build_system/cmake/idf_as_lib/build-esp32.sh examples/build_system/cmake/idf_as_lib/build-esp32c2.sh examples/build_system/cmake/idf_as_lib/build-esp32c3.sh -examples/build_system/cmake/idf_as_lib/build-esp32h4.sh examples/build_system/cmake/idf_as_lib/build-esp32s2.sh examples/build_system/cmake/idf_as_lib/build-esp32s3.sh examples/build_system/cmake/idf_as_lib/build.sh examples/build_system/cmake/idf_as_lib/run-esp32.sh examples/build_system/cmake/idf_as_lib/run-esp32c2.sh examples/build_system/cmake/idf_as_lib/run-esp32c3.sh -examples/build_system/cmake/idf_as_lib/run-esp32h4.sh examples/build_system/cmake/idf_as_lib/run-esp32s2.sh examples/build_system/cmake/idf_as_lib/run-esp32s3.sh examples/build_system/cmake/idf_as_lib/run.sh diff --git a/tools/ci/python_packages/ttfw_idf/IDFDUT.py b/tools/ci/python_packages/ttfw_idf/IDFDUT.py index 4653331ba9..49ae306f6f 100644 --- a/tools/ci/python_packages/ttfw_idf/IDFDUT.py +++ b/tools/ci/python_packages/ttfw_idf/IDFDUT.py @@ -640,15 +640,6 @@ class ESP32H2DUT(IDFDUT): return targets.ESP32H2ROM -class ESP32H4DUT(IDFDUT): - TARGET = 'esp32h4' - TOOLCHAIN_PREFIX = 'riscv32-esp-elf-' - - @classmethod - def get_rom(cls): - return targets.ESP32H4ROM - - class ESP8266DUT(IDFDUT): TARGET = 'esp8266' TOOLCHAIN_PREFIX = 'xtensa-lx106-elf-' @@ -659,7 +650,7 @@ class ESP8266DUT(IDFDUT): def get_target_by_rom_class(cls): - for c in [ESP32DUT, ESP32S2DUT, ESP32S3DUT, ESP32C2DUT, ESP32C3DUT, ESP32C6DUT, ESP32H2DUT, ESP32H4DUT, ESP8266DUT, IDFQEMUDUT]: + for c in [ESP32DUT, ESP32S2DUT, ESP32S3DUT, ESP32C2DUT, ESP32C3DUT, ESP32C6DUT, ESP32H2DUT, ESP8266DUT, IDFQEMUDUT]: if c.get_rom() == cls: return c.TARGET return None diff --git a/tools/ci/python_packages/ttfw_idf/__init__.py b/tools/ci/python_packages/ttfw_idf/__init__.py index 8e48f4ad64..b3a3eac068 100644 --- a/tools/ci/python_packages/ttfw_idf/__init__.py +++ b/tools/ci/python_packages/ttfw_idf/__init__.py @@ -14,7 +14,7 @@ from tiny_test_fw import TinyFW, Utility from .IDFApp import UT, ComponentUTApp, Example, IDFApp, LoadableElfTestApp, TestApp # noqa: export all Apps for users from .IDFDUT import (ESP32C2DUT, ESP32C3DUT, ESP32C3FPGADUT, ESP32C6DUT, ESP32DUT, # noqa: export DUTs for users - ESP32H2DUT, ESP32H4DUT, ESP32QEMUDUT, ESP32S2DUT, ESP32S3DUT, ESP32S3FPGADUT, ESP8266DUT, IDFDUT) + ESP32H2DUT, ESP32QEMUDUT, ESP32S2DUT, ESP32S3DUT, ESP32S3FPGADUT, ESP8266DUT, IDFDUT) from .unity_test_parser import TestFormat, TestResults # pass TARGET_DUT_CLS_DICT to Env.py to avoid circular dependency issue. @@ -27,7 +27,6 @@ TARGET_DUT_CLS_DICT = { 'ESP32C3FPGA': ESP32C3FPGADUT, 'ESP32S3FPGA': ESP32S3FPGADUT, 'ESP32C6': ESP32C6DUT, - 'ESP32H4': ESP32H4DUT, 'ESP32H2': ESP32H2DUT, } diff --git a/tools/ci/test_build_system_cmake.sh b/tools/ci/test_build_system_cmake.sh index 4b8701f60c..a29a696f20 100755 --- a/tools/ci/test_build_system_cmake.sh +++ b/tools/ci/test_build_system_cmake.sh @@ -513,7 +513,7 @@ function run_tests() print_status "Test build ESP-IDF as a library to a custom CMake projects for all targets" IDF_AS_LIB=$IDF_PATH/examples/build_system/cmake/idf_as_lib # note: we just need to run cmake - for TARGET in "esp32" "esp32s2" "esp32s3" "esp32c3" "esp32h4" "esp32c2" "esp32c6" "esp32h2" + for TARGET in "esp32" "esp32s2" "esp32s3" "esp32c3" "esp32c2" "esp32c6" "esp32h2" do echo "Build idf_as_lib for $TARGET target" rm -rf build diff --git a/tools/cmake/dfu.cmake b/tools/cmake/dfu.cmake index 677d1c16f1..f1ecd940e9 100644 --- a/tools/cmake/dfu.cmake +++ b/tools/cmake/dfu.cmake @@ -11,8 +11,6 @@ function(__add_dfu_targets) set(dfu_pid "9") elseif("${target}" STREQUAL "esp32c3") return() - elseif("${target}" STREQUAL "esp32h4") - return() elseif("${target}" STREQUAL "esp32c2") return() elseif("${target}" STREQUAL "esp32c6") diff --git a/tools/cmake/toolchain-esp32h4.cmake b/tools/cmake/toolchain-esp32h4.cmake deleted file mode 100644 index 2eb3a62d64..0000000000 --- a/tools/cmake/toolchain-esp32h4.cmake +++ /dev/null @@ -1,18 +0,0 @@ -include($ENV{IDF_PATH}/tools/cmake/utilities.cmake) - -set(CMAKE_SYSTEM_NAME Generic) - -set(CMAKE_C_COMPILER riscv32-esp-elf-gcc) -set(CMAKE_CXX_COMPILER riscv32-esp-elf-g++) -set(CMAKE_ASM_COMPILER riscv32-esp-elf-gcc) -set(_CMAKE_TOOLCHAIN_PREFIX riscv32-esp-elf-) - -remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_C_FLAGS}" UNIQ_CMAKE_C_FLAGS) -set(CMAKE_C_FLAGS "${UNIQ_CMAKE_C_FLAGS}" CACHE STRING "C Compiler Base Flags" FORCE) -remove_duplicated_flags("-march=rv32imc_zicsr_zifencei ${CMAKE_CXX_FLAGS}" UNIQ_CMAKE_CXX_FLAGS) -set(CMAKE_CXX_FLAGS "${UNIQ_CMAKE_CXX_FLAGS}" CACHE STRING "C++ Compiler Base Flags" FORCE) - -remove_duplicated_flags("-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs \ - ${CMAKE_EXE_LINKER_FLAGS}" - UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS) -set(CMAKE_EXE_LINKER_FLAGS "${UNIQ_CMAKE_SAFE_EXE_LINKER_FLAGS}" CACHE STRING "Linker Base Flags" FORCE) diff --git a/tools/cmake/uf2.cmake b/tools/cmake/uf2.cmake index aa00d5df3c..4e80d8decf 100644 --- a/tools/cmake/uf2.cmake +++ b/tools/cmake/uf2.cmake @@ -12,8 +12,6 @@ function(__add_uf2_targets) set(uf2_family_id "0xc47e5767") elseif("${target}" STREQUAL "esp32h2") set(uf2_family_id "0x332726f6") - elseif("${target}" STREQUAL "esp32h4") - return() elseif("${target}" STREQUAL "esp32c2") set(uf2_family_id "0x2b88d29c") elseif("${target}" STREQUAL "esp32c6") # TODO: IDF-5626 diff --git a/tools/gdb_panic_server.py b/tools/gdb_panic_server.py index 4b5edf26ea..fc429dbe8d 100644 --- a/tools/gdb_panic_server.py +++ b/tools/gdb_panic_server.py @@ -59,7 +59,6 @@ GDB_REGS_INFO_RISCV_ILP32 = [ GDB_REGS_INFO = { 'esp32c3': GDB_REGS_INFO_RISCV_ILP32, 'esp32c2': GDB_REGS_INFO_RISCV_ILP32, - 'esp32h4': GDB_REGS_INFO_RISCV_ILP32, 'esp32c6': GDB_REGS_INFO_RISCV_ILP32, 'esp32h2': GDB_REGS_INFO_RISCV_ILP32 } @@ -155,7 +154,6 @@ def parse_idf_riscv_panic_output(panic_text): # type: (str) -> PanicInfo PANIC_OUTPUT_PARSERS = { 'esp32c3': parse_idf_riscv_panic_output, 'esp32c2': parse_idf_riscv_panic_output, - 'esp32h4': parse_idf_riscv_panic_output, 'esp32c6': parse_idf_riscv_panic_output, 'esp32h2': parse_idf_riscv_panic_output } diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py index 46344fbdb7..ebb7a789f6 100644 --- a/tools/idf_py_actions/constants.py +++ b/tools/idf_py_actions/constants.py @@ -33,7 +33,7 @@ if os.name != 'nt': URL_TO_DOC = 'https://docs.espressif.com/projects/esp-idf' SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32c2', 'esp32c6', 'esp32h2'] -PREVIEW_TARGETS = ['linux', 'esp32h4'] +PREVIEW_TARGETS = ['linux'] OPENOCD_TAGET_CONFIG_DEFAULT = '-f interface/ftdi/esp32_devkitj_v1.cfg -f target/{target}.cfg' OPENOCD_TAGET_CONFIG: Dict[str, str] = { diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml index 8c072cb103..449a56ce60 100644 --- a/tools/test_apps/.build-test-rules.yml +++ b/tools/test_apps/.build-test-rules.yml @@ -100,7 +100,7 @@ tools/test_apps/system/cxx_pthread_bluetooth: tools/test_apps/system/eh_frame: enable: - - if: IDF_TARGET in ["esp32c2", "esp32c3", "esp32h4"] + - if: IDF_TARGET in ["esp32c2", "esp32c3"] temporary: true reason: the other targets are not tested yet @@ -112,7 +112,7 @@ tools/test_apps/system/flash_psram: tools/test_apps/system/g0_components: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32h4", "esp32c6", "esp32h2"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32c6", "esp32h2"] # preview targets tools/test_apps/system/g1_components: @@ -160,7 +160,7 @@ tools/test_apps/system/no_embedded_paths: tools/test_apps/system/panic: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "esp32h4" + - if: INCLUDE_DEFAULT == 1 disable_test: - if: IDF_TARGET not in ["esp32", "esp32s2", "esp32c3", "esp32s3", "esp32c2", "esp32c6", "esp32h2"] temporary: true @@ -168,13 +168,13 @@ tools/test_apps/system/panic: tools/test_apps/system/ram_loadable_app: disable: - - if: IDF_TARGET == "esp32h2" or IDF_TARGET == "esp32h4" + - if: IDF_TARGET == "esp32h2" temporary: true reason: lack of runners tools/test_apps/system/startup: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32h4", "esp32c6"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32c6"] # preview targets tools/test_apps/system/test_watchpoint: enable: diff --git a/tools/test_apps/system/eh_frame/README.md b/tools/test_apps/system/eh_frame/README.md index 95fbea0c46..59a65262c1 100644 --- a/tools/test_apps/system/eh_frame/README.md +++ b/tools/test_apps/system/eh_frame/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-H4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | +| ----------------- | -------- | -------- | # Building and running @@ -10,7 +10,7 @@ Thus, as soon as this example compiles we can considered it passed. However, it In order to build and run the example, use the following commands: ``` -idf.py set-target +idf.py set-target idf.py build idf.py flash monitor ``` diff --git a/tools/test_apps/system/g0_components/README.md b/tools/test_apps/system/g0_components/README.md index 52129284e5..4ebccd4e3d 100644 --- a/tools/test_apps/system/g0_components/README.md +++ b/tools/test_apps/system/g0_components/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # "G0"-components-only app diff --git a/tools/test_apps/system/panic/README.md b/tools/test_apps/system/panic/README.md index 9720983ce6..693fbda6da 100644 --- a/tools/test_apps/system/panic/README.md +++ b/tools/test_apps/system/panic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Introduction diff --git a/tools/test_apps/system/startup/README.md b/tools/test_apps/system/startup/README.md index 30cd8e3cef..a8b7833fa3 100644 --- a/tools/test_apps/system/startup/README.md +++ b/tools/test_apps/system/startup/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/tools/test_build_system/test_cmake.py b/tools/test_build_system/test_cmake.py index d7af9500c1..c3d965d6f9 100644 --- a/tools/test_build_system/test_cmake.py +++ b/tools/test_build_system/test_cmake.py @@ -10,7 +10,7 @@ from test_build_system_helpers import IdfPyFunc, file_contains, run_cmake, run_c def test_build_custom_cmake_project(test_app_copy: Path) -> None: - for target in ['esp32', 'esp32s3', 'esp32c6', 'esp32h4']: + for target in ['esp32', 'esp32s3', 'esp32c6', 'esp32h2']: logging.info(f'Test build ESP-IDF as a library to a custom CMake projects for {target}') idf_path = Path(os.environ['IDF_PATH']) run_cmake_and_build(str(idf_path / 'examples' / 'build_system' / 'cmake' / 'idf_as_lib'), diff --git a/tools/tools.json b/tools/tools.json index 5a52e4492f..9623dc872d 100644 --- a/tools/tools.json +++ b/tools/tools.json @@ -92,8 +92,7 @@ "esp32c3", "esp32c2", "esp32c6", - "esp32h2", - "esp32h4" + "esp32h2" ], "version_cmd": [ "riscv32-esp-elf-gdb-no-python", @@ -389,7 +388,6 @@ "esp32s2", "esp32s3", "esp32c3", - "esp32h4", "esp32c2", "esp32c6", "esp32h2" @@ -454,7 +452,6 @@ "esp32s2", "esp32s3", "esp32c3", - "esp32h4", "esp32c2", "esp32c6", "esp32h2"