diff --git a/components/esp_system/include/esp_private/system_internal.h b/components/esp_system/include/esp_private/system_internal.h index 6851a3fc85..6d9cf54e9b 100644 --- a/components/esp_system/include/esp_private/system_internal.h +++ b/components/esp_system/include/esp_private/system_internal.h @@ -84,6 +84,11 @@ int64_t esp_system_get_time(void); */ uint32_t esp_system_get_time_resolution(void); +/** + * @brief Before the system exit (e.g. panic, brownout, restart, etc.), this function is to be called to reset all necessary peripherals. + */ +void esp_system_reset_modules_on_exit(void); + #ifdef __cplusplus } #endif diff --git a/components/esp_system/panic.c b/components/esp_system/panic.c index 4403fcfaba..f320c28dca 100644 --- a/components/esp_system/panic.c +++ b/components/esp_system/panic.c @@ -400,6 +400,7 @@ void esp_panic_handler(panic_info_t *info) #else disable_all_wdts(); panic_print_str("CPU halted.\r\n"); + esp_system_reset_modules_on_exit(); while (1); #endif /* CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT || CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT */ #endif /* CONFIG_ESP_SYSTEM_PANIC_GDBSTUB */ diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c index 1aa19f934a..8e7041d782 100644 --- a/components/esp_system/port/soc/esp32/system_internal.c +++ b/components/esp_system/port/soc/esp32/system_internal.c @@ -28,6 +28,29 @@ #include "esp32/rom/cache.h" #include "esp32/rom/rtc.h" +void IRAM_ATTR esp_system_reset_modules_on_exit(void) +{ + // Flush any data left in UART FIFOs before reset the UART peripheral + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + // Reset wifi/bluetooth/ethernet/sdio (bb/mac) + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, + DPORT_WIFIBB_RST | DPORT_FE_RST | DPORT_WIFIMAC_RST | DPORT_BTBB_RST | + DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | + DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); + + // Reset timer, spi, uart, mcpwm + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, + //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here. + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | + DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | + DPORT_UART_MEM_RST | DPORT_PWM0_RST | DPORT_PWM1_RST); + DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); +} + /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. @@ -72,11 +95,6 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY if (esp_ptr_external_ram(esp_cpu_get_sp())) { // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used) @@ -100,25 +118,8 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \ - DPORT_FE_RST | \ - DPORT_WIFIMAC_RST | \ - DPORT_BTBB_RST | \ - DPORT_BTMAC_RST | \ - DPORT_SDIO_RST | \ - DPORT_SDIO_HOST_RST | \ - DPORT_EMAC_RST | \ - DPORT_MACPWR_RST | \ - DPORT_RW_BTMAC_RST | \ - DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - // Reset timer/spi/uart - DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, - //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here. - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); + // reset necessary peripheral modules + esp_system_reset_modules_on_exit(); // Set CPU back to XTAL source, no PLL, same as hard reset rtc_clk_cpu_freq_set_xtal(); @@ -138,7 +139,7 @@ void IRAM_ATTR esp_restart_noos(void) esp_cpu_unstall(0); esp_cpu_reset(1); } - while(true) { + while (true) { ; } } diff --git a/components/esp_system/port/soc/esp32c2/system_internal.c b/components/esp_system/port/soc/esp32c2/system_internal.c index f14e225df4..d0624212ad 100644 --- a/components/esp_system/port/soc/esp32c2/system_internal.c +++ b/components/esp_system/port/soc/esp32c2/system_internal.c @@ -27,6 +27,25 @@ #include "esp32c2/rom/cache.h" #include "esp32c2/rom/rtc.h" +void IRAM_ATTR esp_system_reset_modules_on_exit(void) +{ + // Flush any data left in UART FIFOs before reset the UART peripheral + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + + // Reset wifi/bluetooth/ethernet/sdio (bb/mac) + + REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + // Reset timer/spi/uart + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, + SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + // Reset dma + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); +} + /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. @@ -63,9 +82,6 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt0_context); wdt_hal_write_protect_enable(&wdt0_context); - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); // Disable cache Cache_Disable_ICache(); @@ -78,17 +94,7 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - // Reset timer/spi/uart - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - // Reset dma - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + esp_system_reset_modules_on_exit(); // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA diff --git a/components/esp_system/port/soc/esp32c3/system_internal.c b/components/esp_system/port/soc/esp32c3/system_internal.c index f5ca5ddda0..f3a923b5a3 100644 --- a/components/esp_system/port/soc/esp32c3/system_internal.c +++ b/components/esp_system/port/soc/esp32c3/system_internal.c @@ -28,6 +28,32 @@ #include "esp32c3/rom/cache.h" #include "esp32c3/rom/rtc.h" +void IRAM_ATTR esp_system_reset_modules_on_exit(void) +{ + // Flush any data left in UART FIFOs before reset the UART peripheral + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + + // Reset wifi/bluetooth/ethernet/sdio (bb/mac) + SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, + SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | SYSTEM_SDIO_RST | + SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | + SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); + REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + // Reset uart0 core first, then reset apb side. + // rom will clear this bit, as well as SYSTEM_UART_RST + SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M); + + // Reset timer/spi/uart + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, + SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + // Reset dma + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); +} + /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. @@ -69,9 +95,6 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); // Disable cache Cache_Disable_ICache(); @@ -84,25 +107,7 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | - SYSTEM_SDIO_RST | SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | - SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | - SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - // Reset uart0 core first, then reset apb side. - // rom will clear this bit, as well as SYSTEM_UART_RST - SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M); - - // Reset timer/spi/uart - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - // Reset dma - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + esp_system_reset_modules_on_exit(); // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index a7dd7548f3..e214b9c0d1 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -27,6 +27,29 @@ #include "esp32h2/rom/cache.h" #include "esp32h2/rom/rtc.h" +void IRAM_ATTR esp_system_reset_modules_on_exit(void) +{ + // Flush any data left in UART FIFOs before reset the UART peripheral + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + + // Reset timer/spi/uart + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, + SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, + SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST | + SYSTEM_BT_RST | SYSTEM_BTMAC_RST | + SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | + SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST + ); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0); + + // Reset dma + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); +} + /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. @@ -68,9 +91,6 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); // Disable cache Cache_Disable_ICache(); @@ -83,22 +103,6 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - // Reset timer/spi/uart - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG, - SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST | - SYSTEM_BT_RST | SYSTEM_BTMAC_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | - SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST - ); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0); - - // Reset dma - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_freq_set_xtal(); diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c index 1ed1bc363e..ac23b175f0 100644 --- a/components/esp_system/port/soc/esp32s2/system_internal.c +++ b/components/esp_system/port/soc/esp32s2/system_internal.c @@ -31,6 +31,26 @@ extern int _bss_end; +void IRAM_ATTR esp_system_reset_modules_on_exit(void) +{ + // Flush any data left in UART FIFOs before reset the UART peripheral + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + + // Reset wifi/bluetooth/ethernet/sdio (bb/mac) + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, + DPORT_WIFIBB_RST | DPORT_FE_RST | DPORT_WIFIMAC_RST | DPORT_BTBB_RST | + DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | + DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); + + // Reset timer/spi/uart + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | + DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST); + DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); +} + /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. @@ -69,10 +89,6 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY if (esp_ptr_external_ram(esp_cpu_get_sp())) { // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used) @@ -96,23 +112,7 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \ - DPORT_FE_RST | \ - DPORT_WIFIMAC_RST | \ - DPORT_BTBB_RST | \ - DPORT_BTMAC_RST | \ - DPORT_SDIO_RST | \ - DPORT_EMAC_RST | \ - DPORT_MACPWR_RST | \ - DPORT_RW_BTMAC_RST | \ - DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - // Reset timer/spi/uart - DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); + esp_system_reset_modules_on_exit(); // Set CPU back to XTAL source, no PLL, same as hard reset rtc_clk_cpu_freq_set_xtal(); diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index 8af34f401d..6e5a0531aa 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -31,6 +31,34 @@ extern int _bss_end; +void IRAM_ATTR esp_system_reset_modules_on_exit(void) +{ + // Flush any data left in UART FIFOs before reset the UART peripheral + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + // Reset wifi/bluetooth/ethernet/sdio (bb/mac) + SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, + SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | SYSTEM_SDIO_RST | + SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | + SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); + REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + // Reset timer, systimer, spi, uart, mcpwm + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, + SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST | + SYSTEM_PWM0_RST | SYSTEM_PWM1_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + + // Reset dma + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + + SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); +} + /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. @@ -63,10 +91,6 @@ void IRAM_ATTR esp_restart_noos(void) wdt_hal_disable(&wdt1_context); wdt_hal_write_protect_enable(&wdt1_context); - // Flush any data left in UART FIFOs - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY if (esp_ptr_external_ram(esp_cpu_get_sp())) { // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used) @@ -101,25 +125,8 @@ void IRAM_ATTR esp_restart_noos(void) WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | - SYSTEM_SDIO_RST | SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | - SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | - SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - // Reset timer/spi/uart - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, - SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - // Reset dma - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + // reset necessary peripheral modules + esp_system_reset_modules_on_exit(); // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA