espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2026-05-04 20:05:25 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'doc/apply_wavedrom_extension' into 'master'

Browse Source 
doc: apply wavedrom extension

See merge request espressif/esp-idf!17964
This commit is contained in:
morris
2022-05-05 11:01:41 +08:00
parent a01a5dec4a dce0993ce5
commit 8588734a22
11 changed files with 124 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files
docs/en/api-reference/peripherals/spi_master.rst
+1 -3
View File
@@ -509,9 +509,7 @@ Please note that the ISR is disabled during flash operation by default. To keep
:scale: 40 %
:align: center
.. wavedrom does not support rendering pdflatex till now(1.3.1), so we use the png here
.. image:: /../_static/miso_timing_waveform.png
.. wavedrom:: /../_static/diagrams/spi/miso_timing_waveform.json
The maximum allowed frequency is dependent on:
docs/en/api-reference/peripherals/spi_slave.rst
+1 -1
View File
@@ -201,7 +201,7 @@ Restrictions and Known Issues
2. Furthermore, DMA requires SPI modes 1 and 3. For SPI modes 0 and 2, the MISO signal has to be launched half a clock cycle earlier to meet the timing. The new timing is as follows:
.. image:: /../_static/spi_slave_miso_dma.png
.. wavedrom:: /../_static/diagrams/spi/spi_slave_miso_dma.json
If DMA is enabled, a Device's launch edge is half of an SPI clock cycle ahead of the normal time, shifting to the Master's actual latch edge. In this case, if the GPIO matrix is bypassed, the hold time for data sampling is 68.75 ns and no longer a half of an SPI clock cycle. If the GPIO matrix is used, the hold time will increase to 93.75 ns. The Host should sample the data immediately at the latch edge or communicate in SPI modes 1 or 3. If your Host cannot meet these timing requirements, initialize your Device without DMA.