espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-07-31 19:24:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/flash_1v8_enable_vddsdio_reg' into 'master'

Browse Source 
bootloader: Only apply VDDSDIO 1.8V->1.9V if regulator is enabled

See merge request !1601
This commit is contained in:
Jiang Jiang Jian
2017-12-01 19:34:45 +08:00
parent 96cd6f8626 fccc30d2d5
commit 85fc06e3bb
2 changed files with 5 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
components/bootloader/Kconfig.projbuild
View File

@@ -44,14 +44,16 @@ config BOOTLOADER_SPI_WP_PIN
The default value (GPIO 7) is correct for WP pin on ESP32-D2WD integrated flash. The default value (GPIO 7) is correct for WP pin on ESP32-D2WD integrated flash.
config BOOTLOADER_VDDSDIO_BOOST config BOOTLOADER_VDDSDIO_BOOST
bool "Increase VDDSDIO LDO voltage to 1.9V" bool "Increase VDDSDIO 1.8V LDO voltage to 1.9V"
default y default y
help help
If this option is enabled, and VDDSDIO LDO is set to 1.8V (using EFUSE If this option is enabled, and VDDSDIO LDO is set to 1.8V (using EFUSE
or MTDI bootstrapping pin), bootloader will change LDO settings to or MTDI bootstrapping pin), bootloader will change LDO settings to
output 1.9V instead. This helps prevent flash chip from browning out output 1.9V instead. This helps prevent flash chip from browning out
during flash programming operations. during flash programming operations.
For 3.3V flash, this option has no effect.
This option has no effect if VDDSDIO is set to 3.3V, or if the internal
VDDSDIO regulator is disabled via efuse.
endmenu # Bootloader endmenu # Bootloader

3
components/bootloader/subproject/main/bootloader_start.c
View File

@@ -745,12 +745,11 @@ static void vddsdio_configure()
{ {
#if CONFIG_BOOTLOADER_VDDSDIO_BOOST #if CONFIG_BOOTLOADER_VDDSDIO_BOOST
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config(); rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
if (cfg.tieh == 0) { // 1.8V is used if (cfg.enable == 1 && cfg.tieh == 0) { // VDDSDIO regulator is enabled @ 1.8V
cfg.drefh = 3; cfg.drefh = 3;
cfg.drefm = 3; cfg.drefm = 3;
cfg.drefl = 3; cfg.drefl = 3;
cfg.force = 1; cfg.force = 1;
cfg.enable = 1;
rtc_vddsdio_set_config(cfg); rtc_vddsdio_set_config(cfg);
ets_delay_us(10); // wait for regulator to become stable ets_delay_us(10); // wait for regulator to become stable
} }