From 872c42ecf72d12ff28e4680df78c3bb6546dd20f Mon Sep 17 00:00:00 2001 From: Yuriy Shestakov Date: Wed, 18 Aug 2021 23:12:01 +0300 Subject: [PATCH] Fixed GLITCH_RTC_RST for esp32-c3 revision 3 * Issue: https://github.com/espressif/esp-idf/issues/7082 Signed-off-by: Yuriy Shestakov Closes https://github.com/espressif/esp-idf/issues/7082 Closes https://github.com/espressif/esp-idf/pull/7441 --- components/bootloader_support/src/esp32c3/bootloader_esp32c3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 8dcd995e62..f120e770c8 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -282,7 +282,8 @@ static inline void bootloader_glitch_reset_disable(void) uint8_t chip_version = bootloader_common_get_chip_revision(); if (chip_version < 2) { REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); - } else if (chip_version == 2) { + } else { + // checked on ESP32-C3 revisions 2 and 3 REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST); } }