mirror of
https://github.com/espressif/esp-idf.git
synced 2026-05-04 11:55:21 +02:00
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one
update all struct headers to be more "standardized":
- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199
added helper macros to force peripheral registers being accessed in 32 bitwidth
added a check script into ci
This commit is contained in:
SalimTerryLi
@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct apb_ctrl_dev_s {
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union {
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struct {
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uint32_t pre_div : 10;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct apb_saradc_dev_s {
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union {
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struct {
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uint32_t start_force : 1;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct assist_debug_dev_s {
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd : 1;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct efuse_dev_s {
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uint32_t pgm_data0;
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uint32_t pgm_data1;
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uint32_t pgm_data2;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct extmem_dev_s {
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union {
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struct {
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uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct gdma_dev_s {
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struct {
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struct {
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union {
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct gpio_sd_dev_s {
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union {
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struct {
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uint32_t duty : 8;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct gpio_dev_s {
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uint32_t bt_select;
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uint32_t out;
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uint32_t out_w1ts;
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@@ -20,7 +20,7 @@ extern "C" {
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#include <stdint.h>
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typedef volatile struct {
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typedef volatile struct hinf_dev_s {
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union {
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struct {
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uint32_t user_id_fn1: 16;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct host_dev_s {
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uint32_t reserved_0;
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uint32_t reserved_4;
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uint32_t reserved_8;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct i2s_dev_s {
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uint32_t reserved_0;
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uint32_t reserved_4;
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uint32_t reserved_8;
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@@ -18,7 +18,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct interrupt_core0_dev_s {
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union {
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struct {
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uint32_t core0_mac_intr_map: 5;
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@@ -18,7 +18,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct interrupt_core1_dev_s {
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uint32_t reserved_0;
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uint32_t reserved_4;
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uint32_t reserved_8;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct interrupt_dev_s {
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} interrupt_dev_t;
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extern interrupt_dev_t INTERRUPT;
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#ifdef __cplusplus
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@@ -20,7 +20,7 @@ extern "C" {
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#include <stdint.h>
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typedef volatile struct {
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typedef volatile struct ledc_dev_s {
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struct {
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struct {
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union {
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct peri_backup_dev_s {
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union {
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struct {
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uint32_t reg_peri_backup_flow_err : 3;
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@@ -1103,9 +1103,7 @@ typedef struct {
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typedef struct {
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struct {
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union {
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volatile rmt_item32_t data32[48];
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};
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volatile rmt_item32_t data32[48];
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} chan[8];
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} rmt_mem_t;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct rtc_cntl_dev_s {
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union {
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struct {
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uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct rtc_io_dev_s {
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union {
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struct {
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uint32_t reserved0 : 10;
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@@ -21,18 +21,22 @@ extern "C" {
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#endif
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typedef struct sdmmc_desc_s {
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uint32_t reserved1: 1;
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uint32_t disable_int_on_completion: 1;
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uint32_t last_descriptor: 1;
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uint32_t first_descriptor: 1;
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uint32_t second_address_chained: 1;
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uint32_t end_of_ring: 1;
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uint32_t reserved2: 24;
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uint32_t card_error_summary: 1;
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uint32_t owned_by_idmac: 1;
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uint32_t buffer1_size: 13;
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uint32_t buffer2_size: 13;
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uint32_t reserved3: 6;
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struct {
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uint32_t reserved1: 1;
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uint32_t disable_int_on_completion: 1;
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uint32_t last_descriptor: 1;
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uint32_t first_descriptor: 1;
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uint32_t second_address_chained: 1;
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uint32_t end_of_ring: 1;
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uint32_t reserved2: 24;
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uint32_t card_error_summary: 1;
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uint32_t owned_by_idmac: 1;
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};
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struct {
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uint32_t buffer1_size: 13;
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uint32_t buffer2_size: 13;
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uint32_t reserved3: 6;
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};
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void* buffer1_ptr;
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union {
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void* buffer2_ptr;
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@@ -144,8 +148,10 @@ typedef volatile struct sdmmc_dev_s {
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uint32_t val;
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} ctype;
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uint32_t blksiz: 16; ///< block size, default 0x200
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uint32_t : 16;
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struct {
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uint32_t blksiz: 16; ///< block size, default 0x200
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uint32_t reserved: 16;
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};
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uint32_t bytcnt; ///< number of bytes to be transferred
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@@ -324,6 +330,7 @@ typedef volatile struct sdmmc_dev_s {
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uint32_t ces: 1; ///< card error summary
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uint32_t reserved2: 2;
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uint32_t nis: 1; ///< normal interrupt summary
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uint32_t ais: 1; ///< abnormal interrupt summary
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uint32_t fbe_code: 3; ///< code of fatal bus error
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uint32_t fsm: 4; ///< DMAC FSM state
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uint32_t reserved3: 15;
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@@ -359,7 +366,7 @@ typedef volatile struct sdmmc_dev_s {
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uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts
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uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
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uint32_t reserved1 : 13;
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uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
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uint32_t card_threshold : 16; ///< threshold value for reads/writes, in bytes
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};
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uint32_t val;
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} cardthrctl;
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@@ -378,6 +385,7 @@ typedef volatile struct sdmmc_dev_s {
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uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
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uint32_t reserved1 : 2;
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uint32_t clk_sel : 1; ///< clock source select (0: XTAL, 1: 160 MHz from PLL)
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} clock;
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct sens_dev_s {
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union {
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struct {
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uint32_t sar1_clk_div : 8; /*clock divider*/
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@@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct sensitive_dev_s {
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union {
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struct {
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uint32_t cache_dataarray_connect_lock : 1;
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File diff suppressed because it is too large
Load Diff
@@ -1,592 +0,0 @@
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// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_SLC_STRUCT_H_
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#define _SOC_SLC_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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union {
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struct {
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uint32_t tx_rst : 1;
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uint32_t rx_rst : 1;
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uint32_t ahbm_fifo_rst : 1;
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uint32_t ahbm_rst : 1;
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uint32_t tx_loop_test : 1;
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uint32_t rx_loop_test : 1;
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uint32_t rx_auto_wrback : 1;
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uint32_t rx_no_restart_clr : 1;
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uint32_t rxdscr_burst_en : 1;
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uint32_t rxdata_burst_en : 1;
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uint32_t auto_ret : 1;
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uint32_t txdscr_burst_en : 1;
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uint32_t txdata_burst_en : 1;
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uint32_t token_auto_clr : 1;
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uint32_t token_sel : 1;
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uint32_t reserved16 : 2;
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uint32_t wr_retry_mask_en : 1;
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uint32_t reserved19 : 13;
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};
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uint32_t val;
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} slcconf0;
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union {
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struct {
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uint32_t frhost_bit0 : 1;
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uint32_t frhost_bit1 : 1;
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uint32_t frhost_bit2 : 1;
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uint32_t frhost_bit3 : 1;
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uint32_t frhost_bit4 : 1;
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uint32_t frhost_bit5 : 1;
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uint32_t frhost_bit6 : 1;
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uint32_t frhost_bit7 : 1;
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uint32_t rx_start : 1;
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uint32_t tx_start : 1;
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uint32_t rx_udf : 1;
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uint32_t tx_ovf : 1;
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uint32_t token0_1to0 : 1;
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uint32_t token1_1to0 : 1;
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uint32_t tx_done : 1;
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uint32_t tx_suc_eof : 1;
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uint32_t rx_done : 1;
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uint32_t rx_eof : 1;
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uint32_t tohost : 1;
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uint32_t tx_dscr_err : 1;
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uint32_t rx_dscr_err : 1;
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uint32_t tx_dscr_empty : 1;
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uint32_t host_rd_ack : 1;
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uint32_t wr_retry_done : 1;
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uint32_t tx_err_eof : 1;
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uint32_t cmd_dtc : 1;
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uint32_t rx_quick_eof : 1;
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uint32_t host_pop_eof_err : 1;
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uint32_t reserved28 : 4;
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};
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uint32_t val;
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} slc0_int_raw;
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union {
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struct {
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uint32_t frhost_bit0 : 1;
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uint32_t frhost_bit1 : 1;
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uint32_t frhost_bit2 : 1;
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uint32_t frhost_bit3 : 1;
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uint32_t frhost_bit4 : 1;
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uint32_t frhost_bit5 : 1;
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uint32_t frhost_bit6 : 1;
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uint32_t frhost_bit7 : 1;
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uint32_t rx_start : 1;
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uint32_t tx_start : 1;
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uint32_t rx_udf : 1;
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uint32_t tx_ovf : 1;
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uint32_t token0_1to0 : 1;
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uint32_t token1_1to0 : 1;
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uint32_t tx_done : 1;
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uint32_t tx_suc_eof : 1;
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uint32_t rx_done : 1;
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uint32_t rx_eof : 1;
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uint32_t tohost : 1;
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uint32_t tx_dscr_err : 1;
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uint32_t rx_dscr_err : 1;
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uint32_t tx_dscr_empty : 1;
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uint32_t host_rd_ack : 1;
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uint32_t wr_retry_done : 1;
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uint32_t tx_err_eof : 1;
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uint32_t cmd_dtc : 1;
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uint32_t rx_quick_eof : 1;
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uint32_t host_pop_eof_err : 1;
|
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uint32_t reserved28 : 4;
|
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};
|
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uint32_t val;
|
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} slc0_int_st;
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union {
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struct {
|
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uint32_t frhost_bit0 : 1;
|
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uint32_t frhost_bit1 : 1;
|
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uint32_t frhost_bit2 : 1;
|
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uint32_t frhost_bit3 : 1;
|
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uint32_t frhost_bit4 : 1;
|
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uint32_t frhost_bit5 : 1;
|
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uint32_t frhost_bit6 : 1;
|
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uint32_t frhost_bit7 : 1;
|
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uint32_t rx_start : 1;
|
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uint32_t tx_start : 1;
|
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uint32_t rx_udf : 1;
|
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uint32_t tx_ovf : 1;
|
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uint32_t token0_1to0 : 1;
|
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uint32_t token1_1to0 : 1;
|
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uint32_t tx_done : 1;
|
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uint32_t tx_suc_eof : 1;
|
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uint32_t rx_done : 1;
|
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uint32_t rx_eof : 1;
|
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uint32_t tohost : 1;
|
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uint32_t tx_dscr_err : 1;
|
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uint32_t rx_dscr_err : 1;
|
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uint32_t tx_dscr_empty : 1;
|
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uint32_t host_rd_ack : 1;
|
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uint32_t wr_retry_done : 1;
|
||||
uint32_t tx_err_eof : 1;
|
||||
uint32_t cmd_dtc : 1;
|
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uint32_t rx_quick_eof : 1;
|
||||
uint32_t host_pop_eof_err : 1;
|
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uint32_t reserved28 : 4;
|
||||
};
|
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uint32_t val;
|
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} slc0_int_ena;
|
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union {
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struct {
|
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uint32_t frhost_bit0 : 1;
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uint32_t frhost_bit1 : 1;
|
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uint32_t frhost_bit2 : 1;
|
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uint32_t frhost_bit3 : 1;
|
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uint32_t frhost_bit4 : 1;
|
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uint32_t frhost_bit5 : 1;
|
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uint32_t frhost_bit6 : 1;
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uint32_t frhost_bit7 : 1;
|
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uint32_t rx_start : 1;
|
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uint32_t tx_start : 1;
|
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uint32_t rx_udf : 1;
|
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uint32_t tx_ovf : 1;
|
||||
uint32_t token0_1to0 : 1;
|
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uint32_t token1_1to0 : 1;
|
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uint32_t tx_done : 1;
|
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uint32_t tx_suc_eof : 1;
|
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uint32_t rx_done : 1;
|
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uint32_t rx_eof : 1;
|
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uint32_t tohost : 1;
|
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uint32_t tx_dscr_err : 1;
|
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uint32_t rx_dscr_err : 1;
|
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uint32_t tx_dscr_empty : 1;
|
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uint32_t host_rd_ack : 1;
|
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uint32_t wr_retry_done : 1;
|
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uint32_t tx_err_eof : 1;
|
||||
uint32_t cmd_dtc : 1;
|
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uint32_t rx_quick_eof : 1;
|
||||
uint32_t host_pop_eof_err : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_clr;
|
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uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
uint32_t reserved_20;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_full : 1;
|
||||
uint32_t rx_empty : 1;
|
||||
uint32_t rx_buf_len : 12;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_wdata : 9;
|
||||
uint32_t reserved9 : 7;
|
||||
uint32_t rxfifo_push : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rxfifo_push;
|
||||
uint32_t reserved_2c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_full : 1;
|
||||
uint32_t tx_empty : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txfifo_rdata : 11;
|
||||
uint32_t reserved11 : 5;
|
||||
uint32_t txfifo_pop : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_txfifo_pop;
|
||||
uint32_t reserved_38;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr : 20;
|
||||
uint32_t reserved20 : 8;
|
||||
uint32_t stop : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t restart : 1;
|
||||
uint32_t park : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rx_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr : 20;
|
||||
uint32_t reserved20 : 8;
|
||||
uint32_t stop : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t restart : 1;
|
||||
uint32_t park : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_tx_link;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_intvec : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} slcintvec_tohost;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata : 12;
|
||||
uint32_t wr : 1;
|
||||
uint32_t inc : 1;
|
||||
uint32_t inc_more : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t token0 : 12;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0token0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata : 12;
|
||||
uint32_t wr : 1;
|
||||
uint32_t inc : 1;
|
||||
uint32_t inc_more : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t token1 : 12;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token1;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t check_owner : 1;
|
||||
uint32_t tx_check_sum_en : 1;
|
||||
uint32_t rx_check_sum_en : 1;
|
||||
uint32_t reg_cmd_hold_en : 1;
|
||||
uint32_t len_auto_clr : 1;
|
||||
uint32_t tx_stitch_en : 1;
|
||||
uint32_t rx_stitch_en : 1;
|
||||
uint32_t reserved7 : 12;
|
||||
uint32_t host_int_level_sel : 1;
|
||||
uint32_t reserved20 : 2;
|
||||
uint32_t reg_clk_en : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} slcconf1;
|
||||
uint32_t slc0_state0;
|
||||
uint32_t slc0_state1;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txeof_ena : 6;
|
||||
uint32_t reserved6 : 2;
|
||||
uint32_t fifo_map_ena : 4;
|
||||
uint32_t tx_dummy_mode : 1;
|
||||
uint32_t hda_map_128k : 1;
|
||||
uint32_t reserved14 : 2;
|
||||
uint32_t tx_push_idle_num : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} slcbridge_conf;
|
||||
uint32_t slc0_to_eof_des_addr;
|
||||
uint32_t slc0_tx_eof_des_addr;
|
||||
uint32_t slc0_to_eof_bfr_des_addr;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mode : 3;
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t addr : 2;
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} ahb_test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmd_st : 3;
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t func_st : 4;
|
||||
uint32_t sdio_wakeup : 1;
|
||||
uint32_t reserved9 : 3;
|
||||
uint32_t bus_st : 3;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t func1_acc_state : 5;
|
||||
uint32_t reserved21 : 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token_no_replace : 1;
|
||||
uint32_t infor_no_replace : 1;
|
||||
uint32_t rx_fill_mode : 1;
|
||||
uint32_t rx_eof_mode : 1;
|
||||
uint32_t rx_fill_en : 1;
|
||||
uint32_t rd_retry_threshold : 11;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_dscr_conf;
|
||||
uint32_t slc0_txlink_dscr;
|
||||
uint32_t slc0_txlink_dscr_bf0;
|
||||
uint32_t slc0_txlink_dscr_bf1;
|
||||
uint32_t slc0_rxlink_dscr;
|
||||
uint32_t slc0_rxlink_dscr_bf0;
|
||||
uint32_t slc0_rxlink_dscr_bf1;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t slc0_tx_erreof_des_addr;
|
||||
uint32_t reserved_d0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token : 12;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} token_lat;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wr_retry_threshold : 11;
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_dscr_conf;
|
||||
uint32_t cmd_infor0;
|
||||
uint32_t cmd_infor1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len_wdata : 20;
|
||||
uint32_t len_wr : 1;
|
||||
uint32_t len_inc : 1;
|
||||
uint32_t len_inc_more : 1;
|
||||
uint32_t rx_packet_load_en : 1;
|
||||
uint32_t tx_packet_load_en : 1;
|
||||
uint32_t rx_get_used_dscr : 1;
|
||||
uint32_t tx_get_used_dscr : 1;
|
||||
uint32_t rx_new_pkt_ind : 1;
|
||||
uint32_t tx_new_pkt_ind : 1;
|
||||
uint32_t reserved29 : 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_len_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len : 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_length;
|
||||
uint32_t slc0_txpkt_h_dscr;
|
||||
uint32_t slc0_txpkt_e_dscr;
|
||||
uint32_t slc0_rxpkt_h_dscr;
|
||||
uint32_t slc0_rxpkt_e_dscr;
|
||||
uint32_t slc0_txpktu_h_dscr;
|
||||
uint32_t slc0_txpktu_e_dscr;
|
||||
uint32_t slc0_rxpktu_h_dscr;
|
||||
uint32_t slc0_rxpktu_e_dscr;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq_position : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} seq_position;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_dscr_rec_lim : 10;
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_dscr_rec_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dat0_crc_err_cnt : 8;
|
||||
uint32_t dat1_crc_err_cnt : 8;
|
||||
uint32_t dat2_crc_err_cnt : 8;
|
||||
uint32_t dat3_crc_err_cnt : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_crc_st0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmd_crc_err_cnt : 8;
|
||||
uint32_t reserved8 : 23;
|
||||
uint32_t err_cnt_clr : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_crc_st1;
|
||||
uint32_t slc0_eof_start_des;
|
||||
uint32_t slc0_push_dscr_addr;
|
||||
uint32_t slc0_done_dscr_addr;
|
||||
uint32_t slc0_sub_start_des;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_dscr_cnt_lat : 10;
|
||||
uint32_t reserved10 : 6;
|
||||
uint32_t rx_get_eof_occ : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_dscr_cnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len_lim : 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_len_lim_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit01 : 1;
|
||||
uint32_t frhost_bit11 : 1;
|
||||
uint32_t frhost_bit21 : 1;
|
||||
uint32_t frhost_bit31 : 1;
|
||||
uint32_t frhost_bit41 : 1;
|
||||
uint32_t frhost_bit51 : 1;
|
||||
uint32_t frhost_bit61 : 1;
|
||||
uint32_t frhost_bit71 : 1;
|
||||
uint32_t rx_start1 : 1;
|
||||
uint32_t tx_start1 : 1;
|
||||
uint32_t rx_udf1 : 1;
|
||||
uint32_t tx_ovf1 : 1;
|
||||
uint32_t token0_1to01 : 1;
|
||||
uint32_t token1_1to01 : 1;
|
||||
uint32_t tx_done1 : 1;
|
||||
uint32_t tx_suc_eof1 : 1;
|
||||
uint32_t rx_done1 : 1;
|
||||
uint32_t rx_eof1 : 1;
|
||||
uint32_t tohost1 : 1;
|
||||
uint32_t tx_dscr_err1 : 1;
|
||||
uint32_t rx_dscr_err1 : 1;
|
||||
uint32_t tx_dscr_empty1 : 1;
|
||||
uint32_t host_rd_ack1 : 1;
|
||||
uint32_t wr_retry_done1 : 1;
|
||||
uint32_t tx_err_eof1 : 1;
|
||||
uint32_t cmd_dtc1 : 1;
|
||||
uint32_t rx_quick_eof1 : 1;
|
||||
uint32_t host_pop_eof_err1 : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit01 : 1;
|
||||
uint32_t frhost_bit11 : 1;
|
||||
uint32_t frhost_bit21 : 1;
|
||||
uint32_t frhost_bit31 : 1;
|
||||
uint32_t frhost_bit41 : 1;
|
||||
uint32_t frhost_bit51 : 1;
|
||||
uint32_t frhost_bit61 : 1;
|
||||
uint32_t frhost_bit71 : 1;
|
||||
uint32_t rx_start1 : 1;
|
||||
uint32_t tx_start1 : 1;
|
||||
uint32_t rx_udf1 : 1;
|
||||
uint32_t tx_ovf1 : 1;
|
||||
uint32_t token0_1to01 : 1;
|
||||
uint32_t token1_1to01 : 1;
|
||||
uint32_t tx_done1 : 1;
|
||||
uint32_t tx_suc_eof1 : 1;
|
||||
uint32_t rx_done1 : 1;
|
||||
uint32_t rx_eof1 : 1;
|
||||
uint32_t tohost1 : 1;
|
||||
uint32_t tx_dscr_err1 : 1;
|
||||
uint32_t rx_dscr_err1 : 1;
|
||||
uint32_t tx_dscr_empty1 : 1;
|
||||
uint32_t host_rd_ack1 : 1;
|
||||
uint32_t wr_retry_done1 : 1;
|
||||
uint32_t tx_err_eof1 : 1;
|
||||
uint32_t cmd_dtc1 : 1;
|
||||
uint32_t rx_quick_eof1 : 1;
|
||||
uint32_t host_pop_eof_err1 : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena1;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t date;
|
||||
uint32_t id;
|
||||
} slc_dev_t;
|
||||
extern slc_dev_t SLC;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SLC_STRUCT_H_ */
|
||||
@@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct spi_mem_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 17; /*reserved*/
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct spi_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct syscon_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_ctrl_pre_div_cnt: 10;
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct system_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t control_core_1_runstall : 1;
|
||||
|
||||
@@ -90,6 +90,7 @@ typedef union {
|
||||
* update timer_unit0
|
||||
*/
|
||||
uint32_t timer_unit_update: 1;
|
||||
uint32_t reserved_32: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit_op_reg_t;
|
||||
@@ -104,6 +105,7 @@ typedef struct {
|
||||
* timer unit load high 32 bit
|
||||
*/
|
||||
uint32_t timer_unit_load_hi: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
@@ -129,6 +131,7 @@ typedef struct {
|
||||
* timer target high 32 bit
|
||||
*/
|
||||
uint32_t timer_target_hi: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
@@ -177,6 +180,7 @@ typedef struct {
|
||||
* timer read value high 20bit
|
||||
*/
|
||||
uint32_t timer_unit_value_hi: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
@@ -201,6 +205,7 @@ typedef union {
|
||||
* timer comp load value
|
||||
*/
|
||||
uint32_t timer_comp_load: 1;
|
||||
uint32_t reserved_1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp_load_reg_t;
|
||||
@@ -215,6 +220,7 @@ typedef union {
|
||||
* timer unit load value
|
||||
*/
|
||||
uint32_t timer_unit_load: 1;
|
||||
uint32_t reserved_1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit_load_reg_t;
|
||||
@@ -238,6 +244,7 @@ typedef union {
|
||||
* interupt2 enable
|
||||
*/
|
||||
uint32_t target2_int_ena: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_ena_reg_t;
|
||||
@@ -259,6 +266,7 @@ typedef union {
|
||||
* interupt2 raw
|
||||
*/
|
||||
uint32_t target2_int_raw: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_raw_reg_t;
|
||||
@@ -280,6 +288,7 @@ typedef union {
|
||||
* interupt2 clear
|
||||
*/
|
||||
uint32_t target2_int_clr: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_clr_reg_t;
|
||||
@@ -301,6 +310,7 @@ typedef union {
|
||||
* interupt2 status
|
||||
*/
|
||||
uint32_t target2_int_st: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_st_reg_t;
|
||||
@@ -325,6 +335,7 @@ typedef struct {
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
uint32_t target_hi_ro: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
|
||||
@@ -23,7 +23,7 @@ extern "C" {
|
||||
|
||||
/* ---------------------------- Register Layout ------------------------------ */
|
||||
|
||||
/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access
|
||||
/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access
|
||||
* peripheral registers every 32bits. Therefore each TWAI register is mapped to
|
||||
* the least significant byte of every 32bits.
|
||||
*/
|
||||
@@ -36,10 +36,10 @@ typedef volatile struct twai_dev_s {
|
||||
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
|
||||
uint32_t stm: 1; /* MOD.2 Self Test Mode */
|
||||
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
|
||||
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
|
||||
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
|
||||
};
|
||||
uint32_t val;
|
||||
} mode_reg; /* Address 0 */
|
||||
} mode_reg; /* Address 0x0000 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t tr: 1; /* CMR.0 Transmission Request */
|
||||
@@ -47,10 +47,10 @@ typedef volatile struct twai_dev_s {
|
||||
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
|
||||
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
|
||||
uint32_t srr: 1; /* CMR.4 Self Reception Request */
|
||||
uint32_t reserved27: 27; /* Internal Reserved */
|
||||
uint32_t reserved5: 27; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} command_reg; /* Address 1 */
|
||||
} command_reg; /* Address 0x0004 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
|
||||
@@ -62,97 +62,99 @@ typedef volatile struct twai_dev_s {
|
||||
uint32_t es: 1; /* SR.6 Error Status */
|
||||
uint32_t bs: 1; /* SR.7 Bus Status */
|
||||
uint32_t ms: 1; /* SR.8 Miss Status */
|
||||
uint32_t reserved24: 23; /* Internal Reserved */
|
||||
uint32_t reserved9: 23; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} status_reg; /* Address 2 */
|
||||
} status_reg; /* Address 0x0008 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t ri: 1; /* IR.0 Receive Interrupt */
|
||||
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
|
||||
uint32_t ei: 1; /* IR.2 Error Interrupt */
|
||||
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
|
||||
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
|
||||
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
|
||||
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
|
||||
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
|
||||
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} interrupt_reg; /* Address 3 */
|
||||
} interrupt_reg; /* Address 0x000C */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
|
||||
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
|
||||
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
|
||||
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
|
||||
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
|
||||
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
|
||||
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
|
||||
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
|
||||
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} interrupt_enable_reg; /* Address 4 */
|
||||
uint32_t reserved_05; /* Address 5 */
|
||||
} interrupt_enable_reg; /* Address 0x0010 */
|
||||
uint32_t reserved_14;
|
||||
union {
|
||||
struct {
|
||||
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
|
||||
uint32_t reserved1: 1; /* Internal Reserved */
|
||||
uint32_t reserved13: 1; /* Internal Reserved */
|
||||
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
|
||||
uint32_t reserved16: 16; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} bus_timing_0_reg; /* Address 6 */
|
||||
} bus_timing_0_reg; /* Address 0x0018 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
|
||||
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
|
||||
uint32_t sam: 1; /* BTR1.7 Sampling*/
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} bus_timing_1_reg; /* Address 7 */
|
||||
uint32_t reserved_08; /* Address 8 (Output control not supported) */
|
||||
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
|
||||
uint32_t reserved_10; /* Address 10 */
|
||||
} bus_timing_1_reg; /* Address 0x001C */
|
||||
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
|
||||
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
|
||||
uint32_t reserved_28; /* Address 0x0028 */
|
||||
|
||||
//Capture and Counter Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
|
||||
uint32_t reserved27: 27; /* Internal Reserved */
|
||||
uint32_t reserved5: 27; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} arbitration_lost_captue_reg; /* Address 11 */
|
||||
} arbitration_lost_captue_reg; /* Address 0x002C */
|
||||
union {
|
||||
struct {
|
||||
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
|
||||
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
|
||||
uint32_t errc: 2; /* ECC[7:6] Error Code */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} error_code_capture_reg; /* Address 12 */
|
||||
} error_code_capture_reg; /* Address 0x0030 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
|
||||
} error_warning_limit_reg; /* Address 0x0034 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_error_counter_reg; /* Address 12 */
|
||||
} rx_error_counter_reg; /* Address 0x0038 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_error_counter_reg; /* Address 15 */
|
||||
} tx_error_counter_reg; /* Address 0x003C */
|
||||
|
||||
//Shared Registers (TX Buff/RX Buff/Acc Filter)
|
||||
union {
|
||||
@@ -160,45 +162,49 @@ typedef volatile struct twai_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} acr[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} amr[4];
|
||||
uint32_t reserved32[5];
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
} acceptance_filter;
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8;
|
||||
uint32_t reserved24: 24;
|
||||
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_rx_buffer[13];
|
||||
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
|
||||
}; /* Address 0x0040 - 0x0070 */
|
||||
|
||||
//Misc Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
|
||||
uint32_t reserved25: 25; /* Internal Reserved */
|
||||
uint32_t reserved7: 25; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_message_counter_reg; /* Address 29 */
|
||||
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
|
||||
} rx_message_counter_reg; /* Address 0x0074 */
|
||||
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
|
||||
union {
|
||||
struct {
|
||||
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
|
||||
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
|
||||
uint32_t reserved24: 23; /* Internal Reserved */
|
||||
uint32_t reserved9: 23; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_divider_reg; /* Address 31 */
|
||||
} clock_divider_reg; /* Address 0x007C */
|
||||
} twai_dev_t;
|
||||
|
||||
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct uhci_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_rst : 1;
|
||||
|
||||
@@ -20,7 +20,7 @@ extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct usb_serial_jtag_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdwr_byte : 32; /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
|
||||
|
||||
@@ -154,6 +154,7 @@ typedef union {
|
||||
* USB D- rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dm:1;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_test_conf_reg_t;
|
||||
|
||||
@@ -831,7 +831,7 @@ typedef union {
|
||||
uint32_t bbleerr: 1;
|
||||
uint32_t nakintrpt: 1;
|
||||
uint32_t nyetintrpt: 1;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t reserved15: 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_diepint_reg_t;
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
typedef volatile struct world_controller_dev_s {
|
||||
uint32_t wcl_core_0_entry_1_addr;
|
||||
uint32_t wcl_core_0_entry_2_addr;
|
||||
uint32_t wcl_core_0_entry_3_addr;
|
||||
|
||||
Reference in New Issue
Block a user