diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index 0985e9f7da..81383fba05 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -75,10 +75,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, (slow_freq == RTC_SLOW_FREQ_EXT_CLK) ? 1 : 0); - /* The clk_8m_d256 will be closed when rtc_state in SLEEP, - so if the slow_clk is 8md256, clk_8m must be force power on - */ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index fe91dd5ffc..69ee0f6917 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -125,10 +125,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - /* The clk_8m_d256 will be closed when rtc_state in SLEEP, - so if the slow_clk is 8md256, clk_8m must be force power on - */ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk.c b/components/esp_hw_support/port/esp32s2/rtc_clk.c index 08b53dbdc5..6d147fbb3c 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s2/rtc_clk.c @@ -218,10 +218,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - /* The clk_8m_d256 will be closed when rtc_state in SLEEP, - so if the slow_clk is 8md256, clk_8m must be force power on - */ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); } diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 0011e5af43..b93d0c1499 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -146,10 +146,6 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - /* The clk_8m_d256 will be closed when rtc_state in SLEEP, - so if the slow_clk is 8md256, clk_8m must be force power on - */ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH); }