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Merge branch 'bugfix/rtc_clk_32k_bootstrap' into 'master'
bugfix/rtc_clk_32k_bootstrap: Fix starting 32k RTC See merge request idf/esp-idf!2085
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@@ -19,6 +19,7 @@
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#include "rom/ets_sys.h"
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#include "rom/rtc.h"
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#include "rom/uart.h"
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#include "rom/gpio.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_io_reg.h"
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@@ -122,11 +123,37 @@ void rtc_clk_32k_enable(bool enable)
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}
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}
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void rtc_clk_32k_bootstrap()
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/* Helping external 32kHz crystal to start up.
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* External crystal connected to outputs GPIO32 GPIO33.
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* Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
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*/
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void rtc_clk_32k_bootstrap(uint32_t cycle)
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{
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if (cycle){
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const uint32_t pin_32 = 32;
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const uint32_t pin_33 = 33;
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const uint32_t mask_32 = (1 << (pin_32 - 32));
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const uint32_t mask_33 = (1 << (pin_33 - 32));
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gpio_pad_select_gpio(pin_32);
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gpio_pad_select_gpio(pin_33);
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gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0);
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const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2);
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while(cycle){
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gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0);
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ets_delay_us(delay_us);
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gpio_output_set_high(mask_33, mask_32, mask_32 | mask_33, 0);
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ets_delay_us(delay_us);
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cycle--;
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}
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gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins
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}
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
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ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
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rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL,
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XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
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}
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