Merge branch 'patch/ets_delay_us' into 'master'

fix(esp_tee): Patch the `esp_rom_delay_us` API to use U-mode cycle CSR

See merge request espressif/esp-idf!40105

components/esp_rom/CMakeLists.txt

@@ -388,6 +388,12 @@ else() # Regular app build
         endif()
     endif()
 
+    if(CONFIG_ESP_ROM_DELAY_US_PATCH AND
+        (CONFIG_ESP32C5_REV_MIN_FULL LESS_EQUAL 100 OR CONFIG_ESP32C61_REV_MIN_FULL LESS_EQUAL 100))
+        # Force the linker to include esp_rom_sys.c for ets_ops_set_rom_patches constructor
+        target_link_libraries(${COMPONENT_LIB} PRIVATE "-u ets_ops_set_rom_patches")
+    endif()
+
     if(CONFIG_IDF_TARGET_ARCH_XTENSA)
         target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=longjmp")
     endif()

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -118,3 +118,7 @@ config ESP_ROM_CLIC_INT_THRESH_PATCH
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_DELAY_US_PATCH
+    bool
+    default y

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -35,3 +35,4 @@
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_CLIC_INT_THRESH_PATCH       (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_DELAY_US_PATCH              (1) // ROM ets_delay_us needs patch for U-mode operation

components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h

@@ -64,9 +64,9 @@ struct ETSEventTag {
 typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processor*/
 typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
 
-
+typedef struct ets_ops {
-
+  void (*ets_delay_us)(uint32_t us);
-
+} ets_ops;
 
 /**
   * @}

components/esp_rom/esp32c5/ld/esp32c5.rom.ld

@@ -27,7 +27,7 @@ ets_install_putc2 = 0x4000002c;
 ets_install_uart_printf = 0x40000030;
 ets_install_usb_printf = 0x40000034;
 ets_get_printf_channel = 0x40000038;
-ets_delay_us = 0x4000003c;
+PROVIDE ( ets_delay_us = 0x4000003c );
 ets_get_cpu_frequency = 0x40000040;
 ets_update_cpu_frequency = 0x40000044;
 ets_install_lock = 0x40000048;

components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld

@@ -52,7 +52,7 @@ hal_tsf_clear_soc_wakeup_request = 0x40000c60;
 hal_get_tsf_time = 0x40000c64;
 hal_get_sta_tsf = 0x40000c68;
 ic_get_trc = 0x40000c74;
-ic_mac_deinit = 0x40000c78;
+/* ic_mac_deinit = 0x40000c78; */
 /* ic_mac_init = 0x40000c7c; */
 ic_interface_enabled = 0x40000c80;
 is_lmac_idle = 0x40000c84;
@@ -75,7 +75,7 @@ lmacRxDone = 0x40000cc4;
 lmacSetTxFrame = 0x40000cc8;
 lmacTxDone = 0x40000ccc;
 /*lmacTxFrame = 0x40000cd0;*/
-lmacDisableTransmit = 0x40000cd4;
+/* lmacDisableTransmit = 0x40000cd4; */
 lmacDiscardFrameExchangeSequence = 0x40000cd8;
 lmacProcessCollision = 0x40000cdc;
 lmacProcessAckTimeout = 0x40000ce0;

components/esp_rom/esp32c61/Kconfig.soc_caps.in

@@ -114,3 +114,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_DELAY_US_PATCH
+    bool
+    default y

components/esp_rom/esp32c61/esp_rom_caps.h

@@ -34,3 +34,4 @@
 #define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_DELAY_US_PATCH              (1) // ROM ets_delay_us needs patch for U-mode operation

components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h

@@ -64,9 +64,9 @@ struct ETSEventTag {
 typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processor*/
 typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
 
-
+typedef struct ets_ops {
-
+  void (*ets_delay_us)(uint32_t us);
-
+} ets_ops;
 
 /**
   * @}

components/esp_rom/esp32c61/ld/esp32c61.rom.ld

@@ -23,7 +23,7 @@ ets_install_putc2 = 0x4000002c;
 ets_install_uart_printf = 0x40000030;
 ets_install_usb_printf = 0x40000034;
 ets_get_printf_channel = 0x40000038;
-ets_delay_us = 0x4000003c;
+PROVIDE ( ets_delay_us = 0x4000003c );
 ets_get_cpu_frequency = 0x40000040;
 ets_update_cpu_frequency = 0x40000044;
 ets_install_lock = 0x40000048;

components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld

@@ -50,7 +50,7 @@ hal_get_tsf_time = 0x40000bd0;
 hal_get_sta_tsf = 0x40000bd4;
 tsf_hal_get_tbtt_interval = 0x40000bd8;
 ic_get_trc = 0x40000be4;
-ic_mac_deinit = 0x40000be8;
+/* ic_mac_deinit = 0x40000be8; */
 /* ic_mac_init = 0x40000bec; */
 ic_interface_enabled = 0x40000bf0;
 is_lmac_idle = 0x40000bf4;
@@ -73,7 +73,7 @@ lmacRxDone = 0x40000c34;
 lmacSetTxFrame = 0x40000c38;
 lmacTxDone = 0x40000c3c;
 /*lmacTxFrame = 0x40000c40;*/
-lmacDisableTransmit = 0x40000c44;
+/* lmacDisableTransmit = 0x40000c44; */
 lmacDiscardFrameExchangeSequence = 0x40000c48;
 lmacProcessCollision = 0x40000c4c;
 lmacProcessAckTimeout = 0x40000c50;

components/esp_rom/patches/esp_rom_sys.c

@@ -7,10 +7,12 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include <stddef.h>
+#include <string.h>
 #include "soc/soc_caps.h"
 #include "esp_rom_caps.h"
 #include "esp_rom_serial_output.h"
 #include "rom/ets_sys.h"
+#include "esp_rom_sys.h"
 #include "sdkconfig.h"
 
 #if !ESP_ROM_HAS_OUTPUT_PUTC_FUNC
@@ -114,3 +116,46 @@ uint32_t esp_rom_get_bootloader_offset(void)
     return offset_of_active_bootloader;
 }
 #endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED
+
+#if ESP_ROM_DELAY_US_PATCH && !NON_OS_BUILD
+#if CONFIG_ESP32C5_REV_MIN_FULL <= 100 || CONFIG_ESP32C61_REV_MIN_FULL <= 100
+
+#include "riscv/rv_utils.h"
+
+extern const ets_ops *ets_ops_table_ptr;
+
+struct ets_ops ets_ops_patch_table_ptr;
+
+/*
+ * NOTE: Workaround for ROM delay API in ESP32-C5 (<=ECO2) and ESP32-C61 (<=ECO3):
+ *
+ * The ROM implementation of `ets_delay_us` uses the `mcycle` CSR to get CPU cycle count.
+ * This CSR is accessible only in M-mode and when the ROM API is called from U-mode,
+ * accessing `mcycle` causes an illegal instruction fault.
+ *
+ * This issue has been fixed in later ECO revisions of both SoCs.
+ */
+void ets_delay_us(uint32_t us)
+{
+    uint32_t start = rv_utils_get_cycle_count();
+    uint32_t end = us * esp_rom_get_cpu_ticks_per_us();
+
+    while ((rv_utils_get_cycle_count() - start) < end) {
+        /* busy-wait loop for delay */
+    }
+}
+
+void __attribute__((constructor)) ets_ops_set_rom_patches(void)
+{
+    /* Copy ROM default function table into our patch table */
+    memcpy(&ets_ops_patch_table_ptr, ets_ops_table_ptr, sizeof(struct ets_ops));
+
+    /* Replace the ROM's delay function with the patched version */
+    ets_ops_patch_table_ptr.ets_delay_us = ets_delay_us;
+
+    /* Redirect ROM calls to use the patched function table */
+    ets_ops_table_ptr = &ets_ops_patch_table_ptr;
+}
+
+#endif // CONFIG_ESP32C5_REV_MIN_100 || CONFIG_ESP32C61_REV_MIN_100
+#endif // ESP_ROM_DELAY_US_PATCH && CONFIG_SECURE_ENABLE_TEE && !NON_OS_BUILD

components/riscv/include/riscv/rv_utils.h

@@ -104,7 +104,7 @@ FORCE_INLINE_ATTR void *rv_utils_get_sp(void)
 FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_get_cycle_count(void)
 {
 #if !SOC_CPU_HAS_CSR_PC
-    return RV_READ_CSR(mcycle);
+    return RV_READ_CSR(cycle);
 #else
     if (IS_PRV_M_MODE()) {
         return RV_READ_CSR(CSR_PCCR_MACHINE);