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https://github.com/espressif/esp-idf.git
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doc(spi_flash): hide unsupported optional features
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Xiao Xufeng
@@ -887,10 +887,6 @@ config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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bool
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default y
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config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
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bool
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default y
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@@ -415,7 +415,7 @@
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/*-------------------------- SPI MEM CAPS ---------------------------------------*/
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#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
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//#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) //TODO: IDF-7518
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#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
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#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
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#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
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@@ -74,7 +74,7 @@ There are some features that are not supported by all flash chips, or not suppor
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- Flash unique ID - means that flash supports its unique 64-bit ID.
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.. only:: esp32c3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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- Suspend & Resume - means that flash can accept suspend/resume command during its writing/erasing. The {IDF_TARGET_NAME} may keep the cache on when the flash is being written/erased and suspend it to read its contents randomly.
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@@ -11,7 +11,7 @@ The SPI0/1 bus is shared between the instruction & data cache (for firmware exec
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On {IDF_TARGET_NAME}, these caches must be disabled while reading/writing/erasing.
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.. only:: esp32c3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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On {IDF_TARGET_NAME}, the config option :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND` (enabled by default) allows the cache to read flash concurrently with SPI1 operations. See :ref:`auto-suspend` for more details.
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@@ -78,7 +78,7 @@ Non-IRAM-Safe Interrupt Handlers
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If the ``ESP_INTR_FLAG_IRAM`` flag is not set when registering, the interrupt handler will not get executed when the caches are disabled. Once the caches are restored, the non-IRAM-safe interrupts will be re-enabled. After this moment, the interrupt handler will run normally again. This means that as long as caches are disabled, users will not see the corresponding hardware event happening.
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.. only:: esp32c3 or esp32c2 or esp32s3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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.. include:: auto_suspend.inc
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@@ -30,35 +30,31 @@ Some features are not supported on all ESP chips and Flash chips. You can check
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Auto Suspend & Resume
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---------------------
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The support list is as follows.
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This feature is only supported on ESP32-S3, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-H2 for now.
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ESP Chips List:
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The support for ESP32-P4 may be added in the future.
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1. ESP32C3
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2. ESP32C2
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3. ESP32S3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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Flash Chips List:
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List of Flash chips that support this feature:
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1. XM25QxxC series.
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2. GD25QxxE series.
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.. only:: esp32c3 or esp32c2 or esp32s3
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.. attention::
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There are multiple limitations about the auto-suspend feature, please do read :ref:`auto-suspend` for more information before you enable this feature.
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Flash Unique ID
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---------------
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This feature is supported on all Espressif chips.
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Unique ID is not flash id, which means flash has 64-Bit unique ID for each device. The instruction to read the unique ID (4Bh) accesses a factory-set read-only 64-bit number that is unique to each flash device. This ID number helps you to recognize each single device. Not all flash vendors support this feature. If you try to read the unique ID on a chip which does not have this feature, the behavior is not determined. The support list is as follows.
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ESP Chips Lists:
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ALL
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Flash Chips List:
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List of Flash chips that support this feature:
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1. ISSI
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2. GD
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@@ -73,6 +69,12 @@ Flash Chips List:
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High Performance Mode
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---------------------
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This featuer is only supported on ESP32-S3 for now.
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The support for ESP32-S2, ESP32-C3, ESP32-C6, ESP32-H2, ESP32-P4 may be added in the future.
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.. only:: esp32s3
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.. note::
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This section is provided for Dual mode (DOUT/DIO) and Quad mode (QIO/QOUT) flash chips. Octal flash used on ESP-chips support High performance mode by default so far, you can refer to the octal flash support list below.
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@@ -113,12 +115,6 @@ Check whether the bootloader supports `DC Aware` in the following way:
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- For versions below v4.4.4, the bootloader doesn't support `DC Aware`.
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ESP Chips List:
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1. ESP32S3
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(The SW support for other chips haven't been done yet)
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.. _hpm_dc_support_list:
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Quad Flash HPM support list
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@@ -143,6 +139,8 @@ Following flash chips also have HPM feature, but requires the bootloader to supp
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OPI flash Support
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-----------------
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This feature is only supporetd on ESP32-S3 for now.
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OPI flash means that the flash chip supports octal peripheral interface, which has octal I/O pins. Different octal flash has different configurations and different commands. Hence, it is necessary to carefully check the support list.
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.. only:: esp32s3
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@@ -151,13 +149,10 @@ OPI flash means that the flash chip supports octal peripheral interface, which h
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To know how to configure menuconfig for a board with different Flash and PSRAM, please refer to the :ref:`SPI Flash and External SPI RAM Configuration <flash-psram-configuration>`
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ESP Chips List:
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1. ESP32S3
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Flash Chips List:
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List of Flash chips that support this feature:
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1. MX25UM25645G
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2. MX25UM12345G
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.. _32-bit-flash-doc:
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@@ -165,13 +160,11 @@ Flash Chips List:
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32-bit Address Flash Chips
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--------------------------
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This feature is supported on all Espressif chips (with various restrictions to application).
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Most NOR flash chips used by Espressif chips use 24-bits address, which can cover 16 MBytes memory. However, for larger memory (usually equal to or larger than 16 MBytes), flash uses a 32-bits address to address larger memory. Regretfully, 32-bits address chips have vendor-specific commands, so we need to support the chips one by one.
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ESP Chips List:
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ALL ESP Chips support this.
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Flash Chips List:
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List of Flash chips that support this feature:
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1. W25Q256
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2. GD25Q256
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@@ -74,7 +74,7 @@ flash 可选的功能
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- flash 的私有 ID (unique ID) - 表示 flash 支持它自己的 64-bit 独有 ID。
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.. only:: esp32c3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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- 暂停与恢复 - 表示 flash 可以在读/写的过程中接受暂停/恢复的命令。{IDF_TARGET_NAME} 可以在 flash 正在写/擦除的过程中保持 cache 开启，并能随机读取 flash 中的内容。
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@@ -11,7 +11,7 @@ SPI1 flash 并发约束
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在 {IDF_TARGET_NAME} 上，flash 读取/写入/擦除时，必须禁用 cache。
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.. only:: esp32c3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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在 {IDF_TARGET_NAME} 上，默认启用的配置选项 :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND` 允许 flash/PSRAM 的 cache 访问和 SPI1 的操作并发执行。请参阅 :ref:`auto-suspend`，查看详细信息。
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@@ -78,7 +78,7 @@ IRAM 安全中断处理程序
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如果在注册时没有设置 ``ESP_INTR_FLAG_IRAM`` 标志，当禁用 cache 时，将不会执行中断处理程序。一旦 cache 恢复，非 IRAM 安全的中断将重新启用，中断处理程序随即再次正常运行。这意味着，只要禁用了 cache，就不会发生相应的硬件事件。
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.. only:: esp32c3 or esp32c2 or esp32s3
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.. only:: SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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.. include:: auto_suspend.inc
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