Merge branch 'feature/esp32c6_bringup' into 'master'

ESP32C6: Introduce new chip target esp32c6

Closes IDF-5247

See merge request espressif/esp-idf!19286

.gitlab/ci/pre_check.yml

@@ -92,6 +92,7 @@ check_public_headers:
     - IDF_TARGET=esp32s3 python tools/ci/check_public_headers.py --jobs 4 --prefix xtensa-esp32s3-elf-
     - IDF_TARGET=esp32c3 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
     - IDF_TARGET=esp32c2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
+    - IDF_TARGET=esp32c6 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf-
 
 check_chip_support_components:
   extends:

components/bootloader/subproject/main/ld/esp32c6/bootloader.ld

@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *  We put 2nd bootloader in the high address space (before ROM stack/data/bss).
+ *  See memory usage for ROM bootloader at the end of this file.
+ */
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = 0x4086E000, len = 0x2000
+  iram_loader_seg (RWX) :           org = 0x40870000, len = 0x6000
+  dram_seg (RW) :                   org = 0x40876000, len = 0x4000
+}
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ *  +--------+--------------+------+ 0x3FCC_AE00
+ *  |        ^              |
+ *  |        |              |
+ *  |        | data/bss     |
+ *  |        |              |
+ *  |        v              |
+ *  +------------------------------+ 0x3FCD_C710
+ *  |        ^              |
+ *  |        |              |
+ *  |        | stack        |
+ *  |        |              |
+ *  |        v              |
+ *  +------------------------------+ 0x3FCD_E710
+ */

components/bootloader/subproject/main/ld/esp32c6/bootloader.rom.ld

@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-C6 target */

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -128,9 +128,9 @@ static const char *TAG = "bootloader_flash";
    50th block for bootloader_flash_read
 */
 #define MMU_BLOCK0_VADDR  SOC_DROM_LOW
-#define MMU_SIZE          (0x320000)
+#define MMAP_MMU_SIZE     (0x320000)
-#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
+#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE)
-#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
+#define FLASH_READ_VADDR  MMU_BLOCK50_VADDR
 
 #else // !CONFIG_IDF_TARGET_ESP32
 
@@ -139,15 +139,15 @@ static const char *TAG = "bootloader_flash";
 */
 #define MMU_BLOCK0_VADDR  SOC_DROM_LOW
 #ifdef SOC_MMU_PAGE_SIZE_CONFIGURABLE
-#define MMU_SIZE          (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
+#define MMAP_MMU_SIZE     (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
 #else
-#define MMU_SIZE          (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
+#define MMAP_MMU_SIZE     (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
 #endif
-#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
+#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK63_VADDR
 #endif
 
-#define MMU_FREE_PAGES    (MMU_SIZE / FLASH_BLOCK_SIZE)
+#define MMU_FREE_PAGES    (MMAP_MMU_SIZE / CONFIG_MMU_PAGE_SIZE)
 
 static bool mapped;
 
@@ -169,7 +169,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
         ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice");
         return NULL; /* can't map twice */
     }
-    if (size > MMU_SIZE) {
+    if (size > MMAP_MMU_SIZE) {
         ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
         return NULL;
     }
@@ -769,10 +769,8 @@ esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
     bootloader_execute_flash_command(0x05, 0, 0, 0);
 #if CONFIG_IDF_TARGET_ESP32
     if (SPI1.ext2.st != 0)
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-    if (SPIMEM1.fsm.st != 0)
 #else
-    if (SPIMEM1.fsm.spi0_mst_st != 0)
+    if (!spimem_flash_ll_host_idle(&SPIMEM1))
 #endif
     {
         return ESP_FAIL;

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c

@@ -0,0 +1,69 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp32c6/rom/gpio.h"
+#include "esp32c6/rom/spi_flash.h"
+#include "esp32c6/rom/efuse.h"
+#include "soc/gpio_periph.h"
+#include "soc/efuse_reg.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+
+void bootloader_flash_update_id()
+{
+    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+    chip->device_id = bootloader_read_flash_id();
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        spi_clk_div = 1;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        spi_clk_div = 2;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        spi_clk_div = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        spi_clk_div = 4;
+        break;
+    default:
+        break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void IRAM_ATTR bootloader_flash_set_dummy_out(void)
+{
+    REG_SET_BIT(SPI_MEM_CTRL_REG(0), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: IDF-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
+    REG_SET_BIT(SPI_MEM_CTRL_REG(1), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: idf-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
+}
+
+void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
+{
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_set_dummy_out();
+}

components/bootloader_support/bootloader_flash/src/flash_qio_mode.c

@@ -106,8 +106,8 @@ static void s_flash_set_qio_pins(void)
     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
     int wp_pin = bootloader_flash_get_wp_pin();
     esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
-#elif CONFIG_IDF_TARGET_ESP32C2
+#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5649 Add a soc_caps
-    // ESP32C2 doesn't support configure mspi pins. So the second
+    // ESP32C2/ESP32C6 doesn't support configure mspi pins. So the second
     // parameter is set to 0, means that chip uses default SPI pins
     // and wp_gpio_num parameter(the first parameter) is ignored.
     esp_rom_spiflash_select_qio_pins(0, 0);

components/bootloader_support/include/bootloader_memory_utils.h

@@ -69,7 +69,12 @@ inline static bool esp_ptr_in_diram_dram(const void *p) {
  */
 __attribute__((always_inline))
 inline static bool esp_ptr_in_diram_iram(const void *p) {
+// TODO: IDF-5980 esp32c6 D/I RAM share the same address
+#if SOC_DIRAM_IRAM_LOW == SOC_DIRAM_DRAM_LOW
+    return false;
+#else
     return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
+#endif
 }
 
 /**

components/bootloader_support/include/esp_app_format.h

@@ -22,6 +22,7 @@ typedef enum {
 #elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
     ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */
 #endif
+    ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
     ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;
 

components/bootloader_support/private_include/bootloader_signature.h

@@ -21,6 +21,8 @@
 #include "esp32h2/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/secure_boot.h"
 #endif
 
 #if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3

components/bootloader_support/src/bootloader_clock_init.c

@@ -7,7 +7,16 @@
 #include "soc/soc.h"
 #include "soc/rtc.h"
 #include "hal/efuse_hal.h"
+
+#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
 #include "soc/rtc_cntl_reg.h"
+#else
+#include "soc/lp_wdt_reg.h"
+#include "soc/lp_timer_reg.h"
+#include "soc/lp_analog_peri_reg.h"
+#include "soc/pmu_reg.h"
+#endif
+
 #if CONFIG_IDF_TARGET_ESP32
 #include "hal/clk_tree_ll.h"
 #endif
@@ -65,6 +74,24 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     }
 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
 
+// TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6
+    // CLR ENA
+    CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA);                                      /* SWD */
+    CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA);                           /* MAIN_TIMER */
+    CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA);  /* BROWN_OUT */
+    CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA);                                         /* WDT */
+    CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA);                                        /* SLP_REJECT */
+    CLEAR_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_ENA, PMU_SOC_SLEEP_REJECT_INT_ENA);                        /* SLP_WAKEUP */
+    // SET CLR
+    SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR);                                        /* SWD */
+    SET_PERI_REG_MASK(LP_TIMER_LP_INT_CLR_REG, LP_TIMER_MAIN_TIMER_LP_INT_CLR);                             /* MAIN_TIMER */
+    SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR);    /* BROWN_OUT */
+    SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR);                                           /* WDT */
+    SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR);                                          /* SLP_REJECT */
+    SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR);                          /* SLP_WAKEUP */
+#else
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
+#endif
 }

components/bootloader_support/src/bootloader_console.c

@@ -28,6 +28,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/ets_sys.h"
 #include "esp32c2/rom/uart.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/ets_sys.h"
+#include "esp32c6/rom/uart.h"
 #endif
 #include "esp_rom_gpio.h"
 #include "esp_rom_uart.h"

components/bootloader_support/src/bootloader_efuse.c

@@ -30,6 +30,9 @@ int bootloader_clock_get_rated_freq_mhz(void)
 #elif CONFIG_IDF_TARGET_ESP32H2
     return 96;
 
+#elif CONFIG_IDF_TARGET_ESP32C6
+    return 160;
+
 #elif CONFIG_IDF_TARGET_ESP32S2
     return 240;
 

components/bootloader_support/src/bootloader_init.c

@@ -58,27 +58,31 @@ void bootloader_config_wdt(void)
      * protect the remainder of the bootloader process.
      */
     //Disable RWDT flashboot protection.
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
-    wdt_hal_write_protect_disable(&rtc_wdt_ctx);
+    wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
-    wdt_hal_set_flashboot_en(&rtc_wdt_ctx, false);
+#else
-    wdt_hal_write_protect_enable(&rtc_wdt_ctx);
+    wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#endif
+    wdt_hal_write_protect_disable(&rwdt_ctx);
+    wdt_hal_set_flashboot_en(&rwdt_ctx, false);
+    wdt_hal_write_protect_enable(&rwdt_ctx);
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     //Initialize and start RWDT to protect the  for bootloader if configured to do so
     ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS);
-    wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
+    wdt_hal_init(&rwdt_ctx, WDT_RWDT, 0, false);
     uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
-    wdt_hal_write_protect_disable(&rtc_wdt_ctx);
+    wdt_hal_write_protect_disable(&rwdt_ctx);
-    wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
+    wdt_hal_config_stage(&rwdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
-    wdt_hal_enable(&rtc_wdt_ctx);
+    wdt_hal_enable(&rwdt_ctx);
-    wdt_hal_write_protect_enable(&rtc_wdt_ctx);
+    wdt_hal_write_protect_enable(&rwdt_ctx);
 #endif
 
     //Disable MWDT0 flashboot protection. But only after we've enabled the RWDT first so that there's not gap in WDT protection.
-    wdt_hal_context_t wdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
+    wdt_hal_context_t mwdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
-    wdt_hal_write_protect_disable(&wdt_ctx);
+    wdt_hal_write_protect_disable(&mwdt_ctx);
-    wdt_hal_set_flashboot_en(&wdt_ctx, false);
+    wdt_hal_set_flashboot_en(&mwdt_ctx, false);
-    wdt_hal_write_protect_enable(&wdt_ctx);
+    wdt_hal_write_protect_enable(&mwdt_ctx);
 }
 
 void bootloader_enable_random(void)

components/bootloader_support/src/bootloader_mem.c

@@ -12,8 +12,21 @@
 #include "bootloader_mem.h"
 #include "esp_cpu.h"
 
+#if CONFIG_IDF_TARGET_ESP32C6
+#include "soc/hp_apm_reg.h"
+#include "soc/lp_apm_reg.h"
+#include "soc/lp_apm0_reg.h"
+#endif
+
 void bootloader_init_mem(void)
 {
+#if CONFIG_IDF_TARGET_ESP32C6
+    // disable apm filter // TODO: IDF-5909
+    REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
+    REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
+    REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
+#endif
+
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
     // protect memory region
     esp_cpu_configure_region_protection();

components/bootloader_support/src/bootloader_random_esp32c6.c

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "bootloader_random.h"
+#include "esp_log.h"
+
+static const char *TAG = "bootloader_random";
+
+void bootloader_random_enable(void)
+{
+    // TODO: IDF-5352
+    ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
+}
+
+void bootloader_random_disable(void)
+{
+    // TODO: IDF-5352
+    ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
+}

components/bootloader_support/src/bootloader_utility.c

@@ -41,6 +41,13 @@
 #include "esp32c2/rom/uart.h"
 #include "esp32c2/rom/gpio.h"
 #include "esp32c2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/efuse.h"
+#include "esp32c6/rom/crc.h"
+#include "esp32c6/rom/rtc.h"
+#include "esp32c6/rom/uart.h"
+#include "esp32c6/rom/gpio.h"
+#include "esp32c6/rom/secure_boot.h"
 
 #else // CONFIG_IDF_TARGET_*
 #error "Unsupported IDF_TARGET"

components/bootloader_support/src/esp32c6/bootloader_esp32c6.c

@@ -0,0 +1,344 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_image_format.h"
+#include "flash_qio_mode.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_efuse.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "esp_rom_spiflash.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/io_mux_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "esp_cpu.h"
+#include "soc/rtc.h"
+#include "soc/spi_periph.h"
+#include "soc/extmem_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/pcr_reg.h"
+#include "esp32c6/rom/efuse.h"
+#include "esp32c6/rom/ets_sys.h"
+#include "bootloader_common.h"
+#include "bootloader_init.h"
+#include "bootloader_clock.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
+#include "esp_private/regi2c_ctrl.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_bias.h"
+#include "bootloader_console.h"
+#include "bootloader_flash_priv.h"
+#include "bootloader_soc.h"
+#include "esp_efuse.h"
+#include "hal/mmu_hal.h"
+#include "hal/cache_hal.h"
+#include "soc/lp_wdt_reg.h"
+#include "hal/efuse_hal.h"
+
+static const char *TAG = "boot.esp32c6";
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    // TODO: IDF-5649
+    const uint32_t spiconfig = 0;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    if (spiconfig == 0) {
+
+    }
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
+        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    }
+    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
+        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+    }
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+    uint32_t size;
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        size = 1;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        size = 2;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        size = 4;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        size = 8;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        size = 16;
+        break;
+    default:
+        size = 2;
+    }
+    cache_hal_disable(CACHE_TYPE_ALL);
+    // Set flash chip size
+    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
+    cache_hal_enable(CACHE_TYPE_ALL);
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+    ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+    ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+    ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+    ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+    ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+    const char *str;
+    switch (bootloader_hdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_DIV_2:
+        str = "40MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_3:
+        str = "26.7MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_4:
+        str = "20MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_DIV_1:
+        str = "80MHz";
+        break;
+    default:
+        str = "20MHz";
+        break;
+    }
+    ESP_LOGI(TAG, "SPI Speed      : %s", str);
+
+    /* SPI mode could have been set to QIO during boot already,
+       so test the SPI registers not the flash header */
+    uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
+    if (spi_ctrl & SPI_MEM_FREAD_QIO) {
+        str = "QIO";
+    } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
+        str = "QOUT";
+    } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
+        str = "DIO";
+    } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
+        str = "DOUT";
+    } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
+        str = "FAST READ";
+    } else {
+        str = "SLOW READ";
+    }
+    ESP_LOGI(TAG, "SPI Mode       : %s", str);
+
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        str = "1MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        str = "2MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        str = "4MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        str = "8MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        str = "16MB";
+        break;
+    default:
+        str = "2MB";
+        break;
+    }
+    ESP_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void IRAM_ATTR bootloader_init_flash_configure(void)
+{
+    bootloader_flash_dummy_config(&bootloader_image_hdr);
+    bootloader_flash_cs_timing_config();
+}
+
+static void bootloader_spi_flash_resume(void)
+{
+    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+static esp_err_t bootloader_init_spi_flash(void)
+{
+    bootloader_init_flash_configure();
+// TODO: IDF-5649
+// #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
+//     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
+//     if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
+//         ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
+//         return ESP_FAIL;
+//     }
+// #endif
+
+    bootloader_spi_flash_resume();
+    bootloader_flash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+    bootloader_enable_qio_mode();
+#endif
+
+    print_flash_info(&bootloader_image_hdr);
+    update_flash_config(&bootloader_image_hdr);
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+    return ESP_OK;
+}
+
+static void wdt_reset_cpu0_info_enable(void)
+{
+    REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
+    REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
+    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
+}
+
+static void bootloader_check_wdt_reset(void)
+{
+    int wdt_rst = 0;
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
+        rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
+        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+        wdt_rst = 1;
+    }
+    if (wdt_rst) {
+        // if reset by WDT dump info from trace port
+        wdt_reset_info_dump(0);
+    }
+    wdt_reset_cpu0_info_enable();
+}
+
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_WRITE(LP_WDT_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
+    REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
+    REG_WRITE(LP_WDT_WPROTECT_REG, 0);
+}
+
+static inline void bootloader_hardware_init(void)
+{
+    // TODO: IDF-5990 copied from C3, need update
+    // This check is always included in the bootloader so it can
+    // print the minimum revision error message later in the boot
+    if (efuse_hal_get_minor_chip_version() < 3) {
+        REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
+        REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
+    }
+}
+
+static inline void bootloader_ana_reset_config(void)
+{
+    // TODO: IDF-5990 copied from C3, need update
+    /*
+      esp32c6 has removed super wdt!
+      For origin chip & ECO1: only support swt reset;
+      For ECO2: fix brownout reset bug, support swt & brownout reset;
+      For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
+    */
+    uint8_t chip_version = efuse_hal_get_minor_chip_version();
+    switch (chip_version) {
+        case 0:
+        case 1:
+            //Disable BOR and GLITCH reset
+            bootloader_ana_bod_reset_config(false);
+            bootloader_ana_clock_glitch_reset_config(false);
+            break;
+        case 2:
+            //Enable BOR reset. Disable GLITCH reset
+            bootloader_ana_bod_reset_config(true);
+            bootloader_ana_clock_glitch_reset_config(false);
+            break;
+        case 3:
+        default:
+            //Enable BOR, and GLITCH reset
+            bootloader_ana_bod_reset_config(true);
+            bootloader_ana_clock_glitch_reset_config(true);
+            break;
+    }
+}
+
+esp_err_t bootloader_init(void)
+{
+    esp_err_t ret = ESP_OK;
+
+    bootloader_hardware_init();
+    bootloader_ana_reset_config();
+    bootloader_super_wdt_auto_feed();
+    // protect memory region
+    bootloader_init_mem();
+    /* check that static RAM is after the stack */
+    assert(&_bss_start <= &_bss_end);
+    assert(&_data_start <= &_data_end);
+    // clear bss section
+    bootloader_clear_bss_section();
+    // init eFuse virtual mode (read eFuses to RAM)
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_init_virtual_mode_in_ram();
+#endif
+#endif
+    //init cache hal
+    cache_hal_init();
+    //reset mmu
+    mmu_hal_init();
+    // config clock
+    bootloader_clock_configure();
+    // initialize console, from now on, we can use esp_log
+    bootloader_console_init();
+    /* print 2nd bootloader banner */
+    bootloader_print_banner();
+    // update flash ID
+    bootloader_flash_update_id();
+    // Check and run XMC startup flow
+    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
+        ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
+        goto err;
+    }
+    // read bootloader header
+    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
+        goto err;
+    }
+    // read chip revision and check if it's compatible to bootloader
+    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
+        goto err;
+    }
+    // initialize spi flash
+    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
+        goto err;
+    }
+    // check whether a WDT reset happend
+    bootloader_check_wdt_reset();
+    // config WDT
+    bootloader_config_wdt();
+    // enable RNG early entropy source
+    bootloader_enable_random();
+err:
+    return ret;
+}

components/bootloader_support/src/esp32c6/bootloader_sha.c

@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "bootloader_sha.h"
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <sys/param.h>
+
+#include "esp32c6/rom/sha.h"
+
+static SHA_CTX ctx;
+
+bootloader_sha256_handle_t bootloader_sha256_start()
+{
+    // Enable SHA hardware
+    ets_sha_enable();
+    ets_sha_init(&ctx, SHA2_256);
+    return &ctx; // Meaningless non-NULL value
+}
+
+void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
+{
+    assert(handle != NULL);
+    assert(data_len % 4 == 0);
+    ets_sha_update(&ctx, data, data_len, false);
+}
+
+void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
+{
+    assert(handle != NULL);
+
+    if (digest == NULL) {
+        bzero(&ctx, sizeof(ctx));
+        return;
+    }
+    ets_sha_finish(&ctx, digest);
+}

components/bootloader_support/src/esp32c6/bootloader_soc.c

@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/lp_analog_peri_reg.h"
+
+void bootloader_ana_bod_reset_config(bool enable)
+{
+    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
+    if (enable) {
+        REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
+    } else {
+        REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
+    }
+}
+
+void bootloader_ana_clock_glitch_reset_config(bool enable)
+{
+    REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
+    if (enable) {
+        REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
+    } else {
+        REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
+    }
+}

components/bootloader_support/src/esp32c6/flash_encryption_secure_features.c

@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "flash_encrypt";
+
+esp_err_t esp_flash_encryption_enable_secure_features(void)
+{
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
+    ESP_LOGI(TAG, "Disable UART bootloader encryption...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
+#endif
+
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
+    ESP_LOGI(TAG, "Disable UART bootloader cache...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
+    // This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
+    // otherwise the Flash Encryption key cannot be read protected
+    esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+#endif
+
+    return ESP_OK;
+}

components/bootloader_support/src/esp32c6/secure_boot_secure_features.c

@@ -0,0 +1,70 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "secure_boot";
+
+esp_err_t esp_secure_boot_enable_secure_features(void)
+{
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Enabling Security download mode...");
+    esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not enable Security download mode...");
+        return err;
+    }
+#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Disable ROM Download mode...");
+    esp_err_t err = esp_efuse_disable_rom_download_mode();
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Could not disable ROM Download mode...");
+        return err;
+    }
+#else
+    ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable hardware & software JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+    esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
+
+#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
+    bool rd_dis_now = true;
+#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
+    /* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
+       when Flash Encryption is being enabled */
+    rd_dis_now = esp_flash_encryption_enabled();
+#endif
+    if (rd_dis_now) {
+        ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
+        esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
+    }
+#else
+    ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
+#endif
+
+    return ESP_OK;
+}

components/bootloader_support/src/esp_image_format.c

@@ -34,6 +34,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/rtc.h"
 #include "esp32c2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/rtc.h"
+#include "esp32c6/rom/secure_boot.h"
 #endif
 
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))

components/bootloader_support/src/flash_encrypt.c

@@ -142,7 +142,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
             if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
                 mode = ESP_FLASH_ENC_MODE_RELEASE;
             }
-#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
             bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
             bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
             if (dis_dl_enc && dis_dl_icache) {
@@ -191,7 +191,7 @@ void esp_flash_encryption_set_release_mode(void)
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
-#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
 #ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED

components/bootloader_support/src/flash_encryption/flash_encrypt.c

@@ -429,7 +429,11 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length)
         return ESP_FAIL;
     }
 
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
+    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
+#else
     wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#endif
     for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) {
         wdt_hal_write_protect_disable(&rtc_wdt_ctx);
         wdt_hal_feed(&rtc_wdt_ctx);

components/driver/deprecated/driver/adc_types_legacy.h

@@ -61,7 +61,7 @@ typedef enum {
     ADC1_CHANNEL_9,     /*!< ADC1 channel 9 is GPIO10 */
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
 typedef enum {
     ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
     ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO1 */
@@ -86,7 +86,7 @@ typedef enum {
     ADC2_CHANNEL_9,     /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */
     ADC2_CHANNEL_MAX,
 } adc2_channel_t;
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
 typedef enum {
     ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */
     ADC2_CHANNEL_MAX,

components/efuse/efuse_table_gen.py

@@ -488,7 +488,7 @@ def main():
 
     parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
     parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3',
-                        'esp32h2', 'esp32c2'], default='esp32')
+                        'esp32h2', 'esp32c2', 'esp32c6'], default='esp32')
     parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
     parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false')
     parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true')

components/efuse/esp32c6/esp_efuse_fields.c

@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_efuse.h"
+#include "esp_efuse_utility.h"
+#include "esp_efuse_table.h"
+#include "stdlib.h"
+#include "esp_types.h"
+#include "esp32c6/rom/efuse.h"
+#include "assert.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "soc/efuse_periph.h"
+#include "bootloader_random.h"
+#include "sys/param.h"
+
+static __attribute__((unused)) const char *TAG = "efuse";
+
+// Contains functions that provide access to efuse fields which are often used in IDF.
+
+// Returns chip package from efuse
+uint32_t esp_efuse_get_pkg_ver(void)
+{
+    uint32_t pkg_ver = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
+    return pkg_ver;
+}
+
+
+esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
+{
+    int cur_log_scheme = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
+    if (!cur_log_scheme) { // not burned yet
+        return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
+    } else {
+        return ESP_ERR_INVALID_STATE;
+    }
+}
+
+esp_err_t esp_efuse_disable_rom_download_mode(void)
+{
+    return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
+}
+
+esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
+{
+    if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
+}

components/efuse/esp32c6/esp_efuse_rtc_calib.c

@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp_bit_defs.h>
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+
+int esp_efuse_rtc_calib_get_ver(void)
+{
+    uint32_t result = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &result, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
+    return result;
+}
+
+uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
+{
+    assert(version == 1);
+    (void) adc_unit;
+    const esp_efuse_desc_t** init_code_efuse;
+    assert(atten < 4);
+    if (atten == 0) {
+        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0;
+    } else if (atten == 1) {
+        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1;
+    } else if (atten == 2) {
+        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2;
+    } else {
+        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3;
+    }
+
+    int init_code_size = esp_efuse_get_field_size(init_code_efuse);
+    assert(init_code_size == 10);
+
+    uint32_t init_code = 0;
+    ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
+    return init_code + 1000;    // version 1 logic
+}
+
+esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
+{
+    const esp_efuse_desc_t** cal_vol_efuse;
+    uint32_t calib_vol_expected_mv;
+    if (version != 1) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (atten >= 4) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (atten == 0) {
+        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0;
+        calib_vol_expected_mv = 400;
+    } else if (atten == 1) {
+        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1;
+        calib_vol_expected_mv = 550;
+    } else if (atten == 2) {
+        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2;
+        calib_vol_expected_mv = 750;
+    } else {
+        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3;
+        calib_vol_expected_mv = 1370;
+    }
+
+    assert(cal_vol_efuse[0]->bit_count == 10);
+
+    uint32_t cal_vol = 0;
+    ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count));
+
+    *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol);
+    *out_vol_mv = calib_vol_expected_mv;
+    return ESP_OK;
+}
+
+esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
+{
+    uint32_t version = esp_efuse_rtc_calib_get_ver();
+    if (version != 1) {
+        *tsens_cal = 0.0;
+        return ESP_ERR_NOT_SUPPORTED;
+    }
+    const esp_efuse_desc_t** cal_temp_efuse;
+    cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
+    int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
+    assert(cal_temp_size == 9);
+
+    uint32_t cal_temp = 0;
+    esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
+    assert(err == ESP_OK);
+    (void)err;
+    // BIT(8) stands for sign: 1: negtive, 0: positive
+    *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
+    return ESP_OK;
+}

components/efuse/esp32c6/esp_efuse_table.csv

@@ -0,0 +1,178 @@
+# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1..-)     |        #
+#                   |     EFUSE_BLK1  |            |MAX_BLK_LEN*|        #
+#                   |        ...      |            |            |        #
+#                   |     EFUSE_BLK10)|            |            |        #
+##########################################################################
+# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
+# !!!!!!!!!!! #
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
+# this will generate new source files, next rebuild all the sources.
+# !!!!!!!!!!! #
+
+# EFUSE_RD_REPEAT_DATA BLOCK #
+##############################
+    # EFUSE_RD_WR_DIS_REG #
+        WR_DIS,                           EFUSE_BLK0,   0,    32,     Write protection
+            WR_DIS.RD_DIS,                EFUSE_BLK0,   0,    1,      Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
+            WR_DIS.SWAP_UART_SDIO_EN,     EFUSE_BLK0,   1,    1,      Write protection for SWAP_UART_SDIO_EN
+            WR_DIS.GROUP_1,               EFUSE_BLK0,   2,    1,      Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
+            WR_DIS.GROUP_2,               EFUSE_BLK0,   3,    1,      Write protection for WDT_DELAY_SEL
+            WR_DIS.SPI_BOOT_CRYPT_CNT,    EFUSE_BLK0,   4,    1,      Write protection for SPI_BOOT_CRYPT_CNT
+            WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0,  5,    1,      Write protection for SECURE_BOOT_KEY_REVOKE0
+            WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0,  6,    1,      Write protection for SECURE_BOOT_KEY_REVOKE1
+            WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0,  7,    1,      Write protection for SECURE_BOOT_KEY_REVOKE2
+            WR_DIS.KEY0_PURPOSE,          EFUSE_BLK0,   8,    1,      Write protection for key_purpose. KEY0
+            WR_DIS.KEY1_PURPOSE,          EFUSE_BLK0,   9,    1,      Write protection for key_purpose. KEY1
+            WR_DIS.KEY2_PURPOSE,          EFUSE_BLK0,  10,    1,      Write protection for key_purpose. KEY2
+            WR_DIS.KEY3_PURPOSE,          EFUSE_BLK0,  11,    1,      Write protection for key_purpose. KEY3
+            WR_DIS.KEY4_PURPOSE,          EFUSE_BLK0,  12,    1,      Write protection for key_purpose. KEY4
+            WR_DIS.KEY5_PURPOSE,          EFUSE_BLK0,  13,    1,      Write protection for key_purpose. KEY5
+            WR_DIS.SEC_DPA_LEVEL,         EFUSE_BLK0,  14,    1,      Write protection for SEC_DPA_LEVEL
+            WR_DIS.SECURE_BOOT_EN,        EFUSE_BLK0,  15,    1,      Write protection for SECURE_BOOT_EN
+            WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1,   Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
+            WR_DIS.GROUP_3,               EFUSE_BLK0,  18,    1,      Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
+            WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,EFUSE_BLK0, 19, 1,   Write protection for SECURE_BOOT_DISABLE_FAST_WAKE
+            WR_DIS.BLK1,                  EFUSE_BLK0,  20,    1,      Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
+            WR_DIS.SYS_DATA_PART1,        EFUSE_BLK0,  21,    1,      Write protection for EFUSE_BLK2.  SYS_DATA_PART1
+            WR_DIS.USER_DATA,             EFUSE_BLK0,  22,    1,      Write protection for EFUSE_BLK3.  USER_DATA
+            WR_DIS.KEY0,                  EFUSE_BLK0,  23,    1,      Write protection for EFUSE_BLK4.  KEY0
+            WR_DIS.KEY1,                  EFUSE_BLK0,  24,    1,      Write protection for EFUSE_BLK5.  KEY1
+            WR_DIS.KEY2,                  EFUSE_BLK0,  25,    1,      Write protection for EFUSE_BLK6.  KEY2
+            WR_DIS.KEY3,                  EFUSE_BLK0,  26,    1,      Write protection for EFUSE_BLK7.  KEY3
+            WR_DIS.KEY4,                  EFUSE_BLK0,  27,    1,      Write protection for EFUSE_BLK8.  KEY4
+            WR_DIS.KEY5,                  EFUSE_BLK0,  28,    1,      Write protection for EFUSE_BLK9.  KEY5
+            WR_DIS.SYS_DATA_PART2,        EFUSE_BLK0,  29,    1,      Write protection for EFUSE_BLK10. SYS_DATA_PART2
+
+    # EFUSE_RD_REPEAT_DATA0_REG #
+        RD_DIS,                           EFUSE_BLK0,   32,    7,     Read protection
+            RD_DIS.KEY0,                  EFUSE_BLK0,   32,    1,     Read protection for EFUSE_BLK4.  KEY0
+            RD_DIS.KEY1,                  EFUSE_BLK0,   33,    1,     Read protection for EFUSE_BLK5.  KEY1
+            RD_DIS.KEY2,                  EFUSE_BLK0,   34,    1,     Read protection for EFUSE_BLK6.  KEY2
+            RD_DIS.KEY3,                  EFUSE_BLK0,   35,    1,     Read protection for EFUSE_BLK7.  KEY3
+            RD_DIS.KEY4,                  EFUSE_BLK0,   36,    1,     Read protection for EFUSE_BLK8.  KEY4
+            RD_DIS.KEY5,                  EFUSE_BLK0,   37,    1,     Read protection for EFUSE_BLK9.  KEY5
+            RD_DIS.SYS_DATA_PART2,        EFUSE_BLK0,   38,    1,     Read protection for EFUSE_BLK10. SYS_DATA_PART2
+        SWAP_UART_SDIO_EN,                EFUSE_BLK0,   39,    1,     Swap pad of uart and sdio.
+        DIS_ICACHE,                       EFUSE_BLK0,   40,    1,     Disable Icache
+        DIS_USB_JTAG,                     EFUSE_BLK0,   41,    1,     Disable USB JTAG
+        DIS_DOWNLOAD_ICACHE,              EFUSE_BLK0,   42,    1,     Disable Icache in download mode
+        DIS_USB_SERIAL_JTAG,              EFUSE_BLK0,   43,    1,     Disable USB_SERIAL_JTAG
+        DIS_FORCE_DOWNLOAD,               EFUSE_BLK0,   44,    1,     Disable force chip go to download mode function
+        DIS_TWAI,                         EFUSE_BLK0,   46,    1,     Disable TWAI function
+        JTAG_SEL_ENABLE,                  EFUSE_BLK0,   47,    1,     Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+        SOFT_DIS_JTAG,                    EFUSE_BLK0,   48,    3,     Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
+        DIS_PAD_JTAG,                     EFUSE_BLK0,   51,    1,     Disable JTAG in the hard way. JTAG is disabled permanently.
+        DIS_DOWNLOAD_MANUAL_ENCRYPT,      EFUSE_BLK0,   52,    1,     Disable flash encryption when in download boot modes.
+        USB_DREFH,                        EFUSE_BLK0,   53,    2,     Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.
+        USB_DREFL,                        EFUSE_BLK0,   55,    2,     Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.
+        USB_EXCHG_PINS,                   EFUSE_BLK0,   57,    1,     Exchange D+ D- pins
+        VDD_SPI_AS_GPIO,                  EFUSE_BLK0,   58,    1,     Set this bit to vdd spi pin function as gpio
+
+
+    # EFUSE_RD_REPEAT_DATA1_REG #
+        WDT_DELAY_SEL,                    EFUSE_BLK0,   80,    2,     Select RTC WDT time out threshold
+        SPI_BOOT_CRYPT_CNT,               EFUSE_BLK0,   82,    3,     SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
+        SECURE_BOOT_KEY_REVOKE0,          EFUSE_BLK0,   85,    1,     Enable revoke first secure boot key
+        SECURE_BOOT_KEY_REVOKE1,          EFUSE_BLK0,   86,    1,     Enable revoke second secure boot key
+        SECURE_BOOT_KEY_REVOKE2,          EFUSE_BLK0,   87,    1,     Enable revoke third secure boot key
+        KEY_PURPOSE_0,                    EFUSE_BLK0,   88,    4,     Key0 purpose
+        KEY_PURPOSE_1,                    EFUSE_BLK0,   92,    4,     Key1 purpose
+
+    # EFUSE_RD_REPEAT_DATA2_REG #
+        KEY_PURPOSE_2,                    EFUSE_BLK0,   96,    4,     Key2 purpose
+        KEY_PURPOSE_3,                    EFUSE_BLK0,  100,    4,     Key3 purpose
+        KEY_PURPOSE_4,                    EFUSE_BLK0,  104,    4,     Key4 purpose
+        KEY_PURPOSE_5,                    EFUSE_BLK0,  108,    4,     Key5 purpose
+        SEC_DPA_LEVEL,                    EFUSE_BLK0,  112,    2,     Configures the clock random divide mode to determine the spa secure level
+        SECURE_BOOT_EN,                   EFUSE_BLK0,  116,    1,     Secure boot enable
+        SECURE_BOOT_AGGRESSIVE_REVOKE,    EFUSE_BLK0,  117,    1,     Enable aggressive secure boot revoke
+        FLASH_TPUW,                       EFUSE_BLK0,  124,    4,     Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
+
+    # EFUSE_RD_REPEAT_DATA3_REG #
+        DIS_DOWNLOAD_MODE,                EFUSE_BLK0,  128,    1,     Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
+        DIS_DIRECT_BOOT,                  EFUSE_BLK0,  129,    1,     Disable direct boot mode
+        DIS_USB_PRINT,                    EFUSE_BLK0,  130,    1,     Disable USB Print
+        DIS_USB_DOWNLOAD_MODE,            EFUSE_BLK0,  132,    1,     Disable download through USB
+        ENABLE_SECURITY_DOWNLOAD,         EFUSE_BLK0,  133,    1,     Enable security download mode
+        UART_PRINT_CONTROL,               EFUSE_BLK0,  134,    2,     b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
+        FORCE_SEND_RESUME,                EFUSE_BLK0,  141,    1,     Force ROM code to send a resume command during SPI boot
+        SECURE_VERSION,                   EFUSE_BLK0,  142,   16,     Secure version for anti-rollback
+
+    # EFUSE_RD_REPEAT_DATA4_REG #
+        DISABLE_WAFER_VERSION_MAJOR,      EFUSE_BLK0,  160,    1,      Disables check of wafer version major
+        DISABLE_BLK_VERSION_MAJOR,        EFUSE_BLK0,  161,    1,      Disables check of blk version major
+
+# MAC_SPI_SYS BLOCK#
+#######################
+    # RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
+        MAC_FACTORY,                          EFUSE_BLK1,   40,    8,     Factory MAC addr [0]
+        ,                                     EFUSE_BLK1,   32,    8,     Factory MAC addr [1]
+        ,                                     EFUSE_BLK1,   24,    8,     Factory MAC addr [2]
+        ,                                     EFUSE_BLK1,   16,    8,     Factory MAC addr [3]
+        ,                                     EFUSE_BLK1,    8,    8,     Factory MAC addr [4]
+        ,                                     EFUSE_BLK1,    0,    8,     Factory MAC addr [5]
+        SPI_PAD_CONFIG_CLK,                   EFUSE_BLK1,   48,    6,     SPI_PAD_configure CLK
+        SPI_PAD_CONFIG_Q_D1,                  EFUSE_BLK1,   54,    6,     SPI_PAD_configure Q(D1)
+        SPI_PAD_CONFIG_D_D0,                  EFUSE_BLK1,   60,    6,     SPI_PAD_configure D(D0)
+        SPI_PAD_CONFIG_CS,                    EFUSE_BLK1,   66,    6,     SPI_PAD_configure CS
+        SPI_PAD_CONFIG_HD_D3,                 EFUSE_BLK1,   72,    6,     SPI_PAD_configure HD(D3)
+        SPI_PAD_CONFIG_WP_D2,                 EFUSE_BLK1,   78,    6,     SPI_PAD_configure WP(D2)
+        SPI_PAD_CONFIG_DQS,                   EFUSE_BLK1,   84,    6,     SPI_PAD_configure DQS
+        SPI_PAD_CONFIG_D4,                    EFUSE_BLK1,   90,    6,     SPI_PAD_configure D4
+        SPI_PAD_CONFIG_D5,                    EFUSE_BLK1,   96,    6,     SPI_PAD_configure D5
+
+    # RD_MAC_SPI_SYS_3
+        SPI_PAD_CONFIG_D6,                    EFUSE_BLK1,  102,    6,     SPI_PAD_configure D6
+        SPI_PAD_CONFIG_D7,                    EFUSE_BLK1,  108,    6,     SPI_PAD_configure D7
+        WAFER_VERSION_MINOR,                  EFUSE_BLK1,  114,    3,     WAFER_VERSION_MINOR least significant bits
+        ,                                     EFUSE_BLK1,  183,    1,     WAFER_VERSION_MINOR most significant bit
+        # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
+        PKG_VERSION,                          EFUSE_BLK1,  117,    3,     Package version 0:ESP32C3
+        BLK_VERSION_MINOR,                    EFUSE_BLK1,  120,    3,     BLK_VERSION_MINOR
+
+    # RD_MAC_SPI_SYS_5
+        # WAFER_VERSION_MINOR most significant bit
+        WAFER_VERSION_MAJOR,                  EFUSE_BLK1,  184,    2,     WAFER_VERSION_MAJOR
+
+# SYS_DATA_PART1 BLOCK# - System configuration
+#######################
+    # RD_SYS_PART1_DATA0 - rd_sys_part1_data3
+        OPTIONAL_UNIQUE_ID,                   EFUSE_BLK2,    0,  128,     Optional unique 128-bit ID
+
+    # RD_SYS_PART1_DATA4
+        BLK_VERSION_MAJOR,                    EFUSE_BLK2,  128,    2,     BLK_VERSION_MAJOR of BLOCK2
+        TEMP_CALIB,                           EFUSE_BLK2,  131,    9,     Temperature calibration data
+        OCODE,                                EFUSE_BLK2,  140,    8,     ADC OCode
+        ADC1_INIT_CODE_ATTEN0,                EFUSE_BLK2,  148,   10,     ADC1 init code at atten0
+        ADC1_INIT_CODE_ATTEN1,                EFUSE_BLK2,  158,   10,     ADC1 init code at atten1
+
+    # RD_SYS_PART1_DATA5
+        ADC1_INIT_CODE_ATTEN2,                EFUSE_BLK2,  168,   10,     ADC1 init code at atten2
+        ADC1_INIT_CODE_ATTEN3,                EFUSE_BLK2,  178,   10,     ADC1 init code at atten3
+        ADC1_CAL_VOL_ATTEN0,                  EFUSE_BLK2,  188,   10,     ADC1 calibration voltage at atten0
+        ADC1_CAL_VOL_ATTEN1,                  EFUSE_BLK2,  198,   10,     ADC1 calibration voltage at atten1
+        ADC1_CAL_VOL_ATTEN2,                  EFUSE_BLK2,  208,   10,     ADC1 calibration voltage at atten2
+        ADC1_CAL_VOL_ATTEN3,                  EFUSE_BLK2,  218,   10,     ADC1 calibration voltage at atten3
+
+################
+USER_DATA,                                EFUSE_BLK3,    0,  256,     User data
+USER_DATA.MAC_CUSTOM,                     EFUSE_BLK3,  200,   48,     Custom MAC
+
+################
+KEY0,                                     EFUSE_BLK4,    0,  256,     Key0 or user data
+KEY1,                                     EFUSE_BLK5,    0,  256,     Key1 or user data
+KEY2,                                     EFUSE_BLK6,    0,  256,     Key2 or user data
+KEY3,                                     EFUSE_BLK7,    0,  256,     Key3 or user data
+KEY4,                                     EFUSE_BLK8,    0,  256,     Key4 or user data
+KEY5,                                     EFUSE_BLK9,    0,  256,     Key5 or user data
+SYS_DATA_PART2,                           EFUSE_BLK10,   0,  256,     System configuration
+
+# AUTO CONFIG DIG&RTC DBIAS#
+################
+K_RTC_LDO,                              EFUSE_BLK1,    135,    7,      BLOCK1 K_RTC_LDO
+K_DIG_LDO,                              EFUSE_BLK1,    142,    7,      BLOCK1 K_DIG_LDO
+V_RTC_DBIAS20,                          EFUSE_BLK1,    149,    8,      BLOCK1 voltage of rtc dbias20
+V_DIG_DBIAS20,                          EFUSE_BLK1,    157,    8,      BLOCK1 voltage of digital dbias20
+DIG_DBIAS_HVT,                          EFUSE_BLK1,    165,    5,      BLOCK1 digital dbias when hvt
+THRES_HVT,                              EFUSE_BLK1,    170,    10,     BLOCK1 pvt threshold when hvt

components/efuse/esp32c6/esp_efuse_utility.c

@@ -0,0 +1,215 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/param.h>
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "assert.h"
+#include "esp_efuse_utility.h"
+#include "soc/efuse_periph.h"
+#include "hal/efuse_hal.h"
+
+static const char *TAG = "efuse";
+
+#ifdef CONFIG_EFUSE_VIRTUAL
+extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
+#endif // CONFIG_EFUSE_VIRTUAL
+
+/*Range addresses to read blocks*/
+const esp_efuse_range_addr_t range_read_addr_blocks[] = {
+    {EFUSE_RD_WR_DIS_REG,       EFUSE_RD_REPEAT_DATA4_REG},      // range address of EFUSE_BLK0  REPEAT
+    {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG},      // range address of EFUSE_BLK1  MAC_SPI_8M
+    {EFUSE_RD_SYS_PART1_DATA0_REG,    EFUSE_RD_SYS_PART1_DATA7_REG},         // range address of EFUSE_BLK2  SYS_DATA
+    {EFUSE_RD_USR_DATA0_REG,    EFUSE_RD_USR_DATA7_REG},         // range address of EFUSE_BLK3  USR_DATA
+    {EFUSE_RD_KEY0_DATA0_REG,   EFUSE_RD_KEY0_DATA7_REG},        // range address of EFUSE_BLK4  KEY0
+    {EFUSE_RD_KEY1_DATA0_REG,   EFUSE_RD_KEY1_DATA7_REG},        // range address of EFUSE_BLK5  KEY1
+    {EFUSE_RD_KEY2_DATA0_REG,   EFUSE_RD_KEY2_DATA7_REG},        // range address of EFUSE_BLK6  KEY2
+    {EFUSE_RD_KEY3_DATA0_REG,   EFUSE_RD_KEY3_DATA7_REG},        // range address of EFUSE_BLK7  KEY3
+    {EFUSE_RD_KEY4_DATA0_REG,   EFUSE_RD_KEY4_DATA7_REG},        // range address of EFUSE_BLK8  KEY4
+    {EFUSE_RD_KEY5_DATA0_REG,   EFUSE_RD_KEY5_DATA7_REG},        // range address of EFUSE_BLK9  KEY5
+    {EFUSE_RD_SYS_PART2_DATA0_REG,   EFUSE_RD_SYS_PART2_DATA7_REG}         // range address of EFUSE_BLK10 KEY6
+};
+
+static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
+
+/*Range addresses to write blocks (it is not real regs, it is buffer) */
+const esp_efuse_range_addr_t range_write_addr_blocks[] = {
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
+};
+
+#ifndef CONFIG_EFUSE_VIRTUAL
+// Update Efuse timing configuration
+static esp_err_t esp_efuse_set_timing(void)
+{
+    // efuse clock is fixed.
+    // An argument (0) is for compatibility and will be ignored.
+    efuse_hal_set_timing(0);
+    return ESP_OK;
+}
+#endif // ifndef CONFIG_EFUSE_VIRTUAL
+
+// Efuse read operation: copies data from physical efuses to efuse read registers.
+void esp_efuse_utility_clear_program_registers(void)
+{
+    efuse_hal_read();
+    efuse_hal_clear_program_registers();
+}
+
+esp_err_t esp_efuse_utility_check_errors(void)
+{
+    return ESP_OK;
+}
+
+// Burn values written to the efuse write registers
+esp_err_t esp_efuse_utility_burn_chip(void)
+{
+    esp_err_t error = ESP_OK;
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
+    for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
+        int subblock = 0;
+        for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+            virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
+        }
+    }
+#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_utility_write_efuses_to_flash();
+#endif
+#else // CONFIG_EFUSE_VIRTUAL
+    if (esp_efuse_set_timing() != ESP_OK) {
+        ESP_LOGE(TAG, "Efuse fields are not burnt");
+    } else {
+        // Permanently update values written to the efuse write registers
+        // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
+        for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
+            bool need_burn_block = false;
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block) != 0) {
+                    need_burn_block = true;
+                    break;
+                }
+            }
+            if (!need_burn_block) {
+                continue;
+            }
+            if (error) {
+                // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
+                // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
+                ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
+                continue;
+            }
+            efuse_hal_clear_program_registers();
+            if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+                uint8_t block_rs[12];
+                efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstringop-overflow"
+#pragma GCC diagnostic ignored "-Warray-bounds"
+                memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
+#pragma GCC diagnostic pop
+            }
+            unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
+            unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
+            memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
+
+            uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
+#pragma GCC diagnostic push
+#if     __GNUC__ >= 11
+#pragma GCC diagnostic ignored "-Wstringop-overread"
+#endif
+#pragma GCC diagnostic ignored "-Warray-bounds"
+            memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
+#pragma GCC diagnostic pop
+            int repeat_burn_op = 1;
+            bool correct_written_data;
+            bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
+            if (coding_error_before) {
+                ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
+            }
+            bool coding_error_occurred;
+
+            do {
+                ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
+                efuse_hal_program(num_block); // BURN a block
+
+                bool coding_error_after;
+                for (unsigned i = 0; i < 5; i++) {
+                    efuse_hal_read();
+                    coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
+                    if (coding_error_after == true) {
+                        break;
+                    }
+                }
+                coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
+                if (coding_error_occurred) {
+                    ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
+                }
+
+                correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
+                if (!correct_written_data || coding_error_occurred) {
+                    ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstringop-overflow"
+#pragma GCC diagnostic ignored "-Warray-bounds"
+                    memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
+#pragma GCC diagnostic pop
+                }
+
+            } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
+
+            if (coding_error_occurred) {
+                ESP_LOGW(TAG, "Coding error was not fixed");
+                if (num_block == 0) {
+                    ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
+                    error = ESP_FAIL;
+                }
+            }
+            if (!correct_written_data) {
+                ESP_LOGE(TAG, "Written data are incorrect");
+                error = ESP_FAIL;
+            }
+        }
+    }
+#endif // CONFIG_EFUSE_VIRTUAL
+    esp_efuse_utility_reset();
+    return error;
+}
+
+// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
+// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
+// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
+// They will be filled during the burn operation.
+esp_err_t esp_efuse_utility_apply_new_coding_scheme()
+{
+    // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
+    for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
+        if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block)) {
+                    int num_reg = 0;
+                    for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
+                        if (esp_efuse_utility_read_reg(num_block, num_reg)) {
+                            ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
+                            return ESP_ERR_CODING;
+                        }
+                    }
+                    break;
+                }
+            }
+        }
+    }
+    return ESP_OK;
+}

components/efuse/esp32c6/include/esp_efuse_chip.h

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Type of eFuse blocks ESP32C6
+ */
+typedef enum {
+    EFUSE_BLK0                 = 0,   /**< Number of eFuse BLOCK0. REPEAT_DATA */
+
+    EFUSE_BLK1                 = 1,   /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
+
+    EFUSE_BLK2                 = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+    EFUSE_BLK_SYS_DATA_PART1   = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+
+    EFUSE_BLK3                 = 3,   /**< Number of eFuse BLOCK3. USER_DATA*/
+    EFUSE_BLK_USER_DATA        = 3,   /**< Number of eFuse BLOCK3. USER_DATA*/
+
+    EFUSE_BLK4                 = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+    EFUSE_BLK_KEY0             = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+
+    EFUSE_BLK5                 = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+    EFUSE_BLK_KEY1             = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+
+    EFUSE_BLK6                 = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+    EFUSE_BLK_KEY2             = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+
+    EFUSE_BLK7                 = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+    EFUSE_BLK_KEY3             = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+
+    EFUSE_BLK8                 = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+    EFUSE_BLK_KEY4             = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+
+    EFUSE_BLK9                 = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY5             = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY_MAX          = 10,
+
+    EFUSE_BLK10                = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+    EFUSE_BLK_SYS_DATA_PART2   = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+
+    EFUSE_BLK_MAX
+} esp_efuse_block_t;
+
+/**
+ * @brief Type of coding scheme
+ */
+typedef enum {
+    EFUSE_CODING_SCHEME_NONE    = 0,    /**< None */
+    EFUSE_CODING_SCHEME_RS      = 3,    /**< Reed-Solomon coding */
+} esp_efuse_coding_scheme_t;
+
+/**
+ * @brief Type of key purpose
+ */
+typedef enum {
+    ESP_EFUSE_KEY_PURPOSE_USER = 0,                         /**< User purposes (software-only use) */
+    ESP_EFUSE_KEY_PURPOSE_RESERVED = 1,                     /**< Reserved */
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,              /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,                /**< HMAC Downstream mode */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,               /**< JTAG soft enable key (uses HMAC Downstream mode) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,  /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8,                      /**< HMAC Upstream mode */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,          /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,         /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,         /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_MAX,                              /**< MAX PURPOSE */
+} esp_efuse_purpose_t;
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32c6/include/esp_efuse_rtc_calib.h

@@ -0,0 +1,59 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp_types.h>
+#include <esp_err.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//This is the ADC calibration value version burnt in efuse
+#define ESP_EFUSE_ADC_CALIB_VER     1
+
+/**
+ * @brief Get the RTC calibration efuse version
+ *
+ * @return Version of the stored efuse
+ */
+int esp_efuse_rtc_calib_get_ver(void);
+
+/**
+ * @brief Get the init code in the efuse, for the corresponding attenuation.
+ *
+ * @param version   Version of the stored efuse
+ * @param adc_unit  ADC unit. Not used, for compatibility. On esp32c6, for calibration v1, both ADC units use the same init code (calibrated by ADC1)
+ * @param atten     Attenuation of the init code
+ * @return The init code stored in efuse
+ */
+uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten);
+
+/**
+ * @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
+ *
+ * @param version Version of the stored efuse
+ * @param atten         Attenuation to use
+ * @param out_digi      Output buffer of the digits
+ * @param out_vol_mv    Output of the voltage, in mV
+ * @return
+ *      - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
+ *      - ESP_OK: if success
+ */
+esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
+
+/**
+ * @brief Get the temperature sensor calibration number delta_T stored in the efuse.
+ *
+ * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse.
+ *
+ * @return ESP_OK if get the calibration value successfully.
+ *         ESP_ERR_INVALID_ARG if can't get the calibration value.
+ */
+esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal);
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32c6/include/esp_efuse_table.h

@@ -0,0 +1,144 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_efuse.h"
+
+// md5_digest_table 5b3b6e026d28aacca6dc3b96be8bd280
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
+extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
+extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
+extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32c6/private_include/esp_efuse_utility.h

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define COUNT_EFUSE_REG_PER_BLOCK 8      /* The number of registers per block. */
+
+#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
+
+#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32c6/sources.cmake

@@ -0,0 +1,4 @@
+set(EFUSE_SOC_SRCS  "esp_efuse_table.c"
+                    "esp_efuse_fields.c"
+                    "esp_efuse_rtc_calib.c"
+                    "esp_efuse_utility.c")

components/efuse/src/esp_efuse_fields.c

@@ -16,7 +16,6 @@
 #include "esp_log.h"
 #include "soc/efuse_periph.h"
 #include "bootloader_random.h"
-#include "soc/syscon_reg.h"
 #include "sys/param.h"
 
 static __attribute__((unused)) const char *TAG = "efuse";

components/esp_adc/CMakeLists.txt

@@ -27,6 +27,15 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/deprecated/${target}/esp_adc_cal_legacy.c
     list(APPEND srcs "deprecated/${target}/esp_adc_cal_legacy.c")
 endif()
 
+# ESP32C6-TODO
+if(CONFIG_IDF_TARGET_ESP32C6)
+    list(REMOVE_ITEM srcs
+            "adc_cali_curve_fitting.c" # TODO: IDF-5312
+            "adc_oneshot.c"            # TODO: IDF-5310
+            "adc_common.c"
+        )
+endif()
+
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${includes}
                        PRIV_REQUIRES driver efuse

components/esp_adc/esp32c6/include/adc_cali_schemes.h

@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file adc_cali_schemes.h
+ *
+ * @brief Supported calibration schemes
+ */
+
+//Now no scheme supported

components/esp_gdbstub/esp32c6/gdbstub_esp32c6.c

@@ -0,0 +1,140 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include "soc/uart_periph.h"
+#include "soc/gpio_periph.h"
+#include "soc/soc.h"
+#include "soc/usb_serial_jtag_struct.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "esp_gdbstub_common.h"
+#include "sdkconfig.h"
+
+#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
+
+#define GDBSTUB_MEM_REGION_COUNT 9
+
+#define UART_REG_FIELD_LEN 0x84
+
+typedef struct {
+    intptr_t lower;
+    intptr_t upper;
+} mem_bound_t;
+
+static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] =
+{
+    {SOC_DROM_LOW, SOC_DROM_HIGH},
+    {SOC_IROM_LOW, SOC_IROM_HIGH},
+    {SOC_IRAM_LOW, SOC_IRAM_HIGH},
+    {SOC_DRAM_LOW, SOC_DRAM_HIGH},
+    {SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH},
+    {SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH},
+    {SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH},
+    // RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them
+    // We shouldn't read the uart registers since it will disturb the debugging via UART,
+    // so skip UART part of the peripheral registers.
+    {DR_REG_UART_BASE + UART_REG_FIELD_LEN, SOC_PERIPHERAL_HIGH},
+    {SOC_DEBUG_LOW, SOC_DEBUG_HIGH},
+};
+
+static inline bool check_inside_valid_region(intptr_t addr)
+{
+    for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) {
+        if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+void esp_gdbstub_target_init()
+{
+}
+
+#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
+
+int esp_gdbstub_getchar()
+{
+    uint8_t c;
+    //retry the read until we succeed
+    while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ;
+    return c;
+}
+
+void esp_gdbstub_putchar(int c)
+{
+    uint8_t cc=c;
+    //retry the write until we succeed
+    while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ;
+}
+
+void esp_gdbstub_flush()
+{
+    usb_serial_jtag_ll_txfifo_flush();
+}
+
+
+#else
+
+//assume UART gdbstub channel
+
+int esp_gdbstub_getchar()
+{
+    while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) {
+        ;
+    }
+    return REG_READ(UART_FIFO_AHB_REG(UART_NUM));
+}
+
+void esp_gdbstub_putchar(int c)
+{
+    while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) {
+        ;
+    }
+    REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
+}
+
+void esp_gdbstub_flush()
+{
+    //not needed for uart
+}
+
+#endif
+
+int esp_gdbstub_readmem(intptr_t addr)
+{
+    if (!check_inside_valid_region(addr)) {
+        /* see esp_cpu_configure_region_protection */
+        return -1;
+    }
+    uint32_t val_aligned = *(uint32_t *)(addr & (~3));
+    uint32_t shift = (addr & 3) * 8;
+    return (val_aligned >> shift) & 0xff;
+}
+
+int esp_gdbstub_writemem(unsigned int addr, unsigned char data)
+{
+    if (!check_inside_valid_region(addr)) {
+        /* see esp_cpu_configure_region_protection */
+        return -1;
+    }
+
+    int *i = (int *)(addr & (~3));
+    if ((addr & 3) == 0) {
+        *i = (*i & 0xffffff00) | (data << 0);
+    }
+    if ((addr & 3) == 1) {
+        *i = (*i & 0xffff00ff) | (data << 8);
+    }
+    if ((addr & 3) == 2) {
+        *i = (*i & 0xff00ffff) | (data << 16);
+    }
+    if ((addr & 3) == 3) {
+        *i = (*i & 0x00ffffff) | (data << 24);
+    }
+    return 0;
+}

components/esp_gdbstub/esp32c6/gdbstub_target_config.h

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once

components/esp_gdbstub/src/gdbstub.c

@@ -114,7 +114,11 @@ static uint32_t gdbstub_hton(uint32_t i)
     return __builtin_bswap32(i);
 }
 
+#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
 static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#else
+static wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
+#endif
 static wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
 static wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
 

components/esp_hw_support/CMakeLists.txt

@@ -45,6 +45,13 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "port/${target}/systimer.c")
     endif()
 
+    # ESP32C6-TODO
+    if(CONFIG_IDF_TARGET_ESP32C6)
+        list(REMOVE_ITEM srcs
+                "adc_share_hw_ctrl.c" # TODO: IDF-5312
+            )
+    endif()
+
 else()
     # Requires "_esp_error_check_failed()" function
     list(APPEND priv_requires "esp_system")

components/esp_hw_support/Kconfig

@@ -40,7 +40,7 @@ menu "Hardware Settings"
 
         config ESP_SLEEP_GPIO_RESET_WORKAROUND
             bool "light sleep GPIO reset workaround"
-            default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+            default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 # TODO: IDF-5641 (esp32c6)
             select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
             help
                 esp32c2, esp32c3 and esp32s3 will reset at wake-up if GPIO is received a small electrostatic
@@ -165,6 +165,7 @@ menu "Hardware Settings"
 
         config MMU_PAGE_MODE
             string
+            default "8KB" if MMU_PAGE_SIZE_8KB
             default "16KB" if MMU_PAGE_SIZE_16KB
             default "32KB" if MMU_PAGE_SIZE_32KB
             default "64KB" if MMU_PAGE_SIZE_64KB
@@ -176,6 +177,7 @@ menu "Hardware Settings"
             # use of small flash sizes (reducing the wasted space due to alignment), we
             # need to use the smallest possible MMU page size for the given flash size.
             hex
+            default 0x2000 if MMU_PAGE_SIZE_8KB
             default 0x4000 if MMU_PAGE_SIZE_16KB
             default 0x8000 if MMU_PAGE_SIZE_32KB
             default 0x10000 if MMU_PAGE_SIZE_64KB

components/esp_hw_support/cpu.c

@@ -9,7 +9,17 @@
 #include <assert.h>
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
+
+// TODO: IDF-5645
+#if CONFIG_IDF_TARGET_ESP32C6
+#include "soc/lp_aon_reg.h"
+#include "soc/pcr_reg.h"
+#define SYSTEM_CPU_PER_CONF_REG PCR_CPU_WAITI_CONF_REG
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON PCR_CPU_WAIT_MODE_FORCE_ON
+#else
 #include "soc/rtc_cntl_reg.h"
+#endif
+
 #include "hal/soc_hal.h"
 #include "hal/mpu_hal.h"
 #include "esp_bit_defs.h"
@@ -81,6 +91,9 @@ void esp_cpu_unstall(int core_id)
 
 void esp_cpu_reset(int core_id)
 {
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
+    SET_PERI_REG_MASK(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET);
+#else
     assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
 #if SOC_CPU_CORES_NUM > 1
     /*
@@ -93,6 +106,7 @@ void esp_cpu_reset(int core_id)
     int rtc_cntl_rst_m = RTC_CNTL_SW_PROCPU_RST_M;
 #endif // SOC_CPU_CORES_NUM > 1
     SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst_m);
+#endif
 }
 
 void esp_cpu_wait_for_intr(void)
@@ -100,6 +114,7 @@ void esp_cpu_wait_for_intr(void)
 #if __XTENSA__
     xt_utils_wait_for_intr();
 #else
+    // TODO: IDF-5645 (better to implement with ll) C6 register names converted in the #include section at the top
     if (esp_cpu_dbgr_is_attached() && DPORT_REG_GET_BIT(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON) == 0) {
         /* when SYSTEM_CPU_WAIT_MODE_FORCE_ON is disabled in WFI mode SBA access to memory does not work for debugger,
            so do not enter that mode when debugger is connected */
@@ -125,7 +140,13 @@ static bool is_intr_num_resv(int intr_num)
 {
     // Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt"
     // [TODO: IDF-2465]
-    const uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8);
+    uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8);
+
+    // int_num 0,3,4,7 are inavaliable for PULP cpu
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5728 replace with a better macro name
+    reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7);
+#endif
+
     if (reserved & BIT(intr_num)) {
         return true;
     }
@@ -501,6 +522,86 @@ void esp_cpu_configure_region_protection(void)
     PMP_ENTRY_CFG_SET(14, NONE);
     PMP_ENTRY_CFG_SET(15, PMP_TOR | NONE);
 }
+#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5642
+void esp_cpu_configure_region_protection(void)
+{
+    /* Notes on implementation:
+     *
+     * 1) Note: ESP32-C6 CPU doesn't support overlapping PMP regions
+     *
+     * 2) Therefore, we use TOR (top of range) entries to map the whole address
+     * space, bottom to top.
+     *
+     * 3) There are not enough entries to describe all the memory regions 100% accurately.
+     *
+     * 4) This means some gaps (invalid memory) are accessible. Priority for extending regions
+     * to cover gaps is to extend read-only or read-execute regions or read-only regions only
+     * (executing unmapped addresses should always fault with invalid instruction, read-only means
+     * stores will correctly fault even if reads may return some invalid value.)
+     *
+     * 5) Entries are grouped in order with some static asserts to try and verify everything is
+     * correct.
+     */
+    const unsigned NONE = PMP_L | PMP_TOR;
+    const unsigned RW      = PMP_L | PMP_TOR | PMP_R | PMP_W;
+    const unsigned RX      = PMP_L | PMP_TOR | PMP_R | PMP_X;
+    const unsigned RWX     = PMP_L | PMP_TOR | PMP_R | PMP_W | PMP_X;
+
+    // 1. Gap at bottom of address space
+    PMP_ENTRY_SET(0, SOC_DEBUG_LOW, NONE);
+
+    // 2. Debug region
+    PMP_ENTRY_SET(1, SOC_DEBUG_HIGH, RWX);
+    _Static_assert(SOC_DEBUG_LOW < SOC_DEBUG_HIGH, "Invalid CPU debug region");
+
+    // 3. Gap between debug region & IROM
+    PMP_ENTRY_SET(2, SOC_IROM_MASK_LOW, NONE);
+    _Static_assert(SOC_DEBUG_HIGH < SOC_IROM_MASK_LOW, "Invalid PMP entry order");
+
+    // 4. ROM
+    PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, RX);
+    _Static_assert(SOC_IROM_MASK_LOW < SOC_DROM_MASK_HIGH, "Invalid ROM region");
+
+    // 5. Gap between ROM & RAM
+    PMP_ENTRY_SET(4, SOC_IRAM_LOW, NONE);
+    _Static_assert(SOC_DROM_MASK_HIGH < SOC_IRAM_LOW, "Invalid PMP entry order");
+
+    // 6. RAM
+    PMP_ENTRY_SET(5, SOC_IRAM_HIGH, RWX);
+    _Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
+
+    // 7. Gap between DRAM and I_Cache
+    PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
+    _Static_assert(SOC_IRAM_HIGH < SOC_IROM_LOW, "Invalid PMP entry order");
+
+    // 8. I_Cache (flash)
+    PMP_ENTRY_SET(7, SOC_IROM_HIGH, RWX);
+    _Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I_Cache region");
+
+    // 9. D_Cache (flash)
+    PMP_ENTRY_SET(8, SOC_DROM_HIGH, RW);
+    _Static_assert(SOC_DROM_LOW < SOC_DROM_HIGH, "Invalid D_Cache region");
+
+    // 10. Gap between D_Cache & LP_RAM
+    PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE);
+    _Static_assert(SOC_DROM_HIGH < SOC_RTC_IRAM_LOW, "Invalid PMP entry order");
+
+    // 16. LP memory
+    PMP_ENTRY_SET(10, SOC_RTC_IRAM_HIGH, RWX);
+    _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
+
+    // 17. Gap between LP memory & peripheral addresses
+    PMP_ENTRY_SET(11, SOC_PERIPHERAL_LOW, NONE);
+    _Static_assert(SOC_RTC_IRAM_HIGH < SOC_PERIPHERAL_LOW, "Invalid PMP entry order");
+
+    // 18. Peripheral addresses
+    PMP_ENTRY_SET(12, SOC_PERIPHERAL_HIGH, RW);
+    _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
+
+    // 19. End of address space
+    PMP_ENTRY_SET(13, UINT32_MAX, NONE); // all but last 4 bytes
+    PMP_ENTRY_SET(14, UINT32_MAX, PMP_L | PMP_NA4);  // last 4 bytes
+}
 #endif
 
 /* ---------------------------------------------------- Debugging ------------------------------------------------------

components/esp_hw_support/esp_clk.c

@@ -35,6 +35,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/rtc.h"
 #include "esp32c2/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/rtc.h"
+#include "esp32c6/rtc.h"
 #endif
 
 #define MHZ (1000000)
@@ -76,7 +79,7 @@ int IRAM_ATTR esp_clk_xtal_freq(void)
     return rtc_clk_xtal_freq_get() * MHZ;
 }
 
-#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESPS3
 void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
 {
     /* Update scale factors used by esp_rom_delay_us */

components/esp_hw_support/include/esp_chip_info.h

@@ -26,6 +26,7 @@ typedef enum {
     CHIP_ESP32C3 = 5, //!< ESP32-C3
     CHIP_ESP32H2 = 6, //!< ESP32-H2
     CHIP_ESP32C2 = 12, //!< ESP32-C2
+    CHIP_ESP32C6 = 13, //!< ESP32-C6
 } esp_chip_model_t;
 
 /* Chip feature flags, used in esp_chip_info_t */

components/esp_hw_support/include/esp_mac.h

@@ -41,6 +41,8 @@ typedef enum {
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H2_UNIVERSAL_MAC_ADDRESSES
 #elif CONFIG_IDF_TARGET_ESP32C2
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C2_UNIVERSAL_MAC_ADDRESSES
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES
 #endif
 /** @endcond */
 

components/esp_hw_support/include/esp_memory_utils.h

@@ -69,7 +69,12 @@ inline static bool esp_ptr_in_diram_dram(const void *p) {
  */
 __attribute__((always_inline))
 inline static bool esp_ptr_in_diram_iram(const void *p) {
+// TODO: IDF-5980 esp32c6 D/I RAM share the same address
+#if SOC_DIRAM_IRAM_LOW == SOC_DIRAM_DRAM_LOW
+    return false;
+#else
     return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
+#endif
 }
 
 /**

components/esp_hw_support/include/soc/esp32c6/esp_crypto_lock.h

@@ -0,0 +1,68 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Acquire lock for HMAC cryptography peripheral
+ *
+ * Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral
+ */
+void esp_crypto_hmac_lock_acquire(void);
+
+/**
+ * @brief Release lock for HMAC cryptography peripheral
+ *
+ * Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral
+ */
+void esp_crypto_hmac_lock_release(void);
+
+/**
+ * @brief Acquire lock for DS cryptography peripheral
+ *
+ * Internally also locks the HMAC (which locks SHA), AES and MPI  peripheral, as the DS depends on these peripherals
+ */
+void esp_crypto_ds_lock_acquire(void);
+
+/**
+ * @brief Release lock for DS cryptography peripheral
+ *
+ * Internally also releases the HMAC (which locks SHA), AES and MPI  peripheral, as the DS depends on these peripherals
+ */
+void esp_crypto_ds_lock_release(void);
+
+/**
+ * @brief Acquire lock for the SHA and AES cryptography peripheral.
+ *
+ */
+void esp_crypto_sha_aes_lock_acquire(void);
+
+/**
+ * @brief Release lock for the SHA and AES cryptography peripheral.
+ *
+ */
+void esp_crypto_sha_aes_lock_release(void);
+
+
+/**
+ * @brief Acquire lock for the mpi cryptography peripheral.
+ *
+ */
+void esp_crypto_mpi_lock_acquire(void);
+
+/**
+ * @brief Release lock for the mpi/rsa cryptography peripheral.
+ *
+ */
+void esp_crypto_mpi_lock_release(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/include/soc/esp32c6/esp_ds.h

@@ -0,0 +1,220 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_hmac.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP32C6_ERR_HW_CRYPTO_DS_HMAC_FAIL           ESP_ERR_HW_CRYPTO_BASE + 0x1 /*!< HMAC peripheral problem */
+#define ESP32C6_ERR_HW_CRYPTO_DS_INVALID_KEY         ESP_ERR_HW_CRYPTO_BASE + 0x2 /*!< given HMAC key isn't correct,
+                                                                                HMAC peripheral problem */
+#define ESP32C6_ERR_HW_CRYPTO_DS_INVALID_DIGEST      ESP_ERR_HW_CRYPTO_BASE + 0x4 /*!< message digest check failed,
+                                                                                result is invalid */
+#define ESP32C6_ERR_HW_CRYPTO_DS_INVALID_PADDING     ESP_ERR_HW_CRYPTO_BASE + 0x5 /*!< padding check failed, but result
+                                                                                   is produced anyway and can be read*/
+
+#define ESP_DS_IV_BIT_LEN 128
+#define ESP_DS_IV_LEN (ESP_DS_IV_BIT_LEN / 8)
+#define ESP_DS_SIGNATURE_MAX_BIT_LEN 3072
+#define ESP_DS_SIGNATURE_MD_BIT_LEN 256
+#define ESP_DS_SIGNATURE_M_PRIME_BIT_LEN 32
+#define ESP_DS_SIGNATURE_L_BIT_LEN 32
+#define ESP_DS_SIGNATURE_PADDING_BIT_LEN 64
+
+/* Length of parameter 'C' stored in flash, in bytes
+   - Operands Y, M and r_bar; each 3072 bits
+   - Operand MD (message digest); 256 bits
+   - Operands M' and L; each 32 bits
+   - Operand beta (padding value; 64 bits
+*/
+#define ESP_DS_C_LEN (((ESP_DS_SIGNATURE_MAX_BIT_LEN * 3 \
+        + ESP_DS_SIGNATURE_MD_BIT_LEN   \
+        + ESP_DS_SIGNATURE_M_PRIME_BIT_LEN   \
+        + ESP_DS_SIGNATURE_L_BIT_LEN   \
+        + ESP_DS_SIGNATURE_PADDING_BIT_LEN) / 8))
+
+typedef struct esp_ds_context esp_ds_context_t;
+
+typedef enum {
+    ESP_DS_RSA_1024 = (1024 / 32) - 1,
+    ESP_DS_RSA_2048 = (2048 / 32) - 1,
+    ESP_DS_RSA_3072 = (3072 / 32) - 1
+} esp_digital_signature_length_t;
+
+/**
+ * Encrypted private key data. Recommended to store in flash in this format.
+ *
+ * @note This struct has to match to one from the ROM code! This documentation is mostly taken from there.
+ */
+typedef struct esp_digital_signature_data {
+    /**
+     * RSA LENGTH register parameters
+     * (number of words in RSA key & operands, minus one).
+     *
+     * Max value 127 (for RSA 3072).
+     *
+     * This value must match the length field encrypted and stored in 'c',
+     * or invalid results will be returned. (The DS peripheral will
+     * always use the value in 'c', not this value, so an attacker can't
+     * alter the DS peripheral results this way, it will just truncate or
+     * extend the message and the resulting signature in software.)
+     *
+     * @note In IDF, the enum type length is the same as of type unsigned, so they can be used interchangably.
+     *       See the ROM code for the original declaration of struct \c ets_ds_data_t.
+     */
+    esp_digital_signature_length_t rsa_length;
+
+    /**
+     * IV value used to encrypt 'c'
+     */
+    uint32_t iv[ESP_DS_IV_BIT_LEN / 32];
+
+    /**
+     * Encrypted Digital Signature parameters. Result of AES-CBC encryption
+     * of plaintext values. Includes an encrypted message digest.
+     */
+    uint8_t c[ESP_DS_C_LEN];
+} esp_ds_data_t;
+
+/**
+ * Plaintext parameters used by Digital Signature.
+ *
+ * This is only used for encrypting the RSA parameters by calling esp_ds_encrypt_params().
+ * Afterwards, the result can be stored in flash or in other persistent memory.
+ * The encryption is a prerequisite step before any signature operation can be done.
+ */
+typedef struct {
+    uint32_t  Y[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA exponent
+    uint32_t  M[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA modulus
+    uint32_t Rb[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; //!< RSA r inverse operand
+    uint32_t M_prime;                               //!< RSA M prime operand
+    uint32_t length;                                //!< RSA length in words (32 bit)
+} esp_ds_p_data_t;
+
+/**
+ * @brief Sign the message with a hardware key from specific key slot.
+ * The function calculates a plain RSA signature with help of the DS peripheral.
+ * The RSA encryption operation is as follows:
+ * Z = XY mod M where,
+ * Z is the signature, X is the input message,
+ * Y and M are the RSA private key parameters.
+ *
+ * This function is a wrapper around \c esp_ds_finish_sign() and \c esp_ds_start_sign(), so do not use them
+ * in parallel.
+ * It blocks until the signing is finished and then returns the signature.
+ *
+ * @note This function locks the HMAC, SHA, AES and RSA components during its entire execution time.
+ *
+ * @param message the message to be signed; its length should be (data->rsa_length + 1)*4 bytes
+ * @param data the encrypted signing key data (AES encrypted RSA key + IV)
+ * @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the
+ *        signing key data
+ * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long
+ *
+ * @return
+ *      - ESP_OK if successful, the signature was written to the parameter \c signature.
+ *      - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0
+ *      - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key
+ *      - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object
+ *      - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component
+ *      - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid.
+ *      - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though
+ *        since the message digest matches.
+ */
+esp_err_t esp_ds_sign(const void *message,
+        const esp_ds_data_t *data,
+        hmac_key_id_t key_id,
+        void *signature);
+
+/**
+ * @brief Start the signing process.
+ *
+ * This function yields a context object which needs to be passed to \c esp_ds_finish_sign() to finish the signing
+ * process.
+ * The function calculates a plain RSA signature with help of the DS peripheral.
+ * The RSA encryption operation is as follows:
+ * Z = XY mod M where,
+ * Z is the signature, X is the input message,
+ * Y and M are the RSA private key parameters.
+ *
+ * @note This function locks the HMAC, SHA, AES and RSA components, so the user has to ensure to call
+ *       \c esp_ds_finish_sign() in a timely manner.
+ *
+ * @param message the message to be signed; its length should be (data->rsa_length + 1)*4 bytes
+ * @param data the encrypted signing key data (AES encrypted RSA key + IV)
+ * @param key_id the HMAC key ID determining the HMAC key of the HMAC which will be used to decrypt the
+ *        signing key data
+ * @param esp_ds_ctx the context object which is needed for finishing the signing process later
+ *
+ * @return
+ *      - ESP_OK if successful, the ds operation was started now and has to be finished with \c esp_ds_finish_sign()
+ *      - ESP_ERR_INVALID_ARG if one of the parameters is NULL or data->rsa_length is too long or 0
+ *      - ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL if there was an HMAC failure during retrieval of the decryption key
+ *      - ESP_ERR_NO_MEM if there hasn't been enough memory to allocate the context object
+ *      - ESP_ERR_HW_CRYPTO_DS_INVALID_KEY if there's a problem with passing the HMAC key to the DS component
+ */
+esp_err_t esp_ds_start_sign(const void *message,
+        const esp_ds_data_t *data,
+        hmac_key_id_t key_id,
+        esp_ds_context_t **esp_ds_ctx);
+
+/**
+ * Return true if the DS peripheral is busy, otherwise false.
+ *
+ * @note Only valid if \c esp_ds_start_sign() was called before.
+ */
+bool esp_ds_is_busy(void);
+
+/**
+ * @brief Finish the signing process.
+ *
+ * @param signature the destination of the signature, should be (data->rsa_length + 1)*4 bytes long
+ * @param esp_ds_ctx the context object retreived by \c esp_ds_start_sign()
+ *
+ * @return
+ *      - ESP_OK if successful, the ds operation has been finished and the result is written to signature.
+ *      - ESP_ERR_INVALID_ARG if one of the parameters is NULL
+ *      - ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST if the message digest didn't match; the signature is invalid.
+ *        This means that the encrypted RSA key parameters are invalid, indicating that they may have been tampered
+ *        with or indicating a flash error, etc.
+ *      - ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING if the message padding is incorrect, the signature can be read though
+ *        since the message digest matches (see TRM for more details).
+ */
+esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx);
+
+/**
+ * @brief Encrypt the private key parameters.
+ *
+ * The encryption is a prerequisite step before any signature operation can be done.
+ * It is not strictly necessary to use this encryption function, the encryption could also happen on an external
+ * device.
+ *
+ * @param data Output buffer to store encrypted data, suitable for later use generating signatures.
+ *        The allocated memory must be in internal memory and word aligned since it's filled by DMA. Both is asserted
+ *        at run time.
+ * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
+ * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process
+ *        is done and 'data' is stored.
+ * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the
+ *        corresponding HMAC key will be stored to efuse and then permanently erased.
+ *
+ * @return
+ *      - ESP_OK if successful, the ds operation has been finished and the result is written to signature.
+ *      - ESP_ERR_INVALID_ARG if one of the parameters is NULL or p_data->rsa_length is too long
+ */
+esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
+        const void *iv,
+        const esp_ds_p_data_t *p_data,
+        const void *key);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/include/soc/esp32c6/esp_hmac.h

@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ESP_HMAC_H_
+#define _ESP_HMAC_H_
+
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * The possible efuse keys for the HMAC peripheral
+ */
+typedef enum {
+    HMAC_KEY0 = 0,
+    HMAC_KEY1,
+    HMAC_KEY2,
+    HMAC_KEY3,
+    HMAC_KEY4,
+    HMAC_KEY5,
+    HMAC_KEY_MAX
+} hmac_key_id_t;
+
+/**
+ * @brief
+ * Calculate the HMAC of a given message.
+ *
+ * Calculate the HMAC \c hmac of a given message \c message with length \c message_len.
+ * SHA256 is used for the calculation (fixed on ESP32S2).
+ *
+ * @note Uses the HMAC peripheral in "upstream" mode.
+ *
+ * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calcuation.
+ *        The corresponding purpose field of the key block in the efuse must be set to the HMAC upstream purpose value.
+ * @param message the message for which to calculate the HMAC
+ * @param message_len message length
+ *             return ESP_ERR_INVALID_STATE if unsuccessful
+ * @param [out] hmac the hmac result; the buffer behind the provided pointer must be a writeable buffer of 32 bytes
+ *
+ * @return
+ *      * ESP_OK, if the calculation was successful,
+ *      * ESP_ERR_INVALID_ARG if message or hmac is a nullptr or if key_id out of range
+ *      * ESP_FAIL, if the hmac calculation failed
+ */
+esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
+        const void *message,
+        size_t message_len,
+        uint8_t *hmac);
+
+/**
+ * @brief Use HMAC peripheral in Downstream mode to re-enable the JTAG, if it is not permanently disabled by HW.
+ *        In downstream mode, HMAC calculations performed by peripheral are used internally and not provided back to user.
+ *
+ * @param key_id Determines which of the 6 key blocks in the efuses should be used for the HMAC calculation.
+ *        The corresponding purpose field of the key block in the efuse must be set to HMAC downstream purpose.
+ *
+ * @param token Pre calculated HMAC value of the 32-byte 0x00 using SHA-256 and the known private HMAC key. The key is already
+ *        programmed to a eFuse key block. The key block number is provided as the first parameter to this function.
+ *
+ * @return
+ *      * ESP_OK, if the key_purpose of the key_id matches to HMAC downstread mode,
+ *                The API returns success even if calculated HMAC does not match with the provided token.
+ *                However, The JTAG will be re-enabled only if the calculated HMAC value matches with provided token,
+ *                otherwise JTAG will remain disabled.
+ *      * ESP_FAIL, if the key_purpose of the key_id is not set to HMAC downstream purpose
+ *                  or JTAG is permanently disabled by EFUSE_HARD_DIS_JTAG eFuse parameter.
+ *      * ESP_ERR_INVALID_ARG, invalid input arguments
+ *
+ * @note  Return value of the API does not indicate the JTAG status.
+ */
+esp_err_t esp_hmac_jtag_enable(hmac_key_id_t key_id, const uint8_t *token);
+
+/**
+ *  @brief Disable the JTAG which might be enabled using the HMAC downstream mode. This function just clears the result generated
+ *         by calling esp_hmac_jtag_enable() API.
+ *
+ *  @return
+ *       * ESP_OK return ESP_OK after writing the HMAC_SET_INVALIDATE_JTAG_REG with value 1.
+ */
+esp_err_t esp_hmac_jtag_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _ESP_HMAC_H_

components/esp_hw_support/include/soc/esp32c6/rtc.h

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file esp32c6/rtc.h
+ *
+ * This file contains declarations of rtc related functions.
+ */
+
+/**
+ * @brief Get current value of RTC counter in microseconds
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter in microseconds
+ */
+uint64_t esp_rtc_get_time_us(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/include/soc/esp32c6/soc_memprot_types.h

@@ -0,0 +1,175 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+//////////////////////////////////////////////////////////
+// ESP32-C6 PMS memory protection types
+//
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Memory types recognized by PMS
+ */
+typedef enum {
+    MEMPROT_TYPE_NONE                           = 0x00000000,
+    MEMPROT_TYPE_IRAM0_SRAM                     = 0x00000001,
+    MEMPROT_TYPE_DRAM0_SRAM                     = 0x00000002,
+    MEMPROT_TYPE_IRAM0_RTCFAST                  = 0x00000004,
+    MEMPROT_TYPE_ALL                            = 0x7FFFFFFF,
+    MEMPROT_TYPE_INVALID                        = 0x80000000,
+    MEMPROT_TYPE_IRAM0_ANY                      = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_IRAM0_RTCFAST
+} esp_mprot_mem_t;
+
+/**
+ * @brief Splitting address (line) type
+ */
+typedef enum {
+    MEMPROT_SPLIT_ADDR_NONE                     = 0x00000000,
+    MEMPROT_SPLIT_ADDR_IRAM0_DRAM0              = 0x00000001,
+    MEMPROT_SPLIT_ADDR_IRAM0_LINE_0             = 0x00000002,
+    MEMPROT_SPLIT_ADDR_IRAM0_LINE_1             = 0x00000004,
+    MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0         = 0x00000008,
+    MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1         = 0x00000010,
+    MEMPROT_SPLIT_ADDR_ALL                      = 0x7FFFFFFF,
+    MEMPROT_SPLIT_ADDR_INVALID                  = 0x80000000,
+    MEMPROT_SPLIT_ADDR_MAIN                     = MEMPROT_SPLIT_ADDR_IRAM0_DRAM0
+} esp_mprot_split_addr_t;
+
+/**
+ * @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address)
+ */
+typedef enum {
+    MEMPROT_PMS_AREA_NONE                       = 0x00000000,
+    MEMPROT_PMS_AREA_IRAM0_0                    = 0x00000001,
+    MEMPROT_PMS_AREA_IRAM0_1                    = 0x00000002,
+    MEMPROT_PMS_AREA_IRAM0_2                    = 0x00000004,
+    MEMPROT_PMS_AREA_IRAM0_3                    = 0x00000008,
+    MEMPROT_PMS_AREA_DRAM0_0                    = 0x00000010,
+    MEMPROT_PMS_AREA_DRAM0_1                    = 0x00000020,
+    MEMPROT_PMS_AREA_DRAM0_2                    = 0x00000040,
+    MEMPROT_PMS_AREA_DRAM0_3                    = 0x00000080,
+    MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO           = 0x00000100,
+    MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI           = 0x00000200,
+    MEMPROT_PMS_AREA_ALL                        = 0x7FFFFFFF,
+    MEMPROT_PMS_AREA_INVALID                    = 0x80000000
+} esp_mprot_pms_area_t;
+
+/**
+* @brief Memory protection configuration
+*/
+typedef struct {
+    bool invoke_panic_handler;  /*!< Register PMS violation interrupt for panic-handling */
+    bool lock_feature;          /*!< Lock all PMS settings */
+    void *split_addr;           /*!< Main I/D splitting address */
+    uint32_t mem_type_mask;     /*!< Memory types required to protect. See esp_mprot_mem_t enum */
+} esp_memp_config_t;
+
+#define ESP_MEMPROT_DEFAULT_CONFIG() { \
+    .invoke_panic_handler = true, \
+    .lock_feature = true, \
+    .split_addr = NULL, \
+    .mem_type_mask = MEMPROT_TYPE_ALL \
+}
+
+/**
+ * @brief Converts Memory protection type to string
+ *
+ * @param mem_type Memory protection type
+ */
+static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type)
+{
+    switch (mem_type) {
+    case MEMPROT_TYPE_NONE:
+        return "NONE";
+    case MEMPROT_TYPE_IRAM0_SRAM:
+        return "IRAM0_SRAM";
+    case MEMPROT_TYPE_DRAM0_SRAM:
+        return "DRAM0_SRAM";
+    case MEMPROT_TYPE_IRAM0_RTCFAST:
+        return "IRAM0_RTCFAST";
+    case MEMPROT_TYPE_IRAM0_ANY:
+        return "IRAM0_ANY";
+    case MEMPROT_TYPE_ALL:
+        return "ALL";
+    default:
+        return "INVALID";
+    }
+}
+
+/**
+ * @brief Converts Splitting address type to string
+ *
+ * @param line_type Split line type
+ */
+static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type)
+{
+    switch (line_type) {
+    case MEMPROT_SPLIT_ADDR_NONE:
+        return "SPLIT_ADDR_NONE";
+    case MEMPROT_SPLIT_ADDR_IRAM0_DRAM0:
+        return "SPLIT_ADDR_IRAM0_DRAM0";
+    case MEMPROT_SPLIT_ADDR_IRAM0_LINE_0:
+        return "SPLIT_ADDR_IRAM0_LINE_0";
+    case MEMPROT_SPLIT_ADDR_IRAM0_LINE_1:
+        return "SPLIT_ADDR_IRAM0_LINE_1";
+    case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0:
+        return "SPLIT_ADDR_DRAM0_DMA_LINE_0";
+    case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1:
+        return "SPLIT_ADDR_DRAM0_DMA_LINE_1";
+    case MEMPROT_SPLIT_ADDR_ALL:
+        return "SPLIT_ADDR_ALL";
+    default:
+        return "SPLIT_ADDR_INVALID";
+    }
+}
+
+/**
+ * @brief Converts PMS Area type to string
+ *
+ * @param area_type PMS Area type
+ */
+static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type)
+{
+    switch (area_type) {
+    case MEMPROT_PMS_AREA_NONE:
+        return "PMS_AREA_NONE";
+    case MEMPROT_PMS_AREA_IRAM0_0:
+        return "PMS_AREA_IRAM0_0";
+    case MEMPROT_PMS_AREA_IRAM0_1:
+        return "PMS_AREA_IRAM0_1";
+    case MEMPROT_PMS_AREA_IRAM0_2:
+        return "PMS_AREA_IRAM0_2";
+    case MEMPROT_PMS_AREA_IRAM0_3:
+        return "PMS_AREA_IRAM0_3";
+    case MEMPROT_PMS_AREA_DRAM0_0:
+        return "PMS_AREA_DRAM0_0";
+    case MEMPROT_PMS_AREA_DRAM0_1:
+        return "PMS_AREA_DRAM0_1";
+    case MEMPROT_PMS_AREA_DRAM0_2:
+        return "PMS_AREA_DRAM0_2";
+    case MEMPROT_PMS_AREA_DRAM0_3:
+        return "PMS_AREA_DRAM0_3";
+    case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO:
+        return "PMS_AREA_IRAM0_RTCFAST_LO";
+    case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI:
+        return "PMS_AREA_IRAM0_RTCFAST_HI";
+    case MEMPROT_PMS_AREA_ALL:
+        return "PMS_AREA_ALL";
+    default:
+        return "PMS_AREA_INVALID";
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/linker.lf

@@ -13,9 +13,10 @@ entries:
     cpu: esp_cpu_compare_and_set (noflash)
     esp_memory_utils (noflash)
     rtc_clk (noflash)
-    rtc_init:rtc_vddsdio_set_config (noflash)
+    if IDF_TARGET_ESP32C6 = n: # TODO: IDF-5645
-    rtc_pm (noflash_text)
+        rtc_init:rtc_vddsdio_set_config (noflash)
-    rtc_sleep (noflash_text)
+        rtc_pm (noflash_text)
+        rtc_sleep (noflash_text)
     rtc_time (noflash_text)
     if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:
         rtc_wdt (noflash_text)

components/esp_hw_support/port/esp32c6/CMakeLists.txt

@@ -0,0 +1,25 @@
+set(srcs "rtc_clk_init.c"
+         "rtc_clk.c"
+        #  "rtc_init.c" // TODO: IDF-5645
+        #  "rtc_pm.c" // TODO: IDF-5645
+        #  "rtc_sleep.c" // TODO: IDF-5645
+         "rtc_time.c"
+         "chip_info.c"
+         )
+
+if(NOT BOOTLOADER_BUILD)
+    # list(APPEND srcs "esp_hmac.c" // TODO: IDF-5355
+    #                  "esp_crypto_lock.c"
+    #                  "esp_ds.c") // TODO: IDF-5360
+
+    if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
+        list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
+    endif()
+
+endif()
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
+target_include_directories(${COMPONENT_LIB} PRIVATE ../hal)

components/esp_hw_support/port/esp32c6/Kconfig.hw_support

@@ -0,0 +1,15 @@
+choice ESP32C6_REV_MIN
+    prompt "Minimum Supported ESP32-C6 Revision"
+    default ESP32C6_REV_MIN_0
+    help
+        Minimum revision that ESP-IDF would support.
+
+        Only supporting higher chip revisions can reduce binary size.
+
+    config ESP32C6_REV_MIN_0
+        bool "Rev 0"
+endchoice
+
+config ESP32C6_REV_MIN
+    int
+    default 0 if ESP32C6_REV_MIN_0

components/esp_hw_support/port/esp32c6/Kconfig.mac

@@ -0,0 +1,43 @@
+choice ESP32C6_UNIVERSAL_MAC_ADDRESSES
+    bool "Number of universally administered (by IEEE) MAC address"
+    default ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR
+    help
+        Configure the number of universally administered (by IEEE) MAC addresses.
+
+        During initialization, MAC addresses for each network interface are generated or derived from a
+        single base MAC address.
+
+        If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
+        Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
+        sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
+
+        If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
+        receive a universally administered MAC address. These are generated sequentially by adding 0
+        and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
+        receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
+        addresses, respectively.
+
+        When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
+        a custom universal MAC address range, the correct setting will depend on the allocation of MAC
+        addresses in this range (either 2 or 4 per device.)
+
+        Note that ESP32-C6 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()
+        API to return a MAC for Ethernet, this can only be used with an external MAC peripheral.
+
+    config ESP32C6_UNIVERSAL_MAC_ADDRESSES_TWO
+        bool "Two"
+        select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+        select ESP_MAC_ADDR_UNIVERSE_BT
+
+    config ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR
+        bool "Four"
+        select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+        select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
+        select ESP_MAC_ADDR_UNIVERSE_BT
+        select ESP_MAC_ADDR_UNIVERSE_ETH
+endchoice
+
+config ESP32C6_UNIVERSAL_MAC_ADDRESSES
+    int
+    default 2 if ESP32C6_UNIVERSAL_MAC_ADDRESSES_TWO
+    default 4 if ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR

components/esp_hw_support/port/esp32c6/Kconfig.rtc

@@ -0,0 +1,40 @@
+choice RTC_CLK_SRC
+    # TODO: IDF-5346
+    prompt "RTC clock source"
+    default RTC_CLK_SRC_INT_RC
+    help
+        Choose which clock is used as RTC clock source.
+
+    config RTC_CLK_SRC_INT_RC
+        bool "Internal 136kHz RC oscillator"
+    config RTC_CLK_SRC_EXT_CRYS
+        bool "External 32kHz crystal"
+        select ESP_SYSTEM_RTC_EXT_XTAL
+    config RTC_CLK_SRC_EXT_OSC
+        bool "External 32kHz oscillator at 32K_XP pin"
+        select ESP_SYSTEM_RTC_EXT_OSC
+    config RTC_CLK_SRC_INT_8MD256
+        bool "Internal 17.5MHz oscillator, divided by 256"
+endchoice
+
+config RTC_CLK_CAL_CYCLES
+    int "Number of cycles for RTC_SLOW_CLK calibration"
+    default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
+    default 1024 if RTC_CLK_SRC_INT_RC
+    range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256
+    range 0 32766 if RTC_CLK_SRC_INT_RC
+    help
+        When the startup code initializes RTC_SLOW_CLK, it can perform
+        calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
+        frequency. This option sets the number of RTC_SLOW_CLK cycles measured
+        by the calibration routine. Higher numbers increase calibration
+        precision, which may be important for applications which spend a lot of
+        time in deep sleep. Lower numbers reduce startup time.
+
+        When this option is set to 0, clock calibration will not be performed at
+        startup, and approximate clock frequencies will be assumed:
+
+        - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
+        - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
+            In case more value will help improve the definition of the launch of the crystal.
+            If the crystal could not start, it will be switched to internal RC.

components/esp_hw_support/port/esp32c6/chip_info.c

@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "esp_chip_info.h"
+#include "hal/efuse_hal.h"
+
+void esp_chip_info(esp_chip_info_t *out_info)
+{
+    memset(out_info, 0, sizeof(*out_info));
+    out_info->model = CHIP_ESP32C6;
+    out_info->revision = efuse_hal_chip_revision();
+    out_info->cores = 1;
+    out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
+}

components/esp_hw_support/port/esp32c6/esp_crypto_lock.c

@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/lock.h>
+
+#include "esp_crypto_lock.h"
+
+/* Lock overview:
+SHA: peripheral independent, but DMA is shared with AES
+AES: peripheral independent, but DMA is shared with SHA
+MPI/RSA: independent
+HMAC: needs SHA
+DS: needs HMAC (which needs SHA), AES and MPI
+*/
+
+/* Lock for DS peripheral */
+static _lock_t s_crypto_ds_lock;
+
+/* Lock for HMAC peripheral */
+static _lock_t s_crypto_hmac_lock;
+
+/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */
+static _lock_t s_crypto_mpi_lock;
+
+/* Single lock for SHA and AES, sharing a reserved GDMA channel */
+static _lock_t s_crypto_sha_aes_lock;
+
+void esp_crypto_hmac_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_hmac_lock);
+    esp_crypto_sha_aes_lock_acquire();
+}
+
+void esp_crypto_hmac_lock_release(void)
+{
+    esp_crypto_sha_aes_lock_release();
+    _lock_release(&s_crypto_hmac_lock);
+}
+
+void esp_crypto_ds_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_ds_lock);
+    esp_crypto_hmac_lock_acquire();
+    esp_crypto_mpi_lock_acquire();
+}
+
+void esp_crypto_ds_lock_release(void)
+{
+    esp_crypto_mpi_lock_release();
+    esp_crypto_hmac_lock_release();
+    _lock_release(&s_crypto_ds_lock);
+}
+
+void esp_crypto_sha_aes_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_sha_aes_lock);
+}
+
+void esp_crypto_sha_aes_lock_release(void)
+{
+    _lock_release(&s_crypto_sha_aes_lock);
+}
+
+void esp_crypto_mpi_lock_acquire(void)
+{
+    _lock_acquire(&s_crypto_mpi_lock);
+}
+
+void esp_crypto_mpi_lock_release(void)
+{
+    _lock_release(&s_crypto_mpi_lock);
+}

components/esp_hw_support/port/esp32c6/esp_ds.c

@@ -0,0 +1,224 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_private/periph_ctrl.h"
+#include "esp_crypto_lock.h"
+#include "hal/ds_hal.h"
+#include "hal/ds_ll.h"
+#include "hal/hmac_hal.h"
+#include "esp32c6/rom/digital_signature.h"
+#include "esp_timer.h"
+#include "esp_ds.h"
+
+struct esp_ds_context {
+    const esp_ds_data_t *data;
+};
+
+/**
+ * The vtask delay \c esp_ds_sign() is using while waiting for completion of the signing operation.
+ */
+#define ESP_DS_SIGN_TASK_DELAY_MS 10
+
+#define RSA_LEN_MAX 127
+
+/*
+ * esp_digital_signature_length_t is used in esp_ds_data_t in contrast to ets_ds_data_t, where unsigned is used.
+ * Check esp_digital_signature_length_t's width here because it's converted to unsigned using raw casts.
+ */
+_Static_assert(sizeof(esp_digital_signature_length_t) == sizeof(unsigned),
+        "The size of esp_digital_signature_length_t and unsigned has to be the same");
+
+/*
+ * esp_ds_data_t is used in the encryption function but casted to ets_ds_data_t.
+ * Check esp_ds_data_t's width here because it's converted using raw casts.
+ */
+_Static_assert(sizeof(esp_ds_data_t) == sizeof(ets_ds_data_t),
+        "The size of esp_ds_data_t and ets_ds_data_t has to be the same");
+
+static void ds_acquire_enable(void)
+{
+    esp_crypto_ds_lock_acquire();
+
+    // We also enable SHA and HMAC here. SHA is used by HMAC, HMAC is used by DS.
+    periph_module_enable(PERIPH_HMAC_MODULE);
+    periph_module_enable(PERIPH_SHA_MODULE);
+    periph_module_enable(PERIPH_DS_MODULE);
+
+    hmac_hal_start();
+}
+
+static void ds_disable_release(void)
+{
+    ds_hal_finish();
+
+    periph_module_disable(PERIPH_DS_MODULE);
+    periph_module_disable(PERIPH_SHA_MODULE);
+    periph_module_disable(PERIPH_HMAC_MODULE);
+
+    esp_crypto_ds_lock_release();
+}
+
+esp_err_t esp_ds_sign(const void *message,
+        const esp_ds_data_t *data,
+        hmac_key_id_t key_id,
+        void *signature)
+{
+    // Need to check signature here, otherwise the signature is only checked when the signing has finished and fails
+    // but the signing isn't uninitialized and the mutex is still locked.
+    if (!signature) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    esp_ds_context_t *context;
+    esp_err_t result = esp_ds_start_sign(message, data, key_id, &context);
+    if (result != ESP_OK) {
+        return result;
+    }
+
+    while (esp_ds_is_busy())
+        vTaskDelay(ESP_DS_SIGN_TASK_DELAY_MS / portTICK_PERIOD_MS);
+
+    return esp_ds_finish_sign(signature, context);
+}
+
+esp_err_t esp_ds_start_sign(const void *message,
+        const esp_ds_data_t *data,
+        hmac_key_id_t key_id,
+        esp_ds_context_t **esp_ds_ctx)
+{
+    if (!message || !data || !esp_ds_ctx) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if (key_id >= HMAC_KEY_MAX) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if (!(data->rsa_length == ESP_DS_RSA_1024
+            || data->rsa_length == ESP_DS_RSA_2048
+            || data->rsa_length == ESP_DS_RSA_3072)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    ds_acquire_enable();
+
+    // initiate hmac
+    uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id);
+    if (conf_error) {
+        ds_disable_release();
+        return ESP32C6_ERR_HW_CRYPTO_DS_HMAC_FAIL;
+    }
+
+    ds_hal_start();
+
+    // check encryption key from HMAC
+    int64_t start_time = esp_timer_get_time();
+    while (ds_ll_busy() != 0) {
+        if ((esp_timer_get_time() - start_time) > SOC_DS_KEY_CHECK_MAX_WAIT_US) {
+            ds_disable_release();
+            return ESP32C6_ERR_HW_CRYPTO_DS_INVALID_KEY;
+        }
+    }
+
+    esp_ds_context_t *context = malloc(sizeof(esp_ds_context_t));
+    if (!context) {
+        ds_disable_release();
+        return ESP_ERR_NO_MEM;
+    }
+
+    size_t rsa_len = (data->rsa_length + 1) * 4;
+    ds_hal_write_private_key_params(data->c);
+    ds_hal_configure_iv(data->iv);
+    ds_hal_write_message(message, rsa_len);
+
+    // initiate signing
+    ds_hal_start_sign();
+
+    context->data = data;
+    *esp_ds_ctx = context;
+
+    return ESP_OK;
+}
+
+bool esp_ds_is_busy(void)
+{
+    return ds_hal_busy();
+}
+
+esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx)
+{
+    if (!signature || !esp_ds_ctx) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    const esp_ds_data_t *data = esp_ds_ctx->data;
+    unsigned rsa_len = (data->rsa_length + 1) * 4;
+
+    while (ds_hal_busy()) { }
+
+    ds_signature_check_t sig_check_result = ds_hal_read_result((uint8_t*) signature, (size_t) rsa_len);
+
+    esp_err_t return_value = ESP_OK;
+
+    if (sig_check_result == DS_SIGNATURE_MD_FAIL || sig_check_result == DS_SIGNATURE_PADDING_AND_MD_FAIL) {
+        return_value = ESP32C6_ERR_HW_CRYPTO_DS_INVALID_DIGEST;
+    }
+
+    if (sig_check_result == DS_SIGNATURE_PADDING_FAIL) {
+        return_value = ESP32C6_ERR_HW_CRYPTO_DS_INVALID_PADDING;
+    }
+
+    free(esp_ds_ctx);
+
+    hmac_hal_clean();
+
+    ds_disable_release();
+
+    return return_value;
+}
+
+esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
+        const void *iv,
+        const esp_ds_p_data_t *p_data,
+        const void *key)
+{
+    if (!p_data) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    esp_err_t result = ESP_OK;
+
+    esp_crypto_ds_lock_acquire();
+    periph_module_enable(PERIPH_AES_MODULE);
+    periph_module_enable(PERIPH_DS_MODULE);
+    periph_module_enable(PERIPH_SHA_MODULE);
+    periph_module_enable(PERIPH_HMAC_MODULE);
+    periph_module_enable(PERIPH_RSA_MODULE);
+
+    ets_ds_data_t *ds_data = (ets_ds_data_t*) data;
+    const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t*) p_data;
+
+    ets_ds_result_t ets_result = ets_ds_encrypt_params(ds_data, iv, ds_plain_data, key, ETS_DS_KEY_HMAC);
+
+    if (ets_result == ETS_DS_INVALID_PARAM) {
+        result = ESP_ERR_INVALID_ARG;
+    }
+
+    periph_module_disable(PERIPH_RSA_MODULE);
+    periph_module_disable(PERIPH_HMAC_MODULE);
+    periph_module_disable(PERIPH_SHA_MODULE);
+    periph_module_disable(PERIPH_DS_MODULE);
+    periph_module_disable(PERIPH_AES_MODULE);
+    esp_crypto_ds_lock_release();
+
+    return result;
+}

components/esp_hw_support/port/esp32c6/esp_hmac.c

@@ -0,0 +1,182 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: IDF-5355 Copy frome C3
+
+#include <string.h>
+#include "esp_private/periph_ctrl.h"
+#include "esp32c6/rom/hmac.h"
+#include "esp32c6/rom/ets_sys.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_hmac.h"
+#include "esp_log.h"
+#include "esp_crypto_lock.h"
+#include "soc/hwcrypto_reg.h"
+
+#include "hal/hmac_hal.h"
+
+#define SHA256_BLOCK_SZ 64
+#define SHA256_PAD_SZ 8
+
+static const char *TAG = "esp_hmac";
+
+/**
+ * @brief Apply the HMAC padding without the embedded length.
+ *
+ * @note This function does not check the data length, it is the responsibility of the other functions in this
+ * module to make sure that \c data_len is at most SHA256_BLOCK_SZ - 1 so the padding fits in.
+ * Otherwise, this function has undefined behavior.
+ * Note however, that for the actual HMAC implementation on ESP32C6, the length also needs to be applied at the end
+ * of the block. This function alone deosn't do that.
+ */
+static void write_and_padd(uint8_t *block, const uint8_t *data, uint16_t data_len)
+{
+    memcpy(block, data, data_len);
+    // Apply a one bit, followed by zero bits (refer to the ESP32C6 TRM).
+    block[data_len] = 0x80;
+    bzero(block + data_len + 1, SHA256_BLOCK_SZ - data_len - 1);
+}
+
+esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
+                             const void *message,
+                             size_t message_len,
+                             uint8_t *hmac)
+{
+    const uint8_t *message_bytes = (const uint8_t *)message;
+
+    if (!message || !hmac) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (key_id >= HMAC_KEY_MAX) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    esp_crypto_hmac_lock_acquire();
+
+    // We also enable SHA and DS here. SHA is used by HMAC, DS will otherwise hold SHA in reset state.
+    periph_module_enable(PERIPH_HMAC_MODULE);
+    periph_module_enable(PERIPH_SHA_MODULE);
+    periph_module_enable(PERIPH_DS_MODULE);
+
+    hmac_hal_start();
+
+    uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_USER, key_id);
+    if (conf_error) {
+        esp_crypto_hmac_lock_release();
+        return ESP_FAIL;
+    }
+
+    if (message_len + 1 + SHA256_PAD_SZ <= SHA256_BLOCK_SZ) {
+        // If message including padding is only one block...
+        // Last message block, so apply SHA-256 padding rules in software
+        uint8_t block[SHA256_BLOCK_SZ];
+        uint64_t bit_len = __builtin_bswap64(message_len * 8 + 512);
+
+        write_and_padd(block, message_bytes, message_len);
+        // Final block: append the bit length in this block and signal padding to peripheral
+        memcpy(block + SHA256_BLOCK_SZ - sizeof(bit_len),
+               &bit_len, sizeof(bit_len));
+        hmac_hal_write_one_block_512(block);
+    } else {
+        // If message including padding is needs more than one block
+
+        // write all blocks without padding except the last one
+        size_t remaining_blocks = message_len / SHA256_BLOCK_SZ;
+        for (int i = 1; i < remaining_blocks; i++) {
+            hmac_hal_write_block_512(message_bytes);
+            message_bytes += SHA256_BLOCK_SZ;
+            hmac_hal_next_block_normal();
+        }
+
+        // If message fits into one block but without padding, we must not write another block.
+        if (remaining_blocks) {
+            hmac_hal_write_block_512(message_bytes);
+            message_bytes += SHA256_BLOCK_SZ;
+        }
+
+        size_t remaining = message_len % SHA256_BLOCK_SZ;
+        // Last message block, so apply SHA-256 padding rules in software
+        uint8_t block[SHA256_BLOCK_SZ];
+        uint64_t bit_len = __builtin_bswap64(message_len * 8 + 512);
+
+        // If the remaining message and appended padding doesn't fit into a single block, we have to write an
+        // extra block with the rest of the message and potential padding first.
+        if (remaining >= SHA256_BLOCK_SZ - SHA256_PAD_SZ) {
+            write_and_padd(block, message_bytes, remaining);
+            hmac_hal_next_block_normal();
+            hmac_hal_write_block_512(block);
+            bzero(block, SHA256_BLOCK_SZ);
+        } else {
+            write_and_padd(block, message_bytes, remaining);
+        }
+        memcpy(block + SHA256_BLOCK_SZ - sizeof(bit_len),
+               &bit_len, sizeof(bit_len));
+        hmac_hal_next_block_padding();
+        hmac_hal_write_block_512(block);
+    }
+
+    // Read back result (bit swapped)
+    hmac_hal_read_result_256(hmac);
+
+    periph_module_disable(PERIPH_DS_MODULE);
+    periph_module_disable(PERIPH_SHA_MODULE);
+    periph_module_disable(PERIPH_HMAC_MODULE);
+
+    esp_crypto_hmac_lock_release();
+
+    return ESP_OK;
+}
+
+static ets_efuse_block_t convert_key_type(hmac_key_id_t key_id) {
+    return ETS_EFUSE_BLOCK_KEY0 + (ets_efuse_block_t) key_id;
+}
+
+esp_err_t esp_hmac_jtag_enable(hmac_key_id_t key_id, const uint8_t *token)
+{
+    int ets_status;
+    esp_err_t err = ESP_OK;
+
+    if ((!token) || (key_id >= HMAC_KEY_MAX))
+        return ESP_ERR_INVALID_ARG;
+
+    /* Check if JTAG is permanently disabled by HW Disable eFuse */
+    if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_PAD_JTAG)) {
+        ESP_LOGE(TAG, "JTAG disabled permanently.");
+        return ESP_FAIL;
+    }
+
+    esp_crypto_hmac_lock_acquire();
+
+    ets_status = ets_jtag_enable_temporarily(token, convert_key_type(key_id));
+
+    if (ets_status != ETS_OK) {
+        // ets_jtag_enable_temporarily returns either ETS_OK or ETS_FAIL
+        err = ESP_FAIL;
+        ESP_LOGE(TAG, "JTAG re-enabling failed (%d)", err);
+    }
+
+    ESP_LOGD(TAG, "HMAC computation in downstream mode is completed.");
+
+    ets_hmac_disable();
+
+    esp_crypto_hmac_lock_release();
+
+    return err;
+}
+
+esp_err_t esp_hmac_jtag_disable()
+{
+    esp_crypto_hmac_lock_acquire();
+
+    REG_SET_BIT(HMAC_SET_INVALIDATE_JTAG_REG, HMAC_SET_INVALIDATE_JTAG);
+
+    esp_crypto_hmac_lock_release();
+
+    ESP_LOGD(TAG, "Invalidate JTAG result register. JTAG disabled.");
+
+    return ESP_OK;
+}

components/esp_hw_support/port/esp32c6/esp_memprot.c

@@ -0,0 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: IDF-5684
+// ESP32C6 has no memory permission management mechanism based on dividing lines,
+// TEE-based implementation can be added here

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -0,0 +1,226 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <stdlib.h>
+#include "sdkconfig.h"
+#include "esp32c6/rom/ets_sys.h"
+#include "esp32c6/rom/rtc.h"
+#include "soc/rtc.h"
+#include "esp_hw_log.h"
+#include "esp_rom_sys.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "hal/clk_tree_ll.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "soc/lp_clkrst_reg.h"
+
+static const char *TAG = "rtc_clk";
+
+void rtc_clk_32k_enable(bool enable)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_32k_enable_external(void)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_32k_bootstrap(uint32_t cycle)
+{
+    // TODO: IDF-5645
+}
+
+bool rtc_clk_32k_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
+{
+    // TODO: IDF-5645
+}
+
+bool rtc_clk_8m_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+bool rtc_clk_8md256_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
+{
+    // TODO: IDF-5645
+}
+
+soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
+{
+    // TODO: IDF-5645
+    return REG_GET_FIELD(LP_CLKRST_LP_CLK_CONF_REG, LP_CLKRST_SLOW_CLK_SEL);
+}
+
+uint32_t rtc_clk_slow_freq_get_hz(void)
+{
+    // TODO: IDF-5645
+    switch (rtc_clk_slow_freq_get()) {
+        case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
+        case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
+        case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
+        default: return 0;
+    }
+}
+
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
+{
+    // TODO: IDF-5645
+}
+
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+#if 0
+static void rtc_clk_bbpll_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+static void rtc_clk_bbpll_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
+{
+    // TODO: IDF-5645
+}
+
+/**
+ * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
+ * PLL must already be enabled.
+ * @param cpu_freq new CPU frequency
+ */
+static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
+{
+    // TODO: IDF-5645
+}
+#endif
+
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_cpu_freq_set_xtal(void)
+{
+    ESP_EARLY_LOGW(TAG, "rtc_clk_cpu_freq_set_xtal() has not been implemented yet");
+    // TODO: IDF-5645
+}
+
+#if 0
+/**
+ * Switch to XTAL frequency. Does not disable the PLL.
+ */
+static void rtc_clk_cpu_freq_to_xtal(int freq, int div)
+{
+    // TODO: IDF-5645
+}
+
+static void rtc_clk_cpu_freq_to_8m(void)
+{
+    // TODO: IDF-5645
+}
+#endif
+
+rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
+{
+    ESP_EARLY_LOGW(TAG, "rtc_clk_xtal_freq_get() has not been implemented yet");
+    // TODO: IDF-5645
+    return 40;
+}
+
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_apb_freq_update(uint32_t apb_freq)
+{
+    // TODO: IDF-5645
+}
+
+uint32_t rtc_clk_apb_freq_get(void)
+{
+    ESP_EARLY_LOGW(TAG, "rtc_clk_apb_freq_get() has not been implemented yet");
+    // TODO: IDF-5645
+    return 0;
+}
+
+void rtc_clk_divider_set(uint32_t div)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_clk_8m_divider_set(uint32_t div)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_dig_clk8m_enable(void)
+{
+    // TODO: IDF-5645
+}
+
+void rtc_dig_clk8m_disable(void)
+{
+    // TODO: IDF-5645
+}
+
+bool rtc_dig_8m_enabled(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+
+#if 0
+static bool rtc_clk_set_bbpll_always_on(void)
+{
+    // TODO: IDF-5645
+    return 0;
+}
+#endif
+
+/* Name used in libphy.a:phy_chip_v7.o
+ * TODO: update the library to use rtc_clk_xtal_freq_get
+ */
+rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));

components/esp_hw_support/port/esp32c6/rtc_clk_init.c

@@ -0,0 +1,84 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include "esp32c6/rom/ets_sys.h"
+#include "esp32c6/rom/rtc.h"
+#include "esp32c6/rom/uart.h"
+#include "soc/rtc.h"
+#include "soc/efuse_periph.h"
+#include "esp_cpu.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "esp_hw_log.h"
+#include "sdkconfig.h"
+#include "esp_rom_uart.h"
+
+static const char *TAG = "rtc_clk_init";
+
+void rtc_clk_init(rtc_clk_config_t cfg)
+{
+    ESP_HW_LOGW(TAG, "rtc_clk_init() has not been implemented yet");
+#if 0 // TODO: IDF-5645
+    rtc_cpu_freq_config_t old_config, new_config;
+
+    /* Set tuning parameters for 8M and 150k clocks.
+     * Note: this doesn't attempt to set the clocks to precise frequencies.
+     * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
+     * - SCK_DCAP value controls tuning of 150k clock.
+     *   The higher the value of DCAP is, the lower is the frequency.
+     * - CK8M_DFREQ value controls tuning of 8M clock.
+     *   CLK_8M_DFREQ constant gives the best temperature characteristics.
+     */
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
+
+    /* Configure 150k clock division */
+    rtc_clk_divider_set(cfg.clk_rtc_clk_div);
+
+    /* Configure 8M clock division */
+    rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
+
+    /* Reset (disable) i2c internal bus for all regi2c registers */
+    regi2c_ctrl_ll_i2c_reset(); // TODO: This should be move out from rtc_clk_init
+    /* Enable the internal bus used to configure BBPLL */
+    regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
+
+    rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
+    esp_rom_uart_tx_wait_idle(0);
+    rtc_clk_xtal_freq_update(xtal_freq);
+    rtc_clk_apb_freq_update(xtal_freq * MHZ);
+
+    /* Set CPU frequency */
+    rtc_clk_cpu_freq_get_config(&old_config);
+    uint32_t freq_before = old_config.freq_mhz;
+    bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
+    if (!res) {
+        ESP_HW_LOGE(TAG, "invalid CPU frequency value");
+        abort();
+    }
+    rtc_clk_cpu_freq_set_config(&new_config);
+
+    /* Re-calculate the ccount to make time calculation correct. */
+    esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
+
+    /* Slow & fast clocks setup */
+    // We will not power off RC_FAST in bootloader stage even if it is not being used as any
+    // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
+    bool need_rc_fast_en = true;
+    bool need_rc_fast_d256_en = false;
+    if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
+        rtc_clk_32k_enable(true);
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
+        need_rc_fast_d256_en = true;
+    }
+    rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
+    rtc_clk_fast_src_set(cfg.fast_clk_src);
+    rtc_clk_slow_src_set(cfg.slow_clk_src);
+#endif
+}

components/esp_hw_support/port/esp32c6/rtc_init.c

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: IDF-5645

components/esp_hw_support/port/esp32c6/rtc_pm.c

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: IDF-5645

components/esp_hw_support/port/esp32c6/rtc_sleep.c

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: IDF-5645

components/esp_hw_support/port/esp32c6/rtc_time.c

@@ -0,0 +1,103 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp32c6/rom/ets_sys.h"
+#include "soc/rtc.h"
+// #include "soc/rtc_cntl_reg.h"
+#include "hal/clk_tree_ll.h"
+#include "soc/timer_group_reg.h"
+#include "esp_rom_sys.h"
+
+/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ */
+
+/**
+ * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
+ * @param cal_clk which clock to calibrate
+ * @param slowclk_cycles number of slow clock cycles to count
+ * @return number of XTAL clock cycles within the given number of slow clock cycles
+ */
+// TODO: IDF-5645
+static const char *TAG = "rtc_time";
+
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_clk_cal_internal() has not been implemented yet");
+    return 0;
+}
+
+uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_clk_cal_ratio() has not been implemented yet");
+    return 0;
+}
+
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_clk_cal() has not been implemented yet");
+    return 0;
+}
+
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_time_us_to_slowclk() has not been implemented yet");
+    return 0;
+}
+
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_time_slowclk_to_us() has not been implemented yet");
+    return 0;
+}
+
+uint64_t rtc_time_get(void)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_time_get() has not been implemented yet");
+    return 0;
+}
+
+uint64_t rtc_light_slp_time_get(void)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_light_slp_time_get() has not been implemented yet");
+    return 0;
+}
+
+uint64_t rtc_deep_slp_time_get(void)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_deep_slp_time_get() has not been implemented yet");
+    return 0;
+}
+
+void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
+}
+
+uint32_t rtc_clk_freq_cal(uint32_t cal_val)
+{
+    // TODO: IDF-5645
+    ESP_EARLY_LOGW(TAG, "rtc_clk_freq_cal() has not been implemented yet");
+    return 0;
+}

components/esp_hw_support/port/esp32c6/systimer.c

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_private/systimer.h"
+
+/**
+ * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
+ *        So the resolution of the systimer is 40MHz/2.5 = 16MHz.
+ */
+
+uint64_t systimer_ticks_to_us(uint64_t ticks)
+{
+    return ticks / 16;
+}
+
+uint64_t systimer_us_to_ticks(uint64_t us)
+{
+    return us * 16;
+}

components/esp_hw_support/rtc_module.c

@@ -27,6 +27,12 @@
 #endif
 #include "sys/queue.h"
 
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
+static const char *TAG = "rtc_module";
+#endif
+
+#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
+
 #define NOT_REGISTERED      (-1)
 
 portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;
@@ -90,9 +96,14 @@ out:
     portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
     return err;
 }
+#endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-5645
 
 esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags)
 {
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
+    ESP_LOGW(TAG, "rtc_isr_register() has not been implemented yet");
+    return ESP_OK;
+#else
     esp_err_t err = rtc_isr_ensure_installed();
     if (err != ESP_OK) {
         return err;
@@ -115,10 +126,15 @@ esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t r
     SLIST_INSERT_HEAD(&s_rtc_isr_handler_list, item, next);
     portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
     return ESP_OK;
+#endif
 }
 
 esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
 {
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
+    ESP_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet");
+    return ESP_OK;
+#else
     rtc_isr_handler_t* it;
     rtc_isr_handler_t* prev = NULL;
     bool found = false;
@@ -141,8 +157,10 @@ esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
     }
     portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
     return found ? ESP_OK : ESP_ERR_INVALID_STATE;
+#endif
 }
 
+#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
 /**
  * @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled.
  *        There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.)
@@ -160,19 +178,25 @@ static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)
 {
     rtc_intr_cache &= ~rtc_intr_mask;
 }
+#endif
+
 
 IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
 {
+#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
     if (rtc_isr_cpu == cpu) {
         rtc_intr_enabled |= RTCCNTL.int_ena.val;
         RTCCNTL.int_ena.val &= rtc_intr_cache;
     }
+#endif
 }
 
 IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu)
 {
+#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
     if (rtc_isr_cpu == cpu) {
         RTCCNTL.int_ena.val = rtc_intr_enabled;
         rtc_intr_enabled = 0;
     }
+#endif
 }

components/esp_hw_support/sleep_modes.c

@@ -78,6 +78,10 @@
 #include "esp32c2/rom/cache.h"
 #include "esp32c2/rom/rtc.h"
 #include "soc/extmem_reg.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/cache.h"
+#include "esp32c6/rom/rtc.h"
+#include "soc/extmem_reg.h"
 #endif
 
 // If light sleep time is less than that, don't power down flash
@@ -107,6 +111,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C2
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (118)// TODO: IDF-5348
+#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (9)
 #endif
 
 #define LIGHT_SLEEP_TIME_OVERHEAD_US        DEFAULT_HARDWARE_OUT_OVERHEAD_US
@@ -789,7 +796,11 @@ esp_err_t esp_light_sleep_start(void)
     rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
 
     // Safety net: enable WDT in case exit from light sleep fails
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
+    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
+#else
     wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+#endif
     bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx);    // If WDT was enabled in the user code, then do not change it here.
     if (!wdt_was_enabled) {
         wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
@@ -1231,6 +1242,9 @@ esp_err_t esp_sleep_disable_bt_wakeup(void)
 
 esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
 {
+#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
+    return ESP_SLEEP_WAKEUP_UNDEFINED;
+#else
     if (esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP && !s_light_sleep_wakeup) {
         return ESP_SLEEP_WAKEUP_UNDEFINED;
     }
@@ -1278,6 +1292,7 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
     } else {
         return ESP_SLEEP_WAKEUP_UNDEFINED;
     }
+#endif
 }
 
 esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,

components/esp_phy/CMakeLists.txt

@@ -1,5 +1,10 @@
 idf_build_get_property(idf_target IDF_TARGET)
 
+if(IDF_TARGET STREQUAL "esp32c6")
+    # TODO : IDF-5680
+    return()
+endif()
+
 set(srcs "src/phy_override.c" "src/lib_printf.c")
 
 if(CONFIG_APP_NO_BLOBS)

components/esp_pm/include/esp32c6/pm.h

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#pragma once
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief Power management config for ESP32C6
+ *
+ * Pass a pointer to this structure as an argument to esp_pm_configure function.
+ */
+typedef struct {
+    int max_freq_mhz;   /*!< Maximum CPU frequency, in MHz */
+    int min_freq_mhz;   /*!< Minimum CPU frequency to use when no locks are taken, in MHz */
+    bool light_sleep_enable;        /*!< Enter light sleep when no locks are taken */
+} esp_pm_config_esp32c6_t;
+
+
+#ifdef __cplusplus
+}
+#endif

components/esp_pm/include/esp_pm.h

@@ -21,6 +21,8 @@
 #include "esp32h2/pm.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/pm.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/pm.h"
 #endif
 
 #ifdef __cplusplus

components/esp_pm/pm_impl.c

@@ -56,6 +56,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/pm.h"
 #include "driver/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/pm.h"
+#include "driver/gpio.h"
 #endif
 
 #define MHZ (1000000)
@@ -85,13 +88,15 @@
 #define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32S3
 /* Minimal divider at which REF_CLK_FREQ can be obtained */
-#define REF_CLK_DIV_MIN 2
+#define REF_CLK_DIV_MIN 2         // TODO: IDF-5660
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define REF_CLK_DIV_MIN 2
 #elif CONFIG_IDF_TARGET_ESP32C2
 #define REF_CLK_DIV_MIN 2
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define REF_CLK_DIV_MIN 2
 #endif
 
 #ifdef CONFIG_PM_PROFILING
@@ -228,6 +233,8 @@ esp_err_t esp_pm_configure(const void* vconfig)
     const esp_pm_config_esp32h2_t* config = (const esp_pm_config_esp32h2_t*) vconfig;
 #elif CONFIG_IDF_TARGET_ESP32C2
     const esp_pm_config_esp32c2_t* config = (const esp_pm_config_esp32c2_t*) vconfig;
+#elif CONFIG_IDF_TARGET_ESP32C6
+    const esp_pm_config_esp32c6_t* config = (const esp_pm_config_esp32c6_t*) vconfig;
 #endif
 
 #ifndef CONFIG_FREERTOS_USE_TICKLESS_IDLE
@@ -338,6 +345,8 @@ esp_err_t esp_pm_get_configuration(void* vconfig)
     esp_pm_config_esp32h2_t* config = (esp_pm_config_esp32h2_t*) vconfig;
 #elif CONFIG_IDF_TARGET_ESP32C2
     esp_pm_config_esp32c2_t* config = (esp_pm_config_esp32c2_t*) vconfig;
+#elif CONFIG_IDF_TARGET_ESP32C6
+    esp_pm_config_esp32c6_t* config = (esp_pm_config_esp32c6_t*) vconfig;
 #endif
 
     portENTER_CRITICAL(&s_switch_lock);
@@ -782,6 +791,8 @@ void esp_pm_impl_init(void)
     esp_pm_config_esp32h2_t cfg = {
 #elif CONFIG_IDF_TARGET_ESP32C2
     esp_pm_config_esp32c2_t cfg = {
+#elif CONFIG_IDF_TARGET_ESP32C6
+    esp_pm_config_esp32c6_t cfg = {
 #endif
         .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
         .min_freq_mhz = xtal_freq_mhz,

components/esp_pm/test/test_pm.c

@@ -54,6 +54,8 @@ static void switch_freq(int mhz)
     esp_pm_config_esp32c3_t pm_config = {
 #elif CONFIG_IDF_TARGET_ESP32H2
     esp_pm_config_esp32h2_t pm_config = {
+#elif CONFIG_IDF_TARGET_ESP32C6
+    esp_pm_config_esp32c6_t pm_config = {
 #endif
         .max_freq_mhz = mhz,
         .min_freq_mhz = MIN(mhz, xtal_freq_mhz),
@@ -109,6 +111,8 @@ static void light_sleep_enable(void)
     esp_pm_config_esp32c3_t pm_config = {
 #elif CONFIG_IDF_TARGET_ESP32H2
     esp_pm_config_esp32h2_t pm_config = {
+#elif CONFIG_IDF_TARGET_ESP32C6
+    esp_pm_config_esp32c6_t pm_config = {
 #endif
         .max_freq_mhz = cur_freq_mhz,
         .min_freq_mhz = xtal_freq,
@@ -133,6 +137,8 @@ static void light_sleep_disable(void)
     esp_pm_config_esp32c3_t pm_config = {
 #elif CONFIG_IDF_TARGET_ESP32H2
     esp_pm_config_esp32h2_t pm_config = {
+#elif CONFIG_IDF_TARGET_ESP32C6
+    esp_pm_config_esp32c6_t pm_config = {
 #endif
         .max_freq_mhz = cur_freq_mhz,
         .min_freq_mhz = cur_freq_mhz,

components/esp_rom/CMakeLists.txt

@@ -69,6 +69,16 @@ if(target STREQUAL "linux")
 else()
     target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.ld")
     rom_linker_script("api")
+
+    # esp32c6.rom.api.ld has been split to several lds by components
+    if(target STREQUAL "esp32c6")
+        rom_linker_script("phy")
+        rom_linker_script("coexist")
+        rom_linker_script("net80211")
+        rom_linker_script("pp")
+        # rom_linker_script("spiflash") # TODO: IDF-5632 (Supports more rom components)
+    endif()
+
     if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
         rom_linker_script("libgcc")
     else()
@@ -104,6 +114,9 @@ if(BOOTLOADER_BUILD)
     elseif(target STREQUAL "esp32c2")
         rom_linker_script("newlib")
         rom_linker_script("mbedtls")
+
+    elseif(target STREQUAL "esp32c6")
+        rom_linker_script("newlib")
     endif()
 
 else() # Regular app build
@@ -217,17 +230,21 @@ else() # Regular app build
             endif()
         endif()
 
-        if(CONFIG_HEAP_TLSF_USE_ROM_IMPL)
+    elseif(target STREQUAL "esp32c6")
-            # After registering the component, set the tlsf_set_rom_patches symbol as undefined
+        rom_linker_script("newlib")
-            # to force the linker to integrate the whole `esp_rom_tlsf.c` object file inside the
+        rom_linker_script("version")
-            # final binary. This is necessary because tlsf_set_rom_patches is a constructor, thus,
+    endif()
-            # there as no explicit reference/call to it in IDF.
-            if(CONFIG_ESP_ROM_TLSF_CHECK_PATCH)
-                target_link_libraries(${COMPONENT_LIB} PRIVATE "-u tlsf_set_rom_patches")
-            endif()
 
-            rom_linker_script("heap")
+    if(CONFIG_HEAP_TLSF_USE_ROM_IMPL)
+        # After registering the component, set the tlsf_set_rom_patches symbol as undefined
+        # to force the linker to integrate the whole `esp_rom_tlsf.c` object file inside the
+        # final binary. This is necessary because tlsf_set_rom_patches is a constructor, thus,
+        # there as no explicit reference/call to it in IDF.
+        if(CONFIG_ESP_ROM_TLSF_CHECK_PATCH)
+            target_link_libraries(${COMPONENT_LIB} PRIVATE "-u tlsf_set_rom_patches")
         endif()
+
+        rom_linker_script("heap")
     endif()
 
     if(CONFIG_IDF_TARGET_ARCH_XTENSA)

components/esp_rom/esp32c2/Kconfig.soc_caps.in

@@ -42,3 +42,11 @@ config ESP_ROM_HAS_HEAP_TLSF
 config ESP_ROM_TLSF_CHECK_PATCH
     bool
     default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y

components/esp_rom/esp32c2/esp_rom_caps.h

@@ -16,3 +16,5 @@
 #define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
 #define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
 #define ESP_ROM_TLSF_CHECK_PATCH            (1) // ROM does not contain the patch of tlsf_check()
+#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
+#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver

components/esp_rom/esp32c3/Kconfig.soc_caps.in

@@ -38,3 +38,11 @@ config ESP_ROM_GET_CLK_FREQ
 config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
     bool
     default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y

components/esp_rom/esp32c3/esp_rom_caps.h

@@ -15,3 +15,5 @@
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
 #define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
+#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
+#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver

components/esp_rom/esp32c6/Kconfig.soc_caps.in

@@ -30,3 +30,19 @@ config ESP_ROM_HAS_RETARGETABLE_LOCKING
 config ESP_ROM_GET_CLK_FREQ
     bool
     default y
+
+config ESP_ROM_HAS_HEAP_TLSF
+    bool
+    default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_RVFPLIB
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y

components/esp_rom/esp32c6/esp_rom_caps.h

@@ -13,3 +13,7 @@
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
+#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
+#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
+#define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
+#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver

components/esp_rom/esp32c6/ld/esp32c6.rom.coexist.ld

@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.coexist.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group rom_coexist
+ ***************************************/
+
+/* Functions */
+esp_coex_rom_version_get = 0x40000afc;
+coex_bt_release = 0x40000b00;
+coex_bt_request = 0x40000b04;
+coex_core_ble_conn_dyn_prio_get = 0x40000b08;
+coex_core_event_duration_get = 0x40000b0c;
+coex_core_pti_get = 0x40000b10;
+coex_core_release = 0x40000b14;
+coex_core_request = 0x40000b18;
+coex_core_status_get = 0x40000b1c;
+coex_core_timer_idx_get = 0x40000b20;
+coex_event_duration_get = 0x40000b24;
+coex_hw_timer_disable = 0x40000b28;
+coex_hw_timer_enable = 0x40000b2c;
+coex_hw_timer_set = 0x40000b30;
+coex_schm_interval_set = 0x40000b34;
+coex_schm_lock = 0x40000b38;
+coex_schm_unlock = 0x40000b3c;
+coex_status_get = 0x40000b40;
+coex_wifi_release = 0x40000b44;
+esp_coex_ble_conn_dynamic_prio_get = 0x40000b48;
+/* Data (.data, .bss, .rodata) */
+coex_env_ptr = 0x4087ffc4;
+coex_pti_tab_ptr = 0x4087ffc0;
+coex_schm_env_ptr = 0x4087ffbc;
+coexist_funcs = 0x4087ffb8;
+g_coa_funcs_p = 0x4087ffb4;
+g_coex_param_ptr = 0x4087ffb0;

components/esp_rom/esp32c6/ld/esp32c6.rom.eco3.ld

@@ -0,0 +1,138 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ESP32C6 ECO3 ROM address table
+Version 3 API's imported from the ROM
+*/
+
+esf_buf_alloc_dynamic = 0x400015c0;
+esf_buf_recycle = 0x400015c4;
+/*lmacTxDone = 0x4000162c;*/
+/*ppMapTxQueue = 0x400016d8;*/
+rcGetSched = 0x40001764;
+wDevCheckBlockError = 0x400017b4;
+/*ppProcTxDone = 0x40001804;*/
+sta_input = rom_sta_input;
+
+/***************************************
+ Group rom_phy
+ ***************************************/
+
+/* Functions */
+rom_index_to_txbbgain = 0x40001964;
+rom_pbus_xpd_tx_on = 0x400019b0;
+rom_set_tx_dig_gain = 0x400019f0;
+rom_set_txcap_reg = 0x400019f4;
+rom_txbbgain_to_index = 0x40001a0c;
+rom_agc_reg_init = 0x40001a54;
+rom_bb_reg_init = 0x40001a58;
+rom_set_pbus_reg = 0x40001a70;
+rom_phy_xpd_rf = 0x40001a78;
+rom_write_txrate_power_offset = 0x40001a8c;
+rom_temp_to_power = 0x40001ab4;
+rom_open_i2c_xpd = 0x40001af8;
+rom_tsens_read_init = 0x40001b00;
+rom_tsens_code_read = 0x40001b04;
+rom_tsens_dac_cal = 0x40001b10;
+rom_pll_vol_cal = 0x40001b28;
+
+/***************************************
+   Group eco3_wifi
+ ***************************************/
+
+/* Functions */
+wdev_is_data_in_rxlist = 0x40001b2c;
+ppProcTxCallback = 0x40001b30;
+ieee80211_gettid = 0x40001b34;
+
+
+/***************************************
+   Group eco3_bluetooth
+ ***************************************/
+
+/* Functions */
+r_lld_legacy_adv_dynamic_pti_get = 0x40001b38;
+r_lld_legacy_adv_dynamic_pti_process = 0x40001b3c;
+r_lld_ext_adv_dynamic_pti_get = 0x40001b40;
+r_lld_ext_adv_dynamic_aux_pti_process = 0x40001b44;
+r_lld_ext_adv_dynamic_pti_process = 0x40001b48;
+r_lld_adv_ext_pkt_prepare_set = 0x40001b4c;
+r_lld_adv_ext_chain_none_construct = 0x40001b50;
+r_lld_adv_ext_chain_connectable_construct = 0x40001b54;
+r_lld_adv_ext_chain_scannable_construct = 0x40001b58;
+r_lld_adv_pkt_rx_connect_post = 0x40001b5c;
+r_lld_adv_start_init_evt_param = 0x40001b60;
+r_lld_adv_start_set_cs = 0x40001b64;
+r_lld_adv_start_update_filter_policy = 0x40001b68;
+r_lld_adv_start_schedule_asap = 0x40001b6c;
+r_lld_con_tx_prog_new_packet_coex = 0x40001b70;
+r_lld_con_tx_prog_new_packet = 0x40001b74;
+r_lld_per_adv_dynamic_pti_get = 0x40001b78;
+r_lld_per_adv_evt_start_chm_upd = 0x40001b7c;
+r_lld_ext_scan_dynamic_pti_get = 0x40001b80;
+r_lld_scan_try_sched = 0x40001b84;
+r_lld_sync_insert = 0x40001b88;
+r_sch_prog_ble_push = 0x40001b8c;
+r_sch_prog_bt_push = 0x40001b90;
+r_lld_init_evt_end_type_set = 0x40001b94;
+r_lld_init_evt_end_type_get = 0x40001b98;
+r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40001b9c;
+r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x40001ba0;
+r_lld_init_evt_end_type_check_state_set = 0x40001ba4;
+r_lld_init_evt_end_type_check_state_get = 0x40001ba8;
+
+
+/***************************************
+   Group eco3_phy
+ ***************************************/
+
+/* Functions */
+rom_wrtie_pll_cap = 0x40001bac;
+rom_set_tx_gain_mem = 0x40001bb0;
+rom_bt_tx_dig_gain = 0x40001bb4;
+rom_bt_get_tx_gain = 0x40001bb8;
+rom_get_chan_target_power = 0x40001bbc;
+rom_get_tx_gain_value = 0x40001bc0;
+rom_wifi_tx_dig_gain = 0x40001bc4;
+rom_wifi_get_tx_gain = 0x40001bc8;
+rom_fe_i2c_reg_renew = 0x40001bcc;
+rom_wifi_agc_sat_gain = 0x40001bd0;
+rom_i2c_master_reset = 0x40001bd4;
+rom_bt_filter_reg = 0x40001bd8;
+rom_phy_bbpll_cal = 0x40001bdc;
+rom_i2c_sar2_init_code = 0x40001be0;
+rom_phy_param_addr = 0x40001be4;
+rom_phy_reg_init = 0x40001be8;
+rom_set_chan_reg = 0x40001bec;
+rom_phy_wakeup_init = 0x40001bf0;
+rom_phy_i2c_init1 = 0x40001bf4;
+rom_tsens_temp_read = 0x40001bf8;
+rom_bt_track_pll_cap = 0x40001bfc;
+rom_wifi_track_pll_cap = 0x40001c00;
+rom_wifi_set_tx_gain = 0x40001c04;
+rom_txpwr_cal_track = 0x40001c08;
+rom_tx_pwctrl_background = 0x40001c0c;
+rom_bt_set_tx_gain = 0x40001c10;
+rom_noise_check_loop = 0x40001c14;
+rom_phy_close_rf = 0x40001c18;
+rom_phy_xpd_tsens = 0x40001c1c;
+rom_phy_freq_mem_backup = 0x40001c20;
+rom_phy_ant_init = 0x40001c24;
+rom_bt_track_tx_power = 0x40001c28;
+rom_wifi_track_tx_power = 0x40001c2c;
+rom_phy_dig_reg_backup = 0x40001c30;
+chip726_phyrom_version_num = 0x40001c34;
+/* Data (.data, .bss, .rodata) */
+phy_param_rom = 0x3fcdf830;
+
+/***************************************
+   Group eco3_esp_flash
+ ***************************************/
+
+/* Functions */
+PROVIDE( esp_flash_read_chip_id = 0x40001c38 );
+PROVIDE( detect_spi_flash_chip = 0x40001c3c );
+PROVIDE( esp_rom_spiflash_write_disable = 0x40001c40 );

components/esp_rom/esp32c6/ld/esp32c6.rom.heap.ld

@@ -0,0 +1,80 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.heap.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group heap
+ ***************************************/
+
+/* Functions */
+tlsf_create = 0x400003fc;
+tlsf_create_with_pool = 0x40000400;
+tlsf_get_pool = 0x40000404;
+tlsf_add_pool = 0x40000408;
+tlsf_remove_pool = 0x4000040c;
+tlsf_malloc = 0x40000410;
+tlsf_memalign = 0x40000414;
+tlsf_memalign_offs = 0x40000418;
+tlsf_realloc = 0x4000041c;
+tlsf_free = 0x40000420;
+tlsf_block_size = 0x40000424;
+tlsf_size = 0x40000428;
+tlsf_align_size = 0x4000042c;
+tlsf_block_size_min = 0x40000430;
+tlsf_block_size_max = 0x40000434;
+tlsf_pool_overhead = 0x40000438;
+tlsf_alloc_overhead = 0x4000043c;
+tlsf_walk_pool = 0x40000440;
+tlsf_check = 0x40000444;
+tlsf_check_pool = 0x40000448;
+tlsf_poison_fill_pfunc_set = 0x4000044c;
+tlsf_poison_check_pfunc_set = 0x40000450;
+multi_heap_get_block_address_impl = 0x40000454;
+multi_heap_get_allocated_size_impl = 0x40000458;
+multi_heap_register_impl = 0x4000045c;
+multi_heap_set_lock = 0x40000460;
+multi_heap_os_funcs_init = 0x40000464;
+multi_heap_internal_lock = 0x40000468;
+multi_heap_internal_unlock = 0x4000046c;
+multi_heap_get_first_block = 0x40000470;
+multi_heap_get_next_block = 0x40000474;
+multi_heap_is_free = 0x40000478;
+multi_heap_malloc_impl = 0x4000047c;
+multi_heap_free_impl = 0x40000480;
+multi_heap_realloc_impl = 0x40000484;
+multi_heap_aligned_alloc_impl_offs = 0x40000488;
+multi_heap_aligned_alloc_impl = 0x4000048c;
+multi_heap_check = 0x40000490;
+multi_heap_dump = 0x40000494;
+multi_heap_free_size_impl = 0x40000498;
+multi_heap_minimum_free_size_impl = 0x4000049c;
+multi_heap_get_info_impl = 0x400004a0;
+/* Data (.data, .bss, .rodata) */
+heap_tlsf_table_ptr = 0x4087ffd8;
+
+PROVIDE (multi_heap_malloc = multi_heap_malloc_impl);
+PROVIDE (multi_heap_free = multi_heap_free_impl);
+PROVIDE (multi_heap_realloc = multi_heap_realloc_impl);
+PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl);
+PROVIDE (multi_heap_register = multi_heap_register_impl);
+PROVIDE (multi_heap_get_info = multi_heap_get_info_impl);
+PROVIDE (multi_heap_free_size = multi_heap_free_size_impl);
+PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl);
+PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl);
+PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
+PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
+PROVIDE (multi_heap_check = multi_heap_check);
+PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
+PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
+PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);

components/esp_rom/esp32c6/ld/esp32c6.rom.ld

@@ -0,0 +1,476 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group common
+ ***************************************/
+
+/* Functions */
+rtc_get_reset_reason = 0x40000018;
+analog_super_wdt_reset_happened = 0x4000001c;
+rtc_get_wakeup_cause = 0x40000020;
+rtc_unhold_all_pads = 0x40000024;
+ets_printf = 0x40000028;
+ets_install_putc1 = 0x4000002c;
+ets_install_putc2 = 0x40000030;
+ets_install_uart_printf = 0x40000034;
+ets_install_usb_printf = 0x40000038;
+ets_get_printf_channel = 0x4000003c;
+ets_delay_us = 0x40000040;
+ets_get_cpu_frequency = 0x40000044;
+ets_update_cpu_frequency = 0x40000048;
+ets_install_lock = 0x4000004c;
+UartRxString = 0x40000050;
+UartGetCmdLn = 0x40000054;
+uart_tx_one_char = 0x40000058;
+uart_tx_one_char2 = 0x4000005c;
+uart_rx_one_char = 0x40000060;
+uart_rx_one_char_block = 0x40000064;
+uart_rx_intr_handler = 0x40000068;
+uart_rx_readbuff = 0x4000006c;
+uartAttach = 0x40000070;
+uart_tx_flush = 0x40000074;
+uart_tx_wait_idle = 0x40000078;
+uart_div_modify = 0x4000007c;
+ets_write_char_uart = 0x40000080;
+uart_tx_switch = 0x40000084;
+roundup2 = 0x40000088;
+multofup = 0x4000008c;
+software_reset = 0x40000090;
+software_reset_cpu = 0x40000094;
+ets_clk_assist_debug_clock_enable = 0x40000098;
+clear_super_wdt_reset_flag = 0x4000009c;
+disable_default_watchdog = 0x400000a0;
+esp_rom_set_rtc_wake_addr = 0x400000a4;
+esp_rom_get_rtc_wake_addr = 0x400000a8;
+send_packet = 0x400000ac;
+recv_packet = 0x400000b0;
+GetUartDevice = 0x400000b4;
+UartDwnLdProc = 0x400000b8;
+GetSecurityInfoProc = 0x400000bc;
+Uart_Init = 0x400000c0;
+ets_set_user_start = 0x400000c4;
+/* Data (.data, .bss, .rodata) */
+ets_rom_layout_p = 0x4004fffc;
+ets_ops_table_ptr = 0x4087fff8;
+g_saved_pc = 0x4087fffc;
+
+
+/***************************************
+ Group miniz
+ ***************************************/
+
+/* Functions */
+mz_adler32 = 0x400000c8;
+mz_free = 0x400000cc;
+tdefl_compress = 0x400000d0;
+tdefl_compress_buffer = 0x400000d4;
+tdefl_compress_mem_to_heap = 0x400000d8;
+tdefl_compress_mem_to_mem = 0x400000dc;
+tdefl_compress_mem_to_output = 0x400000e0;
+tdefl_get_adler32 = 0x400000e4;
+tdefl_get_prev_return_status = 0x400000e8;
+tdefl_init = 0x400000ec;
+tdefl_write_image_to_png_file_in_memory = 0x400000f0;
+tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4;
+tinfl_decompress = 0x400000f8;
+tinfl_decompress_mem_to_callback = 0x400000fc;
+tinfl_decompress_mem_to_heap = 0x40000100;
+tinfl_decompress_mem_to_mem = 0x40000104;
+
+
+/***************************************
+ Group tjpgd
+ ***************************************/
+
+/* Functions */
+jd_prepare = 0x40000108;
+jd_decomp = 0x4000010c;
+
+
+/***************************************
+ Group spiflash_legacy
+ ***************************************/
+
+/* Functions */
+esp_rom_spiflash_wait_idle = 0x40000110;
+esp_rom_spiflash_write_encrypted = 0x40000114;
+esp_rom_spiflash_write_encrypted_dest = 0x40000118;
+esp_rom_spiflash_write_encrypted_enable = 0x4000011c;
+esp_rom_spiflash_write_encrypted_disable = 0x40000120;
+esp_rom_spiflash_erase_chip = 0x40000124;
+_esp_rom_spiflash_erase_sector = 0x40000128;
+_esp_rom_spiflash_erase_block = 0x4000012c;
+_esp_rom_spiflash_write = 0x40000130;
+_esp_rom_spiflash_read = 0x40000134;
+_esp_rom_spiflash_unlock = 0x40000138;
+_SPIEraseArea = 0x4000013c;
+_SPI_write_enable = 0x40000140;
+esp_rom_spiflash_erase_sector = 0x40000144;
+esp_rom_spiflash_erase_block = 0x40000148;
+esp_rom_spiflash_write = 0x4000014c;
+esp_rom_spiflash_read = 0x40000150;
+esp_rom_spiflash_unlock = 0x40000154;
+SPIEraseArea = 0x40000158;
+SPI_write_enable = 0x4000015c;
+esp_rom_spiflash_config_param = 0x40000160;
+esp_rom_spiflash_read_user_cmd = 0x40000164;
+esp_rom_spiflash_select_qio_pins = 0x40000168;
+esp_rom_spi_flash_auto_sus_res = 0x4000016c;
+esp_rom_spi_flash_send_resume = 0x40000170;
+esp_rom_spi_flash_update_id = 0x40000174;
+esp_rom_spiflash_config_clk = 0x40000178;
+esp_rom_spiflash_config_readmode = 0x4000017c;
+esp_rom_spiflash_read_status = 0x40000180;
+esp_rom_spiflash_read_statushigh = 0x40000184;
+esp_rom_spiflash_write_status = 0x40000188;
+spi_cache_mode_switch = 0x4000018c;
+spi_common_set_dummy_output = 0x40000190;
+spi_common_set_flash_cs_timing = 0x40000194;
+esp_rom_spi_set_address_bit_len = 0x40000198;
+SPILock = 0x4000019c;
+SPIMasterReadModeCnfig = 0x400001a0;
+SPI_Common_Command = 0x400001a4;
+SPI_WakeUp = 0x400001a8;
+SPI_block_erase = 0x400001ac;
+SPI_chip_erase = 0x400001b0;
+SPI_init = 0x400001b4;
+SPI_page_program = 0x400001b8;
+SPI_read_data = 0x400001bc;
+SPI_sector_erase = 0x400001c0;
+SelectSpiFunction = 0x400001c4;
+SetSpiDrvs = 0x400001c8;
+Wait_SPI_Idle = 0x400001cc;
+spi_dummy_len_fix = 0x400001d0;
+Disable_QMode = 0x400001d4;
+Enable_QMode = 0x400001d8;
+spi_flash_attach = 0x400001dc;
+spi_flash_get_chip_size = 0x400001e0;
+spi_flash_guard_set = 0x400001e4;
+spi_flash_guard_get = 0x400001e8;
+spi_flash_read_encrypted = 0x400001ec;
+/* Data (.data, .bss, .rodata) */
+rom_spiflash_legacy_funcs = 0x4087fff0;
+rom_spiflash_legacy_data = 0x4087ffec;
+g_flash_guard_ops = 0x4087fff4;
+
+
+/***************************************
+ Group hal_wdt
+ ***************************************/
+
+/* Functions */
+wdt_hal_init = 0x40000394;
+wdt_hal_deinit = 0x40000398;
+wdt_hal_config_stage = 0x4000039c;
+wdt_hal_write_protect_disable = 0x400003a0;
+wdt_hal_write_protect_enable = 0x400003a4;
+wdt_hal_enable = 0x400003a8;
+wdt_hal_disable = 0x400003ac;
+wdt_hal_handle_intr = 0x400003b0;
+wdt_hal_feed = 0x400003b4;
+wdt_hal_set_flashboot_en = 0x400003b8;
+wdt_hal_is_enabled = 0x400003bc;
+
+
+/***************************************
+ Group hal_systimer
+ ***************************************/
+
+/* Functions */
+systimer_hal_init = 0x400003c0;
+systimer_hal_deinit = 0x400003c4;
+systimer_hal_set_tick_rate_ops = 0x400003c8;
+systimer_hal_get_counter_value = 0x400003cc;
+systimer_hal_get_time = 0x400003d0;
+systimer_hal_set_alarm_target = 0x400003d4;
+systimer_hal_set_alarm_period = 0x400003d8;
+systimer_hal_get_alarm_value = 0x400003dc;
+systimer_hal_enable_alarm_int = 0x400003e0;
+systimer_hal_on_apb_freq_update = 0x400003e4;
+systimer_hal_counter_value_advance = 0x400003e8;
+systimer_hal_enable_counter = 0x400003ec;
+systimer_hal_select_alarm_mode = 0x400003f0;
+systimer_hal_connect_alarm_counter = 0x400003f4;
+systimer_hal_counter_can_stall_by_cpu = 0x400003f8;
+
+
+/***************************************
+ Group cache
+ ***************************************/
+
+/* Functions */
+Cache_Get_ICache_Line_Size = 0x40000628;
+Cache_Get_Mode = 0x4000062c;
+Cache_Address_Through_Cache = 0x40000630;
+ROM_Boot_Cache_Init = 0x40000634;
+MMU_Set_Page_Mode = 0x40000638;
+MMU_Get_Page_Mode = 0x4000063c;
+Cache_Invalidate_ICache_Items = 0x40000640;
+Cache_Op_Addr = 0x40000644;
+Cache_Invalidate_Addr = 0x40000648;
+Cache_Invalidate_ICache_All = 0x4000064c;
+Cache_Mask_All = 0x40000650;
+Cache_UnMask_Dram0 = 0x40000654;
+Cache_Suspend_ICache_Autoload = 0x40000658;
+Cache_Resume_ICache_Autoload = 0x4000065c;
+Cache_Start_ICache_Preload = 0x40000660;
+Cache_ICache_Preload_Done = 0x40000664;
+Cache_End_ICache_Preload = 0x40000668;
+Cache_Config_ICache_Autoload = 0x4000066c;
+Cache_Enable_ICache_Autoload = 0x40000670;
+Cache_Disable_ICache_Autoload = 0x40000674;
+Cache_Enable_ICache_PreLock = 0x40000678;
+Cache_Disable_ICache_PreLock = 0x4000067c;
+Cache_Lock_ICache_Items = 0x40000680;
+Cache_Unlock_ICache_Items = 0x40000684;
+Cache_Lock_Addr = 0x40000688;
+Cache_Unlock_Addr = 0x4000068c;
+Cache_Disable_ICache = 0x40000690;
+Cache_Enable_ICache = 0x40000694;
+Cache_Suspend_ICache = 0x40000698;
+Cache_Resume_ICache = 0x4000069c;
+Cache_Freeze_ICache_Enable = 0x400006a0;
+Cache_Freeze_ICache_Disable = 0x400006a4;
+Cache_Set_IDROM_MMU_Size = 0x400006a8;
+Cache_Get_IROM_MMU_End = 0x400006ac;
+Cache_Get_DROM_MMU_End = 0x400006b0;
+Cache_MMU_Init = 0x400006b4;
+Cache_MSPI_MMU_Set = 0x400006b8;
+Cache_Travel_Tag_Memory = 0x400006bc;
+Cache_Get_Virtual_Addr = 0x400006c0;
+/* Data (.data, .bss, .rodata) */
+rom_cache_op_cb = 0x4087ffcc;
+rom_cache_internal_table_ptr = 0x4087ffc8;
+
+
+/***************************************
+ Group clock
+ ***************************************/
+
+/* Functions */
+ets_clk_get_xtal_freq = 0x400006c4;
+ets_clk_get_cpu_freq = 0x400006c8;
+ets_clk_apb_wait_ready = 0x400006cc;
+ets_clk_mspi_apb_wait_ready = 0x400006d0;
+
+
+/***************************************
+ Group gpio
+ ***************************************/
+
+/* Functions */
+gpio_input_get = 0x400006d4;
+gpio_matrix_in = 0x400006d8;
+gpio_matrix_out = 0x400006dc;
+gpio_output_disable = 0x400006e0;
+gpio_output_enable = 0x400006e4;
+gpio_output_set = 0x400006e8;
+gpio_pad_hold = 0x400006ec;
+gpio_pad_input_disable = 0x400006f0;
+gpio_pad_input_enable = 0x400006f4;
+gpio_pad_pulldown = 0x400006f8;
+gpio_pad_pullup = 0x400006fc;
+gpio_pad_select_gpio = 0x40000700;
+gpio_pad_set_drv = 0x40000704;
+gpio_pad_unhold = 0x40000708;
+gpio_pin_wakeup_disable = 0x4000070c;
+gpio_pin_wakeup_enable = 0x40000710;
+gpio_bypass_matrix_in = 0x40000714;
+
+
+/***************************************
+ Group interrupts
+ ***************************************/
+
+/* Functions */
+esprv_intc_int_set_priority = 0x40000718;
+esprv_intc_int_set_threshold = 0x4000071c;
+esprv_intc_int_enable = 0x40000720;
+esprv_intc_int_disable = 0x40000724;
+esprv_intc_int_set_type = 0x40000728;
+PROVIDE( intr_handler_set = 0x4000072c );
+intr_matrix_set = 0x40000730;
+ets_intr_lock = 0x40000734;
+ets_intr_unlock = 0x40000738;
+ets_isr_attach = 0x4000073c;
+ets_isr_mask = 0x40000740;
+ets_isr_unmask = 0x40000744;
+
+
+/***************************************
+ Group crypto
+ ***************************************/
+
+/* Functions */
+md5_vector = 0x40000748;
+MD5Init = 0x4000074c;
+MD5Update = 0x40000750;
+MD5Final = 0x40000754;
+crc32_le = 0x40000758;
+crc16_le = 0x4000075c;
+crc8_le = 0x40000760;
+crc32_be = 0x40000764;
+crc16_be = 0x40000768;
+crc8_be = 0x4000076c;
+esp_crc8 = 0x40000770;
+ets_sha_enable = 0x40000774;
+ets_sha_disable = 0x40000778;
+ets_sha_get_state = 0x4000077c;
+ets_sha_init = 0x40000780;
+ets_sha_process = 0x40000784;
+ets_sha_starts = 0x40000788;
+ets_sha_update = 0x4000078c;
+ets_sha_finish = 0x40000790;
+ets_sha_clone = 0x40000794;
+ets_hmac_enable = 0x40000798;
+ets_hmac_disable = 0x4000079c;
+ets_hmac_calculate_message = 0x400007a0;
+ets_hmac_calculate_downstream = 0x400007a4;
+ets_hmac_invalidate_downstream = 0x400007a8;
+ets_jtag_enable_temporarily = 0x400007ac;
+ets_aes_enable = 0x400007b0;
+ets_aes_disable = 0x400007b4;
+ets_aes_setkey = 0x400007b8;
+ets_aes_block = 0x400007bc;
+ets_aes_setkey_dec = 0x400007c0;
+ets_aes_setkey_enc = 0x400007c4;
+ets_bigint_enable = 0x400007c8;
+ets_bigint_disable = 0x400007cc;
+ets_bigint_multiply = 0x400007d0;
+ets_bigint_modmult = 0x400007d4;
+ets_bigint_modexp = 0x400007d8;
+ets_bigint_wait_finish = 0x400007dc;
+ets_bigint_getz = 0x400007e0;
+ets_ds_enable = 0x400007e4;
+ets_ds_disable = 0x400007e8;
+ets_ds_start_sign = 0x400007ec;
+ets_ds_is_busy = 0x400007f0;
+ets_ds_finish_sign = 0x400007f4;
+ets_ds_encrypt_params = 0x400007f8;
+ets_mgf1_sha256 = 0x400007fc;
+/* Data (.data, .bss, .rodata) */
+crc32_le_table_ptr = 0x4004fff8;
+crc16_le_table_ptr = 0x4004fff4;
+crc8_le_table_ptr = 0x4004fff0;
+crc32_be_table_ptr = 0x4004ffec;
+crc16_be_table_ptr = 0x4004ffe8;
+crc8_be_table_ptr = 0x4004ffe4;
+
+
+/***************************************
+ Group efuse
+ ***************************************/
+
+/* Functions */
+ets_efuse_read = 0x40000800;
+ets_efuse_program = 0x40000804;
+ets_efuse_clear_program_registers = 0x40000808;
+ets_efuse_write_key = 0x4000080c;
+ets_efuse_get_read_register_address = 0x40000810;
+ets_efuse_get_key_purpose = 0x40000814;
+ets_efuse_key_block_unused = 0x40000818;
+ets_efuse_find_unused_key_block = 0x4000081c;
+ets_efuse_rs_calculate = 0x40000820;
+ets_efuse_count_unused_key_blocks = 0x40000824;
+ets_efuse_secure_boot_enabled = 0x40000828;
+ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000082c;
+ets_efuse_cache_encryption_enabled = 0x40000830;
+ets_efuse_download_modes_disabled = 0x40000834;
+ets_efuse_find_purpose = 0x40000838;
+ets_efuse_force_send_resume = 0x4000083c;
+ets_efuse_get_flash_delay_us = 0x40000840;
+ets_efuse_get_mac = 0x40000844;
+ets_efuse_get_uart_print_control = 0x40000848;
+ets_efuse_direct_boot_mode_disabled = 0x4000084c;
+ets_efuse_security_download_modes_enabled = 0x40000850;
+ets_efuse_set_timing = 0x40000854;
+ets_efuse_jtag_disabled = 0x40000858;
+ets_efuse_usb_print_is_disabled = 0x4000085c;
+ets_efuse_usb_download_mode_disabled = 0x40000860;
+ets_efuse_usb_device_disabled = 0x40000864;
+ets_efuse_secure_boot_fast_wake_enabled = 0x40000868;
+
+
+/***************************************
+ Group secureboot
+ ***************************************/
+
+/* Functions */
+ets_emsa_pss_verify = 0x4000086c;
+ets_rsa_pss_verify = 0x40000870;
+ets_secure_boot_verify_bootloader_with_keys = 0x40000874;
+ets_secure_boot_verify_signature = 0x40000878;
+ets_secure_boot_read_key_digests = 0x4000087c;
+ets_secure_boot_revoke_public_key_digest = 0x40000880;
+
+
+/***************************************
+ Group usb_device_uart
+ ***************************************/
+
+/* Functions */
+usb_serial_device_rx_one_char = 0x40000a80;
+usb_serial_device_rx_one_char_block = 0x40000a84;
+usb_serial_device_tx_flush = 0x40000a88;
+usb_serial_device_tx_one_char = 0x40000a8c;
+
+
+/***************************************
+ Group lldesc
+ ***************************************/
+
+/* Functions */
+lldesc_build_chain = 0x40000a90;
+
+
+/***************************************
+ Group sip
+ ***************************************/
+
+/* Functions */
+sip_after_tx_complete = 0x40000a94;
+sip_alloc_to_host_evt = 0x40000a98;
+sip_download_begin = 0x40000a9c;
+sip_get_ptr = 0x40000aa0;
+sip_get_state = 0x40000aa4;
+sip_init_attach = 0x40000aa8;
+sip_install_rx_ctrl_cb = 0x40000aac;
+sip_install_rx_data_cb = 0x40000ab0;
+sip_is_active = 0x40000ab4;
+sip_post_init = 0x40000ab8;
+sip_reclaim_from_host_cmd = 0x40000abc;
+sip_reclaim_tx_data_pkt = 0x40000ac0;
+sip_send = 0x40000ac4;
+sip_to_host_chain_append = 0x40000ac8;
+sip_to_host_evt_send_done = 0x40000acc;
+
+
+/***************************************
+ Group slc
+ ***************************************/
+
+/* Functions */
+slc_add_credits = 0x40000ad0;
+slc_enable = 0x40000ad4;
+slc_from_host_chain_fetch = 0x40000ad8;
+slc_from_host_chain_recycle = 0x40000adc;
+slc_has_pkt_to_host = 0x40000ae0;
+slc_init_attach = 0x40000ae4;
+slc_init_credit = 0x40000ae8;
+slc_reattach = 0x40000aec;
+slc_send_to_host_chain = 0x40000af0;
+slc_set_host_io_max_window = 0x40000af4;
+slc_to_host_chain_recycle = 0x40000af8;

components/esp_rom/esp32c6/ld/esp32c6.rom.libgcc.ld

@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.libgcc.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libgcc
+ ***************************************/
+
+/* Functions */
+__absvdi2 = 0x40000884;
+__absvsi2 = 0x40000888;
+__adddf3 = 0x4000088c;
+__addsf3 = 0x40000890;
+__addvdi3 = 0x40000894;
+__addvsi3 = 0x40000898;
+__ashldi3 = 0x4000089c;
+__ashrdi3 = 0x400008a0;
+__bswapdi2 = 0x400008a4;
+__bswapsi2 = 0x400008a8;
+__clear_cache = 0x400008ac;
+__clrsbdi2 = 0x400008b0;
+__clrsbsi2 = 0x400008b4;
+__clzdi2 = 0x400008b8;
+__clzsi2 = 0x400008bc;
+__cmpdi2 = 0x400008c0;
+__ctzdi2 = 0x400008c4;
+__ctzsi2 = 0x400008c8;
+__divdc3 = 0x400008cc;
+__divdf3 = 0x400008d0;
+__divdi3 = 0x400008d4;
+__divsc3 = 0x400008d8;
+__divsf3 = 0x400008dc;
+__divsi3 = 0x400008e0;
+__eqdf2 = 0x400008e4;
+__eqsf2 = 0x400008e8;
+__extendsfdf2 = 0x400008ec;
+__ffsdi2 = 0x400008f0;
+__ffssi2 = 0x400008f4;
+__fixdfdi = 0x400008f8;
+__fixdfsi = 0x400008fc;
+__fixsfdi = 0x40000900;
+__fixsfsi = 0x40000904;
+__fixunsdfsi = 0x40000908;
+__fixunssfdi = 0x4000090c;
+__fixunssfsi = 0x40000910;
+__floatdidf = 0x40000914;
+__floatdisf = 0x40000918;
+__floatsidf = 0x4000091c;
+__floatsisf = 0x40000920;
+__floatundidf = 0x40000924;
+__floatundisf = 0x40000928;
+__floatunsidf = 0x4000092c;
+__floatunsisf = 0x40000930;
+__gcc_bcmp = 0x40000934;
+__gedf2 = 0x40000938;
+__gesf2 = 0x4000093c;
+__gtdf2 = 0x40000940;
+__gtsf2 = 0x40000944;
+__ledf2 = 0x40000948;
+__lesf2 = 0x4000094c;
+__lshrdi3 = 0x40000950;
+__ltdf2 = 0x40000954;
+__ltsf2 = 0x40000958;
+__moddi3 = 0x4000095c;
+__modsi3 = 0x40000960;
+__muldc3 = 0x40000964;
+__muldf3 = 0x40000968;
+__muldi3 = 0x4000096c;
+__mulsc3 = 0x40000970;
+__mulsf3 = 0x40000974;
+__mulsi3 = 0x40000978;
+__mulvdi3 = 0x4000097c;
+__mulvsi3 = 0x40000980;
+__nedf2 = 0x40000984;
+__negdf2 = 0x40000988;
+__negdi2 = 0x4000098c;
+__negsf2 = 0x40000990;
+__negvdi2 = 0x40000994;
+__negvsi2 = 0x40000998;
+__nesf2 = 0x4000099c;
+__paritysi2 = 0x400009a0;
+__popcountdi2 = 0x400009a4;
+__popcountsi2 = 0x400009a8;
+__powidf2 = 0x400009ac;
+__powisf2 = 0x400009b0;
+__subdf3 = 0x400009b4;
+__subsf3 = 0x400009b8;
+__subvdi3 = 0x400009bc;
+__subvsi3 = 0x400009c0;
+__truncdfsf2 = 0x400009c4;
+__ucmpdi2 = 0x400009c8;
+__udivdi3 = 0x400009cc;
+__udivmoddi4 = 0x400009d0;
+__udivsi3 = 0x400009d4;
+__udiv_w_sdiv = 0x400009d8;
+__umoddi3 = 0x400009dc;
+__umodsi3 = 0x400009e0;
+__unorddf2 = 0x400009e4;
+__unordsf2 = 0x400009e8;
+__extenddftf2 = 0x400009ec;
+__trunctfdf2 = 0x400009f0;

components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld

@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.net80211.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group rom_net80211
+ ***************************************/
+
+/* Functions */
+esp_net80211_rom_version_get = 0x40000b4c;
+ampdu_dispatch = 0x40000b50;
+ampdu_dispatch_all = 0x40000b54;
+ampdu_dispatch_as_many_as_possible = 0x40000b58;
+ampdu_dispatch_movement = 0x40000b5c;
+ampdu_dispatch_upto = 0x40000b60;
+chm_is_at_home_channel = 0x40000b64;
+cnx_node_is_existing = 0x40000b68;
+cnx_node_search = 0x40000b6c;
+ic_ebuf_recycle_rx = 0x40000b70;
+ic_ebuf_recycle_tx = 0x40000b74;
+ic_reset_rx_ba = 0x40000b78;
+ieee80211_align_eb = 0x40000b7c;
+ieee80211_ampdu_reorder = 0x40000b80;
+ieee80211_ampdu_start_age_timer = 0x40000b84;
+ieee80211_encap_esfbuf = 0x40000b88;
+ieee80211_is_tx_allowed = 0x40000b8c;
+ieee80211_output_pending_eb = 0x40000b90;
+ieee80211_output_process = 0x40000b94;
+ieee80211_set_tx_desc = 0x40000b98;
+sta_input = 0x40000b9c;
+wifi_get_macaddr = 0x40000ba0;
+wifi_rf_phy_disable = 0x40000ba4;
+wifi_rf_phy_enable = 0x40000ba8;
+ic_ebuf_alloc = 0x40000bac;
+ieee80211_classify = 0x40000bb0;
+ieee80211_copy_eb_header = 0x40000bb4;
+ieee80211_recycle_cache_eb = 0x40000bb8;
+ieee80211_search_node = 0x40000bbc;
+ieee80211_crypto_encap = 0x40000bc0;
+ieee80211_crypto_decap = 0x40000bc4;
+ieee80211_decap = 0x40000bc8;
+ieee80211_set_tx_pti = 0x40000bcc;
+wifi_is_started = 0x40000bd0;
+ieee80211_gettid = 0x40000bd4;
+/* Data (.data, .bss, .rodata) */
+net80211_funcs = 0x4087ffac;
+g_scan = 0x4087ffa8;
+g_chm = 0x4087ffa4;
+g_ic_ptr = 0x4087ffa0;
+g_hmac_cnt_ptr = 0x4087ff9c;
+g_tx_cacheq_ptr = 0x4087ff98;
+s_netstack_free = 0x4087ff94;
+mesh_rxcb = 0x4087ff90;
+sta_rxcb = 0x4087ff8c;

components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-nano.ld

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.newlib-nano.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum ff3b116f1987b5a5433645b8f7947f32
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib_nano_format
+ ***************************************/
+
+/* Functions */
+__sprint_r = 0x400005c8;
+_fiprintf_r = 0x400005cc;
+_fprintf_r = 0x400005d0;
+_printf_common = 0x400005d4;
+_printf_i = 0x400005d8;
+_vfiprintf_r = 0x400005dc;
+_vfprintf_r = 0x400005e0;
+fiprintf = 0x400005e4;
+fprintf = 0x400005e8;
+printf = 0x400005ec;
+vfiprintf = 0x400005f0;
+vfprintf = 0x400005f4;

components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-normal.ld

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.newlib-normal.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib_normal_format
+ ***************************************/
+
+/* Functions */
+__sprint_r = 0x400005d4;
+_fiprintf_r = 0x400005d8;
+_fprintf_r = 0x400005dc;
+_vfiprintf_r = 0x400005e0;
+_vfprintf_r = 0x400005e4;
+fiprintf = 0x400005e8;
+fprintf = 0x400005ec;
+printf = 0x400005f0;
+vfiprintf = 0x400005f4;
+vfprintf = 0x400005f8;
+asprintf = 0x400005fc;
+sprintf = 0x40000600;
+snprintf = 0x40000604;
+siprintf = 0x40000608;
+sniprintf = 0x4000060c;
+vprintf = 0x40000610;
+viprintf = 0x40000614;
+vsnprintf = 0x40000618;
+vsniprintf = 0x4000061c;
+sscanf = 0x40000620;
+siscanf = 0x40000624;

components/esp_rom/esp32c6/ld/esp32c6.rom.newlib-time.ld

@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* These are the newlib functions and the .bss/.data symbols which are related to 'time_t'
+   or other structures which include 'time_t' (like 'struct stat').
+   These ROM functions were compiled with sizeof(time_t) == 4.
+   When compiling with sizeof(time_t) == 8, these functions should be excluded from the build.
+ */
+
+_isatty_r = 0x40000380;
+PROVIDE( __smakebuf_r = 0x4000046c );
+PROVIDE( __swhatbuf_r = 0x40000470 );
+PROVIDE( __swsetup_r = 0x4000047c );

components/esp_rom/esp32c6/ld/esp32c6.rom.newlib.ld

@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.newlib.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib
+ ***************************************/
+
+/* Functions */
+esp_rom_newlib_init_common_mutexes = 0x400004a4;
+memset = 0x400004a8;
+memcpy = 0x400004ac;
+memmove = 0x400004b0;
+memcmp = 0x400004b4;
+strcpy = 0x400004b8;
+strncpy = 0x400004bc;
+strcmp = 0x400004c0;
+strncmp = 0x400004c4;
+strlen = 0x400004c8;
+strstr = 0x400004cc;
+bzero = 0x400004d0;
+_isatty_r = 0x400004d4;
+sbrk = 0x400004d8;
+isalnum = 0x400004dc;
+isalpha = 0x400004e0;
+isascii = 0x400004e4;
+isblank = 0x400004e8;
+iscntrl = 0x400004ec;
+isdigit = 0x400004f0;
+islower = 0x400004f4;
+isgraph = 0x400004f8;
+isprint = 0x400004fc;
+ispunct = 0x40000500;
+isspace = 0x40000504;
+isupper = 0x40000508;
+toupper = 0x4000050c;
+tolower = 0x40000510;
+toascii = 0x40000514;
+memccpy = 0x40000518;
+memchr = 0x4000051c;
+memrchr = 0x40000520;
+strcasecmp = 0x40000524;
+strcasestr = 0x40000528;
+strcat = 0x4000052c;
+strdup = 0x40000530;
+strchr = 0x40000534;
+strcspn = 0x40000538;
+strcoll = 0x4000053c;
+strlcat = 0x40000540;
+strlcpy = 0x40000544;
+strlwr = 0x40000548;
+strncasecmp = 0x4000054c;
+strncat = 0x40000550;
+strndup = 0x40000554;
+strnlen = 0x40000558;
+strrchr = 0x4000055c;
+strsep = 0x40000560;
+strspn = 0x40000564;
+strtok_r = 0x40000568;
+strupr = 0x4000056c;
+longjmp = 0x40000570;
+setjmp = 0x40000574;
+abs = 0x40000578;
+div = 0x4000057c;
+labs = 0x40000580;
+ldiv = 0x40000584;
+qsort = 0x40000588;
+rand_r = 0x4000058c;
+rand = 0x40000590;
+srand = 0x40000594;
+utoa = 0x40000598;
+itoa = 0x4000059c;
+atoi = 0x400005a0;
+atol = 0x400005a4;
+strtol = 0x400005a8;
+strtoul = 0x400005ac;
+fflush = 0x400005b0;
+_fflush_r = 0x400005b4;
+_fwalk = 0x400005b8;
+_fwalk_reent = 0x400005bc;
+__smakebuf_r = 0x400005c0;
+__swhatbuf_r = 0x400005c4;
+__swbuf_r = 0x400005c8;
+__swbuf = 0x400005cc;
+__swsetup_r = 0x400005d0;
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x4087ffd4;
+_global_impure_ptr = 0x4087ffd0;

components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld

@@ -0,0 +1,196 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.phy.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group rom_phy
+ ***************************************/
+
+/* Functions */
+phy_get_romfuncs = 0x40000e48;
+rom_abs_temp = 0x40000e4c;
+rom_bb_bss_cbw40_dig = 0x40000e50;
+rom_bb_wdg_test_en = 0x40000e54;
+rom_bb_wdt_get_status = 0x40000e58;
+rom_bb_wdt_int_enable = 0x40000e5c;
+rom_bb_wdt_rst_enable = 0x40000e60;
+rom_bb_wdt_timeout_clear = 0x40000e64;
+rom_cbw2040_cfg = 0x40000e68;
+rom_check_noise_floor = 0x40000e6c;
+rom_chip_i2c_readReg = 0x40000e70;
+rom_chip_i2c_writeReg = 0x40000e74;
+rom_correct_rf_ana_gain = 0x40000e78;
+rom_dc_iq_est = 0x40000e7c;
+rom_disable_agc = 0x40000e80;
+rom_en_pwdet = 0x40000e84;
+rom_enable_agc = 0x40000e88;
+rom_get_bbgain_db = 0x40000e8c;
+rom_get_data_sat = 0x40000e90;
+rom_get_i2c_read_mask = 0x40000e94;
+rom_get_pwctrl_correct = 0x40000e98;
+rom_get_rf_gain_qdb = 0x40000e9c;
+rom_i2c_readReg = 0x40000ea0;
+rom_i2c_readReg_Mask = 0x40000ea4;
+rom_i2c_writeReg = 0x40000ea8;
+rom_i2c_writeReg_Mask = 0x40000eac;
+rom_index_to_txbbgain = 0x40000eb0;
+rom_iq_est_disable = 0x40000eb4;
+rom_iq_est_enable = 0x40000eb8;
+rom_linear_to_db = 0x40000ebc;
+rom_loopback_mode_en = 0x40000ec0;
+rom_mhz2ieee = 0x40000ec4;
+rom_noise_floor_auto_set = 0x40000ec8;
+rom_pbus_debugmode = 0x40000ecc;
+rom_pbus_force_mode = 0x40000ed0;
+rom_pbus_force_test = 0x40000ed4;
+rom_pbus_rd = 0x40000ed8;
+rom_pbus_rd_addr = 0x40000edc;
+rom_pbus_rd_shift = 0x40000ee0;
+rom_pbus_set_dco = 0x40000ee4;
+rom_pbus_set_rxgain = 0x40000ee8;
+rom_pbus_workmode = 0x40000eec;
+rom_pbus_xpd_rx_off = 0x40000ef0;
+rom_pbus_xpd_rx_on = 0x40000ef4;
+rom_pbus_xpd_tx_off = 0x40000ef8;
+rom_pbus_xpd_tx_on = 0x40000efc;
+rom_phy_byte_to_word = 0x40000f00;
+rom_phy_disable_cca = 0x40000f04;
+rom_phy_enable_cca = 0x40000f08;
+rom_phy_get_noisefloor = 0x40000f0c;
+rom_phy_get_rx_freq = 0x40000f10;
+rom_phy_set_bbfreq_init = 0x40000f14;
+rom_pow_usr = 0x40000f18;
+rom_pwdet_sar2_init = 0x40000f1c;
+rom_read_hw_noisefloor = 0x40000f20;
+rom_read_sar_dout = 0x40000f24;
+rom_set_cal_rxdc = 0x40000f28;
+rom_set_chan_cal_interp = 0x40000f2c;
+rom_set_loopback_gain = 0x40000f30;
+rom_set_noise_floor = 0x40000f34;
+rom_set_rxclk_en = 0x40000f38;
+rom_set_tx_dig_gain = 0x40000f3c;
+rom_set_txcap_reg = 0x40000f40;
+rom_set_txclk_en = 0x40000f44;
+rom_spur_cal = 0x40000f48;
+rom_spur_reg_write_one_tone = 0x40000f4c;
+rom_target_power_add_backoff = 0x40000f50;
+rom_tx_pwctrl_bg_init = 0x40000f54;
+rom_txbbgain_to_index = 0x40000f58;
+rom_wifi_11g_rate_chg = 0x40000f5c;
+rom_write_gain_mem = 0x40000f60;
+chip726_phyrom_version = 0x40000f64;
+rom_disable_wifi_agc = 0x40000f68;
+rom_enable_wifi_agc = 0x40000f6c;
+rom_set_tx_gain_table = 0x40000f70;
+rom_bt_index_to_bb = 0x40000f74;
+rom_bt_bb_to_index = 0x40000f78;
+rom_wr_bt_tx_atten = 0x40000f7c;
+rom_wr_bt_tx_gain_mem = 0x40000f80;
+rom_spur_coef_cfg = 0x40000f84;
+rom_bb_bss_cbw40 = 0x40000f88;
+rom_set_cca = 0x40000f8c;
+rom_tx_paon_set = 0x40000f90;
+rom_i2cmst_reg_init = 0x40000f94;
+rom_iq_corr_enable = 0x40000f98;
+rom_fe_reg_init = 0x40000f9c;
+rom_agc_reg_init = 0x40000fa0;
+rom_bb_reg_init = 0x40000fa4;
+rom_mac_enable_bb = 0x40000fa8;
+rom_bb_wdg_cfg = 0x40000fac;
+rom_force_txon = 0x40000fb0;
+rom_fe_txrx_reset = 0x40000fb4;
+rom_set_rx_comp = 0x40000fb8;
+rom_set_pbus_reg = 0x40000fbc;
+rom_write_chan_freq = 0x40000fc0;
+rom_phy_xpd_rf = 0x40000fc4;
+rom_set_xpd_sar = 0x40000fc8;
+rom_write_dac_gain2 = 0x40000fcc;
+rom_get_target_power_offset = 0x40000fd0;
+rom_write_txrate_power_offset = 0x40000fd4;
+rom_get_rate_fcc_index = 0x40000fd8;
+rom_get_rate_target_power = 0x40000fdc;
+rom_write_wifi_dig_gain = 0x40000fe0;
+rom_bt_correct_rf_ana_gain = 0x40000fe4;
+rom_pkdet_vol_start = 0x40000fe8;
+rom_read_sar2_code = 0x40000fec;
+rom_get_sar2_vol = 0x40000ff0;
+rom_get_pll_vol = 0x40000ff4;
+rom_get_phy_target_power = 0x40000ff8;
+rom_temp_to_power = 0x40000ffc;
+rom_phy_track_pll_cap = 0x40001000;
+rom_phy_pwdet_always_en = 0x40001004;
+rom_phy_pwdet_onetime_en = 0x40001008;
+rom_get_i2c_mst0_mask = 0x4000100c;
+rom_get_i2c_hostid = 0x40001010;
+rom_enter_critical_phy = 0x40001014;
+rom_exit_critical_phy = 0x40001018;
+rom_chip_i2c_readReg_org = 0x4000101c;
+rom_i2c_paral_set_mst0 = 0x40001020;
+rom_i2c_paral_set_read = 0x40001024;
+rom_i2c_paral_read = 0x40001028;
+rom_i2c_paral_write = 0x4000102c;
+rom_i2c_paral_write_num = 0x40001030;
+rom_i2c_paral_write_mask = 0x40001034;
+rom_bb_bss_cbw40_ana = 0x40001038;
+rom_chan_to_freq = 0x4000103c;
+rom_open_i2c_xpd = 0x40001040;
+rom_dac_rate_set = 0x40001044;
+rom_tsens_read_init = 0x40001048;
+rom_tsens_code_read = 0x4000104c;
+rom_tsens_index_to_dac = 0x40001050;
+rom_tsens_index_to_offset = 0x40001054;
+rom_tsens_dac_cal = 0x40001058;
+rom_code_to_temp = 0x4000105c;
+rom_write_pll_cap_mem = 0x40001060;
+rom_pll_correct_dcap = 0x40001064;
+rom_phy_en_hw_set_freq = 0x40001068;
+rom_phy_dis_hw_set_freq = 0x4000106c;
+rom_pll_vol_cal = 0x40001070;
+rom_wrtie_pll_cap = 0x40001074;
+rom_set_tx_gain_mem = 0x40001078;
+rom_bt_tx_dig_gain = 0x4000107c;
+rom_bt_get_tx_gain = 0x40001080;
+rom_get_chan_target_power = 0x40001084;
+rom_get_tx_gain_value = 0x40001088;
+rom_wifi_tx_dig_gain = 0x4000108c;
+rom_wifi_get_tx_gain = 0x40001090;
+rom_fe_i2c_reg_renew = 0x40001094;
+rom_wifi_agc_sat_gain = 0x40001098;
+rom_i2c_master_reset = 0x4000109c;
+rom_bt_filter_reg = 0x400010a0;
+rom_phy_bbpll_cal = 0x400010a4;
+rom_i2c_sar2_init_code = 0x400010a8;
+rom_phy_param_addr = 0x400010ac;
+rom_phy_reg_init = 0x400010b0;
+rom_set_chan_reg = 0x400010b4;
+rom_phy_wakeup_init = 0x400010b8;
+rom_phy_i2c_init1 = 0x400010bc;
+rom_tsens_temp_read = 0x400010c0;
+rom_bt_track_pll_cap = 0x400010c4;
+rom_wifi_track_pll_cap = 0x400010c8;
+rom_wifi_set_tx_gain = 0x400010cc;
+rom_txpwr_cal_track = 0x400010d0;
+rom_tx_pwctrl_background = 0x400010d4;
+rom_bt_set_tx_gain = 0x400010d8;
+rom_noise_check_loop = 0x400010dc;
+rom_phy_close_rf = 0x400010e0;
+rom_phy_xpd_tsens = 0x400010e4;
+rom_phy_freq_mem_backup = 0x400010e8;
+rom_phy_ant_init = 0x400010ec;
+rom_bt_track_tx_power = 0x400010f0;
+rom_wifi_track_tx_power = 0x400010f4;
+rom_phy_dig_reg_backup = 0x400010f8;
+chip726_phyrom_version_num = 0x400010fc;
+/* Data (.data, .bss, .rodata) */
+phy_param_rom = 0x4087fcd8;

components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld

@@ -0,0 +1,263 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c6.rom.pp.ld for esp32c6
+ *
+ *
+ * Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group rom_pp
+ ***************************************/
+
+/* Functions */
+esp_pp_rom_version_get = 0x40000bd8;
+RC_GetBlockAckTime = 0x40000bdc;
+ebuf_list_remove = 0x40000be0;
+esf_buf_alloc = 0x40000be4;
+esf_buf_alloc_dynamic = 0x40000be8;
+esf_buf_recycle = 0x40000bec;
+GetAccess = 0x40000bf0;
+hal_mac_is_low_rate_enabled = 0x40000bf4;
+hal_mac_tx_get_blockack = 0x40000bf8;
+hal_mac_tx_set_ppdu = 0x40000bfc;
+ic_get_trc = 0x40000c00;
+ic_mac_deinit = 0x40000c04;
+ic_mac_init = 0x40000c08;
+ic_interface_enabled = 0x40000c0c;
+is_lmac_idle = 0x40000c10;
+lmacAdjustTimestamp = 0x40000c14;
+lmacDiscardAgedMSDU = 0x40000c18;
+lmacDiscardMSDU = 0x40000c1c;
+lmacEndFrameExchangeSequence = 0x40000c20;
+lmacIsIdle = 0x40000c24;
+lmacIsLongFrame = 0x40000c28;
+lmacMSDUAged = 0x40000c2c;
+lmacPostTxComplete = 0x40000c30;
+lmacProcessAllTxTimeout = 0x40000c34;
+lmacProcessCollisions = 0x40000c38;
+lmacProcessRxSucData = 0x40000c3c;
+lmacReachLongLimit = 0x40000c40;
+lmacReachShortLimit = 0x40000c44;
+lmacRecycleMPDU = 0x40000c48;
+lmacRxDone = 0x40000c4c;
+lmacSetTxFrame = 0x40000c50;
+lmacTxDone = 0x40000c54;
+lmacTxFrame = 0x40000c58;
+mac_tx_set_duration = 0x40000c5c;
+mac_tx_set_plcp0 = 0x40000c60;
+mac_tx_set_plcp1 = 0x40000c64;
+mac_tx_set_plcp2 = 0x40000c68;
+pm_check_state = 0x40000c6c;
+pm_disable_dream_timer = 0x40000c70;
+pm_disable_sleep_delay_timer = 0x40000c74;
+pm_dream = 0x40000c78;
+pm_mac_wakeup = 0x40000c7c;
+pm_mac_sleep = 0x40000c80;
+pm_enable_active_timer = 0x40000c84;
+pm_enable_sleep_delay_timer = 0x40000c88;
+pm_local_tsf_process = 0x40000c8c;
+pm_set_beacon_filter = 0x40000c90;
+pm_is_in_wifi_slice_threshold = 0x40000c94;
+pm_is_waked = 0x40000c98;
+pm_keep_alive = 0x40000c9c;
+pm_on_beacon_rx = 0x40000ca0;
+pm_on_data_rx = 0x40000ca4;
+pm_on_tbtt = 0x40000ca8;
+pm_parse_beacon = 0x40000cac;
+pm_process_tim = 0x40000cb0;
+pm_rx_beacon_process = 0x40000cb4;
+pm_rx_data_process = 0x40000cb8;
+pm_sleep = 0x40000cbc;
+pm_sleep_for = 0x40000cc0;
+pm_tbtt_process = 0x40000cc4;
+ppAMPDU2Normal = 0x40000cc8;
+ppAssembleAMPDU = 0x40000ccc;
+ppCalFrameTimes = 0x40000cd0;
+ppCalSubFrameLength = 0x40000cd4;
+ppCalTxAMPDULength = 0x40000cd8;
+ppCheckTxAMPDUlength = 0x40000cdc;
+ppDequeueRxq_Locked = 0x40000ce0;
+ppDequeueTxQ = 0x40000ce4;
+ppEmptyDelimiterLength = 0x40000ce8;
+ppEnqueueRxq = 0x40000cec;
+ppEnqueueTxDone = 0x40000cf0;
+ppGetTxframe = 0x40000cf4;
+ppMapTxQueue = 0x40000cf8;
+ppProcTxSecFrame = 0x40000cfc;
+ppProcessRxPktHdr = 0x40000d00;
+ppProcessTxQ = 0x40000d04;
+ppRecordBarRRC = 0x40000d08;
+ppRecycleAmpdu = 0x40000d0c;
+ppRecycleRxPkt = 0x40000d10;
+ppResortTxAMPDU = 0x40000d14;
+ppResumeTxAMPDU = 0x40000d18;
+ppRxFragmentProc = 0x40000d1c;
+ppRxPkt = 0x40000d20;
+ppRxProtoProc = 0x40000d24;
+ppSearchTxQueue = 0x40000d28;
+ppSearchTxframe = 0x40000d2c;
+ppSelectNextQueue = 0x40000d30;
+ppSubFromAMPDU = 0x40000d34;
+ppTask = 0x40000d38;
+ppTxPkt = 0x40000d3c;
+ppTxProtoProc = 0x40000d40;
+ppTxqUpdateBitmap = 0x40000d44;
+pp_coex_tx_request = 0x40000d48;
+pp_hdrsize = 0x40000d4c;
+pp_post = 0x40000d50;
+pp_process_hmac_waiting_txq = 0x40000d54;
+rcGetAmpduSched = 0x40000d58;
+rcUpdateRxDone = 0x40000d5c;
+rc_get_trc = 0x40000d60;
+rc_get_trc_by_index = 0x40000d64;
+rcAmpduLowerRate = 0x40000d68;
+rcampduuprate = 0x40000d6c;
+rcClearCurAMPDUSched = 0x40000d70;
+rcClearCurSched = 0x40000d74;
+rcClearCurStat = 0x40000d78;
+rcGetSched = 0x40000d7c;
+rcLowerSched = 0x40000d80;
+rcSetTxAmpduLimit = 0x40000d84;
+rcTxUpdatePer = 0x40000d88;
+rcUpdateAckSnr = 0x40000d8c;
+rcUpdateRate = 0x40000d90;
+rcUpdateTxDone = 0x40000d94;
+rcUpdateTxDoneAmpdu2 = 0x40000d98;
+rcUpSched = 0x40000d9c;
+rssi_margin = 0x40000da0;
+rx11NRate2AMPDULimit = 0x40000da4;
+TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000da8;
+TRC_AMPDU_PER_UP_THRESHOLD = 0x40000dac;
+trc_calc_duration = 0x40000db0;
+trc_isTxAmpduOperational = 0x40000db4;
+trc_onAmpduOp = 0x40000db8;
+TRC_PER_IS_GOOD = 0x40000dbc;
+trc_SetTxAmpduState = 0x40000dc0;
+trc_tid_isTxAmpduOperational = 0x40000dc4;
+trcAmpduSetState = 0x40000dc8;
+wDevCheckBlockError = 0x40000dcc;
+wDev_AppendRxBlocks = 0x40000dd0;
+wDev_DiscardFrame = 0x40000dd4;
+wDev_GetNoiseFloor = 0x40000dd8;
+wDev_IndicateAmpdu = 0x40000ddc;
+wDev_IndicateFrame = 0x40000de0;
+wdev_mac_reg_load = 0x40000de4;
+wdev_mac_reg_store = 0x40000de8;
+wdev_mac_special_reg_load = 0x40000dec;
+wdev_mac_special_reg_store = 0x40000df0;
+wdev_mac_wakeup = 0x40000df4;
+wdev_mac_sleep = 0x40000df8;
+hal_mac_is_dma_enable = 0x40000dfc;
+wDev_ProcessFiq = 0x40000e00;
+wDev_ProcessRxSucData = 0x40000e04;
+wdevProcessRxSucDataAll = 0x40000e08;
+wdev_csi_len_align = 0x40000e0c;
+ppDequeueTxDone_Locked = 0x40000e10;
+ppProcTxDone = 0x40000e14;
+pm_tx_data_done_process = 0x40000e18;
+config_is_cache_tx_buf_enabled = 0x40000e1c;
+ppMapWaitTxq = 0x40000e20;
+ppProcessWaitingQueue = 0x40000e24;
+ppDisableQueue = 0x40000e28;
+pm_allow_tx = 0x40000e2c;
+wdev_is_data_in_rxlist = 0x40000e30;
+ppProcTxCallback = 0x40000e34;
+mac_tx_set_hesig = 0x40000e38;
+ppCalPreFecPaddingFactor = 0x40000e3c;
+mac_tx_set_tb = 0x40000e40;
+mac_tx_set_mplen = 0x40000e44;
+/* Data (.data, .bss, .rodata) */
+our_instances_ptr = 0x4004ffe0;
+pTxRx = 0x4087ff88;
+lmacConfMib_ptr = 0x4087ff84;
+our_wait_eb = 0x4087ff80;
+our_tx_eb = 0x4087ff7c;
+pp_wdev_funcs = 0x4087ff78;
+g_osi_funcs_p = 0x4087ff74;
+wDevCtrl_ptr = 0x4087ff70;
+g_wdev_last_desc_reset_ptr = 0x4004ffdc;
+wDevMacSleep_ptr = 0x4087ff6c;
+g_lmac_cnt_ptr = 0x4087ff68;
+our_controls_ptr = 0x4004ffd8;
+pp_sig_cnt_ptr = 0x4087ff64;
+g_eb_list_desc_ptr = 0x4087ff60;
+s_fragment_ptr = 0x4087ff5c;
+if_ctrl_ptr = 0x4087ff58;
+g_intr_lock_mux = 0x4087ff54;
+g_wifi_global_lock = 0x4087ff50;
+s_wifi_queue = 0x4087ff4c;
+pp_task_hdl = 0x4087ff48;
+s_pp_task_create_sem = 0x4087ff44;
+s_pp_task_del_sem = 0x4087ff40;
+g_wifi_menuconfig_ptr = 0x4087ff3c;
+xphyQueue = 0x4087ff38;
+ap_no_lr_ptr = 0x4087ff34;
+rc11BSchedTbl_ptr = 0x4087ff30;
+rc11NSchedTbl_ptr = 0x4087ff2c;
+rcLoRaSchedTbl_ptr = 0x4087ff28;
+BasicOFDMSched_ptr = 0x4087ff24;
+trc_ctl_ptr = 0x4087ff20;
+g_pm_cnt_ptr = 0x4087ff1c;
+g_pm_ptr = 0x4087ff18;
+g_pm_cfg_ptr = 0x4087ff14;
+g_esp_mesh_quick_funcs_ptr = 0x4087ff10;
+g_txop_queue_status_ptr = 0x4087ff0c;
+g_mac_sleep_en_ptr = 0x4087ff08;
+g_mesh_is_root_ptr = 0x4087ff04;
+g_mesh_topology_ptr = 0x4087ff00;
+g_mesh_init_ps_type_ptr = 0x4087fefc;
+g_mesh_is_started_ptr = 0x4087fef8;
+g_config_func = 0x4087fef4;
+g_net80211_tx_func = 0x4087fef0;
+g_timer_func = 0x4087feec;
+s_michael_mic_failure_cb = 0x4087fee8;
+wifi_sta_rx_probe_req = 0x4087fee4;
+g_tx_done_cb_func = 0x4087fee0;
+g_per_conn_trc = 0x4087fe94;
+s_encap_amsdu_func = 0x4087fe90;
+s_mplen_high_bitmap = 0x4087fce8;
+s_mplen_low_bitmap = 0x4087fcf8;
+rx_beacon_count = 0x4087fe8c;
+rx_beacon_sw_parse = 0x4087fe88;
+rx_beacon_hw_parse = 0x4087fe84;
+rx_beacon_tim_count = 0x4087fe80;
+rx_beacon_tim_udata = 0x4087fe7c;
+rx_beacon_tim_udata_bitmap = 0x4087fe78;
+rx_beacon_tim_bdata = 0x4087fe74;
+rx_beacon_tim_bdata_bitmapctl = 0x4087fe70;
+rx_beacon_tim_bdata_bitmap_trans = 0x4087fe6c;
+rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4087fe68;
+rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4087fe64;
+rx_beacon_dtim_tim = 0x4087fe60;
+rx_beacon_dtim_tim_mcast = 0x4087fe5c;
+amdpu_delay_time_ms = 0x4087fce4;
+ampdu_delay_packet = 0x4087fce0;
+ampdu_delay = 0x4087fe59;
+first_ampdu = 0x4087fe58;
+s_ht_ampdu_density_us = 0x4087fcde;
+s_ht_ampdu_density = 0x4087fcdd;
+s_running_phy_type = 0x4087fcdc;
+complete_ena_tb_seqno = 0x4087fe54;
+complete_ena_tb_final = 0x4087fe50;
+complete_ena_tb_count = 0x4087fe4c;
+s_itwt_state = 0x4087fe48;
+g_dbg_interp_tsf = 0x4087fe44;
+g_dbg_interp_tsf_end = 0x4087fe40;
+g_dbg_closrf_tsf = 0x4087fe3c;
+g_dbg_closrf_idx = 0x4087fe38;
+g_dbg_closrf_blk = 0x4087fe34;
+queue_history = 0x4087fd6c;
+queue_history_idx = 0x4087fd68;
+s_he_min_len_bytes = 0x4087fd2c;
+s_he_dcm_min_len_bytes = 0x4087fd0c;
+s_mplen_vi_bitmap = 0x4087fd08;
+s_mplen_low_bitmap = 0x4087fcf8;
+s_mplen_high_bitmap = 0x4087fce8;