components/os: Fix live lock int bt isr using ocd multicore debug

components/os: Fix live lock in bt isr immediately

components/bt/controller/esp32/hli_vectors.S

@@ -39,6 +39,31 @@ _l4_save_ctx:
     .align      4
 
 xt_highint4:
+
+#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+    /*
+    Here, Timer2 is used to count a little time(50us).
+    The subsequent dram0 write operation is blocked due to live lock, which will
+    cause timer2 to timeout and trigger a l5 interrupt.
+    */
+    rsr.ccount  a0
+    addmi   a0, a0, (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ*50)
+    wsr     a0, CCOMPARE2
+
+    /* Enable Timer 2 interrupt */
+    rsr     a0, INTENABLE
+    extui   a0, a0, 16, 1
+    bnez    a0, 1f
+    movi    a0, 0
+    xsr     a0, INTENABLE     // disable all interrupts
+    addmi   a0, a0, (1<<14)
+    addmi   a0, a0, (1<<14)
+    addmi   a0, a0, (1<<14)
+    addmi   a0, a0, (1<<14)
+    wsr     a0, INTENABLE
+1:
+#endif
+
     movi    a0, _l4_save_ctx
     /* save 4 lower registers */
     s32i    a1, a0, 4
@@ -64,6 +89,14 @@ xt_highint4:
     rsr     a2, EPC1
     s32i    a2, a0, 24
 
+#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+    movi    a0, 0
+    xsr     a0, INTENABLE     // disable all interrupts
+    movi    a2, ~(1<<16)
+    and     a0, a2, a0
+    wsr     a0, INTENABLE
+#endif
+
     /* disable exception mode, window overflow */
     movi    a0, PS_INTLEVEL(5) | PS_EXCM  /*TOCHECK*/
     wsr     a0, PS

components/esp_system/int_wdt.c

@@ -116,6 +116,38 @@ void esp_int_wdt_init(void)
     //Enable WDT
     wdt_hal_enable(&iwdt_context);
     wdt_hal_write_protect_enable(&iwdt_context);
+
+
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
+
+#define APB_DCRSET      (0x200c)
+#define APB_ITCTRL      (0x3f00)
+
+#define ERI_ADDR(APB)   (0x100000 + (APB))
+
+#define _SYM2STR(x)     # x
+#define SYM2STR(x)      _SYM2STR(x)
+    uint32_t eriadrs, scratch = 0, immediate = 0;
+    if (soc_has_cache_lock_bug()) {
+        if (xPortGetCoreID() != CONFIG_BTDM_CTRL_PINNED_TO_CORE) {
+            __asm__ __volatile__ (
+                    /* Enable Xtensa Debug Module Integration Mode */
+                    "movi   %[ERI], " SYM2STR(ERI_ADDR(APB_ITCTRL)) "\n"
+                    "rer    %[REG], %[ERI]\n"
+                    "movi   %[IMM], 1\n"
+                    "or     %[REG], %[IMM], %[REG]\n"
+                    "wer    %[REG], %[ERI]\n"
+                    /* Enable Xtensa Debug Module BreakIn signal */
+                    "movi   %[ERI], " SYM2STR(ERI_ADDR(APB_DCRSET)) "\n"
+                    "rer    %[REG], %[ERI]\n"
+                    "movi   %[IMM], 0x10000\n"
+                    "or     %[REG], %[IMM], %[REG]\n"
+                    "wer    %[REG], %[ERI]\n"
+                    : [ERI] "=r" (eriadrs), [REG] "+r" (scratch), [IMM] "+r" (immediate)
+                );
+        }
+    }
+#endif
 }
 
 void esp_int_wdt_cpu_init(void)

components/esp_system/port/soc/esp32/highint_hdl.S

@@ -158,6 +158,14 @@ xt_highint5:
 
  // ETS_T1_WDT_INUM
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT
+    /* Timer 2 interrupt */
+    rsr     a0, INTENABLE
+    extui   a0, a0, 16, 1
+    beqz    a0, 1f
+    rsr     a0, INTERRUPT
+    extui   a0, a0, 16, 1
+    bnez    a0, .handle_multicore_debug_int
+1:
     get_int_status_tg1wdt a0
     beqz    a0, 1f
 
@@ -254,6 +262,50 @@ xt_highint5:
 
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT
+#define APB_ITCTRL              (0x3f00)
+#define APB_DCRSET              (0x200c)
+
+#define ERI_ADDR(APB)           (0x100000 + (APB))
+
+    .align      4
+.handle_multicore_debug_int:
+
+    wsr     a2, depc                        /* temp storage */
+
+    rsr.ccount  a2
+    addmi   a2, a2, (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ*50)
+    wsr     a2, CCOMPARE2
+
+    /* Enable Integration Mode */
+    movi    a2, ERI_ADDR(APB_ITCTRL)
+    rer     a0, a2
+    addi    a0, a0, 1
+    wer     a0, a2
+
+    /* Enable and emit BreakOut signal */
+    movi    a2, ERI_ADDR(APB_DCRSET)
+    rer     a0, a2
+    movi    a2, 0x1020000
+    or      a0, a2, a0
+    movi    a2, ERI_ADDR(APB_DCRSET)
+    wer     a0, a2
+
+    .rept   4
+    nop
+    .endr
+
+    /* Enable Normally Mode */
+    movi    a2, ERI_ADDR(APB_ITCTRL)
+    rer     a0, a2
+    movi    a2, ~0x1
+    and     a0, a2, a0
+    movi    a2, ERI_ADDR(APB_ITCTRL)
+    wer     a0, a2
+
+    rsr     a2, depc
+
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
 
 /*
 --------------------------------------------------------------------------------

components/freertos/port/xtensa/xtensa_vector_defaults.S

@@ -32,6 +32,21 @@ The default behaviour is to just exit the interrupt or call the panic handler on
     .align      4
 
 _xt_debugexception:
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
+#define XT_DEBUGCAUSE_DI        (5)
+    getcoreid   a0
+#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM)
+    beqz    a0, 1f
+#else
+    bnez    a0, 1f
+#endif
+
+    rsr     a0, DEBUGCAUSE
+    extui   a0, a0, XT_DEBUGCAUSE_DI, 1
+    bnez    a0, _xt_debug_di_exc
+1:
+#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
+
     movi    a0,PANIC_RSN_DEBUGEXCEPTION
     wsr     a0,EXCCAUSE
     /* _xt_panic assumes a level 1 exception. As we're
@@ -44,6 +59,55 @@ _xt_debugexception:
     call0   _xt_panic                       /* does not return */
     rfi     XCHAL_DEBUGLEVEL
 
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
+    .align  4
+_xt_debug_di_exc:
+
+/*  After testing,
+    In 80 MHz, it will task 5us to loop 45 times;
+    In 160 MHz, it will task 5us to loop 90 times;
+    In 240 MHz, it will task 5us to loop 135 times;*/
+#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
+
+# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
+    movi    a0, 54
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 108
+# else
+    movi    a0, 135
+# endif
+
+#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
+
+# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 135
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 189
+# else
+    movi    a0, 243
+# endif
+
+#else
+    movi    a0, 243
+#endif
+
+1:  addi    a0, a0, -1
+    .rept   4
+    nop
+    .endr
+    bnez    a0, 1b
+
+    rsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL
+    rfi     XCHAL_DEBUGLEVEL
+#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BT_ENABLED)
 #endif /* Debug exception */