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Driver(Touch sensor): fix the touch sensor wait cycle after wakeup from sleep

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This commit is contained in:
fuzhibo
2021-04-13 10:48:59 +08:00
committed by Michael (XIAO Xufeng)
parent 1b75fb5622
commit 8ab23d4395
3 changed files with 20 additions and 23 deletions
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2
components/esp_hw_support/port/esp32s2/rtc_init.c
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@ -66,6 +66,8 @@ void rtc_init(rtc_config_t cfg)
/* Reset RTC bias to default value (needed if waking up from deep sleep) */ /* Reset RTC bias to default value (needed if waking up from deep sleep) */
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
/* Recover default wait cycle for touch or COCPU after wakeup from deep sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
if (cfg.clkctl_init) { if (cfg.clkctl_init) {
//clear CMMU clock force on //clear CMMU clock force on

38
components/esp_hw_support/port/esp32s2/rtc_sleep.c
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@ -138,6 +138,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
/* Set wait cycle for touch or COCPU after deep sleep and light sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP);
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
} }
@ -157,8 +159,6 @@ void rtc_sleep_set_wakeup_time(uint64_t t)
/* Read back 'reject' status when waking from light or deep sleep */ /* Read back 'reject' status when waking from light or deep sleep */
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu); static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
static const unsigned DEEP_SLEEP_TOUCH_WAIT_CYCLE = 0xFF;
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu) uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
{ {
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
@ -170,9 +170,6 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
/* Set wait cycle for touch or COCPU after deep sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, DEEP_SLEEP_TOUCH_WAIT_CYCLE);
/* Start entry into sleep mode */ /* Start entry into sleep mode */
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
@ -233,23 +230,17 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
"s32i a2, %4, 0\n" "s32i a2, %4, 0\n"
"memw\n" "memw\n"
/* Set wait cycle for touch or COCPU after deep sleep (can be moved to C code part?) */
"l32i a2, %5, 0\n"
"and a2, a2, %6\n"
"or a2, a2, %7\n"
"s32i a2, %5, 0\n"
/* Set register bit to go into deep sleep */ /* Set register bit to go into deep sleep */
"l32i a2, %8, 0\n" "l32i a2, %5, 0\n"
"or a2, a2, %9\n" "or a2, a2, %6\n"
"s32i a2, %8, 0\n" "s32i a2, %5, 0\n"
"memw\n" "memw\n"
/* Wait for sleep reject interrupt (never finishes if successful) */ /* Wait for sleep reject interrupt (never finishes if successful) */
".Lwaitsleep:" ".Lwaitsleep:"
"memw\n" "memw\n"
"l32i a2, %10, 0\n" "l32i a2, %7, 0\n"
"and a2, a2, %11\n" "and a2, a2, %8\n"
"beqz a2, .Lwaitsleep\n" "beqz a2, .Lwaitsleep\n"
: :
@ -260,13 +251,10 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
"r" (DPORT_RTC_MEM_CRC_START), // %2 "r" (DPORT_RTC_MEM_CRC_START), // %2
"r" (DPORT_RTC_FASTMEM_CRC_REG), // %3 "r" (DPORT_RTC_FASTMEM_CRC_REG), // %3
"r" (RTC_MEMORY_CRC_REG), // %4 "r" (RTC_MEMORY_CRC_REG), // %4
"r" (RTC_CNTL_TIMER2_REG), // %5 "r" (RTC_CNTL_STATE0_REG), // %5
"r" (~RTC_CNTL_ULPCP_TOUCH_START_WAIT_M), // %6 "r" (RTC_CNTL_SLEEP_EN), // %6
"r" (DEEP_SLEEP_TOUCH_WAIT_CYCLE << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S), // %7 "r" (RTC_CNTL_INT_RAW_REG), // %7
"r" (RTC_CNTL_STATE0_REG), // %8 "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
"r" (RTC_CNTL_SLEEP_EN), // %9
"r" (RTC_CNTL_INT_RAW_REG), // %10
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %11
: "a2" // working register : "a2" // working register
); );
@ -285,5 +273,9 @@ static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0); rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
rtc_sleep_pd(pd_cfg); rtc_sleep_pd(pd_cfg);
} }
/* Recover default wait cycle for touch or COCPU after wakeup. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
return reject; return reject;
} }

3
components/soc/esp32s2/include/soc/rtc.h
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@ -113,6 +113,9 @@ extern "C" {
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
#define RTC_CNTL_SCK_DCAP_DEFAULT 255 #define RTC_CNTL_SCK_DCAP_DEFAULT 255
#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP (0xFF)
#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT (0x10)
/* /*
set sleep_init default param set sleep_init default param
*/ */