fix(rgb_lcd): relax the check for the data line GPIO

There are a bunch of cases you might want some pins not exposed.

Eg.

  * Reading say 8 bit data and outputting the top 5 bits, discarding the rest by not mapping those data pins to output pins

 * Not using hsync/vsync because sync data is embedded within the data bits for more timing flexibility (eg. interlacing).

 * Using the LCD module as a high speed parallel data output bus, with no need for sync/control pins.

Removing this validation makes these cases work.

Merges https://github.com/espressif/esp-idf/pull/13103

components/hal/esp32s3/include/hal/lcd_ll.h

@@ -27,6 +27,7 @@ extern "C" {
 #define LCD_LL_CLK_FRAC_DIV_N_MAX  256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width
 #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64  // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width
 #define LCD_LL_PCLK_DIV_MAX        64  // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width
+#define LCD_LL_FIFO_DEPTH          16  // Async FIFO depth
 
 #define LCD_LL_COLOR_RANGE_TO_REG(range) (uint8_t[]){0,1}[(range)]
 #define LCD_LL_CONV_STD_TO_REG(std)      (uint8_t[]){0,1}[(std)]