From 8baffe22cbeb05daa8bc8ff4af62da5fcbbba4a1 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Mon, 24 Feb 2025 21:27:41 +0800 Subject: [PATCH] fix(uart): LP UART does not have the pre-divider for its clock source Closes https://github.com/espressif/esp-idf/issues/15427 --- .../esp_driver_uart/include/driver/uart.h | 4 +- components/esp_driver_uart/src/uart.c | 14 ++-- components/hal/esp32/include/hal/uart_ll.h | 24 ++++--- components/hal/esp32c2/include/hal/uart_ll.h | 19 ++++-- components/hal/esp32c3/include/hal/uart_ll.h | 19 ++++-- components/hal/esp32c5/include/hal/uart_ll.h | 65 ++++++++++--------- components/hal/esp32c6/include/hal/uart_ll.h | 65 ++++++++++--------- components/hal/esp32c61/include/hal/uart_ll.h | 19 ++++-- components/hal/esp32h2/include/hal/uart_ll.h | 19 ++++-- components/hal/esp32p4/include/hal/uart_ll.h | 60 ++++++++++------- components/hal/esp32s2/include/hal/uart_ll.h | 24 ++++--- components/hal/esp32s3/include/hal/uart_ll.h | 19 ++++-- components/hal/include/hal/uart_hal.h | 10 +-- .../esp32c5/mp/include/soc/lp_uart_struct.h | 17 +---- .../soc/esp32c5/mp/include/soc/uart_struct.h | 29 ++------- .../soc/esp32c6/include/soc/lp_uart_reg.h | 50 ++------------ .../soc/esp32c6/include/soc/lp_uart_struct.h | 35 ++-------- components/soc/esp32c6/include/soc/uart_reg.h | 44 +++++++++++-- .../soc/esp32c6/include/soc/uart_struct.h | 37 ++--------- .../soc/esp32p4/include/soc/uart_struct.h | 27 ++------ components/ulp/lp_core/lp_core_uart.c | 7 +- 21 files changed, 289 insertions(+), 318 deletions(-) diff --git a/components/esp_driver_uart/include/driver/uart.h b/components/esp_driver_uart/include/driver/uart.h index ff3138ca7c..d574b82efc 100644 --- a/components/esp_driver_uart/include/driver/uart.h +++ b/components/esp_driver_uart/include/driver/uart.h @@ -231,7 +231,7 @@ esp_err_t uart_get_sclk_freq(uart_sclk_t sclk, uint32_t* out_freq_hz); * @param baudrate UART baud rate. * * @return - * - ESP_FAIL Parameter error + * - ESP_FAIL Parameter error, such as baud rate unachievable * - ESP_OK Success */ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baudrate); @@ -461,7 +461,7 @@ esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num); * * @return * - ESP_OK Success - * - ESP_FAIL Parameter error + * - ESP_FAIL Parameter error, such as baud rate unachievable */ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config); diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index 6e0506a419..0656e8a0ca 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -346,20 +346,20 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate) uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk); ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk"); + bool success = false; UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - if (uart_num < SOC_UART_HP_NUM) { HP_UART_SRC_CLK_ATOMIC() { - uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq); + success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq); } } #if (SOC_UART_LP_NUM >= 1) else { - lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq); + success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq); } #endif - UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); + ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable"); return ESP_OK; } @@ -897,12 +897,13 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf uint32_t sclk_freq; ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk"); + bool success = false; UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_init(&(uart_context[uart_num].hal), uart_num); if (uart_num < SOC_UART_HP_NUM) { HP_UART_SRC_CLK_ATOMIC() { uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel); - uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); + success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); } } #if (SOC_UART_LP_NUM >= 1) @@ -910,7 +911,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf LP_UART_SRC_CLK_ATOMIC() { lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel); } - lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq); + success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq); } #endif uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity); @@ -921,6 +922,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); uart_hal_txfifo_rst(&(uart_context[uart_num].hal)); + ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable"); return ESP_OK; } diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h index 02134517e7..2c6500bdb3 100644 --- a/components/hal/esp32/include/hal/uart_ll.h +++ b/components/hal/esp32/include/hal/uart_ll.h @@ -183,17 +183,23 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud-rate to be set. When the source clock is APB, the max baud-rate is `UART_LL_BITRATE_MAX` * @param sclk_freq Frequency of the clock source of UART, in Hz. - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { - uint32_t clk_div; - - clk_div = ((sclk_freq) << 4) / baud; - // The baud-rate configuration register is divided into - // an integer part and a fractional part. - hw->clk_div.div_int = clk_div >> 4; - hw->clk_div.div_frag = clk_div & 0xf; + if (baud == 0) { + return false; + } + uint32_t clk_div = ((sclk_freq) << 4) / baud; + // The baud-rate configuration register is divided into an integer part and a fractional part. + uint32_t clkdiv_int = clk_div >> 4; + if (clkdiv_int > UART_CLKDIV_V) { + return false; // unachievable baud-rate + } + uint32_t clkdiv_frag = clk_div & 0xf; + hw->clk_div.div_int = clkdiv_int; + hw->clk_div.div_frag = clkdiv_frag; + return true; } /** diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index 7c5e3d12ed..52f9d8f011 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -208,23 +208,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP - if (sclk_div == 0) abort(); + if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clk_div.div_int = clk_div >> 4; hw->clk_div.div_frag = clk_div & 0xf; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP + return true; } /** diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index f9f00ad85a..8818397460 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -212,23 +212,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP - if (sclk_div == 0) abort(); + if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clk_div.div_int = clk_div >> 4; hw->clk_div.div_frag = clk_div & 0xf; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP + return true; } /** diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h index 0d20c2335a..3f2afb7f85 100644 --- a/components/hal/esp32c5/include/hal/uart_ll.h +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -152,23 +152,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_ * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - - if (sclk_div == 0) abort(); - - uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. - hw->clkdiv_sync.clkdiv_int = clk_div >> 4; - hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); + if (baud == 0) { + return false; + } + // No pre-divider for LP UART clock source on the target + uint32_t clk_div = (sclk_freq << 4) / baud; + // The baud rate configuration register is divided into an integer part and a fractional part. + uint32_t clkdiv_int = clk_div >> 4; + if (clkdiv_int > UART_CLKDIV_V) { + return false; // unachievable baud-rate + } + uint32_t clkdiv_frag = clk_div & 0xf; + hw->clkdiv_sync.clkdiv_int = clkdiv_int; + hw->clkdiv_sync.clkdiv_frag = clkdiv_frag; uart_ll_update(hw); + return true; } /** @@ -394,28 +396,33 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + if ((hw) == &LP_UART) { + abort(); // need to call lp_uart_ll_set_baudrate() + } - if (sclk_div == 0) abort(); +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits + uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP + + if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clkdiv_sync.clkdiv_int = clk_div >> 4; hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - if ((hw) == &LP_UART) { - abort(); - } else { - UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); - } -#undef DIV_UP + UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); uart_ll_update(hw); + return true; } /** @@ -432,7 +439,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr div_reg.val = hw->clkdiv_sync.val; int sclk_div; if ((hw) == &LP_UART) { - sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; + sclk_div = 1; // no pre-divider for LP UART clock source on the target } else { sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; } diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h index c6518beaa4..2b229d7c7d 100644 --- a/components/hal/esp32c6/include/hal/uart_ll.h +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -155,23 +155,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_ * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - - if (sclk_div == 0) abort(); - - uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. - hw->clkdiv_sync.clkdiv_int = clk_div >> 4; - hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); + if (baud == 0) { + return false; + } + // No pre-divider for LP UART clock source on the target + uint32_t clk_div = (sclk_freq << 4) / baud; + // The baud rate configuration register is divided into an integer part and a fractional part. + uint32_t clkdiv_int = clk_div >> 4; + if (clkdiv_int > UART_CLKDIV_V) { + return false; // unachievable baud-rate + } + uint32_t clkdiv_frag = clk_div & 0xf; + hw->clkdiv_sync.clkdiv_int = clkdiv_int; + hw->clkdiv_sync.clkdiv_frag = clkdiv_frag; uart_ll_update(hw); + return true; } /** @@ -378,28 +380,33 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); + if ((hw) == &LP_UART) { + abort(); // need to call lp_uart_ll_set_baudrate() + } - if (sclk_div == 0) abort(); +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits + uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP + + if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clkdiv_sync.clkdiv_int = clk_div >> 4; hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - if ((hw) == &LP_UART) { - abort(); - } else { - UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); - } -#undef DIV_UP + UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); uart_ll_update(hw); + return true; } /** @@ -416,7 +423,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr div_reg.val = hw->clkdiv_sync.val; int sclk_div; if ((hw) == &LP_UART) { - sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; + sclk_div = 1; // no pre-divider for LP UART clock source on the target } else { sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1; } diff --git a/components/hal/esp32c61/include/hal/uart_ll.h b/components/hal/esp32c61/include/hal/uart_ll.h index 6e5a0a208f..ecb6ac4b2c 100644 --- a/components/hal/esp32c61/include/hal/uart_ll.h +++ b/components/hal/esp32c61/include/hal/uart_ll.h @@ -238,24 +238,29 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP - if (sclk_div == 0) abort(); + if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clkdiv_sync.clkdiv_int = clk_div >> 4; hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP uart_ll_update(hw); + return true; } /** diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index 878bdf0085..4a77627d83 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -240,24 +240,29 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP - if (sclk_div == 0) abort(); + if (sclk_div == 0 || sclk_div > (PCR_UART0_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clkdiv_sync.clkdiv_int = clk_div >> 4; hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP uart_ll_update(hw); + return true; } /** diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 8b5a143311..6138f27c18 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -17,6 +17,7 @@ #include "soc/uart_reg.h" #include "soc/uart_struct.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/hp_sys_clkrst_reg.h" #include "soc/lp_uart_reg.h" #include "soc/lp_clkrst_struct.h" #include "soc/lpperi_struct.h" @@ -148,24 +149,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_ * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { -#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits - uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - if (sclk_div == 0) abort(); - - uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. - hw->clkdiv_sync.clkdiv = clk_div >> 4; - hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; - //needs force u32 write - HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP + if (baud == 0) { + return false; + } + // No pre-divider for LP UART clock source on the target + uint32_t clk_div = (sclk_freq << 4) / baud; + // The baud rate configuration register is divided into an integer part and a fractional part. + uint32_t clkdiv_int = clk_div >> 4; + if (clkdiv_int > UART_CLKDIV_V) { + return false; // unachievable baud-rate + } + uint32_t clkdiv_frag = clk_div & 0xf; + hw->clkdiv_sync.clkdiv = clkdiv_int; + hw->clkdiv_sync.clkdiv_frag = clkdiv_frag; uart_ll_update(hw); + return true; } /** @@ -474,18 +476,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { + if ((hw) == &LP_UART) { + abort(); // need to call lp_uart_ll_set_baudrate() + } + #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); - if (sclk_div == 0) abort(); +#undef DIV_UP + + if (sclk_div == 0 || sclk_div > (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clkdiv_sync.clkdiv = clk_div >> 4; hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf; //needs force u32 write @@ -502,12 +514,12 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3 } else { abort(); } -#undef DIV_UP uart_ll_update(hw); + return true; } #if !BOOTLOADER_BUILD //HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way -#define uart_ll_set_baudrate(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_baudrate(__VA_ARGS__) +#define uart_ll_set_baudrate(...) uart_ll_set_baudrate(__VA_ARGS__); (void)__DECLARE_RCC_ATOMIC_ENV #endif /** @@ -534,7 +546,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr } else if ((hw) == &UART4) { sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num) + 1; } else if ((hw) == &LP_UART) { - sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1; + sclk_div = 1; // no pre-divider for LP UART clock source on the target } return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * sclk_div); } diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h index 4dfbeb9543..719c1173ad 100644 --- a/components/hal/esp32s2/include/hal/uart_ll.h +++ b/components/hal/esp32s2/include/hal/uart_ll.h @@ -172,17 +172,23 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. When the source clock is APB, the max baud rate is `UART_LL_BITRATE_MAX` * @param sclk_freq Frequency of the clock source of UART, in Hz. - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { - uint32_t clk_div; - - clk_div = ((sclk_freq) << 4) / baud; - // The baud rate configuration register is divided into - // an integer part and a fractional part. - hw->clk_div.div_int = clk_div >> 4; - hw->clk_div.div_frag = clk_div & 0xf; + if (baud == 0) { + return false; + } + uint32_t clk_div = ((sclk_freq) << 4) / baud; + // The baud-rate configuration register is divided into an integer part and a fractional part. + uint32_t clkdiv_int = clk_div >> 4; + if (clkdiv_int > UART_CLKDIV_V) { + return false; // unachievable baud-rate + } + uint32_t clkdiv_frag = clk_div & 0xf; + hw->clk_div.div_int = clkdiv_int; + hw->clk_div.div_frag = clkdiv_frag; + return true; } /** diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 3dd538ec50..00c04fed0b 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -195,23 +195,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source * @param baud The baud rate to be set. * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ -FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) +FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) { #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) - const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + if (baud == 0) { + return false; + } + const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud); +#undef DIV_UP - if (sclk_div == 0) abort(); + if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) { + return false; // unachievable baud-rate + } uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); - // The baud rate configuration register is divided into - // an integer part and a fractional part. + // The baud rate configuration register is divided into an integer part and a fractional part. hw->clkdiv.clkdiv = clk_div >> 4; hw->clkdiv.clkdiv_frag = clk_div & 0xf; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); -#undef DIV_UP + return true; } /** diff --git a/components/hal/include/hal/uart_hal.h b/components/hal/include/hal/uart_hal.h index 1ea84a7888..6d628f3481 100644 --- a/components/hal/include/hal/uart_hal.h +++ b/components/hal/include/hal/uart_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -36,7 +36,7 @@ typedef struct { * @param baud_rate The baud-rate to be set * @param sclk_freq Frequency of the clock source of UART, in Hz. * - * @return None + * @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved */ #define uart_hal_set_baudrate(hal, baud_rate, sclk_freq) uart_ll_set_baudrate((hal)->dev, baud_rate, sclk_freq) @@ -202,7 +202,7 @@ void uart_hal_init(uart_hal_context_t *hal, uart_port_t uart_num); * @brief Get the UART source clock type * * @param hal Context of the HAL layer - * @param sclk The poiter to accept the UART source clock type + * @param sclk The pointer to accept the UART source clock type * * @return None */ @@ -357,7 +357,7 @@ void uart_hal_set_mode(uart_hal_context_t *hal, uart_mode_t mode); * @brief Configure the UART hardware to inverse the signals * * @param hal Context of the HAL layer - * @param inv_mask The sigal mask needs to be inversed. Use the ORred mask of type `uart_signal_inv_t` + * @param inv_mask The signal mask needs to be inversed. Use the ORred mask of type `uart_signal_inv_t` * * @return None */ @@ -437,7 +437,7 @@ bool uart_hal_is_hw_rts_en(uart_hal_context_t *hal); * @brief Configure TX signal loop back to RX module, just for the testing purposes * * @param hal Context of the HAL layer - * @param loop_back_en Set ture to enable the loop back function, else set it false. + * @param loop_back_en Set true to enable the loop back function, else set it false. * * @return None */ diff --git a/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h b/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h index 316b3bc1b3..ad53ed0d9d 100644 --- a/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h +++ b/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h @@ -844,22 +844,7 @@ typedef union { */ typedef union { struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - * Only available to LP UART instance - */ - uint32_t sclk_div_b:6; - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - * Only available to LP UART instance - */ - uint32_t sclk_div_a:6; - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - * Only available to LP UART instance - */ - uint32_t sclk_div_num:8; - uint32_t reserved_20:4; + uint32_t reserved_0:24; /** tx_sclk_en : R/W; bitpos: [24]; default: 1; * Configures whether or not to enable LP UART TX clock.\\ * 0: Disable\\ diff --git a/components/soc/esp32c5/mp/include/soc/uart_struct.h b/components/soc/esp32c5/mp/include/soc/uart_struct.h index 1cc6ed2d32..9848e5a9fa 100644 --- a/components/soc/esp32c5/mp/include/soc/uart_struct.h +++ b/components/soc/esp32c5/mp/include/soc/uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -946,22 +946,7 @@ typedef union { */ typedef union { struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor.' - * Only available to LP UART instance - */ - uint32_t sclk_div_b:6; - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - * Only available to LP UART instance - */ - uint32_t sclk_div_a:6; - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - * Only available to LP UART instance - */ - uint32_t sclk_div_num:8; - uint32_t reserved_20:4; + uint32_t reserved_0:24; /** tx_sclk_en : R/W; bitpos: [24]; default: 1; * Configures whether or not to enable UART TX clock.\\ * 0: Disable\\ @@ -1338,11 +1323,11 @@ typedef struct { volatile uart_mem_tx_status_reg_t mem_tx_status; volatile uart_mem_rx_status_reg_t mem_rx_status; volatile uart_fsm_status_reg_t fsm_status; - volatile uart_pospulse_reg_t pospulse; - volatile uart_negpulse_reg_t negpulse; - volatile uart_lowpulse_reg_t lowpulse; - volatile uart_highpulse_reg_t highpulse; - volatile uart_rxd_cnt_reg_t rxd_cnt; + volatile uart_pospulse_reg_t pospulse; /* LP_UART instance has this register reserved */ + volatile uart_negpulse_reg_t negpulse; /* LP_UART instance has this register reserved */ + volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */ + volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */ + volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */ volatile uart_clk_conf_reg_t clk_conf; volatile uart_date_reg_t date; volatile uart_afifo_status_reg_t afifo_status; diff --git a/components/soc/esp32c6/include/soc/lp_uart_reg.h b/components/soc/esp32c6/include/soc/lp_uart_reg.h index b67fa1b59e..d01c6d4cc0 100644 --- a/components/soc/esp32c6/include/soc/lp_uart_reg.h +++ b/components/soc/esp32c6/include/soc/lp_uart_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -100,7 +100,7 @@ extern "C" { #define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 /** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define LP_UART_SW_XON_INT_RAW (BIT(9)) @@ -671,7 +671,7 @@ extern "C" { #define LP_UART_STOP_BIT_NUM_V 0x00000003U #define LP_UART_STOP_BIT_NUM_S 4 /** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define LP_UART_TXD_BRK (BIT(6)) @@ -1151,7 +1151,7 @@ extern "C" { */ #define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) /** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define LP_UART_RX_TOUT_EN (BIT(0)) #define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) @@ -1235,48 +1235,6 @@ extern "C" { * UART core clock configuration */ #define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88) -/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ -#define LP_UART_SCLK_DIV_B 0x0000003FU -#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S) -#define LP_UART_SCLK_DIV_B_V 0x0000003FU -#define LP_UART_SCLK_DIV_B_S 0 -/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ -#define LP_UART_SCLK_DIV_A 0x0000003FU -#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S) -#define LP_UART_SCLK_DIV_A_V 0x0000003FU -#define LP_UART_SCLK_DIV_A_S 6 -/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ -#define LP_UART_SCLK_DIV_NUM 0x000000FFU -#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S) -#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU -#define LP_UART_SCLK_DIV_NUM_S 12 -/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ -#define LP_UART_SCLK_SEL 0x00000003U -#define LP_UART_SCLK_SEL_M (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S) -#define LP_UART_SCLK_SEL_V 0x00000003U -#define LP_UART_SCLK_SEL_S 20 -/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ -#define LP_UART_SCLK_EN (BIT(22)) -#define LP_UART_SCLK_EN_M (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S) -#define LP_UART_SCLK_EN_V 0x00000001U -#define LP_UART_SCLK_EN_S 22 -/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ -#define LP_UART_RST_CORE (BIT(23)) -#define LP_UART_RST_CORE_M (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S) -#define LP_UART_RST_CORE_V 0x00000001U -#define LP_UART_RST_CORE_S 23 /** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ diff --git a/components/soc/esp32c6/include/soc/lp_uart_struct.h b/components/soc/esp32c6/include/soc/lp_uart_struct.h index 122c7d920a..f761e854e0 100644 --- a/components/soc/esp32c6/include/soc/lp_uart_struct.h +++ b/components/soc/esp32c6/include/soc/lp_uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout:1; /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon:1; @@ -466,7 +466,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -791,30 +791,7 @@ typedef union { */ typedef union { struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ - uint32_t sclk_div_b:6; - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ - uint32_t sclk_div_a:6; - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ - uint32_t sclk_div_num:8; - /** sclk_sel : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ - uint32_t sclk_sel:2; - /** sclk_en : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ - uint32_t sclk_en:1; - /** rst_core : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ - uint32_t rst_core:1; + uint32_t reserved_20:24; /** tx_sclk_en : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ @@ -1115,7 +1092,7 @@ typedef struct lp_uart_dev_t { volatile lp_uart_id_reg_t id; } lp_uart_dev_t; -// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h +// We map the LP_UART instance to the uart_dev_t struct for convenience of using the same HAL/LL. See soc/uart_struct.h // extern lp_uart_dev_t LP_UART; #ifndef __cplusplus diff --git a/components/soc/esp32c6/include/soc/uart_reg.h b/components/soc/esp32c6/include/soc/uart_reg.h index abac8d92b1..0d82c1fef3 100644 --- a/components/soc/esp32c6/include/soc/uart_reg.h +++ b/components/soc/esp32c6/include/soc/uart_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -100,7 +100,7 @@ extern "C" { #define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U #define UART_RXFIFO_TOUT_INT_RAW_S 8 /** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ #define UART_SW_XON_INT_RAW (BIT(9)) @@ -760,7 +760,7 @@ extern "C" { #define UART_STOP_BIT_NUM_V 0x00000003U #define UART_STOP_BIT_NUM_S 4 /** UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ #define UART_TXD_BRK (BIT(6)) @@ -1326,7 +1326,7 @@ extern "C" { */ #define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ #define UART_RX_TOUT_EN (BIT(0)) #define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) @@ -1450,7 +1450,7 @@ extern "C" { */ #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ #define UART_HIGHPULSE_MIN_CNT 0x00000FFFU @@ -1471,6 +1471,40 @@ extern "C" { #define UART_RXD_EDGE_CNT_V 0x000003FFU #define UART_RXD_EDGE_CNT_S 0 + +/** UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) +#define UART_TX_SCLK_EN_V 0x00000001U +#define UART_TX_SCLK_EN_S 24 +/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) +#define UART_RX_SCLK_EN_V 0x00000001U +#define UART_RX_SCLK_EN_S 25 +/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) +#define UART_TX_RST_CORE_V 0x00000001U +#define UART_TX_RST_CORE_S 26 +/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) +#define UART_RX_RST_CORE_V 0x00000001U +#define UART_RX_RST_CORE_S 27 + /** UART_DATE_REG register * UART Version register */ diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/include/soc/uart_struct.h index 674af37135..0be18356fe 100644 --- a/components/soc/esp32c6/include/soc/uart_struct.h +++ b/components/soc/esp32c6/include/soc/uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout:1; /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon:1; @@ -515,7 +515,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -880,30 +880,7 @@ typedef union { */ typedef union { struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ - uint32_t sclk_div_b:6; - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ - uint32_t sclk_div_a:6; - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ - uint32_t sclk_div_num:8; - /** sclk_sel : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ - uint32_t sclk_sel:2; - /** sclk_en : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ - uint32_t sclk_en:1; - /** rst_core : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ - uint32_t rst_core:1; + uint32_t reserved_0:24; /** tx_sclk_en : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ @@ -1170,7 +1147,7 @@ typedef union { typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ uint32_t highpulse_min_cnt:12; @@ -1273,7 +1250,7 @@ typedef struct uart_dev_s { volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */ volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */ volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */ - volatile uart_clk_conf_reg_t clk_conf; /* UART0/1 instance have this register reserved, configure in corresponding PCR registers */ + volatile uart_clk_conf_reg_t clk_conf; volatile uart_date_reg_t date; volatile uart_afifo_status_reg_t afifo_status; uint32_t reserved_094; diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/include/soc/uart_struct.h index b23e6db930..afc9331539 100644 --- a/components/soc/esp32p4/include/soc/uart_struct.h +++ b/components/soc/esp32p4/include/soc/uart_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,7 +49,7 @@ typedef union { typedef union { struct { /** rx_tout_en : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. + * This is the enable bit for uart receiver's timeout function. */ uint32_t rx_tout_en:1; /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; @@ -120,7 +120,7 @@ typedef union { */ uint32_t rxfifo_tout_int_raw:1; /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon char when + * This interrupt raw bit turns to high level when receiver receives Xon char when * uart_sw_flow_con_en is set to 1. */ uint32_t sw_xon_int_raw:1; @@ -515,7 +515,7 @@ typedef union { */ uint32_t stop_bit_num:2; /** txd_brk : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of sending data + * Set this bit to enable transmitter to send NULL when the process of sending data * is done. */ uint32_t txd_brk:1; @@ -880,20 +880,7 @@ typedef union { */ typedef union { struct { - /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ - uint32_t sclk_div_b:6; //HP UART's sclk_div_b is in hp_sys_clkrst_struct.h - /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ - uint32_t sclk_div_a:6; //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h - /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - * It is only used by LP UART - */ - uint32_t sclk_div_num:8; //HP UART's sclk_div_num is in hp_sys_clkrst_struct.h - uint32_t reserved_20:4; + uint32_t reserved_0:24; /** tx_sclk_en : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ @@ -1160,7 +1147,7 @@ typedef union { typedef union { struct { /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high level + * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. */ uint32_t highpulse_min_cnt:12; @@ -1263,7 +1250,7 @@ typedef struct uart_dev_t{ volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */ volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */ volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */ - volatile uart_clk_conf_reg_t clk_conf; /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */ + volatile uart_clk_conf_reg_t clk_conf; volatile uart_date_reg_t date; volatile uart_afifo_status_reg_t afifo_status; uint32_t reserved_094; diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c index 94f751b38c..7a9d3ade87 100644 --- a/components/ulp/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core_uart.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -61,7 +61,10 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg) uart_hal_init(&hal, LP_UART_PORT_NUM); /* Override protocol parameters from the configuration */ - lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq); + if (!lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq)) { + /* Unachievable baud rate */ + return ESP_FAIL; + } uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity); uart_hal_set_data_bit_num(&hal, cfg->uart_proto_cfg.data_bits); uart_hal_set_stop_bits(&hal, cfg->uart_proto_cfg.stop_bits);