espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-04 21:24:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

feat(esp_hw_support): update pmu sleep parameters and register header and structure file for esp32c61

Browse Source
This commit is contained in:
wuzhenghui
2025-05-28 15:27:20 +08:00
committed by yinqingzhao
parent 0a25960783
commit 8bd81b2bfd
3 changed files with 69 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

97
components/esp_hw_support/port/esp32c61/pmu_param.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -202,66 +202,69 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
} }
#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \ #define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
.bias = { \ .bias = { \
.xpd_bias = 1, \ .xpd_bias = 1, \
.dbg_atten = 0x0, \ .dbg_atten = 0x0, \
.pd_cur = 0, \ .pd_cur = 0, \
.bias_sleep = 0 \ .bias_sleep = 0 \
}, \ }, \
.regulator0 = { \ .regulator0 = { \
.lp_dbias_vol = 0xd, \ .slp_connect_en_active = 1, \
.hp_dbias_vol = 0x1c,\ .lp_dbias_vol = 0xd, \
.dbias_sel = 1, \ .hp_dbias_vol = 0x1c,\
.dbias_init = 1, \ .dbias_sel = 1, \
.slp_mem_xpd = 0, \ .dbias_init_active = 1, \
.slp_logic_xpd = 0, \ .slp_mem_xpd = 0, \
.xpd = 1, \ .slp_logic_xpd = 0, \
.slp_mem_dbias = 0, \ .xpd = 1, \
.slp_logic_dbias = 0, \ .slp_mem_dbias = 0, \
.dbias = HP_CALI_DBIAS_DEFAULT \ .slp_logic_dbias = 0, \
.dbias = HP_CALI_DBIAS_DEFAULT \
}, \ }, \
.regulator1 = { \ .regulator1 = { \
.drv_b = 0x0 \ .drv_b = 0x0 \
} \ } \
} }
#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \ #define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \
.bias = { \ .bias = { \
.xpd_bias = 0, \ .xpd_bias = 0, \
.dbg_atten = 0x0, \ .dbg_atten = 0x0,\
.pd_cur = 0, \ .pd_cur = 0, \
.bias_sleep = 0 \ .bias_sleep = 0 \
}, \ }, \
.regulator0 = { \ .regulator0 = { \
.slp_mem_xpd = 0, \ .slp_connect_en_modem = 1, \
.slp_logic_xpd = 0, \ .slp_mem_xpd = 0, \
.xpd = 1, \ .slp_logic_xpd = 0, \
.slp_mem_dbias = 0, \ .xpd = 1, \
.slp_logic_dbias = 0, \ .slp_mem_dbias = 0, \
.dbias = HP_CALI_DBIAS_DEFAULT \ .slp_logic_dbias = 0, \
.dbias = HP_CALI_DBIAS_DEFAULT \
}, \ }, \
.regulator1 = { \ .regulator1 = { \
.drv_b = 0x0 \ .drv_b = 0x0 \
} \ } \
} }
#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ #define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
.bias = { \ .bias = { \
.xpd_bias = 0, \ .xpd_bias = 0, \
.dbg_atten = 0x0, \ .dbg_atten = 0x0,\
.pd_cur = 0, \ .pd_cur = 0, \
.bias_sleep = 0 \ .bias_sleep = 0 \
}, \ }, \
.regulator0 = { \ .regulator0 = { \
.slp_mem_xpd = 0, \ .slp_connect_en_sleep = 1, \
.slp_logic_xpd = 0, \ .slp_mem_xpd = 0, \
.xpd = 1, \ .slp_logic_xpd = 0, \
.slp_mem_dbias = 0, \ .xpd = 1, \
.slp_logic_dbias = 0, \ .slp_mem_dbias = 0, \
.dbias = 1 \ .slp_logic_dbias = 0, \
.dbias = 1 \
}, \ }, \
.regulator1 = { \ .regulator1 = { \
.drv_b = 0x0 \ .drv_b = 0x0 \
} \ } \
} }

26
components/soc/esp32c61/register/soc/pmu_reg.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -1336,18 +1336,6 @@ extern "C" {
#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU
#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28
/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register
* need_des
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4)
/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S)
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0
/** PMU_HP_SLEEP_LP_DIG_POWER_REG register /** PMU_HP_SLEEP_LP_DIG_POWER_REG register
* need_des * need_des
*/ */
@@ -1400,18 +1388,6 @@ extern "C" {
#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U
#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 #define PMU_HP_SLEEP_PD_OSC_CLK_S 31
/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register
* need_des
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0)
/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S)
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0
/** PMU_LP_SLEEP_LP_REGULATOR0_REG register /** PMU_LP_SLEEP_LP_REGULATOR0_REG register
* need_des * need_des
*/ */

19
components/soc/esp32c61/register/soc/pmu_struct.h
View File

@@ -1,5 +1,5 @@
/** /**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -156,6 +156,23 @@ typedef union {
uint32_t slp_logic_dbias: 4; uint32_t slp_logic_dbias: 4;
uint32_t dbias : 5; uint32_t dbias : 5;
}; };
struct {
uint32_t reserved2 : 3;
uint32_t slp_connect_en_active: 1;
uint32_t reserved3 : 11;
uint32_t dbias_init_active : 1;
uint32_t reserved4 : 16;
};
struct {
uint32_t reserved5 : 15;
uint32_t slp_connect_en_modem : 1;
uint32_t reserved6 : 16;
};
struct {
uint32_t reserved7 : 15;
uint32_t slp_connect_en_sleep : 1;
uint32_t reserved8 : 16;
};
uint32_t val; uint32_t val;
} pmu_hp_regulator0_reg_t; } pmu_hp_regulator0_reg_t;