diff --git a/components/esp_driver_i2s/Kconfig b/components/esp_driver_i2s/Kconfig
index 72628d820e..919b6ec143 100644
--- a/components/esp_driver_i2s/Kconfig
+++ b/components/esp_driver_i2s/Kconfig
@@ -3,6 +3,7 @@ menu "ESP-Driver:I2S Configurations"
     config I2S_ISR_IRAM_SAFE
         bool "I2S ISR IRAM-Safe"
         default n
+        select GDMA_ISR_IRAM_SAFE if SOC_GDMA_SUPPORTED
         help
             Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be
             executable when the cache is disabled (e.g. SPI Flash write).
diff --git a/components/esp_driver_i2s/i2s_private.h b/components/esp_driver_i2s/i2s_private.h
index 3675d29897..d2e914b80a 100644
--- a/components/esp_driver_i2s/i2s_private.h
+++ b/components/esp_driver_i2s/i2s_private.h
@@ -31,7 +31,7 @@ extern "C" {
 
 // If ISR handler is allowed to run whilst cache is disabled,
 // Make sure all the code and related variables used by the handler are in the SRAM
-#if CONFIG_I2S_ISR_IRAM_SAFE
+#if CONFIG_I2S_ISR_IRAM_SAFE || CONFIG_GDMA_ISR_IRAM_SAFE
 #define I2S_INTR_ALLOC_FLAGS    (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED)
 #define I2S_MEM_ALLOC_CAPS      (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
 #else