mirror of
https://github.com/espressif/esp-idf.git
synced 2026-05-19 23:45:28 +02:00
fix(esp32p4): Fixed interrupt handling to use the CLIC controller
This commit is contained in:
Omar Chebib
+25
-120
@@ -9,6 +9,7 @@
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#include "riscv/rvruntime-frames.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#include "esp_private/vectors_const.h"
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.equ SAVE_REGS, 32
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@@ -60,7 +61,7 @@
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/* Restore the general purpose registers (excluding gp) from the context on
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* the stack. The context is then deallocated. The default size is CONTEXT_SIZE
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* but it can be overriden. */
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* but it can be overridden. */
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.macro restore_general_regs cxt_size=CONTEXT_SIZE
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lw ra, RV_STK_RA(sp)
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lw tp, RV_STK_TP(sp)
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@@ -107,92 +108,10 @@
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#endif
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.section .exception_vectors.text
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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/**
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* TODO: IDF-7863, P4, see jira to know what changed and what need to be checked
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*/
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#if SOC_INT_CLIC_SUPPORTED
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.balign 0x40
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#else
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.balign 0x100
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#endif
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.global _vector_table
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.type _vector_table, @function
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_vector_table:
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.option push
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.option norvc
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#if SOC_INT_CLIC_SUPPORTED
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j _trap_handler
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#else
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j _panic_handler /* exception handler, entry 0 */
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#if ETS_INT_WDT_INUM != 24
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#error "ETS_INT_WDT_INUM expected to be 24"
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#endif
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.rept (ETS_INT_WDT_INUM - 1)
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j _interrupt_handler /* 23 identical entries, all pointing to the interrupt handler */
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.endr
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j _panic_handler /* 24: ETS_INT_WDT_INUM panic-interrupt (soc-level panic) */
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j _panic_handler /* 25: ETS_CACHEERR_INUM panic-interrupt (soc-level panic) */
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#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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j _panic_handler /* 26: ETS_MEMPROT_ERR_INUM panic-interrupt (soc-level panic) */
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#else
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j _interrupt_handler /* 26: interrupt-handler */
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#endif // CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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j _panic_handler /* 27: ETS_ASSIST_DEBUG_INUM panic-interrupt (soc-level panic) */
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#else
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j _interrupt_handler /* 27: interrupt-handler */
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#endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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.rept (ETS_MAX_INUM - ETS_ASSIST_DEBUG_INUM)
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j _interrupt_handler /* remain entries are identical, all pointing to the interrupt handler */
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.endr
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#endif
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.option pop
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.size _vector_table, .-_vector_table
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#if SOC_INT_CLIC_SUPPORTED
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.balign 0x40
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.global _mtvt_table
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.type _mtvt_table, @function
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_mtvt_table:
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.option push
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.option norvc
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.rept 48
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.word _interrupt_handler
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.endr
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.option pop
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.size _mtvt_table, .-_mtvt_table
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#endif
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#if SOC_INT_CLIC_SUPPORTED
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.type _trap_handler, @function
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_trap_handler:
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addi sp, sp, -RV_STK_FRMSZ
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sw t0, RV_STK_T0(sp)
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sw t1, RV_STK_T1(sp)
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csrr t0, mcause
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li t1, 0x80000000
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bltu t0, t1, _panic_handler
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lw t0, RV_STK_T0(sp)
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lw t1, RV_STK_T1(sp)
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addi sp, sp, RV_STK_FRMSZ
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//ESP32P4-TODO: ETS_T1_WDT_INUM/ETS_CACHEERR_INUM/ETS_MEMPROT_ERR_INUM
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j _interrupt_handler
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.size _trap_handler, .-_trap_handler
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#endif
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/* Exception handler.*/
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.type _panic_handler, @function
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.global _panic_handler
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_panic_handler:
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/* Allocate space on the stack and store general purpose registers */
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save_general_regs RV_STK_FRMSZ
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@@ -224,16 +143,11 @@ _panic_handler:
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mv a0, sp
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csrr a1, mcause
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/*
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* MINHV[30]: CPU is fetching vector interrupt entry address or not
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* MPP[29:28]: MSTATUS.MPP[1:0]
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* MPIL[23:16]: interrupt level before entrering interrupt isr
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*/
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#if SOC_INT_CLIC_SUPPORTED
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la t1, 0x80000fff
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/* Only keep the interrupt bit and the source cause of the trap */
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li t1, VECTORS_MCAUSE_INTBIT_MASK | VECTORS_MCAUSE_REASON_MASK
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and a1, a1, t1
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#endif
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/* Branches instructions don't accept immediates values, so use t1 to
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/* Branches instructions don't accept immediate values, so use t1 to
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* store our comparator */
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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@@ -258,6 +172,10 @@ _call_panic_handler:
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* structure */
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not t0, t0
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and a1, a1, t0
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#if CONFIG_SOC_INT_CLIC_SUPPORTED
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/* When CLIC is supported, external interrupts are shifted by 16, deduct this difference from mcause */
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add a1, a1, -16
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#endif // CONFIG_SOC_INT_CLIC_SUPPORTED
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sw a1, RV_STK_MCAUSE(sp)
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jal panic_from_isr
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@@ -275,6 +193,7 @@ _return_from_exception:
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mret
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.size _panic_handler, .-_panic_handler
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/* This is the interrupt handler.
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* It saves the registers on the stack,
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* prepares for interrupt nesting,
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@@ -300,12 +219,8 @@ _interrupt_handler:
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/* Save SP */
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sw t0, RV_STK_SP(sp)
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7861
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/* Before doing anythig preserve the stack pointer */
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/* It will be saved in current TCB, if needed */
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mv a0, sp
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#endif //#if CONFIG_IDF_TARGET_ESP32P4
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/* Notify the RTOS that an interrupt ocurred, it will save the current stack pointer
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* in the running TCB, no need to pass it as a parameter */
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call rtos_int_enter
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/* If this is a non-nested interrupt, SP now points to the interrupt stack */
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@@ -313,13 +228,13 @@ _interrupt_handler:
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csrr s1, mcause
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csrr s2, mstatus
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#if !SOC_INT_CLIC_SUPPORTED
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#if !SOC_INT_HW_NESTED_SUPPORTED
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/* Save the interrupt threshold level */
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li t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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lw s3, 0(t0)
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/* Increase interrupt threshold level */
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li t2, 0x7fffffff
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li t2, VECTORS_MCAUSE_REASON_MASK
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and t1, s1, t2 /* t1 = mcause & mask */
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slli t1, t1, 2 /* t1 = mcause * 4 */
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li t2, INTC_INT_PRIO_REG(0)
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@@ -328,7 +243,7 @@ _interrupt_handler:
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addi t2, t2, 1 /* t2 = t2 +1 */
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sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
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fence
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#endif
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#endif // !SOC_INT_HW_NESTED_SUPPORTED
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li t0, 0x8
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csrrs t0, mstatus, t0
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@@ -354,11 +269,7 @@ _interrupt_handler:
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mv a0, sp /* argument 1, stack pointer */
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mv a1, s1 /* argument 2, interrupt number (mcause) */
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/* mask off the interrupt flag of mcause */
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#if !SOC_INT_CLIC_SUPPORTED
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li t0, 0x7fffffff
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#else
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li t0, 0x00000fff
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#endif
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li t0, VECTORS_MCAUSE_REASON_MASK
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and a1, a1, t0
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jal _global_interrupt_handler
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@@ -368,26 +279,20 @@ _interrupt_handler:
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csrrc t0, mstatus, t0
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/* MIE cleared. Nested interrupts are disabled */
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#if !SOC_INT_CLIC_SUPPORTED
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#if !SOC_INT_HW_NESTED_SUPPORTED
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/* restore the interrupt threshold level */
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li t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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sw s3, 0(t0)
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fence
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#endif
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#endif // !SOC_INT_HW_NESTED_SUPPORTED
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#if SOC_INT_CLIC_SUPPORTED
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/* Yield to the next task is needed: */
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mv a0, sp
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#endif
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/* The RTOS will restore the current TCB stack pointer. This routine will preserve s1 and s2 but alter s0. */
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call rtos_int_exit
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#if CONFIG_IDF_TARGET_ESP32P4
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//TODO: IDF-7861
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/* The next (or current) stack pointer is returned in a0 */
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mv sp, a0
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#endif //#if CONFIG_IDF_TARGET_ESP32P4
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/* restore the rest of the registers */
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/* Restore the rest of the registers.
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* In case the target uses the CLIC, it is mandatory to restore `mcause` register since it contains
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* the former CPU priority. When executing `mret`, the hardware will restore the former threshold,
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* from `mcause` to `mintstatus` CSR */
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csrw mcause, s1
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csrw mstatus, s2
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restore_mepc
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