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fix(spi_master): change MOSI pin default idle level to low

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Chen Jichang
2024-07-01 15:44:19 +08:00
parent 8cac15e95b
commit 8d15c0417f
1 changed files with 17 additions and 6 deletions
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23
components/hal/esp32p4/include/hal/spi_ll.h
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@ -42,6 +42,7 @@ extern "C" {
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words #define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV 1 //clock source have divider before peripheral
#define SPI_LL_CLK_SRC_PRE_DIV_MAX 512//div1(8bit) * div2(8bit but set const 2) #define SPI_LL_CLK_SRC_PRE_DIV_MAX 512//div1(8bit) * div2(8bit but set const 2)
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
/** /**
* The data structure holding calculated clock configuration. Since the * The data structure holding calculated clock configuration. Since the
@ -358,7 +359,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
/** /**
* Reset SPI CPU TX FIFO * Reset SPI CPU TX FIFO
* *
* On P4, this function is not seperated * On P4, this function is not separated
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
*/ */
@ -371,7 +372,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
/** /**
* Reset SPI CPU RX FIFO * Reset SPI CPU RX FIFO
* *
* On P4, this function is not seperated * On P4, this function is not separated
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
*/ */
@ -760,7 +761,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl
* Get the frequency of given dividers. Don't use in app. * Get the frequency of given dividers. Don't use in app.
* *
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param pre Pre devider. * @param pre Pre divider.
* @param n Main divider. * @param n Main divider.
* *
* @return Frequency of given dividers. * @return Frequency of given dividers.
@ -771,10 +772,10 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
} }
/** /**
* Calculate the nearest frequency avaliable for master. * Calculate the nearest frequency available for master.
* *
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param hz Frequncy desired. * @param hz Frequency desired.
* @param duty_cycle Duty cycle desired. * @param duty_cycle Duty cycle desired.
* @param out_reg Output address to store the calculated clock configurations for the return frequency. * @param out_reg Output address to store the calculated clock configurations for the return frequency.
* *
@ -854,7 +855,7 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
* *
* @param hw Beginning address of the peripheral registers. * @param hw Beginning address of the peripheral registers.
* @param fapb APB clock of the system. * @param fapb APB clock of the system.
* @param hz Frequncy desired. * @param hz Frequency desired.
* @param duty_cycle Duty cycle desired. * @param duty_cycle Duty cycle desired.
* *
* @return Actual frequency that is used. * @return Actual frequency that is used.
@ -880,6 +881,16 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela
{ {
} }
/**
* Determine and unify the default level of mosi line when bus free
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
}
/** /**
* Set the miso delay applied to the input signal before the internal peripheral. (Preview) * Set the miso delay applied to the input signal before the internal peripheral. (Preview)
* *