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esp_system: check early for single core variant

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This commit is contained in:
Renz Bagaporo
2020-10-05 18:50:09 +08:00
committed by bot
parent 2a6dd33d35
commit 8d32232899
2 changed files with 38 additions and 43 deletions
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72
components/esp_system/port/cpu_start.c
View File

@@ -202,51 +202,55 @@ void IRAM_ATTR call_start_cpu1(void)
static void start_other_core(void) static void start_other_core(void)
{ {
// If not the single core variant of ESP32 - check this since there is esp_chip_info_t chip_info;
esp_chip_info(&chip_info);
// If not the single core variant of a target - check this since there is
// no separate soc_caps.h for the single core variant. // no separate soc_caps.h for the single core variant.
bool is_single_core = false; if (!(chip_info.cores > 1)) {
#if CONFIG_IDF_TARGET_ESP32 ESP_EARLY_LOGE(TAG, "Running on single core variant of a chip, but app is built with multi-core support.");
is_single_core = REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU); ESP_EARLY_LOGE(TAG, "Check that CONFIG_FREERTOS_UNICORE is enabled in menuconfig");
#endif abort();
if (!is_single_core) { }
ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
Cache_Flush(1); Cache_Flush(1);
Cache_Read_Enable(1); Cache_Read_Enable(1);
#endif #endif
esp_cpu_unstall(1);
// Enable clock and reset APP CPU. Note that OpenOCD may have already esp_cpu_unstall(1);
// enabled clock and taken APP CPU out of reset. In this case don't reset
// APP CPU again, as that will clear the breakpoints which may have already // Enable clock and reset APP CPU. Note that OpenOCD may have already
// been set. // enabled clock and taken APP CPU out of reset. In this case don't reset
// APP CPU again, as that will clear the breakpoints which may have already
// been set.
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) { if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
} }
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) { if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) {
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING); REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING); REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
} }
#endif #endif
ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1); ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
volatile bool cpus_up = false; bool cpus_up = false;
while (!cpus_up) { while (!cpus_up) {
cpus_up = true; cpus_up = true;
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
cpus_up &= s_cpu_up[i]; cpus_up &= s_cpu_up[i];
}
esp_rom_delay_us(100);
} }
esp_rom_delay_us(100);
} }
} }
#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

9
components/freertos/port/xtensa/port.c
View File

@@ -534,15 +534,6 @@ void esp_startup_start_app(void)
#endif #endif
#endif #endif
// ESP32 has single core variants. Check that FreeRTOS has been configured properly.
#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
ESP_EARLY_LOGE(TAG, "Running on single core chip, but FreeRTOS is built with dual core support.");
ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
abort();
}
#endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
esp_startup_start_app_common(); esp_startup_start_app_common();
ESP_LOGI(TAG, "Starting scheduler on PRO CPU."); ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");