espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-02 20:24:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

heap: update RTC memory heap caps

Browse Source
This commit is contained in:
wuzhenghui
2021-11-03 19:20:39 +08:00
parent 226f49f37d
commit 8d33d54af7
4 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/heap/port/esp32/memory_layout.c
View File

@@ -69,7 +69,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
//Type 15: SPI SRAM data //Type 15: SPI SRAM data
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 16: RTC Fast RAM //Type 16: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t); const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);

2
components/heap/port/esp32c3/memory_layout.c
View File

@@ -43,7 +43,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
// Type 3: IRAM // Type 3: IRAM
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 4: RTCRAM // Type 4: RTCRAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE

2
components/heap/port/esp32h2/memory_layout.c
View File

@@ -43,7 +43,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
// Type 3: IRAM // Type 3: IRAM
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 4: RTCRAM // Type 4: RTCRAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE

2
components/heap/port/esp32s2/memory_layout.c
View File

@@ -52,7 +52,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
//TODO, in fact, part of them support EDMA, to be supported. //TODO, in fact, part of them support EDMA, to be supported.
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 5: RTC Fast RAM //Type 5: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE