diff --git a/components/efuse/esp32c5/esp_efuse_utility.c b/components/efuse/esp32c5/esp_efuse_utility.c index 1dc28a7aa0..44262ee4f7 100644 --- a/components/efuse/esp32c5/esp_efuse_utility.c +++ b/components/efuse/esp32c5/esp_efuse_utility.c @@ -20,7 +20,7 @@ extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; /*Range addresses to read blocks*/ const esp_efuse_range_addr_t range_read_addr_blocks[] = { - {EFUSE_RD_WR_DIS0_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT {EFUSE_RD_MAC_SYS0_REG, EFUSE_RD_MAC_SYS5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA diff --git a/components/hal/ecdsa_hal.c b/components/hal/ecdsa_hal.c index 5c10802e2c..4ed2d5bfc3 100644 --- a/components/hal/ecdsa_hal.c +++ b/components/hal/ecdsa_hal.c @@ -26,7 +26,7 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf) { if (conf->use_km_key == 0) { - efuse_hal_set_ecdsa_key(conf->efuse_key_blk); + efuse_hal_set_ecdsa_key(conf->curve, conf->efuse_key_blk); #if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY // Force Key Manager to use eFuse key for XTS-AES operation @@ -49,9 +49,11 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf) #if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE ecdsa_ll_set_k_type(conf->sign_type); +#if !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP if (conf->sign_type == ECDSA_K_TYPE_DETERMINISITIC) { ecdsa_ll_set_deterministic_loop(conf->loop_number); } +#endif /* !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ #endif } @@ -224,11 +226,9 @@ void ecdsa_hal_export_pubkey(ecdsa_hal_config_t *conf, uint8_t *pub_x, uint8_t * } #endif /* SOC_ECDSA_SUPPORT_EXPORT_PUBKEY */ -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE - +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP bool ecdsa_hal_det_signature_k_check(void) { return (ecdsa_ll_check_k_value() == 0); } - -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c index 43a007aca2..afafaac53e 100644 --- a/components/hal/efuse_hal.c +++ b/components/hal/efuse_hal.c @@ -57,9 +57,9 @@ IRAM_ATTR bool efuse_hal_flash_encryption_enabled(void) } #if SOC_EFUSE_ECDSA_KEY -void efuse_hal_set_ecdsa_key(int efuse_blk) +void efuse_hal_set_ecdsa_key(ecdsa_curve_t curve, int efuse_blk) { - efuse_ll_set_ecdsa_key_blk(efuse_blk); + efuse_ll_set_ecdsa_key_blk(curve, efuse_blk); efuse_ll_rs_bypass_update(); diff --git a/components/hal/esp32c5/include/hal/ecdsa_ll.h b/components/hal/esp32c5/include/hal/ecdsa_ll.h index 58bb389aeb..52ddd9e4c3 100644 --- a/components/hal/esp32c5/include/hal/ecdsa_ll.h +++ b/components/hal/esp32c5/include/hal/ecdsa_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -194,11 +194,11 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode) static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve) { switch (curve) { - case ECDSA_CURVE_SECP256R1: - REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE); - break; case ECDSA_CURVE_SECP192R1: - REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE); + case ECDSA_CURVE_SECP256R1: + case ECDSA_CURVE_SECP384R1: + case ECDSA_CURVE_SM2: + REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve); break; default: HAL_ASSERT(false && "Unsupported curve"); @@ -248,16 +248,6 @@ static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type) } } -/** - * @brief Set the loop number value that is used for deterministic derivation of K - * - * @param loop_number Loop number for deterministic K - */ -static inline void ecdsa_ll_set_deterministic_loop(uint16_t loop_number) -{ - REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_LOOP, loop_number); -} - /** * @brief Set the stage of ECDSA operation * @@ -415,17 +405,6 @@ static inline int ecdsa_ll_get_operation_result(void) return REG_GET_BIT(ECDSA_RESULT_REG, ECDSA_OPERATION_RESULT); } -/** - * @brief Check if the k value is greater than the curve order. - * - * @return 0, k value is not greater than the curve order. In this case, the k value is the set k value. - * @return 1, k value is greater than than the curve order. In this case, the k value is the set (k mod n). - */ -static inline int ecdsa_ll_check_k_value(void) -{ - return REG_GET_BIT(ECDSA_RESULT_REG, ECDSA_K_VALUE_WARNING); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h index 359a0a6562..081f6242b2 100644 --- a/components/hal/esp32c5/include/hal/efuse_ll.h +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -38,7 +39,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_c __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) { - return EFUSE.rd_repeat_data1.wdt_delay_sel; + return EFUSE.rd_repeat_data0.wdt_delay_sel; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) @@ -93,14 +94,25 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return EFUSE.rd_mac_sys2.pkg_version; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { - EFUSE.conf.cfg_ecdsa_blk = efuse_blk; + switch (curve) { + case ECDSA_CURVE_SECP192R1: + EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk; + break; + case ECDSA_CURVE_SECP256R1: + EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk; + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + break; + } } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) { - return EFUSE.rd_sys_part1_data4.ocode; + // TODO: IDF-13007 + return 0; } /******************* eFuse control functions *************************/ diff --git a/components/hal/esp32c61/include/hal/efuse_ll.h b/components/hal/esp32c61/include/hal/efuse_ll.h index be9c240152..f86f8392ba 100644 --- a/components/hal/esp32c61/include/hal/efuse_ll.h +++ b/components/hal/esp32c61/include/hal/efuse_ll.h @@ -13,6 +13,7 @@ #include "soc/efuse_struct.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -98,8 +99,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE0.conf.cfg_ecdsa_blk; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE0.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/esp32h2/include/hal/efuse_ll.h b/components/hal/esp32h2/include/hal/efuse_ll.h index 16226aa463..c120dfe383 100644 --- a/components/hal/esp32h2/include/hal/efuse_ll.h +++ b/components/hal/esp32h2/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -107,8 +108,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE.conf.cfg_ecdsa_blk; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/esp32h21/include/hal/efuse_ll.h b/components/hal/esp32h21/include/hal/efuse_ll.h index 59159d9df6..99ac523246 100644 --- a/components/hal/esp32h21/include/hal/efuse_ll.h +++ b/components/hal/esp32h21/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" //TODO: [ESP32H21] IDF-11556, inherit from h2 @@ -114,8 +115,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return EFUSE.conf.cfg_ecdsa_blk; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/esp32h4/include/hal/efuse_ll.h b/components/hal/esp32h4/include/hal/efuse_ll.h index 0530ca9bca..a3e6c26611 100644 --- a/components/hal/esp32h4/include/hal/efuse_ll.h +++ b/components/hal/esp32h4/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" //TODO: [ESP32H4] IDF-12322 inherited from verification branch, need check @@ -96,9 +97,10 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk return 0; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { //ESP32H4 TODO + (void)curve; (void)efuse_blk; } diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h index 11fd66c61d..d399f530a8 100644 --- a/components/hal/esp32p4/include/hal/efuse_ll.h +++ b/components/hal/esp32p4/include/hal/efuse_ll.h @@ -11,6 +11,7 @@ #include "soc/efuse_periph.h" #include "hal/assert.h" #include "rom/efuse.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -91,8 +92,9 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return EFUSE.rd_mac_sys_2.pkg_version; } -__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) +__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) { + (void) curve; EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } diff --git a/components/hal/include/hal/ecdsa_hal.h b/components/hal/include/hal/ecdsa_hal.h index 6994410375..182ebbe80d 100644 --- a/components/hal/include/hal/ecdsa_hal.h +++ b/components/hal/include/hal/ecdsa_hal.h @@ -98,7 +98,7 @@ void ecdsa_hal_export_pubkey(ecdsa_hal_config_t *conf, uint8_t *pub_x, uint8_t * */ bool ecdsa_hal_get_operation_result(void); -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP /** * @brief Check if the K value derived by the peripheral during deterministic signature generation is valid * @@ -107,7 +107,7 @@ bool ecdsa_hal_get_operation_result(void); */ bool ecdsa_hal_det_signature_k_check(void); -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ #ifdef __cplusplus } diff --git a/components/hal/include/hal/ecdsa_types.h b/components/hal/include/hal/ecdsa_types.h index c72ae963f7..20caf84a1f 100644 --- a/components/hal/include/hal/ecdsa_types.h +++ b/components/hal/include/hal/ecdsa_types.h @@ -26,6 +26,8 @@ typedef enum { typedef enum { ECDSA_CURVE_SECP192R1, ECDSA_CURVE_SECP256R1, + ECDSA_CURVE_SECP384R1, + ECDSA_CURVE_SM2, } ecdsa_curve_t; /** diff --git a/components/hal/include/hal/efuse_hal.h b/components/hal/include/hal/efuse_hal.h index cfed79f591..c3810acf65 100644 --- a/components/hal/include/hal/efuse_hal.h +++ b/components/hal/include/hal/efuse_hal.h @@ -9,6 +9,7 @@ #include #include #include "soc/soc_caps.h" +#include "hal/ecdsa_types.h" #ifdef __cplusplus extern "C" { @@ -80,9 +81,10 @@ uint32_t efuse_hal_get_chip_ver_pkg(void); * * @note The efuse block must be burnt with key purpose ECDSA_KEY * + * @param curve ECDSA curve type * @param efuse_key_blk Efuse key block number (Must be in [EFUSE_BLK_KEY0...EFUSE_BLK_KEY_MAX - 1] range) */ -void efuse_hal_set_ecdsa_key(int efuse_key_blk); +void efuse_hal_set_ecdsa_key(ecdsa_curve_t curve, int efuse_key_blk); #endif #ifdef __cplusplus diff --git a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c index 8cf5e1dac4..56abd58cb1 100644 --- a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c +++ b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c @@ -198,11 +198,11 @@ void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, b || !memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len); -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP if (k_type == ECDSA_K_TYPE_DETERMINISITIC) { process_again |= !ecdsa_hal_det_signature_k_check(); } -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ } while(process_again); diff --git a/components/mbedtls/port/ecdsa/ecdsa_alt.c b/components/mbedtls/port/ecdsa/ecdsa_alt.c index 5fca558a6f..8a30aa89fd 100644 --- a/components/mbedtls/port/ecdsa/ecdsa_alt.c +++ b/components/mbedtls/port/ecdsa/ecdsa_alt.c @@ -391,11 +391,11 @@ static int esp_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi* r, mbedtls_mpi* s || !memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len); -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP if (k_type == ECDSA_K_TYPE_DETERMINISITIC) { process_again |= !ecdsa_hal_det_signature_k_check(); } -#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ +#endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE && !SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP */ } while (process_again); diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 1767d45aa0..b36ac4c83d 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1051,6 +1051,14 @@ config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY bool default y +config SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE + bool + default y + +config SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP + bool + default y + config SOC_SDM_GROUPS int default 1 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index aacbf2fe1a..8301c855d0 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -423,6 +423,8 @@ /*--------------------------- ECDSA CAPS ---------------------------------------*/ #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1) +#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1) +#define SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP (1) /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_GROUPS 1U diff --git a/components/soc/esp32c5/register/soc/ecdsa_reg.h b/components/soc/esp32c5/register/soc/ecdsa_reg.h index 4893390ced..401786a165 100644 --- a/components/soc/esp32c5/register/soc/ecdsa_reg.h +++ b/components/soc/esp32c5/register/soc/ecdsa_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,44 +23,37 @@ extern "C" { #define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) #define ECDSA_WORK_MODE_V 0x00000003U #define ECDSA_WORK_MODE_S 0 -/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. +/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. */ -#define ECDSA_ECC_CURVE (BIT(2)) +#define ECDSA_ECC_CURVE 0x00000003U #define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) -#define ECDSA_ECC_CURVE_V 0x00000001U +#define ECDSA_ECC_CURVE_V 0x00000003U #define ECDSA_ECC_CURVE_S 2 -/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0; * The source of k select bit. 0: k is automatically generated by hardware. 1: k is * written by software. */ -#define ECDSA_SOFTWARE_SET_K (BIT(3)) +#define ECDSA_SOFTWARE_SET_K (BIT(4)) #define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) #define ECDSA_SOFTWARE_SET_K_V 0x00000001U -#define ECDSA_SOFTWARE_SET_K_S 3 -/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; +#define ECDSA_SOFTWARE_SET_K_S 4 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0; * The source of z select bit. 0: z is generated from SHA result. 1: z is written by * software. */ -#define ECDSA_SOFTWARE_SET_Z (BIT(4)) +#define ECDSA_SOFTWARE_SET_Z (BIT(5)) #define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) #define ECDSA_SOFTWARE_SET_Z_V 0x00000001U -#define ECDSA_SOFTWARE_SET_Z_S 4 -/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; +#define ECDSA_SOFTWARE_SET_Z_S 5 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0; * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by * deterministic derivation algorithm. */ -#define ECDSA_DETERMINISTIC_K (BIT(5)) +#define ECDSA_DETERMINISTIC_K (BIT(6)) #define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) #define ECDSA_DETERMINISTIC_K_V 0x00000001U -#define ECDSA_DETERMINISTIC_K_S 5 -/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0; - * The (loop number - 1) value in the deterministic derivation algorithm to derive k. - */ -#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU -#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S) -#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU -#define ECDSA_DETERMINISTIC_LOOP_S 6 +#define ECDSA_DETERMINISTIC_K_S 6 /** ECDSA_CLK_REG register * ECDSA clock gate register @@ -260,20 +253,12 @@ extern "C" { #define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) #define ECDSA_OPERATION_RESULT_V 0x00000001U #define ECDSA_OPERATION_RESULT_S 0 -/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0; - * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the - * curve order, then actually taken k = k mod n. - */ -#define ECDSA_K_VALUE_WARNING (BIT(1)) -#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S) -#define ECDSA_K_VALUE_WARNING_V 0x00000001U -#define ECDSA_K_VALUE_WARNING_S 1 /** ECDSA_DATE_REG register * Version control register */ #define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) -/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36725040; +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984; * ECDSA version control register */ #define ECDSA_DATE 0x0FFFFFFFU @@ -285,13 +270,14 @@ extern "C" { * ECDSA control SHA register */ #define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) -/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. - * Others: invalid. +/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. */ -#define ECDSA_SHA_MODE 0x00000007U +#define ECDSA_SHA_MODE 0x0000000FU #define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) -#define ECDSA_SHA_MODE_V 0x00000007U +#define ECDSA_SHA_MODE_V 0x0000000FU #define ECDSA_SHA_MODE_S 0 /** ECDSA_SHA_START_REG register @@ -337,37 +323,37 @@ extern "C" { * The memory that stores message. */ #define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) -#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64 /** ECDSA_R_MEM register * The memory that stores r. */ -#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340) -#define ECDSA_R_MEM_SIZE_BYTES 32 +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0) +#define ECDSA_R_MEM_SIZE_BYTES 48 /** ECDSA_S_MEM register * The memory that stores s. */ -#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360) -#define ECDSA_S_MEM_SIZE_BYTES 32 +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410) +#define ECDSA_S_MEM_SIZE_BYTES 48 /** ECDSA_Z_MEM register * The memory that stores software written z. */ -#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380) -#define ECDSA_Z_MEM_SIZE_BYTES 32 +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440) +#define ECDSA_Z_MEM_SIZE_BYTES 48 /** ECDSA_QAX_MEM register * The memory that stores x coordinates of QA or software written k. */ -#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0) -#define ECDSA_QAX_MEM_SIZE_BYTES 32 +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470) +#define ECDSA_QAX_MEM_SIZE_BYTES 48 /** ECDSA_QAY_MEM register * The memory that stores y coordinates of QA. */ -#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0) -#define ECDSA_QAY_MEM_SIZE_BYTES 32 +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0) +#define ECDSA_QAY_MEM_SIZE_BYTES 48 #ifdef __cplusplus } diff --git a/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h b/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h deleted file mode 100644 index 401786a165..0000000000 --- a/components/soc/esp32c5/register/soc/ecdsa_reg_eco2.h +++ /dev/null @@ -1,360 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** ECDSA_CONF_REG register - * ECDSA configure register - */ -#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) -/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; - * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature - * Generate Mode. 2: Export Public Key Mode. 3: invalid. - */ -#define ECDSA_WORK_MODE 0x00000003U -#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) -#define ECDSA_WORK_MODE_V 0x00000003U -#define ECDSA_WORK_MODE_S 0 -/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. - */ -#define ECDSA_ECC_CURVE 0x00000003U -#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) -#define ECDSA_ECC_CURVE_V 0x00000003U -#define ECDSA_ECC_CURVE_S 2 -/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0; - * The source of k select bit. 0: k is automatically generated by hardware. 1: k is - * written by software. - */ -#define ECDSA_SOFTWARE_SET_K (BIT(4)) -#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) -#define ECDSA_SOFTWARE_SET_K_V 0x00000001U -#define ECDSA_SOFTWARE_SET_K_S 4 -/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0; - * The source of z select bit. 0: z is generated from SHA result. 1: z is written by - * software. - */ -#define ECDSA_SOFTWARE_SET_Z (BIT(5)) -#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) -#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U -#define ECDSA_SOFTWARE_SET_Z_S 5 -/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0; - * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by - * deterministic derivation algorithm. - */ -#define ECDSA_DETERMINISTIC_K (BIT(6)) -#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) -#define ECDSA_DETERMINISTIC_K_V 0x00000001U -#define ECDSA_DETERMINISTIC_K_S 6 - -/** ECDSA_CLK_REG register - * ECDSA clock gate register - */ -#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) -/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; - * Write 1 to force on register clock gate. - */ -#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) -#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) -#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U -#define ECDSA_CLK_GATE_FORCE_ON_S 0 - -/** ECDSA_INT_RAW_REG register - * ECDSA interrupt raw register, valid in level. - */ -#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) -/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_RAW (BIT(0)) -#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) -#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U -#define ECDSA_PREP_DONE_INT_RAW_S 0 -/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_RAW (BIT(1)) -#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) -#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U -#define ECDSA_PROC_DONE_INT_RAW_S 1 -/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_RAW (BIT(2)) -#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) -#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U -#define ECDSA_POST_DONE_INT_RAW_S 2 -/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) -#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_RAW_S 3 - -/** ECDSA_INT_ST_REG register - * ECDSA interrupt status register. - */ -#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) -/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_ST (BIT(0)) -#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) -#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U -#define ECDSA_PREP_DONE_INT_ST_S 0 -/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_ST (BIT(1)) -#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) -#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U -#define ECDSA_PROC_DONE_INT_ST_S 1 -/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_ST (BIT(2)) -#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) -#define ECDSA_POST_DONE_INT_ST_V 0x00000001U -#define ECDSA_POST_DONE_INT_ST_S 2 -/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) -#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_ST_S 3 - -/** ECDSA_INT_ENA_REG register - * ECDSA interrupt enable register. - */ -#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) -/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_ENA (BIT(0)) -#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) -#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U -#define ECDSA_PREP_DONE_INT_ENA_S 0 -/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_ENA (BIT(1)) -#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) -#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U -#define ECDSA_PROC_DONE_INT_ENA_S 1 -/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_ENA (BIT(2)) -#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) -#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U -#define ECDSA_POST_DONE_INT_ENA_S 2 -/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) -#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_ENA_S 3 - -/** ECDSA_INT_CLR_REG register - * ECDSA interrupt clear register. - */ -#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) -/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecdsa_prep_done_int interrupt - */ -#define ECDSA_PREP_DONE_INT_CLR (BIT(0)) -#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) -#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U -#define ECDSA_PREP_DONE_INT_CLR_S 0 -/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the ecdsa_proc_done_int interrupt - */ -#define ECDSA_PROC_DONE_INT_CLR (BIT(1)) -#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) -#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U -#define ECDSA_PROC_DONE_INT_CLR_S 1 -/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the ecdsa_post_done_int interrupt - */ -#define ECDSA_POST_DONE_INT_CLR (BIT(2)) -#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) -#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U -#define ECDSA_POST_DONE_INT_CLR_S 2 -/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the ecdsa_sha_release_int interrupt - */ -#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) -#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) -#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U -#define ECDSA_SHA_RELEASE_INT_CLR_S 3 - -/** ECDSA_START_REG register - * ECDSA start register - */ -#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) -/** ECDSA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared - * after configuration. - */ -#define ECDSA_START (BIT(0)) -#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) -#define ECDSA_START_V 0x00000001U -#define ECDSA_START_S 0 -/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; - * Write 1 to input load done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ -#define ECDSA_LOAD_DONE (BIT(1)) -#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) -#define ECDSA_LOAD_DONE_V 0x00000001U -#define ECDSA_LOAD_DONE_S 1 -/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; - * Write 1 to input get done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ -#define ECDSA_GET_DONE (BIT(2)) -#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) -#define ECDSA_GET_DONE_V 0x00000001U -#define ECDSA_GET_DONE_S 2 - -/** ECDSA_STATE_REG register - * ECDSA status register - */ -#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) -/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; - * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY - * state. - */ -#define ECDSA_BUSY 0x00000003U -#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) -#define ECDSA_BUSY_V 0x00000003U -#define ECDSA_BUSY_S 0 - -/** ECDSA_RESULT_REG register - * ECDSA result register - */ -#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) -/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; - * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is - * done. - */ -#define ECDSA_OPERATION_RESULT (BIT(0)) -#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) -#define ECDSA_OPERATION_RESULT_V 0x00000001U -#define ECDSA_OPERATION_RESULT_S 0 - -/** ECDSA_DATE_REG register - * Version control register - */ -#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) -/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984; - * ECDSA version control register - */ -#define ECDSA_DATE 0x0FFFFFFFU -#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) -#define ECDSA_DATE_V 0x0FFFFFFFU -#define ECDSA_DATE_S 0 - -/** ECDSA_SHA_MODE_REG register - * ECDSA control SHA register - */ -#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) -/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: - * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: - * invalid. - */ -#define ECDSA_SHA_MODE 0x0000000FU -#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) -#define ECDSA_SHA_MODE_V 0x0000000FU -#define ECDSA_SHA_MODE_S 0 - -/** ECDSA_SHA_START_REG register - * ECDSA control SHA register - */ -#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) -/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ -#define ECDSA_SHA_START (BIT(0)) -#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) -#define ECDSA_SHA_START_V 0x00000001U -#define ECDSA_SHA_START_S 0 - -/** ECDSA_SHA_CONTINUE_REG register - * ECDSA control SHA register - */ -#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) -/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ -#define ECDSA_SHA_CONTINUE (BIT(0)) -#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) -#define ECDSA_SHA_CONTINUE_V 0x00000001U -#define ECDSA_SHA_CONTINUE_S 0 - -/** ECDSA_SHA_BUSY_REG register - * ECDSA status register - */ -#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) -/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; - * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in - * calculation. 0: SHA is idle. - */ -#define ECDSA_SHA_BUSY (BIT(0)) -#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) -#define ECDSA_SHA_BUSY_V 0x00000001U -#define ECDSA_SHA_BUSY_S 0 - -/** ECDSA_MESSAGE_MEM register - * The memory that stores message. - */ -#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) -#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64 - -/** ECDSA_R_MEM register - * The memory that stores r. - */ -#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0) -#define ECDSA_R_MEM_SIZE_BYTES 48 - -/** ECDSA_S_MEM register - * The memory that stores s. - */ -#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410) -#define ECDSA_S_MEM_SIZE_BYTES 48 - -/** ECDSA_Z_MEM register - * The memory that stores software written z. - */ -#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440) -#define ECDSA_Z_MEM_SIZE_BYTES 48 - -/** ECDSA_QAX_MEM register - * The memory that stores x coordinates of QA or software written k. - */ -#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470) -#define ECDSA_QAX_MEM_SIZE_BYTES 48 - -/** ECDSA_QAY_MEM register - * The memory that stores y coordinates of QA. - */ -#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0) -#define ECDSA_QAY_MEM_SIZE_BYTES 48 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/ecdsa_struct.h b/components/soc/esp32c5/register/soc/ecdsa_struct.h index 858a4ffc5f..6659f30a90 100644 --- a/components/soc/esp32c5/register/soc/ecdsa_struct.h +++ b/components/soc/esp32c5/register/soc/ecdsa_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,30 +23,26 @@ typedef union { * Generate Mode. 2: Export Public Key Mode. 3: invalid. */ uint32_t work_mode:2; - /** ecc_curve : R/W; bitpos: [2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + /** ecc_curve : R/W; bitpos: [3:2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. */ - uint32_t ecc_curve:1; - /** software_set_k : R/W; bitpos: [3]; default: 0; + uint32_t ecc_curve:2; + /** software_set_k : R/W; bitpos: [4]; default: 0; * The source of k select bit. 0: k is automatically generated by hardware. 1: k is * written by software. */ uint32_t software_set_k:1; - /** software_set_z : R/W; bitpos: [4]; default: 0; + /** software_set_z : R/W; bitpos: [5]; default: 0; * The source of z select bit. 0: z is generated from SHA result. 1: z is written by * software. */ uint32_t software_set_z:1; - /** deterministic_k : R/W; bitpos: [5]; default: 0; + /** deterministic_k : R/W; bitpos: [6]; default: 0; * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by * deterministic derivation algorithm. */ uint32_t deterministic_k:1; - /** deterministic_loop : R/W; bitpos: [21:6]; default: 0; - * The (loop number - 1) value in the deterministic derivation algorithm to derive k. - */ - uint32_t deterministic_loop:16; - uint32_t reserved_22:10; + uint32_t reserved_7:25; }; uint32_t val; } ecdsa_conf_reg_t; @@ -227,12 +223,7 @@ typedef union { * done. */ uint32_t operation_result:1; - /** k_value_warning : RO/SS; bitpos: [1]; default: 0; - * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the - * curve order, then actually taken k = k mod n. - */ - uint32_t k_value_warning:1; - uint32_t reserved_2:30; + uint32_t reserved_1:31; }; uint32_t val; } ecdsa_result_reg_t; @@ -244,12 +235,13 @@ typedef union { */ typedef union { struct { - /** sha_mode : R/W; bitpos: [2:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. - * Others: invalid. + /** sha_mode : R/W; bitpos: [3:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: + * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: + * invalid. */ - uint32_t sha_mode:3; - uint32_t reserved_3:29; + uint32_t sha_mode:4; + uint32_t reserved_4:28; }; uint32_t val; } ecdsa_sha_mode_reg_t; @@ -306,7 +298,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36725040; + /** date : R/W; bitpos: [27:0]; default: 37785984; * ECDSA version control register */ uint32_t date:28; @@ -336,19 +328,19 @@ typedef struct { volatile ecdsa_sha_continue_reg_t sha_continue; volatile ecdsa_sha_busy_reg_t sha_busy; uint32_t reserved_21c[25]; - volatile uint32_t message[8]; - uint32_t reserved_2a0[40]; - volatile uint32_t r[8]; - volatile uint32_t s[8]; - volatile uint32_t z[8]; - volatile uint32_t qax[8]; - volatile uint32_t qay[8]; + volatile uint32_t message[16]; + uint32_t reserved_2c0[72]; + volatile uint32_t r[12]; + volatile uint32_t s[12]; + volatile uint32_t z[12]; + volatile uint32_t qax[12]; + volatile uint32_t qay[12]; } ecdsa_dev_t; extern ecdsa_dev_t ECDSA; #ifndef __cplusplus -_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure"); +_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h b/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h deleted file mode 100644 index 6659f30a90..0000000000 --- a/components/soc/esp32c5/register/soc/ecdsa_struct_eco2.h +++ /dev/null @@ -1,348 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Data Memory */ - -/** Group: Configuration registers */ -/** Type of conf register - * ECDSA configure register - */ -typedef union { - struct { - /** work_mode : R/W; bitpos: [1:0]; default: 0; - * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature - * Generate Mode. 2: Export Public Key Mode. 3: invalid. - */ - uint32_t work_mode:2; - /** ecc_curve : R/W; bitpos: [3:2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2. - */ - uint32_t ecc_curve:2; - /** software_set_k : R/W; bitpos: [4]; default: 0; - * The source of k select bit. 0: k is automatically generated by hardware. 1: k is - * written by software. - */ - uint32_t software_set_k:1; - /** software_set_z : R/W; bitpos: [5]; default: 0; - * The source of z select bit. 0: z is generated from SHA result. 1: z is written by - * software. - */ - uint32_t software_set_z:1; - /** deterministic_k : R/W; bitpos: [6]; default: 0; - * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by - * deterministic derivation algorithm. - */ - uint32_t deterministic_k:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} ecdsa_conf_reg_t; - -/** Type of start register - * ECDSA start register - */ -typedef union { - struct { - /** start : WT; bitpos: [0]; default: 0; - * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared - * after configuration. - */ - uint32_t start:1; - /** load_done : WT; bitpos: [1]; default: 0; - * Write 1 to input load done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ - uint32_t load_done:1; - /** get_done : WT; bitpos: [2]; default: 0; - * Write 1 to input get done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. - */ - uint32_t get_done:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ecdsa_start_reg_t; - - -/** Group: Clock and reset registers */ -/** Type of clk register - * ECDSA clock gate register - */ -typedef union { - struct { - /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; - * Write 1 to force on register clock gate. - */ - uint32_t clk_gate_force_on:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_clk_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * ECDSA interrupt raw register, valid in level. - */ -typedef union { - struct { - /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_raw:1; - /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_raw:1; - /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_raw:1; - /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_raw_reg_t; - -/** Type of int_st register - * ECDSA interrupt status register. - */ -typedef union { - struct { - /** prep_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_st:1; - /** proc_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_st:1; - /** post_done_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_st:1; - /** sha_release_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_st_reg_t; - -/** Type of int_ena register - * ECDSA interrupt enable register. - */ -typedef union { - struct { - /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_ena:1; - /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_ena:1; - /** post_done_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_ena:1; - /** sha_release_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_ena_reg_t; - -/** Type of int_clr register - * ECDSA interrupt clear register. - */ -typedef union { - struct { - /** prep_done_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecdsa_prep_done_int interrupt - */ - uint32_t prep_done_int_clr:1; - /** proc_done_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the ecdsa_proc_done_int interrupt - */ - uint32_t proc_done_int_clr:1; - /** post_done_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the ecdsa_post_done_int interrupt - */ - uint32_t post_done_int_clr:1; - /** sha_release_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the ecdsa_sha_release_int interrupt - */ - uint32_t sha_release_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_int_clr_reg_t; - - -/** Group: Status registers */ -/** Type of state register - * ECDSA status register - */ -typedef union { - struct { - /** busy : RO; bitpos: [1:0]; default: 0; - * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY - * state. - */ - uint32_t busy:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} ecdsa_state_reg_t; - - -/** Group: Result registers */ -/** Type of result register - * ECDSA result register - */ -typedef union { - struct { - /** operation_result : RO/SS; bitpos: [0]; default: 0; - * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is - * done. - */ - uint32_t operation_result:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_result_reg_t; - - -/** Group: SHA register */ -/** Type of sha_mode register - * ECDSA control SHA register - */ -typedef union { - struct { - /** sha_mode : R/W; bitpos: [3:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2: - * SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others: - * invalid. - */ - uint32_t sha_mode:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ecdsa_sha_mode_reg_t; - -/** Type of sha_start register - * ECDSA control SHA register - */ -typedef union { - struct { - /** sha_start : WT; bitpos: [0]; default: 0; - * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ - uint32_t sha_start:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_sha_start_reg_t; - -/** Type of sha_continue register - * ECDSA control SHA register - */ -typedef union { - struct { - /** sha_continue : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. - */ - uint32_t sha_continue:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_sha_continue_reg_t; - -/** Type of sha_busy register - * ECDSA status register - */ -typedef union { - struct { - /** sha_busy : RO; bitpos: [0]; default: 0; - * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in - * calculation. 0: SHA is idle. - */ - uint32_t sha_busy:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ecdsa_sha_busy_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 37785984; - * ECDSA version control register - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} ecdsa_date_reg_t; - - -typedef struct { - uint32_t reserved_000; - volatile ecdsa_conf_reg_t conf; - volatile ecdsa_clk_reg_t clk; - volatile ecdsa_int_raw_reg_t int_raw; - volatile ecdsa_int_st_reg_t int_st; - volatile ecdsa_int_ena_reg_t int_ena; - volatile ecdsa_int_clr_reg_t int_clr; - volatile ecdsa_start_reg_t start; - volatile ecdsa_state_reg_t state; - volatile ecdsa_result_reg_t result; - uint32_t reserved_028[53]; - volatile ecdsa_date_reg_t date; - uint32_t reserved_100[64]; - volatile ecdsa_sha_mode_reg_t sha_mode; - uint32_t reserved_204[3]; - volatile ecdsa_sha_start_reg_t sha_start; - volatile ecdsa_sha_continue_reg_t sha_continue; - volatile ecdsa_sha_busy_reg_t sha_busy; - uint32_t reserved_21c[25]; - volatile uint32_t message[16]; - uint32_t reserved_2c0[72]; - volatile uint32_t r[12]; - volatile uint32_t s[12]; - volatile uint32_t z[12]; - volatile uint32_t qax[12]; - volatile uint32_t qay[12]; -} ecdsa_dev_t; - -extern ecdsa_dev_t ECDSA; - -#ifndef __cplusplus -_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/efuse_reg.h b/components/soc/esp32c5/register/soc/efuse_reg.h index 51a6a3122d..ec17a5b29a 100644 --- a/components/soc/esp32c5/register/soc/efuse_reg.h +++ b/components/soc/esp32c5/register/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -143,13 +143,16 @@ extern "C" { #define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -/** EFUSE_RD_WR_DIS0_REG register +/** EFUSE_RD_WR_DIS_REG register * Represents rd_wr_dis */ -#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c) +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled or - * enabled.\\ 1: Disabled\\ 0: Enabled\\ + * Represents whether programming of individual eFuse memory bit is disabled. For + * mapping between the bits of this field and the eFuse memory bits, please refer to + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -161,102 +164,131 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether reading of individual eFuse block (BLOCK4 \verb+~+ BLOCK10) is + * disabled. For mapping between the bits of this field and the eFuse blocks, please + * refer to Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 -/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [7]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI : RO; bitpos: [7]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the high part of the field). */ -#define EFUSE_RD_RESERVE_0_39 (BIT(7)) -#define EFUSE_RD_RESERVE_0_39_M (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S) -#define EFUSE_RD_RESERVE_0_39_V 0x00000001U -#define EFUSE_RD_RESERVE_0_39_S 7 +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI (BIT(7)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether cache is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) #define EFUSE_DIS_ICACHE_V 0x00000001U #define EFUSE_DIS_ICACHE_S 8 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note + * that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only + * when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_USB_JTAG (BIT(9)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 -/** EFUSE_RD_RESERVE_0_42 : RW; bitpos: [10]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [10]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. + * 1: Enabled + * 0: Disabled */ -#define EFUSE_RD_RESERVE_0_42 (BIT(10)) -#define EFUSE_RD_RESERVE_0_42_M (EFUSE_RD_RESERVE_0_42_V << EFUSE_RD_RESERVE_0_42_S) -#define EFUSE_RD_RESERVE_0_42_V 0x00000001U -#define EFUSE_RD_RESERVE_0_42_S 10 +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(10)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether USB Serial/JTAG is disabled. + * 1: Disabled + * 0: Enabled + * + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) #define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) #define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether the function that forces chip into Download mode is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether SPI0 controller during boot\_mode\_download is disabled. + * 0: Enabled + * 1: Disabled */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether TWAI$^®$ function is disabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) #define EFUSE_DIS_TWAI_V 0x00000001U #define EFUSE_DIS_TWAI_S 14 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Represents whether the selection between usb_to_jtag and pad_to_jtag through - * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether the selection of a JTAG signal source through the strapping pin + * value is enabled when all of + * \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}, + * \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and + * \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Enabled + * 0: Disabled */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even - * number: enabled\\ + * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via + * HMAC. + * Odd count of bits with a value of 1: Disabled + * Even count of bits with a value of 1: Enabled */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ - * 0: enabled\\ + * Represents whether PAD JTAG is disabled in the hard way (permanently). + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) #define EFUSE_DIS_PAD_JTAG_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode).\\ 1: disabled\\ 0: enabled\\ + * Represents whether flash encryption is disabled (except in SPI boot mode). + * 1: Disabled + * 0: Enabled */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) @@ -264,6 +296,7 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) @@ -271,221 +304,286 @@ extern "C" { #define EFUSE_USB_DREFH_S 21 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) #define EFUSE_USB_DREFL_V 0x00000003U #define EFUSE_USB_DREFL_S 23 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not - * exchanged\\ + * Represents whether the D+ and D- pins is exchanged. + * 1: Exchanged + * 0: Not exchanged */ #define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) #define EFUSE_USB_EXCHG_PINS_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_S 25 /** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not - * functioned\\ + * Represents whether VDD SPI pin is functioned as GPIO. + * 1: Functioned + * 0: Not functioned */ #define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 26 -/** EFUSE_RD_RESERVE_0_59 : RW; bitpos: [31:27]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [28:27]; default: 0; + * Represents RTC watchdog timeout threshold. + * 0: The originally configured STG0 threshold × 2 + * 1: The originally configured STG0 threshold × 4 + * 2: The originally configured STG0 threshold × 8 + * 3: The originally configured STG0 threshold × 16 */ -#define EFUSE_RD_RESERVE_0_59 0x0000001FU -#define EFUSE_RD_RESERVE_0_59_M (EFUSE_RD_RESERVE_0_59_V << EFUSE_RD_RESERVE_0_59_S) -#define EFUSE_RD_RESERVE_0_59_V 0x0000001FU -#define EFUSE_RD_RESERVE_0_59_S 27 +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 27 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO : RO; bitpos: [31:29]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the low part of the field). + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_V 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_S 29 /** EFUSE_RD_REPEAT_DATA1_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0; - * Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled - * \\ 0: enabled.\\ + * Represents whether the new key deployment of key manager is disabled. + * Bit0: Represents whether the new ECDSA key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is + * disabled + * 0: Enabled + * 1: Disabled + * Bit2: Represents whether the new HMAC key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit3: Represents whether the new DS key deployment is disabled + * 0: Enabled + * 1: Disabled */ #define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) #define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_S 0 /** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0; - * Set the bits to control key manager random number switch cycle. 0: control by - * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + * Represents the cycle at which the Key Manager switches random numbers. + * 0: Controlled by the + * \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For + * more information, please refer to Chapter \ref{mod:keymng} + * \textit{\nameref{mod:keymng}} + * 1: 8 Key Manager clock cycles + * 2: 16 Key Manager clock cycles + * 3: 32 Key Manager clock cycles */ #define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U #define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) #define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U #define EFUSE_KM_RND_SWITCH_CYCLE_S 4 /** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0; - * Set each bit to control whether corresponding key can only be deployed once. 1 is - * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds + * Represents whether the corresponding key can be deployed only once. + * Bit0: Represents whether the ECDSA key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit2: Represents whether the HMAC key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit3: Represents whether the DS key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once */ #define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) #define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_S 6 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0; - * Set each bit to control whether corresponding key must come from key manager. 1 is - * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds + * Represents whether the corresponding key must come from Key Manager. + * Bit0: Represents whether the ECDSA key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key + * Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit2: Represents whether the HMAC key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit3: Represents whether the DS key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 10 /** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0; - * Set this bit to disable software written init key, and force use efuse_init_key. + * Represents whether to disable the use of the initialization key written by software + * and instead force use efuse\_init\_key. + * 0: Enable + * 1: Disable */ #define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(14)) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 -/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [15]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader. + * 1: Enable + * 0: Disable */ -#define EFUSE_RD_RESERVE_0_79 (BIT(15)) -#define EFUSE_RD_RESERVE_0_79_M (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S) -#define EFUSE_RD_RESERVE_0_79_V 0x00000001U -#define EFUSE_RD_RESERVE_0_79_S 15 -/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ - */ -#define EFUSE_WDT_DELAY_SEL 0x00000003U -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_S 16 -/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of - * 1: enabled\\ Even number of 1: disabled\\ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(15)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S 15 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [18:16]; default: 0; + * Represents whether SPI boot encryption/decryption is enabled. + * Odd count of bits with a value of 1: Enabled + * Even count of bits with a value of 1: Disabled */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 16 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [19]; default: 0; + * Represents whether revoking Secure Boot key digest 0 is enabled. + * 1: Enabled + * 0: Disabled */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(19)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 19 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [20]; default: 0; + * Represents whether revoking Secure Boot key digest 1 is enabled. + * 1: Enabled + * 0: Disabled */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(20)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 20 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [21]; default: 0; + * Represents whether revoking Secure Boot key digest 2 is enabled. + * 1: Enabled + * 0: Disabled */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 21 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [26:22]; default: 0; + * Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}. */ -#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0 0x0000001FU #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_S 24 -/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. +#define EFUSE_KEY_PURPOSE_0_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_0_S 22 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:27]; default: 0; + * Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}. */ -#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1 0x0000001FU #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_S 28 +#define EFUSE_KEY_PURPOSE_1_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_1_S 27 /** EFUSE_RD_REPEAT_DATA2_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [4:0]; default: 0; + * Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}. */ -#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2 0x0000001FU #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_V 0x0000001FU #define EFUSE_KEY_PURPOSE_2_S 0 -/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [9:5]; default: 0; + * Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}. */ -#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3 0x0000001FU #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_S 4 -/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. +#define EFUSE_KEY_PURPOSE_3_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_3_S 5 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [14:10]; default: 0; + * Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}. */ -#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4 0x0000001FU #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_S 8 -/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. +#define EFUSE_KEY_PURPOSE_4_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_4_S 10 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [19:15]; default: 0; + * Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}. */ -#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5 0x0000001FU #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_S 12 -/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. +#define EFUSE_KEY_PURPOSE_5_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_5_S 15 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [21:20]; default: 0; + * Represents the security level of anti-DPA attack. The level is adjusted by + * configuring the clock random frequency division mode. + * 0: Security level is SEC\_DPA\_OFF + * 1: Security level is SEC\_DPA\_LOW + * 2: Security level is SEC\_DPA\_MIDDLE + * 3: Security level is SEC\_DPA\_HIGH + * For more information, please refer to Chapter \ref{mod:sysreg} + * \textit{\nameref{mod:sysreg}} > Section + * \ref{sec:sysreg-anti-dpa-attack-security-control} + * \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. */ #define EFUSE_SEC_DPA_LEVEL 0x00000003U #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [19:18]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +#define EFUSE_SEC_DPA_LEVEL_S 20 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI : RO; bitpos: [24:22]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The high part of the field). */ -#define EFUSE_RD_RESERVE_0_114 0x00000003U -#define EFUSE_RD_RESERVE_0_114_M (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S) -#define EFUSE_RD_RESERVE_0_114_V 0x00000003U -#define EFUSE_RD_RESERVE_0_114_S 18 -/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_V 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_S 22 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [25]; default: 0; + * Represents whether Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ -#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN (BIT(25)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_S 20 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ +#define EFUSE_SECURE_BOOT_EN_S 25 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [26]; default: 0; + * Represents whether aggressive revocation of Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(26)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [26:22]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func - */ -#define EFUSE_RD_RESERVE_0_118 0x0000001FU -#define EFUSE_RD_RESERVE_0_118_M (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S) -#define EFUSE_RD_RESERVE_0_118_V 0x0000001FU -#define EFUSE_RD_RESERVE_0_118_S 22 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 26 /** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0; - * Set this bitto configure flash encryption use xts-128 key. else use xts-256 key. + * Represents which key flash encryption uses. + * 0: XTS-AES-256 key + * 1: XTS-AES-128 key */ #define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(27)) #define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) #define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U #define EFUSE_KM_XTS_KEY_LENGTH_256_S 27 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. + * Represents the flash waiting time after power-up. Measurement unit: ms. When the + * value is less than 15, the waiting time is the programmed value. Otherwise, the + * waiting time is a fixed value, i.e. 30 ms. */ #define EFUSE_FLASH_TPUW 0x0000000FU #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) @@ -497,167 +595,186 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether Download mode is disable or enable. 1. Disable + * 0: Enable. */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether direct boot mode is disabled or enabled. 1. Disable + * 0: Enable. */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable + * 0: Enable. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 /** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; - * Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ + * Represents whether the keys in the Key Manager are locked after deployment. + * 0: Not locked + * 1: Locked */ #define EFUSE_LOCK_KM_KEY (BIT(3)) #define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) #define EFUSE_LOCK_KM_KEY_V 0x00000001U #define EFUSE_LOCK_KM_KEY_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ - * 1: Disable\\ 0: Enable\\ + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * Disable + * 0: Enable. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: - * disabled\\ + * Represents whether security download is enabled. Only downloading into flash is + * supported. Reading/writing RAM or registers is not supported (i.e. stub download is + * not supported). + * 1: Enabled + * 0: Disabled */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable - * printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset - * at high level\\ 11: force disable printing\\ + * Represents the type of UART printing. + * 0: Force enable printing. + * 1: Enable printing when GPIO27 is reset at low level. + * 2: Enable printing when GPIO27 is reset at high level. + * 3: Force disable printing. */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot.\\ - * 1: forced\\ 0:not forced\\ + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: Forced. + * 0: Not forced. */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 8 -/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. +/** EFUSE_SECURE_VERSION : RO; bitpos: [17:9]; default: 0; + * Represents the app secure version used by ESP-IDF anti-rollback feature. */ -#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION 0x000001FFU #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_V 0x000001FFU #define EFUSE_SECURE_VERSION_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. + * 1: Disabled + * 0: Enabled */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 /** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Represents whether the hysteresis function of PAD0 – PAD27 is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_HYS_EN_PAD (BIT(26)) #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 26 /** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; - * Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: - * Moderate 1. Low\\ 0: Disabled\\ + * Represents the pseudo round level of XTS-AES anti-DPA attack. + * 0: Disabled + * 1: Low + * 2: Moderate + * 3: High */ #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) #define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 /** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0; - * Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: - * Disable.\\ + * Represents whether XTS-AES anti-DPA attack clock is enabled. + * 0: Disable + * 1: Enabled */ #define EFUSE_XTS_DPA_CLK_ENABLE (BIT(29)) #define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) #define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_S 29 -/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [31:30]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [31]; default: 0; + * Represents if the chip supports ECDSA P384 */ -#define EFUSE_RD_RESERVE_0_158 0x00000003U -#define EFUSE_RD_RESERVE_0_158_M (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S) -#define EFUSE_RD_RESERVE_0_158_V 0x00000003U -#define EFUSE_RD_RESERVE_0_158_S 30 +#define EFUSE_ECDSA_P384_ENABLE (BIT(31)) +#define EFUSE_ECDSA_P384_ENABLE_M (EFUSE_ECDSA_P384_ENABLE_V << EFUSE_ECDSA_P384_ENABLE_S) +#define EFUSE_ECDSA_P384_ENABLE_V 0x00000001U +#define EFUSE_ECDSA_P384_ENABLE_S 31 /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) /** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0; - * Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ - * Even of 1 is valid.\\ + * Represents whether the HUK generate mode is valid. + * Odd count of bits with a value of 1: Invalid + * Even count of bits with a value of 1: Valid */ #define EFUSE_HUK_GEN_STATE 0x000001FFU #define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) #define EFUSE_HUK_GEN_STATE_V 0x000001FFU #define EFUSE_HUK_GEN_STATE_S 0 /** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0; - * Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used. - * If this field contains Odd number bit '1': Enable 48MHz XTAL\\ Even number bit '1': - * Enable 40MHz XTAL. + * Determines the frequency of the XTAL clock alone in \textbf{SPI Boot} mode, or + * together with \hyperref[fielddesc:EFUSEXTAL48MSELMODE]{EFUSE\_XTAL\_48M\_SEL\_MODE} + * in \textbf{Joint Download Boot} mode. For more information, please refer to Chapter + * \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}. + * Odd count of bits with a value of 1: 48 MHz + * Even count of bits with a value of 1: 40 MHz */ #define EFUSE_XTAL_48M_SEL 0x00000007U #define EFUSE_XTAL_48M_SEL_M (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S) #define EFUSE_XTAL_48M_SEL_V 0x00000007U #define EFUSE_XTAL_48M_SEL_S 9 /** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0; - * Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: - * eFuse\\ 0: strapping-PAD-state. + * Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. + * For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 0: Strapping PAD state + * 1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse */ #define EFUSE_XTAL_48M_SEL_MODE (BIT(12)) #define EFUSE_XTAL_48M_SEL_MODE_M (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S) #define EFUSE_XTAL_48M_SEL_MODE_V 0x00000001U #define EFUSE_XTAL_48M_SEL_MODE_S 12 -/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [13]; default: 0; - * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. +/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [13]; default: 0; + * Represents whether to force ECC to use constant-time mode for point multiplication + * calculation. + * 0: Not force + * 1: Force */ -#define EFUSE_ECDSA_DISABLE_P192 (BIT(13)) -#define EFUSE_ECDSA_DISABLE_P192_M (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S) -#define EFUSE_ECDSA_DISABLE_P192_V 0x00000001U -#define EFUSE_ECDSA_DISABLE_P192_S 13 -/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [14]; default: 0; - * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. - * \\ 0: Disable. - */ -#define EFUSE_ECC_FORCE_CONST_TIME (BIT(14)) +#define EFUSE_ECC_FORCE_CONST_TIME (BIT(13)) #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_S 14 -/** EFUSE_RD_RESERVE_0_175 : RW; bitpos: [31:15]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +#define EFUSE_ECC_FORCE_CONST_TIME_S 13 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO : RO; bitpos: [22:14]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The low part of the field). */ -#define EFUSE_RD_RESERVE_0_175 0x0001FFFFU -#define EFUSE_RD_RESERVE_0_175_M (EFUSE_RD_RESERVE_0_175_V << EFUSE_RD_RESERVE_0_175_S) -#define EFUSE_RD_RESERVE_0_175_V 0x0001FFFFU -#define EFUSE_RD_RESERVE_0_175_S 15 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S 14 /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys @@ -692,193 +809,65 @@ extern "C" { /** EFUSE_RD_MAC_SYS2_REG register * Represents rd_mac_sys + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0; - * Minor chip version +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU -#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) -#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU -#define EFUSE_WAFER_VERSION_MINOR_S 0 -/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0; - * Minor chip version +#define EFUSE_MAC_RESERVED_0 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_S 0 +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U -#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) -#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U -#define EFUSE_WAFER_VERSION_MAJOR_S 4 -/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0; - * Disables check of wafer version major - */ -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6)) -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U -#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6 -/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; - * Disables check of blk version major - */ -#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) -#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) -#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U -#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 -/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0; - * BLK_VERSION_MINOR of BLOCK2 - */ -#define EFUSE_BLK_VERSION_MINOR 0x00000007U -#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) -#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U -#define EFUSE_BLK_VERSION_MINOR_S 8 -/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0; - * BLK_VERSION_MAJOR of BLOCK2 - */ -#define EFUSE_BLK_VERSION_MAJOR 0x00000003U -#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) -#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U -#define EFUSE_BLK_VERSION_MAJOR_S 11 -/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0; - * Flash capacity - */ -#define EFUSE_FLASH_CAP 0x00000007U -#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) -#define EFUSE_FLASH_CAP_V 0x00000007U -#define EFUSE_FLASH_CAP_S 13 -/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0; - * Flash vendor - */ -#define EFUSE_FLASH_VENDOR 0x00000007U -#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) -#define EFUSE_FLASH_VENDOR_V 0x00000007U -#define EFUSE_FLASH_VENDOR_S 16 -/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0; - * Psram capacity - */ -#define EFUSE_PSRAM_CAP 0x00000007U -#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) -#define EFUSE_PSRAM_CAP_V 0x00000007U -#define EFUSE_PSRAM_CAP_S 19 -/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0; - * Psram vendor - */ -#define EFUSE_PSRAM_VENDOR 0x00000003U -#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) -#define EFUSE_PSRAM_VENDOR_V 0x00000003U -#define EFUSE_PSRAM_VENDOR_S 22 -/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0; - * Temp (die embedded inside) - */ -#define EFUSE_TEMP 0x00000003U -#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S) -#define EFUSE_TEMP_V 0x00000003U -#define EFUSE_TEMP_S 24 -/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0; - * Package version - */ -#define EFUSE_PKG_VERSION 0x00000007U -#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) -#define EFUSE_PKG_VERSION_V 0x00000007U -#define EFUSE_PKG_VERSION_S 26 -/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0; - * PADC CAL PA trim version - */ -#define EFUSE_PA_TRIM_VERSION 0x00000007U -#define EFUSE_PA_TRIM_VERSION_M (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S) -#define EFUSE_PA_TRIM_VERSION_V 0x00000007U -#define EFUSE_PA_TRIM_VERSION_S 29 +#define EFUSE_MAC_RESERVED_1 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_S 14 /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0; - * PADC CAL N bias +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_TRIM_N_BIAS 0x0000001FU -#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S) -#define EFUSE_TRIM_N_BIAS_V 0x0000001FU -#define EFUSE_TRIM_N_BIAS_S 0 -/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0; - * PADC CAL P bias +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. */ -#define EFUSE_TRIM_P_BIAS 0x0000001FU -#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S) -#define EFUSE_TRIM_P_BIAS_V 0x0000001FU -#define EFUSE_TRIM_P_BIAS_S 5 -/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [13:10]; default: 0; - * Active HP DBIAS of fixed voltage - */ -#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU -#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) -#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU -#define EFUSE_ACTIVE_HP_DBIAS_S 10 -/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [17:14]; default: 0; - * Active LP DBIAS of fixed voltage - */ -#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU -#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) -#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU -#define EFUSE_ACTIVE_LP_DBIAS_S 14 -/** EFUSE_LSLP_HP_DBG : R; bitpos: [19:18]; default: 0; - * LSLP HP DBG of fixed voltage - */ -#define EFUSE_LSLP_HP_DBG 0x00000003U -#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S) -#define EFUSE_LSLP_HP_DBG_V 0x00000003U -#define EFUSE_LSLP_HP_DBG_S 18 -/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [23:20]; default: 0; - * LSLP HP DBIAS of fixed voltage - */ -#define EFUSE_LSLP_HP_DBIAS 0x0000000FU -#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S) -#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU -#define EFUSE_LSLP_HP_DBIAS_S 20 -/** EFUSE_DSLP_LP_DBG : R; bitpos: [27:24]; default: 0; - * DSLP LP DBG of fixed voltage - */ -#define EFUSE_DSLP_LP_DBG 0x0000000FU -#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S) -#define EFUSE_DSLP_LP_DBG_V 0x0000000FU -#define EFUSE_DSLP_LP_DBG_S 24 -/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [31:28]; default: 0; - * DSLP LP DBIAS of fixed voltage - */ -#define EFUSE_DSLP_LP_DBIAS 0x0000000FU -#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S) -#define EFUSE_DSLP_LP_DBIAS_V 0x0000000FU -#define EFUSE_DSLP_LP_DBIAS_S 28 +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_DSLP_LP_DBIAS_1 : R; bitpos: [0]; default: 0; - * DSLP LP DBIAS of fixed voltage +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. */ -#define EFUSE_DSLP_LP_DBIAS_1 (BIT(0)) -#define EFUSE_DSLP_LP_DBIAS_1_M (EFUSE_DSLP_LP_DBIAS_1_V << EFUSE_DSLP_LP_DBIAS_1_S) -#define EFUSE_DSLP_LP_DBIAS_1_V 0x00000001U -#define EFUSE_DSLP_LP_DBIAS_1_S 0 -/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [5:1]; default: 0; - * DBIAS gap between LP and HP - */ -#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU -#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S) -#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU -#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 1 -/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_1_134 0x03FFFFFFU -#define EFUSE_RESERVED_1_134_M (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S) -#define EFUSE_RESERVED_1_134_V 0x03FFFFFFU -#define EFUSE_RESERVED_1_134_S 6 +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 /** EFUSE_RD_MAC_SYS5_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) /** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. + * Represents the third 32-bit of zeroth part of system data. */ #define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) @@ -889,209 +878,97 @@ extern "C" { * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) -#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU -#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0; - * Temperature calibration data +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU -#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S) -#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU -#define EFUSE_TEMPERATURE_SENSOR_S 0 -/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0; - * ADC OCode - */ -#define EFUSE_OCODE 0x000000FFU -#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) -#define EFUSE_OCODE_V 0x000000FFU -#define EFUSE_OCODE_S 9 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0; - * Average initcode of ADC1 atten0 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0; - * Average initcode of ADC1 atten0 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27 +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0; - * Average initcode of ADC1 atten0 +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0; - * Average initcode of ADC1 atten0 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0; - * Average initcode of ADC1 atten0 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15 -/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0; - * HI DOUT of ADC1 atten0 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU -#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU -#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25 +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 /** EFUSE_RD_SYS_PART1_DATA6_REG register * Represents rd_sys_part1_data6 */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0; - * HI DOUT of ADC1 atten0 +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U -#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0 -/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0; - * HI DOUT of ADC1 atten1 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3 -/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0; - * HI DOUT of ADC1 atten2 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13 -/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0; - * HI DOUT of ADC1 atten3 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23 +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 /** EFUSE_RD_SYS_PART1_DATA7_REG register * Represents rd_sys_part1_data7 */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0; - * HI DOUT of ADC1 atten3 +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0)) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U -#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0 -/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0; - * Gap between ADC1 CH0 and average initcode - */ -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1 -/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0; - * Gap between ADC1 CH1 and average initcode - */ -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5 -/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0; - * Gap between ADC1 CH2 and average initcode - */ -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9 -/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0; - * Gap between ADC1 CH3 and average initcode - */ -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13 -/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0; - * Gap between ADC1 CH4 and average initcode - */ -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17 -/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [24:21]; default: 0; - * Gap between ADC1 CH5 and average initcode - */ -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 21 -/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_2_249 0x0000007FU -#define EFUSE_RESERVED_2_249_M (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S) -#define EFUSE_RESERVED_2_249_V 0x0000007FU -#define EFUSE_RESERVED_2_249_S 25 +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 /** EFUSE_RD_USR_DATA0_REG register * Represents rd_usr_data0 @@ -1169,39 +1046,25 @@ extern "C" { * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; - * reserved +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). */ -#define EFUSE_RESERVED_3_192 0x000000FFU -#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) -#define EFUSE_RESERVED_3_192_V 0x000000FFU -#define EFUSE_RESERVED_3_192_S 0 -/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; - * Custom MAC - */ -#define EFUSE_CUSTOM_MAC 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) -#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_S 8 +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 /** EFUSE_RD_USR_DATA7_REG register * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; - * Custom MAC +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). */ -#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) -#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU -#define EFUSE_CUSTOM_MAC_1_S 0 -/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_3_248 0x000000FFU -#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) -#define EFUSE_RESERVED_3_248_V 0x000000FFU -#define EFUSE_RESERVED_3_248_S 24 +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 /** EFUSE_RD_KEY0_DATA0_REG register * Represents rd_key0_data0 @@ -1886,6 +1749,13 @@ extern "C" { #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) #define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR (BIT(7)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_S 7 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; * Represents the programming error of EFUSE_DIS_ICACHE */ @@ -1900,8 +1770,16 @@ extern "C" { #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR (BIT(10)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) @@ -1958,6 +1836,7 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 /** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; * Represents the programming error of EFUSE_USB_DREFH + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_USB_DREFH_ERR 0x00000003U #define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) @@ -1965,6 +1844,7 @@ extern "C" { #define EFUSE_USB_DREFH_ERR_S 21 /** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; * Represents the programming error of EFUSE_USB_DREFL + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_USB_DREFL_ERR 0x00000003U #define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) @@ -1984,6 +1864,21 @@ extern "C" { #define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) #define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 27 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR : RO; bitpos: [31:29]; + * default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_V 0x00000007U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_S 29 /** EFUSE_RD_REPEAT_DATA_ERR1_REG register * Represents rd_repeat_data_err @@ -2024,109 +1919,116 @@ extern "C" { #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 14 -/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM */ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 -/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR (BIT(15)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S 15 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [18:16]; default: 0; * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 16 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [19]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(19)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 19 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [20]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 20 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [21]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 21 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [26:22]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000001FU #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 -/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 22 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:27]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000001FU #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 27 /** EFUSE_RD_REPEAT_DATA_ERR2_REG register * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [4:0]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000001FU #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000001FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 -/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [9:5]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000001FU #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 -/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 5 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [14:10]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000001FU #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 -/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 10 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [19:15]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000001FU #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 -/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000001FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 15 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [21:20]; default: 0; * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; +#define EFUSE_SEC_DPA_LEVEL_ERR_S 20 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR : RO; bitpos: [24:22]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_V 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_S 22 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [25]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_EN */ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(25)) #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; +#define EFUSE_SECURE_BOOT_EN_ERR_S 25 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [26]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(26)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 26 /** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0; * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 */ @@ -2202,12 +2104,12 @@ extern "C" { #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 -/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [17:9]; default: 0; * Represents the programming error of EFUSE_SECURE_VERSION */ -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR 0x000001FFU #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_V 0x000001FFU #define EFUSE_SECURE_VERSION_ERR_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE @@ -2237,6 +2139,13 @@ extern "C" { #define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S) #define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S 29 +/** EFUSE_ECDSA_P384_ENABLE_ERR : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_ECDSA_P384_ENABLE + */ +#define EFUSE_ECDSA_P384_ENABLE_ERR (BIT(31)) +#define EFUSE_ECDSA_P384_ENABLE_ERR_M (EFUSE_ECDSA_P384_ENABLE_ERR_V << EFUSE_ECDSA_P384_ENABLE_ERR_S) +#define EFUSE_ECDSA_P384_ENABLE_ERR_V 0x00000001U +#define EFUSE_ECDSA_P384_ENABLE_ERR_S 31 /** EFUSE_RD_REPEAT_DATA_ERR4_REG register * Represents rd_repeat_data_err @@ -2263,156 +2172,163 @@ extern "C" { #define EFUSE_XTAL_48M_SEL_MODE_ERR_M (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S) #define EFUSE_XTAL_48M_SEL_MODE_ERR_V 0x00000001U #define EFUSE_XTAL_48M_SEL_MODE_ERR_S 12 -/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_ECDSA_DISABLE_P192 - */ -#define EFUSE_ECDSA_DISABLE_P192_ERR (BIT(13)) -#define EFUSE_ECDSA_DISABLE_P192_ERR_M (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S) -#define EFUSE_ECDSA_DISABLE_P192_ERR_V 0x00000001U -#define EFUSE_ECDSA_DISABLE_P192_ERR_S 13 -/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [14]; default: 0; +/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [13]; default: 0; * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ -#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(14)) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(13)) #define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) #define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 14 +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 13 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR : RO; bitpos: [22:14]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_V 0x000001FFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_S 14 /** EFUSE_RD_RS_DATA_ERR0_REG register * Represents rd_rs_data_err */ #define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) /** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_mac_sys + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys */ #define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) #define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 /** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number - * of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. */ #define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) #define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) #define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U #define EFUSE_RD_MAC_SYS_FAIL_S 3 /** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 /** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ #define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) #define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) #define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 /** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_usr_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data */ #define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) #define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_S 8 /** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_USR_DATA_FAIL (BIT(11)) #define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) #define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U #define EFUSE_RD_USR_DATA_FAIL_S 11 /** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key0_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data */ #define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) #define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 /** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) #define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) #define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY0_DATA_FAIL_S 15 /** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data */ #define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) #define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 /** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) #define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) #define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY1_DATA_FAIL_S 19 /** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data */ #define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) #define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 /** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) #define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) #define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY2_DATA_FAIL_S 23 /** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key3_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data */ #define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) #define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 /** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) #define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) #define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY3_DATA_FAIL_S 27 /** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key4_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data */ #define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) #define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 /** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) #define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) @@ -2424,34 +2340,36 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) /** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key5_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data */ #define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) #define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 /** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) #define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) #define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY5_DATA_FAIL_S 3 /** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 /** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. */ #define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) #define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) @@ -2462,8 +2380,9 @@ extern "C" { * eFuse version register. */ #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37752960; - * Stores eFuse version. +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37818960; + * Represents eFuse version. Date:2024-12-19 16:08:23, + * ScriptRev:5b7d298cf2df9f93b161800aff1807aeadbb74f4 */ #define EFUSE_DATE 0x0FFFFFFFU #define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) @@ -2475,28 +2394,36 @@ extern "C" { */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2508,109 +2435,172 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) #define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. + +/** EFUSE_ECDSA_REG register + * eFuse status register. */ -#define EFUSE_CFG_ECDSA_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) -#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_S 16 +#define EFUSE_ECDSA_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_CFG_ECDSA_P192_BLK : R/W; bitpos: [3:0]; default: 0; + * Configures which block to use for ECDSA P192 key output. + */ +#define EFUSE_CFG_ECDSA_P192_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P192_BLK_M (EFUSE_CFG_ECDSA_P192_BLK_V << EFUSE_CFG_ECDSA_P192_BLK_S) +#define EFUSE_CFG_ECDSA_P192_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P192_BLK_S 0 +/** EFUSE_CFG_ECDSA_P256_BLK : R/W; bitpos: [7:4]; default: 0; + * Configures which block to use for ECDSA P256 key output. + */ +#define EFUSE_CFG_ECDSA_P256_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P256_BLK_M (EFUSE_CFG_ECDSA_P256_BLK_V << EFUSE_CFG_ECDSA_P256_BLK_S) +#define EFUSE_CFG_ECDSA_P256_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P256_BLK_S 4 +/** EFUSE_CFG_ECDSA_P384_L_BLK : R/W; bitpos: [11:8]; default: 0; + * Configures which block to use for ECDSA P384 key low part output. + */ +#define EFUSE_CFG_ECDSA_P384_L_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_L_BLK_M (EFUSE_CFG_ECDSA_P384_L_BLK_V << EFUSE_CFG_ECDSA_P384_L_BLK_S) +#define EFUSE_CFG_ECDSA_P384_L_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_L_BLK_S 8 +/** EFUSE_CFG_ECDSA_P384_H_BLK : R/W; bitpos: [15:12]; default: 0; + * Configures which block to use for ECDSA P256 key high part output. + */ +#define EFUSE_CFG_ECDSA_P384_H_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_H_BLK_M (EFUSE_CFG_ECDSA_P384_H_BLK_V << EFUSE_CFG_ECDSA_P384_H_BLK_S) +#define EFUSE_CFG_ECDSA_P384_H_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_H_BLK_S 12 +/** EFUSE_CUR_ECDSA_P192_BLK : RO; bitpos: [19:16]; default: 0; + * Represents which block is used for ECDSA P192 key output. + */ +#define EFUSE_CUR_ECDSA_P192_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P192_BLK_M (EFUSE_CUR_ECDSA_P192_BLK_V << EFUSE_CUR_ECDSA_P192_BLK_S) +#define EFUSE_CUR_ECDSA_P192_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P192_BLK_S 16 +/** EFUSE_CUR_ECDSA_P256_BLK : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA P256 key output. + */ +#define EFUSE_CUR_ECDSA_P256_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P256_BLK_M (EFUSE_CUR_ECDSA_P256_BLK_V << EFUSE_CUR_ECDSA_P256_BLK_S) +#define EFUSE_CUR_ECDSA_P256_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P256_BLK_S 20 +/** EFUSE_CUR_ECDSA_P384_L_BLK : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA P384 key low part output. + */ +#define EFUSE_CUR_ECDSA_P384_L_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_L_BLK_M (EFUSE_CUR_ECDSA_P384_L_BLK_V << EFUSE_CUR_ECDSA_P384_L_BLK_S) +#define EFUSE_CUR_ECDSA_P384_L_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_L_BLK_S 24 +/** EFUSE_CUR_ECDSA_P384_H_BLK : RO; bitpos: [31:28]; default: 0; + * Represents which block is used for ECDSA P384 key high part output. + */ +#define EFUSE_CUR_ECDSA_P384_H_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_H_BLK_M (EFUSE_CUR_ECDSA_P384_H_BLK_V << EFUSE_CUR_ECDSA_P384_H_BLK_S) +#define EFUSE_CUR_ECDSA_P384_H_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_H_BLK_S 28 /** EFUSE_STATUS_REG register * eFuse status register. */ -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) #define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 /** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. + * Represents the value of OTP_LOAD_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_LOAD_SW (BIT(4)) #define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) #define EFUSE_OTP_LOAD_SW_V 0x00000001U #define EFUSE_OTP_LOAD_SW_S 4 /** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. + * Represents the value of OTP_VDDQ_C_SYNC2. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) #define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) #define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U #define EFUSE_OTP_VDDQ_C_SYNC2_S 5 /** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. + * Represents the value of OTP_STROBE_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_STROBE_SW (BIT(6)) #define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) #define EFUSE_OTP_STROBE_SW_V 0x00000001U #define EFUSE_OTP_STROBE_SW_S 6 /** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. + * Represents the value of OTP_CSB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_CSB_SW (BIT(7)) #define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) #define EFUSE_OTP_CSB_SW_V 0x00000001U #define EFUSE_OTP_CSB_SW_S 7 /** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. + * Represents the value of OTP_PGENB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_PGENB_SW (BIT(8)) #define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) #define EFUSE_OTP_PGENB_SW_V 0x00000001U #define EFUSE_OTP_PGENB_SW_S 8 /** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. + * Represents the value of OTP_VDDQ_IS_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) #define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) #define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U #define EFUSE_OTP_VDDQ_IS_SW_S 9 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. + * Represents the number of block valid bit. */ #define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) #define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. - */ -#define EFUSE_CUR_ECDSA_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) -#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_S 20 /** EFUSE_CMD_REG register * eFuse command register. */ -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d8) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. + * Configures whether to send read commands. + * 1: Send + * 0: No effect */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. + * Configures whether to send programming commands. + * 1: Send + * 0: No effect */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) #define EFUSE_PGM_CMD_V 0x00000001U #define EFUSE_PGM_CMD_S 1 /** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. + * Configures the serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. */ #define EFUSE_BLK_NUM 0x0000000FU #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) @@ -2620,16 +2610,16 @@ extern "C" { /** EFUSE_INT_RAW_REG register * eFuse raw interrupt register. */ -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1dc) /** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. + * The raw interrupt status of EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 /** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. + * The raw interrupt status of EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) @@ -2639,16 +2629,16 @@ extern "C" { /** EFUSE_INT_ST_REG register * eFuse interrupt status register. */ -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1e0) /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. + * The masked interrupt status of EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) #define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. + * The masked interrupt status of EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_ST (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) @@ -2658,16 +2648,16 @@ extern "C" { /** EFUSE_INT_ENA_REG register * eFuse interrupt enable register. */ -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e4) /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. + * Write 1 to enable EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. + * Write 1 to enable EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) @@ -2677,16 +2667,16 @@ extern "C" { /** EFUSE_INT_CLR_REG register * eFuse interrupt clear register. */ -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e8) /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. + * Write 1 to clear EFUSE_READ_DONE_INT. */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 /** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. + * Write 1 to clear EFUSE_PGM_DONE_INT. */ #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) @@ -2696,9 +2686,9 @@ extern "C" { /** EFUSE_DAC_CONF_REG register * Controls the eFuse programming voltage. */ -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 19; + * Configures the division factor of the rising clock of the programming voltage. */ #define EFUSE_DAC_CLK_DIV 0x000000FFU #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) @@ -2712,14 +2702,17 @@ extern "C" { #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U #define EFUSE_DAC_CLK_PAD_SEL_S 8 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. + * Configures clock cycles for programming voltage to rise. Measurement unit: a clock + * cycle divided by EFUSE_DAC_CLK_DIV. */ #define EFUSE_DAC_NUM 0x000000FFU #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -2729,30 +2722,31 @@ extern "C" { /** EFUSE_RD_TIM_CONF_REG register * Configures read timing parameters. */ -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1f0) /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. + * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. */ #define EFUSE_THR_A 0x000000FFU #define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) #define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 /** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. + * Configures the read time. Measurement unit: One cycle of the eFuse core clock. */ #define EFUSE_TRD 0x000000FFU #define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) #define EFUSE_TRD_V 0x000000FFU #define EFUSE_TRD_S 8 /** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. + * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. */ #define EFUSE_TSUR_A 0x000000FFU #define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) #define EFUSE_TSUR_A_V 0x000000FFU #define EFUSE_TSUR_A_S 16 -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 22; - * Configures the waiting time of reading eFuse memory. +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of + * the eFuse core clock. */ #define EFUSE_READ_INIT_NUM 0x000000FFU #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) @@ -2762,23 +2756,26 @@ extern "C" { /** EFUSE_WR_TIM_CONF1_REG register * Configurarion register 1 of eFuse programming timing parameters. */ -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. + * Configures the programming setup time. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_TSUP_A 0x000000FFU #define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) #define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 -/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288; - * Configures the power up time for VDDQ. +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_PWR_ON_NUM 0x0000FFFFU #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 /** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. + * Configures the programming hold time. Measurement unit: One cycle of the eFuse core + * clock. */ #define EFUSE_THP_A 0x000000FFU #define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) @@ -2788,16 +2785,18 @@ extern "C" { /** EFUSE_WR_TIM_CONF2_REG register * Configurarion register 2 of eFuse programming timing parameters. */ -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) -/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_PWR_OFF_NUM 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 -/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; - * Configures the active programming time. +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_TPGM 0x0000FFFFU #define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) @@ -2808,30 +2807,35 @@ extern "C" { * Configurarion register0 of eFuse programming time parameters and rs bypass * operation. */ -#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1fc) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) #define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U #define EFUSE_BYPASS_RS_CORRECTION_S 0 /** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. + * Configures which block number to bypass the Reed-Solomon (RS) correction step. */ #define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) #define EFUSE_UPDATE_V 0x00000001U #define EFUSE_UPDATE_S 12 /** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. + * Configures the inactive programming time. Measurement unit: One cycle of the eFuse + * core clock. */ #define EFUSE_TPGM_INACTIVE 0x000000FFU #define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) diff --git a/components/soc/esp32c5/register/soc/efuse_reg_eco2.h b/components/soc/esp32c5/register/soc/efuse_reg_eco2.h deleted file mode 100644 index ec17a5b29a..0000000000 --- a/components/soc/esp32c5/register/soc/efuse_reg_eco2.h +++ /dev/null @@ -1,4407 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** EFUSE_PGM_DATA0_REG register - * Represents pgm_data0 - */ -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) -/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_0 0xFFFFFFFFU -#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_0_S 0 - -/** EFUSE_PGM_DATA1_REG register - * Represents pgm_data1 - */ -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_1 0xFFFFFFFFU -#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_1_S 0 - -/** EFUSE_PGM_DATA2_REG register - * Represents pgm_data2 - */ -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) -/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_2 0xFFFFFFFFU -#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_2_S 0 - -/** EFUSE_PGM_DATA3_REG register - * Represents pgm_data3 - */ -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) -/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_3 0xFFFFFFFFU -#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_3_S 0 - -/** EFUSE_PGM_DATA4_REG register - * Represents pgm_data4 - */ -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) -/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_4 0xFFFFFFFFU -#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_4_S 0 - -/** EFUSE_PGM_DATA5_REG register - * Represents pgm_data5 - */ -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) -/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_5 0xFFFFFFFFU -#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_5_S 0 - -/** EFUSE_PGM_DATA6_REG register - * Represents pgm_data6 - */ -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) -/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_6 0xFFFFFFFFU -#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_6_S 0 - -/** EFUSE_PGM_DATA7_REG register - * Represents pgm_data7 - */ -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) -/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. - */ -#define EFUSE_PGM_DATA_7 0xFFFFFFFFU -#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU -#define EFUSE_PGM_DATA_7_S 0 - -/** EFUSE_PGM_CHECK_VALUE0_REG register - * Represents pgm_check_value0 - */ -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) -/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_0_S 0 - -/** EFUSE_PGM_CHECK_VALUE1_REG register - * Represents pgm_check_value1 - */ -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) -/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_1_S 0 - -/** EFUSE_PGM_CHECK_VALUE2_REG register - * Represents pgm_check_value2 - */ -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) -/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th RS code to be programmed. - */ -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU -#define EFUSE_PGM_RS_DATA_2_S 0 - -/** EFUSE_RD_WR_DIS_REG register - * Represents rd_wr_dis - */ -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) -/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled. For - * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_WR_DIS 0xFFFFFFFFU -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xFFFFFFFFU -#define EFUSE_WR_DIS_S 0 - -/** EFUSE_RD_REPEAT_DATA0_REG register - * Represents rd_repeat_data - */ -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block (BLOCK4 \verb+~+ BLOCK10) is - * disabled. For mapping between the bits of this field and the eFuse blocks, please - * refer to Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_RD_DIS 0x0000007FU -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007FU -#define EFUSE_RD_DIS_S 0 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI : RO; bitpos: [7]; default: 0; - * Represents the anti-rollback secure version of the 2nd stage bootloader used by the - * ROM bootloader (the high part of the field). - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI (BIT(7)) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_V 0x00000001U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_S 7 -/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Represents whether cache is disabled. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) -#define EFUSE_DIS_ICACHE_V 0x00000001U -#define EFUSE_DIS_ICACHE_S 8 -/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note - * that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only - * when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is - * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} - * \textit{\nameref{mod:bootctrl}}. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_DIS_USB_JTAG (BIT(9)) -#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) -#define EFUSE_DIS_USB_JTAG_V 0x00000001U -#define EFUSE_DIS_USB_JTAG_S 9 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [10]; default: 0; - * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(10)) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V 0x00000001U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 10 -/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; - * Represents whether USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled - * - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 -/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 -/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot\_mode\_download is disabled. - * 0: Enabled - * 1: Disabled - */ -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 -/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI$^®$ function is disabled. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_DIS_TWAI (BIT(14)) -#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) -#define EFUSE_DIS_TWAI_V 0x00000001U -#define EFUSE_DIS_TWAI_S 14 -/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Represents whether the selection of a JTAG signal source through the strapping pin - * value is enabled when all of - * \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}, - * \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and - * \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are - * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} - * \textit{\nameref{mod:bootctrl}}. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) -#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U -#define EFUSE_JTAG_SEL_ENABLE_S 15 -/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled - */ -#define EFUSE_SOFT_DIS_JTAG 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) -#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_S 16 -/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) -#define EFUSE_DIS_PAD_JTAG_V 0x00000001U -#define EFUSE_DIS_PAD_JTAG_S 19 -/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_USB_DREFH 0x00000003U -#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) -#define EFUSE_USB_DREFH_V 0x00000003U -#define EFUSE_USB_DREFH_S 21 -/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_USB_DREFL 0x00000003U -#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) -#define EFUSE_USB_DREFL_V 0x00000003U -#define EFUSE_USB_DREFL_S 23 -/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged - */ -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) -#define EFUSE_USB_EXCHG_PINS_V 0x00000001U -#define EFUSE_USB_EXCHG_PINS_S 25 -/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * Represents whether VDD SPI pin is functioned as GPIO. - * 1: Functioned - * 0: Not functioned - */ -#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) -#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U -#define EFUSE_VDD_SPI_AS_GPIO_S 26 -/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [28:27]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0: The originally configured STG0 threshold × 2 - * 1: The originally configured STG0 threshold × 4 - * 2: The originally configured STG0 threshold × 8 - * 3: The originally configured STG0 threshold × 16 - */ -#define EFUSE_WDT_DELAY_SEL 0x00000003U -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_S 27 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO : RO; bitpos: [31:29]; default: 0; - * Represents the anti-rollback secure version of the 2nd stage bootloader used by the - * ROM bootloader (the low part of the field). - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO 0x00000007U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_V 0x00000007U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_S 29 - -/** EFUSE_RD_REPEAT_DATA1_REG register - * Represents rd_repeat_data - */ -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0; - * Represents whether the new key deployment of key manager is disabled. - * Bit0: Represents whether the new ECDSA key deployment is disabled - * 0: Enabled - * 1: Disabled - * Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is - * disabled - * 0: Enabled - * 1: Disabled - * Bit2: Represents whether the new HMAC key deployment is disabled - * 0: Enabled - * 1: Disabled - * Bit3: Represents whether the new DS key deployment is disabled - * 0: Enabled - * 1: Disabled - */ -#define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 0 -/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0; - * Represents the cycle at which the Key Manager switches random numbers. - * 0: Controlled by the - * \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For - * more information, please refer to Chapter \ref{mod:keymng} - * \textit{\nameref{mod:keymng}} - * 1: 8 Key Manager clock cycles - * 2: 16 Key Manager clock cycles - * 3: 32 Key Manager clock cycles - */ -#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) -#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_S 4 -/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0; - * Represents whether the corresponding key can be deployed only once. - * Bit0: Represents whether the ECDSA key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - * Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - * Bit2: Represents whether the HMAC key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - * Bit3: Represents whether the DS key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - */ -#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) -#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 6 -/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0; - * Represents whether the corresponding key must come from Key Manager. - * Bit0: Represents whether the ECDSA key must come from Key Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - * Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key - * Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - * Bit2: Represents whether the HMAC key must come from Key Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - * Bit3: Represents whether the DS key must come from Key Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - */ -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 10 -/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0; - * Represents whether to disable the use of the initialization key written by software - * and instead force use efuse\_init\_key. - * 0: Enable - * 1: Disable - */ -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(14)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [15]; default: 0; - * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM - * bootloader. - * 1: Enable - * 0: Disable - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(15)) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V 0x00000001U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S 15 -/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [18:16]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled - */ -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 16 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [19]; default: 0; - * Represents whether revoking Secure Boot key digest 0 is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(19)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 19 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [20]; default: 0; - * Represents whether revoking Secure Boot key digest 1 is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(20)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 20 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key digest 2 is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 21 -/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [26:22]; default: 0; - * Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}. - */ -#define EFUSE_KEY_PURPOSE_0 0x0000001FU -#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_0_S 22 -/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:27]; default: 0; - * Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}. - */ -#define EFUSE_KEY_PURPOSE_1 0x0000001FU -#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_1_S 27 - -/** EFUSE_RD_REPEAT_DATA2_REG register - * Represents rd_repeat_data - */ -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) -/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [4:0]; default: 0; - * Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}. - */ -#define EFUSE_KEY_PURPOSE_2 0x0000001FU -#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_2_S 0 -/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [9:5]; default: 0; - * Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}. - */ -#define EFUSE_KEY_PURPOSE_3 0x0000001FU -#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_3_S 5 -/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [14:10]; default: 0; - * Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}. - */ -#define EFUSE_KEY_PURPOSE_4 0x0000001FU -#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_4_S 10 -/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [19:15]; default: 0; - * Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}. - */ -#define EFUSE_KEY_PURPOSE_5 0x0000001FU -#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_5_S 15 -/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [21:20]; default: 0; - * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC\_DPA\_OFF - * 1: Security level is SEC\_DPA\_LOW - * 2: Security level is SEC\_DPA\_MIDDLE - * 3: Security level is SEC\_DPA\_HIGH - * For more information, please refer to Chapter \ref{mod:sysreg} - * \textit{\nameref{mod:sysreg}} > Section - * \ref{sec:sysreg-anti-dpa-attack-security-control} - * \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. - */ -#define EFUSE_SEC_DPA_LEVEL 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) -#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_S 20 -/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI : RO; bitpos: [24:22]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. (The high part of the field). - */ -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI 0x00000007U -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_S) -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_V 0x00000007U -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_S 22 -/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [25]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_SECURE_BOOT_EN (BIT(25)) -#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) -#define EFUSE_SECURE_BOOT_EN_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_S 25 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [26]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(26)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 26 -/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0; - * Represents which key flash encryption uses. - * 0: XTS-AES-256 key - * 1: XTS-AES-128 key - */ -#define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(27)) -#define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) -#define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U -#define EFUSE_KM_XTS_KEY_LENGTH_256_S 27 -/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. When the - * value is less than 15, the waiting time is the programmed value. Otherwise, the - * waiting time is a fixed value, i.e. 30 ms. - */ -#define EFUSE_FLASH_TPUW 0x0000000FU -#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) -#define EFUSE_FLASH_TPUW_V 0x0000000FU -#define EFUSE_FLASH_TPUW_S 28 - -/** EFUSE_RD_REPEAT_DATA3_REG register - * Represents rd_repeat_data - */ -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) -/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disable or enable. 1. Disable - * 0: Enable. - */ -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 -/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1. Disable - * 0: Enable. - */ -#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) -#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U -#define EFUSE_DIS_DIRECT_BOOT_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable - * 0: Enable. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 -/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; - * Represents whether the keys in the Key Manager are locked after deployment. - * 0: Not locked - * 1: Locked - */ -#define EFUSE_LOCK_KM_KEY (BIT(3)) -#define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) -#define EFUSE_LOCK_KM_KEY_V 0x00000001U -#define EFUSE_LOCK_KM_KEY_S 3 -/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * Disable - * 0: Enable. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 -/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled. Only downloading into flash is - * supported. Reading/writing RAM or registers is not supported (i.e. stub download is - * not supported). - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO27 is reset at low level. - * 2: Enable printing when GPIO27 is reset at high level. - * 3: Force disable printing. - */ -#define EFUSE_UART_PRINT_CONTROL 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) -#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_S 6 -/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced. - * 0: Not forced. - */ -#define EFUSE_FORCE_SEND_RESUME (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) -#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U -#define EFUSE_FORCE_SEND_RESUME_S 8 -/** EFUSE_SECURE_VERSION : RO; bitpos: [17:9]; default: 0; - * Represents the app secure version used by ESP-IDF anti-rollback feature. - */ -#define EFUSE_SECURE_VERSION 0x000001FFU -#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x000001FFU -#define EFUSE_SECURE_VERSION_S 9 -/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled - */ -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 -/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of PAD0 – PAD27 is enabled. - * 1: Enabled - * 0: Disabled - */ -#define EFUSE_HYS_EN_PAD (BIT(26)) -#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) -#define EFUSE_HYS_EN_PAD_V 0x00000001U -#define EFUSE_HYS_EN_PAD_S 26 -/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; - * Represents the pseudo round level of XTS-AES anti-DPA attack. - * 0: Disabled - * 1: Low - * 2: Moderate - * 3: High - */ -#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 -/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0; - * Represents whether XTS-AES anti-DPA attack clock is enabled. - * 0: Disable - * 1: Enabled - */ -#define EFUSE_XTS_DPA_CLK_ENABLE (BIT(29)) -#define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) -#define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U -#define EFUSE_XTS_DPA_CLK_ENABLE_S 29 -/** EFUSE_ECDSA_P384_ENABLE : RO; bitpos: [31]; default: 0; - * Represents if the chip supports ECDSA P384 - */ -#define EFUSE_ECDSA_P384_ENABLE (BIT(31)) -#define EFUSE_ECDSA_P384_ENABLE_M (EFUSE_ECDSA_P384_ENABLE_V << EFUSE_ECDSA_P384_ENABLE_S) -#define EFUSE_ECDSA_P384_ENABLE_V 0x00000001U -#define EFUSE_ECDSA_P384_ENABLE_S 31 - -/** EFUSE_RD_REPEAT_DATA4_REG register - * Represents rd_repeat_data - */ -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0; - * Represents whether the HUK generate mode is valid. - * Odd count of bits with a value of 1: Invalid - * Even count of bits with a value of 1: Valid - */ -#define EFUSE_HUK_GEN_STATE 0x000001FFU -#define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) -#define EFUSE_HUK_GEN_STATE_V 0x000001FFU -#define EFUSE_HUK_GEN_STATE_S 0 -/** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0; - * Determines the frequency of the XTAL clock alone in \textbf{SPI Boot} mode, or - * together with \hyperref[fielddesc:EFUSEXTAL48MSELMODE]{EFUSE\_XTAL\_48M\_SEL\_MODE} - * in \textbf{Joint Download Boot} mode. For more information, please refer to Chapter - * \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}. - * Odd count of bits with a value of 1: 48 MHz - * Even count of bits with a value of 1: 40 MHz - */ -#define EFUSE_XTAL_48M_SEL 0x00000007U -#define EFUSE_XTAL_48M_SEL_M (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S) -#define EFUSE_XTAL_48M_SEL_V 0x00000007U -#define EFUSE_XTAL_48M_SEL_S 9 -/** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0; - * Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. - * For more information, please refer to Chapter \ref{mod:bootctrl} - * \textit{\nameref{mod:bootctrl}}. - * 0: Strapping PAD state - * 1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse - */ -#define EFUSE_XTAL_48M_SEL_MODE (BIT(12)) -#define EFUSE_XTAL_48M_SEL_MODE_M (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S) -#define EFUSE_XTAL_48M_SEL_MODE_V 0x00000001U -#define EFUSE_XTAL_48M_SEL_MODE_S 12 -/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [13]; default: 0; - * Represents whether to force ECC to use constant-time mode for point multiplication - * calculation. - * 0: Not force - * 1: Force - */ -#define EFUSE_ECC_FORCE_CONST_TIME (BIT(13)) -#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) -#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_S 13 -/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO : RO; bitpos: [22:14]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. (The low part of the field). - */ -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO 0x000001FFU -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S) -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_V 0x000001FFU -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_S 14 - -/** EFUSE_RD_MAC_SYS0_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) -/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. - */ -#define EFUSE_MAC_0 0xFFFFFFFFU -#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) -#define EFUSE_MAC_0_V 0xFFFFFFFFU -#define EFUSE_MAC_0_S 0 - -/** EFUSE_RD_MAC_SYS1_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) -/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. - */ -#define EFUSE_MAC_1 0x0000FFFFU -#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) -#define EFUSE_MAC_1_V 0x0000FFFFU -#define EFUSE_MAC_1_S 0 -/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. - */ -#define EFUSE_MAC_EXT 0x0000FFFFU -#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) -#define EFUSE_MAC_EXT_V 0x0000FFFFU -#define EFUSE_MAC_EXT_S 16 - -/** EFUSE_RD_MAC_SYS2_REG register - * Represents rd_mac_sys - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_MAC_RESERVED_0 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_S 0 -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_MAC_RESERVED_1 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_S 14 - -/** EFUSE_RD_MAC_SYS3_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 - -/** EFUSE_RD_MAC_SYS4_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_1_S 0 - -/** EFUSE_RD_MAC_SYS5_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 0 - -/** EFUSE_RD_SYS_PART1_DATA0_REG register - * Represents rd_sys_part1_data0 - */ -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 - -/** EFUSE_RD_SYS_PART1_DATA1_REG register - * Represents rd_sys_part1_data1 - */ -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 - -/** EFUSE_RD_SYS_PART1_DATA2_REG register - * Represents rd_sys_part1_data2 - */ -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 - -/** EFUSE_RD_SYS_PART1_DATA3_REG register - * Represents rd_sys_part1_data3 - */ -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 - -/** EFUSE_RD_SYS_PART1_DATA4_REG register - * Represents rd_sys_part1_data4 - */ -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 - -/** EFUSE_RD_SYS_PART1_DATA5_REG register - * Represents rd_sys_part1_data5 - */ -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_S 0 - -/** EFUSE_RD_SYS_PART1_DATA6_REG register - * Represents rd_sys_part1_data6 - */ -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_S 0 - -/** EFUSE_RD_SYS_PART1_DATA7_REG register - * Represents rd_sys_part1_data7 - */ -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_S 0 - -/** EFUSE_RD_USR_DATA0_REG register - * Represents rd_usr_data0 - */ -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) -/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA0 0xFFFFFFFFU -#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) -#define EFUSE_USR_DATA0_V 0xFFFFFFFFU -#define EFUSE_USR_DATA0_S 0 - -/** EFUSE_RD_USR_DATA1_REG register - * Represents rd_usr_data1 - */ -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) -/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA1 0xFFFFFFFFU -#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) -#define EFUSE_USR_DATA1_V 0xFFFFFFFFU -#define EFUSE_USR_DATA1_S 0 - -/** EFUSE_RD_USR_DATA2_REG register - * Represents rd_usr_data2 - */ -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) -/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA2 0xFFFFFFFFU -#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) -#define EFUSE_USR_DATA2_V 0xFFFFFFFFU -#define EFUSE_USR_DATA2_S 0 - -/** EFUSE_RD_USR_DATA3_REG register - * Represents rd_usr_data3 - */ -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) -/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA3 0xFFFFFFFFU -#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) -#define EFUSE_USR_DATA3_V 0xFFFFFFFFU -#define EFUSE_USR_DATA3_S 0 - -/** EFUSE_RD_USR_DATA4_REG register - * Represents rd_usr_data4 - */ -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) -/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA4 0xFFFFFFFFU -#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) -#define EFUSE_USR_DATA4_V 0xFFFFFFFFU -#define EFUSE_USR_DATA4_S 0 - -/** EFUSE_RD_USR_DATA5_REG register - * Represents rd_usr_data5 - */ -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) -/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA5 0xFFFFFFFFU -#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) -#define EFUSE_USR_DATA5_V 0xFFFFFFFFU -#define EFUSE_USR_DATA5_S 0 - -/** EFUSE_RD_USR_DATA6_REG register - * Represents rd_usr_data6 - */ -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 - -/** EFUSE_RD_USR_DATA7_REG register - * Represents rd_usr_data7 - */ -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 - -/** EFUSE_RD_KEY0_DATA0_REG register - * Represents rd_key0_data0 - */ -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) -/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA0 0xFFFFFFFFU -#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA0_S 0 - -/** EFUSE_RD_KEY0_DATA1_REG register - * Represents rd_key0_data1 - */ -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) -/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA1 0xFFFFFFFFU -#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA1_S 0 - -/** EFUSE_RD_KEY0_DATA2_REG register - * Represents rd_key0_data2 - */ -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) -/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA2 0xFFFFFFFFU -#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA2_S 0 - -/** EFUSE_RD_KEY0_DATA3_REG register - * Represents rd_key0_data3 - */ -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) -/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA3 0xFFFFFFFFU -#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA3_S 0 - -/** EFUSE_RD_KEY0_DATA4_REG register - * Represents rd_key0_data4 - */ -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) -/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA4 0xFFFFFFFFU -#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA4_S 0 - -/** EFUSE_RD_KEY0_DATA5_REG register - * Represents rd_key0_data5 - */ -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) -/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA5 0xFFFFFFFFU -#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA5_S 0 - -/** EFUSE_RD_KEY0_DATA6_REG register - * Represents rd_key0_data6 - */ -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) -/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA6 0xFFFFFFFFU -#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA6_S 0 - -/** EFUSE_RD_KEY0_DATA7_REG register - * Represents rd_key0_data7 - */ -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) -/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ -#define EFUSE_KEY0_DATA7 0xFFFFFFFFU -#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY0_DATA7_S 0 - -/** EFUSE_RD_KEY1_DATA0_REG register - * Represents rd_key1_data0 - */ -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) -/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA0 0xFFFFFFFFU -#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA0_S 0 - -/** EFUSE_RD_KEY1_DATA1_REG register - * Represents rd_key1_data1 - */ -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) -/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA1 0xFFFFFFFFU -#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA1_S 0 - -/** EFUSE_RD_KEY1_DATA2_REG register - * Represents rd_key1_data2 - */ -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) -/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA2 0xFFFFFFFFU -#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA2_S 0 - -/** EFUSE_RD_KEY1_DATA3_REG register - * Represents rd_key1_data3 - */ -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) -/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA3 0xFFFFFFFFU -#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA3_S 0 - -/** EFUSE_RD_KEY1_DATA4_REG register - * Represents rd_key1_data4 - */ -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) -/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA4 0xFFFFFFFFU -#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA4_S 0 - -/** EFUSE_RD_KEY1_DATA5_REG register - * Represents rd_key1_data5 - */ -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) -/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA5 0xFFFFFFFFU -#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA5_S 0 - -/** EFUSE_RD_KEY1_DATA6_REG register - * Represents rd_key1_data6 - */ -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) -/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA6 0xFFFFFFFFU -#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA6_S 0 - -/** EFUSE_RD_KEY1_DATA7_REG register - * Represents rd_key1_data7 - */ -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) -/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ -#define EFUSE_KEY1_DATA7 0xFFFFFFFFU -#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY1_DATA7_S 0 - -/** EFUSE_RD_KEY2_DATA0_REG register - * Represents rd_key2_data0 - */ -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) -/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA0 0xFFFFFFFFU -#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA0_S 0 - -/** EFUSE_RD_KEY2_DATA1_REG register - * Represents rd_key2_data1 - */ -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) -/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA1 0xFFFFFFFFU -#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA1_S 0 - -/** EFUSE_RD_KEY2_DATA2_REG register - * Represents rd_key2_data2 - */ -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) -/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA2 0xFFFFFFFFU -#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA2_S 0 - -/** EFUSE_RD_KEY2_DATA3_REG register - * Represents rd_key2_data3 - */ -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) -/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA3 0xFFFFFFFFU -#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA3_S 0 - -/** EFUSE_RD_KEY2_DATA4_REG register - * Represents rd_key2_data4 - */ -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) -/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA4 0xFFFFFFFFU -#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA4_S 0 - -/** EFUSE_RD_KEY2_DATA5_REG register - * Represents rd_key2_data5 - */ -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) -/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA5 0xFFFFFFFFU -#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA5_S 0 - -/** EFUSE_RD_KEY2_DATA6_REG register - * Represents rd_key2_data6 - */ -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) -/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA6 0xFFFFFFFFU -#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA6_S 0 - -/** EFUSE_RD_KEY2_DATA7_REG register - * Represents rd_key2_data7 - */ -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) -/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ -#define EFUSE_KEY2_DATA7 0xFFFFFFFFU -#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY2_DATA7_S 0 - -/** EFUSE_RD_KEY3_DATA0_REG register - * Represents rd_key3_data0 - */ -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) -/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA0 0xFFFFFFFFU -#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA0_S 0 - -/** EFUSE_RD_KEY3_DATA1_REG register - * Represents rd_key3_data1 - */ -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) -/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA1 0xFFFFFFFFU -#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA1_S 0 - -/** EFUSE_RD_KEY3_DATA2_REG register - * Represents rd_key3_data2 - */ -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) -/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA2 0xFFFFFFFFU -#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA2_S 0 - -/** EFUSE_RD_KEY3_DATA3_REG register - * Represents rd_key3_data3 - */ -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) -/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA3 0xFFFFFFFFU -#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA3_S 0 - -/** EFUSE_RD_KEY3_DATA4_REG register - * Represents rd_key3_data4 - */ -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) -/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA4 0xFFFFFFFFU -#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA4_S 0 - -/** EFUSE_RD_KEY3_DATA5_REG register - * Represents rd_key3_data5 - */ -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) -/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA5 0xFFFFFFFFU -#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA5_S 0 - -/** EFUSE_RD_KEY3_DATA6_REG register - * Represents rd_key3_data6 - */ -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) -/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA6 0xFFFFFFFFU -#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA6_S 0 - -/** EFUSE_RD_KEY3_DATA7_REG register - * Represents rd_key3_data7 - */ -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) -/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ -#define EFUSE_KEY3_DATA7 0xFFFFFFFFU -#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY3_DATA7_S 0 - -/** EFUSE_RD_KEY4_DATA0_REG register - * Represents rd_key4_data0 - */ -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) -/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA0 0xFFFFFFFFU -#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA0_S 0 - -/** EFUSE_RD_KEY4_DATA1_REG register - * Represents rd_key4_data1 - */ -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) -/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA1 0xFFFFFFFFU -#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA1_S 0 - -/** EFUSE_RD_KEY4_DATA2_REG register - * Represents rd_key4_data2 - */ -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) -/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA2 0xFFFFFFFFU -#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA2_S 0 - -/** EFUSE_RD_KEY4_DATA3_REG register - * Represents rd_key4_data3 - */ -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) -/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA3 0xFFFFFFFFU -#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA3_S 0 - -/** EFUSE_RD_KEY4_DATA4_REG register - * Represents rd_key4_data4 - */ -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) -/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA4 0xFFFFFFFFU -#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA4_S 0 - -/** EFUSE_RD_KEY4_DATA5_REG register - * Represents rd_key4_data5 - */ -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) -/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA5 0xFFFFFFFFU -#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA5_S 0 - -/** EFUSE_RD_KEY4_DATA6_REG register - * Represents rd_key4_data6 - */ -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) -/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA6 0xFFFFFFFFU -#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA6_S 0 - -/** EFUSE_RD_KEY4_DATA7_REG register - * Represents rd_key4_data7 - */ -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) -/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ -#define EFUSE_KEY4_DATA7 0xFFFFFFFFU -#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY4_DATA7_S 0 - -/** EFUSE_RD_KEY5_DATA0_REG register - * Represents rd_key5_data0 - */ -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) -/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA0 0xFFFFFFFFU -#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA0_S 0 - -/** EFUSE_RD_KEY5_DATA1_REG register - * Represents rd_key5_data1 - */ -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) -/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA1 0xFFFFFFFFU -#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA1_S 0 - -/** EFUSE_RD_KEY5_DATA2_REG register - * Represents rd_key5_data2 - */ -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) -/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA2 0xFFFFFFFFU -#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA2_S 0 - -/** EFUSE_RD_KEY5_DATA3_REG register - * Represents rd_key5_data3 - */ -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) -/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA3 0xFFFFFFFFU -#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA3_S 0 - -/** EFUSE_RD_KEY5_DATA4_REG register - * Represents rd_key5_data4 - */ -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) -/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA4 0xFFFFFFFFU -#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA4_S 0 - -/** EFUSE_RD_KEY5_DATA5_REG register - * Represents rd_key5_data5 - */ -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) -/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA5 0xFFFFFFFFU -#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA5_S 0 - -/** EFUSE_RD_KEY5_DATA6_REG register - * Represents rd_key5_data6 - */ -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) -/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA6 0xFFFFFFFFU -#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA6_S 0 - -/** EFUSE_RD_KEY5_DATA7_REG register - * Represents rd_key5_data7 - */ -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) -/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ -#define EFUSE_KEY5_DATA7 0xFFFFFFFFU -#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU -#define EFUSE_KEY5_DATA7_S 0 - -/** EFUSE_RD_SYS_PART2_DATA0_REG register - * Represents rd_sys_part2_data0 - */ -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_S 0 - -/** EFUSE_RD_SYS_PART2_DATA1_REG register - * Represents rd_sys_part2_data1 - */ -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_S 0 - -/** EFUSE_RD_SYS_PART2_DATA2_REG register - * Represents rd_sys_part2_data2 - */ -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_S 0 - -/** EFUSE_RD_SYS_PART2_DATA3_REG register - * Represents rd_sys_part2_data3 - */ -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_S 0 - -/** EFUSE_RD_SYS_PART2_DATA4_REG register - * Represents rd_sys_part2_data4 - */ -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) -/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_4_S 0 - -/** EFUSE_RD_SYS_PART2_DATA5_REG register - * Represents rd_sys_part2_data5 - */ -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_5_S 0 - -/** EFUSE_RD_SYS_PART2_DATA6_REG register - * Represents rd_sys_part2_data6 - */ -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_S 0 - -/** EFUSE_RD_SYS_PART2_DATA7_REG register - * Represents rd_sys_part2_data7 - */ -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_S 0 - -/** EFUSE_RD_REPEAT_DATA_ERR0_REG register - * Represents rd_repeat_data_err - */ -#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) -/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS - */ -#define EFUSE_RD_DIS_ERR 0x0000007FU -#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) -#define EFUSE_RD_DIS_ERR_V 0x0000007FU -#define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR (BIT(7)) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_V 0x00000001U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI_ERR_S 7 -/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_DIS_ICACHE - */ -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) -#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U -#define EFUSE_DIS_ICACHE_ERR_S 8 -/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG - */ -#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) -#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_USB_JTAG_ERR_S 9 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR (BIT(10)) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V 0x00000001U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S 10 -/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 -/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD - */ -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 -/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS - */ -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U -#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 -/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI - */ -#define EFUSE_DIS_TWAI_ERR (BIT(14)) -#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) -#define EFUSE_DIS_TWAI_ERR_V 0x00000001U -#define EFUSE_DIS_TWAI_ERR_S 14 -/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE - */ -#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) -#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) -#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U -#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 -/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG - */ -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 -/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG - */ -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 -/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT - */ -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; - * Represents the programming error of EFUSE_USB_DREFH - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_USB_DREFH_ERR 0x00000003U -#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) -#define EFUSE_USB_DREFH_ERR_V 0x00000003U -#define EFUSE_USB_DREFH_ERR_S 21 -/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; - * Represents the programming error of EFUSE_USB_DREFL - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_USB_DREFL_ERR 0x00000003U -#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) -#define EFUSE_USB_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_DREFL_ERR_S 23 -/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_EXCHG_PINS - */ -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 -/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO - */ -#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) -#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U -#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL - */ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_S 27 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR : RO; bitpos: [31:29]; - * default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR 0x00000007U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_V 0x00000007U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO_ERR_S 29 - -/** EFUSE_RD_REPEAT_DATA_ERR1_REG register - * Represents rd_repeat_data_err - */ -#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE - */ -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x0000000FU -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 0 -/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0; - * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE - */ -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 4 -/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0; - * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE - */ -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU -#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 6 -/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0; - * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY - */ -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU -#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 10 -/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY - */ -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(14)) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U -#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 14 -/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM - */ -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR (BIT(15)) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S) -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V 0x00000001U -#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S 15 -/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT - */ -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 16 -/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(19)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 19 -/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 20 -/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 - */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 21 -/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [26:22]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 - */ -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000001FU -#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_0_ERR_S 22 -/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:27]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 - */ -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000001FU -#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_1_ERR_S 27 - -/** EFUSE_RD_REPEAT_DATA_ERR2_REG register - * Represents rd_repeat_data_err - */ -#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [4:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 - */ -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000001FU -#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 -/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [9:5]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 - */ -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000001FU -#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_3_ERR_S 5 -/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [14:10]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 - */ -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000001FU -#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_4_ERR_S 10 -/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [19:15]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 - */ -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000001FU -#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000001FU -#define EFUSE_KEY_PURPOSE_5_ERR_S 15 -/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [21:20]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL - */ -#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) -#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U -#define EFUSE_SEC_DPA_LEVEL_ERR_S 20 -/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR : RO; bitpos: [24:22]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI - */ -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR 0x00000007U -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_S) -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_V 0x00000007U -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI_ERR_S 22 -/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN - */ -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(25)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_EN_ERR_S 25 -/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE - */ -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(26)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 26 -/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 - */ -#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR (BIT(27)) -#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S) -#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V 0x00000001U -#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S 27 -/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW - */ -#define EFUSE_FLASH_TPUW_ERR 0x0000000FU -#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) -#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU -#define EFUSE_FLASH_TPUW_ERR_S 28 - -/** EFUSE_RD_REPEAT_DATA_ERR3_REG register - * Represents rd_repeat_data_err - */ -#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE - */ -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 -/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT - */ -#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) -#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U -#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 -/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; - * Represents the programming error of EFUSE_LOCK_KM_KEY - */ -#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) -#define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) -#define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U -#define EFUSE_LOCK_KM_KEY_ERR_S 3 -/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE - */ -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 -/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD - */ -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 -/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL - */ -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 -/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME - */ -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U -#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 -/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [17:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION - */ -#define EFUSE_SECURE_VERSION_ERR 0x000001FFU -#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x000001FFU -#define EFUSE_SECURE_VERSION_ERR_S 9 -/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE - */ -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U -#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 -/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD - */ -#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) -#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) -#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U -#define EFUSE_HYS_EN_PAD_ERR_S 26 -/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL - */ -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 27 -/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE - */ -#define EFUSE_XTS_DPA_CLK_ENABLE_ERR (BIT(29)) -#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S) -#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V 0x00000001U -#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S 29 -/** EFUSE_ECDSA_P384_ENABLE_ERR : RO; bitpos: [31]; default: 0; - * Represents the programming error of EFUSE_ECDSA_P384_ENABLE - */ -#define EFUSE_ECDSA_P384_ENABLE_ERR (BIT(31)) -#define EFUSE_ECDSA_P384_ENABLE_ERR_M (EFUSE_ECDSA_P384_ENABLE_ERR_V << EFUSE_ECDSA_P384_ENABLE_ERR_S) -#define EFUSE_ECDSA_P384_ENABLE_ERR_V 0x00000001U -#define EFUSE_ECDSA_P384_ENABLE_ERR_S 31 - -/** EFUSE_RD_REPEAT_DATA_ERR4_REG register - * Represents rd_repeat_data_err - */ -#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) -/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [8:0]; default: 0; - * Represents the programming error of EFUSE_HUK_GEN_STATE - */ -#define EFUSE_HUK_GEN_STATE_ERR 0x000001FFU -#define EFUSE_HUK_GEN_STATE_ERR_M (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S) -#define EFUSE_HUK_GEN_STATE_ERR_V 0x000001FFU -#define EFUSE_HUK_GEN_STATE_ERR_S 0 -/** EFUSE_XTAL_48M_SEL_ERR : RO; bitpos: [11:9]; default: 0; - * Represents the programming error of EFUSE_XTAL_48M_SEL - */ -#define EFUSE_XTAL_48M_SEL_ERR 0x00000007U -#define EFUSE_XTAL_48M_SEL_ERR_M (EFUSE_XTAL_48M_SEL_ERR_V << EFUSE_XTAL_48M_SEL_ERR_S) -#define EFUSE_XTAL_48M_SEL_ERR_V 0x00000007U -#define EFUSE_XTAL_48M_SEL_ERR_S 9 -/** EFUSE_XTAL_48M_SEL_MODE_ERR : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE - */ -#define EFUSE_XTAL_48M_SEL_MODE_ERR (BIT(12)) -#define EFUSE_XTAL_48M_SEL_MODE_ERR_M (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S) -#define EFUSE_XTAL_48M_SEL_MODE_ERR_V 0x00000001U -#define EFUSE_XTAL_48M_SEL_MODE_ERR_S 12 -/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME - */ -#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(13)) -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 13 -/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR : RO; bitpos: [22:14]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO - */ -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR 0x000001FFU -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_S) -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_V 0x000001FFU -#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO_ERR_S 14 - -/** EFUSE_RD_RS_DATA_ERR0_REG register - * Represents rd_rs_data_err - */ -#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) -/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U -#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) -#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U -#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 -/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. - */ -#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) -#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U -#define EFUSE_RD_MAC_SYS_FAIL_S 3 -/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data - */ -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 -/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. - */ -#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) -#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) -#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 -/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data - */ -#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) -#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 -/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) -#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) -#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_USR_DATA_FAIL_S 11 -/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data - */ -#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 -/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) -#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) -#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY0_DATA_FAIL_S 15 -/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data - */ -#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 -/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) -#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) -#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY1_DATA_FAIL_S 19 -/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data - */ -#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 -/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) -#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) -#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY2_DATA_FAIL_S 23 -/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data - */ -#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 -/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) -#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) -#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY3_DATA_FAIL_S 27 -/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data - */ -#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 -/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) -#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) -#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY4_DATA_FAIL_S 31 - -/** EFUSE_RD_RS_DATA_ERR1_REG register - * Represents rd_rs_data_err - */ -#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) -/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data - */ -#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 -/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) -#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) -#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY5_DATA_FAIL_S 3 -/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data - */ -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 -/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. - */ -#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) -#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) -#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 - -/** EFUSE_DATE_REG register - * eFuse version register. - */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37818960; - * Represents eFuse version. Date:2024-12-19 16:08:23, - * ScriptRev:5b7d298cf2df9f93b161800aff1807aeadbb74f4 - */ -#define EFUSE_DATE 0x0FFFFFFFU -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0FFFFFFFU -#define EFUSE_DATE_S 0 - -/** EFUSE_CLK_REG register - * eFuse clcok configuration register. - */ -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) -/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect - */ -#define EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) -#define EFUSE_MEM_FORCE_PD_V 0x00000001U -#define EFUSE_MEM_FORCE_PD_S 0 -/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect - */ -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U -#define EFUSE_MEM_CLK_FORCE_ON_S 1 -/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect - */ -#define EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) -#define EFUSE_MEM_FORCE_PU_V 0x00000001U -#define EFUSE_MEM_FORCE_PU_S 2 -/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers - */ -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) -#define EFUSE_CLK_EN_V 0x00000001U -#define EFUSE_CLK_EN_S 16 - -/** EFUSE_CONF_REG register - * eFuse operation mode configuration register - */ -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) -/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect - */ -#define EFUSE_OP_CODE 0x0000FFFFU -#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) -#define EFUSE_OP_CODE_V 0x0000FFFFU -#define EFUSE_OP_CODE_S 0 - -/** EFUSE_ECDSA_REG register - * eFuse status register. - */ -#define EFUSE_ECDSA_REG (DR_REG_EFUSE_BASE + 0x1d0) -/** EFUSE_CFG_ECDSA_P192_BLK : R/W; bitpos: [3:0]; default: 0; - * Configures which block to use for ECDSA P192 key output. - */ -#define EFUSE_CFG_ECDSA_P192_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_P192_BLK_M (EFUSE_CFG_ECDSA_P192_BLK_V << EFUSE_CFG_ECDSA_P192_BLK_S) -#define EFUSE_CFG_ECDSA_P192_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_P192_BLK_S 0 -/** EFUSE_CFG_ECDSA_P256_BLK : R/W; bitpos: [7:4]; default: 0; - * Configures which block to use for ECDSA P256 key output. - */ -#define EFUSE_CFG_ECDSA_P256_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_P256_BLK_M (EFUSE_CFG_ECDSA_P256_BLK_V << EFUSE_CFG_ECDSA_P256_BLK_S) -#define EFUSE_CFG_ECDSA_P256_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_P256_BLK_S 4 -/** EFUSE_CFG_ECDSA_P384_L_BLK : R/W; bitpos: [11:8]; default: 0; - * Configures which block to use for ECDSA P384 key low part output. - */ -#define EFUSE_CFG_ECDSA_P384_L_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_P384_L_BLK_M (EFUSE_CFG_ECDSA_P384_L_BLK_V << EFUSE_CFG_ECDSA_P384_L_BLK_S) -#define EFUSE_CFG_ECDSA_P384_L_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_P384_L_BLK_S 8 -/** EFUSE_CFG_ECDSA_P384_H_BLK : R/W; bitpos: [15:12]; default: 0; - * Configures which block to use for ECDSA P256 key high part output. - */ -#define EFUSE_CFG_ECDSA_P384_H_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_P384_H_BLK_M (EFUSE_CFG_ECDSA_P384_H_BLK_V << EFUSE_CFG_ECDSA_P384_H_BLK_S) -#define EFUSE_CFG_ECDSA_P384_H_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_P384_H_BLK_S 12 -/** EFUSE_CUR_ECDSA_P192_BLK : RO; bitpos: [19:16]; default: 0; - * Represents which block is used for ECDSA P192 key output. - */ -#define EFUSE_CUR_ECDSA_P192_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_P192_BLK_M (EFUSE_CUR_ECDSA_P192_BLK_V << EFUSE_CUR_ECDSA_P192_BLK_S) -#define EFUSE_CUR_ECDSA_P192_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_P192_BLK_S 16 -/** EFUSE_CUR_ECDSA_P256_BLK : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA P256 key output. - */ -#define EFUSE_CUR_ECDSA_P256_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_P256_BLK_M (EFUSE_CUR_ECDSA_P256_BLK_V << EFUSE_CUR_ECDSA_P256_BLK_S) -#define EFUSE_CUR_ECDSA_P256_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_P256_BLK_S 20 -/** EFUSE_CUR_ECDSA_P384_L_BLK : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA P384 key low part output. - */ -#define EFUSE_CUR_ECDSA_P384_L_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_P384_L_BLK_M (EFUSE_CUR_ECDSA_P384_L_BLK_V << EFUSE_CUR_ECDSA_P384_L_BLK_S) -#define EFUSE_CUR_ECDSA_P384_L_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_P384_L_BLK_S 24 -/** EFUSE_CUR_ECDSA_P384_H_BLK : RO; bitpos: [31:28]; default: 0; - * Represents which block is used for ECDSA P384 key high part output. - */ -#define EFUSE_CUR_ECDSA_P384_H_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_P384_H_BLK_M (EFUSE_CUR_ECDSA_P384_H_BLK_V << EFUSE_CUR_ECDSA_P384_H_BLK_S) -#define EFUSE_CUR_ECDSA_P384_H_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_P384_H_BLK_S 28 - -/** EFUSE_STATUS_REG register - * eFuse status register. - */ -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d4) -/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state - */ -#define EFUSE_STATE 0x0000000FU -#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) -#define EFUSE_STATE_V 0x0000000FU -#define EFUSE_STATE_S 0 -/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * Represents the value of OTP_LOAD_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) -#define EFUSE_OTP_LOAD_SW_V 0x00000001U -#define EFUSE_OTP_LOAD_SW_S 4 -/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * Represents the value of OTP_VDDQ_C_SYNC2. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 -/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * Represents the value of OTP_STROBE_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) -#define EFUSE_OTP_STROBE_SW_V 0x00000001U -#define EFUSE_OTP_STROBE_SW_S 6 -/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * Represents the value of OTP_CSB_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) -#define EFUSE_OTP_CSB_SW_V 0x00000001U -#define EFUSE_OTP_CSB_SW_S 7 -/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * Represents the value of OTP_PGENB_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) -#define EFUSE_OTP_PGENB_SW_V 0x00000001U -#define EFUSE_OTP_PGENB_SW_S 8 -/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * Represents the value of OTP_VDDQ_IS_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U -#define EFUSE_OTP_VDDQ_IS_SW_S 9 -/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; - * Represents the number of block valid bit. - */ -#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU -#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) -#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU -#define EFUSE_BLK0_VALID_BIT_CNT_S 10 - -/** EFUSE_CMD_REG register - * eFuse command register. - */ -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d8) -/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect - */ -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) -#define EFUSE_READ_CMD_V 0x00000001U -#define EFUSE_READ_CMD_S 0 -/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect - */ -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) -#define EFUSE_PGM_CMD_V 0x00000001U -#define EFUSE_PGM_CMD_S 1 -/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * Configures the serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. - */ -#define EFUSE_BLK_NUM 0x0000000FU -#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) -#define EFUSE_BLK_NUM_V 0x0000000FU -#define EFUSE_BLK_NUM_S 2 - -/** EFUSE_INT_RAW_REG register - * eFuse raw interrupt register. - */ -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1dc) -/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of EFUSE_READ_DONE_INT. - */ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) -#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U -#define EFUSE_READ_DONE_INT_RAW_S 0 -/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status of EFUSE_PGM_DONE_INT. - */ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) -#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/** EFUSE_INT_ST_REG register - * eFuse interrupt status register. - */ -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1e0) -/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of EFUSE_READ_DONE_INT. - */ -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) -#define EFUSE_READ_DONE_INT_ST_V 0x00000001U -#define EFUSE_READ_DONE_INT_ST_S 0 -/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of EFUSE_PGM_DONE_INT. - */ -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) -#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/** EFUSE_INT_ENA_REG register - * eFuse interrupt enable register. - */ -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e4) -/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable EFUSE_READ_DONE_INT. - */ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) -#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U -#define EFUSE_READ_DONE_INT_ENA_S 0 -/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable EFUSE_PGM_DONE_INT. - */ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) -#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/** EFUSE_INT_CLR_REG register - * eFuse interrupt clear register. - */ -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear EFUSE_READ_DONE_INT. - */ -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) -#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U -#define EFUSE_READ_DONE_INT_CLR_S 0 -/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear EFUSE_PGM_DONE_INT. - */ -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) -#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/** EFUSE_DAC_CONF_REG register - * Controls the eFuse programming voltage. - */ -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 19; - * Configures the division factor of the rising clock of the programming voltage. - */ -#define EFUSE_DAC_CLK_DIV 0x000000FFU -#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) -#define EFUSE_DAC_CLK_DIV_V 0x000000FFU -#define EFUSE_DAC_CLK_DIV_S 0 -/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; - * Don't care. - */ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U -#define EFUSE_DAC_CLK_PAD_SEL_S 8 -/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Configures clock cycles for programming voltage to rise. Measurement unit: a clock - * cycle divided by EFUSE_DAC_CLK_DIV. - */ -#define EFUSE_DAC_NUM 0x000000FFU -#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) -#define EFUSE_DAC_NUM_V 0x000000FFU -#define EFUSE_DAC_NUM_S 9 -/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce - */ -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) -#define EFUSE_OE_CLR_V 0x00000001U -#define EFUSE_OE_CLR_S 17 - -/** EFUSE_RD_TIM_CONF_REG register - * Configures read timing parameters. - */ -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1f0) -/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. - */ -#define EFUSE_THR_A 0x000000FFU -#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) -#define EFUSE_THR_A_V 0x000000FFU -#define EFUSE_THR_A_S 0 -/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. Measurement unit: One cycle of the eFuse core clock. - */ -#define EFUSE_TRD 0x000000FFU -#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) -#define EFUSE_TRD_V 0x000000FFU -#define EFUSE_TRD_S 8 -/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. - */ -#define EFUSE_TSUR_A 0x000000FFU -#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) -#define EFUSE_TSUR_A_V 0x000000FFU -#define EFUSE_TSUR_A_S 16 -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of - * the eFuse core clock. - */ -#define EFUSE_READ_INIT_NUM 0x000000FFU -#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) -#define EFUSE_READ_INIT_NUM_V 0x000000FFU -#define EFUSE_READ_INIT_NUM_S 24 - -/** EFUSE_WR_TIM_CONF1_REG register - * Configurarion register 1 of eFuse programming timing parameters. - */ -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) -/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. Measurement unit: One cycle of the eFuse - * core clock. - */ -#define EFUSE_TSUP_A 0x000000FFU -#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) -#define EFUSE_TSUP_A_V 0x000000FFU -#define EFUSE_TSUP_A_S 0 -/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. - */ -#define EFUSE_PWR_ON_NUM 0x0000FFFFU -#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) -#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU -#define EFUSE_PWR_ON_NUM_S 8 -/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. Measurement unit: One cycle of the eFuse core - * clock. - */ -#define EFUSE_THP_A 0x000000FFU -#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) -#define EFUSE_THP_A_V 0x000000FFU -#define EFUSE_THP_A_S 24 - -/** EFUSE_WR_TIM_CONF2_REG register - * Configurarion register 2 of eFuse programming timing parameters. - */ -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) -/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. - */ -#define EFUSE_PWR_OFF_NUM 0x0000FFFFU -#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) -#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU -#define EFUSE_PWR_OFF_NUM_S 0 -/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. Measurement unit: One cycle of the eFuse - * core clock. - */ -#define EFUSE_TPGM 0x0000FFFFU -#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) -#define EFUSE_TPGM_V 0x0000FFFFU -#define EFUSE_TPGM_S 16 - -/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1fc) -/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass - */ -#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) -#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) -#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U -#define EFUSE_BYPASS_RS_CORRECTION_S 0 -/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; - * Configures which block number to bypass the Reed-Solomon (RS) correction step. - */ -#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU -#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) -#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU -#define EFUSE_BYPASS_RS_BLK_NUM_S 1 -/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect - */ -#define EFUSE_UPDATE (BIT(12)) -#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) -#define EFUSE_UPDATE_V 0x00000001U -#define EFUSE_UPDATE_S 12 -/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. Measurement unit: One cycle of the eFuse - * core clock. - */ -#define EFUSE_TPGM_INACTIVE 0x000000FFU -#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) -#define EFUSE_TPGM_INACTIVE_V 0x000000FFU -#define EFUSE_TPGM_INACTIVE_S 13 - -/** EFUSE_APB2OTP_WR_DIS_REG register - * eFuse apb2otp block0 data register1. - */ -#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x500) -/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ -#define EFUSE_APB2OTP_BLOCK0_WR_DIS 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S) -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register - * eFuse apb2otp block0 data register2. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x504) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register - * eFuse apb2otp block0 data register3. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x508) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register - * eFuse apb2otp block0 data register4. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x50c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register - * eFuse apb2otp block0 data register5. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x510) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register - * eFuse apb2otp block0 data register6. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x514) -/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register - * eFuse apb2otp block0 data register7. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x518) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register - * eFuse apb2otp block0 data register8. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x51c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register - * eFuse apb2otp block0 data register9. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x520) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register - * eFuse apb2otp block0 data register10. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x524) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register - * eFuse apb2otp block0 data register11. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x528) -/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register - * eFuse apb2otp block0 data register12. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x52c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register - * eFuse apb2otp block0 data register13. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x530) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register - * eFuse apb2otp block0 data register14. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x534) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register - * eFuse apb2otp block0 data register15. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x538) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register - * eFuse apb2otp block0 data register16. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x53c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register - * eFuse apb2otp block0 data register17. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x540) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register - * eFuse apb2otp block0 data register18. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x544) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register - * eFuse apb2otp block0 data register19. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x548) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register - * eFuse apb2otp block0 data register20. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x54c) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S 0 - -/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register - * eFuse apb2otp block0 data register21. - */ -#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x550) -/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S) -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S 0 - -/** EFUSE_APB2OTP_BLK1_W1_REG register - * eFuse apb2otp block1 data register1. - */ -#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x554) -/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W1_M (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S) -#define EFUSE_APB2OTP_BLOCK1_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W1_S 0 - -/** EFUSE_APB2OTP_BLK1_W2_REG register - * eFuse apb2otp block1 data register2. - */ -#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x558) -/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W2_M (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S) -#define EFUSE_APB2OTP_BLOCK1_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W2_S 0 - -/** EFUSE_APB2OTP_BLK1_W3_REG register - * eFuse apb2otp block1 data register3. - */ -#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x55c) -/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W3_M (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S) -#define EFUSE_APB2OTP_BLOCK1_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W3_S 0 - -/** EFUSE_APB2OTP_BLK1_W4_REG register - * eFuse apb2otp block1 data register4. - */ -#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x560) -/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W4_M (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S) -#define EFUSE_APB2OTP_BLOCK1_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W4_S 0 - -/** EFUSE_APB2OTP_BLK1_W5_REG register - * eFuse apb2otp block1 data register5. - */ -#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x564) -/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W5_M (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S) -#define EFUSE_APB2OTP_BLOCK1_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W5_S 0 - -/** EFUSE_APB2OTP_BLK1_W6_REG register - * eFuse apb2otp block1 data register6. - */ -#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x568) -/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W6_M (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S) -#define EFUSE_APB2OTP_BLOCK1_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W6_S 0 - -/** EFUSE_APB2OTP_BLK1_W7_REG register - * eFuse apb2otp block1 data register7. - */ -#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x56c) -/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W7_M (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S) -#define EFUSE_APB2OTP_BLOCK1_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W7_S 0 - -/** EFUSE_APB2OTP_BLK1_W8_REG register - * eFuse apb2otp block1 data register8. - */ -#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x570) -/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W8_M (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S) -#define EFUSE_APB2OTP_BLOCK1_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W8_S 0 - -/** EFUSE_APB2OTP_BLK1_W9_REG register - * eFuse apb2otp block1 data register9. - */ -#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x574) -/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK1_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W9_M (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S) -#define EFUSE_APB2OTP_BLOCK1_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK1_W9_S 0 - -/** EFUSE_APB2OTP_BLK2_W1_REG register - * eFuse apb2otp block2 data register1. - */ -#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x578) -/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W1_M (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S) -#define EFUSE_APB2OTP_BLOCK2_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W1_S 0 - -/** EFUSE_APB2OTP_BLK2_W2_REG register - * eFuse apb2otp block2 data register2. - */ -#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x57c) -/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W2_M (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S) -#define EFUSE_APB2OTP_BLOCK2_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W2_S 0 - -/** EFUSE_APB2OTP_BLK2_W3_REG register - * eFuse apb2otp block2 data register3. - */ -#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x580) -/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W3_M (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S) -#define EFUSE_APB2OTP_BLOCK2_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W3_S 0 - -/** EFUSE_APB2OTP_BLK2_W4_REG register - * eFuse apb2otp block2 data register4. - */ -#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x584) -/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W4_M (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S) -#define EFUSE_APB2OTP_BLOCK2_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W4_S 0 - -/** EFUSE_APB2OTP_BLK2_W5_REG register - * eFuse apb2otp block2 data register5. - */ -#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x588) -/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W5_M (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S) -#define EFUSE_APB2OTP_BLOCK2_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W5_S 0 - -/** EFUSE_APB2OTP_BLK2_W6_REG register - * eFuse apb2otp block2 data register6. - */ -#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x58c) -/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W6_M (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S) -#define EFUSE_APB2OTP_BLOCK2_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W6_S 0 - -/** EFUSE_APB2OTP_BLK2_W7_REG register - * eFuse apb2otp block2 data register7. - */ -#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x590) -/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W7_M (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S) -#define EFUSE_APB2OTP_BLOCK2_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W7_S 0 - -/** EFUSE_APB2OTP_BLK2_W8_REG register - * eFuse apb2otp block2 data register8. - */ -#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x594) -/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W8_M (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S) -#define EFUSE_APB2OTP_BLOCK2_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W8_S 0 - -/** EFUSE_APB2OTP_BLK2_W9_REG register - * eFuse apb2otp block2 data register9. - */ -#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x598) -/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W9_M (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S) -#define EFUSE_APB2OTP_BLOCK2_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W9_S 0 - -/** EFUSE_APB2OTP_BLK2_W10_REG register - * eFuse apb2otp block2 data register10. - */ -#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x59c) -/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W10_M (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S) -#define EFUSE_APB2OTP_BLOCK2_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W10_S 0 - -/** EFUSE_APB2OTP_BLK2_W11_REG register - * eFuse apb2otp block2 data register11. - */ -#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x5a0) -/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK2_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W11_M (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S) -#define EFUSE_APB2OTP_BLOCK2_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK2_W11_S 0 - -/** EFUSE_APB2OTP_BLK3_W1_REG register - * eFuse apb2otp block3 data register1. - */ -#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x5a4) -/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W1_M (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S) -#define EFUSE_APB2OTP_BLOCK3_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W1_S 0 - -/** EFUSE_APB2OTP_BLK3_W2_REG register - * eFuse apb2otp block3 data register2. - */ -#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x5a8) -/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W2_M (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S) -#define EFUSE_APB2OTP_BLOCK3_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W2_S 0 - -/** EFUSE_APB2OTP_BLK3_W3_REG register - * eFuse apb2otp block3 data register3. - */ -#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x5ac) -/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W3_M (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S) -#define EFUSE_APB2OTP_BLOCK3_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W3_S 0 - -/** EFUSE_APB2OTP_BLK3_W4_REG register - * eFuse apb2otp block3 data register4. - */ -#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x5b0) -/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W4_M (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S) -#define EFUSE_APB2OTP_BLOCK3_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W4_S 0 - -/** EFUSE_APB2OTP_BLK3_W5_REG register - * eFuse apb2otp block3 data register5. - */ -#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x5b4) -/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W5_M (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S) -#define EFUSE_APB2OTP_BLOCK3_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W5_S 0 - -/** EFUSE_APB2OTP_BLK3_W6_REG register - * eFuse apb2otp block3 data register6. - */ -#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x5b8) -/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W6_M (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S) -#define EFUSE_APB2OTP_BLOCK3_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W6_S 0 - -/** EFUSE_APB2OTP_BLK3_W7_REG register - * eFuse apb2otp block3 data register7. - */ -#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x5bc) -/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W7_M (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S) -#define EFUSE_APB2OTP_BLOCK3_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W7_S 0 - -/** EFUSE_APB2OTP_BLK3_W8_REG register - * eFuse apb2otp block3 data register8. - */ -#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x5c0) -/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W8_M (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S) -#define EFUSE_APB2OTP_BLOCK3_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W8_S 0 - -/** EFUSE_APB2OTP_BLK3_W9_REG register - * eFuse apb2otp block3 data register9. - */ -#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x5c4) -/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W9_M (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S) -#define EFUSE_APB2OTP_BLOCK3_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W9_S 0 - -/** EFUSE_APB2OTP_BLK3_W10_REG register - * eFuse apb2otp block3 data register10. - */ -#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x5c8) -/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W10_M (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S) -#define EFUSE_APB2OTP_BLOCK3_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W10_S 0 - -/** EFUSE_APB2OTP_BLK3_W11_REG register - * eFuse apb2otp block3 data register11. - */ -#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x5cc) -/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK3_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W11_M (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S) -#define EFUSE_APB2OTP_BLOCK3_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK3_W11_S 0 - -/** EFUSE_APB2OTP_BLK4_W1_REG register - * eFuse apb2otp BLOCK7 data register1. - */ -#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x5d0) -/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W1_M (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S) -#define EFUSE_APB2OTP_BLOCK4_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W1_S 0 - -/** EFUSE_APB2OTP_BLK4_W2_REG register - * eFuse apb2otp block4 data register2. - */ -#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x5d4) -/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W2_M (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S) -#define EFUSE_APB2OTP_BLOCK4_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W2_S 0 - -/** EFUSE_APB2OTP_BLK4_W3_REG register - * eFuse apb2otp block4 data register3. - */ -#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x5d8) -/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W3_M (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S) -#define EFUSE_APB2OTP_BLOCK4_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W3_S 0 - -/** EFUSE_APB2OTP_BLK4_W4_REG register - * eFuse apb2otp block4 data register4. - */ -#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x5dc) -/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W4_M (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S) -#define EFUSE_APB2OTP_BLOCK4_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W4_S 0 - -/** EFUSE_APB2OTP_BLK4_W5_REG register - * eFuse apb2otp block4 data register5. - */ -#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x5e0) -/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W5_M (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S) -#define EFUSE_APB2OTP_BLOCK4_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W5_S 0 - -/** EFUSE_APB2OTP_BLK4_W6_REG register - * eFuse apb2otp block4 data register6. - */ -#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x5e4) -/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W6_M (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S) -#define EFUSE_APB2OTP_BLOCK4_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W6_S 0 - -/** EFUSE_APB2OTP_BLK4_W7_REG register - * eFuse apb2otp block4 data register7. - */ -#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x5e8) -/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W7_M (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S) -#define EFUSE_APB2OTP_BLOCK4_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W7_S 0 - -/** EFUSE_APB2OTP_BLK4_W8_REG register - * eFuse apb2otp block4 data register8. - */ -#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x5ec) -/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W8_M (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S) -#define EFUSE_APB2OTP_BLOCK4_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W8_S 0 - -/** EFUSE_APB2OTP_BLK4_W9_REG register - * eFuse apb2otp block4 data register9. - */ -#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x5f0) -/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W9_M (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S) -#define EFUSE_APB2OTP_BLOCK4_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W9_S 0 - -/** EFUSE_APB2OTP_BLK4_W10_REG register - * eFuse apb2otp block4 data registe10. - */ -#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x5f4) -/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W10_M (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S) -#define EFUSE_APB2OTP_BLOCK4_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W10_S 0 - -/** EFUSE_APB2OTP_BLK4_W11_REG register - * eFuse apb2otp block4 data register11. - */ -#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x5f8) -/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK4_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W11_M (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S) -#define EFUSE_APB2OTP_BLOCK4_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK4_W11_S 0 - -/** EFUSE_APB2OTP_BLK5_W1_REG register - * eFuse apb2otp block5 data register1. - */ -#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x5fc) -/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W1_M (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S) -#define EFUSE_APB2OTP_BLOCK5_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W1_S 0 - -/** EFUSE_APB2OTP_BLK5_W2_REG register - * eFuse apb2otp block5 data register2. - */ -#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x600) -/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W2_M (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S) -#define EFUSE_APB2OTP_BLOCK5_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W2_S 0 - -/** EFUSE_APB2OTP_BLK5_W3_REG register - * eFuse apb2otp block5 data register3. - */ -#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x604) -/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W3_M (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S) -#define EFUSE_APB2OTP_BLOCK5_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W3_S 0 - -/** EFUSE_APB2OTP_BLK5_W4_REG register - * eFuse apb2otp block5 data register4. - */ -#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x608) -/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W4_M (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S) -#define EFUSE_APB2OTP_BLOCK5_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W4_S 0 - -/** EFUSE_APB2OTP_BLK5_W5_REG register - * eFuse apb2otp block5 data register5. - */ -#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x60c) -/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W5_M (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S) -#define EFUSE_APB2OTP_BLOCK5_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W5_S 0 - -/** EFUSE_APB2OTP_BLK5_W6_REG register - * eFuse apb2otp block5 data register6. - */ -#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x610) -/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W6_M (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S) -#define EFUSE_APB2OTP_BLOCK5_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W6_S 0 - -/** EFUSE_APB2OTP_BLK5_W7_REG register - * eFuse apb2otp block5 data register7. - */ -#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x614) -/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W7_M (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S) -#define EFUSE_APB2OTP_BLOCK5_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W7_S 0 - -/** EFUSE_APB2OTP_BLK5_W8_REG register - * eFuse apb2otp block5 data register8. - */ -#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x618) -/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W8_M (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S) -#define EFUSE_APB2OTP_BLOCK5_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W8_S 0 - -/** EFUSE_APB2OTP_BLK5_W9_REG register - * eFuse apb2otp block5 data register9. - */ -#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x61c) -/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W9_M (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S) -#define EFUSE_APB2OTP_BLOCK5_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W9_S 0 - -/** EFUSE_APB2OTP_BLK5_W10_REG register - * eFuse apb2otp block5 data register10. - */ -#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x620) -/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W10_M (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S) -#define EFUSE_APB2OTP_BLOCK5_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W10_S 0 - -/** EFUSE_APB2OTP_BLK5_W11_REG register - * eFuse apb2otp block5 data register11. - */ -#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x624) -/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK5_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W11_M (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S) -#define EFUSE_APB2OTP_BLOCK5_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK5_W11_S 0 - -/** EFUSE_APB2OTP_BLK6_W1_REG register - * eFuse apb2otp block6 data register1. - */ -#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x628) -/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W1_M (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S) -#define EFUSE_APB2OTP_BLOCK6_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W1_S 0 - -/** EFUSE_APB2OTP_BLK6_W2_REG register - * eFuse apb2otp block6 data register2. - */ -#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x62c) -/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W2_M (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S) -#define EFUSE_APB2OTP_BLOCK6_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W2_S 0 - -/** EFUSE_APB2OTP_BLK6_W3_REG register - * eFuse apb2otp block6 data register3. - */ -#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x630) -/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W3_M (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S) -#define EFUSE_APB2OTP_BLOCK6_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W3_S 0 - -/** EFUSE_APB2OTP_BLK6_W4_REG register - * eFuse apb2otp block6 data register4. - */ -#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x634) -/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W4_M (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S) -#define EFUSE_APB2OTP_BLOCK6_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W4_S 0 - -/** EFUSE_APB2OTP_BLK6_W5_REG register - * eFuse apb2otp block6 data register5. - */ -#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x638) -/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W5_M (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S) -#define EFUSE_APB2OTP_BLOCK6_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W5_S 0 - -/** EFUSE_APB2OTP_BLK6_W6_REG register - * eFuse apb2otp block6 data register6. - */ -#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x63c) -/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W6_M (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S) -#define EFUSE_APB2OTP_BLOCK6_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W6_S 0 - -/** EFUSE_APB2OTP_BLK6_W7_REG register - * eFuse apb2otp block6 data register7. - */ -#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x640) -/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W7_M (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S) -#define EFUSE_APB2OTP_BLOCK6_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W7_S 0 - -/** EFUSE_APB2OTP_BLK6_W8_REG register - * eFuse apb2otp block6 data register8. - */ -#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x644) -/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W8_M (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S) -#define EFUSE_APB2OTP_BLOCK6_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W8_S 0 - -/** EFUSE_APB2OTP_BLK6_W9_REG register - * eFuse apb2otp block6 data register9. - */ -#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x648) -/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W9_M (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S) -#define EFUSE_APB2OTP_BLOCK6_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W9_S 0 - -/** EFUSE_APB2OTP_BLK6_W10_REG register - * eFuse apb2otp block6 data register10. - */ -#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x64c) -/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W10_M (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S) -#define EFUSE_APB2OTP_BLOCK6_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W10_S 0 - -/** EFUSE_APB2OTP_BLK6_W11_REG register - * eFuse apb2otp block6 data register11. - */ -#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x650) -/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK6_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W11_M (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S) -#define EFUSE_APB2OTP_BLOCK6_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK6_W11_S 0 - -/** EFUSE_APB2OTP_BLK7_W1_REG register - * eFuse apb2otp block7 data register1. - */ -#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x654) -/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W1_M (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S) -#define EFUSE_APB2OTP_BLOCK7_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W1_S 0 - -/** EFUSE_APB2OTP_BLK7_W2_REG register - * eFuse apb2otp block7 data register2. - */ -#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x658) -/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W2_M (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S) -#define EFUSE_APB2OTP_BLOCK7_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W2_S 0 - -/** EFUSE_APB2OTP_BLK7_W3_REG register - * eFuse apb2otp block7 data register3. - */ -#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x65c) -/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W3_M (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S) -#define EFUSE_APB2OTP_BLOCK7_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W3_S 0 - -/** EFUSE_APB2OTP_BLK7_W4_REG register - * eFuse apb2otp block7 data register4. - */ -#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x660) -/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W4_M (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S) -#define EFUSE_APB2OTP_BLOCK7_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W4_S 0 - -/** EFUSE_APB2OTP_BLK7_W5_REG register - * eFuse apb2otp block7 data register5. - */ -#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x664) -/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W5_M (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S) -#define EFUSE_APB2OTP_BLOCK7_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W5_S 0 - -/** EFUSE_APB2OTP_BLK7_W6_REG register - * eFuse apb2otp block7 data register6. - */ -#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x668) -/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W6_M (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S) -#define EFUSE_APB2OTP_BLOCK7_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W6_S 0 - -/** EFUSE_APB2OTP_BLK7_W7_REG register - * eFuse apb2otp block7 data register7. - */ -#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x66c) -/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W7_M (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S) -#define EFUSE_APB2OTP_BLOCK7_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W7_S 0 - -/** EFUSE_APB2OTP_BLK7_W8_REG register - * eFuse apb2otp block7 data register8. - */ -#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x670) -/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W8_M (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S) -#define EFUSE_APB2OTP_BLOCK7_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W8_S 0 - -/** EFUSE_APB2OTP_BLK7_W9_REG register - * eFuse apb2otp block7 data register9. - */ -#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x674) -/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W9_M (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S) -#define EFUSE_APB2OTP_BLOCK7_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W9_S 0 - -/** EFUSE_APB2OTP_BLK7_W10_REG register - * eFuse apb2otp block7 data register10. - */ -#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x678) -/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W10_M (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S) -#define EFUSE_APB2OTP_BLOCK7_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W10_S 0 - -/** EFUSE_APB2OTP_BLK7_W11_REG register - * eFuse apb2otp block7 data register11. - */ -#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x67c) -/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK7_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W11_M (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S) -#define EFUSE_APB2OTP_BLOCK7_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK7_W11_S 0 - -/** EFUSE_APB2OTP_BLK8_W1_REG register - * eFuse apb2otp block8 data register1. - */ -#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x680) -/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W1_M (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S) -#define EFUSE_APB2OTP_BLOCK8_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W1_S 0 - -/** EFUSE_APB2OTP_BLK8_W2_REG register - * eFuse apb2otp block8 data register2. - */ -#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x684) -/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W2_M (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S) -#define EFUSE_APB2OTP_BLOCK8_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W2_S 0 - -/** EFUSE_APB2OTP_BLK8_W3_REG register - * eFuse apb2otp block8 data register3. - */ -#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x688) -/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W3_M (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S) -#define EFUSE_APB2OTP_BLOCK8_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W3_S 0 - -/** EFUSE_APB2OTP_BLK8_W4_REG register - * eFuse apb2otp block8 data register4. - */ -#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x68c) -/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W4_M (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S) -#define EFUSE_APB2OTP_BLOCK8_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W4_S 0 - -/** EFUSE_APB2OTP_BLK8_W5_REG register - * eFuse apb2otp block8 data register5. - */ -#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x690) -/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W5_M (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S) -#define EFUSE_APB2OTP_BLOCK8_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W5_S 0 - -/** EFUSE_APB2OTP_BLK8_W6_REG register - * eFuse apb2otp block8 data register6. - */ -#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x694) -/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W6_M (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S) -#define EFUSE_APB2OTP_BLOCK8_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W6_S 0 - -/** EFUSE_APB2OTP_BLK8_W7_REG register - * eFuse apb2otp block8 data register7. - */ -#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x698) -/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W7_M (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S) -#define EFUSE_APB2OTP_BLOCK8_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W7_S 0 - -/** EFUSE_APB2OTP_BLK8_W8_REG register - * eFuse apb2otp block8 data register8. - */ -#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x69c) -/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W8_M (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S) -#define EFUSE_APB2OTP_BLOCK8_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W8_S 0 - -/** EFUSE_APB2OTP_BLK8_W9_REG register - * eFuse apb2otp block8 data register9. - */ -#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x6a0) -/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W9_M (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S) -#define EFUSE_APB2OTP_BLOCK8_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W9_S 0 - -/** EFUSE_APB2OTP_BLK8_W10_REG register - * eFuse apb2otp block8 data register10. - */ -#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x6a4) -/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W10_M (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S) -#define EFUSE_APB2OTP_BLOCK8_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W10_S 0 - -/** EFUSE_APB2OTP_BLK8_W11_REG register - * eFuse apb2otp block8 data register11. - */ -#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x6a8) -/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK8_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W11_M (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S) -#define EFUSE_APB2OTP_BLOCK8_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK8_W11_S 0 - -/** EFUSE_APB2OTP_BLK9_W1_REG register - * eFuse apb2otp block9 data register1. - */ -#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x6ac) -/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W1_M (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S) -#define EFUSE_APB2OTP_BLOCK9_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W1_S 0 - -/** EFUSE_APB2OTP_BLK9_W2_REG register - * eFuse apb2otp block9 data register2. - */ -#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x6b0) -/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W2_M (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S) -#define EFUSE_APB2OTP_BLOCK9_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W2_S 0 - -/** EFUSE_APB2OTP_BLK9_W3_REG register - * eFuse apb2otp block9 data register3. - */ -#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x6b4) -/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W3_M (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S) -#define EFUSE_APB2OTP_BLOCK9_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W3_S 0 - -/** EFUSE_APB2OTP_BLK9_W4_REG register - * eFuse apb2otp block9 data register4. - */ -#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x6b8) -/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W4_M (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S) -#define EFUSE_APB2OTP_BLOCK9_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W4_S 0 - -/** EFUSE_APB2OTP_BLK9_W5_REG register - * eFuse apb2otp block9 data register5. - */ -#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x6bc) -/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W5_M (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S) -#define EFUSE_APB2OTP_BLOCK9_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W5_S 0 - -/** EFUSE_APB2OTP_BLK9_W6_REG register - * eFuse apb2otp block9 data register6. - */ -#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x6c0) -/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W6_M (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S) -#define EFUSE_APB2OTP_BLOCK9_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W6_S 0 - -/** EFUSE_APB2OTP_BLK9_W7_REG register - * eFuse apb2otp block9 data register7. - */ -#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x6c4) -/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W7_M (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S) -#define EFUSE_APB2OTP_BLOCK9_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W7_S 0 - -/** EFUSE_APB2OTP_BLK9_W8_REG register - * eFuse apb2otp block9 data register8. - */ -#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x6c8) -/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W8_M (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S) -#define EFUSE_APB2OTP_BLOCK9_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W8_S 0 - -/** EFUSE_APB2OTP_BLK9_W9_REG register - * eFuse apb2otp block9 data register9. - */ -#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x6cc) -/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W9_M (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S) -#define EFUSE_APB2OTP_BLOCK9_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W9_S 0 - -/** EFUSE_APB2OTP_BLK9_W10_REG register - * eFuse apb2otp block9 data register10. - */ -#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x6d0) -/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W10_M (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S) -#define EFUSE_APB2OTP_BLOCK9_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W10_S 0 - -/** EFUSE_APB2OTP_BLK9_W11_REG register - * eFuse apb2otp block9 data register11. - */ -#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x6d4) -/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK9_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W11_M (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S) -#define EFUSE_APB2OTP_BLOCK9_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK9_W11_S 0 - -/** EFUSE_APB2OTP_BLK10_W1_REG register - * eFuse apb2otp block10 data register1. - */ -#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x6d8) -/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W1 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W1_M (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S) -#define EFUSE_APB2OTP_BLOCK10_W1_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W1_S 0 - -/** EFUSE_APB2OTP_BLK10_W2_REG register - * eFuse apb2otp block10 data register2. - */ -#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x6dc) -/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W2 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W2_M (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S) -#define EFUSE_APB2OTP_BLOCK10_W2_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W2_S 0 - -/** EFUSE_APB2OTP_BLK10_W3_REG register - * eFuse apb2otp block10 data register3. - */ -#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x6e0) -/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W3 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W3_M (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S) -#define EFUSE_APB2OTP_BLOCK10_W3_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W3_S 0 - -/** EFUSE_APB2OTP_BLK10_W4_REG register - * eFuse apb2otp block10 data register4. - */ -#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x6e4) -/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W4 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W4_M (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S) -#define EFUSE_APB2OTP_BLOCK10_W4_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W4_S 0 - -/** EFUSE_APB2OTP_BLK10_W5_REG register - * eFuse apb2otp block10 data register5. - */ -#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x6e8) -/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W5 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W5_M (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S) -#define EFUSE_APB2OTP_BLOCK10_W5_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W5_S 0 - -/** EFUSE_APB2OTP_BLK10_W6_REG register - * eFuse apb2otp block10 data register6. - */ -#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x6ec) -/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W6 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W6_M (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S) -#define EFUSE_APB2OTP_BLOCK10_W6_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W6_S 0 - -/** EFUSE_APB2OTP_BLK10_W7_REG register - * eFuse apb2otp block10 data register7. - */ -#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x6f0) -/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W7 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W7_M (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S) -#define EFUSE_APB2OTP_BLOCK10_W7_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W7_S 0 - -/** EFUSE_APB2OTP_BLK10_W8_REG register - * eFuse apb2otp block10 data register8. - */ -#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x6f4) -/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W8 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W8_M (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S) -#define EFUSE_APB2OTP_BLOCK10_W8_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W8_S 0 - -/** EFUSE_APB2OTP_BLK10_W9_REG register - * eFuse apb2otp block10 data register9. - */ -#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x6f8) -/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W9 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W9_M (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S) -#define EFUSE_APB2OTP_BLOCK10_W9_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W9_S 0 - -/** EFUSE_APB2OTP_BLK10_W10_REG register - * eFuse apb2otp block10 data register10. - */ -#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x6fc) -/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W10 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W10_M (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S) -#define EFUSE_APB2OTP_BLOCK10_W10_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W10_S 0 - -/** EFUSE_APB2OTP_BLK10_W11_REG register - * eFuse apb2otp block10 data register11. - */ -#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0x700) -/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ -#define EFUSE_APB2OTP_BLOCK10_W11 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W11_M (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S) -#define EFUSE_APB2OTP_BLOCK10_W11_V 0xFFFFFFFFU -#define EFUSE_APB2OTP_BLOCK10_W11_S 0 - -/** EFUSE_APB2OTP_EN_REG register - * eFuse apb2otp enable configuration register. - */ -#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0x708) -/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0; - * Apb2otp mode enable signal. - */ -#define EFUSE_APB2OTP_APB2OTP_EN (BIT(0)) -#define EFUSE_APB2OTP_APB2OTP_EN_M (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S) -#define EFUSE_APB2OTP_APB2OTP_EN_V 0x00000001U -#define EFUSE_APB2OTP_APB2OTP_EN_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/efuse_struct.h b/components/soc/esp32c5/register/soc/efuse_struct.h index 8e61447783..a94c274ba0 100644 --- a/components/soc/esp32c5/register/soc/efuse_struct.h +++ b/components/soc/esp32c5/register/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,167 +10,51 @@ extern "C" { #endif -/** Group: buffer0 registers */ -/** Type of pgm_data0 register - * Represents pgm_data0 +/** Group: program_data registers */ +/** Type of pgm_datan register + * Represents pgm_datan */ typedef union { struct { - /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. + /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth 32-bit data to be programmed. */ - uint32_t pgm_data_0:32; + uint32_t pgm_data_n:32; }; uint32_t val; -} efuse_pgm_data0_reg_t; +} efuse_pgm_datan_reg_t; -/** Type of pgm_data1 register - * Represents pgm_data1 +/** Type of pgm_check_valuen register + * Represents pgm_check_valuen */ typedef union { struct { - /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. + /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth RS code to be programmed. */ - uint32_t pgm_data_1:32; + uint32_t pgm_rs_data_n:32; }; uint32_t val; -} efuse_pgm_data1_reg_t; - -/** Type of pgm_data2 register - * Represents pgm_data2 - */ -typedef union { - struct { - /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_2:32; - }; - uint32_t val; -} efuse_pgm_data2_reg_t; - -/** Type of pgm_data3 register - * Represents pgm_data3 - */ -typedef union { - struct { - /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_3:32; - }; - uint32_t val; -} efuse_pgm_data3_reg_t; - -/** Type of pgm_data4 register - * Represents pgm_data4 - */ -typedef union { - struct { - /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_4:32; - }; - uint32_t val; -} efuse_pgm_data4_reg_t; - -/** Type of pgm_data5 register - * Represents pgm_data5 - */ -typedef union { - struct { - /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_5:32; - }; - uint32_t val; -} efuse_pgm_data5_reg_t; - -/** Type of pgm_data6 register - * Represents pgm_data6 - */ -typedef union { - struct { - /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_6:32; - }; - uint32_t val; -} efuse_pgm_data6_reg_t; - -/** Type of pgm_data7 register - * Represents pgm_data7 - */ -typedef union { - struct { - /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. - */ - uint32_t pgm_data_7:32; - }; - uint32_t val; -} efuse_pgm_data7_reg_t; - - -/** Group: buffer1 registers */ -/** Type of pgm_check_value0 register - * Represents pgm_check_value0 - */ -typedef union { - struct { - /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th RS code to be programmed. - */ - uint32_t pgm_rs_data_0:32; - }; - uint32_t val; -} efuse_pgm_check_value0_reg_t; - -/** Type of pgm_check_value1 register - * Represents pgm_check_value1 - */ -typedef union { - struct { - /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th RS code to be programmed. - */ - uint32_t pgm_rs_data_1:32; - }; - uint32_t val; -} efuse_pgm_check_value1_reg_t; - -/** Type of pgm_check_value2 register - * Represents pgm_check_value2 - */ -typedef union { - struct { - /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th RS code to be programmed. - */ - uint32_t pgm_rs_data_2:32; - }; - uint32_t val; -} efuse_pgm_check_value2_reg_t; +} efuse_pgm_check_valuen_reg_t; /** Group: block0 registers */ -/** Type of rd_wr_dis0 register +/** Type of rd_wr_dis register * Represents rd_wr_dis */ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled or - * enabled.\\ 1: Disabled\\ 0: Enabled\\ + * Represents whether programming of individual eFuse memory bit is disabled. For + * mapping between the bits of this field and the eFuse memory bits, please refer to + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled */ uint32_t wr_dis:32; }; uint32_t val; -} efuse_rd_wr_dis0_reg_t; +} efuse_rd_wr_dis_reg_t; /** Type of rd_repeat_data0 register * Represents rd_repeat_data @@ -178,90 +62,132 @@ typedef union { typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether reading of individual eFuse block (BLOCK4 \verb+~+ BLOCK10) is + * disabled. For mapping between the bits of this field and the eFuse blocks, please + * refer to Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled */ uint32_t rd_dis:7; - /** rd_reserve_0_39 : RW; bitpos: [7]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** bootloader_anti_rollback_secure_version_hi : RO; bitpos: [7]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the high part of the field). */ - uint32_t rd_reserve_0_39:1; + uint32_t bootloader_anti_rollback_secure_version_hi:1; /** dis_icache : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether cache is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note + * that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only + * when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Disabled + * 0: Enabled */ uint32_t dis_usb_jtag:1; - /** rd_reserve_0_42 : RW; bitpos: [10]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** bootloader_anti_rollback_en : RO; bitpos: [10]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. + * 1: Enabled + * 0: Disabled */ - uint32_t rd_reserve_0_42:1; + uint32_t bootloader_anti_rollback_en:1; /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether USB Serial/JTAG is disabled. + * 1: Disabled + * 0: Enabled + * + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether the function that forces chip into Download mode is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether SPI0 controller during boot\_mode\_download is disabled. + * 0: Enabled + * 1: Disabled */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether TWAI$^®$ function is disabled. + * 1: Disabled + * 0: Enabled */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Represents whether the selection between usb_to_jtag and pad_to_jtag through - * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether the selection of a JTAG signal source through the strapping pin + * value is enabled when all of + * \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}, + * \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and + * \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are + * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 1: Enabled + * 0: Disabled */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even - * number: enabled\\ + * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via + * HMAC. + * Odd count of bits with a value of 1: Disabled + * Even count of bits with a value of 1: Enabled */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ - * 0: enabled\\ + * Represents whether PAD JTAG is disabled in the hard way (permanently). + * 1: Disabled + * 0: Enabled */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode).\\ 1: disabled\\ 0: enabled\\ + * Represents whether flash encryption is disabled (except in SPI boot mode). + * 1: Disabled + * 0: Enabled */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [22:21]; default: 0; * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [24:23]; default: 0; * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not - * exchanged\\ + * Represents whether the D+ and D- pins is exchanged. + * 1: Exchanged + * 0: Not exchanged */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not - * functioned\\ + * Represents whether VDD SPI pin is functioned as GPIO. + * 1: Functioned + * 0: Not functioned */ uint32_t vdd_spi_as_gpio:1; - /** rd_reserve_0_59 : RW; bitpos: [31:27]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** wdt_delay_sel : RO; bitpos: [28:27]; default: 0; + * Represents RTC watchdog timeout threshold. + * 0: The originally configured STG0 threshold × 2 + * 1: The originally configured STG0 threshold × 4 + * 2: The originally configured STG0 threshold × 8 + * 3: The originally configured STG0 threshold × 16 */ - uint32_t rd_reserve_0_59:5; + uint32_t wdt_delay_sel:2; + /** bootloader_anti_rollback_secure_version_lo : RO; bitpos: [31:29]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader (the low part of the field). + */ + uint32_t bootloader_anti_rollback_secure_version_lo:3; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; @@ -272,68 +198,112 @@ typedef union { typedef union { struct { /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0; - * Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled - * \\ 0: enabled.\\ + * Represents whether the new key deployment of key manager is disabled. + * Bit0: Represents whether the new ECDSA key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is + * disabled + * 0: Enabled + * 1: Disabled + * Bit2: Represents whether the new HMAC key deployment is disabled + * 0: Enabled + * 1: Disabled + * Bit3: Represents whether the new DS key deployment is disabled + * 0: Enabled + * 1: Disabled */ uint32_t km_disable_deploy_mode:4; /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0; - * Set the bits to control key manager random number switch cycle. 0: control by - * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + * Represents the cycle at which the Key Manager switches random numbers. + * 0: Controlled by the + * \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For + * more information, please refer to Chapter \ref{mod:keymng} + * \textit{\nameref{mod:keymng}} + * 1: 8 Key Manager clock cycles + * 2: 16 Key Manager clock cycles + * 3: 32 Key Manager clock cycles */ uint32_t km_rnd_switch_cycle:2; /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0; - * Set each bit to control whether corresponding key can only be deployed once. 1 is - * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds + * Represents whether the corresponding key can be deployed only once. + * Bit0: Represents whether the ECDSA key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit2: Represents whether the HMAC key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once + * Bit3: Represents whether the DS key can be deployed only once + * 0: The key can be deployed multiple times + * 1: The key can be deployed only once */ uint32_t km_deploy_only_once:4; /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0; - * Set each bit to control whether corresponding key must come from key manager. 1 is - * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds + * Represents whether the corresponding key must come from Key Manager. + * Bit0: Represents whether the ECDSA key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key + * Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit2: Represents whether the HMAC key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager + * Bit3: Represents whether the DS key must come from Key Manager. + * 0: The key does not need to come from Key Manager + * 1: The key must come from Key Manager */ uint32_t force_use_key_manager_key:4; /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0; - * Set this bit to disable software written init key, and force use efuse_init_key. + * Represents whether to disable the use of the initialization key written by software + * and instead force use efuse\_init\_key. + * 0: Enable + * 1: Disable */ uint32_t force_disable_sw_init_key:1; - /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [15]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader. + * 1: Enable + * 0: Disable */ - uint32_t rd_reserve_0_79:1; - /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ - */ - uint32_t wdt_delay_sel:2; - /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of - * 1: enabled\\ Even number of 1: disabled\\ + uint32_t bootloader_anti_rollback_update_in_rom:1; + /** spi_boot_crypt_cnt : RO; bitpos: [18:16]; default: 0; + * Represents whether SPI boot encryption/decryption is enabled. + * Odd count of bits with a value of 1: Enabled + * Even count of bits with a value of 1: Disabled */ uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + /** secure_boot_key_revoke0 : RO; bitpos: [19]; default: 0; + * Represents whether revoking Secure Boot key digest 0 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + /** secure_boot_key_revoke1 : RO; bitpos: [20]; default: 0; + * Represents whether revoking Secure Boot key digest 1 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + /** secure_boot_key_revoke2 : RO; bitpos: [21]; default: 0; + * Represents whether revoking Secure Boot key digest 2 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. + /** key_purpose_0 : RO; bitpos: [26:22]; default: 0; + * Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}. */ - uint32_t key_purpose_0:4; - /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. + uint32_t key_purpose_0:5; + /** key_purpose_1 : RO; bitpos: [31:27]; default: 0; + * Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}. */ - uint32_t key_purpose_1:4; + uint32_t key_purpose_1:5; }; uint32_t val; } efuse_rd_repeat_data1_reg_t; @@ -343,51 +313,63 @@ typedef union { */ typedef union { struct { - /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. + /** key_purpose_2 : RO; bitpos: [4:0]; default: 0; + * Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}. */ - uint32_t key_purpose_2:4; - /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. + uint32_t key_purpose_2:5; + /** key_purpose_3 : RO; bitpos: [9:5]; default: 0; + * Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}. */ - uint32_t key_purpose_3:4; - /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. + uint32_t key_purpose_3:5; + /** key_purpose_4 : RO; bitpos: [14:10]; default: 0; + * Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}. */ - uint32_t key_purpose_4:4; - /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. + uint32_t key_purpose_4:5; + /** key_purpose_5 : RO; bitpos: [19:15]; default: 0; + * Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}. */ - uint32_t key_purpose_5:4; - /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. + uint32_t key_purpose_5:5; + /** sec_dpa_level : RO; bitpos: [21:20]; default: 0; + * Represents the security level of anti-DPA attack. The level is adjusted by + * configuring the clock random frequency division mode. + * 0: Security level is SEC\_DPA\_OFF + * 1: Security level is SEC\_DPA\_LOW + * 2: Security level is SEC\_DPA\_MIDDLE + * 3: Security level is SEC\_DPA\_HIGH + * For more information, please refer to Chapter \ref{mod:sysreg} + * \textit{\nameref{mod:sysreg}} > Section + * \ref{sec:sysreg-anti-dpa-attack-security-control} + * \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. */ uint32_t sec_dpa_level:2; - /** rd_reserve_0_114 : RW; bitpos: [19:18]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** recovery_bootloader_flash_sector_hi : RO; bitpos: [24:22]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The high part of the field). */ - uint32_t rd_reserve_0_114:2; - /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + uint32_t recovery_bootloader_flash_sector_hi:3; + /** secure_boot_en : RO; bitpos: [25]; default: 0; + * Represents whether Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + /** secure_boot_aggressive_revoke : RO; bitpos: [26]; default: 0; + * Represents whether aggressive revocation of Secure Boot is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t secure_boot_aggressive_revoke:1; - /** rd_reserve_0_118 : RW; bitpos: [26:22]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func - */ - uint32_t rd_reserve_0_118:5; /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0; - * Set this bitto configure flash encryption use xts-128 key. else use xts-256 key. + * Represents which key flash encryption uses. + * 0: XTS-AES-256 key + * 1: XTS-AES-128 key */ uint32_t km_xts_key_length_256:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. + * Represents the flash waiting time after power-up. Measurement unit: ms. When the + * value is less than 15, the waiting time is the programmed value. Otherwise, the + * waiting time is a fixed value, i.e. 30 ms. */ uint32_t flash_tpuw:4; }; @@ -400,73 +382,90 @@ typedef union { typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether Download mode is disable or enable. 1. Disable + * 0: Enable. */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether direct boot mode is disabled or enabled. 1. Disable + * 0: Enable. */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable + * 0: Enable. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** lock_km_key : RO; bitpos: [3]; default: 0; - * Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ + * Represents whether the keys in the Key Manager are locked after deployment. + * 0: Not locked + * 1: Locked */ uint32_t lock_km_key:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ - * 1: Disable\\ 0: Enable\\ + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * Disable + * 0: Enable. */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: - * disabled\\ + * Represents whether security download is enabled. Only downloading into flash is + * supported. Reading/writing RAM or registers is not supported (i.e. stub download is + * not supported). + * 1: Enabled + * 0: Disabled */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable - * printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset - * at high level\\ 11: force disable printing\\ + * Represents the type of UART printing. + * 0: Force enable printing. + * 1: Enable printing when GPIO27 is reset at low level. + * 2: Enable printing when GPIO27 is reset at high level. + * 3: Force disable printing. */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot.\\ - * 1: forced\\ 0:not forced\\ + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: Forced. + * 0: Not forced. */ uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. + /** secure_version : RO; bitpos: [17:9]; default: 0; + * Represents the app secure version used by ESP-IDF anti-rollback feature. */ - uint32_t secure_version:16; + uint32_t secure_version:9; + uint32_t reserved_18:7; /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. + * 1: Disabled + * 0: Enabled */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Represents whether the hysteresis function of PAD0 – PAD27 is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t hys_en_pad:1; /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; - * Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: - * Moderate 1. Low\\ 0: Disabled\\ + * Represents the pseudo round level of XTS-AES anti-DPA attack. + * 0: Disabled + * 1: Low + * 2: Moderate + * 3: High */ uint32_t xts_dpa_pseudo_level:2; /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0; - * Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: - * Disable.\\ + * Represents whether XTS-AES anti-DPA attack clock is enabled. + * 0: Disable + * 1: Enabled */ uint32_t xts_dpa_clk_enable:1; - /** rd_reserve_0_158 : RW; bitpos: [31:30]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + uint32_t reserved_30:1; + /** ecdsa_p384_enable : RO; bitpos: [31]; default: 0; + * Represents if the chip supports ECDSA P384 */ - uint32_t rd_reserve_0_158:2; + uint32_t ecdsa_p384_enable:1; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; @@ -477,34 +476,42 @@ typedef union { typedef union { struct { /** huk_gen_state : RO; bitpos: [8:0]; default: 0; - * Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ - * Even of 1 is valid.\\ + * Represents whether the HUK generate mode is valid. + * Odd count of bits with a value of 1: Invalid + * Even count of bits with a value of 1: Valid */ uint32_t huk_gen_state:9; /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0; - * Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used. - * If this field contains Odd number bit '1': Enable 48MHz XTAL\\ Even number bit '1': - * Enable 40MHz XTAL. + * Determines the frequency of the XTAL clock alone in \textbf{SPI Boot} mode, or + * together with \hyperref[fielddesc:EFUSEXTAL48MSELMODE]{EFUSE\_XTAL\_48M\_SEL\_MODE} + * in \textbf{Joint Download Boot} mode. For more information, please refer to Chapter + * \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}. + * Odd count of bits with a value of 1: 48 MHz + * Even count of bits with a value of 1: 40 MHz */ uint32_t xtal_48m_sel:3; /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0; - * Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: - * eFuse\\ 0: strapping-PAD-state. + * Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. + * For more information, please refer to Chapter \ref{mod:bootctrl} + * \textit{\nameref{mod:bootctrl}}. + * 0: Strapping PAD state + * 1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse */ uint32_t xtal_48m_sel_mode:1; - /** ecdsa_disable_p192 : RO; bitpos: [13]; default: 0; - * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. - */ - uint32_t ecdsa_disable_p192:1; - /** ecc_force_const_time : RO; bitpos: [14]; default: 0; - * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. - * \\ 0: Disable. + /** ecc_force_const_time : RO; bitpos: [13]; default: 0; + * Represents whether to force ECC to use constant-time mode for point multiplication + * calculation. + * 0: Not force + * 1: Force */ uint32_t ecc_force_const_time:1; - /** rd_reserve_0_175 : RW; bitpos: [31:15]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** recovery_bootloader_flash_sector_lo : RO; bitpos: [22:14]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. (The low part of the field). */ - uint32_t rd_reserve_0_175:17; + uint32_t recovery_bootloader_flash_sector_lo:9; + uint32_t reserved_23:9; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; @@ -607,38 +614,15 @@ typedef union { */ typedef union { struct { - /** trim_n_bias : R; bitpos: [4:0]; default: 0; - * PADC CAL N bias + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t trim_n_bias:5; - /** trim_p_bias : R; bitpos: [9:5]; default: 0; - * PADC CAL P bias + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. */ - uint32_t trim_p_bias:5; - /** active_hp_dbias : R; bitpos: [13:10]; default: 0; - * Active HP DBIAS of fixed voltage - */ - uint32_t active_hp_dbias:4; - /** active_lp_dbias : R; bitpos: [17:14]; default: 0; - * Active LP DBIAS of fixed voltage - */ - uint32_t active_lp_dbias:4; - /** lslp_hp_dbg : R; bitpos: [19:18]; default: 0; - * LSLP HP DBG of fixed voltage - */ - uint32_t lslp_hp_dbg:2; - /** lslp_hp_dbias : R; bitpos: [23:20]; default: 0; - * LSLP HP DBIAS of fixed voltage - */ - uint32_t lslp_hp_dbias:4; - /** dslp_lp_dbg : R; bitpos: [27:24]; default: 0; - * DSLP LP DBG of fixed voltage - */ - uint32_t dslp_lp_dbg:4; - /** dslp_lp_dbias : R; bitpos: [31:28]; default: 0; - * DSLP LP DBIAS of fixed voltage - */ - uint32_t dslp_lp_dbias:4; + uint32_t sys_data_part0_0:14; }; uint32_t val; } efuse_rd_mac_sys3_reg_t; @@ -648,18 +632,10 @@ typedef union { */ typedef union { struct { - /** dslp_lp_dbias_1 : R; bitpos: [0]; default: 0; - * DSLP LP DBIAS of fixed voltage + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. */ - uint32_t dslp_lp_dbias_1:1; - /** lp_hp_dbias_vol_gap : R; bitpos: [5:1]; default: 0; - * DBIAS gap between LP and HP - */ - uint32_t lp_hp_dbias_vol_gap:5; - /** reserved_1_134 : R; bitpos: [31:6]; default: 0; - * reserved - */ - uint32_t reserved_1_134:26; + uint32_t sys_data_part0_1:32; }; uint32_t val; } efuse_rd_mac_sys4_reg_t; @@ -670,7 +646,7 @@ typedef union { typedef union { struct { /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. + * Represents the third 32-bit of zeroth part of system data. */ uint32_t sys_data_part0_2:32; }; @@ -679,1029 +655,138 @@ typedef union { /** Group: block2 registers */ -/** Type of rd_sys_part1_data0 register - * Represents rd_sys_part1_data0 +/** Type of rd_sys_part1_datan register + * Represents rd_sys_part1_datan */ typedef union { struct { - /** optional_unique_id : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID + /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ - uint32_t optional_unique_id:32; + uint32_t sys_data_part1_n:32; }; uint32_t val; -} efuse_rd_sys_part1_data0_reg_t; - -/** Type of rd_sys_part1_data1 register - * Represents rd_sys_part1_data1 - */ -typedef union { - struct { - /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id_1:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data1_reg_t; - -/** Type of rd_sys_part1_data2 register - * Represents rd_sys_part1_data2 - */ -typedef union { - struct { - /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id_2:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data2_reg_t; - -/** Type of rd_sys_part1_data3 register - * Represents rd_sys_part1_data3 - */ -typedef union { - struct { - /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; - * Optional unique 128-bit ID - */ - uint32_t optional_unique_id_3:32; - }; - uint32_t val; -} efuse_rd_sys_part1_data3_reg_t; - -/** Type of rd_sys_part1_data4 register - * Represents rd_sys_part1_data4 - */ -typedef union { - struct { - /** temperature_sensor : R; bitpos: [8:0]; default: 0; - * Temperature calibration data - */ - uint32_t temperature_sensor:9; - /** ocode : R; bitpos: [16:9]; default: 0; - * ADC OCode - */ - uint32_t ocode:8; - /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0; - * Average initcode of ADC1 atten0 - */ - uint32_t adc1_ave_initcode_atten0:10; - /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0; - * Average initcode of ADC1 atten0 - */ - uint32_t adc1_ave_initcode_atten1:5; - }; - uint32_t val; -} efuse_rd_sys_part1_data4_reg_t; - -/** Type of rd_sys_part1_data5 register - * Represents rd_sys_part1_data5 - */ -typedef union { - struct { - /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0; - * Average initcode of ADC1 atten0 - */ - uint32_t adc1_ave_initcode_atten1_1:5; - /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0; - * Average initcode of ADC1 atten0 - */ - uint32_t adc1_ave_initcode_atten2:10; - /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0; - * Average initcode of ADC1 atten0 - */ - uint32_t adc1_ave_initcode_atten3:10; - /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; - * HI DOUT of ADC1 atten0 - */ - uint32_t adc1_hi_dout_atten0:7; - }; - uint32_t val; -} efuse_rd_sys_part1_data5_reg_t; - -/** Type of rd_sys_part1_data6 register - * Represents rd_sys_part1_data6 - */ -typedef union { - struct { - /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; - * HI DOUT of ADC1 atten0 - */ - uint32_t adc1_hi_dout_atten0_1:3; - /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; - * HI DOUT of ADC1 atten1 - */ - uint32_t adc1_hi_dout_atten1:10; - /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; - * HI DOUT of ADC1 atten2 - */ - uint32_t adc1_hi_dout_atten2:10; - /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; - * HI DOUT of ADC1 atten3 - */ - uint32_t adc1_hi_dout_atten3:9; - }; - uint32_t val; -} efuse_rd_sys_part1_data6_reg_t; - -/** Type of rd_sys_part1_data7 register - * Represents rd_sys_part1_data7 - */ -typedef union { - struct { - /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; - * HI DOUT of ADC1 atten3 - */ - uint32_t adc1_hi_dout_atten3_1:1; - /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; - * Gap between ADC1 CH0 and average initcode - */ - uint32_t adc1_ch0_atten0_initcode_diff:4; - /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; - * Gap between ADC1 CH1 and average initcode - */ - uint32_t adc1_ch1_atten0_initcode_diff:4; - /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; - * Gap between ADC1 CH2 and average initcode - */ - uint32_t adc1_ch2_atten0_initcode_diff:4; - /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; - * Gap between ADC1 CH3 and average initcode - */ - uint32_t adc1_ch3_atten0_initcode_diff:4; - /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0; - * Gap between ADC1 CH4 and average initcode - */ - uint32_t adc1_ch4_atten0_initcode_diff:4; - /** adc1_ch5_atten0_initcode_diff : R; bitpos: [24:21]; default: 0; - * Gap between ADC1 CH5 and average initcode - */ - uint32_t adc1_ch5_atten0_initcode_diff:4; - /** reserved_2_249 : R; bitpos: [31:25]; default: 0; - * reserved - */ - uint32_t reserved_2_249:7; - }; - uint32_t val; -} efuse_rd_sys_part1_data7_reg_t; +} efuse_rd_sys_part1_datan_reg_t; /** Group: block3 registers */ -/** Type of rd_usr_data0 register - * Represents rd_usr_data0 +/** Type of rd_usr_datan register + * Represents rd_usr_datan */ typedef union { struct { - /** usr_data0 : RO; bitpos: [31:0]; default: 0; + /** usr_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ - uint32_t usr_data0:32; + uint32_t usr_datan:32; }; uint32_t val; -} efuse_rd_usr_data0_reg_t; - -/** Type of rd_usr_data1 register - * Represents rd_usr_data1 - */ -typedef union { - struct { - /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_data1:32; - }; - uint32_t val; -} efuse_rd_usr_data1_reg_t; - -/** Type of rd_usr_data2 register - * Represents rd_usr_data2 - */ -typedef union { - struct { - /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_data2:32; - }; - uint32_t val; -} efuse_rd_usr_data2_reg_t; - -/** Type of rd_usr_data3 register - * Represents rd_usr_data3 - */ -typedef union { - struct { - /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_data3:32; - }; - uint32_t val; -} efuse_rd_usr_data3_reg_t; - -/** Type of rd_usr_data4 register - * Represents rd_usr_data4 - */ -typedef union { - struct { - /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_data4:32; - }; - uint32_t val; -} efuse_rd_usr_data4_reg_t; - -/** Type of rd_usr_data5 register - * Represents rd_usr_data5 - */ -typedef union { - struct { - /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_data5:32; - }; - uint32_t val; -} efuse_rd_usr_data5_reg_t; - -/** Type of rd_usr_data6 register - * Represents rd_usr_data6 - */ -typedef union { - struct { - /** reserved_3_192 : R; bitpos: [7:0]; default: 0; - * reserved - */ - uint32_t reserved_3_192:8; - /** custom_mac : R; bitpos: [31:8]; default: 0; - * Custom MAC - */ - uint32_t custom_mac:24; - }; - uint32_t val; -} efuse_rd_usr_data6_reg_t; - -/** Type of rd_usr_data7 register - * Represents rd_usr_data7 - */ -typedef union { - struct { - /** custom_mac_1 : R; bitpos: [23:0]; default: 0; - * Custom MAC - */ - uint32_t custom_mac_1:24; - /** reserved_3_248 : R; bitpos: [31:24]; default: 0; - * reserved - */ - uint32_t reserved_3_248:8; - }; - uint32_t val; -} efuse_rd_usr_data7_reg_t; +} efuse_rd_usr_datan_reg_t; /** Group: block4 registers */ -/** Type of rd_key0_data0 register - * Represents rd_key0_data0 +/** Type of rd_key0_datan register + * Represents rd_key0_datan */ typedef union { struct { - /** key0_data0 : RO; bitpos: [31:0]; default: 0; + /** key0_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ - uint32_t key0_data0:32; + uint32_t key0_datan:32; }; uint32_t val; -} efuse_rd_key0_data0_reg_t; - -/** Type of rd_key0_data1 register - * Represents rd_key0_data1 - */ -typedef union { - struct { - /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data1:32; - }; - uint32_t val; -} efuse_rd_key0_data1_reg_t; - -/** Type of rd_key0_data2 register - * Represents rd_key0_data2 - */ -typedef union { - struct { - /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data2:32; - }; - uint32_t val; -} efuse_rd_key0_data2_reg_t; - -/** Type of rd_key0_data3 register - * Represents rd_key0_data3 - */ -typedef union { - struct { - /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data3:32; - }; - uint32_t val; -} efuse_rd_key0_data3_reg_t; - -/** Type of rd_key0_data4 register - * Represents rd_key0_data4 - */ -typedef union { - struct { - /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data4:32; - }; - uint32_t val; -} efuse_rd_key0_data4_reg_t; - -/** Type of rd_key0_data5 register - * Represents rd_key0_data5 - */ -typedef union { - struct { - /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data5:32; - }; - uint32_t val; -} efuse_rd_key0_data5_reg_t; - -/** Type of rd_key0_data6 register - * Represents rd_key0_data6 - */ -typedef union { - struct { - /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data6:32; - }; - uint32_t val; -} efuse_rd_key0_data6_reg_t; - -/** Type of rd_key0_data7 register - * Represents rd_key0_data7 - */ -typedef union { - struct { - /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_data7:32; - }; - uint32_t val; -} efuse_rd_key0_data7_reg_t; +} efuse_rd_key0_datan_reg_t; /** Group: block5 registers */ -/** Type of rd_key1_data0 register - * Represents rd_key1_data0 +/** Type of rd_key1_datan register + * Represents rd_key1_datan */ typedef union { struct { - /** key1_data0 : RO; bitpos: [31:0]; default: 0; + /** key1_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ - uint32_t key1_data0:32; + uint32_t key1_datan:32; }; uint32_t val; -} efuse_rd_key1_data0_reg_t; - -/** Type of rd_key1_data1 register - * Represents rd_key1_data1 - */ -typedef union { - struct { - /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data1:32; - }; - uint32_t val; -} efuse_rd_key1_data1_reg_t; - -/** Type of rd_key1_data2 register - * Represents rd_key1_data2 - */ -typedef union { - struct { - /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data2:32; - }; - uint32_t val; -} efuse_rd_key1_data2_reg_t; - -/** Type of rd_key1_data3 register - * Represents rd_key1_data3 - */ -typedef union { - struct { - /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data3:32; - }; - uint32_t val; -} efuse_rd_key1_data3_reg_t; - -/** Type of rd_key1_data4 register - * Represents rd_key1_data4 - */ -typedef union { - struct { - /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data4:32; - }; - uint32_t val; -} efuse_rd_key1_data4_reg_t; - -/** Type of rd_key1_data5 register - * Represents rd_key1_data5 - */ -typedef union { - struct { - /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data5:32; - }; - uint32_t val; -} efuse_rd_key1_data5_reg_t; - -/** Type of rd_key1_data6 register - * Represents rd_key1_data6 - */ -typedef union { - struct { - /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data6:32; - }; - uint32_t val; -} efuse_rd_key1_data6_reg_t; - -/** Type of rd_key1_data7 register - * Represents rd_key1_data7 - */ -typedef union { - struct { - /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_data7:32; - }; - uint32_t val; -} efuse_rd_key1_data7_reg_t; +} efuse_rd_key1_datan_reg_t; /** Group: block6 registers */ -/** Type of rd_key2_data0 register - * Represents rd_key2_data0 +/** Type of rd_key2_datan register + * Represents rd_key2_datan */ typedef union { struct { - /** key2_data0 : RO; bitpos: [31:0]; default: 0; + /** key2_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ - uint32_t key2_data0:32; + uint32_t key2_datan:32; }; uint32_t val; -} efuse_rd_key2_data0_reg_t; - -/** Type of rd_key2_data1 register - * Represents rd_key2_data1 - */ -typedef union { - struct { - /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data1:32; - }; - uint32_t val; -} efuse_rd_key2_data1_reg_t; - -/** Type of rd_key2_data2 register - * Represents rd_key2_data2 - */ -typedef union { - struct { - /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data2:32; - }; - uint32_t val; -} efuse_rd_key2_data2_reg_t; - -/** Type of rd_key2_data3 register - * Represents rd_key2_data3 - */ -typedef union { - struct { - /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data3:32; - }; - uint32_t val; -} efuse_rd_key2_data3_reg_t; - -/** Type of rd_key2_data4 register - * Represents rd_key2_data4 - */ -typedef union { - struct { - /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data4:32; - }; - uint32_t val; -} efuse_rd_key2_data4_reg_t; - -/** Type of rd_key2_data5 register - * Represents rd_key2_data5 - */ -typedef union { - struct { - /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data5:32; - }; - uint32_t val; -} efuse_rd_key2_data5_reg_t; - -/** Type of rd_key2_data6 register - * Represents rd_key2_data6 - */ -typedef union { - struct { - /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data6:32; - }; - uint32_t val; -} efuse_rd_key2_data6_reg_t; - -/** Type of rd_key2_data7 register - * Represents rd_key2_data7 - */ -typedef union { - struct { - /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_data7:32; - }; - uint32_t val; -} efuse_rd_key2_data7_reg_t; +} efuse_rd_key2_datan_reg_t; /** Group: block7 registers */ -/** Type of rd_key3_data0 register - * Represents rd_key3_data0 +/** Type of rd_key3_datan register + * Represents rd_key3_datan */ typedef union { struct { - /** key3_data0 : RO; bitpos: [31:0]; default: 0; + /** key3_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ - uint32_t key3_data0:32; + uint32_t key3_datan:32; }; uint32_t val; -} efuse_rd_key3_data0_reg_t; - -/** Type of rd_key3_data1 register - * Represents rd_key3_data1 - */ -typedef union { - struct { - /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data1:32; - }; - uint32_t val; -} efuse_rd_key3_data1_reg_t; - -/** Type of rd_key3_data2 register - * Represents rd_key3_data2 - */ -typedef union { - struct { - /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data2:32; - }; - uint32_t val; -} efuse_rd_key3_data2_reg_t; - -/** Type of rd_key3_data3 register - * Represents rd_key3_data3 - */ -typedef union { - struct { - /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data3:32; - }; - uint32_t val; -} efuse_rd_key3_data3_reg_t; - -/** Type of rd_key3_data4 register - * Represents rd_key3_data4 - */ -typedef union { - struct { - /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data4:32; - }; - uint32_t val; -} efuse_rd_key3_data4_reg_t; - -/** Type of rd_key3_data5 register - * Represents rd_key3_data5 - */ -typedef union { - struct { - /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data5:32; - }; - uint32_t val; -} efuse_rd_key3_data5_reg_t; - -/** Type of rd_key3_data6 register - * Represents rd_key3_data6 - */ -typedef union { - struct { - /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data6:32; - }; - uint32_t val; -} efuse_rd_key3_data6_reg_t; - -/** Type of rd_key3_data7 register - * Represents rd_key3_data7 - */ -typedef union { - struct { - /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_data7:32; - }; - uint32_t val; -} efuse_rd_key3_data7_reg_t; +} efuse_rd_key3_datan_reg_t; /** Group: block8 registers */ -/** Type of rd_key4_data0 register - * Represents rd_key4_data0 +/** Type of rd_key4_datan register + * Represents rd_key4_datan */ typedef union { struct { - /** key4_data0 : RO; bitpos: [31:0]; default: 0; + /** key4_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ - uint32_t key4_data0:32; + uint32_t key4_datan:32; }; uint32_t val; -} efuse_rd_key4_data0_reg_t; - -/** Type of rd_key4_data1 register - * Represents rd_key4_data1 - */ -typedef union { - struct { - /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data1:32; - }; - uint32_t val; -} efuse_rd_key4_data1_reg_t; - -/** Type of rd_key4_data2 register - * Represents rd_key4_data2 - */ -typedef union { - struct { - /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data2:32; - }; - uint32_t val; -} efuse_rd_key4_data2_reg_t; - -/** Type of rd_key4_data3 register - * Represents rd_key4_data3 - */ -typedef union { - struct { - /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data3:32; - }; - uint32_t val; -} efuse_rd_key4_data3_reg_t; - -/** Type of rd_key4_data4 register - * Represents rd_key4_data4 - */ -typedef union { - struct { - /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data4:32; - }; - uint32_t val; -} efuse_rd_key4_data4_reg_t; - -/** Type of rd_key4_data5 register - * Represents rd_key4_data5 - */ -typedef union { - struct { - /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data5:32; - }; - uint32_t val; -} efuse_rd_key4_data5_reg_t; - -/** Type of rd_key4_data6 register - * Represents rd_key4_data6 - */ -typedef union { - struct { - /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data6:32; - }; - uint32_t val; -} efuse_rd_key4_data6_reg_t; - -/** Type of rd_key4_data7 register - * Represents rd_key4_data7 - */ -typedef union { - struct { - /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_data7:32; - }; - uint32_t val; -} efuse_rd_key4_data7_reg_t; +} efuse_rd_key4_datan_reg_t; /** Group: block9 registers */ -/** Type of rd_key5_data0 register - * Represents rd_key5_data0 +/** Type of rd_key5_datan register + * Represents rd_key5_datan */ typedef union { struct { - /** key5_data0 : RO; bitpos: [31:0]; default: 0; + /** key5_datan : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ - uint32_t key5_data0:32; + uint32_t key5_datan:32; }; uint32_t val; -} efuse_rd_key5_data0_reg_t; - -/** Type of rd_key5_data1 register - * Represents rd_key5_data1 - */ -typedef union { - struct { - /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data1:32; - }; - uint32_t val; -} efuse_rd_key5_data1_reg_t; - -/** Type of rd_key5_data2 register - * Represents rd_key5_data2 - */ -typedef union { - struct { - /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data2:32; - }; - uint32_t val; -} efuse_rd_key5_data2_reg_t; - -/** Type of rd_key5_data3 register - * Represents rd_key5_data3 - */ -typedef union { - struct { - /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data3:32; - }; - uint32_t val; -} efuse_rd_key5_data3_reg_t; - -/** Type of rd_key5_data4 register - * Represents rd_key5_data4 - */ -typedef union { - struct { - /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data4:32; - }; - uint32_t val; -} efuse_rd_key5_data4_reg_t; - -/** Type of rd_key5_data5 register - * Represents rd_key5_data5 - */ -typedef union { - struct { - /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data5:32; - }; - uint32_t val; -} efuse_rd_key5_data5_reg_t; - -/** Type of rd_key5_data6 register - * Represents rd_key5_data6 - */ -typedef union { - struct { - /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data6:32; - }; - uint32_t val; -} efuse_rd_key5_data6_reg_t; - -/** Type of rd_key5_data7 register - * Represents rd_key5_data7 - */ -typedef union { - struct { - /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_data7:32; - }; - uint32_t val; -} efuse_rd_key5_data7_reg_t; +} efuse_rd_key5_datan_reg_t; /** Group: block10 registers */ -/** Type of rd_sys_part2_data0 register - * Represents rd_sys_part2_data0 +/** Type of rd_sys_part2_datan register + * Represents rd_sys_part2_datan */ typedef union { struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ - uint32_t sys_data_part2_0:32; + uint32_t sys_data_part2_n:32; }; uint32_t val; -} efuse_rd_sys_part2_data0_reg_t; - -/** Type of rd_sys_part2_data1 register - * Represents rd_sys_part2_data1 - */ -typedef union { - struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_1:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data1_reg_t; - -/** Type of rd_sys_part2_data2 register - * Represents rd_sys_part2_data2 - */ -typedef union { - struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_2:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data2_reg_t; - -/** Type of rd_sys_part2_data3 register - * Represents rd_sys_part2_data3 - */ -typedef union { - struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_3:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data3_reg_t; - -/** Type of rd_sys_part2_data4 register - * Represents rd_sys_part2_data4 - */ -typedef union { - struct { - /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_4:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data4_reg_t; - -/** Type of rd_sys_part2_data5 register - * Represents rd_sys_part2_data5 - */ -typedef union { - struct { - /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_5:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data5_reg_t; - -/** Type of rd_sys_part2_data6 register - * Represents rd_sys_part2_data6 - */ -typedef union { - struct { - /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_6:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data6_reg_t; - -/** Type of rd_sys_part2_data7 register - * Represents rd_sys_part2_data7 - */ -typedef union { - struct { - /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_7:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data7_reg_t; +} efuse_rd_sys_part2_datan_reg_t; /** Group: block0 error report registers */ @@ -1714,7 +799,10 @@ typedef union { * Represents the programming error of EFUSE_RD_DIS */ uint32_t rd_dis_err:7; - uint32_t reserved_7:1; + /** bootloader_anti_rollback_secure_version_hi_err : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI + */ + uint32_t bootloader_anti_rollback_secure_version_hi_err:1; /** dis_icache_err : RO; bitpos: [8]; default: 0; * Represents the programming error of EFUSE_DIS_ICACHE */ @@ -1723,9 +811,13 @@ typedef union { * Represents the programming error of EFUSE_DIS_USB_JTAG */ uint32_t dis_usb_jtag_err:1; - uint32_t reserved_10:1; + /** bootloader_anti_rollback_en_err : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ + uint32_t bootloader_anti_rollback_en_err:1; /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; @@ -1758,10 +850,12 @@ typedef union { uint32_t dis_download_manual_encrypt_err:1; /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; * Represents the programming error of EFUSE_USB_DREFH + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usb_drefh_err:2; /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; * Represents the programming error of EFUSE_USB_DREFL + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usb_drefl_err:2; /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; @@ -1772,7 +866,14 @@ typedef union { * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO */ uint32_t vdd_spi_as_gpio_err:1; - uint32_t reserved_27:5; + /** wdt_delay_sel_err : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ + uint32_t wdt_delay_sel_err:2; + /** bootloader_anti_rollback_secure_version_lo_err : RO; bitpos: [31:29]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO + */ + uint32_t bootloader_anti_rollback_secure_version_lo_err:3; }; uint32_t val; } efuse_rd_repeat_data_err0_reg_t; @@ -1802,35 +903,34 @@ typedef union { * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY */ uint32_t force_disable_sw_init_key_err:1; - uint32_t reserved_15:1; - /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL + /** bootloader_anti_rollback_update_in_rom_err : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM */ - uint32_t wdt_delay_sel_err:2; - /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + uint32_t bootloader_anti_rollback_update_in_rom_err:1; + /** spi_boot_crypt_cnt_err : RO; bitpos: [18:16]; default: 0; * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ uint32_t spi_boot_crypt_cnt_err:3; - /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + /** secure_boot_key_revoke0_err : RO; bitpos: [19]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ uint32_t secure_boot_key_revoke0_err:1; - /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + /** secure_boot_key_revoke1_err : RO; bitpos: [20]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ uint32_t secure_boot_key_revoke1_err:1; - /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + /** secure_boot_key_revoke2_err : RO; bitpos: [21]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ uint32_t secure_boot_key_revoke2_err:1; - /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + /** key_purpose_0_err : RO; bitpos: [26:22]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ - uint32_t key_purpose_0_err:4; - /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + uint32_t key_purpose_0_err:5; + /** key_purpose_1_err : RO; bitpos: [31:27]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ - uint32_t key_purpose_1_err:4; + uint32_t key_purpose_1_err:5; }; uint32_t val; } efuse_rd_repeat_data_err1_reg_t; @@ -1840,36 +940,38 @@ typedef union { */ typedef union { struct { - /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + /** key_purpose_2_err : RO; bitpos: [4:0]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ - uint32_t key_purpose_2_err:4; - /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + uint32_t key_purpose_2_err:5; + /** key_purpose_3_err : RO; bitpos: [9:5]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ - uint32_t key_purpose_3_err:4; - /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + uint32_t key_purpose_3_err:5; + /** key_purpose_4_err : RO; bitpos: [14:10]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ - uint32_t key_purpose_4_err:4; - /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + uint32_t key_purpose_4_err:5; + /** key_purpose_5_err : RO; bitpos: [19:15]; default: 0; * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ - uint32_t key_purpose_5_err:4; - /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; + uint32_t key_purpose_5_err:5; + /** sec_dpa_level_err : RO; bitpos: [21:20]; default: 0; * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ uint32_t sec_dpa_level_err:2; - uint32_t reserved_18:2; - /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + /** recovery_bootloader_flash_sector_hi_err : RO; bitpos: [24:22]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI + */ + uint32_t recovery_bootloader_flash_sector_hi_err:3; + /** secure_boot_en_err : RO; bitpos: [25]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_EN */ uint32_t secure_boot_en_err:1; - /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [26]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ uint32_t secure_boot_aggressive_revoke_err:1; - uint32_t reserved_22:5; /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0; * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 */ @@ -1919,10 +1021,11 @@ typedef union { * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ uint32_t force_send_resume_err:1; - /** secure_version_err : RO; bitpos: [24:9]; default: 0; + /** secure_version_err : RO; bitpos: [17:9]; default: 0; * Represents the programming error of EFUSE_SECURE_VERSION */ - uint32_t secure_version_err:16; + uint32_t secure_version_err:9; + uint32_t reserved_18:7; /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ @@ -1939,7 +1042,11 @@ typedef union { * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE */ uint32_t xts_dpa_clk_enable_err:1; - uint32_t reserved_30:2; + uint32_t reserved_30:1; + /** ecdsa_p384_enable_err : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_ECDSA_P384_ENABLE + */ + uint32_t ecdsa_p384_enable_err:1; }; uint32_t val; } efuse_rd_repeat_data_err3_reg_t; @@ -1961,15 +1068,15 @@ typedef union { * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE */ uint32_t xtal_48m_sel_mode_err:1; - /** ecdsa_disable_p192_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_ECDSA_DISABLE_P192 - */ - uint32_t ecdsa_disable_p192_err:1; - /** ecc_force_const_time_err : RO; bitpos: [14]; default: 0; + /** ecc_force_const_time_err : RO; bitpos: [13]; default: 0; * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ uint32_t ecc_force_const_time_err:1; - uint32_t reserved_15:17; + /** recovery_bootloader_flash_sector_lo_err : RO; bitpos: [22:14]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO + */ + uint32_t recovery_bootloader_flash_sector_lo_err:9; + uint32_t reserved_23:9; }; uint32_t val; } efuse_rd_repeat_data_err4_reg_t; @@ -1982,91 +1089,98 @@ typedef union { typedef union { struct { /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_mac_sys + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys */ uint32_t rd_mac_sys_err_num:3; /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number - * of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. */ uint32_t rd_mac_sys_fail:1; /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ uint32_t rd_sys_part1_data_err_num:3; /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ uint32_t rd_sys_part1_data_fail:1; /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_usr_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data */ uint32_t rd_usr_data_err_num:3; /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. */ uint32_t rd_usr_data_fail:1; /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key0_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data */ uint32_t rd_key0_data_err_num:3; /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key0_data_fail:1; /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data */ uint32_t rd_key1_data_err_num:3; /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key1_data_fail:1; /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data */ uint32_t rd_key2_data_err_num:3; /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key2_data_fail:1; /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key3_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data */ uint32_t rd_key3_data_err_num:3; /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key3_data_fail:1; /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key4_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data */ uint32_t rd_key4_data_err_num:3; /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key4_data_fail:1; }; @@ -2079,25 +1193,27 @@ typedef union { typedef union { struct { /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key5_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data */ uint32_t rd_key5_data_err_num:3; /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key5_data_fail:1; /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data */ uint32_t rd_sys_part2_data_err_num:3; /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. */ uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_8:24; @@ -2112,8 +1228,9 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37752960; - * Stores eFuse version. + /** date : R/W; bitpos: [27:0]; default: 37818960; + * Represents eFuse version. Date:2024-12-19 16:08:23, + * ScriptRev:5b7d298cf2df9f93b161800aff1807aeadbb74f4 */ uint32_t date:28; uint32_t reserved_28:4; @@ -2129,20 +1246,28 @@ typedef union { typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -2158,18 +1283,190 @@ typedef union { typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect */ uint32_t op_code:16; - /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. - */ - uint32_t cfg_ecdsa_blk:4; - uint32_t reserved_20:12; + uint32_t reserved_16:16; }; uint32_t val; } efuse_conf_reg_t; +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 19; + * Configures the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Configures clock cycles for programming voltage to rise. Measurement unit: a clock + * cycle divided by EFUSE_DAC_CLK_DIV. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of + * the eFuse core clock. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. Measurement unit: One cycle of the eFuse core + * clock. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures which block number to bypass the Reed-Solomon (RS) correction step. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. Measurement unit: One cycle of the eFuse + * core clock. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + + +/** Group: EFUSE ECDSA Configure Registers */ +/** Type of ecdsa register + * eFuse status register. + */ +typedef union { + struct { + /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0; + * Configures which block to use for ECDSA P192 key output. + */ + uint32_t cfg_ecdsa_p192_blk:4; + /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0; + * Configures which block to use for ECDSA P256 key output. + */ + uint32_t cfg_ecdsa_p256_blk:4; + /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0; + * Configures which block to use for ECDSA P384 key low part output. + */ + uint32_t cfg_ecdsa_p384_l_blk:4; + /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0; + * Configures which block to use for ECDSA P256 key high part output. + */ + uint32_t cfg_ecdsa_p384_h_blk:4; + /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0; + * Represents which block is used for ECDSA P192 key output. + */ + uint32_t cur_ecdsa_p192_blk:4; + /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA P256 key output. + */ + uint32_t cur_ecdsa_p256_blk:4; + /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA P384 key low part output. + */ + uint32_t cur_ecdsa_p384_l_blk:4; + /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0; + * Represents which block is used for ECDSA P384 key high part output. + */ + uint32_t cur_ecdsa_p384_h_blk:4; + }; + uint32_t val; +} efuse_ecdsa_reg_t; + /** Group: EFUSE Status Registers */ /** Type of status register @@ -2178,42 +1475,47 @@ typedef union { typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state */ uint32_t state:4; /** otp_load_sw : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. + * Represents the value of OTP_LOAD_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_load_sw:1; /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. + * Represents the value of OTP_VDDQ_C_SYNC2. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_vddq_c_sync2:1; /** otp_strobe_sw : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. + * Represents the value of OTP_STROBE_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_strobe_sw:1; /** otp_csb_sw : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. + * Represents the value of OTP_CSB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_csb_sw:1; /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. + * Represents the value of OTP_PGENB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_pgenb_sw:1; /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. + * Represents the value of OTP_VDDQ_IS_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_vddq_is_sw:1; /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. + * Represents the number of block valid bit. */ uint32_t blk0_valid_bit_cnt:10; - /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. - */ - uint32_t cur_ecdsa_blk:4; - uint32_t reserved_24:8; + uint32_t reserved_20:12; }; uint32_t val; } efuse_status_reg_t; @@ -2226,16 +1528,20 @@ typedef union { typedef union { struct { /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. + * Configures whether to send read commands. + * 1: Send + * 0: No effect */ uint32_t read_cmd:1; /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. + * Configures whether to send programming commands. + * 1: Send + * 0: No effect */ uint32_t pgm_cmd:1; /** blk_num : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. + * Configures the serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. */ uint32_t blk_num:4; uint32_t reserved_6:26; @@ -2251,11 +1557,11 @@ typedef union { typedef union { struct { /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. + * The raw interrupt status of EFUSE_READ_DONE_INT. */ uint32_t read_done_int_raw:1; /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. + * The raw interrupt status of EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_raw:1; uint32_t reserved_2:30; @@ -2269,11 +1575,11 @@ typedef union { typedef union { struct { /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. + * The masked interrupt status of EFUSE_READ_DONE_INT. */ uint32_t read_done_int_st:1; /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. + * The masked interrupt status of EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_st:1; uint32_t reserved_2:30; @@ -2287,11 +1593,11 @@ typedef union { typedef union { struct { /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. + * Write 1 to enable EFUSE_READ_DONE_INT. */ uint32_t read_done_int_ena:1; /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. + * Write 1 to enable EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_ena:1; uint32_t reserved_2:30; @@ -2305,11 +1611,11 @@ typedef union { typedef union { struct { /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. + * Write 1 to clear EFUSE_READ_DONE_INT. */ uint32_t read_done_int_clr:1; /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. + * Write 1 to clear EFUSE_PGM_DONE_INT. */ uint32_t pgm_done_int_clr:1; uint32_t reserved_2:30; @@ -2318,124 +1624,6 @@ typedef union { } efuse_int_clr_reg_t; -/** Group: EFUSE Configure Registers */ -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 22; - * Configures the waiting time of reading eFuse memory. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 200; - * Configures the active programming time. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - - /** Group: EFUSE_APB2OTP Block0 Write Disable Data */ /** Type of apb2otp_wr_dis register * eFuse apb2otp block0 data register1. @@ -3050,7 +2238,6 @@ typedef union { uint32_t val; } efuse_apb2otp_blk2_w11_reg_t; -/** Group: EFUSE_APB2OTP Block2 Word11 Data */ /** Type of apb2otp_blk10_w11 register * eFuse apb2otp block10 data register11. */ @@ -4387,6 +3574,53 @@ typedef union { typedef struct { + volatile efuse_pgm_datan_reg_t pgm_datan[8]; + volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; + volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; + volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; + volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; + volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; + volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; + volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; + volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; + volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; + volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; + volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; + volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; + volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; + volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; + volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; + volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; + volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; + volatile efuse_date_reg_t date; + uint32_t reserved_19c[11]; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_ecdsa_reg_t ecdsa; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + uint32_t reserved_200[192]; volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; @@ -4518,132 +3752,9 @@ typedef struct { volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; uint32_t reserved_704; volatile efuse_apb2otp_en_reg_t apb2otp_en; -} otp_debug_dev_t; - -typedef struct { - volatile efuse_pgm_data0_reg_t pgm_data0; - volatile efuse_pgm_data1_reg_t pgm_data1; - volatile efuse_pgm_data2_reg_t pgm_data2; - volatile efuse_pgm_data3_reg_t pgm_data3; - volatile efuse_pgm_data4_reg_t pgm_data4; - volatile efuse_pgm_data5_reg_t pgm_data5; - volatile efuse_pgm_data6_reg_t pgm_data6; - volatile efuse_pgm_data7_reg_t pgm_data7; - volatile efuse_pgm_check_value0_reg_t pgm_check_value0; - volatile efuse_pgm_check_value1_reg_t pgm_check_value1; - volatile efuse_pgm_check_value2_reg_t pgm_check_value2; - volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0; - volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; - volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; - volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; - volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; - volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; - volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; - volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; - volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; - volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; - volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; - volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; - volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; - volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; - volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; - volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; - volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; - volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; - volatile efuse_rd_usr_data0_reg_t rd_usr_data0; - volatile efuse_rd_usr_data1_reg_t rd_usr_data1; - volatile efuse_rd_usr_data2_reg_t rd_usr_data2; - volatile efuse_rd_usr_data3_reg_t rd_usr_data3; - volatile efuse_rd_usr_data4_reg_t rd_usr_data4; - volatile efuse_rd_usr_data5_reg_t rd_usr_data5; - volatile efuse_rd_usr_data6_reg_t rd_usr_data6; - volatile efuse_rd_usr_data7_reg_t rd_usr_data7; - volatile efuse_rd_key0_data0_reg_t rd_key0_data0; - volatile efuse_rd_key0_data1_reg_t rd_key0_data1; - volatile efuse_rd_key0_data2_reg_t rd_key0_data2; - volatile efuse_rd_key0_data3_reg_t rd_key0_data3; - volatile efuse_rd_key0_data4_reg_t rd_key0_data4; - volatile efuse_rd_key0_data5_reg_t rd_key0_data5; - volatile efuse_rd_key0_data6_reg_t rd_key0_data6; - volatile efuse_rd_key0_data7_reg_t rd_key0_data7; - volatile efuse_rd_key1_data0_reg_t rd_key1_data0; - volatile efuse_rd_key1_data1_reg_t rd_key1_data1; - volatile efuse_rd_key1_data2_reg_t rd_key1_data2; - volatile efuse_rd_key1_data3_reg_t rd_key1_data3; - volatile efuse_rd_key1_data4_reg_t rd_key1_data4; - volatile efuse_rd_key1_data5_reg_t rd_key1_data5; - volatile efuse_rd_key1_data6_reg_t rd_key1_data6; - volatile efuse_rd_key1_data7_reg_t rd_key1_data7; - volatile efuse_rd_key2_data0_reg_t rd_key2_data0; - volatile efuse_rd_key2_data1_reg_t rd_key2_data1; - volatile efuse_rd_key2_data2_reg_t rd_key2_data2; - volatile efuse_rd_key2_data3_reg_t rd_key2_data3; - volatile efuse_rd_key2_data4_reg_t rd_key2_data4; - volatile efuse_rd_key2_data5_reg_t rd_key2_data5; - volatile efuse_rd_key2_data6_reg_t rd_key2_data6; - volatile efuse_rd_key2_data7_reg_t rd_key2_data7; - volatile efuse_rd_key3_data0_reg_t rd_key3_data0; - volatile efuse_rd_key3_data1_reg_t rd_key3_data1; - volatile efuse_rd_key3_data2_reg_t rd_key3_data2; - volatile efuse_rd_key3_data3_reg_t rd_key3_data3; - volatile efuse_rd_key3_data4_reg_t rd_key3_data4; - volatile efuse_rd_key3_data5_reg_t rd_key3_data5; - volatile efuse_rd_key3_data6_reg_t rd_key3_data6; - volatile efuse_rd_key3_data7_reg_t rd_key3_data7; - volatile efuse_rd_key4_data0_reg_t rd_key4_data0; - volatile efuse_rd_key4_data1_reg_t rd_key4_data1; - volatile efuse_rd_key4_data2_reg_t rd_key4_data2; - volatile efuse_rd_key4_data3_reg_t rd_key4_data3; - volatile efuse_rd_key4_data4_reg_t rd_key4_data4; - volatile efuse_rd_key4_data5_reg_t rd_key4_data5; - volatile efuse_rd_key4_data6_reg_t rd_key4_data6; - volatile efuse_rd_key4_data7_reg_t rd_key4_data7; - volatile efuse_rd_key5_data0_reg_t rd_key5_data0; - volatile efuse_rd_key5_data1_reg_t rd_key5_data1; - volatile efuse_rd_key5_data2_reg_t rd_key5_data2; - volatile efuse_rd_key5_data3_reg_t rd_key5_data3; - volatile efuse_rd_key5_data4_reg_t rd_key5_data4; - volatile efuse_rd_key5_data5_reg_t rd_key5_data5; - volatile efuse_rd_key5_data6_reg_t rd_key5_data6; - volatile efuse_rd_key5_data7_reg_t rd_key5_data7; - volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; - volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; - volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; - volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; - volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; - volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; - volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; - volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; - volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; - volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; - volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; - volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; - volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; - volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; - volatile efuse_date_reg_t date; - uint32_t reserved_19c[11]; - volatile efuse_clk_reg_t clk; - volatile efuse_conf_reg_t conf; - volatile efuse_status_reg_t status; - volatile efuse_cmd_reg_t cmd; - volatile efuse_int_raw_reg_t int_raw; - volatile efuse_int_st_reg_t int_st; - volatile efuse_int_ena_reg_t int_ena; - volatile efuse_int_clr_reg_t int_clr; - volatile efuse_dac_conf_reg_t dac_conf; - volatile efuse_rd_tim_conf_reg_t rd_tim_conf; - volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; - volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; - volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; - uint32_t reserved_1fc[193]; - volatile otp_debug_dev_t otp_debug; } efuse_dev_t; extern efuse_dev_t EFUSE; -extern otp_debug_dev_t OTP_DEBUG; #ifndef __cplusplus _Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure"); diff --git a/components/soc/esp32c5/register/soc/efuse_struct_eco2.h b/components/soc/esp32c5/register/soc/efuse_struct_eco2.h deleted file mode 100644 index 0d48c19129..0000000000 --- a/components/soc/esp32c5/register/soc/efuse_struct_eco2.h +++ /dev/null @@ -1,3723 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: program_data registers */ -/** Type of pgm_datan register - * Represents pgm_datan - */ -typedef union { - struct { - /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth 32-bit data to be programmed. - */ - uint32_t pgm_data_n:32; - }; - uint32_t val; -} efuse_pgm_datan_reg_t; - -/** Type of pgm_check_valuen register - * Represents pgm_check_valuen - */ -typedef union { - struct { - /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth RS code to be programmed. - */ - uint32_t pgm_rs_data_n:32; - }; - uint32_t val; -} efuse_pgm_check_valuen_reg_t; - - -/** Group: block0 registers */ -/** Type of rd_wr_dis register - * Represents rd_wr_dis - */ -typedef union { - struct { - /** wr_dis : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled. For - * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled - */ - uint32_t wr_dis:32; - }; - uint32_t val; -} efuse_rd_wr_dis_reg_t; - -/** Type of rd_repeat_data0 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** rd_dis : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block (BLOCK4 \verb+~+ BLOCK10) is - * disabled. For mapping between the bits of this field and the eFuse blocks, please - * refer to Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled - */ - uint32_t rd_dis:7; - /** bootloader_anti_rollback_secure_version_hi : RO; bitpos: [7]; default: 0; - * Represents the anti-rollback secure version of the 2nd stage bootloader used by the - * ROM bootloader (the high part of the field). - */ - uint32_t bootloader_anti_rollback_secure_version_hi:1; - /** dis_icache : RO; bitpos: [8]; default: 0; - * Represents whether cache is disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_icache:1; - /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. Note - * that \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} is available only - * when \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} is - * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} - * \textit{\nameref{mod:bootctrl}}. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_usb_jtag:1; - /** bootloader_anti_rollback_en : RO; bitpos: [10]; default: 0; - * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t bootloader_anti_rollback_en:1; - /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; - * Represents whether USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled - * - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t dis_usb_serial_jtag:1; - /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_force_download:1; - /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot\_mode\_download is disabled. - * 0: Enabled - * 1: Disabled - */ - uint32_t spi_download_mspi_dis:1; - /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI$^®$ function is disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_twai:1; - /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Represents whether the selection of a JTAG signal source through the strapping pin - * value is enabled when all of - * \hyperref[fielddesc:EFUSEDISPADJTAG]{EFUSE\_DIS\_PAD\_JTAG}, - * \hyperref[fielddesc:EFUSEDISUSBJTAG]{EFUSE\_DIS\_USB\_JTAG} and - * \hyperref[fielddesc:EFUSEDISUSBSERIALJTAG]{EFUSE\_DIS\_USB\_SERIAL\_JTAG} are - * configured to 0. For more information, please refer to Chapter \ref{mod:bootctrl} - * \textit{\nameref{mod:bootctrl}}. - * 1: Enabled - * 0: Disabled - */ - uint32_t jtag_sel_enable:1; - /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled - */ - uint32_t soft_dis_jtag:3; - /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_pad_jtag:1; - /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_download_manual_encrypt:1; - /** usb_drefh : RO; bitpos: [22:21]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t usb_drefh:2; - /** usb_drefl : RO; bitpos: [24:23]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t usb_drefl:2; - /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged - */ - uint32_t usb_exchg_pins:1; - /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * Represents whether VDD SPI pin is functioned as GPIO. - * 1: Functioned - * 0: Not functioned - */ - uint32_t vdd_spi_as_gpio:1; - /** wdt_delay_sel : RO; bitpos: [28:27]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0: The originally configured STG0 threshold × 2 - * 1: The originally configured STG0 threshold × 4 - * 2: The originally configured STG0 threshold × 8 - * 3: The originally configured STG0 threshold × 16 - */ - uint32_t wdt_delay_sel:2; - /** bootloader_anti_rollback_secure_version_lo : RO; bitpos: [31:29]; default: 0; - * Represents the anti-rollback secure version of the 2nd stage bootloader used by the - * ROM bootloader (the low part of the field). - */ - uint32_t bootloader_anti_rollback_secure_version_lo:3; - }; - uint32_t val; -} efuse_rd_repeat_data0_reg_t; - -/** Type of rd_repeat_data1 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0; - * Represents whether the new key deployment of key manager is disabled. - * Bit0: Represents whether the new ECDSA key deployment is disabled - * 0: Enabled - * 1: Disabled - * Bit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is - * disabled - * 0: Enabled - * 1: Disabled - * Bit2: Represents whether the new HMAC key deployment is disabled - * 0: Enabled - * 1: Disabled - * Bit3: Represents whether the new DS key deployment is disabled - * 0: Enabled - * 1: Disabled - */ - uint32_t km_disable_deploy_mode:4; - /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0; - * Represents the cycle at which the Key Manager switches random numbers. - * 0: Controlled by the - * \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For - * more information, please refer to Chapter \ref{mod:keymng} - * \textit{\nameref{mod:keymng}} - * 1: 8 Key Manager clock cycles - * 2: 16 Key Manager clock cycles - * 3: 32 Key Manager clock cycles - */ - uint32_t km_rnd_switch_cycle:2; - /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0; - * Represents whether the corresponding key can be deployed only once. - * Bit0: Represents whether the ECDSA key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - * Bit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - * Bit2: Represents whether the HMAC key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - * Bit3: Represents whether the DS key can be deployed only once - * 0: The key can be deployed multiple times - * 1: The key can be deployed only once - */ - uint32_t km_deploy_only_once:4; - /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0; - * Represents whether the corresponding key must come from Key Manager. - * Bit0: Represents whether the ECDSA key must come from Key Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - * Bit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key - * Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - * Bit2: Represents whether the HMAC key must come from Key Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - * Bit3: Represents whether the DS key must come from Key Manager. - * 0: The key does not need to come from Key Manager - * 1: The key must come from Key Manager - */ - uint32_t force_use_key_manager_key:4; - /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0; - * Represents whether to disable the use of the initialization key written by software - * and instead force use efuse\_init\_key. - * 0: Enable - * 1: Disable - */ - uint32_t force_disable_sw_init_key:1; - /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [15]; default: 0; - * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM - * bootloader. - * 1: Enable - * 0: Disable - */ - uint32_t bootloader_anti_rollback_update_in_rom:1; - /** spi_boot_crypt_cnt : RO; bitpos: [18:16]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled - */ - uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [19]; default: 0; - * Represents whether revoking Secure Boot key digest 0 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [20]; default: 0; - * Represents whether revoking Secure Boot key digest 1 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key digest 2 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [26:22]; default: 0; - * Represents the purpose of Key0. See Table \ref{tab:efuse-key-purpose}. - */ - uint32_t key_purpose_0:5; - /** key_purpose_1 : RO; bitpos: [31:27]; default: 0; - * Represents the purpose of Key1. See Table \ref{tab:efuse-key-purpose}. - */ - uint32_t key_purpose_1:5; - }; - uint32_t val; -} efuse_rd_repeat_data1_reg_t; - -/** Type of rd_repeat_data2 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** key_purpose_2 : RO; bitpos: [4:0]; default: 0; - * Represents the purpose of Key2. See Table \ref{tab:efuse-key-purpose}. - */ - uint32_t key_purpose_2:5; - /** key_purpose_3 : RO; bitpos: [9:5]; default: 0; - * Represents the purpose of Key3. See Table \ref{tab:efuse-key-purpose}. - */ - uint32_t key_purpose_3:5; - /** key_purpose_4 : RO; bitpos: [14:10]; default: 0; - * Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose}. - */ - uint32_t key_purpose_4:5; - /** key_purpose_5 : RO; bitpos: [19:15]; default: 0; - * Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose}. - */ - uint32_t key_purpose_5:5; - /** sec_dpa_level : RO; bitpos: [21:20]; default: 0; - * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC\_DPA\_OFF - * 1: Security level is SEC\_DPA\_LOW - * 2: Security level is SEC\_DPA\_MIDDLE - * 3: Security level is SEC\_DPA\_HIGH - * For more information, please refer to Chapter \ref{mod:sysreg} - * \textit{\nameref{mod:sysreg}} > Section - * \ref{sec:sysreg-anti-dpa-attack-security-control} - * \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. - */ - uint32_t sec_dpa_level:2; - /** recovery_bootloader_flash_sector_hi : RO; bitpos: [24:22]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. (The high part of the field). - */ - uint32_t recovery_bootloader_flash_sector_hi:3; - /** secure_boot_en : RO; bitpos: [25]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [26]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_aggressive_revoke:1; - /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0; - * Represents which key flash encryption uses. - * 0: XTS-AES-256 key - * 1: XTS-AES-128 key - */ - uint32_t km_xts_key_length_256:1; - /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. When the - * value is less than 15, the waiting time is the programmed value. Otherwise, the - * waiting time is a fixed value, i.e. 30 ms. - */ - uint32_t flash_tpuw:4; - }; - uint32_t val; -} efuse_rd_repeat_data2_reg_t; - -/** Type of rd_repeat_data3 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disable or enable. 1. Disable - * 0: Enable. - */ - uint32_t dis_download_mode:1; - /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1. Disable - * 0: Enable. - */ - uint32_t dis_direct_boot:1; - /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable - * 0: Enable. - */ - uint32_t dis_usb_serial_jtag_rom_print:1; - /** lock_km_key : RO; bitpos: [3]; default: 0; - * Represents whether the keys in the Key Manager are locked after deployment. - * 0: Not locked - * 1: Locked - */ - uint32_t lock_km_key:1; - /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * Disable - * 0: Enable. - */ - uint32_t dis_usb_serial_jtag_download_mode:1; - /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled. Only downloading into flash is - * supported. Reading/writing RAM or registers is not supported (i.e. stub download is - * not supported). - * 1: Enabled - * 0: Disabled - */ - uint32_t enable_security_download:1; - /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO27 is reset at low level. - * 2: Enable printing when GPIO27 is reset at high level. - * 3: Force disable printing. - */ - uint32_t uart_print_control:2; - /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced. - * 0: Not forced. - */ - uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [17:9]; default: 0; - * Represents the app secure version used by ESP-IDF anti-rollback feature. - */ - uint32_t secure_version:9; - uint32_t reserved_18:7; - /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t secure_boot_disable_fast_wake:1; - /** hys_en_pad : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of PAD0 – PAD27 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t hys_en_pad:1; - /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; - * Represents the pseudo round level of XTS-AES anti-DPA attack. - * 0: Disabled - * 1: Low - * 2: Moderate - * 3: High - */ - uint32_t xts_dpa_pseudo_level:2; - /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0; - * Represents whether XTS-AES anti-DPA attack clock is enabled. - * 0: Disable - * 1: Enabled - */ - uint32_t xts_dpa_clk_enable:1; - uint32_t reserved_30:1; - /** ecdsa_p384_enable : RO; bitpos: [31]; default: 0; - * Represents if the chip supports ECDSA P384 - */ - uint32_t ecdsa_p384_enable:1; - }; - uint32_t val; -} efuse_rd_repeat_data3_reg_t; - -/** Type of rd_repeat_data4 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** huk_gen_state : RO; bitpos: [8:0]; default: 0; - * Represents whether the HUK generate mode is valid. - * Odd count of bits with a value of 1: Invalid - * Even count of bits with a value of 1: Valid - */ - uint32_t huk_gen_state:9; - /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0; - * Determines the frequency of the XTAL clock alone in \textbf{SPI Boot} mode, or - * together with \hyperref[fielddesc:EFUSEXTAL48MSELMODE]{EFUSE\_XTAL\_48M\_SEL\_MODE} - * in \textbf{Joint Download Boot} mode. For more information, please refer to Chapter - * \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}. - * Odd count of bits with a value of 1: 48 MHz - * Even count of bits with a value of 1: 40 MHz - */ - uint32_t xtal_48m_sel:3; - /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0; - * Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. - * For more information, please refer to Chapter \ref{mod:bootctrl} - * \textit{\nameref{mod:bootctrl}}. - * 0: Strapping PAD state - * 1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse - */ - uint32_t xtal_48m_sel_mode:1; - /** ecc_force_const_time : RO; bitpos: [13]; default: 0; - * Represents whether to force ECC to use constant-time mode for point multiplication - * calculation. - * 0: Not force - * 1: Force - */ - uint32_t ecc_force_const_time:1; - /** recovery_bootloader_flash_sector_lo : RO; bitpos: [22:14]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. (The low part of the field). - */ - uint32_t recovery_bootloader_flash_sector_lo:9; - uint32_t reserved_23:9; - }; - uint32_t val; -} efuse_rd_repeat_data4_reg_t; - - -/** Group: block1 registers */ -/** Type of rd_mac_sys0 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. - */ - uint32_t mac_0:32; - }; - uint32_t val; -} efuse_rd_mac_sys0_reg_t; - -/** Type of rd_mac_sys1 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. - */ - uint32_t mac_1:16; - /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. - */ - uint32_t mac_ext:16; - }; - uint32_t val; -} efuse_rd_mac_sys1_reg_t; - -/** Type of rd_mac_sys2 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mac_reserved_0:14; - /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mac_reserved_1:18; - }; - uint32_t val; -} efuse_rd_mac_sys2_reg_t; - -/** Type of rd_mac_sys3 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mac_reserved_2:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_0:14; - }; - uint32_t val; -} efuse_rd_mac_sys3_reg_t; - -/** Type of rd_mac_sys4 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_1:32; - }; - uint32_t val; -} efuse_rd_mac_sys4_reg_t; - -/** Type of rd_mac_sys5 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_2:32; - }; - uint32_t val; -} efuse_rd_mac_sys5_reg_t; - - -/** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan - */ -typedef union { - struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ - uint32_t sys_data_part1_n:32; - }; - uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; - - -/** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan - */ -typedef union { - struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_datan:32; - }; - uint32_t val; -} efuse_rd_usr_datan_reg_t; - - -/** Group: block4 registers */ -/** Type of rd_key0_datan register - * Represents rd_key0_datan - */ -typedef union { - struct { - /** key0_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_datan:32; - }; - uint32_t val; -} efuse_rd_key0_datan_reg_t; - - -/** Group: block5 registers */ -/** Type of rd_key1_datan register - * Represents rd_key1_datan - */ -typedef union { - struct { - /** key1_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_datan:32; - }; - uint32_t val; -} efuse_rd_key1_datan_reg_t; - - -/** Group: block6 registers */ -/** Type of rd_key2_datan register - * Represents rd_key2_datan - */ -typedef union { - struct { - /** key2_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_datan:32; - }; - uint32_t val; -} efuse_rd_key2_datan_reg_t; - - -/** Group: block7 registers */ -/** Type of rd_key3_datan register - * Represents rd_key3_datan - */ -typedef union { - struct { - /** key3_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_datan:32; - }; - uint32_t val; -} efuse_rd_key3_datan_reg_t; - - -/** Group: block8 registers */ -/** Type of rd_key4_datan register - * Represents rd_key4_datan - */ -typedef union { - struct { - /** key4_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_datan:32; - }; - uint32_t val; -} efuse_rd_key4_datan_reg_t; - - -/** Group: block9 registers */ -/** Type of rd_key5_datan register - * Represents rd_key5_datan - */ -typedef union { - struct { - /** key5_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_datan:32; - }; - uint32_t val; -} efuse_rd_key5_datan_reg_t; - - -/** Group: block10 registers */ -/** Type of rd_sys_part2_datan register - * Represents rd_sys_part2_datan - */ -typedef union { - struct { - /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_n:32; - }; - uint32_t val; -} efuse_rd_sys_part2_datan_reg_t; - - -/** Group: block0 error report registers */ -/** Type of rd_repeat_data_err0 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS - */ - uint32_t rd_dis_err:7; - /** bootloader_anti_rollback_secure_version_hi_err : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_HI - */ - uint32_t bootloader_anti_rollback_secure_version_hi_err:1; - /** dis_icache_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_DIS_ICACHE - */ - uint32_t dis_icache_err:1; - /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG - */ - uint32_t dis_usb_jtag_err:1; - /** bootloader_anti_rollback_en_err : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN - */ - uint32_t bootloader_anti_rollback_en_err:1; - /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t dis_usb_serial_jtag_err:1; - /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD - */ - uint32_t dis_force_download_err:1; - /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS - */ - uint32_t spi_download_mspi_dis_err:1; - /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI - */ - uint32_t dis_twai_err:1; - /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE - */ - uint32_t jtag_sel_enable_err:1; - /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG - */ - uint32_t soft_dis_jtag_err:3; - /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG - */ - uint32_t dis_pad_jtag_err:1; - /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT - */ - uint32_t dis_download_manual_encrypt_err:1; - /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; - * Represents the programming error of EFUSE_USB_DREFH - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t usb_drefh_err:2; - /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; - * Represents the programming error of EFUSE_USB_DREFL - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t usb_drefl_err:2; - /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_EXCHG_PINS - */ - uint32_t usb_exchg_pins_err:1; - /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO - */ - uint32_t vdd_spi_as_gpio_err:1; - /** wdt_delay_sel_err : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL - */ - uint32_t wdt_delay_sel_err:2; - /** bootloader_anti_rollback_secure_version_lo_err : RO; bitpos: [31:29]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_LO - */ - uint32_t bootloader_anti_rollback_secure_version_lo_err:3; - }; - uint32_t val; -} efuse_rd_repeat_data_err0_reg_t; - -/** Type of rd_repeat_data_err1 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** km_disable_deploy_mode_err : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE - */ - uint32_t km_disable_deploy_mode_err:4; - /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0; - * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE - */ - uint32_t km_rnd_switch_cycle_err:2; - /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0; - * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE - */ - uint32_t km_deploy_only_once_err:4; - /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0; - * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY - */ - uint32_t force_use_key_manager_key_err:4; - /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY - */ - uint32_t force_disable_sw_init_key_err:1; - /** bootloader_anti_rollback_update_in_rom_err : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM - */ - uint32_t bootloader_anti_rollback_update_in_rom_err:1; - /** spi_boot_crypt_cnt_err : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT - */ - uint32_t spi_boot_crypt_cnt_err:3; - /** secure_boot_key_revoke0_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 - */ - uint32_t secure_boot_key_revoke0_err:1; - /** secure_boot_key_revoke1_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 - */ - uint32_t secure_boot_key_revoke1_err:1; - /** secure_boot_key_revoke2_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 - */ - uint32_t secure_boot_key_revoke2_err:1; - /** key_purpose_0_err : RO; bitpos: [26:22]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 - */ - uint32_t key_purpose_0_err:5; - /** key_purpose_1_err : RO; bitpos: [31:27]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 - */ - uint32_t key_purpose_1_err:5; - }; - uint32_t val; -} efuse_rd_repeat_data_err1_reg_t; - -/** Type of rd_repeat_data_err2 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** key_purpose_2_err : RO; bitpos: [4:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 - */ - uint32_t key_purpose_2_err:5; - /** key_purpose_3_err : RO; bitpos: [9:5]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 - */ - uint32_t key_purpose_3_err:5; - /** key_purpose_4_err : RO; bitpos: [14:10]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 - */ - uint32_t key_purpose_4_err:5; - /** key_purpose_5_err : RO; bitpos: [19:15]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 - */ - uint32_t key_purpose_5_err:5; - /** sec_dpa_level_err : RO; bitpos: [21:20]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL - */ - uint32_t sec_dpa_level_err:2; - /** recovery_bootloader_flash_sector_hi_err : RO; bitpos: [24:22]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI - */ - uint32_t recovery_bootloader_flash_sector_hi_err:3; - /** secure_boot_en_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN - */ - uint32_t secure_boot_en_err:1; - /** secure_boot_aggressive_revoke_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE - */ - uint32_t secure_boot_aggressive_revoke_err:1; - /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 - */ - uint32_t km_xts_key_length_256_err:1; - /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW - */ - uint32_t flash_tpuw_err:4; - }; - uint32_t val; -} efuse_rd_repeat_data_err2_reg_t; - -/** Type of rd_repeat_data_err3 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE - */ - uint32_t dis_download_mode_err:1; - /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT - */ - uint32_t dis_direct_boot_err:1; - /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT - */ - uint32_t dis_usb_serial_jtag_rom_print_err:1; - /** lock_km_key_err : RO; bitpos: [3]; default: 0; - * Represents the programming error of EFUSE_LOCK_KM_KEY - */ - uint32_t lock_km_key_err:1; - /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE - */ - uint32_t dis_usb_serial_jtag_download_mode_err:1; - /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD - */ - uint32_t enable_security_download_err:1; - /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL - */ - uint32_t uart_print_control_err:2; - /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME - */ - uint32_t force_send_resume_err:1; - /** secure_version_err : RO; bitpos: [17:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION - */ - uint32_t secure_version_err:9; - uint32_t reserved_18:7; - /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE - */ - uint32_t secure_boot_disable_fast_wake_err:1; - /** hys_en_pad_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD - */ - uint32_t hys_en_pad_err:1; - /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL - */ - uint32_t xts_dpa_pseudo_level_err:2; - /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE - */ - uint32_t xts_dpa_clk_enable_err:1; - uint32_t reserved_30:1; - /** ecdsa_p384_enable_err : RO; bitpos: [31]; default: 0; - * Represents the programming error of EFUSE_ECDSA_P384_ENABLE - */ - uint32_t ecdsa_p384_enable_err:1; - }; - uint32_t val; -} efuse_rd_repeat_data_err3_reg_t; - -/** Type of rd_repeat_data_err4 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** huk_gen_state_err : RO; bitpos: [8:0]; default: 0; - * Represents the programming error of EFUSE_HUK_GEN_STATE - */ - uint32_t huk_gen_state_err:9; - /** xtal_48m_sel_err : RO; bitpos: [11:9]; default: 0; - * Represents the programming error of EFUSE_XTAL_48M_SEL - */ - uint32_t xtal_48m_sel_err:3; - /** xtal_48m_sel_mode_err : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE - */ - uint32_t xtal_48m_sel_mode_err:1; - /** ecc_force_const_time_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME - */ - uint32_t ecc_force_const_time_err:1; - /** recovery_bootloader_flash_sector_lo_err : RO; bitpos: [22:14]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO - */ - uint32_t recovery_bootloader_flash_sector_lo_err:9; - uint32_t reserved_23:9; - }; - uint32_t val; -} efuse_rd_repeat_data_err4_reg_t; - - -/** Group: RS block error report registers */ -/** Type of rd_rs_data_err0 register - * Represents rd_rs_data_err - */ -typedef union { - struct { - /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys - */ - uint32_t rd_mac_sys_err_num:3; - /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. - */ - uint32_t rd_mac_sys_fail:1; - /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data - */ - uint32_t rd_sys_part1_data_err_num:3; - /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. - */ - uint32_t rd_sys_part1_data_fail:1; - /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data - */ - uint32_t rd_usr_data_err_num:3; - /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_usr_data_fail:1; - /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data - */ - uint32_t rd_key0_data_err_num:3; - /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key0_data_fail:1; - /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data - */ - uint32_t rd_key1_data_err_num:3; - /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key1_data_fail:1; - /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data - */ - uint32_t rd_key2_data_err_num:3; - /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key2_data_fail:1; - /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data - */ - uint32_t rd_key3_data_err_num:3; - /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key3_data_fail:1; - /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data - */ - uint32_t rd_key4_data_err_num:3; - /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key4_data_fail:1; - }; - uint32_t val; -} efuse_rd_rs_data_err0_reg_t; - -/** Type of rd_rs_data_err1 register - * Represents rd_rs_data_err - */ -typedef union { - struct { - /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data - */ - uint32_t rd_key5_data_err_num:3; - /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key5_data_fail:1; - /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data - */ - uint32_t rd_sys_part2_data_err_num:3; - /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. - */ - uint32_t rd_sys_part2_data_fail:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} efuse_rd_rs_data_err1_reg_t; - - -/** Group: EFUSE Version Register */ -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 37818960; - * Represents eFuse version. Date:2024-12-19 16:08:23, - * ScriptRev:5b7d298cf2df9f93b161800aff1807aeadbb74f4 - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - -/** Group: EFUSE Clock Registers */ -/** Type of clk register - * eFuse clcok configuration register. - */ -typedef union { - struct { - /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect - */ - uint32_t mem_force_pd:1; - /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect - */ - uint32_t mem_clk_force_on:1; - /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect - */ - uint32_t mem_force_pu:1; - uint32_t reserved_3:13; - /** clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers - */ - uint32_t clk_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} efuse_clk_reg_t; - - -/** Group: EFUSE Configure Registers */ -/** Type of conf register - * eFuse operation mode configuration register - */ -typedef union { - struct { - /** op_code : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect - */ - uint32_t op_code:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_conf_reg_t; - -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 19; - * Configures the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Configures clock cycles for programming voltage to rise. Measurement unit: a clock - * cycle divided by EFUSE_DAC_CLK_DIV. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. Measurement unit: One cycle of the eFuse core clock. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of - * the eFuse core clock. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. Measurement unit: One cycle of the eFuse - * core clock. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. Measurement unit: One cycle of the eFuse core - * clock. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. Measurement unit: One cycle of the eFuse - * core clock. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures which block number to bypass the Reed-Solomon (RS) correction step. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. Measurement unit: One cycle of the eFuse - * core clock. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - - -/** Group: EFUSE ECDSA Configure Registers */ -/** Type of ecdsa register - * eFuse status register. - */ -typedef union { - struct { - /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0; - * Configures which block to use for ECDSA P192 key output. - */ - uint32_t cfg_ecdsa_p192_blk:4; - /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0; - * Configures which block to use for ECDSA P256 key output. - */ - uint32_t cfg_ecdsa_p256_blk:4; - /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0; - * Configures which block to use for ECDSA P384 key low part output. - */ - uint32_t cfg_ecdsa_p384_l_blk:4; - /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0; - * Configures which block to use for ECDSA P256 key high part output. - */ - uint32_t cfg_ecdsa_p384_h_blk:4; - /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0; - * Represents which block is used for ECDSA P192 key output. - */ - uint32_t cur_ecdsa_p192_blk:4; - /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA P256 key output. - */ - uint32_t cur_ecdsa_p256_blk:4; - /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA P384 key low part output. - */ - uint32_t cur_ecdsa_p384_l_blk:4; - /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0; - * Represents which block is used for ECDSA P384 key high part output. - */ - uint32_t cur_ecdsa_p384_h_blk:4; - }; - uint32_t val; -} efuse_ecdsa_reg_t; - - -/** Group: EFUSE Status Registers */ -/** Type of status register - * eFuse status register. - */ -typedef union { - struct { - /** state : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state - */ - uint32_t state:4; - /** otp_load_sw : RO; bitpos: [4]; default: 0; - * Represents the value of OTP_LOAD_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t otp_load_sw:1; - /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; - * Represents the value of OTP_VDDQ_C_SYNC2. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t otp_vddq_c_sync2:1; - /** otp_strobe_sw : RO; bitpos: [6]; default: 0; - * Represents the value of OTP_STROBE_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t otp_strobe_sw:1; - /** otp_csb_sw : RO; bitpos: [7]; default: 0; - * Represents the value of OTP_CSB_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t otp_csb_sw:1; - /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; - * Represents the value of OTP_PGENB_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t otp_pgenb_sw:1; - /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; - * Represents the value of OTP_VDDQ_IS_SW. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t otp_vddq_is_sw:1; - /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Represents the number of block valid bit. - */ - uint32_t blk0_valid_bit_cnt:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} efuse_status_reg_t; - - -/** Group: EFUSE Command Registers */ -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * Configures the serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * eFuse raw interrupt register. - */ -typedef union { - struct { - /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of EFUSE_READ_DONE_INT. - */ - uint32_t read_done_int_raw:1; - /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status of EFUSE_PGM_DONE_INT. - */ - uint32_t pgm_done_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_raw_reg_t; - -/** Type of int_st register - * eFuse interrupt status register. - */ -typedef union { - struct { - /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of EFUSE_READ_DONE_INT. - */ - uint32_t read_done_int_st:1; - /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of EFUSE_PGM_DONE_INT. - */ - uint32_t pgm_done_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_st_reg_t; - -/** Type of int_ena register - * eFuse interrupt enable register. - */ -typedef union { - struct { - /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable EFUSE_READ_DONE_INT. - */ - uint32_t read_done_int_ena:1; - /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable EFUSE_PGM_DONE_INT. - */ - uint32_t pgm_done_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_ena_reg_t; - -/** Type of int_clr register - * eFuse interrupt clear register. - */ -typedef union { - struct { - /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear EFUSE_READ_DONE_INT. - */ - uint32_t read_done_int_clr:1; - /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear EFUSE_PGM_DONE_INT. - */ - uint32_t pgm_done_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_clr_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Write Disable Data */ -/** Type of apb2otp_wr_dis register - * eFuse apb2otp block0 data register1. - */ -typedef union { - struct { - /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ - uint32_t apb2otp_block0_wr_dis:32; - }; - uint32_t val; -} efuse_apb2otp_wr_dis_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */ -/** Type of apb2otp_blk0_backup1_w1 register - * eFuse apb2otp block0 data register2. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ - uint32_t apb2otp_block0_backup1_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */ -/** Type of apb2otp_blk0_backup1_w2 register - * eFuse apb2otp block0 data register3. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ - uint32_t apb2otp_block0_backup1_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */ -/** Type of apb2otp_blk0_backup1_w3 register - * eFuse apb2otp block0 data register4. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ - uint32_t apb2otp_block0_backup1_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */ -/** Type of apb2otp_blk0_backup1_w4 register - * eFuse apb2otp block0 data register5. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ - uint32_t apb2otp_block0_backup1_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */ -/** Type of apb2otp_blk0_backup1_w5 register - * eFuse apb2otp block0 data register6. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ - uint32_t apb2otp_block0_backup1_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */ -/** Type of apb2otp_blk0_backup2_w1 register - * eFuse apb2otp block0 data register7. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ - uint32_t apb2otp_block0_backup2_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */ -/** Type of apb2otp_blk0_backup2_w2 register - * eFuse apb2otp block0 data register8. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ - uint32_t apb2otp_block0_backup2_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */ -/** Type of apb2otp_blk0_backup2_w3 register - * eFuse apb2otp block0 data register9. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ - uint32_t apb2otp_block0_backup2_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */ -/** Type of apb2otp_blk0_backup2_w4 register - * eFuse apb2otp block0 data register10. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ - uint32_t apb2otp_block0_backup2_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */ -/** Type of apb2otp_blk0_backup2_w5 register - * eFuse apb2otp block0 data register11. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ - uint32_t apb2otp_block0_backup2_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */ -/** Type of apb2otp_blk0_backup3_w1 register - * eFuse apb2otp block0 data register12. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ - uint32_t apb2otp_block0_backup3_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */ -/** Type of apb2otp_blk0_backup3_w2 register - * eFuse apb2otp block0 data register13. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ - uint32_t apb2otp_block0_backup3_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */ -/** Type of apb2otp_blk0_backup3_w3 register - * eFuse apb2otp block0 data register14. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ - uint32_t apb2otp_block0_backup3_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */ -/** Type of apb2otp_blk0_backup3_w4 register - * eFuse apb2otp block0 data register15. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ - uint32_t apb2otp_block0_backup3_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */ -/** Type of apb2otp_blk0_backup3_w5 register - * eFuse apb2otp block0 data register16. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ - uint32_t apb2otp_block0_backup3_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */ -/** Type of apb2otp_blk0_backup4_w1 register - * eFuse apb2otp block0 data register17. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ - uint32_t apb2otp_block0_backup4_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */ -/** Type of apb2otp_blk0_backup4_w2 register - * eFuse apb2otp block0 data register18. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ - uint32_t apb2otp_block0_backup4_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */ -/** Type of apb2otp_blk0_backup4_w3 register - * eFuse apb2otp block0 data register19. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ - uint32_t apb2otp_block0_backup4_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */ -/** Type of apb2otp_blk0_backup4_w4 register - * eFuse apb2otp block0 data register20. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ - uint32_t apb2otp_block0_backup4_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */ -/** Type of apb2otp_blk0_backup4_w5 register - * eFuse apb2otp block0 data register21. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ - uint32_t apb2otp_block0_backup4_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word1 Data */ -/** Type of apb2otp_blk1_w1 register - * eFuse apb2otp block1 data register1. - */ -typedef union { - struct { - /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ - uint32_t apb2otp_block1_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word2 Data */ -/** Type of apb2otp_blk1_w2 register - * eFuse apb2otp block1 data register2. - */ -typedef union { - struct { - /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ - uint32_t apb2otp_block1_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word3 Data */ -/** Type of apb2otp_blk1_w3 register - * eFuse apb2otp block1 data register3. - */ -typedef union { - struct { - /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ - uint32_t apb2otp_block1_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word4 Data */ -/** Type of apb2otp_blk1_w4 register - * eFuse apb2otp block1 data register4. - */ -typedef union { - struct { - /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ - uint32_t apb2otp_block1_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word5 Data */ -/** Type of apb2otp_blk1_w5 register - * eFuse apb2otp block1 data register5. - */ -typedef union { - struct { - /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ - uint32_t apb2otp_block1_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word6 Data */ -/** Type of apb2otp_blk1_w6 register - * eFuse apb2otp block1 data register6. - */ -typedef union { - struct { - /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ - uint32_t apb2otp_block1_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word7 Data */ -/** Type of apb2otp_blk1_w7 register - * eFuse apb2otp block1 data register7. - */ -typedef union { - struct { - /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ - uint32_t apb2otp_block1_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word8 Data */ -/** Type of apb2otp_blk1_w8 register - * eFuse apb2otp block1 data register8. - */ -typedef union { - struct { - /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ - uint32_t apb2otp_block1_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word9 Data */ -/** Type of apb2otp_blk1_w9 register - * eFuse apb2otp block1 data register9. - */ -typedef union { - struct { - /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ - uint32_t apb2otp_block1_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word1 Data */ -/** Type of apb2otp_blk2_w1 register - * eFuse apb2otp block2 data register1. - */ -typedef union { - struct { - /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ - uint32_t apb2otp_block2_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word2 Data */ -/** Type of apb2otp_blk2_w2 register - * eFuse apb2otp block2 data register2. - */ -typedef union { - struct { - /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ - uint32_t apb2otp_block2_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word3 Data */ -/** Type of apb2otp_blk2_w3 register - * eFuse apb2otp block2 data register3. - */ -typedef union { - struct { - /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ - uint32_t apb2otp_block2_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word4 Data */ -/** Type of apb2otp_blk2_w4 register - * eFuse apb2otp block2 data register4. - */ -typedef union { - struct { - /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ - uint32_t apb2otp_block2_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word5 Data */ -/** Type of apb2otp_blk2_w5 register - * eFuse apb2otp block2 data register5. - */ -typedef union { - struct { - /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ - uint32_t apb2otp_block2_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word6 Data */ -/** Type of apb2otp_blk2_w6 register - * eFuse apb2otp block2 data register6. - */ -typedef union { - struct { - /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ - uint32_t apb2otp_block2_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word7 Data */ -/** Type of apb2otp_blk2_w7 register - * eFuse apb2otp block2 data register7. - */ -typedef union { - struct { - /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ - uint32_t apb2otp_block2_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word8 Data */ -/** Type of apb2otp_blk2_w8 register - * eFuse apb2otp block2 data register8. - */ -typedef union { - struct { - /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ - uint32_t apb2otp_block2_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word9 Data */ -/** Type of apb2otp_blk2_w9 register - * eFuse apb2otp block2 data register9. - */ -typedef union { - struct { - /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ - uint32_t apb2otp_block2_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word10 Data */ -/** Type of apb2otp_blk2_w10 register - * eFuse apb2otp block2 data register10. - */ -typedef union { - struct { - /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ - uint32_t apb2otp_block2_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word11 Data */ -/** Type of apb2otp_blk2_w11 register - * eFuse apb2otp block2 data register11. - */ -typedef union { - struct { - /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ - uint32_t apb2otp_block2_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w11_reg_t; - -/** Type of apb2otp_blk10_w11 register - * eFuse apb2otp block10 data register11. - */ -typedef union { - struct { - /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t apb2otp_block10_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word1 Data */ -/** Type of apb2otp_blk3_w1 register - * eFuse apb2otp block3 data register1. - */ -typedef union { - struct { - /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ - uint32_t apb2otp_block3_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word2 Data */ -/** Type of apb2otp_blk3_w2 register - * eFuse apb2otp block3 data register2. - */ -typedef union { - struct { - /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ - uint32_t apb2otp_block3_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word3 Data */ -/** Type of apb2otp_blk3_w3 register - * eFuse apb2otp block3 data register3. - */ -typedef union { - struct { - /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ - uint32_t apb2otp_block3_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word4 Data */ -/** Type of apb2otp_blk3_w4 register - * eFuse apb2otp block3 data register4. - */ -typedef union { - struct { - /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ - uint32_t apb2otp_block3_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word5 Data */ -/** Type of apb2otp_blk3_w5 register - * eFuse apb2otp block3 data register5. - */ -typedef union { - struct { - /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ - uint32_t apb2otp_block3_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word6 Data */ -/** Type of apb2otp_blk3_w6 register - * eFuse apb2otp block3 data register6. - */ -typedef union { - struct { - /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ - uint32_t apb2otp_block3_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word7 Data */ -/** Type of apb2otp_blk3_w7 register - * eFuse apb2otp block3 data register7. - */ -typedef union { - struct { - /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ - uint32_t apb2otp_block3_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word8 Data */ -/** Type of apb2otp_blk3_w8 register - * eFuse apb2otp block3 data register8. - */ -typedef union { - struct { - /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ - uint32_t apb2otp_block3_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word9 Data */ -/** Type of apb2otp_blk3_w9 register - * eFuse apb2otp block3 data register9. - */ -typedef union { - struct { - /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ - uint32_t apb2otp_block3_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word10 Data */ -/** Type of apb2otp_blk3_w10 register - * eFuse apb2otp block3 data register10. - */ -typedef union { - struct { - /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ - uint32_t apb2otp_block3_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word11 Data */ -/** Type of apb2otp_blk3_w11 register - * eFuse apb2otp block3 data register11. - */ -typedef union { - struct { - /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ - uint32_t apb2otp_block3_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w11_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */ -/** Type of apb2otp_blk4_w1 register - * eFuse apb2otp BLOCK7 data register1. - */ -typedef union { - struct { - /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ - uint32_t apb2otp_block4_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w1_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */ -/** Type of apb2otp_blk4_w2 register - * eFuse apb2otp block4 data register2. - */ -typedef union { - struct { - /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ - uint32_t apb2otp_block4_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w2_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */ -/** Type of apb2otp_blk4_w3 register - * eFuse apb2otp block4 data register3. - */ -typedef union { - struct { - /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ - uint32_t apb2otp_block4_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w3_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */ -/** Type of apb2otp_blk4_w4 register - * eFuse apb2otp block4 data register4. - */ -typedef union { - struct { - /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ - uint32_t apb2otp_block4_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w4_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */ -/** Type of apb2otp_blk4_w5 register - * eFuse apb2otp block4 data register5. - */ -typedef union { - struct { - /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ - uint32_t apb2otp_block4_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w5_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */ -/** Type of apb2otp_blk4_w6 register - * eFuse apb2otp block4 data register6. - */ -typedef union { - struct { - /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ - uint32_t apb2otp_block4_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w6_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */ -/** Type of apb2otp_blk4_w7 register - * eFuse apb2otp block4 data register7. - */ -typedef union { - struct { - /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ - uint32_t apb2otp_block4_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w7_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */ -/** Type of apb2otp_blk4_w8 register - * eFuse apb2otp block4 data register8. - */ -typedef union { - struct { - /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ - uint32_t apb2otp_block4_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w8_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */ -/** Type of apb2otp_blk4_w9 register - * eFuse apb2otp block4 data register9. - */ -typedef union { - struct { - /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ - uint32_t apb2otp_block4_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w9_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */ -/** Type of apb2otp_blk4_w10 register - * eFuse apb2otp block4 data registe10. - */ -typedef union { - struct { - /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ - uint32_t apb2otp_block4_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w10_reg_t; - - -/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */ -/** Type of apb2otp_blk4_w11 register - * eFuse apb2otp block4 data register11. - */ -typedef union { - struct { - /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ - uint32_t apb2otp_block4_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word1 Data */ -/** Type of apb2otp_blk5_w1 register - * eFuse apb2otp block5 data register1. - */ -typedef union { - struct { - /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ - uint32_t apb2otp_block5_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word2 Data */ -/** Type of apb2otp_blk5_w2 register - * eFuse apb2otp block5 data register2. - */ -typedef union { - struct { - /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ - uint32_t apb2otp_block5_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word3 Data */ -/** Type of apb2otp_blk5_w3 register - * eFuse apb2otp block5 data register3. - */ -typedef union { - struct { - /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ - uint32_t apb2otp_block5_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word4 Data */ -/** Type of apb2otp_blk5_w4 register - * eFuse apb2otp block5 data register4. - */ -typedef union { - struct { - /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ - uint32_t apb2otp_block5_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word5 Data */ -/** Type of apb2otp_blk5_w5 register - * eFuse apb2otp block5 data register5. - */ -typedef union { - struct { - /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ - uint32_t apb2otp_block5_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word6 Data */ -/** Type of apb2otp_blk5_w6 register - * eFuse apb2otp block5 data register6. - */ -typedef union { - struct { - /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ - uint32_t apb2otp_block5_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word7 Data */ -/** Type of apb2otp_blk5_w7 register - * eFuse apb2otp block5 data register7. - */ -typedef union { - struct { - /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ - uint32_t apb2otp_block5_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word8 Data */ -/** Type of apb2otp_blk5_w8 register - * eFuse apb2otp block5 data register8. - */ -typedef union { - struct { - /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ - uint32_t apb2otp_block5_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word9 Data */ -/** Type of apb2otp_blk5_w9 register - * eFuse apb2otp block5 data register9. - */ -typedef union { - struct { - /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ - uint32_t apb2otp_block5_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word10 Data */ -/** Type of apb2otp_blk5_w10 register - * eFuse apb2otp block5 data register10. - */ -typedef union { - struct { - /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ - uint32_t apb2otp_block5_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word11 Data */ -/** Type of apb2otp_blk5_w11 register - * eFuse apb2otp block5 data register11. - */ -typedef union { - struct { - /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ - uint32_t apb2otp_block5_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word1 Data */ -/** Type of apb2otp_blk6_w1 register - * eFuse apb2otp block6 data register1. - */ -typedef union { - struct { - /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ - uint32_t apb2otp_block6_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word2 Data */ -/** Type of apb2otp_blk6_w2 register - * eFuse apb2otp block6 data register2. - */ -typedef union { - struct { - /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ - uint32_t apb2otp_block6_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word3 Data */ -/** Type of apb2otp_blk6_w3 register - * eFuse apb2otp block6 data register3. - */ -typedef union { - struct { - /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ - uint32_t apb2otp_block6_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word4 Data */ -/** Type of apb2otp_blk6_w4 register - * eFuse apb2otp block6 data register4. - */ -typedef union { - struct { - /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ - uint32_t apb2otp_block6_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word5 Data */ -/** Type of apb2otp_blk6_w5 register - * eFuse apb2otp block6 data register5. - */ -typedef union { - struct { - /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ - uint32_t apb2otp_block6_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word6 Data */ -/** Type of apb2otp_blk6_w6 register - * eFuse apb2otp block6 data register6. - */ -typedef union { - struct { - /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ - uint32_t apb2otp_block6_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word7 Data */ -/** Type of apb2otp_blk6_w7 register - * eFuse apb2otp block6 data register7. - */ -typedef union { - struct { - /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ - uint32_t apb2otp_block6_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word8 Data */ -/** Type of apb2otp_blk6_w8 register - * eFuse apb2otp block6 data register8. - */ -typedef union { - struct { - /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ - uint32_t apb2otp_block6_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word9 Data */ -/** Type of apb2otp_blk6_w9 register - * eFuse apb2otp block6 data register9. - */ -typedef union { - struct { - /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ - uint32_t apb2otp_block6_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word10 Data */ -/** Type of apb2otp_blk6_w10 register - * eFuse apb2otp block6 data register10. - */ -typedef union { - struct { - /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ - uint32_t apb2otp_block6_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word11 Data */ -/** Type of apb2otp_blk6_w11 register - * eFuse apb2otp block6 data register11. - */ -typedef union { - struct { - /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ - uint32_t apb2otp_block6_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word1 Data */ -/** Type of apb2otp_blk7_w1 register - * eFuse apb2otp block7 data register1. - */ -typedef union { - struct { - /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ - uint32_t apb2otp_block7_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word2 Data */ -/** Type of apb2otp_blk7_w2 register - * eFuse apb2otp block7 data register2. - */ -typedef union { - struct { - /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ - uint32_t apb2otp_block7_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word3 Data */ -/** Type of apb2otp_blk7_w3 register - * eFuse apb2otp block7 data register3. - */ -typedef union { - struct { - /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ - uint32_t apb2otp_block7_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word4 Data */ -/** Type of apb2otp_blk7_w4 register - * eFuse apb2otp block7 data register4. - */ -typedef union { - struct { - /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ - uint32_t apb2otp_block7_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word5 Data */ -/** Type of apb2otp_blk7_w5 register - * eFuse apb2otp block7 data register5. - */ -typedef union { - struct { - /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ - uint32_t apb2otp_block7_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word6 Data */ -/** Type of apb2otp_blk7_w6 register - * eFuse apb2otp block7 data register6. - */ -typedef union { - struct { - /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ - uint32_t apb2otp_block7_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word7 Data */ -/** Type of apb2otp_blk7_w7 register - * eFuse apb2otp block7 data register7. - */ -typedef union { - struct { - /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ - uint32_t apb2otp_block7_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word8 Data */ -/** Type of apb2otp_blk7_w8 register - * eFuse apb2otp block7 data register8. - */ -typedef union { - struct { - /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ - uint32_t apb2otp_block7_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word9 Data */ -/** Type of apb2otp_blk7_w9 register - * eFuse apb2otp block7 data register9. - */ -typedef union { - struct { - /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ - uint32_t apb2otp_block7_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word10 Data */ -/** Type of apb2otp_blk7_w10 register - * eFuse apb2otp block7 data register10. - */ -typedef union { - struct { - /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ - uint32_t apb2otp_block7_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word11 Data */ -/** Type of apb2otp_blk7_w11 register - * eFuse apb2otp block7 data register11. - */ -typedef union { - struct { - /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ - uint32_t apb2otp_block7_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word1 Data */ -/** Type of apb2otp_blk8_w1 register - * eFuse apb2otp block8 data register1. - */ -typedef union { - struct { - /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ - uint32_t apb2otp_block8_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word2 Data */ -/** Type of apb2otp_blk8_w2 register - * eFuse apb2otp block8 data register2. - */ -typedef union { - struct { - /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ - uint32_t apb2otp_block8_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word3 Data */ -/** Type of apb2otp_blk8_w3 register - * eFuse apb2otp block8 data register3. - */ -typedef union { - struct { - /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ - uint32_t apb2otp_block8_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word4 Data */ -/** Type of apb2otp_blk8_w4 register - * eFuse apb2otp block8 data register4. - */ -typedef union { - struct { - /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ - uint32_t apb2otp_block8_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word5 Data */ -/** Type of apb2otp_blk8_w5 register - * eFuse apb2otp block8 data register5. - */ -typedef union { - struct { - /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ - uint32_t apb2otp_block8_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word6 Data */ -/** Type of apb2otp_blk8_w6 register - * eFuse apb2otp block8 data register6. - */ -typedef union { - struct { - /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ - uint32_t apb2otp_block8_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word7 Data */ -/** Type of apb2otp_blk8_w7 register - * eFuse apb2otp block8 data register7. - */ -typedef union { - struct { - /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ - uint32_t apb2otp_block8_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word8 Data */ -/** Type of apb2otp_blk8_w8 register - * eFuse apb2otp block8 data register8. - */ -typedef union { - struct { - /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ - uint32_t apb2otp_block8_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word9 Data */ -/** Type of apb2otp_blk8_w9 register - * eFuse apb2otp block8 data register9. - */ -typedef union { - struct { - /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ - uint32_t apb2otp_block8_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word10 Data */ -/** Type of apb2otp_blk8_w10 register - * eFuse apb2otp block8 data register10. - */ -typedef union { - struct { - /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ - uint32_t apb2otp_block8_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word11 Data */ -/** Type of apb2otp_blk8_w11 register - * eFuse apb2otp block8 data register11. - */ -typedef union { - struct { - /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ - uint32_t apb2otp_block8_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word1 Data */ -/** Type of apb2otp_blk9_w1 register - * eFuse apb2otp block9 data register1. - */ -typedef union { - struct { - /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ - uint32_t apb2otp_block9_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word2 Data */ -/** Type of apb2otp_blk9_w2 register - * eFuse apb2otp block9 data register2. - */ -typedef union { - struct { - /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ - uint32_t apb2otp_block9_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word3 Data */ -/** Type of apb2otp_blk9_w3 register - * eFuse apb2otp block9 data register3. - */ -typedef union { - struct { - /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ - uint32_t apb2otp_block9_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word4 Data */ -/** Type of apb2otp_blk9_w4 register - * eFuse apb2otp block9 data register4. - */ -typedef union { - struct { - /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ - uint32_t apb2otp_block9_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word5 Data */ -/** Type of apb2otp_blk9_w5 register - * eFuse apb2otp block9 data register5. - */ -typedef union { - struct { - /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ - uint32_t apb2otp_block9_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word6 Data */ -/** Type of apb2otp_blk9_w6 register - * eFuse apb2otp block9 data register6. - */ -typedef union { - struct { - /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ - uint32_t apb2otp_block9_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word7 Data */ -/** Type of apb2otp_blk9_w7 register - * eFuse apb2otp block9 data register7. - */ -typedef union { - struct { - /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ - uint32_t apb2otp_block9_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word8 Data */ -/** Type of apb2otp_blk9_w8 register - * eFuse apb2otp block9 data register8. - */ -typedef union { - struct { - /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ - uint32_t apb2otp_block9_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word9 Data */ -/** Type of apb2otp_blk9_w9 register - * eFuse apb2otp block9 data register9. - */ -typedef union { - struct { - /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ - uint32_t apb2otp_block9_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word10 Data */ -/** Type of apb2otp_blk9_w10 register - * eFuse apb2otp block9 data register10. - */ -typedef union { - struct { - /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ - uint32_t apb2otp_block9_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word11 Data */ -/** Type of apb2otp_blk9_w11 register - * eFuse apb2otp block9 data register11. - */ -typedef union { - struct { - /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ - uint32_t apb2otp_block9_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word1 Data */ -/** Type of apb2otp_blk10_w1 register - * eFuse apb2otp block10 data register1. - */ -typedef union { - struct { - /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ - uint32_t apb2otp_block10_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word2 Data */ -/** Type of apb2otp_blk10_w2 register - * eFuse apb2otp block10 data register2. - */ -typedef union { - struct { - /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ - uint32_t apb2otp_block10_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word3 Data */ -/** Type of apb2otp_blk10_w3 register - * eFuse apb2otp block10 data register3. - */ -typedef union { - struct { - /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ - uint32_t apb2otp_block10_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word4 Data */ -/** Type of apb2otp_blk10_w4 register - * eFuse apb2otp block10 data register4. - */ -typedef union { - struct { - /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ - uint32_t apb2otp_block10_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word5 Data */ -/** Type of apb2otp_blk10_w5 register - * eFuse apb2otp block10 data register5. - */ -typedef union { - struct { - /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ - uint32_t apb2otp_block10_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word6 Data */ -/** Type of apb2otp_blk10_w6 register - * eFuse apb2otp block10 data register6. - */ -typedef union { - struct { - /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ - uint32_t apb2otp_block10_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word7 Data */ -/** Type of apb2otp_blk10_w7 register - * eFuse apb2otp block10 data register7. - */ -typedef union { - struct { - /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ - uint32_t apb2otp_block10_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word8 Data */ -/** Type of apb2otp_blk10_w8 register - * eFuse apb2otp block10 data register8. - */ -typedef union { - struct { - /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ - uint32_t apb2otp_block10_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word9 Data */ -/** Type of apb2otp_blk10_w9 register - * eFuse apb2otp block10 data register9. - */ -typedef union { - struct { - /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ - uint32_t apb2otp_block10_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word10 Data */ -/** Type of apb2otp_blk10_w10 register - * eFuse apb2otp block10 data register10. - */ -typedef union { - struct { - /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ - uint32_t apb2otp_block10_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Function Enable Signal */ -/** Type of apb2otp_en register - * eFuse apb2otp enable configuration register. - */ -typedef union { - struct { - /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0; - * Apb2otp mode enable signal. - */ - uint32_t apb2otp_apb2otp_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} efuse_apb2otp_en_reg_t; - - -typedef struct { - volatile efuse_pgm_datan_reg_t pgm_datan[8]; - volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; - volatile efuse_rd_wr_dis_reg_t rd_wr_dis; - volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; - volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; - volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; - volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; - volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; - volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; - volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; - volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; - volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; - volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; - volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; - volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; - volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; - volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; - volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; - volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; - volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; - volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; - volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; - volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; - volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; - volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; - volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; - volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; - volatile efuse_date_reg_t date; - uint32_t reserved_19c[11]; - volatile efuse_clk_reg_t clk; - volatile efuse_conf_reg_t conf; - volatile efuse_ecdsa_reg_t ecdsa; - volatile efuse_status_reg_t status; - volatile efuse_cmd_reg_t cmd; - volatile efuse_int_raw_reg_t int_raw; - volatile efuse_int_st_reg_t int_st; - volatile efuse_int_ena_reg_t int_ena; - volatile efuse_int_clr_reg_t int_clr; - volatile efuse_dac_conf_reg_t dac_conf; - volatile efuse_rd_tim_conf_reg_t rd_tim_conf; - volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; - volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; - volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; - uint32_t reserved_200[192]; - volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; - volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; - volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; - volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3; - volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4; - volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5; - volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1; - volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2; - volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3; - volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4; - volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5; - volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1; - volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2; - volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3; - volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4; - volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5; - volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1; - volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2; - volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3; - volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4; - volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5; - volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1; - volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2; - volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3; - volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4; - volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5; - volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6; - volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7; - volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8; - volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9; - volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1; - volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2; - volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3; - volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4; - volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5; - volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6; - volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7; - volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8; - volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9; - volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10; - volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11; - volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1; - volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2; - volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3; - volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4; - volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5; - volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6; - volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7; - volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8; - volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9; - volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10; - volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11; - volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1; - volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2; - volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3; - volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4; - volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5; - volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6; - volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7; - volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8; - volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9; - volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10; - volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11; - volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1; - volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2; - volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3; - volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4; - volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5; - volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6; - volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7; - volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8; - volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9; - volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10; - volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11; - volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1; - volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2; - volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3; - volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4; - volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5; - volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6; - volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7; - volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8; - volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9; - volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10; - volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11; - volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1; - volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2; - volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3; - volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4; - volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5; - volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6; - volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7; - volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8; - volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9; - volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10; - volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11; - volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1; - volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2; - volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3; - volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4; - volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5; - volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6; - volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7; - volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8; - volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9; - volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10; - volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11; - volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1; - volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2; - volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3; - volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4; - volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5; - volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6; - volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7; - volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8; - volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9; - volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10; - volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11; - volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1; - volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2; - volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3; - volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4; - volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5; - volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6; - volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7; - volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8; - volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9; - volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10; - volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; - uint32_t reserved_704; - volatile efuse_apb2otp_en_reg_t apb2otp_en; -} efuse_dev_t; - -extern efuse_dev_t EFUSE; - -#ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/tools/test_apps/configs/sdkconfig.flash_auto_suspend_iram_reduction b/tools/test_apps/configs/sdkconfig.flash_auto_suspend_iram_reduction index 4f2f56ff3f..1dc627ce6c 100644 --- a/tools/test_apps/configs/sdkconfig.flash_auto_suspend_iram_reduction +++ b/tools/test_apps/configs/sdkconfig.flash_auto_suspend_iram_reduction @@ -32,7 +32,9 @@ CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM=n CONFIG_GDMA_ISR_HANDLER_IN_IRAM=n # BT -CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY=y +# Enabling following config causes a build failures for some targets +# Disabling until this is fixed +# CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY=y # System CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y