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Merge branch 'bugfix/fix_driver_ut_i2s' into 'master'

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bugfix(i2s): fix driver ut i2s

See merge request espressif/esp-idf!6946
This commit is contained in:
Michael (XIAO Xufeng)
2020-03-06 11:55:07 +08:00
parent b7a14c47e6 b3ae9fa978
commit 8e348dcdcd
15 changed files with 359 additions and 228 deletions
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18
components/soc/src/esp32/include/hal/adc_ll.h
View File

@@ -203,18 +203,16 @@ static inline void adc_ll_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t pat
*/
static inline void adc_ll_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_ll_pattern_table_t pattern)
{
uint32_t tab;
uint8_t *arg;
const uint32_t patt_tab_idx = pattern_index / 4;
const uint32_t patt_shift = (3 - (pattern_index % 4)) * 8;
const uint32_t patt_mask = 0xFF << patt_shift;
if (adc_n == ADC_NUM_1) {
tab = SYSCON.saradc_sar1_patt_tab[pattern_index / 4];
arg = (uint8_t *)&tab;
arg[pattern_index % 4] = pattern.val;
SYSCON.saradc_sar1_patt_tab[pattern_index / 4] = tab;
SYSCON.saradc_sar1_patt_tab[patt_tab_idx] &= ~patt_mask;
SYSCON.saradc_sar1_patt_tab[patt_tab_idx] |= pattern.val << patt_shift;
} else { // adc_n == ADC_NUM_2
tab = SYSCON.saradc_sar2_patt_tab[pattern_index / 4];
arg = (uint8_t *)&tab;
arg[pattern_index % 4] = pattern.val;
SYSCON.saradc_sar2_patt_tab[pattern_index / 4] = tab;
SYSCON.saradc_sar2_patt_tab[patt_tab_idx] &= ~patt_mask;
SYSCON.saradc_sar2_patt_tab[patt_tab_idx] |= pattern.val << patt_shift;
}
}

63
components/soc/src/esp32s2/include/hal/adc_ll.h
View File

@@ -2,7 +2,7 @@
#include "soc/adc_periph.h"
#include "hal/adc_types.h"
#include "soc/apb_ctrl_struct.h"
#include "soc/apb_saradc_struct.h"
#include <stdbool.h>
#ifdef __cplusplus
@@ -83,11 +83,11 @@ typedef enum {
static inline void adc_ll_dig_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
{
// Internal FSM reset wait time
APB_CTRL.saradc_fsm_wait.rstb_wait = rst_wait;
APB_SARADC.fsm_wait.rstb_wait = rst_wait;
// Internal FSM start wait time
APB_CTRL.saradc_fsm_wait.xpd_wait = start_wait;
APB_SARADC.fsm_wait.xpd_wait = start_wait;
// Internal FSM standby wait time
APB_CTRL.saradc_fsm_wait.standby_wait = standby_wait;
APB_SARADC.fsm_wait.standby_wait = standby_wait;
}
/**
@@ -99,7 +99,7 @@ static inline void adc_ll_dig_set_fsm_time(uint32_t rst_wait, uint32_t start_wai
*/
static inline void adc_ll_dig_set_sample_cycle(uint32_t sample_cycle)
{
APB_CTRL.saradc_fsm.sample_cycle = sample_cycle;
APB_SARADC.fsm.sample_cycle = sample_cycle;
}
/**
@@ -109,7 +109,7 @@ static inline void adc_ll_dig_set_sample_cycle(uint32_t sample_cycle)
*/
static inline void adc_ll_dig_set_output_format(adc_ll_dig_output_format_t format)
{
APB_CTRL.saradc_ctrl.data_sar_sel = format;
APB_SARADC.ctrl.data_sar_sel = format;
}
/**
@@ -120,7 +120,7 @@ static inline void adc_ll_dig_set_output_format(adc_ll_dig_output_format_t forma
*/
static inline void adc_ll_dig_set_convert_limit_num(uint32_t meas_num)
{
APB_CTRL.saradc_ctrl2.max_meas_num = meas_num;
APB_SARADC.ctrl2.max_meas_num = meas_num;
}
/**
@@ -129,7 +129,7 @@ static inline void adc_ll_dig_set_convert_limit_num(uint32_t meas_num)
*/
static inline void adc_ll_dig_convert_limit_enable(void)
{
APB_CTRL.saradc_ctrl2.meas_num_limit = 1;
APB_SARADC.ctrl2.meas_num_limit = 1;
}
/**
@@ -138,7 +138,7 @@ static inline void adc_ll_dig_convert_limit_enable(void)
*/
static inline void adc_ll_dig_convert_limit_disable(void)
{
APB_CTRL.saradc_ctrl2.meas_num_limit = 0;
APB_SARADC.ctrl2.meas_num_limit = 0;
}
/**
@@ -151,15 +151,15 @@ static inline void adc_ll_dig_convert_limit_disable(void)
static inline void adc_ll_dig_set_convert_mode(adc_ll_convert_mode_t mode)
{
if (mode == ADC_CONV_SINGLE_UNIT_1) {
APB_CTRL.saradc_ctrl.work_mode = 0;
APB_CTRL.saradc_ctrl.sar_sel = 0;
APB_SARADC.ctrl.work_mode = 0;
APB_SARADC.ctrl.sar_sel = 0;
} else if (mode == ADC_CONV_SINGLE_UNIT_2) {
APB_CTRL.saradc_ctrl.work_mode = 0;
APB_CTRL.saradc_ctrl.sar_sel = 1;
APB_SARADC.ctrl.work_mode = 0;
APB_SARADC.ctrl.sar_sel = 1;
} else if (mode == ADC_CONV_BOTH_UNIT) {
APB_CTRL.saradc_ctrl.work_mode = 1;
APB_SARADC.ctrl.work_mode = 1;
} else if (mode == ADC_CONV_ALTER_UNIT) {
APB_CTRL.saradc_ctrl.work_mode = 2;
APB_SARADC.ctrl.work_mode = 2;
}
}
@@ -171,7 +171,7 @@ static inline void adc_ll_dig_set_convert_mode(adc_ll_convert_mode_t mode)
static inline void adc_ll_dig_set_data_source(adc_i2s_source_t src)
{
/* 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix */
APB_CTRL.saradc_ctrl.data_to_i2s = src;
APB_SARADC.ctrl.data_to_i2s = src;
}
/**
@@ -186,9 +186,9 @@ static inline void adc_ll_dig_set_data_source(adc_i2s_source_t src)
static inline void adc_ll_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len)
{
if (adc_n == ADC_NUM_1) {
APB_CTRL.saradc_ctrl.sar1_patt_len = patt_len - 1;
APB_SARADC.ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2
APB_CTRL.saradc_ctrl.sar2_patt_len = patt_len - 1;
APB_SARADC.ctrl.sar2_patt_len = patt_len - 1;
}
}
@@ -204,18 +204,17 @@ static inline void adc_ll_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t pat
*/
static inline void adc_ll_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_ll_pattern_table_t pattern)
{
uint32_t tab;
uint8_t *arg;
const uint32_t patt_tab_idx = pattern_index / 4;
const uint32_t patt_shift = (3 - (pattern_index % 4)) * 8;
const uint32_t patt_mask = 0xFF << patt_shift;
if (adc_n == ADC_NUM_1) {
tab = *(uint32_t *)(&APB_CTRL.saradc_sar1_patt_tab1 + pattern_index / 4);
arg = (uint8_t *)&tab;
arg[pattern_index % 4] = pattern.val;
*(uint32_t *)(&APB_CTRL.saradc_sar1_patt_tab1 + pattern_index / 4) = tab;
} else { // adc_n == ADC_NUM_2
tab = *(uint32_t *)(&APB_CTRL.saradc_sar2_patt_tab1 + pattern_index / 4);
arg = (uint8_t *)&tab;
arg[pattern_index % 4] = pattern.val;
*(uint32_t *)(&APB_CTRL.saradc_sar2_patt_tab1 + pattern_index / 4) = tab;
APB_SARADC.sar1_patt_tab[patt_tab_idx] &= ~patt_mask;
APB_SARADC.sar1_patt_tab[patt_tab_idx] |= pattern.val << patt_shift;
}
else { // adc_n == ADC_NUM_2
APB_SARADC.sar2_patt_tab[patt_tab_idx] &= ~patt_mask;
APB_SARADC.sar2_patt_tab[patt_tab_idx] |= pattern.val << patt_shift;
}
}
@@ -390,7 +389,7 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
static inline void adc_ll_set_clk_div(uint32_t div)
{
/* ADC clock devided from APB clk, e.g. 80 / 2 = 40Mhz, */
APB_CTRL.saradc_ctrl.sar_clk_div = div;
APB_SARADC.ctrl.sar_clk_div = div;
}
/**
@@ -457,9 +456,9 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_dig_output_invert(adc_ll_num_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
APB_CTRL.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
APB_CTRL.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
}
}

143
components/soc/src/esp32s2/include/hal/i2s_ll.h
View File

@@ -353,6 +353,28 @@ static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val)
hw->conf_chan.rx_chan_mod = val;
}
/**
* @brief Set I2S tx dma equal
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx dma equal
*/
static inline void i2s_ll_set_tx_dma_equal(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_dma_equal = val;
}
/**
* @brief Set I2S rx dma equal
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx dma equal
*/
static inline void i2s_ll_set_rx_dma_equal(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_dma_equal = val;
}
/**
* @brief Set I2S out link address
*
@@ -386,61 +408,6 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val)
hw->rx_eof_num = val;
}
/**
* @brief Get I2S tx pdm fp
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to get tx pdm fp
*/
static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val)
{
*val = hw->pdm_freq_conf.tx_pdm_fp;
}
/**
* @brief Get I2S tx pdm fs
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to get tx pdm fs
*/
static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val)
{
*val = hw->pdm_freq_conf.tx_pdm_fs;
}
/**
* @brief Set I2S tx pdm fp
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx pdm fp
*/
static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val)
{
hw->pdm_freq_conf.tx_pdm_fp = val;
}
/**
* @brief Set I2S tx pdm fs
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx pdm fs
*/
static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val)
{
hw->pdm_freq_conf.tx_pdm_fs = val;
}
/**
* @brief Get I2S rx sinc dsr 16 en
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to get rx sinc dsr 16 en
*/
static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val)
{
*val = hw->pdm_conf.rx_sinc_dsr_16_en;
}
/**
* @brief Set I2S clkm div num
*
@@ -529,17 +496,6 @@ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val)
hw->sample_rate_conf.rx_bits_mod = val;
}
/**
* @brief Set I2S rx sinc dsr 16 en
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx sinc dsr 16 en
*/
static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val)
{
hw->pdm_conf.rx_sinc_dsr_16_en = val;
}
/**
* @brief Set I2S dscr en
*
@@ -573,50 +529,6 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val)
hw->conf2.camera_en = val;
}
/**
* @brief Set I2S pcm2pdm conv en
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set pcm2pdm conv en
*/
static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val)
{
hw->pdm_conf.pcm2pdm_conv_en = val;
}
/**
* @brief Set I2S pdm2pcm conv en
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set pdm2pcm conv en
*/
static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val)
{
hw->pdm_conf.pdm2pcm_conv_en = val;
}
/**
* @brief Set I2S rx pdm en
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx pdm en
*/
static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val)
{
hw->pdm_conf.rx_pdm_en = val;
}
/**
* @brief Set I2S tx pdm en
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx pdm en
*/
static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val)
{
hw->pdm_conf.tx_pdm_en = val;
}
/**
* @brief Set I2S tx msb shift
*
@@ -793,17 +705,6 @@ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val)
hw->conf.rx_mono = val;
}
/**
* @brief Set I2S tx sinc osr2
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx sinc osr2
*/
static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val)
{
hw->pdm_conf.tx_sinc_osr2 = val;
}
/**
* @brief Set I2S sig loopback
*

1
components/soc/src/hal/adc_hal.c
View File

@@ -16,7 +16,6 @@
void adc_hal_init(void)
{
adc_ll_set_power_manage(ADC_POWER_BY_FSM);
// Set internal FSM wait time, fixed value.
adc_ll_dig_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);

21
components/soc/src/hal/i2s_hal.c
View File

@@ -32,6 +32,9 @@ void i2s_hal_set_tx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_
i2s_ll_set_tx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 2 : 3);
}
i2s_ll_set_tx_chan_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
#if SOC_I2S_SUPPORTS_DMA_EQUAL
i2s_ll_set_tx_dma_equal(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
#endif
}
void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits)
@@ -42,6 +45,9 @@ void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_
i2s_ll_set_rx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 2 : 3);
}
i2s_ll_set_rx_chan_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
#if SOC_I2S_SUPPORTS_DMA_EQUAL
i2s_ll_set_rx_dma_equal(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
#endif
}
void i2s_hal_set_in_link(i2s_hal_context_t *hal, uint32_t bytes_num, uint32_t addr)
@@ -50,11 +56,13 @@ void i2s_hal_set_in_link(i2s_hal_context_t *hal, uint32_t bytes_num, uint32_t ad
i2s_ll_set_rx_eof_num(hal->dev, bytes_num);
}
#if SOC_I2S_SUPPORTS_PDM
void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, int *fp, int *fs)
{
i2s_ll_get_tx_pdm_fp(hal->dev, (uint32_t *)fp);
i2s_ll_get_tx_pdm_fs(hal->dev, (uint32_t *)fs);
}
#endif
void i2s_hal_set_clk_div(i2s_hal_context_t *hal, int div_num, int div_a, int div_b, int tx_bck_div, int rx_bck_div)
{
@@ -121,8 +129,10 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config
i2s_ll_set_lcd_en(hal->dev, 0);
i2s_ll_set_camera_en(hal->dev, 0);
#if SOC_I2S_SUPPORTS_PDM
i2s_ll_set_pcm2pdm_conv_en(hal->dev, 0);
i2s_ll_set_pdm2pcm_conv_en(hal->dev, 0);
#endif
i2s_ll_set_dscr_en(hal->dev, 0);
@@ -162,13 +172,15 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config
}
}
#if SOC_I2S_SUPPORTS_ADC_DAC
if (i2s_config->mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN)) {
i2s_ll_set_lcd_en(hal->dev, 1);
i2s_ll_set_tx_right_first(hal->dev, 1);
i2s_ll_set_camera_en(hal->dev, 0);
}
#endif
#if SOC_I2S_SUPPORT_PDM
#if SOC_I2S_SUPPORTS_PDM
if (i2s_config->mode & I2S_MODE_PDM) {
i2s_ll_set_rx_fifo_mod_force_en(hal->dev, 1);
i2s_ll_set_tx_fifo_mod_force_en(hal->dev, 1);
@@ -190,11 +202,8 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config
i2s_ll_set_rx_pdm_en(hal->dev, 0);
i2s_ll_set_tx_pdm_en(hal->dev, 0);
}
#else
i2s_ll_set_rx_pdm_en(hal->dev, 0);
i2s_ll_set_tx_pdm_en(hal->dev, 0);
#endif
if (i2s_config->communication_format & I2S_COMM_FORMAT_I2S || i2s_config->communication_format & I2S_COMM_FORMAT_I2S_MSB || i2s_config->communication_format & I2S_COMM_FORMAT_I2S_LSB) {
if (i2s_config->communication_format & I2S_COMM_FORMAT_I2S) {
i2s_ll_set_tx_short_sync(hal->dev, 0);
i2s_ll_set_rx_short_sync(hal->dev, 0);
i2s_ll_set_tx_msb_shift(hal->dev, 1);
@@ -209,7 +218,7 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config
}
}
if (i2s_config->communication_format & I2S_COMM_FORMAT_PCM || i2s_config->communication_format & I2S_COMM_FORMAT_PCM_LONG || i2s_config->communication_format & I2S_COMM_FORMAT_PCM_SHORT) {
if (i2s_config->communication_format & I2S_COMM_FORMAT_PCM) {
i2s_ll_set_tx_msb_shift(hal->dev, 0);
i2s_ll_set_rx_msb_shift(hal->dev, 0);
i2s_ll_set_tx_short_sync(hal->dev, 0);