diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index f6a69f0994..d6a9dbdf71 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/hal/esp32h2/include/hal/lp_clkrst_ll.h b/components/hal/esp32h2/include/hal/lp_clkrst_ll.h index a91f01a857..9556b26996 100644 --- a/components/hal/esp32h2/include/hal/lp_clkrst_ll.h +++ b/components/hal/esp32h2/include/hal/lp_clkrst_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/hal/esp32h2/include/hal/rtc_io_ll.h b/components/hal/esp32h2/include/hal/rtc_io_ll.h index dcd32b2239..4efbe6f8bf 100644 --- a/components/hal/esp32h2/include/hal/rtc_io_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/soc/esp32h2/include/soc/lpperi_reg.h b/components/soc/esp32h2/include/soc/lpperi_reg.h index f4046ad2a3..4587bb9fd6 100644 --- a/components/soc/esp32h2/include/soc/lpperi_reg.h +++ b/components/soc/esp32h2/include/soc/lpperi_reg.h @@ -1,7 +1,7 @@ -/** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,6 +11,34 @@ extern "C" { #endif +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36732976 (0x2308030); + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +/** + * @brief Get the register offset according to the register version + * @note H2 ECO5 inserted a new register LPPERI_RNG_CFG_REG, + * so the addressed of the rest registers are shifted 4 bytes + * This macro can help to get the correct register offset according to the register version + */ +#define LPPERI_REG_OFFSET(offset) (REG_GET_FIELD(LPPERI_DATE_REG, LPPERI_LPPERI_DATE) >= 0x2308030 ? (offset) : (offset) - 4) + + /** LPPERI_CLK_EN_REG register * need_des */ @@ -140,22 +168,40 @@ extern "C" { #define LPPERI_LP_CPU_RESET_EN_V 0x00000001U #define LPPERI_LP_CPU_RESET_EN_S 31 -/** LPPERI_RNG_DATA_REG register +/** LPPERI_RNG_CFG_REG register * need_des */ -#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RNG_CFG_ENABLE : R/W; bitpos: [1:0]; default: 0; + * need_des + * Note: this register only exist on the chips that LPPERI_LPPERI_DATE >= 0x2308030, + * i.e., ESP32-H2 chip_revision >= 1.2 + */ +#define LPPERI_RNG_CFG_ENABLE 0x00000003U +#define LPPERI_RNG_CFG_ENABLE_M (LPPERI_RNG_CFG_ENABLE_V << LPPERI_RNG_CFG_ENABLE_S) +#define LPPERI_RNG_CFG_ENABLE_V 0x00000003U +#define LPPERI_RNG_CFG_ENABLE_S 0 + +/** LPPERI_RNG_DATA_REG register + * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0xc)) /** LPPERI_RNG_DATA : RO; bitpos: [31:0]; default: 0; * need_des */ -#define LPPERI_RNG_DATA 0xFFFFFFFFU -#define LPPERI_RND_GATA_M (LPPERI_RND_GATA_V << LPPERI_RND_GATA_S) -#define LPPERI_RND_GATA_V 0xFFFFFFFFU -#define LPPERI_RND_GATA_S 0 +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 /** LPPERI_CPU_REG register * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x10)) /** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; * need_des */ @@ -166,8 +212,10 @@ extern "C" { /** LPPERI_BUS_TIMEOUT_REG register * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10) +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x14)) /** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; * need_des */ @@ -192,8 +240,10 @@ extern "C" { /** LPPERI_BUS_TIMEOUT_ADDR_REG register * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14) +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x18)) /** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -204,8 +254,10 @@ extern "C" { /** LPPERI_BUS_TIMEOUT_UID_REG register * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18) +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x1c)) /** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; * need_des */ @@ -216,8 +268,10 @@ extern "C" { /** LPPERI_MEM_CTRL_REG register * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c) +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x20)) /** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; * need_des */ @@ -256,8 +310,10 @@ extern "C" { /** LPPERI_INTERRUPT_SOURCE_REG register * need_des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x24)) /** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, * lp_io_int @@ -269,8 +325,10 @@ extern "C" { /** LPPERI_DEBUG_SEL0_REG register * need des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x24) +#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x28)) /** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; * need des */ @@ -302,8 +360,10 @@ extern "C" { /** LPPERI_DEBUG_SEL1_REG register * need des + * Note: this register address is different on different H2 revisions, + * here uses LPPERI_REG_OFFSET to get the compatible offset. */ -#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x28) +#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x2c)) /** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; * need des */ @@ -312,25 +372,6 @@ extern "C" { #define LPPERI_DEBUG_SEL4_V 0x0000007FU #define LPPERI_DEBUG_SEL4_S 0 -/** LPPERI_DATE_REG register - * need_des - */ -#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) -/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 35676464; - * need_des - */ -#define LPPERI_LPPERI_DATE 0x7FFFFFFFU -#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) -#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU -#define LPPERI_LPPERI_DATE_S 0 -/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define LPPERI_CLK_EN (BIT(31)) -#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) -#define LPPERI_CLK_EN_V 0x00000001U -#define LPPERI_CLK_EN_S 31 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/include/soc/lpperi_rev0_0_struct.h b/components/soc/esp32h2/include/soc/lpperi_rev0_0_struct.h new file mode 100644 index 0000000000..b3826439ac --- /dev/null +++ b/components/soc/esp32h2/include/soc/lpperi_rev0_0_struct.h @@ -0,0 +1,310 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/** + * @file lpperi_rev0_0_struct.h + * @brief Applicable to the ESP32-H2 that chip revision < 1.2. + */ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_rev0_0_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_rev0_0_reset_en_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rev0_0_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_rev0_0_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_rev0_0_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_rev0_0_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_rev0_0_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_rev0_0_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_rev0_0_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_rev0_0_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_rev0_0_debug_sel1_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 35676464; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_rev0_0_date_reg_t; + + +typedef struct { + volatile lpperi_rev0_0_clk_en_reg_t clk_en; + volatile lpperi_rev0_0_reset_en_reg_t reset_en; + volatile lpperi_rev0_0_rng_data_reg_t rng_data; + volatile lpperi_rev0_0_cpu_reg_t cpu; + volatile lpperi_rev0_0_bus_timeout_reg_t bus_timeout; + volatile lpperi_rev0_0_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_rev0_0_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_rev0_0_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_rev0_0_interrupt_source_reg_t interrupt_source; + volatile lpperi_rev0_0_debug_sel0_reg_t debug_sel0; + volatile lpperi_rev0_0_debug_sel1_reg_t debug_sel1; + uint32_t reserved_02c[244]; + volatile lpperi_rev0_0_date_reg_t date; +} lpperi_rev0_0_dev_t; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_rev0_0_dev_t) == 0x400, "Invalid size of lpperi_rev0_0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lpperi_rev1_2_struct.h b/components/soc/esp32h2/include/soc/lpperi_rev1_2_struct.h new file mode 100644 index 0000000000..338f92014b --- /dev/null +++ b/components/soc/esp32h2/include/soc/lpperi_rev1_2_struct.h @@ -0,0 +1,325 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +/** + * @file lpperi_rev1_2_struct.h + * @brief Applicable to the ESP32-H2 that chip revision >= 1.2. + */ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_cfg_enable : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t rng_cfg_enable:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_debug_sel1_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 36732976 (0x2308030); + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_cfg_reg_t rng_cfg; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_debug_sel0_reg_t debug_sel0; + volatile lpperi_debug_sel1_reg_t debug_sel1; + uint32_t reserved_030[243]; + volatile lpperi_date_reg_t date; +} lpperi_rev1_2_dev_t; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_rev1_2_dev_t) == 0x400, "Invalid size of lpperi_rev1_2_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/lpperi_struct.h b/components/soc/esp32h2/include/soc/lpperi_struct.h index c5456eed1b..f450ede75c 100644 --- a/components/soc/esp32h2/include/soc/lpperi_struct.h +++ b/components/soc/esp32h2/include/soc/lpperi_struct.h @@ -1,306 +1,49 @@ /** - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ + +/* This is a wrapper for revisions compatibility */ + #pragma once +#include "soc/lpperi_rev0_0_struct.h" +#include "soc/lpperi_rev1_2_struct.h" + #include #ifdef __cplusplus extern "C" { #endif -/** Group: configure_register */ -/** Type of clk_en register - * need_des +/** + * @brief Compatible lpperi struct wrapper + * */ typedef union { - struct { - uint32_t reserved_0:24; - /** rng_ck_en : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t rng_ck_en:1; - /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; - * need_des - */ - uint32_t otp_dbg_ck_en:1; - /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; - * need_des - */ - uint32_t lp_uart_ck_en:1; - /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t lp_io_ck_en:1; - /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; - * need_des - */ - uint32_t lp_ext_i2c_ck_en:1; - /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; - * need_des - */ - uint32_t lp_ana_i2c_ck_en:1; - /** efuse_ck_en : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t efuse_ck_en:1; - /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_ck_en:1; - }; - uint32_t val; -} lpperi_clk_en_reg_t; - -/** Type of reset_en register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** bus_reset_en : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t bus_reset_en:1; - /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t lp_ble_timer_reset_en:1; - /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t otp_dbg_reset_en:1; - /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t lp_uart_reset_en:1; - /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_io_reset_en:1; - /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_ext_i2c_reset_en:1; - /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_ana_i2c_reset_en:1; - /** efuse_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t efuse_reset_en:1; - /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_reset_en:1; - }; - uint32_t val; -} lpperi_reset_en_reg_t; - -/** Type of rng_data register - * need_des - */ -typedef union { - struct { - /** rng_data : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t rng_data:32; - }; - uint32_t val; -} lpperi_rng_data_reg_t; - -/** Type of cpu register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lpcore_dbgm_unavaliable:1; - }; - uint32_t val; -} lpperi_cpu_reg_t; - -/** Type of bus_timeout register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:14; - /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; - * need_des - */ - uint32_t lp_peri_timeout_thres:16; - /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_peri_timeout_int_clear:1; - /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_peri_timeout_protect_en:1; - }; - uint32_t val; -} lpperi_bus_timeout_reg_t; - -/** Type of bus_timeout_addr register - * need_des - */ -typedef union { - struct { - /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t lp_peri_timeout_addr:32; - }; - uint32_t val; -} lpperi_bus_timeout_addr_reg_t; - -/** Type of bus_timeout_uid register - * need_des - */ -typedef union { - struct { - /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; - * need_des - */ - uint32_t lp_peri_timeout_uid:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} lpperi_bus_timeout_uid_reg_t; - -/** Type of mem_ctrl register - * need_des - */ -typedef union { - struct { - /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t uart_wakeup_flag_clr:1; - /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; - * need_des - */ - uint32_t uart_wakeup_flag:1; - uint32_t reserved_2:27; - /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t uart_wakeup_en:1; - /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t uart_mem_force_pd:1; - /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t uart_mem_force_pu:1; - }; - uint32_t val; -} lpperi_mem_ctrl_reg_t; - -/** Type of interrupt_source register - * need_des - */ -typedef union { - struct { - /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; - * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, - * lp_io_int - */ - uint32_t lp_interrupt_source:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} lpperi_interrupt_source_reg_t; - -/** Type of debug_sel0 register - * need des - */ -typedef union { - struct { - /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; - * need des - */ - uint32_t debug_sel0:7; - /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; - * need des - */ - uint32_t debug_sel1:7; - /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; - * need des - */ - uint32_t debug_sel2:7; - /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; - * need des - */ - uint32_t debug_sel3:7; - uint32_t reserved_28:4; - }; - uint32_t val; -} lpperi_debug_sel0_reg_t; - -/** Type of debug_sel1 register - * need des - */ -typedef union { - struct { - /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; - * need des - */ - uint32_t debug_sel4:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} lpperi_debug_sel1_reg_t; - - -/** Group: Version register */ -/** Type of date register - * need_des - */ -typedef union { - struct { - /** lpperi_date : R/W; bitpos: [30:0]; default: 35676464; - * need_des - */ - uint32_t lpperi_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} lpperi_date_reg_t; - - -typedef struct { - volatile lpperi_clk_en_reg_t clk_en; - volatile lpperi_reset_en_reg_t reset_en; - volatile lpperi_rng_data_reg_t rng_data; - volatile lpperi_cpu_reg_t cpu; - volatile lpperi_bus_timeout_reg_t bus_timeout; - volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; - volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; - volatile lpperi_mem_ctrl_reg_t mem_ctrl; - volatile lpperi_interrupt_source_reg_t interrupt_source; - volatile lpperi_debug_sel0_reg_t debug_sel0; - volatile lpperi_debug_sel1_reg_t debug_sel1; - uint32_t reserved_02c[244]; - volatile lpperi_date_reg_t date; + volatile lpperi_rev0_0_dev_t rev0_0; /* Struct for LPPERI v0.0 < rev < v1.2 */ + volatile lpperi_rev1_2_dev_t rev1_2; /* Struct for LPPERI rev >= v1.2*/ } lpperi_dev_t; extern lpperi_dev_t LPPERI; -#ifndef __cplusplus -_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); -#endif +/** The LPPERI date version of chip revision 1.2*/ +#define LPPERI_REV1_2_DATE (0x2308030) + +/** + * @brief Set the register value compatibly + * @param reg The register to set (can carry the field, like clk_en.lp_io_ck_en) + * @param val The value to set + */ +#define LPPERI_REG_SET(reg, val) (LPPERI.rev1_2.date.lpperi_date >= LPPERI_REV1_2_DATE ? \ + (LPPERI.rev1_2.reg = (val)) : (LPPERI.rev0_0.reg = (val))) + +/** + * @brief Get the register value compatibly + * @param reg The register to get (can carry the field, like clk_en.lp_io_ck_en) + */ +#define LPPERI_REG_GET(reg) (LPPERI.rev1_2.date.lpperi_date >= LPPERI_REV1_2_DATE ? \ + (LPPERI.rev1_2.reg) : (LPPERI.rev0_0.reg)) #ifdef __cplusplus } diff --git a/components/soc/esp32h2/ld/esp32h2.peripherals.ld b/components/soc/esp32h2/ld/esp32h2.peripherals.ld index faac00ad3c..91acc8d394 100644 --- a/components/soc/esp32h2/ld/esp32h2.peripherals.ld +++ b/components/soc/esp32h2/ld/esp32h2.peripherals.ld @@ -66,7 +66,7 @@ PROVIDE ( LP_TIMER = 0x600B0C00 ); PROVIDE ( LP_AON = 0x600B1000 ); PROVIDE ( LP_WDT = 0x600B1C00 ); PROVIDE ( I2C_ANA_MST = 0x600B2400 ); -PROVIDE ( LP_PERI = 0x600B2800 ); +PROVIDE ( LPPERI = 0x600B2800 ); PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); PROVIDE ( LP_APM = 0x600B3800 ); PROVIDE ( OTP_DEBUG = 0x600B3C00 );