change(cache): no use sdkconfig in cache/mmu hal

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c

@@ -22,6 +22,7 @@
 #include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"
 #include "hal/gpio_hal.h"
+#include "hal/mmu_hal.h"
 #include "flash_qio_mode.h"
 #include "bootloader_common.h"
 #include "bootloader_flash_config.h"
@@ -453,6 +454,14 @@ void bootloader_flash_hardware_init(void)
     Cache_Flush(1);
 #endif
     mmu_init(0);
+    mmu_hal_config_t mmu_config = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        .core_nums = 1,
+#else
+        .core_nums = SOC_CPU_CORES_NUM,
+#endif
+    };
+    mmu_hal_ctx_init(&mmu_config);
 #if !CONFIG_FREERTOS_UNICORE
     /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
         necessary to work around a hardware bug. */

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c

@@ -307,10 +307,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
 

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c

@@ -315,10 +315,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -292,10 +292,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c

@@ -275,10 +275,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c

@@ -281,10 +281,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c

@@ -278,10 +278,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c

@@ -266,10 +266,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c

@@ -276,12 +276,11 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
+
     // Check and run XMC startup flow
     esp_err_t ret = bootloader_flash_xmc_startup();
     assert(ret == ESP_OK);

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c

@@ -286,12 +286,11 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(0, false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //reset mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
+
     // Check and run XMC startup flow
     esp_err_t ret = bootloader_flash_xmc_startup();
     assert(ret == ESP_OK);

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c

@@ -313,10 +313,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
 
-    // init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked.
     REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
     // update flash ID

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c

@@ -340,10 +340,9 @@ void bootloader_flash_hardware_init(void)
 {
     esp_rom_spiflash_attach(esp_rom_efuse_get_flash_gpio_info(), false);
 
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
+
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/private_include/bootloader_init.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -55,6 +55,11 @@ void bootloader_print_banner(void);
  */
 esp_err_t bootloader_init(void);
 
+/**
+ * @brief Initialize cache and mmu
+ */
+void bootloader_init_ext_mem(void);
+
 #ifdef __cplusplus
 }
 #endif

components/bootloader_support/src/bootloader_init.c

@@ -15,9 +15,12 @@
 #include "bootloader_clock.h"
 #include "bootloader_common.h"
 #include "esp_cpu.h"
+#include "soc/soc_caps.h"
 #include "soc/rtc.h"
 #include "hal/wdt_hal.h"
 #include "hal/efuse_hal.h"
+#include "hal/cache_hal.h"
+#include "hal/mmu_hal.h"
 #include "esp_bootloader_desc.h"
 #include "esp_rom_sys.h"
 
@@ -123,3 +126,30 @@ void bootloader_print_banner(void)
     ESP_EARLY_LOGI(TAG, "Multicore bootloader");
 #endif
 }
+
+void bootloader_init_ext_mem(void)
+{
+    //init cache hal
+    cache_hal_config_t cache_config = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        .core_nums = 1,
+#else
+        .core_nums = SOC_CPU_CORES_NUM,
+#endif
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+        .l2_cache_size = CONFIG_CACHE_L2_CACHE_SIZE,
+        .l2_cache_line_size = CONFIG_CACHE_L2_CACHE_LINE_SIZE,
+#endif
+    };
+    cache_hal_init(&cache_config);
+    //reset mmu
+    mmu_hal_config_t mmu_config = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        .core_nums = 1,
+#else
+        .core_nums = SOC_CPU_CORES_NUM,
+#endif
+        .mmu_page_size = CONFIG_MMU_PAGE_SIZE,
+    };
+    mmu_hal_init(&mmu_config);
+}

components/bootloader_support/src/esp32/bootloader_esp32.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,6 +27,7 @@
 #include "soc/rtc.h"
 #include "soc/spi_periph.h"
 #include "hal/gpio_hal.h"
+#include "hal/mmu_hal.h"
 #include "xtensa/config/core.h"
 #include "xt_instr_macros.h"
 
@@ -60,6 +61,15 @@ static void bootloader_reset_mmu(void)
     DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
 #endif
 
+    mmu_hal_config_t mmu_config = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        .core_nums = 1,
+#else
+        .core_nums = SOC_CPU_CORES_NUM,
+#endif
+    };
+    mmu_hal_ctx_init(&mmu_config);
+
     /* normal ROM boot exits with DROM0 cache unmasked,
         but serial bootloader exits with it masked. */
     DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);

components/bootloader_support/src/esp32c2/bootloader_esp32c2.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -119,10 +119,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // read bootloader header

components/bootloader_support/src/esp32c3/bootloader_esp32c3.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -158,10 +158,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -139,10 +139,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32c6/bootloader_esp32c6.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -142,10 +142,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -130,10 +130,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -139,10 +139,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32h21/bootloader_esp32h21.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -136,10 +136,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32h4/bootloader_esp32h4.c

@@ -150,10 +150,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -160,10 +160,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //reset mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/bootloader_support/src/esp32s2/bootloader_esp32s2.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -140,10 +140,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    // init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked.
     REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
     // update flash ID

components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -180,10 +180,8 @@ esp_err_t bootloader_init(void)
     bootloader_print_banner();
 
 #if !CONFIG_APP_BUILD_TYPE_RAM
-    //init cache hal
+    // init cache and mmu
-    cache_hal_init();
+    bootloader_init_ext_mem();
-    //init mmu
-    mmu_hal_init();
     // update flash ID
     bootloader_flash_update_id();
     // Check and run XMC startup flow

components/esp_system/port/cpu_start.c

@@ -96,6 +96,7 @@
 #include "soc/rtc.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/mmu_hal.h"
 #include "hal/efuse_ll.h"
 #include "hal/uart_ll.h"
 #include "soc/uart_pins.h"
@@ -463,15 +464,35 @@ FORCE_INLINE_ATTR IRAM_ATTR void ram_app_init(void)
 
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 //Keep this static, the compiler will check output parameters are initialized.
-FORCE_INLINE_ATTR IRAM_ATTR void cache_init(void)
+FORCE_INLINE_ATTR IRAM_ATTR void ext_mem_init(void)
 {
 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
     // It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
     do_multicore_settings();
 #endif
 
+    cache_hal_config_t config = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        .core_nums = 1,
+#else
+        .core_nums = SOC_CPU_CORES_NUM,
+#endif
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+        .l2_cache_size = CONFIG_CACHE_L2_CACHE_SIZE,
+        .l2_cache_line_size = CONFIG_CACHE_L2_CACHE_LINE_SIZE,
+#endif
+    };
     //cache hal ctx needs to be initialised
-    cache_hal_init();
+    cache_hal_init(&config);
+    //mmu hal ctx needs to be initialised
+    mmu_hal_config_t mmu_config = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        .core_nums = 1,
+#else
+        .core_nums = SOC_CPU_CORES_NUM,
+#endif
+    };
+    mmu_hal_ctx_init(&mmu_config);
 
 #if CONFIG_IDF_TARGET_ESP32S2
     /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
@@ -921,9 +942,9 @@ void IRAM_ATTR call_start_cpu0(void)
     ram_app_init();
 #endif  //CONFIG_APP_BUILD_TYPE_RAM
 
-    // Initialize the cache.
+    // Initialize the cache and mmu.
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-    cache_init();
+    ext_mem_init();
 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 
     sys_rtc_init(rst_reas);

components/hal/cache_hal.c

@@ -6,7 +6,6 @@
 #include <sys/param.h>
 #include <stdint.h>
 #include <stdbool.h>
-#include "sdkconfig.h"
 #include "esp_err.h"
 #include "esp_attr.h"
 #include "hal/assert.h"
@@ -56,31 +55,30 @@ void s_cache_hal_init_ctx(void)
 }
 
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-//TODO: IDF-5670, add cache init API, then don't need sdkconfig
+void cache_hal_init_l2_cache(const cache_hal_config_t *config)
-void cache_hal_init_l2_cache(void)
 {
     cache_size_t cache_size;
     cache_line_size_t cache_line_size;
-#if CONFIG_CACHE_L2_CACHE_128KB
+    if (config->l2_cache_size == 0x20000) {
-    cache_size = CACHE_SIZE_128K;
+        cache_size = CACHE_SIZE_128K;
-#elif CONFIG_CACHE_L2_CACHE_256KB
+    } else if (config->l2_cache_size == 0x40000) {
-    cache_size = CACHE_SIZE_256K;
+        cache_size = CACHE_SIZE_256K;
-#else
+    } else {
-    cache_size = CACHE_SIZE_512K;
+        cache_size = CACHE_SIZE_512K;
-#endif
+    }
 
-#if CONFIG_CACHE_L2_CACHE_LINE_64B
+    if (config->l2_cache_line_size == 64) {
-    cache_line_size = CACHE_LINE_SIZE_64B;
+        cache_line_size = CACHE_LINE_SIZE_64B;
-#else
+    } else {
-    cache_line_size = CACHE_LINE_SIZE_128B;
+        cache_line_size = CACHE_LINE_SIZE_128B;
-#endif
+    }
 
     Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size);
     Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
 }
 #endif
 
-void cache_hal_init(void)
+void cache_hal_init(const cache_hal_config_t *config)
 {
     s_cache_hal_init_ctx();
 
@@ -90,12 +88,10 @@ void cache_hal_init(void)
         cache_ll_enable_cache(2, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, ctx.l2.i_autoload_en, ctx.l2.d_autoload_en);
     }
 
-    cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK);
+    for (int i = 0; i < config->core_nums; i++) {
-    cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK);
+        cache_ll_l1_enable_bus(i, CACHE_LL_DEFAULT_DBUS_MASK);
-#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        cache_ll_l1_enable_bus(i, CACHE_LL_DEFAULT_IBUS_MASK);
-    cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK);
+    }
-    cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK);
-#endif
 
 #if CACHE_LL_ENABLE_DISABLE_STATE_SW
     ctx.l1.i_cache_enabled = 1;
@@ -105,7 +101,7 @@ void cache_hal_init(void)
 #endif
 
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-    cache_hal_init_l2_cache();
+    cache_hal_init_l2_cache(config);
 #endif
 }
 

components/hal/esp32/cache_hal_esp32.c

@@ -8,7 +8,7 @@
 
 static uint32_t s_cache_status[2];
 
-void cache_hal_init(void)
+void cache_hal_init(const cache_hal_config_t *config)
 {
     //for compatibility
 }

components/hal/include/hal/cache_hal.h

@@ -1,6 +1,6 @@
 
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,9 +17,20 @@ extern "C" {
 #endif
 
 /**
- * Cache init and cache hal context init
+ * @brief Cache hal config
  */
-void cache_hal_init(void);
+typedef struct {
+    uint8_t core_nums;              ///< CPU core numbers
+    uint32_t l2_cache_size;         ///< L2 cache size
+    uint32_t l2_cache_line_size;    ///< L2 cache line size
+} cache_hal_config_t;
+
+/**
+ * Cache init and cache hal context init
+ *
+ * @param config  Cache hal config
+ */
+void cache_hal_init(const cache_hal_config_t *config);
 
 /**
  * @brief Disable Cache

components/hal/include/hal/mmu_hal.h

@@ -15,9 +15,26 @@ extern "C" {
 #endif
 
 /**
- * MMU Hal layer initialisation
+ * @brief MMU hal config
  */
-void mmu_hal_init(void);
+typedef struct {
+    uint8_t core_nums;         ///< CPU core numbers
+    uint32_t mmu_page_size;    ///< MMU page size
+} mmu_hal_config_t;
+
+/**
+ * MMU Hal layer initialisation
+ *
+ * @param config  MMU hal config
+ */
+void mmu_hal_init(const mmu_hal_config_t *config);
+
+/**
+ * MMU Hal layer context initialisation
+ *
+ * @param config  MMU hal config
+ */
+void mmu_hal_ctx_init(const mmu_hal_config_t *config);
 
 /**
  * Unmap all the MMU table. After this all external memory vaddr are not available

components/hal/mmu_hal.c

@@ -6,7 +6,6 @@
 #include <sys/param.h>
 #include <stdint.h>
 #include <stdbool.h>
-#include "sdkconfig.h"
 #include "esp_err.h"
 #include "esp_attr.h"
 #include "hal/assert.h"
@@ -14,14 +13,27 @@
 #include "hal/mmu_ll.h"
 #include "soc/soc_caps.h"
 #include "rom/cache.h"
+#include "esp_rom_caps.h"
 
-void mmu_hal_init(void)
+typedef struct {
+    uint8_t core_nums;
+} mmu_hal_context_t;
+
+static mmu_hal_context_t s_ctx;
+
+void mmu_hal_ctx_init(const mmu_hal_config_t *config)
 {
-#if CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT
+    s_ctx.core_nums = config->core_nums;
+}
+
+void mmu_hal_init(const mmu_hal_config_t *config)
+{
+    mmu_hal_ctx_init(config);
+
+#if ESP_ROM_RAM_APP_NEEDS_MMU_INIT
     ROM_Boot_Cache_Init();
 #endif
-
+    mmu_ll_set_page_size(0, config->mmu_page_size);
-    mmu_ll_set_page_size(0, CONFIG_MMU_PAGE_SIZE);
     mmu_hal_unmap_all();
 }
 
@@ -31,10 +43,9 @@ void mmu_hal_unmap_all(void)
     mmu_ll_unmap_all(MMU_LL_FLASH_MMU_ID);
     mmu_ll_unmap_all(MMU_LL_PSRAM_MMU_ID);
 #else
-    mmu_ll_unmap_all(0);
+    for (int i = 0; i < s_ctx.core_nums; i++) {
-#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+        mmu_ll_unmap_all(i);
-    mmu_ll_unmap_all(1);
+    }
-#endif
 #endif
 }
 

tools/ci/sg_rules/no_kconfig_in_hal_component.yml

@@ -14,8 +14,6 @@ ignores:
   - "components/esp_hal*/test_apps/**/*"
   # the following files should be refactored to remove Kconfig macros
   - "components/hal/adc_oneshot_hal.c"
-  - "components/hal/cache_hal.c"
-  - "components/hal/mmu_hal.c"
   - "components/hal/twai_hal_sja1000.c"
   - "components/hal/esp32/include/hal/twai_ll.h"
   - "components/hal/esp32/include/hal/uart_ll.h"
@@ -53,8 +51,6 @@ ignores:
   - "components/esp_hal*/test_apps/**/*"
   # the following files should be refactored to remove sdkconfig.h
   - "components/hal/adc_oneshot_hal.c"
-  - "components/hal/cache_hal.c"
-  - "components/hal/mmu_hal.c"
   - "components/hal/twai_hal_sja1000.c"
   - "components/hal/include/hal/twai_types_deprecated.h"
 rule: