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Power Management: update pmu init and sleep parameter

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This commit is contained in:
Lou Tianhao
2023-05-29 12:01:36 +08:00
parent 3b40ce4d9b
commit 8ef8459c0d
2 changed files with 16 additions and 22 deletions
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6
components/esp_hw_support/port/esp32h2/pmu_param.c
View File

@@ -166,7 +166,7 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod
.syscntl = { \ .syscntl = { \
.uart_wakeup_en = 1, \ .uart_wakeup_en = 1, \
.lp_pad_hold_all = 0, \ .lp_pad_hold_all = 0, \
.hp_pad_hold_all = 1, \ .hp_pad_hold_all = 0, \
.dig_pad_slp_sel = 1, \ .dig_pad_slp_sel = 1, \
.dig_pause_wdt = 1, \ .dig_pause_wdt = 1, \
.dig_cpu_stall = 1 \ .dig_cpu_stall = 1 \
@@ -176,8 +176,8 @@ const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mod
#define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \ #define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \
.syscntl = { \ .syscntl = { \
.uart_wakeup_en = 1, \ .uart_wakeup_en = 1, \
.lp_pad_hold_all = 1, \ .lp_pad_hold_all = 0, \
.hp_pad_hold_all = 1, \ .hp_pad_hold_all = 0, \
.dig_pad_slp_sel = 0, \ .dig_pad_slp_sel = 0, \
.dig_pause_wdt = 1, \ .dig_pause_wdt = 1, \
.dig_cpu_stall = 1 \ .dig_cpu_stall = 1 \

32
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
View File

@@ -172,38 +172,36 @@ typedef struct {
.hp_sys = { \ .hp_sys = { \
.analog = { \ .analog = { \
.xpd_bias = 0x0, \ .xpd_bias = 0x0, \
.dbg_atten = 0x0, \
.pd_cur = 1, \ .pd_cur = 1, \
.bias_sleep = 1, \ .bias_sleep = 1, \
.slp_mem_xpd = 1, \ .slp_mem_xpd = 0, \
.slp_logic_xpd = 1, \ .slp_logic_xpd = 0, \
.slp_mem_dbias = 0x4, \ .slp_mem_dbias = 0, \
.slp_logic_dbias = 0x4, \ .slp_logic_dbias = 0, \
.xpd = 0, \ .xpd = 1, \
.dbias = 0, \ .dbias = 0, \
.drv_b = 0 \ .drv_b = 0xFFFFF8 \
} \ } \
}, \ }, \
.lp_sys[PMU_MODE_LP_ACTIVE] = { \ .lp_sys[PMU_MODE_LP_ACTIVE] = { \
.analog = { \ .analog = { \
.slp_xpd = 0, \ .slp_xpd = 0, \
.slp_dbias = 0xc, \ .slp_dbias = 0x0, \
.xpd = 1, \ .xpd = 1, \
.dbias = 0x1a, \ .dbias = 0xe, \
.drv_b = 0x0 \ .drv_b = 0x0 \
} \ } \
}, \ }, \
.lp_sys[PMU_MODE_LP_SLEEP] = { \ .lp_sys[PMU_MODE_LP_SLEEP] = { \
.analog = { \ .analog = { \
.xpd_bias = 0, \ .xpd_bias = 0, \
.dbg_atten = 0x0, \
.pd_cur = 1, \ .pd_cur = 1, \
.bias_sleep = 1, \ .bias_sleep = 1, \
.xpd = 0, \ .xpd = 0, \
.dbias = 0x1c, \ .dbias = 0, \
.slp_xpd = 1, \ .slp_xpd = 1, \
.slp_dbias = 0x3, \ .slp_dbias = 0x5, \
.drv_b = 0x0 \ .drv_b = 0x7 \
} \ } \
} \ } \
} }
@@ -294,8 +292,6 @@ typedef struct pmu_sleep_machine_constant {
} lp; } lp;
struct { struct {
uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */
uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */
uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */
uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */ uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */
uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ uint16_t power_supply_wait_time_us; /* (unit: microsecond) */
uint16_t power_up_wait_time_us; /* (unit: microsecond) */ uint16_t power_up_wait_time_us; /* (unit: microsecond) */
@@ -318,13 +314,11 @@ typedef struct pmu_sleep_machine_constant {
}, \ }, \
.hp = { \ .hp = { \
.min_slp_time_us = 450, \ .min_slp_time_us = 450, \
.clock_domain_sync_time_us = 150, \
.system_dfs_up_work_time_us = 124, \
.analog_wait_time_us = 154, \ .analog_wait_time_us = 154, \
.power_supply_wait_time_us = 2, \ .power_supply_wait_time_us = 2, \
.power_up_wait_time_us = 2, \ .power_up_wait_time_us = 2, \
.regdma_s2a_work_time_us = 430, \ .regdma_s2a_work_time_us = 0, \
.regdma_a2s_work_time_us = 338, \ .regdma_a2s_work_time_us = 0, \
.xtal_wait_stable_time_us = 250, \ .xtal_wait_stable_time_us = 250, \
.pll_wait_stable_time_us = 1 \ .pll_wait_stable_time_us = 1 \
} \ } \