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https://github.com/espressif/esp-idf.git
synced 2026-05-19 23:45:28 +02:00
dac: optimize the dma stratege
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@@ -9,7 +9,9 @@ menu "A2DP Example Configuration"
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config EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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bool "Internal DAC"
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help
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Select this to use Internal DAC sink output
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Select this to use Internal DAC sink output,
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note that DAC_DMA_AUTO_16BIT_ALIGN should be turned off
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because the audio data are already 16-bit width
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config EXAMPLE_A2DP_SINK_OUTPUT_EXTERNAL_I2S
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bool "External I2S Codec"
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@@ -22,7 +22,7 @@
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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#include "driver/dac_driver.h"
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#include "driver/dac_conti.h"
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#else
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#include "driver/i2s_std.h"
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#endif
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@@ -55,7 +55,7 @@ static bool s_volume_notify;
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#ifndef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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extern i2s_chan_handle_t tx_chan;
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#else
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extern dac_channels_handle_t tx_chan;
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extern dac_conti_handle_t tx_chan;
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#endif
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/* callback for A2DP sink */
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@@ -172,17 +172,21 @@ static void bt_av_hdl_a2d_evt(uint16_t event, void *p_param)
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sample_rate = 48000;
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}
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#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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dac_conti_disable(tx_chan);
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dac_del_conti_channels(tx_chan);
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dac_conti_config_t conti_cfg = {
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.freq_hz = sample_rate,
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.chan_mode = DAC_CHANNEL_MODE_ALTER,
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.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
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.desc_num = 6,
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.chan_mask = DAC_CHANNEL_MASK_ALL,
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.desc_num = 8,
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.buf_size = 2048,
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.freq_hz = sample_rate,
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.offset = 127,
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.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // Using APLL as clock source to get a wider frequency range
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.chan_mode = DAC_CHANNEL_MODE_ALTER,
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};
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dac_channels_disable_continuous_mode(tx_chan);
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dac_channels_deinit_continuous_mode(tx_chan);
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dac_channels_init_continuous_mode(tx_chan, &conti_cfg);
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dac_channels_enable_continuous_mode(tx_chan);
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/* Allocate continuous channels */
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dac_new_conti_channels(&conti_cfg, &tx_chan);
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/* Enable the continuous channels */
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dac_conti_enable(tx_chan);
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#else
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i2s_channel_disable(tx_chan);
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i2s_std_clk_config_t clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(sample_rate);
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@@ -16,7 +16,7 @@
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#include "bt_app_core.h"
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#include "freertos/ringbuf.h"
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#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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#include "driver/dac_driver.h"
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#include "driver/dac_conti.h"
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#else
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#include "driver/i2s_std.h"
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#endif
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@@ -32,7 +32,7 @@ static RingbufHandle_t s_ringbuf_i2s = NULL;
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#ifndef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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extern i2s_chan_handle_t tx_chan;
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#else
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extern dac_channels_handle_t tx_chan;
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extern dac_conti_handle_t tx_chan;
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#endif
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bool bt_app_work_dispatch(bt_app_cb_t p_cback, uint16_t event, void *p_params, int param_len, bt_app_copy_cb_t p_copy_cback)
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@@ -133,7 +133,7 @@ static void bt_i2s_task_handler(void *arg)
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data = (uint8_t *)xRingbufferReceive(s_ringbuf_i2s, &item_size, (TickType_t)portMAX_DELAY);
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if (item_size != 0){
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#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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dac_channels_write_continuously(tx_chan, data, item_size, &bytes_written, portMAX_DELAY);
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dac_conti_write(tx_chan, data, item_size, &bytes_written, -1);
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#else
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i2s_channel_write(tx_chan, data, item_size, &bytes_written, portMAX_DELAY);
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#endif
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@@ -36,8 +36,7 @@
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#include "esp_a2dp_api.h"
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#include "esp_avrc_api.h"
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#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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// DAC DMA mode is only supported by the legacy I2S driver, it will be replaced once DAC has its own DMA dirver
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#include "driver/dac_driver.h"
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#include "driver/dac_conti.h"
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#else
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#include "driver/i2s_std.h"
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#endif
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@@ -78,7 +77,7 @@ static prepare_type_env_t b_prepare_write_env;
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#ifndef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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i2s_chan_handle_t tx_chan;
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#else
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dac_channels_handle_t tx_chan;
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dac_conti_handle_t tx_chan;
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#endif
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//Declare the static function
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@@ -693,24 +692,19 @@ void app_main(void)
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ESP_ERROR_CHECK(err);
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#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
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dac_channels_config_t cfg = {
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.chan_sel = DAC_CHANNEL_MASK_BOTH,
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};
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dac_conti_config_t conti_cfg = {
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.freq_hz = 44100,
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.chan_mode = DAC_CHANNEL_MODE_ALTER,
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.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
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.desc_num = 6,
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.chan_mask = DAC_CHANNEL_MASK_ALL,
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.desc_num = 8,
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.buf_size = 2048,
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.freq_hz = 44100,
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.offset = 127,
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.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // Using APLL as clock source to get a wider frequency range
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.chan_mode = DAC_CHANNEL_MODE_ALTER,
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};
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/* Allocate the channel group */
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ESP_ERROR_CHECK(dac_new_channels(&cfg, &tx_chan));
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/* Enable the channels in the group */
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ESP_ERROR_CHECK(dac_channels_enable(tx_chan));
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/* Initialize DAC DMA peripheral */
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ESP_ERROR_CHECK(dac_channels_init_continuous_mode(tx_chan, conti_cfg));
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/* Start the DAC DMA peripheral */
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ESP_ERROR_CHECK(dac_channels_enable_continuous_mode(tx_chan));
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/* Allocate continuous channels */
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ESP_ERROR_CHECK(dac_new_conti_channels(&conti_cfg, &tx_chan));
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/* Enable the continuous channels */
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ESP_ERROR_CHECK(dac_conti_enable(tx_chan));
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#else
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i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
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chan_cfg.auto_clear = true;
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@@ -29,4 +29,4 @@ CONFIG_BT_ACL_CONNECTIONS=4
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CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=n
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CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=n
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CONFIG_BT_SMP_ENABLE=y
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CONFIG_I2S_SUPPRESS_DEPRECATE_WARN=y
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CONFIG_DAC_DMA_AUTO_16BIT_ALIGN=n
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