dac: optimize the dma stratege

This commit is contained in:
laokaiyao
2022-10-10 19:17:22 +08:00
parent f9f9a09dfb
commit 8ef9fd4623
113 changed files with 9162 additions and 7829 deletions
@@ -9,7 +9,9 @@ menu "A2DP Example Configuration"
config EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
bool "Internal DAC"
help
Select this to use Internal DAC sink output
Select this to use Internal DAC sink output,
note that DAC_DMA_AUTO_16BIT_ALIGN should be turned off
because the audio data are already 16-bit width
config EXAMPLE_A2DP_SINK_OUTPUT_EXTERNAL_I2S
bool "External I2S Codec"
@@ -22,7 +22,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
#include "driver/dac_driver.h"
#include "driver/dac_conti.h"
#else
#include "driver/i2s_std.h"
#endif
@@ -55,7 +55,7 @@ static bool s_volume_notify;
#ifndef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
extern i2s_chan_handle_t tx_chan;
#else
extern dac_channels_handle_t tx_chan;
extern dac_conti_handle_t tx_chan;
#endif
/* callback for A2DP sink */
@@ -172,17 +172,21 @@ static void bt_av_hdl_a2d_evt(uint16_t event, void *p_param)
sample_rate = 48000;
}
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
dac_conti_disable(tx_chan);
dac_del_conti_channels(tx_chan);
dac_conti_config_t conti_cfg = {
.freq_hz = sample_rate,
.chan_mode = DAC_CHANNEL_MODE_ALTER,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
.desc_num = 6,
.chan_mask = DAC_CHANNEL_MASK_ALL,
.desc_num = 8,
.buf_size = 2048,
.freq_hz = sample_rate,
.offset = 127,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // Using APLL as clock source to get a wider frequency range
.chan_mode = DAC_CHANNEL_MODE_ALTER,
};
dac_channels_disable_continuous_mode(tx_chan);
dac_channels_deinit_continuous_mode(tx_chan);
dac_channels_init_continuous_mode(tx_chan, &conti_cfg);
dac_channels_enable_continuous_mode(tx_chan);
/* Allocate continuous channels */
dac_new_conti_channels(&conti_cfg, &tx_chan);
/* Enable the continuous channels */
dac_conti_enable(tx_chan);
#else
i2s_channel_disable(tx_chan);
i2s_std_clk_config_t clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(sample_rate);
@@ -16,7 +16,7 @@
#include "bt_app_core.h"
#include "freertos/ringbuf.h"
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
#include "driver/dac_driver.h"
#include "driver/dac_conti.h"
#else
#include "driver/i2s_std.h"
#endif
@@ -32,7 +32,7 @@ static RingbufHandle_t s_ringbuf_i2s = NULL;
#ifndef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
extern i2s_chan_handle_t tx_chan;
#else
extern dac_channels_handle_t tx_chan;
extern dac_conti_handle_t tx_chan;
#endif
bool bt_app_work_dispatch(bt_app_cb_t p_cback, uint16_t event, void *p_params, int param_len, bt_app_copy_cb_t p_copy_cback)
@@ -133,7 +133,7 @@ static void bt_i2s_task_handler(void *arg)
data = (uint8_t *)xRingbufferReceive(s_ringbuf_i2s, &item_size, (TickType_t)portMAX_DELAY);
if (item_size != 0){
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
dac_channels_write_continuously(tx_chan, data, item_size, &bytes_written, portMAX_DELAY);
dac_conti_write(tx_chan, data, item_size, &bytes_written, -1);
#else
i2s_channel_write(tx_chan, data, item_size, &bytes_written, portMAX_DELAY);
#endif
@@ -36,8 +36,7 @@
#include "esp_a2dp_api.h"
#include "esp_avrc_api.h"
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
// DAC DMA mode is only supported by the legacy I2S driver, it will be replaced once DAC has its own DMA dirver
#include "driver/dac_driver.h"
#include "driver/dac_conti.h"
#else
#include "driver/i2s_std.h"
#endif
@@ -78,7 +77,7 @@ static prepare_type_env_t b_prepare_write_env;
#ifndef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
i2s_chan_handle_t tx_chan;
#else
dac_channels_handle_t tx_chan;
dac_conti_handle_t tx_chan;
#endif
//Declare the static function
@@ -693,24 +692,19 @@ void app_main(void)
ESP_ERROR_CHECK(err);
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
dac_channels_config_t cfg = {
.chan_sel = DAC_CHANNEL_MASK_BOTH,
};
dac_conti_config_t conti_cfg = {
.freq_hz = 44100,
.chan_mode = DAC_CHANNEL_MODE_ALTER,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
.desc_num = 6,
.chan_mask = DAC_CHANNEL_MASK_ALL,
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 44100,
.offset = 127,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // Using APLL as clock source to get a wider frequency range
.chan_mode = DAC_CHANNEL_MODE_ALTER,
};
/* Allocate the channel group */
ESP_ERROR_CHECK(dac_new_channels(&cfg, &tx_chan));
/* Enable the channels in the group */
ESP_ERROR_CHECK(dac_channels_enable(tx_chan));
/* Initialize DAC DMA peripheral */
ESP_ERROR_CHECK(dac_channels_init_continuous_mode(tx_chan, conti_cfg));
/* Start the DAC DMA peripheral */
ESP_ERROR_CHECK(dac_channels_enable_continuous_mode(tx_chan));
/* Allocate continuous channels */
ESP_ERROR_CHECK(dac_new_conti_channels(&conti_cfg, &tx_chan));
/* Enable the continuous channels */
ESP_ERROR_CHECK(dac_conti_enable(tx_chan));
#else
i2s_chan_config_t chan_cfg = I2S_CHANNEL_DEFAULT_CONFIG(I2S_NUM_0, I2S_ROLE_MASTER);
chan_cfg.auto_clear = true;
@@ -29,4 +29,4 @@ CONFIG_BT_ACL_CONNECTIONS=4
CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=n
CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=n
CONFIG_BT_SMP_ENABLE=y
CONFIG_I2S_SUPPRESS_DEPRECATE_WARN=y
CONFIG_DAC_DMA_AUTO_16BIT_ALIGN=n