diff --git a/components/soc/esp32h21/register/soc/i2c_reg.h b/components/soc/esp32h21/register/soc/i2c_reg.h index 9b4a07e16a..9999169b89 100644 --- a/components/soc/esp32h21/register/soc/i2c_reg.h +++ b/components/soc/esp32h21/register/soc/i2c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,13 +12,12 @@ extern "C" { #endif /** I2C_SCL_LOW_PERIOD_REG register - * Configures the low level width of the SCL - * Clock + * Configures the low level width of the SCL Clock */ #define I2C_SCL_LOW_PERIOD_REG(i) (DR_REG_I2C_BASE(i) + 0x0) /** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure for how long SCL remains low in master mode, in - * I2C module clock cycles. + * Configures the low level width of the SCL Clock in Master mode. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_LOW_PERIOD 0x000001FFU #define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) @@ -26,119 +25,139 @@ extern "C" { #define I2C_SCL_LOW_PERIOD_S 0 /** I2C_CTR_REG register - * Transmission setting + * Transmission setting register */ #define I2C_CTR_REG(i) (DR_REG_I2C_BASE(i) + 0x4) /** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; - * 1: direct output, 0: open drain output. + * Configures the SDA output mode. + * 0: Open drain output + * 1: Direct output */ #define I2C_SDA_FORCE_OUT (BIT(0)) #define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) #define I2C_SDA_FORCE_OUT_V 0x00000001U #define I2C_SDA_FORCE_OUT_S 0 /** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; - * 1: direct output, 0: open drain output. + * Configures the SCL output mode. + * 0: Open drain output + * 1: Direct output */ #define I2C_SCL_FORCE_OUT (BIT(1)) #define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) #define I2C_SCL_FORCE_OUT_V 0x00000001U #define I2C_SCL_FORCE_OUT_S 1 /** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; - * This register is used to select the sample mode. - * 1: sample SDA data on the SCL low level. - * 0: sample SDA data on the SCL high level. + * Configures the sample mode for SDA. + * 0: Sample SDA data on the SCL high level + * 1: Sample SDA data on the SCL low level */ #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) #define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U #define I2C_SAMPLE_SCL_LEVEL_S 2 -/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; - * This register is used to configure the ACK value that need to sent by master when - * the rx_fifo_cnt has reached the threshold. +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 0; + * Configures the ACK value that needs to be sent by master when rx_fifo_cnt has + * reached the threshold. */ #define I2C_RX_FULL_ACK_LEVEL (BIT(3)) #define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) #define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U #define I2C_RX_FULL_ACK_LEVEL_S 3 /** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; - * Set this bit to configure the module as an I2C Master. Clear this bit to configure - * the - * module as an I2C Slave. + * Configures the module as an I2C Master or Slave. + * 0: Slave + * 1: Master */ #define I2C_MS_MODE (BIT(4)) #define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) #define I2C_MS_MODE_V 0x00000001U #define I2C_MS_MODE_S 4 /** I2C_TRANS_START : WT; bitpos: [5]; default: 0; - * Set this bit to start sending the data in txfifo. + * Configures whether the slave starts sending the data in TX FIFO. + * 0: No effect + * 1: Start */ #define I2C_TRANS_START (BIT(5)) #define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) #define I2C_TRANS_START_V 0x00000001U #define I2C_TRANS_START_S 5 /** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; - * This bit is used to control the sending mode for data needing to be sent. - * 1: send data from the least significant bit, - * 0: send data from the most significant bit. + * Configures whether or not to control the sending order for data needing to be sent. + * 0: Send data from the most significant bit + * 1: Send data from the least significant bit */ #define I2C_TX_LSB_FIRST (BIT(6)) #define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) #define I2C_TX_LSB_FIRST_V 0x00000001U #define I2C_TX_LSB_FIRST_S 6 /** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; - * This bit is used to control the storage mode for received data. - * 1: receive data from the least significant bit, - * 0: receive data from the most significant bit. + * Configures whether or not to control the storage order for received data. + * 0: Receive data from the most significant bit + * 1: Receive data from the least significant bit */ #define I2C_RX_LSB_FIRST (BIT(7)) #define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) #define I2C_RX_LSB_FIRST_V 0x00000001U #define I2C_RX_LSB_FIRST_S 7 /** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; - * Reserved + * Configures whether to gate clock signal for registers. + * 0: Support clock only when registers are read or written to by software + * 1: Force clock on for registers */ #define I2C_CLK_EN (BIT(8)) #define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) #define I2C_CLK_EN_V 0x00000001U #define I2C_CLK_EN_S 8 -/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; - * This is the enable bit for arbitration_lost. +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 0; + * Configures whether to enable I2C bus arbitration detection. + * 0: No effect + * 1: Enable */ #define I2C_ARBITRATION_EN (BIT(9)) #define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) #define I2C_ARBITRATION_EN_V 0x00000001U #define I2C_ARBITRATION_EN_S 9 /** I2C_FSM_RST : WT; bitpos: [10]; default: 0; - * This register is used to reset the scl FMS. + * Configures whether to reset the SCL_FSM. + * 0: No effect + * 1: Reset */ #define I2C_FSM_RST (BIT(10)) #define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) #define I2C_FSM_RST_V 0x00000001U #define I2C_FSM_RST_S 10 /** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; - * synchronization bit + * Configures the bit for synchronization. + * 0: No effect + * 1: Synchronize */ #define I2C_CONF_UPGATE (BIT(11)) #define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) #define I2C_CONF_UPGATE_V 0x00000001U #define I2C_CONF_UPGATE_S 11 /** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; - * This is the enable bit for slave to send data automatically + * Configures whether to enable slave to send data automatically + * 0: Disable + * 1: Enable */ #define I2C_SLV_TX_AUTO_START_EN (BIT(12)) #define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) #define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U #define I2C_SLV_TX_AUTO_START_EN_S 12 /** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; - * This is the enable bit to check if the r/w bit of 10bit addressing consists with - * I2C protocol + * Configures whether to check if the $R/\overline W$ bit of 10-bit addressing + * consists with I2C protocol. + * 0: Not check + * 1: Check */ #define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) #define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) #define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U #define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 /** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; - * This is the enable bit to support the 7bit general call function. + * Configures whether to support the 7-bit general call function. + * 0: Not support + * 1: Support */ #define I2C_ADDR_BROADCASTING_EN (BIT(14)) #define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) @@ -146,80 +165,103 @@ extern "C" { #define I2C_ADDR_BROADCASTING_EN_S 14 /** I2C_SR_REG register - * Describe I2C work status. + * I2C working status register */ #define I2C_SR_REG(i) (DR_REG_I2C_BASE(i) + 0x8) /** I2C_RESP_REC : RO; bitpos: [0]; default: 0; - * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + * Represents the received ACK value in Master mode or Slave mode. + * 0: ACK + * 1: NACK */ #define I2C_RESP_REC (BIT(0)) #define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) #define I2C_RESP_REC_V 0x00000001U #define I2C_RESP_REC_S 0 /** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; - * When in slave mode, 1: master reads from slave, 0: master writes to slave. + * Represents the transfer direction in Slave mode. + * 0: Master writes to slave + * 1: Master reads from slave */ #define I2C_SLAVE_RW (BIT(1)) #define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) #define I2C_SLAVE_RW_V 0x00000001U #define I2C_SLAVE_RW_S 1 /** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; - * When the I2C controller loses control of SCL line, this register changes to 1. + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * 1: Arbitration lost */ #define I2C_ARB_LOST (BIT(3)) #define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) #define I2C_ARB_LOST_V 0x00000001U #define I2C_ARB_LOST_S 3 /** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; - * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + * Represents the I2C bus state. + * 0: The I2C bus is in idle state + * 1: The I2C bus is busy transferring data */ #define I2C_BUS_BUSY (BIT(4)) #define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) #define I2C_BUS_BUSY_V 0x00000001U #define I2C_BUS_BUSY_S 4 /** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; - * When configured as an I2C Slave, and the address sent by the master is - * equal to the address of the slave, then this bit will be of high level. + * Represents whether the address sent by the master is equal to the address of the + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * 1: Equal */ #define I2C_SLAVE_ADDRESSED (BIT(5)) #define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) #define I2C_SLAVE_ADDRESSED_V 0x00000001U #define I2C_SLAVE_ADDRESSED_S 5 /** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; - * This field represents the amount of data needed to be sent. + * Represents the number of data bytes received in RAM. */ #define I2C_RXFIFO_CNT 0x0000003FU #define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) #define I2C_RXFIFO_CNT_V 0x0000003FU #define I2C_RXFIFO_CNT_S 8 -/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; - * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the - * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty - * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 0; + * Represents the cause of SCL clocking stretching in Slave mode. + * 0: Stretching SCL low when the master starts to read data. + * 1: Stretching SCL low when I2C TX FIFO is empty in Slave mode. + * 2: Stretching SCL low when I2C RX FIFO is full in Slave mode. */ #define I2C_STRETCH_CAUSE 0x00000003U #define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) #define I2C_STRETCH_CAUSE_V 0x00000003U #define I2C_STRETCH_CAUSE_S 14 /** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; - * This field stores the amount of received data in RAM. + * Represents the number of data bytes to be sent. */ #define I2C_TXFIFO_CNT 0x0000003FU #define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) #define I2C_TXFIFO_CNT_V 0x0000003FU #define I2C_TXFIFO_CNT_S 18 /** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; - * This field indicates the states of the I2C module state machine. - * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: - * Wait ACK + * Represents the states of the I2C module state machine. + * 0: Idle + * 1: Address shift + * 2: ACK address + * 3: Rx data + * 4: Tx data + * 5: Send ACK + * 6: Wait ACK */ #define I2C_SCL_MAIN_STATE_LAST 0x00000007U #define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) #define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U #define I2C_SCL_MAIN_STATE_LAST_S 24 /** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; - * This field indicates the states of the state machine used to produce SCL. - * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + * Represents the states of the state machine used to produce SCL. + * 0: Idle + * 1: Start + * 2: Negative edge + * 3: Low + * 4: Positive edge + * 5: High + * 6: Stop */ #define I2C_SCL_STATE_LAST 0x00000007U #define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) @@ -227,19 +269,22 @@ extern "C" { #define I2C_SCL_STATE_LAST_S 28 /** I2C_TO_REG register - * Setting time out control for receiving data. + * Timeout control register for receiving data */ #define I2C_TO_REG(i) (DR_REG_I2C_BASE(i) + 0xc) /** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; - * This register is used to configure the timeout for receiving a data bit in APB - * clock cycles. + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2\^{}(reg_time_out_value). + * Measurement unit: I2C_SCLK */ #define I2C_TIME_OUT_VALUE 0x0000001FU #define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) #define I2C_TIME_OUT_VALUE_V 0x0000001FU #define I2C_TIME_OUT_VALUE_S 0 /** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; - * This is the enable bit for time out control. + * Configures whether to enable timeout control. + * 0: No effect + * 1: Enable */ #define I2C_TIME_OUT_EN (BIT(5)) #define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) @@ -247,18 +292,20 @@ extern "C" { #define I2C_TIME_OUT_EN_S 5 /** I2C_SLAVE_ADDR_REG register - * Local slave address setting + * Local slave address setting register */ #define I2C_SLAVE_ADDR_REG(i) (DR_REG_I2C_BASE(i) + 0x10) /** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; - * When configured as an I2C Slave, this field is used to configure the slave address. + * Configures the slave address of the I2C slave. */ #define I2C_SLAVE_ADDR 0x00007FFFU #define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) #define I2C_SLAVE_ADDR_V 0x00007FFFU #define I2C_SLAVE_ADDR_S 0 /** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; - * This field is used to enable the slave 10-bit addressing mode in master mode. + * Configures whether to enable the slave 10-bit addressing mode in Master mode. + * 0: No effect + * 1: Enable */ #define I2C_ADDR_10BIT_EN (BIT(31)) #define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) @@ -266,39 +313,40 @@ extern "C" { #define I2C_ADDR_10BIT_EN_S 31 /** I2C_FIFO_ST_REG register - * FIFO status register. + * FIFO status register */ #define I2C_FIFO_ST_REG(i) (DR_REG_I2C_BASE(i) + 0x14) /** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; - * This is the offset address of the APB reading from rxfifo + * Represents the offset address of the APB reading from RX FIFO. */ #define I2C_RXFIFO_RADDR 0x0000001FU #define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) #define I2C_RXFIFO_RADDR_V 0x0000001FU #define I2C_RXFIFO_RADDR_S 0 /** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; - * This is the offset address of i2c module receiving data and writing to rxfifo. + * Represents the offset address of i2c module receiving data and writing to RX FIFO. */ #define I2C_RXFIFO_WADDR 0x0000001FU #define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) #define I2C_RXFIFO_WADDR_V 0x0000001FU #define I2C_RXFIFO_WADDR_S 5 /** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; - * This is the offset address of i2c module reading from txfifo. + * Represents the offset address of I2C module reading from TX FIFO. */ #define I2C_TXFIFO_RADDR 0x0000001FU #define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) #define I2C_TXFIFO_RADDR_V 0x0000001FU #define I2C_TXFIFO_RADDR_S 10 /** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; - * This is the offset address of APB bus writing to txfifo. + * Represents the offset address of APB bus writing to TX FIFO. */ #define I2C_TXFIFO_WADDR 0x0000001FU #define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) #define I2C_TXFIFO_WADDR_V 0x0000001FU #define I2C_TXFIFO_WADDR_S 15 /** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; - * The received data in I2C slave mode. + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C Slave mode. */ #define I2C_SLAVE_RW_POINT 0x000000FFU #define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) @@ -306,59 +354,69 @@ extern "C" { #define I2C_SLAVE_RW_POINT_S 22 /** I2C_FIFO_CONF_REG register - * FIFO configuration register. + * FIFO configuration register */ #define I2C_FIFO_CONF_REG(i) (DR_REG_I2C_BASE(i) + 0x18) -/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; - * The water mark threshold of rx FIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than - * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 0; + * Configures the watermark threshold of RX FIFO in non-FIFO access mode. When + * I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], + * the I2C_RXFIFO_WM_INT_RAW bit will be valid. */ #define I2C_RXFIFO_WM_THRHD 0x0000001FU #define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) #define I2C_RXFIFO_WM_THRHD_V 0x0000001FU #define I2C_RXFIFO_WM_THRHD_S 0 -/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; - * The water mark threshold of tx FIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than - * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 0; + * Configures the watermark threshold of TX FIFO in non-FIFO access mode. When + * I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0], + * the I2C_TXFIFO_WM_INT_RAW bit will be valid. */ #define I2C_TXFIFO_WM_THRHD 0x0000001FU #define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) #define I2C_TXFIFO_WM_THRHD_V 0x0000001FU #define I2C_TXFIFO_WM_THRHD_S 5 /** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; - * Set this bit to enable APB nonfifo access. + * Configures whether to enable APB non-FIFO access. */ #define I2C_NONFIFO_EN (BIT(10)) #define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) #define I2C_NONFIFO_EN_V 0x00000001U #define I2C_NONFIFO_EN_S 10 /** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; - * When this bit is set to 1, the byte received after the I2C address byte represents - * the offset address in the I2C Slave RAM. + * Configures the slave to enable dual address mode. When this mode is enabled, the + * byte received after the I2C address byte represents the offset address in the I2C + * Slave RAM. + * 0: Disable + * 1: Enable */ #define I2C_FIFO_ADDR_CFG_EN (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) #define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U #define I2C_FIFO_ADDR_CFG_EN_S 11 /** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; - * Set this bit to reset rx-fifo. + * Configures whether or not to reset RX FIFO. + * 0: No effect + * 1: Reset */ #define I2C_RX_FIFO_RST (BIT(12)) #define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) #define I2C_RX_FIFO_RST_V 0x00000001U #define I2C_RX_FIFO_RST_S 12 /** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; - * Set this bit to reset tx-fifo. + * Configures whether or not to reset TX FIFO. + * 0: No effect + * 1: Reset */ #define I2C_TX_FIFO_RST (BIT(13)) #define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) #define I2C_TX_FIFO_RST_V 0x00000001U #define I2C_TX_FIFO_RST_S 13 -/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; - * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls - * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 0; + * Configures whether to enable FIFO pointer in non-FIFO access mode. This bit + * controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty + * interrupts. + * 0: No effect + * 1: Enable */ #define I2C_FIFO_PRT_EN (BIT(14)) #define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) @@ -366,11 +424,11 @@ extern "C" { #define I2C_FIFO_PRT_EN_S 14 /** I2C_DATA_REG register - * Rx FIFO read data. + * Rx FIFO read data */ #define I2C_DATA_REG(i) (DR_REG_I2C_BASE(i) + 0x1c) -/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0; - * The value of rx FIFO read data. +/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; + * Represents the value of RX FIFO read data. */ #define I2C_FIFO_RDATA 0x000000FFU #define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) @@ -378,137 +436,137 @@ extern "C" { #define I2C_FIFO_RDATA_S 0 /** I2C_INT_RAW_REG register - * Raw interrupt status + * Raw interrupt status register */ #define I2C_INT_RAW_REG(i) (DR_REG_I2C_BASE(i) + 0x20) /** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + * The raw interrupt status of I2C_RXFIFO_WM_INT. */ #define I2C_RXFIFO_WM_INT_RAW (BIT(0)) #define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) #define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U #define I2C_RXFIFO_WM_INT_RAW_S 0 -/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of I2C_TXFIFO_WM_INT. */ #define I2C_TXFIFO_WM_INT_RAW (BIT(1)) #define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) #define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U #define I2C_TXFIFO_WM_INT_RAW_S 1 /** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + * The raw interrupt status of I2C_RXFIFO_OVF_INT. */ #define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) #define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U #define I2C_RXFIFO_OVF_INT_RAW_S 2 /** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + * The raw interrupt status of I2C_END_DETECT_INT. */ #define I2C_END_DETECT_INT_RAW (BIT(3)) #define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) #define I2C_END_DETECT_INT_RAW_V 0x00000001U #define I2C_END_DETECT_INT_RAW_S 3 /** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + * The raw interrupt status of I2C_BYTE_TRANS_DONE_INT. */ #define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) #define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 /** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + * The raw interrupt status of I2C_ARBITRATION_LOST_INT. */ #define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) #define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_RAW_S 5 /** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + * The raw interrupt status of I2C_MST_TXFIFO_UDF_INT. */ #define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) #define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 /** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT. */ #define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) #define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_RAW_S 7 /** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + * The raw interrupt status of I2C_TIME_OUT_INT. */ #define I2C_TIME_OUT_INT_RAW (BIT(8)) #define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) #define I2C_TIME_OUT_INT_RAW_V 0x00000001U #define I2C_TIME_OUT_INT_RAW_S 8 /** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + * The raw interrupt status of I2C_TRANS_START_INT. */ #define I2C_TRANS_START_INT_RAW (BIT(9)) #define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) #define I2C_TRANS_START_INT_RAW_V 0x00000001U #define I2C_TRANS_START_INT_RAW_S 9 /** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + * The raw interrupt status of I2C_NACK_INT. */ #define I2C_NACK_INT_RAW (BIT(10)) #define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) #define I2C_NACK_INT_RAW_V 0x00000001U #define I2C_NACK_INT_RAW_S 10 /** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + * The raw interrupt status of I2C_TXFIFO_OVF_INT. */ #define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) #define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) #define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U #define I2C_TXFIFO_OVF_INT_RAW_S 11 /** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + * The raw interrupt status of I2C_RXFIFO_UDF_INT. */ #define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) #define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) #define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U #define I2C_RXFIFO_UDF_INT_RAW_S 12 /** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + * The raw interrupt status of I2C_SCL_ST_TO_INT. */ #define I2C_SCL_ST_TO_INT_RAW (BIT(13)) #define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) #define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U #define I2C_SCL_ST_TO_INT_RAW_S 13 /** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT. */ #define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) #define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 /** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt bit for I2C_DET_START_INT interrupt. + * The raw interrupt status of I2C_DET_START_INT. */ #define I2C_DET_START_INT_RAW (BIT(15)) #define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) #define I2C_DET_START_INT_RAW_V 0x00000001U #define I2C_DET_START_INT_RAW_S 15 /** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + * The raw interrupt status of I2C_SLAVE_STRETCH_INT. */ #define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) #define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) #define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U #define I2C_SLAVE_STRETCH_INT_RAW_S 16 /** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; - * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + * The raw interrupt status of I2C_GENERAL_CALL_INT. */ #define I2C_GENERAL_CALL_INT_RAW (BIT(17)) #define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) #define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U #define I2C_GENERAL_CALL_INT_RAW_S 17 /** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0; - * The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT. */ #define I2C_SLAVE_ADDR_UNMATCH_INT_RAW (BIT(18)) #define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S) @@ -516,137 +574,137 @@ extern "C" { #define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S 18 /** I2C_INT_CLR_REG register - * Interrupt clear bits + * Interrupt clear register */ #define I2C_INT_CLR_REG(i) (DR_REG_I2C_BASE(i) + 0x24) /** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + * Write 1 to clear I2C_RXFIFO_WM_INT. */ #define I2C_RXFIFO_WM_INT_CLR (BIT(0)) #define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) #define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U #define I2C_RXFIFO_WM_INT_CLR_S 0 /** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + * Write 1 to clear I2C_TXFIFO_WM_INT. */ #define I2C_TXFIFO_WM_INT_CLR (BIT(1)) #define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) #define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U #define I2C_TXFIFO_WM_INT_CLR_S 1 /** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + * Write 1 to clear I2C_RXFIFO_OVF_INT. */ #define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) #define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U #define I2C_RXFIFO_OVF_INT_CLR_S 2 /** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. + * Write 1 to clear I2C_END_DETECT_INT. */ #define I2C_END_DETECT_INT_CLR (BIT(3)) #define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) #define I2C_END_DETECT_INT_CLR_V 0x00000001U #define I2C_END_DETECT_INT_CLR_S 3 /** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. + * Write 1 to clear I2C_BYTE_TRANS_DONE_INT. */ #define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) #define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 /** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + * Write 1 to clear I2C_ARBITRATION_LOST_INT. */ #define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) #define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_CLR_S 5 /** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to clear I2C_MST_TXFIFO_UDF_INT. */ #define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) #define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 /** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to clear I2C_TRANS_COMPLETE_INT. */ #define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) #define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_CLR_S 7 /** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + * Write 1 to clear I2C_TIME_OUT_INT. */ #define I2C_TIME_OUT_INT_CLR (BIT(8)) #define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) #define I2C_TIME_OUT_INT_CLR_V 0x00000001U #define I2C_TIME_OUT_INT_CLR_S 8 /** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the I2C_TRANS_START_INT interrupt. + * Write 1 to clear I2C_TRANS_START_INT. */ #define I2C_TRANS_START_INT_CLR (BIT(9)) #define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) #define I2C_TRANS_START_INT_CLR_V 0x00000001U #define I2C_TRANS_START_INT_CLR_S 9 /** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to clear I2C_NACK_INT. */ #define I2C_NACK_INT_CLR (BIT(10)) #define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) #define I2C_NACK_INT_CLR_V 0x00000001U #define I2C_NACK_INT_CLR_S 10 /** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + * Write 1 to clear I2C_TXFIFO_OVF_INT. */ #define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) #define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) #define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U #define I2C_TXFIFO_OVF_INT_CLR_S 11 /** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + * Write 1 to clear I2C_RXFIFO_UDF_INT. */ #define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) #define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) #define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U #define I2C_RXFIFO_UDF_INT_CLR_S 12 /** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + * Write 1 to clear I2C_SCL_ST_TO_INT. */ #define I2C_SCL_ST_TO_INT_CLR (BIT(13)) #define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) #define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U #define I2C_SCL_ST_TO_INT_CLR_S 13 /** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT. */ #define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) #define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 /** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear I2C_DET_START_INT interrupt. + * Write 1 to clear I2C_DET_START_INT. */ #define I2C_DET_START_INT_CLR (BIT(15)) #define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) #define I2C_DET_START_INT_CLR_V 0x00000001U #define I2C_DET_START_INT_CLR_S 15 /** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to clear I2C_SLAVE_STRETCH_INT. */ #define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) #define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) #define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U #define I2C_SLAVE_STRETCH_INT_CLR_S 16 /** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; - * Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + * Write 1 to clear I2C_GENERAL_CALL_INT. */ #define I2C_GENERAL_CALL_INT_CLR (BIT(17)) #define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) #define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U #define I2C_GENERAL_CALL_INT_CLR_S 17 /** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0; - * Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT. */ #define I2C_SLAVE_ADDR_UNMATCH_INT_CLR (BIT(18)) #define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S) @@ -654,137 +712,137 @@ extern "C" { #define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S 18 /** I2C_INT_ENA_REG register - * Interrupt enable bits + * Interrupt enable register */ #define I2C_INT_ENA_REG(i) (DR_REG_I2C_BASE(i) + 0x28) /** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + * Write 1 to enable I2C_RXFIFO_WM_INT. */ #define I2C_RXFIFO_WM_INT_ENA (BIT(0)) #define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) #define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U #define I2C_RXFIFO_WM_INT_ENA_S 0 /** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + * Write 1 to enable I2C_TXFIFO_WM_INT. */ #define I2C_TXFIFO_WM_INT_ENA (BIT(1)) #define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) #define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U #define I2C_TXFIFO_WM_INT_ENA_S 1 /** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + * Write 1 to enable I2C_RXFIFO_OVF_INT. */ #define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) #define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U #define I2C_RXFIFO_OVF_INT_ENA_S 2 /** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + * Write 1 to enable I2C_END_DETECT_INT. */ #define I2C_END_DETECT_INT_ENA (BIT(3)) #define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) #define I2C_END_DETECT_INT_ENA_V 0x00000001U #define I2C_END_DETECT_INT_ENA_S 3 /** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + * Write 1 to enable I2C_BYTE_TRANS_DONE_INT. */ #define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) #define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 /** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + * Write 1 to enable I2C_ARBITRATION_LOST_INT. */ #define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) #define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_ENA_S 5 /** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to enable I2C_MST_TXFIFO_UDF_INT. */ #define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) #define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 /** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to enable I2C_TRANS_COMPLETE_INT. */ #define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) #define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_ENA_S 7 /** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + * Write 1 to enable I2C_TIME_OUT_INT. */ #define I2C_TIME_OUT_INT_ENA (BIT(8)) #define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) #define I2C_TIME_OUT_INT_ENA_V 0x00000001U #define I2C_TIME_OUT_INT_ENA_S 8 /** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + * Write 1 to enable I2C_TRANS_START_INT. */ #define I2C_TRANS_START_INT_ENA (BIT(9)) #define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) #define I2C_TRANS_START_INT_ENA_V 0x00000001U #define I2C_TRANS_START_INT_ENA_S 9 /** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to enable I2C_NACK_INT. */ #define I2C_NACK_INT_ENA (BIT(10)) #define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) #define I2C_NACK_INT_ENA_V 0x00000001U #define I2C_NACK_INT_ENA_S 10 /** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + * Write 1 to enable I2C_TXFIFO_OVF_INT. */ #define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) #define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) #define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U #define I2C_TXFIFO_OVF_INT_ENA_S 11 /** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + * Write 1 to enable I2C_RXFIFO_UDF_INT. */ #define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) #define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) #define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U #define I2C_RXFIFO_UDF_INT_ENA_S 12 /** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + * Write 1 to enable I2C_SCL_ST_TO_INT. */ #define I2C_SCL_ST_TO_INT_ENA (BIT(13)) #define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) #define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U #define I2C_SCL_ST_TO_INT_ENA_S 13 /** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT. */ #define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) #define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 /** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for I2C_DET_START_INT interrupt. + * Write 1 to enable I2C_DET_START_INT. */ #define I2C_DET_START_INT_ENA (BIT(15)) #define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) #define I2C_DET_START_INT_ENA_V 0x00000001U #define I2C_DET_START_INT_ENA_S 15 /** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to enable I2C_SLAVE_STRETCH_INT. */ #define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) #define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) #define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U #define I2C_SLAVE_STRETCH_INT_ENA_S 16 /** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; - * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + * Write 1 to enable I2C_GENERAL_CALL_INT. */ #define I2C_GENERAL_CALL_INT_ENA (BIT(17)) #define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) #define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U #define I2C_GENERAL_CALL_INT_ENA_S 17 /** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0; - * The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT. */ #define I2C_SLAVE_ADDR_UNMATCH_INT_ENA (BIT(18)) #define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S) @@ -792,137 +850,137 @@ extern "C" { #define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S 18 /** I2C_INT_STATUS_REG register - * Status of captured I2C communication events + * Status register of captured I2C communication events */ #define I2C_INT_STATUS_REG(i) (DR_REG_I2C_BASE(i) + 0x2c) /** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + * The masked interrupt status of I2C_RXFIFO_WM_INT. */ #define I2C_RXFIFO_WM_INT_ST (BIT(0)) #define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) #define I2C_RXFIFO_WM_INT_ST_V 0x00000001U #define I2C_RXFIFO_WM_INT_ST_S 0 /** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + * The masked interrupt status of I2C_TXFIFO_WM_INT. */ #define I2C_TXFIFO_WM_INT_ST (BIT(1)) #define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) #define I2C_TXFIFO_WM_INT_ST_V 0x00000001U #define I2C_TXFIFO_WM_INT_ST_S 1 /** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + * The masked interrupt status of I2C_RXFIFO_OVF_INT. */ #define I2C_RXFIFO_OVF_INT_ST (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) #define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U #define I2C_RXFIFO_OVF_INT_ST_S 2 /** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + * The masked interrupt status of I2C_END_DETECT_INT. */ #define I2C_END_DETECT_INT_ST (BIT(3)) #define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) #define I2C_END_DETECT_INT_ST_V 0x00000001U #define I2C_END_DETECT_INT_ST_S 3 /** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + * The masked interrupt status of I2C_BYTE_TRANS_DONE_INT. */ #define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) #define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) #define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U #define I2C_BYTE_TRANS_DONE_INT_ST_S 4 /** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + * The masked interrupt status of I2C_ARBITRATION_LOST_INT. */ #define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) #define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U #define I2C_ARBITRATION_LOST_INT_ST_S 5 /** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + * The masked interrupt status of I2C_MST_TXFIFO_UDF_INT. */ #define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) #define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) #define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U #define I2C_MST_TXFIFO_UDF_INT_ST_S 6 /** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + * The masked interrupt status of I2C_TRANS_COMPLETE_INT. */ #define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) #define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U #define I2C_TRANS_COMPLETE_INT_ST_S 7 /** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + * The masked interrupt status of I2C_TIME_OUT_INT. */ #define I2C_TIME_OUT_INT_ST (BIT(8)) #define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) #define I2C_TIME_OUT_INT_ST_V 0x00000001U #define I2C_TIME_OUT_INT_ST_S 8 /** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + * The masked interrupt status of I2C_TRANS_START_INT. */ #define I2C_TRANS_START_INT_ST (BIT(9)) #define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) #define I2C_TRANS_START_INT_ST_V 0x00000001U #define I2C_TRANS_START_INT_ST_S 9 /** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + * The masked interrupt status of I2C_NACK_INT. */ #define I2C_NACK_INT_ST (BIT(10)) #define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) #define I2C_NACK_INT_ST_V 0x00000001U #define I2C_NACK_INT_ST_S 10 /** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + * The masked interrupt status of I2C_TXFIFO_OVF_INT. */ #define I2C_TXFIFO_OVF_INT_ST (BIT(11)) #define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) #define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U #define I2C_TXFIFO_OVF_INT_ST_S 11 /** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + * The masked interrupt status of I2C_RXFIFO_UDF_INT. */ #define I2C_RXFIFO_UDF_INT_ST (BIT(12)) #define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) #define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U #define I2C_RXFIFO_UDF_INT_ST_S 12 /** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + * The masked interrupt status of I2C_SCL_ST_TO_INT. */ #define I2C_SCL_ST_TO_INT_ST (BIT(13)) #define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) #define I2C_SCL_ST_TO_INT_ST_V 0x00000001U #define I2C_SCL_ST_TO_INT_ST_S 13 /** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + * The masked interrupt status of I2C_SCL_MAIN_ST_TO_INT. */ #define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) #define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) #define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U #define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 /** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for I2C_DET_START_INT interrupt. + * The masked interrupt status of I2C_DET_START_INT. */ #define I2C_DET_START_INT_ST (BIT(15)) #define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) #define I2C_DET_START_INT_ST_V 0x00000001U #define I2C_DET_START_INT_ST_S 15 /** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + * The masked interrupt status of I2C_SLAVE_STRETCH_INT. */ #define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) #define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) #define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U #define I2C_SLAVE_STRETCH_INT_ST_S 16 /** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; - * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + * The masked interrupt status of I2C_GENERAL_CALL_INT. */ #define I2C_GENERAL_CALL_INT_ST (BIT(17)) #define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) #define I2C_GENERAL_CALL_INT_ST_V 0x00000001U #define I2C_GENERAL_CALL_INT_ST_S 17 /** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + * The masked interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT. */ #define I2C_SLAVE_ADDR_UNMATCH_INT_ST (BIT(18)) #define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S) @@ -930,12 +988,12 @@ extern "C" { #define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S 18 /** I2C_SDA_HOLD_REG register - * Configures the hold time after a negative SCL edge. + * Configures the hold time after a negative SCL edge */ #define I2C_SDA_HOLD_REG(i) (DR_REG_I2C_BASE(i) + 0x30) /** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure the time to hold the data after the negative - * edge of SCL, in I2C module clock cycles. + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: I2C_SCLK */ #define I2C_SDA_HOLD_TIME 0x000001FFU #define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) @@ -943,12 +1001,12 @@ extern "C" { #define I2C_SDA_HOLD_TIME_S 0 /** I2C_SDA_SAMPLE_REG register - * Configures the sample time after a positive SCL edge. + * Configures the sample time after a positive SCL edge */ #define I2C_SDA_SAMPLE_REG(i) (DR_REG_I2C_BASE(i) + 0x34) /** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure for how long SDA is sampled, in I2C module clock - * cycles. + * Configures the time for sampling SDA. + * Measurement unit: I2C_SCLK */ #define I2C_SDA_SAMPLE_TIME 0x000001FFU #define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) @@ -960,16 +1018,16 @@ extern "C" { */ #define I2C_SCL_HIGH_PERIOD_REG(i) (DR_REG_I2C_BASE(i) + 0x38) /** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure for how long SCL remains high in master mode, in - * I2C module clock cycles. + * Configures for how long SCL remains high in Master mode. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_HIGH_PERIOD 0x000001FFU #define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) #define I2C_SCL_HIGH_PERIOD_V 0x000001FFU #define I2C_SCL_HIGH_PERIOD_S 0 /** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; - * This register is used to configure for the SCL_FSM's waiting period for SCL high - * level in master mode, in I2C module clock cycles. + * Configures the SCL_FSM's waiting period for SCL high level in Master mode. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU #define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) @@ -980,10 +1038,10 @@ extern "C" { * Configures the delay between the SDA and SCL negative edge for a start condition */ #define I2C_SCL_START_HOLD_REG(i) (DR_REG_I2C_BASE(i) + 0x40) -/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the negative edge - * of SDA and the negative edge of SCL for a START condition, in I2C module clock - * cycles. +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_START_HOLD_TIME 0x000001FFU #define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) @@ -991,14 +1049,13 @@ extern "C" { #define I2C_SCL_START_HOLD_TIME_S 0 /** I2C_SCL_RSTART_SETUP_REG register - * Configures the delay between the positive - * edge of SCL and the negative edge of SDA + * Configures the delay between the positive edge of SCL and the negative edge of SDA */ #define I2C_SCL_RSTART_SETUP_REG(i) (DR_REG_I2C_BASE(i) + 0x44) -/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the positive - * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module - * clock cycles. +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU #define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) @@ -1006,13 +1063,12 @@ extern "C" { #define I2C_SCL_RSTART_SETUP_TIME_S 0 /** I2C_SCL_STOP_HOLD_REG register - * Configures the delay after the SCL clock - * edge for a stop condition + * Configures the delay after the SCL clock edge for a stop condition */ #define I2C_SCL_STOP_HOLD_REG(i) (DR_REG_I2C_BASE(i) + 0x48) -/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the delay after the STOP condition, - * in I2C module clock cycles. +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the delay after the STOP condition. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_STOP_HOLD_TIME 0x000001FFU #define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) @@ -1020,13 +1076,13 @@ extern "C" { #define I2C_SCL_STOP_HOLD_TIME_S 0 /** I2C_SCL_STOP_SETUP_REG register - * Configures the delay between the SDA and - * SCL positive edge for a stop condition + * Configures the delay between the SDA and SCL rising edge for a stop condition. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_STOP_SETUP_REG(i) (DR_REG_I2C_BASE(i) + 0x4c) -/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the positive edge - * of SCL and the positive edge of SDA, in I2C module clock cycles. +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_STOP_SETUP_TIME 0x000001FFU #define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) @@ -1038,95 +1094,70 @@ extern "C" { */ #define I2C_FILTER_CFG_REG(i) (DR_REG_I2C_BASE(i) + 0x50) /** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; - * When a pulse on the SCL input has smaller width than this register value - * in I2C module clock cycles, the I2C controller will ignore that pulse. + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_FILTER_THRES 0x0000000FU #define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) #define I2C_SCL_FILTER_THRES_V 0x0000000FU #define I2C_SCL_FILTER_THRES_S 0 /** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; - * When a pulse on the SDA input has smaller width than this register value - * in I2C module clock cycles, the I2C controller will ignore that pulse. + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: I2C_SCLK */ #define I2C_SDA_FILTER_THRES 0x0000000FU #define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) #define I2C_SDA_FILTER_THRES_V 0x0000000FU #define I2C_SDA_FILTER_THRES_S 4 -/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; - * This is the filter enable bit for SCL. +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 0; + * Configures whether to enable the filter function for SCL. + * 0: No effect + * 1: Enable */ #define I2C_SCL_FILTER_EN (BIT(8)) #define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) #define I2C_SCL_FILTER_EN_V 0x00000001U #define I2C_SCL_FILTER_EN_S 8 -/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; - * This is the filter enable bit for SDA. +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 0; + * Configures whether to enable the filter function for SDA. + * 0: No effect + * 1: Enable */ #define I2C_SDA_FILTER_EN (BIT(9)) #define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) #define I2C_SDA_FILTER_EN_V 0x00000001U #define I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register - * I2C CLK configuration register - */ -#define I2C_CLK_CONF_REG(i) (DR_REG_I2C_BASE(i) + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * the integral part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; - * the numerator of the fractional part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; - * the denominator of the fractional part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; - * The clock switch for i2c module - */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 - /** I2C_COMD0_REG register * I2C command register 0 */ #define I2C_COMD0_REG(i) (DR_REG_I2C_BASE(i) + 0x58) /** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 0. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. + * Configures command 0. + * It consists of three parts: + * op_code is the command + * 0: RSTART + * 1: WRITE + * 2: READ + * 3: STOP + * 4: END. * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + * " */ #define I2C_COMMAND0 0x00003FFFU #define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) #define I2C_COMMAND0_V 0x00003FFFU #define I2C_COMMAND0_S 0 /** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 0 is done in I2C Master mode, this bit changes to high - * level. + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND0_DONE (BIT(31)) #define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) @@ -1138,20 +1169,16 @@ extern "C" { */ #define I2C_COMD1_REG(i) (DR_REG_I2C_BASE(i) + 0x5c) /** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 1. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 1. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND1 0x00003FFFU #define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) #define I2C_COMMAND1_V 0x00003FFFU #define I2C_COMMAND1_S 0 /** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 1 is done in I2C Master mode, this bit changes to high - * level. + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND1_DONE (BIT(31)) #define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) @@ -1163,20 +1190,16 @@ extern "C" { */ #define I2C_COMD2_REG(i) (DR_REG_I2C_BASE(i) + 0x60) /** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 2. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 2. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND2 0x00003FFFU #define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) #define I2C_COMMAND2_V 0x00003FFFU #define I2C_COMMAND2_S 0 /** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 2 is done in I2C Master mode, this bit changes to high - * Level. + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND2_DONE (BIT(31)) #define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) @@ -1188,20 +1211,16 @@ extern "C" { */ #define I2C_COMD3_REG(i) (DR_REG_I2C_BASE(i) + 0x64) /** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 3. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 3. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND3 0x00003FFFU #define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) #define I2C_COMMAND3_V 0x00003FFFU #define I2C_COMMAND3_S 0 /** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 3 is done in I2C Master mode, this bit changes to high - * level. + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND3_DONE (BIT(31)) #define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) @@ -1213,20 +1232,16 @@ extern "C" { */ #define I2C_COMD4_REG(i) (DR_REG_I2C_BASE(i) + 0x68) /** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 4. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 4. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND4 0x00003FFFU #define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) #define I2C_COMMAND4_V 0x00003FFFU #define I2C_COMMAND4_S 0 /** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 4 is done in I2C Master mode, this bit changes to high - * level. + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND4_DONE (BIT(31)) #define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) @@ -1238,19 +1253,16 @@ extern "C" { */ #define I2C_COMD5_REG(i) (DR_REG_I2C_BASE(i) + 0x6c) /** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 5. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 5. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND5 0x00003FFFU #define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) #define I2C_COMMAND5_V 0x00003FFFU #define I2C_COMMAND5_S 0 /** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 5 is done in I2C Master mode, this bit changes to high level. + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND5_DONE (BIT(31)) #define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) @@ -1262,19 +1274,16 @@ extern "C" { */ #define I2C_COMD6_REG(i) (DR_REG_I2C_BASE(i) + 0x70) /** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 6. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 6. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND6 0x00003FFFU #define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) #define I2C_COMMAND6_V 0x00003FFFU #define I2C_COMMAND6_S 0 /** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 6 is done in I2C Master mode, this bit changes to high level. + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND6_DONE (BIT(31)) #define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) @@ -1286,19 +1295,16 @@ extern "C" { */ #define I2C_COMD7_REG(i) (DR_REG_I2C_BASE(i) + 0x74) /** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; - * This is the content of command 7. It consists of three parts: - * op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. - * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more - * Information. + * Configures command 7. See details in I2C_COMD0_REG [13:0]. */ #define I2C_COMMAND7 0x00003FFFU #define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) #define I2C_COMMAND7_V 0x00003FFFU #define I2C_COMMAND7_S 0 /** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; - * When command 7 is done in I2C Master mode, this bit changes to high level. + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND7_DONE (BIT(31)) #define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) @@ -1306,11 +1312,17 @@ extern "C" { #define I2C_COMMAND7_DONE_S 31 /** I2C_SCL_ST_TIME_OUT_REG register - * SCL status time out register + * SCL status timeout register */ #define I2C_SCL_ST_TIME_OUT_REG(i) (DR_REG_I2C_BASE(i) + 0x78) /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; - * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23, more than 1. + * \[ + * \text{Threshold} = 2^{\text{I2C_SCL_ST_TO_I2C} - 1} + * \] + * + * Measurement unit: I2C_SCLK */ #define I2C_SCL_ST_TO_I2C 0x0000001FU #define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) @@ -1318,12 +1330,13 @@ extern "C" { #define I2C_SCL_ST_TO_I2C_S 0 /** I2C_SCL_MAIN_ST_TIME_OUT_REG register - * SCL main status time out register + * SCL main status timeout register */ #define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (DR_REG_I2C_BASE(i) + 0x7c) /** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; - * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more - * than 23 + * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be + * no more than 23. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU #define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) @@ -1335,32 +1348,37 @@ extern "C" { */ #define I2C_SCL_SP_CONF_REG(i) (DR_REG_I2C_BASE(i) + 0x80) /** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; - * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses - * equals to reg_scl_rst_slv_num[4:0]. + * Configures whether or not to send out SCL pulses when I2C master is IDLE. The + * number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0]. */ #define I2C_SCL_RST_SLV_EN (BIT(0)) #define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) #define I2C_SCL_RST_SLV_EN_V 0x00000001U #define I2C_SCL_RST_SLV_EN_S 0 /** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. Valid when - * reg_scl_rst_slv_en is 1. + * Configure the pulses of SCL generated in I2C Master mode. + * Valid when I2C_SCL_RST_SLV_EN is 1. + * Measurement unit: I2C_SCLK */ #define I2C_SCL_RST_SLV_NUM 0x0000001FU #define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) #define I2C_SCL_RST_SLV_NUM_V 0x0000001FU #define I2C_SCL_RST_SLV_NUM_S 1 /** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; - * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power - * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + * Configures whether or not to power down the I2C output SCL line. + * 0: Not power down + * 1: Power down + * Valid only when I2C_SCL_FORCE_OUT is 1. */ #define I2C_SCL_PD_EN (BIT(6)) #define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) #define I2C_SCL_PD_EN_V 0x00000001U #define I2C_SCL_PD_EN_S 6 /** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; - * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power - * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + * Configures whether or not to power down the I2C output SDA line. + * 0: Not power down + * 1: Power down + * Valid only when I2C_SDA_FORCE_OUT is 1. */ #define I2C_SDA_PD_EN (BIT(7)) #define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) @@ -1368,41 +1386,51 @@ extern "C" { #define I2C_SDA_PD_EN_S 7 /** I2C_SCL_STRETCH_CONF_REG register - * Set SCL stretch of I2C slave + * SCL stretch setting register of I2C slave */ #define I2C_SCL_STRETCH_CONF_REG(i) (DR_REG_I2C_BASE(i) + 0x84) /** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; - * Configure the period of I2C slave stretching SCL line. + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: I2C_SCLK */ #define I2C_STRETCH_PROTECT_NUM 0x000003FFU #define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) #define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU #define I2C_STRETCH_PROTECT_NUM_S 0 /** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; - * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL - * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch - * event happens. The stretch cause can be seen in reg_stretch_cause. + * Configures whether to enable slave SCL stretch function. The SCL output line will + * be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The + * stretch cause can be seen in I2C_STRETCH_CAUSE. + * 0: Disable + * 1: Enable */ #define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) #define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) #define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U #define I2C_SLAVE_SCL_STRETCH_EN_S 10 /** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the I2C slave SCL stretch function. + * Configures whether or not to clear the I2C slave SCL stretch function. + * 0: No effect + * 1: Clear */ #define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) #define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) #define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U #define I2C_SLAVE_SCL_STRETCH_CLR_S 11 /** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; - * The enable bit for slave to control ACK level function. + * Configures whether to enable the function for slave to control ACK level. + * 0: Disable + * 1: Enable */ #define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) #define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) #define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U #define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 /** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables. + * Configures the ACK level when slave controlling ACK level function enables. + * 0: Low level + * 1: High level */ #define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) #define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) @@ -1410,11 +1438,11 @@ extern "C" { #define I2C_SLAVE_BYTE_ACK_LVL_S 13 /** I2C_DATE_REG register - * Version register + * Version control register */ #define I2C_DATE_REG(i) (DR_REG_I2C_BASE(i) + 0xf8) /** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050; - * This is the the version register. + * Version control register. */ #define I2C_DATE 0xFFFFFFFFU #define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) @@ -1426,7 +1454,7 @@ extern "C" { */ #define I2C_TXFIFO_START_ADDR_REG(i) (DR_REG_I2C_BASE(i) + 0x100) /** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; - * This is the I2C txfifo first address. + * Represents the I2C TX FIFO first address. */ #define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU #define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) @@ -1438,7 +1466,7 @@ extern "C" { */ #define I2C_RXFIFO_START_ADDR_REG(i) (DR_REG_I2C_BASE(i) + 0x180) /** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; - * This is the I2C rxfifo first address. + * Represents the I2C RX FIFO first address. */ #define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU #define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) diff --git a/components/soc/esp32h21/register/soc/i2c_struct.h b/components/soc/esp32h21/register/soc/i2c_struct.h index 75aa768513..62f8db4f25 100644 --- a/components/soc/esp32h21/register/soc/i2c_struct.h +++ b/components/soc/esp32h21/register/soc/i2c_struct.h @@ -12,14 +12,13 @@ extern "C" { /** Group: Timing registers */ /** Type of scl_low_period register - * Configures the low level width of the SCL - * Clock + * Configures the low level width of the SCL Clock */ typedef union { struct { /** scl_low_period : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure for how long SCL remains low in master mode, in - * I2C module clock cycles. + * Configures the low level width of the SCL Clock in Master mode. + * Measurement unit: I2C_SCLK */ uint32_t scl_low_period:9; uint32_t reserved_9:23; @@ -28,13 +27,13 @@ typedef union { } i2c_scl_low_period_reg_t; /** Type of sda_hold register - * Configures the hold time after a negative SCL edge. + * Configures the hold time after a negative SCL edge */ typedef union { struct { /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure the time to hold the data after the negative - * edge of SCL, in I2C module clock cycles. + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: I2C_SCLK */ uint32_t sda_hold_time:9; uint32_t reserved_9:23; @@ -43,13 +42,13 @@ typedef union { } i2c_sda_hold_reg_t; /** Type of sda_sample register - * Configures the sample time after a positive SCL edge. + * Configures the sample time after a positive SCL edge */ typedef union { struct { /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure for how long SDA is sampled, in I2C module clock - * cycles. + * Configures the time for sampling SDA. + * Measurement unit: I2C_SCLK */ uint32_t sda_sample_time:9; uint32_t reserved_9:23; @@ -63,13 +62,13 @@ typedef union { typedef union { struct { /** scl_high_period : R/W; bitpos: [8:0]; default: 0; - * This register is used to configure for how long SCL remains high in master mode, in - * I2C module clock cycles. + * Configures for how long SCL remains high in Master mode. + * Measurement unit: I2C_SCLK */ uint32_t scl_high_period:9; /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; - * This register is used to configure for the SCL_FSM's waiting period for SCL high - * level in master mode, in I2C module clock cycles. + * Configures the SCL_FSM's waiting period for SCL high level in Master mode. + * Measurement unit: I2C_SCLK */ uint32_t scl_wait_high_period:7; uint32_t reserved_16:16; @@ -82,10 +81,10 @@ typedef union { */ typedef union { struct { - /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the negative edge - * of SDA and the negative edge of SCL for a START condition, in I2C module clock - * cycles. + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: I2C_SCLK */ uint32_t scl_start_hold_time:9; uint32_t reserved_9:23; @@ -94,15 +93,14 @@ typedef union { } i2c_scl_start_hold_reg_t; /** Type of scl_rstart_setup register - * Configures the delay between the positive - * edge of SCL and the negative edge of SDA + * Configures the delay between the positive edge of SCL and the negative edge of SDA */ typedef union { struct { - /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the positive - * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module - * clock cycles. + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: I2C_SCLK */ uint32_t scl_rstart_setup_time:9; uint32_t reserved_9:23; @@ -111,14 +109,13 @@ typedef union { } i2c_scl_rstart_setup_reg_t; /** Type of scl_stop_hold register - * Configures the delay after the SCL clock - * edge for a stop condition + * Configures the delay after the SCL clock edge for a stop condition */ typedef union { struct { - /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the delay after the STOP condition, - * in I2C module clock cycles. + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the delay after the STOP condition. + * Measurement unit: I2C_SCLK */ uint32_t scl_stop_hold_time:9; uint32_t reserved_9:23; @@ -127,14 +124,14 @@ typedef union { } i2c_scl_stop_hold_reg_t; /** Type of scl_stop_setup register - * Configures the delay between the SDA and - * SCL positive edge for a stop condition + * Configures the delay between the SDA and SCL rising edge for a stop condition. + * Measurement unit: I2C_SCLK */ typedef union { struct { - /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; - * This register is used to configure the time between the positive edge - * of SCL and the positive edge of SDA, in I2C module clock cycles. + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: I2C_SCLK */ uint32_t scl_stop_setup_time:9; uint32_t reserved_9:23; @@ -143,12 +140,18 @@ typedef union { } i2c_scl_stop_setup_reg_t; /** Type of scl_st_time_out register - * SCL status time out register + * SCL status timeout register */ typedef union { struct { /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; - * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23, more than 1. + * \[ + * \text{Threshold} = 2^{\text{I2C_SCL_ST_TO_I2C} - 1} + * \] + * + * Measurement unit: I2C_SCLK */ uint32_t scl_st_to_i2c:5; uint32_t reserved_5:27; @@ -157,13 +160,14 @@ typedef union { } i2c_scl_st_time_out_reg_t; /** Type of scl_main_st_time_out register - * SCL main status time out register + * SCL main status timeout register */ typedef union { struct { /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; - * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more - * than 23 + * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be + * no more than 23. + * Measurement unit: I2C_SCLK */ uint32_t scl_main_st_to_i2c:5; uint32_t reserved_5:27; @@ -174,78 +178,98 @@ typedef union { /** Group: Configuration registers */ /** Type of ctr register - * Transmission setting + * Transmission setting register */ typedef union { struct { /** sda_force_out : R/W; bitpos: [0]; default: 0; - * 1: direct output, 0: open drain output. + * Configures the SDA output mode. + * 0: Open drain output + * 1: Direct output */ uint32_t sda_force_out:1; /** scl_force_out : R/W; bitpos: [1]; default: 0; - * 1: direct output, 0: open drain output. + * Configures the SCL output mode. + * 0: Open drain output + * 1: Direct output */ uint32_t scl_force_out:1; /** sample_scl_level : R/W; bitpos: [2]; default: 0; - * This register is used to select the sample mode. - * 1: sample SDA data on the SCL low level. - * 0: sample SDA data on the SCL high level. + * Configures the sample mode for SDA. + * 0: Sample SDA data on the SCL high level + * 1: Sample SDA data on the SCL low level */ uint32_t sample_scl_level:1; - /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; - * This register is used to configure the ACK value that need to sent by master when - * the rx_fifo_cnt has reached the threshold. + /** rx_full_ack_level : R/W; bitpos: [3]; default: 0; + * Configures the ACK value that needs to be sent by master when rx_fifo_cnt has + * reached the threshold. */ uint32_t rx_full_ack_level:1; /** ms_mode : R/W; bitpos: [4]; default: 0; - * Set this bit to configure the module as an I2C Master. Clear this bit to configure - * the - * module as an I2C Slave. + * Configures the module as an I2C Master or Slave. + * 0: Slave + * 1: Master */ uint32_t ms_mode:1; /** trans_start : WT; bitpos: [5]; default: 0; - * Set this bit to start sending the data in txfifo. + * Configures whether the slave starts sending the data in TX FIFO. + * 0: No effect + * 1: Start */ uint32_t trans_start:1; /** tx_lsb_first : R/W; bitpos: [6]; default: 0; - * This bit is used to control the sending mode for data needing to be sent. - * 1: send data from the least significant bit, - * 0: send data from the most significant bit. + * Configures whether or not to control the sending order for data needing to be sent. + * 0: Send data from the most significant bit + * 1: Send data from the least significant bit */ uint32_t tx_lsb_first:1; /** rx_lsb_first : R/W; bitpos: [7]; default: 0; - * This bit is used to control the storage mode for received data. - * 1: receive data from the least significant bit, - * 0: receive data from the most significant bit. + * Configures whether or not to control the storage order for received data. + * 0: Receive data from the most significant bit + * 1: Receive data from the least significant bit */ uint32_t rx_lsb_first:1; /** clk_en : R/W; bitpos: [8]; default: 0; - * Reserved + * Configures whether to gate clock signal for registers. + * 0: Support clock only when registers are read or written to by software + * 1: Force clock on for registers */ uint32_t clk_en:1; - /** arbitration_en : R/W; bitpos: [9]; default: 1; - * This is the enable bit for arbitration_lost. + /** arbitration_en : R/W; bitpos: [9]; default: 0; + * Configures whether to enable I2C bus arbitration detection. + * 0: No effect + * 1: Enable */ uint32_t arbitration_en:1; /** fsm_rst : WT; bitpos: [10]; default: 0; - * This register is used to reset the scl FMS. + * Configures whether to reset the SCL_FSM. + * 0: No effect + * 1: Reset */ uint32_t fsm_rst:1; /** conf_upgate : WT; bitpos: [11]; default: 0; - * synchronization bit + * Configures the bit for synchronization. + * 0: No effect + * 1: Synchronize */ uint32_t conf_upgate:1; /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; - * This is the enable bit for slave to send data automatically + * Configures whether to enable slave to send data automatically + * 0: Disable + * 1: Enable */ uint32_t slv_tx_auto_start_en:1; /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; - * This is the enable bit to check if the r/w bit of 10bit addressing consists with - * I2C protocol + * Configures whether to check if the $R/\overline W$ bit of 10-bit addressing + * consists with I2C protocol. + * 0: Not check + * 1: Check */ uint32_t addr_10bit_rw_check_en:1; /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; - * This is the enable bit to support the 7bit general call function. + * Configures whether to support the 7-bit general call function. + * 0: Not support + * 1: Support */ uint32_t addr_broadcasting_en:1; uint32_t reserved_15:17; @@ -254,17 +278,20 @@ typedef union { } i2c_ctr_reg_t; /** Type of to register - * Setting time out control for receiving data. + * Timeout control register for receiving data */ typedef union { struct { /** time_out_value : R/W; bitpos: [4:0]; default: 16; - * This register is used to configure the timeout for receiving a data bit in APB - * clock cycles. + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2\^{}(reg_time_out_value). + * Measurement unit: I2C_SCLK */ uint32_t time_out_value:5; /** time_out_en : R/W; bitpos: [5]; default: 0; - * This is the enable bit for time out control. + * Configures whether to enable timeout control. + * 0: No effect + * 1: Enable */ uint32_t time_out_en:1; uint32_t reserved_6:26; @@ -273,17 +300,19 @@ typedef union { } i2c_to_reg_t; /** Type of slave_addr register - * Local slave address setting + * Local slave address setting register */ typedef union { struct { /** slave_addr : R/W; bitpos: [14:0]; default: 0; - * When configured as an I2C Slave, this field is used to configure the slave address. + * Configures the slave address of the I2C slave. */ uint32_t slave_addr:15; uint32_t reserved_15:16; /** addr_10bit_en : R/W; bitpos: [31]; default: 0; - * This field is used to enable the slave 10-bit addressing mode in master mode. + * Configures whether to enable the slave 10-bit addressing mode in Master mode. + * 0: No effect + * 1: Enable */ uint32_t addr_10bit_en:1; }; @@ -291,42 +320,52 @@ typedef union { } i2c_slave_addr_reg_t; /** Type of fifo_conf register - * FIFO configuration register. + * FIFO configuration register */ typedef union { struct { - /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; - * The water mark threshold of rx FIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than - * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 0; + * Configures the watermark threshold of RX FIFO in non-FIFO access mode. When + * I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], + * the I2C_RXFIFO_WM_INT_RAW bit will be valid. */ uint32_t rxfifo_wm_thrhd:5; - /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; - * The water mark threshold of tx FIFO in nonfifo access mode. When - * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than - * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 0; + * Configures the watermark threshold of TX FIFO in non-FIFO access mode. When + * I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0], + * the I2C_TXFIFO_WM_INT_RAW bit will be valid. */ uint32_t txfifo_wm_thrhd:5; /** nonfifo_en : R/W; bitpos: [10]; default: 0; - * Set this bit to enable APB nonfifo access. + * Configures whether to enable APB non-FIFO access. */ uint32_t nonfifo_en:1; /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; - * When this bit is set to 1, the byte received after the I2C address byte represents - * the offset address in the I2C Slave RAM. + * Configures the slave to enable dual address mode. When this mode is enabled, the + * byte received after the I2C address byte represents the offset address in the I2C + * Slave RAM. + * 0: Disable + * 1: Enable */ uint32_t fifo_addr_cfg_en:1; /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; - * Set this bit to reset rx-fifo. + * Configures whether or not to reset RX FIFO. + * 0: No effect + * 1: Reset */ uint32_t rx_fifo_rst:1; /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; - * Set this bit to reset tx-fifo. + * Configures whether or not to reset TX FIFO. + * 0: No effect + * 1: Reset */ uint32_t tx_fifo_rst:1; - /** fifo_prt_en : R/W; bitpos: [14]; default: 1; - * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls - * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + /** fifo_prt_en : R/W; bitpos: [14]; default: 0; + * Configures whether to enable FIFO pointer in non-FIFO access mode. This bit + * controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty + * interrupts. + * 0: No effect + * 1: Enable */ uint32_t fifo_prt_en:1; uint32_t reserved_15:17; @@ -340,21 +379,29 @@ typedef union { typedef union { struct { /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; - * When a pulse on the SCL input has smaller width than this register value - * in I2C module clock cycles, the I2C controller will ignore that pulse. + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: I2C_SCLK */ uint32_t scl_filter_thres:4; /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; - * When a pulse on the SDA input has smaller width than this register value - * in I2C module clock cycles, the I2C controller will ignore that pulse. + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: I2C_SCLK */ uint32_t sda_filter_thres:4; - /** scl_filter_en : R/W; bitpos: [8]; default: 1; - * This is the filter enable bit for SCL. + /** scl_filter_en : R/W; bitpos: [8]; default: 0; + * Configures whether to enable the filter function for SCL. + * 0: No effect + * 1: Enable */ uint32_t scl_filter_en:1; - /** sda_filter_en : R/W; bitpos: [9]; default: 1; - * This is the filter enable bit for SDA. + /** sda_filter_en : R/W; bitpos: [9]; default: 0; + * Configures whether to enable the filter function for SDA. + * 0: No effect + * 1: Enable */ uint32_t sda_filter_en:1; uint32_t reserved_10:22; @@ -362,59 +409,34 @@ typedef union { uint32_t val; } i2c_filter_cfg_reg_t; -/** Type of clk_conf register - * I2C CLK configuration register - */ -typedef union { - struct { - /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; - * the integral part of the fractional divisor for i2c module - */ - uint32_t sclk_div_num:8; - /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; - * the numerator of the fractional part of the fractional divisor for i2c module - */ - uint32_t sclk_div_a:6; - /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; - * the denominator of the fractional part of the fractional divisor for i2c module - */ - uint32_t sclk_div_b:6; - /** sclk_sel : R/W; bitpos: [20]; default: 0; - * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - */ - uint32_t sclk_sel:1; - /** sclk_active : R/W; bitpos: [21]; default: 1; - * The clock switch for i2c module - */ - uint32_t sclk_active:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} i2c_clk_conf_reg_t; - /** Type of scl_sp_conf register * Power configuration register */ typedef union { struct { /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; - * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses - * equals to reg_scl_rst_slv_num[4:0]. + * Configures whether or not to send out SCL pulses when I2C master is IDLE. The + * number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0]. */ uint32_t scl_rst_slv_en:1; /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. Valid when - * reg_scl_rst_slv_en is 1. + * Configure the pulses of SCL generated in I2C Master mode. + * Valid when I2C_SCL_RST_SLV_EN is 1. + * Measurement unit: I2C_SCLK */ uint32_t scl_rst_slv_num:5; /** scl_pd_en : R/W; bitpos: [6]; default: 0; - * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power - * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + * Configures whether or not to power down the I2C output SCL line. + * 0: Not power down + * 1: Power down + * Valid only when I2C_SCL_FORCE_OUT is 1. */ uint32_t scl_pd_en:1; /** sda_pd_en : R/W; bitpos: [7]; default: 0; - * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power - * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + * Configures whether or not to power down the I2C output SDA line. + * 0: Not power down + * 1: Power down + * Valid only when I2C_SDA_FORCE_OUT is 1. */ uint32_t sda_pd_en:1; uint32_t reserved_8:24; @@ -423,30 +445,40 @@ typedef union { } i2c_scl_sp_conf_reg_t; /** Type of scl_stretch_conf register - * Set SCL stretch of I2C slave + * SCL stretch setting register of I2C slave */ typedef union { struct { /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; - * Configure the period of I2C slave stretching SCL line. + * Configures the time period to release the SCL line from stretching to avoid timing + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: I2C_SCLK */ uint32_t stretch_protect_num:10; /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; - * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL - * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch - * event happens. The stretch cause can be seen in reg_stretch_cause. + * Configures whether to enable slave SCL stretch function. The SCL output line will + * be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The + * stretch cause can be seen in I2C_STRETCH_CAUSE. + * 0: Disable + * 1: Enable */ uint32_t slave_scl_stretch_en:1; /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear the I2C slave SCL stretch function. + * Configures whether or not to clear the I2C slave SCL stretch function. + * 0: No effect + * 1: Clear */ uint32_t slave_scl_stretch_clr:1; /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; - * The enable bit for slave to control ACK level function. + * Configures whether to enable the function for slave to control ACK level. + * 0: Disable + * 1: Enable */ uint32_t slave_byte_ack_ctl_en:1; /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables. + * Configures the ACK level when slave controlling ACK level function enables. + * 0: Low level + * 1: High level */ uint32_t slave_byte_ack_lvl:1; uint32_t reserved_14:18; @@ -457,58 +489,81 @@ typedef union { /** Group: Status registers */ /** Type of sr register - * Describe I2C work status. + * I2C working status register */ typedef union { struct { /** resp_rec : RO; bitpos: [0]; default: 0; - * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + * Represents the received ACK value in Master mode or Slave mode. + * 0: ACK + * 1: NACK */ uint32_t resp_rec:1; /** slave_rw : RO; bitpos: [1]; default: 0; - * When in slave mode, 1: master reads from slave, 0: master writes to slave. + * Represents the transfer direction in Slave mode. + * 0: Master writes to slave + * 1: Master reads from slave */ uint32_t slave_rw:1; uint32_t reserved_2:1; /** arb_lost : RO; bitpos: [3]; default: 0; - * When the I2C controller loses control of SCL line, this register changes to 1. + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * 1: Arbitration lost */ uint32_t arb_lost:1; /** bus_busy : RO; bitpos: [4]; default: 0; - * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + * Represents the I2C bus state. + * 0: The I2C bus is in idle state + * 1: The I2C bus is busy transferring data */ uint32_t bus_busy:1; /** slave_addressed : RO; bitpos: [5]; default: 0; - * When configured as an I2C Slave, and the address sent by the master is - * equal to the address of the slave, then this bit will be of high level. + * Represents whether the address sent by the master is equal to the address of the + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * 1: Equal */ uint32_t slave_addressed:1; uint32_t reserved_6:2; /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; - * This field represents the amount of data needed to be sent. + * Represents the number of data bytes received in RAM. */ uint32_t rxfifo_cnt:6; - /** stretch_cause : RO; bitpos: [15:14]; default: 3; - * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the - * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty - * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + /** stretch_cause : RO; bitpos: [15:14]; default: 0; + * Represents the cause of SCL clocking stretching in Slave mode. + * 0: Stretching SCL low when the master starts to read data. + * 1: Stretching SCL low when I2C TX FIFO is empty in Slave mode. + * 2: Stretching SCL low when I2C RX FIFO is full in Slave mode. */ uint32_t stretch_cause:2; uint32_t reserved_16:2; /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; - * This field stores the amount of received data in RAM. + * Represents the number of data bytes to be sent. */ uint32_t txfifo_cnt:6; /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; - * This field indicates the states of the I2C module state machine. - * 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: - * Wait ACK + * Represents the states of the I2C module state machine. + * 0: Idle + * 1: Address shift + * 2: ACK address + * 3: Rx data + * 4: Tx data + * 5: Send ACK + * 6: Wait ACK */ uint32_t scl_main_state_last:3; uint32_t reserved_27:1; /** scl_state_last : RO; bitpos: [30:28]; default: 0; - * This field indicates the states of the state machine used to produce SCL. - * 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + * Represents the states of the state machine used to produce SCL. + * 0: Idle + * 1: Start + * 2: Negative edge + * 3: Low + * 4: Positive edge + * 5: High + * 6: Stop */ uint32_t scl_state_last:3; uint32_t reserved_31:1; @@ -517,29 +572,30 @@ typedef union { } i2c_sr_reg_t; /** Type of fifo_st register - * FIFO status register. + * FIFO status register */ typedef union { struct { /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; - * This is the offset address of the APB reading from rxfifo + * Represents the offset address of the APB reading from RX FIFO. */ uint32_t rxfifo_raddr:5; /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; - * This is the offset address of i2c module receiving data and writing to rxfifo. + * Represents the offset address of i2c module receiving data and writing to RX FIFO. */ uint32_t rxfifo_waddr:5; /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; - * This is the offset address of i2c module reading from txfifo. + * Represents the offset address of I2C module reading from TX FIFO. */ uint32_t txfifo_raddr:5; /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; - * This is the offset address of APB bus writing to txfifo. + * Represents the offset address of APB bus writing to TX FIFO. */ uint32_t txfifo_waddr:5; uint32_t reserved_20:2; /** slave_rw_point : RO; bitpos: [29:22]; default: 0; - * The received data in I2C slave mode. + * Represents the offset address in the I2C Slave RAM addressed by I2C Master when in + * I2C Slave mode. */ uint32_t slave_rw_point:8; uint32_t reserved_30:2; @@ -548,12 +604,12 @@ typedef union { } i2c_fifo_st_reg_t; /** Type of data register - * Rx FIFO read data. + * Rx FIFO read data */ typedef union { struct { - /** fifo_rdata : HRO; bitpos: [7:0]; default: 0; - * The value of rx FIFO read data. + /** fifo_rdata : RO; bitpos: [7:0]; default: 0; + * Represents the value of RX FIFO read data. */ uint32_t fifo_rdata:8; uint32_t reserved_8:24; @@ -564,84 +620,84 @@ typedef union { /** Group: Interrupt registers */ /** Type of int_raw register - * Raw interrupt status + * Raw interrupt status register */ typedef union { struct { /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + * The raw interrupt status of I2C_RXFIFO_WM_INT. */ uint32_t rxfifo_wm_int_raw:1; - /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of I2C_TXFIFO_WM_INT. */ uint32_t txfifo_wm_int_raw:1; /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + * The raw interrupt status of I2C_RXFIFO_OVF_INT. */ uint32_t rxfifo_ovf_int_raw:1; /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + * The raw interrupt status of I2C_END_DETECT_INT. */ uint32_t end_detect_int_raw:1; /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + * The raw interrupt status of I2C_BYTE_TRANS_DONE_INT. */ uint32_t byte_trans_done_int_raw:1; /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + * The raw interrupt status of I2C_ARBITRATION_LOST_INT. */ uint32_t arbitration_lost_int_raw:1; /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + * The raw interrupt status of I2C_MST_TXFIFO_UDF_INT. */ uint32_t mst_txfifo_udf_int_raw:1; /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT. */ uint32_t trans_complete_int_raw:1; /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + * The raw interrupt status of I2C_TIME_OUT_INT. */ uint32_t time_out_int_raw:1; /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + * The raw interrupt status of I2C_TRANS_START_INT. */ uint32_t trans_start_int_raw:1; /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + * The raw interrupt status of I2C_NACK_INT. */ uint32_t nack_int_raw:1; /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + * The raw interrupt status of I2C_TXFIFO_OVF_INT. */ uint32_t txfifo_ovf_int_raw:1; /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + * The raw interrupt status of I2C_RXFIFO_UDF_INT. */ uint32_t rxfifo_udf_int_raw:1; /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + * The raw interrupt status of I2C_SCL_ST_TO_INT. */ uint32_t scl_st_to_int_raw:1; /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT. */ uint32_t scl_main_st_to_int_raw:1; /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt bit for I2C_DET_START_INT interrupt. + * The raw interrupt status of I2C_DET_START_INT. */ uint32_t det_start_int_raw:1; /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + * The raw interrupt status of I2C_SLAVE_STRETCH_INT. */ uint32_t slave_stretch_int_raw:1; /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; - * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + * The raw interrupt status of I2C_GENERAL_CALL_INT. */ uint32_t general_call_int_raw:1; /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0; - * The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + * The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT. */ uint32_t slave_addr_unmatch_int_raw:1; uint32_t reserved_19:13; @@ -650,84 +706,84 @@ typedef union { } i2c_int_raw_reg_t; /** Type of int_clr register - * Interrupt clear bits + * Interrupt clear register */ typedef union { struct { /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + * Write 1 to clear I2C_RXFIFO_WM_INT. */ uint32_t rxfifo_wm_int_clr:1; /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + * Write 1 to clear I2C_TXFIFO_WM_INT. */ uint32_t txfifo_wm_int_clr:1; /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + * Write 1 to clear I2C_RXFIFO_OVF_INT. */ uint32_t rxfifo_ovf_int_clr:1; /** end_detect_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. + * Write 1 to clear I2C_END_DETECT_INT. */ uint32_t end_detect_int_clr:1; /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. + * Write 1 to clear I2C_BYTE_TRANS_DONE_INT. */ uint32_t byte_trans_done_int_clr:1; /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; - * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + * Write 1 to clear I2C_ARBITRATION_LOST_INT. */ uint32_t arbitration_lost_int_clr:1; /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; - * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to clear I2C_MST_TXFIFO_UDF_INT. */ uint32_t mst_txfifo_udf_int_clr:1; /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; - * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to clear I2C_TRANS_COMPLETE_INT. */ uint32_t trans_complete_int_clr:1; /** time_out_int_clr : WT; bitpos: [8]; default: 0; - * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + * Write 1 to clear I2C_TIME_OUT_INT. */ uint32_t time_out_int_clr:1; /** trans_start_int_clr : WT; bitpos: [9]; default: 0; - * Set this bit to clear the I2C_TRANS_START_INT interrupt. + * Write 1 to clear I2C_TRANS_START_INT. */ uint32_t trans_start_int_clr:1; /** nack_int_clr : WT; bitpos: [10]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to clear I2C_NACK_INT. */ uint32_t nack_int_clr:1; /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; - * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + * Write 1 to clear I2C_TXFIFO_OVF_INT. */ uint32_t txfifo_ovf_int_clr:1; /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; - * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + * Write 1 to clear I2C_RXFIFO_UDF_INT. */ uint32_t rxfifo_udf_int_clr:1; /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; - * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + * Write 1 to clear I2C_SCL_ST_TO_INT. */ uint32_t scl_st_to_int_clr:1; /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; - * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT. */ uint32_t scl_main_st_to_int_clr:1; /** det_start_int_clr : WT; bitpos: [15]; default: 0; - * Set this bit to clear I2C_DET_START_INT interrupt. + * Write 1 to clear I2C_DET_START_INT. */ uint32_t det_start_int_clr:1; /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to clear I2C_SLAVE_STRETCH_INT. */ uint32_t slave_stretch_int_clr:1; /** general_call_int_clr : WT; bitpos: [17]; default: 0; - * Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + * Write 1 to clear I2C_GENERAL_CALL_INT. */ uint32_t general_call_int_clr:1; /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0; - * Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + * Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT. */ uint32_t slave_addr_unmatch_int_clr:1; uint32_t reserved_19:13; @@ -736,84 +792,84 @@ typedef union { } i2c_int_clr_reg_t; /** Type of int_ena register - * Interrupt enable bits + * Interrupt enable register */ typedef union { struct { /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + * Write 1 to enable I2C_RXFIFO_WM_INT. */ uint32_t rxfifo_wm_int_ena:1; /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + * Write 1 to enable I2C_TXFIFO_WM_INT. */ uint32_t txfifo_wm_int_ena:1; /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + * Write 1 to enable I2C_RXFIFO_OVF_INT. */ uint32_t rxfifo_ovf_int_ena:1; /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + * Write 1 to enable I2C_END_DETECT_INT. */ uint32_t end_detect_int_ena:1; /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + * Write 1 to enable I2C_BYTE_TRANS_DONE_INT. */ uint32_t byte_trans_done_int_ena:1; /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + * Write 1 to enable I2C_ARBITRATION_LOST_INT. */ uint32_t arbitration_lost_int_ena:1; /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to enable I2C_MST_TXFIFO_UDF_INT. */ uint32_t mst_txfifo_udf_int_ena:1; /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + * Write 1 to enable I2C_TRANS_COMPLETE_INT. */ uint32_t trans_complete_int_ena:1; /** time_out_int_ena : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + * Write 1 to enable I2C_TIME_OUT_INT. */ uint32_t time_out_int_ena:1; /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + * Write 1 to enable I2C_TRANS_START_INT. */ uint32_t trans_start_int_ena:1; /** nack_int_ena : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to enable I2C_NACK_INT. */ uint32_t nack_int_ena:1; /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + * Write 1 to enable I2C_TXFIFO_OVF_INT. */ uint32_t txfifo_ovf_int_ena:1; /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + * Write 1 to enable I2C_RXFIFO_UDF_INT. */ uint32_t rxfifo_udf_int_ena:1; /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + * Write 1 to enable I2C_SCL_ST_TO_INT. */ uint32_t scl_st_to_int_ena:1; /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + * Write 1 to enable I2C_SCL_MAIN_ST_TO_INT. */ uint32_t scl_main_st_to_int_ena:1; /** det_start_int_ena : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for I2C_DET_START_INT interrupt. + * Write 1 to enable I2C_DET_START_INT. */ uint32_t det_start_int_ena:1; /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + * Write 1 to enable I2C_SLAVE_STRETCH_INT. */ uint32_t slave_stretch_int_ena:1; /** general_call_int_ena : R/W; bitpos: [17]; default: 0; - * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + * Write 1 to enable I2C_GENERAL_CALL_INT. */ uint32_t general_call_int_ena:1; /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0; - * The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + * Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT. */ uint32_t slave_addr_unmatch_int_ena:1; uint32_t reserved_19:13; @@ -822,84 +878,84 @@ typedef union { } i2c_int_ena_reg_t; /** Type of int_status register - * Status of captured I2C communication events + * Status register of captured I2C communication events */ typedef union { struct { /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + * The masked interrupt status of I2C_RXFIFO_WM_INT. */ uint32_t rxfifo_wm_int_st:1; /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + * The masked interrupt status of I2C_TXFIFO_WM_INT. */ uint32_t txfifo_wm_int_st:1; /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + * The masked interrupt status of I2C_RXFIFO_OVF_INT. */ uint32_t rxfifo_ovf_int_st:1; /** end_detect_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + * The masked interrupt status of I2C_END_DETECT_INT. */ uint32_t end_detect_int_st:1; /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + * The masked interrupt status of I2C_BYTE_TRANS_DONE_INT. */ uint32_t byte_trans_done_int_st:1; /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + * The masked interrupt status of I2C_ARBITRATION_LOST_INT. */ uint32_t arbitration_lost_int_st:1; /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + * The masked interrupt status of I2C_MST_TXFIFO_UDF_INT. */ uint32_t mst_txfifo_udf_int_st:1; /** trans_complete_int_st : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + * The masked interrupt status of I2C_TRANS_COMPLETE_INT. */ uint32_t trans_complete_int_st:1; /** time_out_int_st : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + * The masked interrupt status of I2C_TIME_OUT_INT. */ uint32_t time_out_int_st:1; /** trans_start_int_st : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + * The masked interrupt status of I2C_TRANS_START_INT. */ uint32_t trans_start_int_st:1; /** nack_int_st : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + * The masked interrupt status of I2C_NACK_INT. */ uint32_t nack_int_st:1; /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + * The masked interrupt status of I2C_TXFIFO_OVF_INT. */ uint32_t txfifo_ovf_int_st:1; /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + * The masked interrupt status of I2C_RXFIFO_UDF_INT. */ uint32_t rxfifo_udf_int_st:1; /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + * The masked interrupt status of I2C_SCL_ST_TO_INT. */ uint32_t scl_st_to_int_st:1; /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + * The masked interrupt status of I2C_SCL_MAIN_ST_TO_INT. */ uint32_t scl_main_st_to_int_st:1; /** det_start_int_st : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for I2C_DET_START_INT interrupt. + * The masked interrupt status of I2C_DET_START_INT. */ uint32_t det_start_int_st:1; /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + * The masked interrupt status of I2C_SLAVE_STRETCH_INT. */ uint32_t slave_stretch_int_st:1; /** general_call_int_st : RO; bitpos: [17]; default: 0; - * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + * The masked interrupt status of I2C_GENERAL_CALL_INT. */ uint32_t general_call_int_st:1; /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + * The masked interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT. */ uint32_t slave_addr_unmatch_int_st:1; uint32_t reserved_19:13; @@ -915,24 +971,24 @@ typedef union { typedef union { struct { /** command0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. It consists of three parts: - * op_code is the command, - * 0: RSTART, - * 1: WRITE, - * 2: READ, - * 3: STOP, + * Configures command 0. + * It consists of three parts: + * op_code is the command + * 0: RSTART + * 1: WRITE + * 2: READ + * 3: STOP * 4: END. - * * Byte_num represents the number of bytes that need to be sent or received. - * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure for more information. + * ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + * " */ uint32_t command:14; uint32_t reserved_14:17; /** command_done : R/W/SS; bitpos: [31]; default: 0; * Represents whether command 0 is done in I2C Master mode. * 0: Not done - * * 1: Done */ uint32_t command_done:1; @@ -942,12 +998,12 @@ typedef union { /** Group: Version register */ /** Type of date register - * Version register + * Version control register */ typedef union { struct { /** date : R/W; bitpos: [31:0]; default: 35656050; - * This is the the version register. + * Version control register. */ uint32_t date:32; }; @@ -962,7 +1018,7 @@ typedef union { typedef union { struct { /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * This is the I2C txfifo first address. + * Represents the I2C TX FIFO first address. */ uint32_t txfifo_start_addr:32; }; @@ -975,7 +1031,7 @@ typedef union { typedef union { struct { /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; - * This is the I2C rxfifo first address. + * Represents the I2C RX FIFO first address. */ uint32_t rxfifo_start_addr:32; }; @@ -1005,7 +1061,7 @@ typedef struct { volatile i2c_scl_stop_hold_reg_t scl_stop_hold; volatile i2c_scl_stop_setup_reg_t scl_stop_setup; volatile i2c_filter_cfg_reg_t filter_cfg; - volatile i2c_clk_conf_reg_t clk_conf; + uint32_t reserved_054; volatile i2c_comd_reg_t command[8]; volatile i2c_scl_st_time_out_reg_t scl_st_time_out; volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;