diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml
index b884ad3ffb..216be7f9ee 100644
--- a/.gitlab/ci/target-test.yml
+++ b/.gitlab/ci/target-test.yml
@@ -817,7 +817,7 @@ UT_046:
 
 UT_047:
   extends: .unit_test_esp32s2_template
-  parallel: 6
+  parallel: 13
   tags:
     - ESP32S2_IDF
     - UT_T1_1
@@ -880,7 +880,7 @@ UT_C3_SDSPI:
 
 UT_S3:
   extends: .unit_test_esp32s3_template
-  parallel: 32
+  parallel: 44
   tags:
     - ESP32S3_IDF
     - UT_T1_1
diff --git a/components/bt/esp_ble_mesh/mesh_core/adv.c b/components/bt/esp_ble_mesh/mesh_core/adv.c
index 1d019feaec..b8bcf38966 100644
--- a/components/bt/esp_ble_mesh/mesh_core/adv.c
+++ b/components/bt/esp_ble_mesh/mesh_core/adv.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -110,7 +110,7 @@ static void bt_mesh_ble_adv_deinit(void);
 struct bt_mesh_adv_task {
     TaskHandle_t handle;
 #if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \
-     CONFIG_SPIRAM_CACHE_WORKAROUND && \
+     (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && \
      CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY)
     StaticTask_t *task;
     StackType_t *stack;
@@ -639,7 +639,7 @@ void bt_mesh_adv_init(void)
 #endif /* defined(CONFIG_BLE_MESH_RELAY_ADV_BUF) */
 
 #if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \
-     CONFIG_SPIRAM_CACHE_WORKAROUND && \
+    (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && \
      CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY)
     adv_task.task = heap_caps_calloc(1, sizeof(StaticTask_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
     __ASSERT(adv_task.task, "Failed to create adv thread task");
@@ -648,12 +648,12 @@ void bt_mesh_adv_init(void)
     adv_task.handle = xTaskCreateStaticPinnedToCore(adv_thread, BLE_MESH_ADV_TASK_NAME, BLE_MESH_ADV_TASK_STACK_SIZE, NULL,
                                   BLE_MESH_ADV_TASK_PRIO, adv_task.stack, adv_task.task, BLE_MESH_ADV_TASK_CORE);
     __ASSERT(adv_task.handle, "Failed to create static adv thread");
-#else /* CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && CONFIG_SPIRAM_CACHE_WORKAROUND && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
+#else /* CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
     int ret = xTaskCreatePinnedToCore(adv_thread, BLE_MESH_ADV_TASK_NAME, BLE_MESH_ADV_TASK_STACK_SIZE, NULL,
                                       BLE_MESH_ADV_TASK_PRIO, &adv_task.handle, BLE_MESH_ADV_TASK_CORE);
     __ASSERT(ret == pdTRUE, "Failed to create adv thread");
     (void)ret;
-#endif /* CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && CONFIG_SPIRAM_CACHE_WORKAROUND && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
+#endif /* CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
 }
 
 #if CONFIG_BLE_MESH_DEINIT
@@ -666,7 +666,7 @@ void bt_mesh_adv_deinit(void)
     vTaskDelete(adv_task.handle);
     adv_task.handle = NULL;
 #if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \
-     CONFIG_SPIRAM_CACHE_WORKAROUND && \
+    (CONFIG_SPIRAM_CACHE_WORKAROUND || !CONFIG_IDF_TARGET_ESP32) && \
      CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY)
     heap_caps_free(adv_task.stack);
     adv_task.stack = NULL;
diff --git a/components/driver/test/test_adc2_with_wifi.c b/components/driver/test/test_adc2_with_wifi.c
index e224ec73a9..e5c494df20 100644
--- a/components/driver/test/test_adc2_with_wifi.c
+++ b/components/driver/test/test_adc2_with_wifi.c
@@ -127,6 +127,11 @@ TEST_CASE("adc2 work with wifi","[adc]")
     esp_netif_create_default_wifi_sta();
 
     wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
+
+    /* Restrict the number of buffers to allocate to account for limited memory when running large number of tests */
+    cfg.static_rx_buf_num = 2;
+    cfg.static_tx_buf_num = 2;
+
     TEST_ESP_OK(esp_wifi_init(&cfg));
     wifi_config_t wifi_config = {
         .sta = {
diff --git a/components/esp32s2/Kconfig b/components/esp32s2/Kconfig
index 33c3b5af0b..e6102314ec 100644
--- a/components/esp32s2/Kconfig
+++ b/components/esp32s2/Kconfig
@@ -118,6 +118,10 @@ menu "ESP32S2-specific"
     menu "SPI RAM config"
         depends on ESP32S2_SPIRAM_SUPPORT
 
+        config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+            bool
+            default "y"
+
         choice SPIRAM_TYPE
             prompt "Type of SPI RAM chip in use"
             default SPIRAM_TYPE_AUTO
@@ -191,7 +195,8 @@ menu "ESP32S2-specific"
                 bool "20Mhz clock speed"
         endchoice
 
-        # insert non-chip-specific items here
+
+        # insert non-chip-specific items here NOERROR
         source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common"
 
     endmenu
diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig
index 84bd13543a..c05ea01eea 100644
--- a/components/esp32s3/Kconfig
+++ b/components/esp32s3/Kconfig
@@ -175,6 +175,10 @@ menu "ESP32S3-Specific"
     menu "SPI RAM config"
         depends on ESP32S3_SPIRAM_SUPPORT
 
+        config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+            bool
+            default "y"
+
         choice SPIRAM_MODE
             prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
             default SPIRAM_MODE_QUAD
diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c
index 4251b3f108..b130dd2fc0 100644
--- a/components/esp_system/port/soc/esp32s2/system_internal.c
+++ b/components/esp_system/port/soc/esp32s2/system_internal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,10 +23,15 @@
 #include "soc/rtc_periph.h"
 #include "hal/wdt_hal.h"
 #include "freertos/xtensa_api.h"
+#include "soc/soc_memory_layout.h"
 #include "hal/cpu_hal.h"
 
 #include "esp32s2/rom/rtc.h"
 
+#define ALIGN_DOWN(val, align)  ((val) & ~((align) - 1))
+
+extern int _bss_end;
+
 /* "inner" restart function for after RTOS, interrupts & anything else on this
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
@@ -68,6 +73,17 @@ void IRAM_ATTR esp_restart_noos(void)
     // Flush any data left in UART FIFOs
     esp_rom_uart_tx_wait_idle(0);
     esp_rom_uart_tx_wait_idle(1);
+
+#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+    if (esp_ptr_external_ram(esp_cpu_get_sp())) {
+        // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
+        // then need to switch SP to Internal Memory otherwise
+        // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
+        uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
+        SET_STACK(new_sp);
+    }
+#endif
+
     // Disable cache
     Cache_Disable_ICache();
     Cache_Disable_DCache();
diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c
index 4d9aec1666..073b7d17ed 100644
--- a/components/esp_system/port/soc/esp32s3/system_internal.c
+++ b/components/esp_system/port/soc/esp32s3/system_internal.c
@@ -1,6 +1,6 @@
 
 /*
- * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,10 +22,15 @@
 #include "soc/rtc_periph.h"
 #include "hal/wdt_hal.h"
 #include "freertos/xtensa_api.h"
+#include "soc/soc_memory_layout.h"
 
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/rtc.h"
 
+#define ALIGN_DOWN(val, align)  ((val) & ~((align) - 1))
+
+extern int _bss_end;
+
 /* "inner" restart function for after RTOS, interrupts & anything else on this
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
@@ -61,6 +66,17 @@ void IRAM_ATTR esp_restart_noos(void)
     // Flush any data left in UART FIFOs
     esp_rom_uart_tx_wait_idle(0);
     esp_rom_uart_tx_wait_idle(1);
+
+#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+    if (esp_ptr_external_ram(esp_cpu_get_sp())) {
+        // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
+        // then need to switch SP to Internal Memory otherwise
+        // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
+        uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
+        SET_STACK(new_sp);
+    }
+#endif
+
     // Disable cache
     Cache_Disable_ICache();
     Cache_Disable_DCache();
diff --git a/components/heap/test/test_aligned_alloc_caps.c b/components/heap/test/test_aligned_alloc_caps.c
index e66488155d..585061483a 100644
--- a/components/heap/test/test_aligned_alloc_caps.c
+++ b/components/heap/test/test_aligned_alloc_caps.c
@@ -43,11 +43,11 @@ TEST_CASE("Capabilities aligned allocator test", "[heap]")
     uint32_t *not_permitted_buf = (uint32_t *)heap_caps_aligned_alloc(alignments, (alignments + 137), MALLOC_CAP_EXEC | MALLOC_CAP_32BIT);
     TEST_ASSERT( not_permitted_buf == NULL );
 
-#if CONFIG_ESP32_SPIRAM_SUPPORT || CONFIG_ESP32S2_SPIRAM_SUPPORT
+#if CONFIG_SPIRAM
     alignments = 0;
     printf("[ALIGNED_ALLOC] Allocating from external memory: \n");
 
-    for(;alignments <= 1024 * 1024; alignments++) {
+    for(;alignments <= 1024 * 512; alignments++) {
         //Now try to take aligned memory from IRAM:
         uint8_t *buf = (uint8_t *)heap_caps_aligned_alloc(alignments, 10*1024, MALLOC_CAP_SPIRAM);
         if(((alignments & (alignments - 1)) != 0) || (!alignments)) {
@@ -112,11 +112,10 @@ TEST_CASE("Capabilities aligned calloc test", "[heap]")
     uint32_t *not_permitted_buf = (uint32_t *)heap_caps_aligned_calloc(alignments, 1, (alignments + 137), MALLOC_CAP_32BIT);
     TEST_ASSERT( not_permitted_buf == NULL );
 
-#if CONFIG_ESP32_SPIRAM_SUPPORT || CONFIG_ESP32S2_SPIRAM_SUPPORT
+#if CONFIG_SPIRAM
     alignments = 0;
     printf("[ALIGNED_ALLOC] Allocating from external memory: \n");
-
-    for(;alignments <= 1024 * 1024; alignments++) {
+    for(;alignments <= 1024 * 512; alignments++) {
         //Now try to take aligned memory from IRAM:
         uint8_t *buf = (uint8_t *)(uint8_t *)heap_caps_aligned_calloc(alignments, 1, 10*1024, MALLOC_CAP_SPIRAM);
         if(((alignments & (alignments - 1)) != 0) || (!alignments)) {
diff --git a/components/mbedtls/test/test_aes.c b/components/mbedtls/test/test_aes.c
index eba3ab56ba..780ba84eea 100644
--- a/components/mbedtls/test/test_aes.c
+++ b/components/mbedtls/test/test_aes.c
@@ -1474,30 +1474,58 @@ TEST_CASE("mbedtls AES external flash tests", "[aes]")
 #endif // CONFIG_SPIRAM_USE_MALLOC
 
 
-#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
-
-RTC_FAST_ATTR uint8_t rtc_stack[4096];
 static SemaphoreHandle_t done_sem;
 
-static void aes_ctr_stream_test_task(void *pv)
+static void __attribute__((unused)) aes_ctr_stream_test_task(void *pv)
 {
     aes_ctr_stream_test();
     xSemaphoreGive(done_sem);
     vTaskDelete(NULL);
 }
 
+#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
+
 TEST_CASE("mbedtls AES stack in RTC RAM", "[mbedtls]")
 {
     done_sem = xSemaphoreCreateBinary();
     static StaticTask_t rtc_task;
-    memset(rtc_stack, 0, sizeof(rtc_stack));
-
+    size_t STACK_SIZE = 3072;
+    uint8_t *rtc_stack = heap_caps_calloc(STACK_SIZE, 1, MALLOC_CAP_RTCRAM);
     TEST_ASSERT(esp_ptr_in_rtc_dram_fast(rtc_stack));
 
-    TEST_ASSERT_NOT_NULL(xTaskCreateStatic(aes_ctr_stream_test_task, "aes_ctr_task", sizeof(rtc_stack), NULL,
+    TEST_ASSERT_NOT_NULL(xTaskCreateStatic(aes_ctr_stream_test_task, "aes_ctr_task", STACK_SIZE, NULL,
                                             3, rtc_stack, &rtc_task));
     TEST_ASSERT_TRUE(xSemaphoreTake(done_sem, 10000 / portTICK_PERIOD_MS));
+
+    /* Give task time to cleanup before freeing stack */
+    vTaskDelay(1000 / portTICK_PERIOD_MS);
+    free(rtc_stack);
+
     vSemaphoreDelete(done_sem);
 }
 
 #endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
+
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
+
+TEST_CASE("mbedtls AES stack in PSRAM", "[mbedtls]")
+{
+    done_sem = xSemaphoreCreateBinary();
+    static StaticTask_t psram_task;
+    size_t STACK_SIZE = 3072;
+    uint8_t *psram_stack = heap_caps_calloc(STACK_SIZE, 1, MALLOC_CAP_SPIRAM);
+
+    TEST_ASSERT(esp_ptr_external_ram(psram_stack));
+
+    TEST_ASSERT_NOT_NULL(xTaskCreateStatic(aes_ctr_stream_test_task, "aes_ctr_task", STACK_SIZE, NULL,
+                                            3, psram_stack, &psram_task));
+    TEST_ASSERT_TRUE(xSemaphoreTake(done_sem, 10000 / portTICK_PERIOD_MS));
+
+    /* Give task time to cleanup before freeing stack */
+    vTaskDelay(1000 / portTICK_PERIOD_MS);
+    free(psram_stack);
+
+    vSemaphoreDelete(done_sem);
+}
+
+#endif //CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
diff --git a/components/mbedtls/test/test_mbedtls_sha.c b/components/mbedtls/test/test_mbedtls_sha.c
index 64a9244d11..7f78b4da5e 100644
--- a/components/mbedtls/test/test_mbedtls_sha.c
+++ b/components/mbedtls/test/test_mbedtls_sha.c
@@ -520,22 +520,48 @@ TEST_CASE("mbedtls SHA256 PSRAM DMA", "[mbedtls]")
 
 #if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
 
-extern RTC_FAST_ATTR uint8_t rtc_stack[4096];
-
-static SemaphoreHandle_t done_sem;
-
 TEST_CASE("mbedtls SHA stack in RTC RAM", "[mbedtls]")
 {
     done_sem = xSemaphoreCreateBinary();
     static StaticTask_t rtc_task;
-    memset(rtc_stack, 0, sizeof(rtc_stack));
+    size_t STACK_SIZE = 3072;
+    uint8_t *rtc_stack = heap_caps_calloc(STACK_SIZE, 1, MALLOC_CAP_RTCRAM);
 
     TEST_ASSERT(esp_ptr_in_rtc_dram_fast(rtc_stack));
 
-    TEST_ASSERT_NOT_NULL(xTaskCreateStatic(tskRunSHA256Test, "tskRunSHA256Test_task", sizeof(rtc_stack), NULL,
+    TEST_ASSERT_NOT_NULL(xTaskCreateStatic(tskRunSHA256Test, "tskRunSHA256Test_task", STACK_SIZE, NULL,
                                             3, rtc_stack, &rtc_task));
     TEST_ASSERT_TRUE(xSemaphoreTake(done_sem, 10000 / portTICK_PERIOD_MS));
+
+     /* Give task time to cleanup before freeing stack */
+    vTaskDelay(1000 / portTICK_PERIOD_MS);
+    free(rtc_stack);
+
     vSemaphoreDelete(done_sem);
 }
 
 #endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
+
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
+
+TEST_CASE("mbedtls SHA stack in PSRAM", "[mbedtls]")
+{
+    done_sem = xSemaphoreCreateBinary();
+    static StaticTask_t psram_task;
+    size_t STACK_SIZE = 3072;
+    uint8_t *psram_stack = heap_caps_calloc(STACK_SIZE, 1, MALLOC_CAP_SPIRAM);
+
+    TEST_ASSERT(esp_ptr_external_ram(psram_stack));
+
+    TEST_ASSERT_NOT_NULL(xTaskCreateStatic(tskRunSHA256Test, "tskRunSHA256Test_task", STACK_SIZE, NULL,
+                                            3, psram_stack, &psram_task));
+    TEST_ASSERT_TRUE(xSemaphoreTake(done_sem, 10000 / portTICK_PERIOD_MS));
+
+    /* Give task time to cleanup before freeing stack */
+    vTaskDelay(1000 / portTICK_PERIOD_MS);
+    free(psram_stack);
+
+    vSemaphoreDelete(done_sem);
+}
+
+#endif //CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index 8cb43abcdc..baf1823cab 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -798,11 +798,11 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
     uint32_t instruction_use_spiram = 0;
     uint32_t rodata_use_spiram = 0;
 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
-    extern uint32_t esp_spiram_instruction_access_enabled();
+    extern uint32_t esp_spiram_instruction_access_enabled(void);
     instruction_use_spiram = esp_spiram_instruction_access_enabled();
 #endif
 #if CONFIG_SPIRAM_RODATA
-    extern uint32_t esp_spiram_rodata_access_enabled();
+    extern uint32_t esp_spiram_rodata_access_enabled(void);
     rodata_use_spiram = esp_spiram_rodata_access_enabled();
 #endif
 
diff --git a/components/xtensa/include/xt_instr_macros.h b/components/xtensa/include/xt_instr_macros.h
index e7931f4bf4..efcdbd4a78 100644
--- a/components/xtensa/include/xt_instr_macros.h
+++ b/components/xtensa/include/xt_instr_macros.h
@@ -1,19 +1,13 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
+#include "xtensa/xtruntime.h"
+
 #define RSR(reg, at)         asm volatile ("rsr %0, %1" : "=r" (at) : "i" (reg))
 #define WSR(reg, at)         asm volatile ("wsr %0, %1" : : "r" (at), "i" (reg))
 #define XSR(reg, at)         asm volatile ("xsr %0, %1" : "+r" (at) : "i" (reg))
@@ -23,14 +17,27 @@
 #define WITLB(at, as)        asm volatile ("witlb  %0, %1; \n isync \n " : : "r" (at), "r" (as))
 #define WDTLB(at, as)        asm volatile ("wdtlb  %0, %1; \n dsync \n " : : "r" (at), "r" (as))
 
+#define EXTRA_SAVE_AREA_SIZE 32
+#define BASE_SAVE_AREA_SIZE  16
+#define SAVE_AREA_OFFSET (EXTRA_SAVE_AREA_SIZE + BASE_SAVE_AREA_SIZE)
+#define BASE_AREA_SP_OFFSET  12
+
 /* The SET_STACK implements a setting a new stack pointer (sp or a1).
  * to do this the need reset PS_WOE, reset WINDOWSTART, update SP, and return PS_WOE.
  *
+ * In addition, if a windowOverflow8/12 happens the exception handler expects to be able to look at
+ * the previous frames stackpointer to find the extra save area. So this function will reserve space
+ * for this area as well as initialise the previous sp that points to it
+ *
  * Note: It has 2 implementations one for using in assembler files (*.S) and one for using in C.
  *
  * C code prototype for SET_STACK:
  *   uint32_t ps_reg;
  *   uint32_t w_base;
+ *
+ *   uint32_t sp = (uint32_t)new_sp - SAVE_AREA_OFFSET; \
+    *(uint32_t*)(sp - 12) = (uint32_t)new_sp; \
+
  *   RSR(PS, ps_reg);
  *   ps_reg &= ~(PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK);
  *   WSR(PS, ps_reg);
@@ -46,6 +53,10 @@
 */
 #ifdef __ASSEMBLER__
     .macro SET_STACK  new_sp tmp1 tmp2
+    addi tmp1, new_sp, -SAVE_AREA_OFFSET
+    addi tmp2, tmp1, -BASE_AREA_SP_OFFSET
+    s32i new_sp, tmp2, 0
+    addi new_sp, tmp1, 0
     rsr.ps \tmp1
     movi \tmp2, ~(PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK)
     and \tmp1, \tmp1, \tmp2
@@ -68,8 +79,11 @@
     rsync
     .endm
 #else
+
 #define SET_STACK(new_sp) \
     do { \
+        uint32_t sp = (uint32_t)new_sp - SAVE_AREA_OFFSET; \
+        *(uint32_t*)(sp - BASE_AREA_SP_OFFSET) = (uint32_t)new_sp; \
         uint32_t tmp1 = 0, tmp2 = 0; \
         asm volatile ( \
           "rsr.ps %1 \n"\
@@ -93,6 +107,6 @@
           "or %1, %1, %2 \n"\
           "wsr.ps %1 \n"\
           "rsync \n"\
-          : "+r"(new_sp), "+r"(tmp1), "+r"(tmp2)); \
+          : "+r"(sp), "+r"(tmp1), "+r"(tmp2)); \
     } while (0);
 #endif // __ASSEMBLER__
diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst
index 2d1f8609d8..dab9191fe9 100644
--- a/docs/en/api-guides/external-ram.rst
+++ b/docs/en/api-guides/external-ram.rst
@@ -137,12 +137,18 @@ External RAM use has the following restrictions:
 
  * External RAM uses the same cache region as the external flash. This means that frequently accessed variables in external RAM can be read and modified almost as quickly as in internal ram. However, when accessing large chunks of data (>32 KB), the cache can be insufficient, and speeds will fall back to the access speed of the external RAM. Moreover, accessing large chunks of data can "push out" cached flash, possibly making the execution of code slower afterwards.
 
- * In general, external RAM cannot be used as task stack memory. Due to this, :cpp:func:`xTaskCreate` and similar functions will always allocate internal memory for stack and task TCBs, and functions such as :cpp:func:`xTaskCreateStatic` will check if the buffers passed are internal.
+ * In general, external RAM will not be used as task stack memory. :cpp:func:`xTaskCreate` and similar functions will always allocate internal memory for stack and task TCBs.
 
 .. only:: esp32
 
     The option :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` can be used to place task stacks into external memory. In these cases :cpp:func:`xTaskCreateStatic` must be used to specify a task stack buffer allocated from external memory, otherwise task stacks will still be allocated from internal memory.
 
+
+.. only:: not esp32
+
+    :cpp:func:`xTaskCreateStatic` can be used to explicitly place task stacks into external memory.
+
+
 Failure to initialize
 =====================
 
diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt
index b49059cd30..bdba16bbdd 100644
--- a/tools/ci/check_copyright_ignore.txt
+++ b/tools/ci/check_copyright_ignore.txt
@@ -2026,7 +2026,6 @@ components/xtensa/esp32s3/include/xtensa/config/tie-asm.h
 components/xtensa/esp32s3/include/xtensa/config/tie.h
 components/xtensa/include/eri.h
 components/xtensa/include/esp_private/panic_reason.h
-components/xtensa/include/xt_instr_macros.h
 components/xtensa/include/xt_trax.h
 components/xtensa/include/xtensa-debug-module.h
 components/xtensa/include/xtensa/cacheasm.h
diff --git a/tools/unit-test-app/configs/psram_s2_base b/tools/unit-test-app/configs/psram_s2_base
index a625628d56..d76d506cc5 100644
--- a/tools/unit-test-app/configs/psram_s2_base
+++ b/tools/unit-test-app/configs/psram_s2_base
@@ -1,3 +1,3 @@
 CONFIG_IDF_TARGET="esp32s2"
-TEST_COMPONENTS=esp_hw_support
+TEST_COMPONENTS=esp_hw_support mbedtls esp_system
 CONFIG_ESP32S2_SPIRAM_SUPPORT=y
diff --git a/tools/unit-test-app/configs/psram_s3_base b/tools/unit-test-app/configs/psram_s3_base
new file mode 100644
index 0000000000..6b85a2920a
--- /dev/null
+++ b/tools/unit-test-app/configs/psram_s3_base
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32s3"
+TEST_COMPONENTS=esp_hw_support mbedtls esp_system
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y