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https://github.com/espressif/esp-idf.git
synced 2026-05-04 20:05:25 +02:00
Move write key and stage action select constants into headers
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@@ -49,7 +49,7 @@ static void IRAM_ATTR task_wdt_isr(void *arg) {
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wdt_task_t *wdttask;
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const char *cpu;
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//Feed the watchdog so we do not reset
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TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_feed=1;
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TIMERG0.wdt_wprotect=0;
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//Ack interrupt
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@@ -107,7 +107,7 @@ void esp_task_wdt_feed() {
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}
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if (do_feed_wdt) {
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//All tasks have checked in; time to feed the hw watchdog.
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TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_feed=1;
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TIMERG0.wdt_wprotect=0;
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//Reset fed_watchdog status
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@@ -141,13 +141,13 @@ void esp_task_wdt_delete() {
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}
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void esp_task_wdt_init() {
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TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG0.wdt_config0.sys_reset_length=7; //3.2uS
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TIMERG0.wdt_config0.cpu_reset_length=7; //3.2uS
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TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_config0.sys_reset_length=7; //3.2uS
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TIMERG0.wdt_config0.cpu_reset_length=7; //3.2uS
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TIMERG0.wdt_config0.level_int_en=1;
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TIMERG0.wdt_config0.stg0=1; //1st stage timeout: interrupt
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TIMERG0.wdt_config0.stg1=3; //2nd stage timeout: reset system
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TIMERG0.wdt_config1.clk_prescale=80*500; //Prescaler: wdt counts in ticks of 0.5mS
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TIMERG0.wdt_config0.stg0=TIMG_WDT_STG_SEL_INT; //1st stage timeout: interrupt
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TIMERG0.wdt_config0.stg1=TIMG_WDT_STG_SEL_RESET_SYSTEM; //2nd stage timeout: reset system
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TIMERG0.wdt_config1.clk_prescale=80*500; //Prescaler: wdt counts in ticks of 0.5mS
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TIMERG0.wdt_config2=CONFIG_TASK_WDT_TIMEOUT_S*2000; //Set timeout before interrupt
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TIMERG0.wdt_config3=CONFIG_TASK_WDT_TIMEOUT_S*4000; //Set timeout before reset
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TIMERG0.wdt_config0.en=1;
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