diff --git a/components/esp_hw_support/include/esp_cpu.h b/components/esp_hw_support/include/esp_cpu.h
index c0b84749bf..f0f441b713 100644
--- a/components/esp_hw_support/include/esp_cpu.h
+++ b/components/esp_hw_support/include/esp_cpu.h
@@ -578,6 +578,14 @@ FORCE_INLINE_ATTR void esp_cpu_branch_prediction_enable(void)
 {
     rv_utils_en_branch_predictor();
 }
+
+/**
+ * @brief Disable branch prediction
+ */
+FORCE_INLINE_ATTR void esp_cpu_branch_prediction_disable(void)
+{
+    rv_utils_dis_branch_predictor();
+}
 #endif  //#if SOC_BRANCH_PREDICTOR_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h
index c0d3a64b2f..cc8c608e4a 100644
--- a/components/riscv/include/riscv/rv_utils.h
+++ b/components/riscv/include/riscv/rv_utils.h
@@ -27,6 +27,13 @@ extern "C" {
 #define CSR_PCCR_MACHINE    0x7e2
 #endif /* SOC_CPU_HAS_CSR_PC */
 
+#if SOC_BRANCH_PREDICTOR_SUPPORTED
+#define MHCR 0x7c1
+#define MHCR_RS (1<<4)   /* R/W, address return stack set bit */
+#define MHCR_BFE (1<<5)  /* R/W, allow predictive jump set bit */
+#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
+#endif  //SOC_BRANCH_PREDICTOR_SUPPORTED
+
 #if SOC_CPU_HAS_FPU
 
 /* FPU bits in mstatus start at bit 13 */
@@ -363,12 +370,13 @@ FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_
 #if SOC_BRANCH_PREDICTOR_SUPPORTED
 FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
 {
-#define MHCR 0x7c1
-#define MHCR_RS (1<<4)   /* R/W, address return stack set bit */
-#define MHCR_BFE (1<<5)  /* R/W, allow predictive jump set bit */
-#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
     RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
 }
+
+FORCE_INLINE_ATTR void rv_utils_dis_branch_predictor(void)
+{
+    RV_CLEAR_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
+}
 #endif
 
 #ifdef __cplusplus