From 427fe1bcde797b8cbd61844ad0ca59151e3e59b5 Mon Sep 17 00:00:00 2001 From: Wangjialin Date: Tue, 16 Mar 2021 00:50:31 +0800 Subject: [PATCH] uart: fix esp32c3 uart output garbage value after resetting --- components/driver/uart.c | 15 ++++++++++++--- components/esp32c3/system_api_esp32c3.c | 5 +++++ components/hal/esp32c3/include/hal/uart_ll.h | 5 ++--- components/hal/include/hal/uart_hal.h | 10 ++++++++++ components/soc/esp32c3/include/soc/soc_caps.h | 1 + 5 files changed, 30 insertions(+), 6 deletions(-) diff --git a/components/driver/uart.c b/components/driver/uart.c index bf21ac3f80..5e22420fe5 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -197,10 +197,19 @@ static void uart_module_enable(uart_port_t uart_num) { UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); if (uart_context[uart_num].hw_enabled != true) { - if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { - periph_module_reset(uart_periph_signal[uart_num].module); - } periph_module_enable(uart_periph_signal[uart_num].module); + if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { + // Workaround for ESP32C3: enable core reset + // before enabling uart module clock + // to prevent uart output garbage value. + #if SOC_UART_REQUIRE_CORE_RESET + uart_hal_set_reset_core(&(uart_context[uart_num].hal), true); + periph_module_reset(uart_periph_signal[uart_num].module); + uart_hal_set_reset_core(&(uart_context[uart_num].hal), false); + #else + periph_module_reset(uart_periph_signal[uart_num].module); + #endif + } uart_context[uart_num].hw_enabled = true; } UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); diff --git a/components/esp32c3/system_api_esp32c3.c b/components/esp32c3/system_api_esp32c3.c index 740769cfad..eb7f170974 100644 --- a/components/esp32c3/system_api_esp32c3.c +++ b/components/esp32c3/system_api_esp32c3.c @@ -31,6 +31,7 @@ #include "soc/rtc.h" #include "soc/syscon_reg.h" #include "soc/system_reg.h" +#include "soc/uart_reg.h" #include "hal/wdt_hal.h" /* "inner" restart function for after RTOS, interrupts & anything else on this @@ -99,6 +100,10 @@ void IRAM_ATTR esp_restart_noos(void) REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + // Reset uart0 core first, then reset apb side. + // rom will clear this bit, as well as SYSTEM_UART_RST + SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M); + // Reset timer/spi/uart SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST); diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index c166e472f5..a917caadcb 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -58,9 +58,8 @@ typedef enum { UART_INTR_CMD_CHAR_DET = (0x1 << 18), } uart_intr_t; -static inline void uart_ll_reset_core(uart_dev_t *hw) { - hw->clk_conf.rst_core = 1; - hw->clk_conf.rst_core = 0; +static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) { + hw->clk_conf.rst_core = core_rst_en; } static inline void uart_ll_sclk_enable(uart_dev_t *hw) { diff --git a/components/hal/include/hal/uart_hal.h b/components/hal/include/hal/uart_hal.h index d236431dca..f7b9488806 100644 --- a/components/hal/include/hal/uart_hal.h +++ b/components/hal/include/hal/uart_hal.h @@ -124,6 +124,16 @@ typedef struct { */ #define uart_hal_is_tx_idle(hal) uart_ll_is_tx_idle((hal)->dev) +/** + * @brief Configure the UART core reset + * + * @param hal Context of the HAL layer + * @param Set true to enable the core reset, otherwise set it false + * + * @return None + */ +#define uart_hal_set_reset_core(hal, core_rst_en) uart_ll_set_reset_core((hal)->dev, core_rst_en) + /** * @brief Read data from the UART rxfifo * diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 30f339318b..110c15c83c 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -229,6 +229,7 @@ #define SOC_UART_SUPPORT_RTC_CLK (1) #define SOC_UART_SUPPORT_XTAL_CLK (1) +#define SOC_UART_REQUIRE_CORE_RESET (1) // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)