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esp_system: fix garbled UART output on startup on esp32s2

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Closes https://github.com/espressif/esp-idf/issues/9168
This commit is contained in:
Ivan Grokhotkov
2022-06-16 15:28:21 +02:00
committed by BOT
parent a015532f66
commit 95dbc746ed
1 changed files with 6 additions and 0 deletions
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6
components/esp_system/port/soc/esp32s2/clk.c
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@@ -81,6 +81,12 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rst_reas = rtc_get_reset_reason(0); rst_reas = rtc_get_reset_reason(0);
if (rst_reas == POWERON_RESET) { if (rst_reas == POWERON_RESET) {
cfg.cali_ocode = 1; cfg.cali_ocode = 1;
/* Ocode calibration will switch to XTAL frequency, need to wait for UART FIFO
* to be empty, to avoid garbled output.
*/
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
} }
rtc_init(cfg); rtc_init(cfg);