From 96b152a01fa3522789c23f89bf4c15d5e8430661 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Tue, 6 Dec 2022 12:50:40 +0530 Subject: [PATCH] ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301 --- components/ulp/ulp_riscv.c | 4 ---- components/ulp/ulp_riscv/ulp_riscv_utils.c | 7 ++----- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/components/ulp/ulp_riscv.c b/components/ulp/ulp_riscv.c index 6e39254206..44c4953bbb 100644 --- a/components/ulp/ulp_riscv.c +++ b/components/ulp/ulp_riscv.c @@ -32,8 +32,6 @@ esp_err_t ulp_riscv_run(void) #if CONFIG_IDF_TARGET_ESP32S2 /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - esp_rom_delay_us(20); - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); /* The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ @@ -57,8 +55,6 @@ esp_err_t ulp_riscv_run(void) #elif CONFIG_IDF_TARGET_ESP32S3 /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - esp_rom_delay_us(20); - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); /* The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ diff --git a/components/ulp/ulp_riscv/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_riscv_utils.c index d6cbc60a46..d116f5e315 100644 --- a/components/ulp/ulp_riscv/ulp_riscv_utils.c +++ b/components/ulp/ulp_riscv/ulp_riscv_utils.c @@ -31,11 +31,8 @@ void ulp_riscv_shutdown(void) /* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */ REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F); - /* suspends the ulp operation*/ - SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE); - - /* Resets the processor */ - SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); + /* Suspends the ulp operation and reset the ULP core. Must be the final operation before going to halt. */ + SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN); while(1); }