From 7eb9ecb4f69123d0c2ed69595e13c486bf89c69d Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 2 Apr 2021 17:03:10 +0800 Subject: [PATCH 1/3] esp_ds: move timeout mechanism to driver layer --- components/esp32c3/esp_ds.c | 13 ++++++++----- components/hal/ds_hal.c | 12 ------------ components/hal/include/hal/ds_hal.h | 5 ----- 3 files changed, 8 insertions(+), 22 deletions(-) diff --git a/components/esp32c3/esp_ds.c b/components/esp32c3/esp_ds.c index e77c40531d..03b2f2fffb 100644 --- a/components/esp32c3/esp_ds.c +++ b/components/esp32c3/esp_ds.c @@ -21,9 +21,10 @@ #include "driver/periph_ctrl.h" #include "esp_crypto_lock.h" #include "hal/ds_hal.h" +#include "hal/ds_ll.h" #include "hal/hmac_hal.h" #include "esp32c3/rom/digital_signature.h" - +#include "esp_timer.h" #include "esp_ds.h" struct esp_ds_context { @@ -128,10 +129,12 @@ esp_err_t esp_ds_start_sign(const void *message, ds_hal_start(); // check encryption key from HMAC - ds_key_check_t key_check_result = ds_hal_check_decryption_key(); - if (key_check_result != DS_KEY_INPUT_OK) { - ds_disable_release(); - return ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY; + int64_t start_time = esp_timer_get_time(); + while (ds_ll_busy() != 0) { + if ((esp_timer_get_time() - start_time) > DS_KEY_CHECK_MAX_WAIT_US) { + ds_disable_release(); + return ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY; + } } esp_ds_context_t *context = malloc(sizeof(esp_ds_context_t)); diff --git a/components/hal/ds_hal.c b/components/hal/ds_hal.c index efd7404ae0..6a8fec9afd 100644 --- a/components/hal/ds_hal.c +++ b/components/hal/ds_hal.c @@ -26,18 +26,6 @@ void ds_hal_finish(void) ds_ll_finish(); } -ds_key_check_t ds_hal_check_decryption_key(void) -{ - uint64_t start_time = systimer_hal_get_time(SYSTIMER_COUNTER_0); - while (ds_ll_busy() != 0) { - if ((systimer_hal_get_time(SYSTIMER_COUNTER_0) - start_time) > DS_KEY_CHECK_MAX_WAIT_US) { - return ds_ll_key_error_source(); - } - } - - return DS_KEY_INPUT_OK; -} - void ds_hal_configure_iv(const uint32_t *iv) { ds_ll_configure_iv(iv); diff --git a/components/hal/include/hal/ds_hal.h b/components/hal/include/hal/ds_hal.h index fe7d7892fb..253fab9f96 100644 --- a/components/hal/include/hal/ds_hal.h +++ b/components/hal/include/hal/ds_hal.h @@ -60,11 +60,6 @@ void ds_hal_start(void); */ void ds_hal_finish(void); -/** - * @brief Check whether the key input (HMAC on ESP32-C3) is correct. - */ -ds_key_check_t ds_hal_check_decryption_key(void); - /** * @brief Write the initialization vector. */ From 7c1e1c9e2d58468e8d67e8378270514797297a8f Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 2 Apr 2021 12:41:08 +0800 Subject: [PATCH 2/3] systimer: update soc data --- components/esp32c3/ld/esp32c3.peripherals.ld | 1 + components/esp32s2/ld/esp32s2.peripherals.ld | 1 + components/esp32s3/ld/esp32s3.peripherals.ld | 2 +- components/hal/include/hal/systimer_types.h | 27 +- components/soc/esp32c3/include/soc/soc.h | 2 +- components/soc/esp32c3/include/soc/soc_caps.h | 10 +- .../soc/esp32c3/include/soc/systimer_caps.h | 24 - .../soc/esp32c3/include/soc/systimer_reg.h | 917 ++++++++++-------- .../soc/esp32c3/include/soc/systimer_struct.h | 559 ++++++----- components/soc/esp32s2/include/soc/soc_caps.h | 7 +- .../soc/esp32s2/include/soc/systimer_reg.h | 170 ++-- .../soc/esp32s2/include/soc/systimer_struct.h | 330 +++++++ components/soc/esp32s3/include/soc/soc.h | 2 +- components/soc/esp32s3/include/soc/soc_caps.h | 8 +- .../soc/esp32s3/include/soc/sys_timer_reg.h | 474 --------- .../esp32s3/include/soc/sys_timer_struct.h | 271 ------ .../soc/esp32s3/include/soc/systimer_caps.h | 22 - .../soc/esp32s3/include/soc/systimer_reg.h | 639 ++++++++++++ .../soc/esp32s3/include/soc/systimer_struct.h | 397 ++++++++ 19 files changed, 2337 insertions(+), 1526 deletions(-) delete mode 100644 components/soc/esp32c3/include/soc/systimer_caps.h create mode 100644 components/soc/esp32s2/include/soc/systimer_struct.h delete mode 100644 components/soc/esp32s3/include/soc/sys_timer_reg.h delete mode 100644 components/soc/esp32s3/include/soc/sys_timer_struct.h delete mode 100644 components/soc/esp32s3/include/soc/systimer_caps.h create mode 100644 components/soc/esp32s3/include/soc/systimer_reg.h create mode 100644 components/soc/esp32s3/include/soc/systimer_struct.h diff --git a/components/esp32c3/ld/esp32c3.peripherals.ld b/components/esp32c3/ld/esp32c3.peripherals.ld index 61164a12cd..cd93401198 100644 --- a/components/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/esp32c3/ld/esp32c3.peripherals.ld @@ -20,6 +20,7 @@ PROVIDE ( SLC = 0x60018000 ); PROVIDE ( LEDC = 0x60019000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); diff --git a/components/esp32s2/ld/esp32s2.peripherals.ld b/components/esp32s2/ld/esp32s2.peripherals.ld index 512d840f8e..48aa0414ca 100644 --- a/components/esp32s2/ld/esp32s2.peripherals.ld +++ b/components/esp32s2/ld/esp32s2.peripherals.ld @@ -20,6 +20,7 @@ PROVIDE ( LEDC = 0x3f419000 ); PROVIDE ( CP_DMA = 0x3f4c3000 ); PROVIDE ( TIMERG0 = 0x3f41F000 ); PROVIDE ( TIMERG1 = 0x3f420000 ); +PROVIDE ( SYSTIMER = 0x3f423000 ); PROVIDE ( GPSPI2 = 0x3f424000 ); PROVIDE ( GPSPI3 = 0x3f425000 ); PROVIDE ( SYSCON = 0x3f426000 ); diff --git a/components/esp32s3/ld/esp32s3.peripherals.ld b/components/esp32s3/ld/esp32s3.peripherals.ld index 55772f958e..fd04255209 100644 --- a/components/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/esp32s3/ld/esp32s3.peripherals.ld @@ -23,7 +23,7 @@ PROVIDE ( MCPWM1 = 0x6002C000 ); PROVIDE ( MCP = 0x600c3000 ); PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); -PROVIDE ( SYS_TIMER = 0x60023000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); diff --git a/components/hal/include/hal/systimer_types.h b/components/hal/include/hal/systimer_types.h index cf88a00f24..2af2f60f30 100644 --- a/components/hal/include/hal/systimer_types.h +++ b/components/hal/include/hal/systimer_types.h @@ -14,13 +14,13 @@ #pragma once +#include +#include "soc/soc_caps.h" + #ifdef __cplusplus extern "C" { #endif -#include -#include "soc/soc_caps.h" - /* * @brief The structure of the counter value in systimer * @@ -39,27 +39,6 @@ typedef struct { _Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t should occupy 8 bytes in memory"); /** @endcond */ -/** - * @brief systimer counter ID - * - */ -typedef enum { - SYSTIMER_COUNTER_0, /*!< systimer counter 0 */ -#if SOC_SYSTIMER_COUNTER_NUM > 1 - SYSTIMER_COUNTER_1, /*!< systimer counter 1 */ -#endif -} systimer_counter_id_t; - -/** - * @brief systimer alarm ID - * - */ -typedef enum { - SYSTIMER_ALARM_0, /*!< systimer alarm 0 */ - SYSTIMER_ALARM_1, /*!< systimer alarm 1 */ - SYSTIMER_ALARM_2, /*!< systimer alarm 2 */ -} systimer_alarm_id_t; - /** * @brief systimer alarm mode * diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index e17ef9870e..a6769b990f 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -58,7 +58,7 @@ #define DR_REG_BB_BASE 0x6001D000 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SYSTIMER_BASE 0x60023000 #define DR_REG_SPI2_BASE 0x60024000 #define DR_REG_SYSCON_BASE 0x60026000 #define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index f36268f498..c886a8dd5a 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -16,7 +16,6 @@ #include "i2c_caps.h" #include "mpu_caps.h" #include "sigmadelta_caps.h" -#include "systimer_caps.h" #include "uart_caps.h" #include "brownout_caps.h" #include "gdma_caps.h" @@ -62,6 +61,15 @@ #define SOC_SHA_SUPPORT_SHA224 (1) #define SOC_SHA_SUPPORT_SHA256 (1) +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1) diff --git a/components/soc/esp32c3/include/soc/systimer_caps.h b/components/soc/esp32c3/include/soc/systimer_caps.h deleted file mode 100644 index feda097f45..0000000000 --- a/components/soc/esp32c3/include/soc/systimer_caps.h +++ /dev/null @@ -1,24 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units - -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part - -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // If defined, number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt diff --git a/components/soc/esp32c3/include/soc/systimer_reg.h b/components/soc/esp32c3/include/soc/systimer_reg.h index cb6ebe6a43..4e9f64fffa 100644 --- a/components/soc/esp32c3/include/soc/systimer_reg.h +++ b/components/soc/esp32c3/include/soc/systimer_reg.h @@ -1,424 +1,567 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_REG_H_ -#define _SOC_SYS_TIMER_REG_H_ - +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000) -/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: register file clk gating*/ -#define SYS_TIMER_CLK_EN (BIT(31)) -#define SYS_TIMER_CLK_EN_M (BIT(31)) -#define SYS_TIMER_CLK_EN_V 0x1 -#define SYS_TIMER_CLK_EN_S 31 -/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: timer unit0 work enable*/ -#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 -/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer unit1 work enable*/ -#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 -/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core0 stalled*/ -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 -/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core1 stalled*/ -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 -/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core0 stalled*/ -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 -/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core1 stalled*/ -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 -/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: target0 work enable*/ -#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET0_WORK_EN_S 24 -/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: target1 work enable*/ -#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET1_WORK_EN_S 23 -/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: target2 work enable*/ -#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET2_WORK_EN_S 22 -/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: systimer clock force on*/ -#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 -#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004) -/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer_unit0*/ -#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_CONF_REG register + * SYSTIMER_CONF. + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTIMER_CLK_EN_S 31 -#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008) -/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer unit1*/ -#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_UNIT0_OP_REG register + * SYSTIMER_UNIT0_OP. + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C) -/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit0 load high 32 bit*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 +/** SYSTIMER_UNIT1_OP_REG register + * SYSTIMER_UNIT1_OP. + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010) -/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit0 load low 32 bit*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * SYSTIMER_UNIT0_LOAD_HI. + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014) -/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit1 load high 32 bit*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * SYSTIMER_UNIT0_LOAD_LO. + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018) -/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit1 load low 32 bit*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * SYSTIMER_UNIT1_LOAD_HI. + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C) -/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget0 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) -#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_S 0 +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * SYSTIMER_UNIT1_LOAD_LO. + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bit + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020) -/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget0 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) -#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_S 0 +/** SYSTIMER_TARGET0_HI_REG register + * SYSTIMER_TARGET0_HI. + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024) -/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget1 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) -#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_S 0 +/** SYSTIMER_TARGET0_LO_REG register + * SYSTIMER_TARGET0_LO. + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028) -/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget1 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) -#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_S 0 +/** SYSTIMER_TARGET1_HI_REG register + * SYSTIMER_TARGET1_HI. + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C) -/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget2 high 32 bit*/ -#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) -#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_S 0 +/** SYSTIMER_TARGET1_LO_REG register + * SYSTIMER_TARGET1_LO. + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030) -/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget2 low 32 bit*/ -#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) -#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_S 0 +/** SYSTIMER_TARGET2_HI_REG register + * SYSTIMER_TARGET2_HI. + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_S 0 -#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034) -/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target0 to period mode*/ -#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target0 period*/ -#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) -#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET2_LO_REG register + * SYSTIMER_TARGET2_LO. + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bit + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_S 0 -#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038) -/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target1 to period mode*/ -#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target1 period*/ -#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) -#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET0_CONF_REG register + * SYSTIMER_TARGET0_CONF. + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 -#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C) -/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare*/ -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target2 to period mode*/ -#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target2 period*/ -#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) -#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET1_CONF_REG register + * SYSTIMER_TARGET1_CONF. + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040) -/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 +/** SYSTIMER_TARGET2_CONF_REG register + * SYSTIMER_TARGET2_CONF. + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044) -/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * SYSTIMER_UNIT0_VALUE_HI. + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048) -/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * SYSTIMER_UNIT0_VALUE_LO. + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C) -/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * SYSTIMER_UNIT1_VALUE_HI. + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 -#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050) -/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp0 load value*/ -#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * SYSTIMER_UNIT1_VALUE_LO. + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 -#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054) -/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp1 load value*/ -#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 +/** SYSTIMER_COMP0_LOAD_REG register + * SYSTIMER_COMP0_LOAD. + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 load value + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058) -/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp2 load value*/ -#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 +/** SYSTIMER_COMP1_LOAD_REG register + * SYSTIMER_COMP1_LOAD. + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 load value + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C) -/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit0 load value*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 +/** SYSTIMER_COMP2_LOAD_REG register + * SYSTIMER_COMP2_LOAD. + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 load value + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060) -/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit1 load value*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 +/** SYSTIMER_UNIT0_LOAD_REG register + * SYSTIMER_UNIT0_LOAD. + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 load value + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064) -/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 enable*/ -#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET2_INT_ENA_S 2 -/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 enable*/ -#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET1_INT_ENA_S 1 -/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 enable*/ -#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_UNIT1_LOAD_REG register + * SYSTIMER_UNIT1_LOAD. + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 load value + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 -#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068) -/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 raw*/ -#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET2_INT_RAW_S 2 -/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 raw*/ -#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET1_INT_RAW_S 1 -/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 raw*/ -#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_INT_ENA_REG register + * SYSTIMER_INT_ENA. + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ENA_S 2 -#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c) -/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 clear*/ -#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET2_INT_CLR_S 2 -/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 clear*/ -#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET1_INT_CLR_S 1 -/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 clear*/ -#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_INT_RAW_REG register + * SYSTIMER_INT_RAW. + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET2_INT_RAW_S 2 -#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070) -/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_V 0x1 -#define SYS_TIMER_TARGET2_INT_ST_S 2 -/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_V 0x1 -#define SYS_TIMER_TARGET1_INT_ST_S 1 -/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_V 0x1 -#define SYS_TIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_INT_CLR_REG register + * SYSTIMER_INT_CLR. + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET2_INT_CLR_S 2 -#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc) -/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2006171 ; */ -/*description: */ -#define SYS_TIMER_DATE 0xFFFFFFFF -#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) -#define SYS_TIMER_DATE_V 0xFFFFFFFF -#define SYS_TIMER_DATE_S 0 +/** SYSTIMER_INT_ST_REG register + * SYSTIMER_INT_ST. + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_DATE_REG register + * SYSTIMER_DATE. + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ +#define SYSTIMER_DATE 0xFFFFFFFF +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFF +#define SYSTIMER_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SYS_TIMER_REG_H_ */ diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/include/soc/systimer_struct.h index b029eca80b..af41b1f3e2 100644 --- a/components/soc/esp32c3/include/soc/systimer_struct.h +++ b/components/soc/esp32c3/include/soc/systimer_struct.h @@ -1,251 +1,370 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_STRUCT_H_ -#define _SOC_SYS_TIMER_STRUCT_H_ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct { +/** Configuration Register */ +/** Type of conf register + * SYSTIMER_CONF. + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo: 1; + uint32_t reserved_1: 21; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en: 1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en: 1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en: 1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en: 1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en: 1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en: 1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en: 1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en: 1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en: 1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit_update: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ +typedef struct { union { struct { - uint32_t systimer_clk_fo: 1; /*systimer clock force on*/ - uint32_t reserved1: 21; - uint32_t target2_work_en: 1; /*target2 work enable*/ - uint32_t target1_work_en: 1; /*target1 work enable*/ - uint32_t target0_work_en: 1; /*target0 work enable*/ - uint32_t timer_unit1_core1_stall_en: 1; /*If timer unit1 is stalled when core1 stalled*/ - uint32_t timer_unit1_core0_stall_en: 1; /*If timer unit1 is stalled when core0 stalled*/ - uint32_t timer_unit0_core1_stall_en: 1; /*If timer unit0 is stalled when core1 stalled*/ - uint32_t timer_unit0_core0_stall_en: 1; /*If timer unit0 is stalled when core0 stalled*/ - uint32_t timer_unit1_work_en: 1; /*timer unit1 work enable*/ - uint32_t timer_unit0_work_en: 1; /*timer unit0 work enable*/ - uint32_t clk_en: 1; /*register file clk gating*/ + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 32 bit + */ + uint32_t timer_unit_load_hi: 20; }; uint32_t val; - } systimer_conf; + } hi; union { struct { - uint32_t reserved0: 29; - uint32_t timer_unit0_value_valid: 1; - uint32_t timer_unit0_update: 1; /*update timer_unit0*/ - uint32_t reserved31: 1; + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; }; uint32_t val; - } systimer_unit0_op; + } lo; +} systimer_unit_load_val_reg_t; + +/** Type of target register + * SYSTIMER_TARGET. + */ +typedef struct { union { struct { - uint32_t reserved0: 29; - uint32_t timer_unit1_value_valid: 1; /*timer value is sync and valid*/ - uint32_t timer_unit1_update: 1; /*update timer unit1*/ - uint32_t reserved31: 1; + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 32 bit + */ + uint32_t timer_target_hi: 20; }; uint32_t val; - } systimer_unit1_op; + } hi; union { struct { - uint32_t timer_unit0_load_hi:20; /*timer unit0 load high 32 bit*/ - uint32_t reserved20: 12; + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; }; uint32_t val; - } systimer_unit0_load_hi; - uint32_t systimer_unit0_load_lo; /**/ + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ +typedef struct { union { struct { - uint32_t timer_unit1_load_hi:20; /*timer unit1 load high 32 bit*/ - uint32_t reserved20: 12; + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bit + */ + uint32_t timer_unit_value_hi: 20; }; uint32_t val; - } systimer_unit1_load_hi; - uint32_t systimer_unit1_load_lo; /**/ + } hi; union { struct { - uint32_t timer_target0_hi:20; /*timer taget0 high 32 bit*/ - uint32_t reserved20: 12; + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ + uint32_t timer_unit_value_lo: 32; }; uint32_t val; - } systimer_target0_hi; - uint32_t systimer_target0_lo; /**/ - union { - struct { - uint32_t timer_target1_hi:20; /*timer taget1 high 32 bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_target1_hi; - uint32_t systimer_target1_lo; /**/ - union { - struct { - uint32_t timer_target2_hi:20; /*timer taget2 high 32 bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_target2_hi; - uint32_t systimer_target2_lo; /**/ - union { - struct { - uint32_t target0_period: 26; /*target0 period*/ - uint32_t reserved26: 4; - uint32_t target0_period_mode: 1; /*Set target0 to period mode*/ - uint32_t target0_timer_unit_sel: 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target0_conf; - union { - struct { - uint32_t target1_period: 26; /*target1 period*/ - uint32_t reserved26: 4; - uint32_t target1_period_mode: 1; /*Set target1 to period mode*/ - uint32_t target1_timer_unit_sel: 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target1_conf; - union { - struct { - uint32_t target2_period: 26; /*target2 period*/ - uint32_t reserved26: 4; - uint32_t target2_period_mode: 1; /*Set target2 to period mode*/ - uint32_t target2_timer_unit_sel: 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target2_conf; - union { - struct { - uint32_t timer_unit0_value_hi:20; /*timer read value high 32bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_unit0_value_hi; - uint32_t systimer_unit0_value_lo; /**/ - union { - struct { - uint32_t timer_unit1_value_hi:20; /*timer read value high 32bit*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } systimer_unit1_value_hi; - uint32_t systimer_unit1_value_lo; /**/ - union { - struct { - uint32_t timer_comp0_load: 1; /*timer comp0 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_comp0_load; - union { - struct { - uint32_t timer_comp1_load: 1; /*timer comp1 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_comp1_load; - union { - struct { - uint32_t timer_comp2_load: 1; /*timer comp2 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_comp2_load; - union { - struct { - uint32_t timer_unit0_load: 1; /*timer unit0 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_unit0_load; - union { - struct { - uint32_t timer_unit1_load: 1; /*timer unit1 load value*/ - uint32_t reserved1: 31; - }; - uint32_t val; - } systimer_unit1_load; - union { - struct { - uint32_t target0: 1; /*interupt0 enable*/ - uint32_t target1: 1; /*interupt1 enable*/ - uint32_t target2: 1; /*interupt2 enable*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_ena; - union { - struct { - uint32_t target0: 1; /*interupt0 raw*/ - uint32_t target1: 1; /*interupt1 raw*/ - uint32_t target2: 1; /*interupt2 raw*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_raw; - union { - struct { - uint32_t target0: 1; /*interupt0 clear*/ - uint32_t target1: 1; /*interupt1 clear*/ - uint32_t target2: 1; /*interupt2 clear*/ - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_clr; - union { - struct { - uint32_t target0: 1; - uint32_t target1: 1; - uint32_t target2: 1; - uint32_t reserved3: 29; - }; - uint32_t val; - } systimer_int_st; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t systimer_date; /**/ -} sys_timer_dev_t; -extern sys_timer_dev_t SYS_TIMER; + } lo; +} systimer_unit_value_reg_t; + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp load value + */ + uint32_t timer_comp_load: 1; + }; + uint32_t val; +} systimer_comp_load_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + }; + uint32_t val; +} systimer_unit_load_reg_t; + +/** Interrupt Register */ +/** Type of int_ena register + * SYSTIMER_INT_ENA. + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena: 1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena: 1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * SYSTIMER_INT_RAW. + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw: 1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw: 1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * SYSTIMER_INT_CLR. + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr: 1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr: 1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * SYSTIMER_INT_ST. + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * reg_target0_int_st + */ + uint32_t target0_int_st: 1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * reg_target1_int_st + */ + uint32_t target1_int_st: 1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * reg_target2_int_st + */ + uint32_t target2_int_st: 1; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** Version Register */ +/** Type of date register + * SYSTIMER_DATE. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 33579377; + * reg_date + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + #ifdef __cplusplus } #endif - -#endif /* _SOC_SYS_TIMER_STRUCT_H_ */ diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 5d16add7a8..355994d420 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -210,10 +210,9 @@ #define SOC_MEMSPI_IS_INDEPENDENT 1 -/*-------------------------- SYS TIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units - +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units #define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part #define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part diff --git a/components/soc/esp32s2/include/soc/systimer_reg.h b/components/soc/esp32s2/include/soc/systimer_reg.h index 5debf1148a..ede37127c4 100644 --- a/components/soc/esp32s2/include/soc/systimer_reg.h +++ b/components/soc/esp32s2/include/soc/systimer_reg.h @@ -1,16 +1,17 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #pragma once #include @@ -38,7 +39,6 @@ extern "C" { #define SYSTIMER_CLK_EN_V 0x00000001 #define SYSTIMER_CLK_EN_S 31 - /** SYSTIMER_LOAD_REG register * load value to system timer */ @@ -51,12 +51,11 @@ extern "C" { #define SYSTIMER_TIMER_LOAD_V 0x00000001 #define SYSTIMER_TIMER_LOAD_S 31 - /** SYSTIMER_LOAD_HI_REG register * High 32-bit load to system timer */ #define SYSTIMER_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x8) -/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [31:0]; default: 0; * High 32-bit load to system timer */ #define SYSTIMER_TIMER_LOAD_HI 0xFFFFFFFF @@ -64,12 +63,11 @@ extern "C" { #define SYSTIMER_TIMER_LOAD_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_LOAD_HI_S 0 - /** SYSTIMER_LOAD_LO_REG register * Low 32-bit load to system timer */ #define SYSTIMER_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0xc) -/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [31:0]; default: 0; * Low 32-bit load to system timer */ #define SYSTIMER_TIMER_LOAD_LO 0xFFFFFFFF @@ -77,19 +75,18 @@ extern "C" { #define SYSTIMER_TIMER_LOAD_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_LOAD_LO_S 0 - /** SYSTIMER_STEP_REG register * system timer accumulation step */ #define SYSTIMER_STEP_REG (DR_REG_SYSTIMER_BASE + 0x10) -/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [10:0]; default: 80; +/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [9:0]; default: 80; * system timer accumulation step when using XTAL */ #define SYSTIMER_TIMER_XTAL_STEP 0x000003FF #define SYSTIMER_TIMER_XTAL_STEP_M (SYSTIMER_TIMER_XTAL_STEP_V << SYSTIMER_TIMER_XTAL_STEP_S) #define SYSTIMER_TIMER_XTAL_STEP_V 0x000003FF #define SYSTIMER_TIMER_XTAL_STEP_S 0 -/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [20:10]; default: 1; +/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [19:10]; default: 1; * system timer accumulation step when using PLL */ #define SYSTIMER_TIMER_PLL_STEP 0x000003FF @@ -97,12 +94,11 @@ extern "C" { #define SYSTIMER_TIMER_PLL_STEP_V 0x000003FF #define SYSTIMER_TIMER_PLL_STEP_S 10 - /** SYSTIMER_TARGET0_HI_REG register * System timer target0 high 32-bit */ #define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) -/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [31:0]; default: 0; * System timer target0 high 32-bit */ #define SYSTIMER_TIMER_TARGET0_HI 0xFFFFFFFF @@ -110,12 +106,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET0_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET0_HI_S 0 - /** SYSTIMER_TARGET0_LO_REG register * System timer target0 low 32-bit */ #define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) -/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; * System timer target0 low 32-bit */ #define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF @@ -123,12 +118,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET0_LO_S 0 - /** SYSTIMER_TARGET1_HI_REG register * System timer target1 high 32-bit */ #define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) -/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [31:0]; default: 0; * System timer target1 high 32-bit */ #define SYSTIMER_TIMER_TARGET1_HI 0xFFFFFFFF @@ -136,12 +130,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET1_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET1_HI_S 0 - /** SYSTIMER_TARGET1_LO_REG register * System timer target1 low 32-bit */ #define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) -/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; * System timer target1 low 32-bit */ #define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF @@ -149,12 +142,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET1_LO_S 0 - /** SYSTIMER_TARGET2_HI_REG register * System timer target2 high 32-bit */ #define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) -/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [31:0]; default: 0; * System timer target2 high 32-bit */ #define SYSTIMER_TIMER_TARGET2_HI 0xFFFFFFFF @@ -162,12 +154,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET2_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET2_HI_S 0 - /** SYSTIMER_TARGET2_LO_REG register * System timer target2 low 32-bit */ #define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) -/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; * System timer target2 low 32-bit */ #define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF @@ -175,12 +166,11 @@ extern "C" { #define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_TARGET2_LO_S 0 - /** SYSTIMER_TARGET0_CONF_REG register * Configure system timer target0 work mode */ #define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x2c) -/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [30:0]; default: 0; +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [29:0]; default: 0; * System timer target0 alarm period */ #define SYSTIMER_TARGET0_PERIOD 0x3FFFFFFF @@ -202,12 +192,11 @@ extern "C" { #define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 #define SYSTIMER_TARGET0_WORK_EN_S 31 - /** SYSTIMER_TARGET1_CONF_REG register * Configure system timer target1 work mode */ #define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x30) -/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [30:0]; default: 0; +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [29:0]; default: 0; * System timer target1 alarm period */ #define SYSTIMER_TARGET1_PERIOD 0x3FFFFFFF @@ -229,12 +218,11 @@ extern "C" { #define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 #define SYSTIMER_TARGET1_WORK_EN_S 31 - /** SYSTIMER_TARGET2_CONF_REG register * Configure system timer target2 work mode */ #define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) -/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [30:0]; default: 0; +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [29:0]; default: 0; * System timer target2 alarm period */ #define SYSTIMER_TARGET2_PERIOD 0x3FFFFFFF @@ -256,7 +244,6 @@ extern "C" { #define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 #define SYSTIMER_TARGET2_WORK_EN_S 31 - /** SYSTIMER_UPDATE_REG register * Read out system timer value */ @@ -276,12 +263,11 @@ extern "C" { #define SYSTIMER_TIMER_UPDATE_V 0x00000001 #define SYSTIMER_TIMER_UPDATE_S 31 - /** SYSTIMER_VALUE_HI_REG register * system timer high 32-bit */ #define SYSTIMER_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x3c) -/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [31:0]; default: 0; * system timer high 32-bit */ #define SYSTIMER_TIMER_VALUE_HI 0xFFFFFFFF @@ -289,12 +275,11 @@ extern "C" { #define SYSTIMER_TIMER_VALUE_HI_V 0xFFFFFFFF #define SYSTIMER_TIMER_VALUE_HI_S 0 - /** SYSTIMER_VALUE_LO_REG register * system timer low 32-bit */ #define SYSTIMER_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x40) -/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [32:0]; default: 0; +/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [31:0]; default: 0; * system timer low 32-bit */ #define SYSTIMER_TIMER_VALUE_LO 0xFFFFFFFF @@ -302,93 +287,89 @@ extern "C" { #define SYSTIMER_TIMER_VALUE_LO_V 0xFFFFFFFF #define SYSTIMER_TIMER_VALUE_LO_S 0 - /** SYSTIMER_INT_ENA_REG register * system timer interrupt enable */ #define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x44) -/** SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0; +/** SYSTIMER_SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0; * system timer target0 interrupt enable */ -#define SYSTIMER_INT0_ENA (BIT(0)) -#define SYSTIMER_INT0_ENA_M (SYSTIMER_INT0_ENA_V << SYSTIMER_INT0_ENA_S) -#define SYSTIMER_INT0_ENA_V 0x00000001 -#define SYSTIMER_INT0_ENA_S 0 -/** SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0; +#define SYSTIMER_SYSTIMER_INT0_ENA (BIT(0)) +#define SYSTIMER_SYSTIMER_INT0_ENA_M (SYSTIMER_SYSTIMER_INT0_ENA_V << SYSTIMER_SYSTIMER_INT0_ENA_S) +#define SYSTIMER_SYSTIMER_INT0_ENA_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT0_ENA_S 0 +/** SYSTIMER_SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0; * system timer target1 interrupt enable */ -#define SYSTIMER_INT1_ENA (BIT(1)) -#define SYSTIMER_INT1_ENA_M (SYSTIMER_INT1_ENA_V << SYSTIMER_INT1_ENA_S) -#define SYSTIMER_INT1_ENA_V 0x00000001 -#define SYSTIMER_INT1_ENA_S 1 -/** SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0; +#define SYSTIMER_SYSTIMER_INT1_ENA (BIT(1)) +#define SYSTIMER_SYSTIMER_INT1_ENA_M (SYSTIMER_SYSTIMER_INT1_ENA_V << SYSTIMER_SYSTIMER_INT1_ENA_S) +#define SYSTIMER_SYSTIMER_INT1_ENA_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT1_ENA_S 1 +/** SYSTIMER_SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0; * system timer target2 interrupt enable */ -#define SYSTIMER_INT2_ENA (BIT(2)) -#define SYSTIMER_INT2_ENA_M (SYSTIMER_INT2_ENA_V << SYSTIMER_INT2_ENA_S) -#define SYSTIMER_INT2_ENA_V 0x00000001 -#define SYSTIMER_INT2_ENA_S 2 - +#define SYSTIMER_SYSTIMER_INT2_ENA (BIT(2)) +#define SYSTIMER_SYSTIMER_INT2_ENA_M (SYSTIMER_SYSTIMER_INT2_ENA_V << SYSTIMER_SYSTIMER_INT2_ENA_S) +#define SYSTIMER_SYSTIMER_INT2_ENA_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT2_ENA_S 2 /** SYSTIMER_INT_RAW_REG register * system timer interrupt raw */ #define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x48) -/** SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0; +/** SYSTIMER_SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0; * system timer target0 interrupt raw */ -#define SYSTIMER_INT0_RAW (BIT(0)) -#define SYSTIMER_INT0_RAW_M (SYSTIMER_INT0_RAW_V << SYSTIMER_INT0_RAW_S) -#define SYSTIMER_INT0_RAW_V 0x00000001 -#define SYSTIMER_INT0_RAW_S 0 -/** SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0; +#define SYSTIMER_SYSTIMER_INT0_RAW (BIT(0)) +#define SYSTIMER_SYSTIMER_INT0_RAW_M (SYSTIMER_SYSTIMER_INT0_RAW_V << SYSTIMER_SYSTIMER_INT0_RAW_S) +#define SYSTIMER_SYSTIMER_INT0_RAW_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT0_RAW_S 0 +/** SYSTIMER_SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0; * system timer target1 interrupt raw */ -#define SYSTIMER_INT1_RAW (BIT(1)) -#define SYSTIMER_INT1_RAW_M (SYSTIMER_INT1_RAW_V << SYSTIMER_INT1_RAW_S) -#define SYSTIMER_INT1_RAW_V 0x00000001 -#define SYSTIMER_INT1_RAW_S 1 -/** SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0; +#define SYSTIMER_SYSTIMER_INT1_RAW (BIT(1)) +#define SYSTIMER_SYSTIMER_INT1_RAW_M (SYSTIMER_SYSTIMER_INT1_RAW_V << SYSTIMER_SYSTIMER_INT1_RAW_S) +#define SYSTIMER_SYSTIMER_INT1_RAW_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT1_RAW_S 1 +/** SYSTIMER_SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0; * system timer target2 interrupt raw */ -#define SYSTIMER_INT2_RAW (BIT(2)) -#define SYSTIMER_INT2_RAW_M (SYSTIMER_INT2_RAW_V << SYSTIMER_INT2_RAW_S) -#define SYSTIMER_INT2_RAW_V 0x00000001 -#define SYSTIMER_INT2_RAW_S 2 - +#define SYSTIMER_SYSTIMER_INT2_RAW (BIT(2)) +#define SYSTIMER_SYSTIMER_INT2_RAW_M (SYSTIMER_SYSTIMER_INT2_RAW_V << SYSTIMER_SYSTIMER_INT2_RAW_S) +#define SYSTIMER_SYSTIMER_INT2_RAW_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT2_RAW_S 2 /** SYSTIMER_INT_CLR_REG register * system timer interrupt clear */ #define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x4c) -/** SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0; +/** SYSTIMER_SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0; * system timer target0 interrupt clear */ -#define SYSTIMER_INT0_CLR (BIT(0)) -#define SYSTIMER_INT0_CLR_M (SYSTIMER_INT0_CLR_V << SYSTIMER_INT0_CLR_S) -#define SYSTIMER_INT0_CLR_V 0x00000001 -#define SYSTIMER_INT0_CLR_S 0 -/** SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0; +#define SYSTIMER_SYSTIMER_INT0_CLR (BIT(0)) +#define SYSTIMER_SYSTIMER_INT0_CLR_M (SYSTIMER_SYSTIMER_INT0_CLR_V << SYSTIMER_SYSTIMER_INT0_CLR_S) +#define SYSTIMER_SYSTIMER_INT0_CLR_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT0_CLR_S 0 +/** SYSTIMER_SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0; * system timer target1 interrupt clear */ -#define SYSTIMER_INT1_CLR (BIT(1)) -#define SYSTIMER_INT1_CLR_M (SYSTIMER_INT1_CLR_V << SYSTIMER_INT1_CLR_S) -#define SYSTIMER_INT1_CLR_V 0x00000001 -#define SYSTIMER_INT1_CLR_S 1 -/** SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0; +#define SYSTIMER_SYSTIMER_INT1_CLR (BIT(1)) +#define SYSTIMER_SYSTIMER_INT1_CLR_M (SYSTIMER_SYSTIMER_INT1_CLR_V << SYSTIMER_SYSTIMER_INT1_CLR_S) +#define SYSTIMER_SYSTIMER_INT1_CLR_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT1_CLR_S 1 +/** SYSTIMER_SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0; * system timer target2 interrupt clear */ -#define SYSTIMER_INT2_CLR (BIT(2)) -#define SYSTIMER_INT2_CLR_M (SYSTIMER_INT2_CLR_V << SYSTIMER_INT2_CLR_S) -#define SYSTIMER_INT2_CLR_V 0x00000001 -#define SYSTIMER_INT2_CLR_S 2 - +#define SYSTIMER_SYSTIMER_INT2_CLR (BIT(2)) +#define SYSTIMER_SYSTIMER_INT2_CLR_M (SYSTIMER_SYSTIMER_INT2_CLR_V << SYSTIMER_SYSTIMER_INT2_CLR_S) +#define SYSTIMER_SYSTIMER_INT2_CLR_V 0x00000001 +#define SYSTIMER_SYSTIMER_INT2_CLR_S 2 /** SYSTIMER_DATE_REG register * system timer register version */ #define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) -/** SYSTIMER_DATE : R/W; bitpos: [32:0]; default: 25194848; +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 25194848; * system timer register version */ #define SYSTIMER_DATE 0xFFFFFFFF @@ -396,7 +377,6 @@ extern "C" { #define SYSTIMER_DATE_V 0xFFFFFFFF #define SYSTIMER_DATE_S 0 - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/include/soc/systimer_struct.h b/components/soc/esp32s2/include/soc/systimer_struct.h new file mode 100644 index 0000000000..48b1d79276 --- /dev/null +++ b/components/soc/esp32s2/include/soc/systimer_struct.h @@ -0,0 +1,330 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTEM TIMER REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** clk_fo : R/W; bitpos: [0]; default: 0; + * system timer force clock enable + */ + uint32_t clk_fo: 1; + uint32_t reserved_1: 30; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register clock enable + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + +/** Type of load register + * load value to system timer + */ +typedef union { + struct { + uint32_t reserved_0: 31; + /** timer_load : WO; bitpos: [31]; default: 0; + * load value to system timer + */ + uint32_t timer_load: 1; + }; + uint32_t val; +} systimer_load_reg_t; + +/** Type of load_hi register + * High 32-bit load to system timer + */ +typedef union { + struct { + /** timer_load_hi : R/W; bitpos: [31:0]; default: 0; + * High 32-bit load to system timer + */ + uint32_t timer_load_hi: 32; + }; + uint32_t val; +} systimer_load_hi_reg_t; + +/** Type of load_lo register + * Low 32-bit load to system timer + */ +typedef union { + struct { + /** timer_load_lo : R/W; bitpos: [31:0]; default: 0; + * Low 32-bit load to system timer + */ + uint32_t timer_load_lo: 32; + }; + uint32_t val; +} systimer_load_lo_reg_t; + +/** Type of step register + * system timer accumulation step + */ +typedef union { + struct { + /** timer_xtal_step : R/W; bitpos: [9:0]; default: 80; + * system timer accumulation step when using XTAL + */ + uint32_t timer_xtal_step: 10; + /** timer_pll_step : R/W; bitpos: [19:10]; default: 1; + * system timer accumulation step when using PLL + */ + uint32_t timer_pll_step: 10; + }; + uint32_t val; +} systimer_step_reg_t; + +/** Type of target_val register + * System timer target value + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [31:0]; default: 0; + * System timer target0 high 32-bit + */ + uint32_t timer_target_hi: 32; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * System timer target0 low 32-bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + +/** Type of target_conf register + * Configure system timer target work mode + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [29:0]; default: 0; + * System timer target alarm period + */ + uint32_t target_period: 30; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Whether system timer target work in period mode + */ + uint32_t target_period_mode: 1; + /** target_work_en : R/W; bitpos: [31]; default: 0; + * system timer target work enable + */ + uint32_t target_work_en: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + +/** Type of update register + * Read out system timer value + */ +typedef union { + struct { + uint32_t reserved_0: 30; + /** timer_value_valid : RO; bitpos: [30]; default: 0; + * If it is valid to read out timer value from register + */ + uint32_t timer_value_valid: 1; + /** timer_update : WO; bitpos: [31]; default: 0; + * Update system timer value to register + */ + uint32_t timer_update: 1; + }; + uint32_t val; +} systimer_update_reg_t; + +/** Type of value_hi register + * system timer high 32-bit + */ +typedef union { + struct { + /** timer_value_hi : RO; bitpos: [31:0]; default: 0; + * system timer high 32-bit + */ + uint32_t timer_value_hi: 32; + }; + uint32_t val; +} systimer_value_hi_reg_t; + +/** Type of value_lo register + * system timer low 32-bit + */ +typedef union { + struct { + /** timer_value_lo : RO; bitpos: [31:0]; default: 0; + * system timer low 32-bit + */ + uint32_t timer_value_lo: 32; + }; + uint32_t val; +} systimer_value_lo_reg_t; + +/** Type of int_ena register + * system timer interrupt enable + */ +typedef union { + struct { + /** systimer_int0_ena : R/W; bitpos: [0]; default: 0; + * system timer target0 interrupt enable + */ + uint32_t systimer_int0_ena: 1; + /** systimer_int1_ena : R/W; bitpos: [1]; default: 0; + * system timer target1 interrupt enable + */ + uint32_t systimer_int1_ena: 1; + /** systimer_int2_ena : R/W; bitpos: [2]; default: 0; + * system timer target2 interrupt enable + */ + uint32_t systimer_int2_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * system timer interrupt raw + */ +typedef union { + struct { + /** systimer_int0_raw : RO; bitpos: [0]; default: 0; + * system timer target0 interrupt raw + */ + uint32_t systimer_int0_raw: 1; + /** systimer_int1_raw : RO; bitpos: [1]; default: 0; + * system timer target1 interrupt raw + */ + uint32_t systimer_int1_raw: 1; + /** systimer_int2_raw : RO; bitpos: [2]; default: 0; + * system timer target2 interrupt raw + */ + uint32_t systimer_int2_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * system timer interrupt clear + */ +typedef union { + struct { + /** systimer_int0_clr : WO; bitpos: [0]; default: 0; + * system timer target0 interrupt clear + */ + uint32_t systimer_int0_clr: 1; + /** systimer_int1_clr : WO; bitpos: [1]; default: 0; + * system timer target1 interrupt clear + */ + uint32_t systimer_int1_clr: 1; + /** systimer_int2_clr : WO; bitpos: [2]; default: 0; + * system timer target2 interrupt clear + */ + uint32_t systimer_int2_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + + +/** DATE */ +/** Type of date register + * system timer register version + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 25194848; + * system timer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_load_reg_t load; + volatile systimer_load_hi_reg_t load_hi; + volatile systimer_load_lo_reg_t load_lo; + volatile systimer_step_reg_t step; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_update_reg_t update; + volatile systimer_value_hi_reg_t value_hi; + volatile systimer_value_lo_reg_t value_lo; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + uint32_t reserved_050; + uint32_t reserved_054; + uint32_t reserved_058; + uint32_t reserved_05c; + uint32_t reserved_060; + uint32_t reserved_064; + uint32_t reserved_068; + uint32_t reserved_06c; + uint32_t reserved_070; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 2583b13130..27568c92d2 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -77,7 +77,7 @@ #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 #define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SYSTIMER_BASE 0x60023000 #define DR_REG_SPI2_BASE 0x60024000 #define DR_REG_SPI3_BASE 0x60025000 #define DR_REG_SYSCON_BASE 0x60026000 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index ba177fa275..659b51505a 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -103,7 +103,13 @@ #define SOC_SPIRAM_SUPPORTED 1 /*-------------------------- SYS TIMER CAPS ----------------------------------*/ -#include "systimer_caps.h" +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) /*-------------------------- TIMER GROUP CAPS --------------------------------*/ #define SOC_TIMER_GROUPS (2) diff --git a/components/soc/esp32s3/include/soc/sys_timer_reg.h b/components/soc/esp32s3/include/soc/sys_timer_reg.h deleted file mode 100644 index 55c1802312..0000000000 --- a/components/soc/esp32s3/include/soc/sys_timer_reg.h +++ /dev/null @@ -1,474 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_REG_H_ -#define _SOC_SYS_TIMER_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" - -#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0) -/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: register file clk gating.*/ -#define SYS_TIMER_CLK_EN (BIT(31)) -#define SYS_TIMER_CLK_EN_M (BIT(31)) -#define SYS_TIMER_CLK_EN_V 0x1 -#define SYS_TIMER_CLK_EN_S 31 -/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: timer unit0 work enable.*/ -#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 -/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer unit1 work enable.*/ -#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 -/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core0 stalled.*/ -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 -/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: If timer unit0 is stalled when core1 stalled.*/ -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 -/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core0 stalled.*/ -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 -/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: If timer unit1 is stalled when core1 stalled.*/ -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 -/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: target0 work enable.*/ -#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) -#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET0_WORK_EN_S 24 -/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: target1 work enable.*/ -#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) -#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET1_WORK_EN_S 23 -/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: target2 work enable.*/ -#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) -#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 -#define SYS_TIMER_TARGET2_WORK_EN_S 22 -/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: systimer clock force on.*/ -#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) -#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 -#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x4) -/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer_unit0.*/ -#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 - -#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x8) -/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: update timer unit1.*/ -#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) -#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 -/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: timer value is sync and valid.*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 - -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0xC) -/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit0 load high 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x10) -/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit0 load low 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x14) -/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer unit1 load high 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x18) -/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer unit1 load low 32 bit.*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x1C) -/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget0 high 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S)) -#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET0_HI_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x20) -/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget0 low 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S)) -#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET0_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x24) -/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget1 high 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S)) -#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET1_HI_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x28) -/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget1 low 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S)) -#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET1_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x2C) -/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer taget2 high 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S)) -#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_TARGET2_HI_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x30) -/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer taget2 low 32 bit.*/ -#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S)) -#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_TARGET2_LO_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x34) -/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target0 to period mode.*/ -#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target0 period.*/ -#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S)) -#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET0_PERIOD_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x38) -/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target1 to period mode.*/ -#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target1 period.*/ -#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S)) -#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET1_PERIOD_S 0 - -#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x3C) -/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: select which unit to compare.*/ -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 -#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 -/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set target2 to period mode.*/ -#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) -#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 -#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 -/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: target2 period.*/ -#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S)) -#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF -#define SYS_TIMER_TARGET2_PERIOD_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x40) -/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit.*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x44) -/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit.*/ -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x48) -/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: timer read value high 32bit.*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x4C) -/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: timer read value low 32bit.*/ -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF -#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 - -#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x50) -/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp0 load value.*/ -#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x54) -/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp1 load value.*/ -#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x58) -/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer comp2 load value.*/ -#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 -#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x5C) -/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit0 load value.*/ -#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x60) -/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: timer unit1 load value.*/ -#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) -#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 -#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 - -#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x64) -/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 enable.*/ -#define SYS_TIMER_TARGET2_INT_ENA (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET2_INT_ENA_S 2 -/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 enable.*/ -#define SYS_TIMER_TARGET1_INT_ENA (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET1_INT_ENA_S 1 -/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 enable.*/ -#define SYS_TIMER_TARGET0_INT_ENA (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ENA_V 0x1 -#define SYS_TIMER_TARGET0_INT_ENA_S 0 - -#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x68) -/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 raw.*/ -#define SYS_TIMER_TARGET2_INT_RAW (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET2_INT_RAW_S 2 -/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 raw.*/ -#define SYS_TIMER_TARGET1_INT_RAW (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET1_INT_RAW_S 1 -/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 raw.*/ -#define SYS_TIMER_TARGET0_INT_RAW (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_RAW_V 0x1 -#define SYS_TIMER_TARGET0_INT_RAW_S 0 - -#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x6C) -/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: interupt2 clear.*/ -#define SYS_TIMER_TARGET2_INT_CLR (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET2_INT_CLR_S 2 -/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: interupt1 clear.*/ -#define SYS_TIMER_TARGET1_INT_CLR (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET1_INT_CLR_S 1 -/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: interupt0 clear.*/ -#define SYS_TIMER_TARGET0_INT_CLR (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_CLR_V 0x1 -#define SYS_TIMER_TARGET0_INT_CLR_S 0 - -#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x70) -/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET2_INT_ST (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2)) -#define SYS_TIMER_TARGET2_INT_ST_V 0x1 -#define SYS_TIMER_TARGET2_INT_ST_S 2 -/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET1_INT_ST (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1)) -#define SYS_TIMER_TARGET1_INT_ST_V 0x1 -#define SYS_TIMER_TARGET1_INT_ST_S 1 -/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET0_INT_ST (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0)) -#define SYS_TIMER_TARGET0_INT_ST_V 0x1 -#define SYS_TIMER_TARGET0_INT_ST_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x74) -/* SYS_TIMER_TARGET0_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET0_LO_RO 0xFFFFFFFF -#define SYS_TIMER_TARGET0_LO_RO_M ((SYS_TIMER_TARGET0_LO_RO_V)<<(SYS_TIMER_TARGET0_LO_RO_S)) -#define SYS_TIMER_TARGET0_LO_RO_V 0xFFFFFFFF -#define SYS_TIMER_TARGET0_LO_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x78) -/* SYS_TIMER_TARGET0_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET0_HI_RO 0x000FFFFF -#define SYS_TIMER_TARGET0_HI_RO_M ((SYS_TIMER_TARGET0_HI_RO_V)<<(SYS_TIMER_TARGET0_HI_RO_S)) -#define SYS_TIMER_TARGET0_HI_RO_V 0xFFFFF -#define SYS_TIMER_TARGET0_HI_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x7C) -/* SYS_TIMER_TARGET1_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET1_LO_RO 0xFFFFFFFF -#define SYS_TIMER_TARGET1_LO_RO_M ((SYS_TIMER_TARGET1_LO_RO_V)<<(SYS_TIMER_TARGET1_LO_RO_S)) -#define SYS_TIMER_TARGET1_LO_RO_V 0xFFFFFFFF -#define SYS_TIMER_TARGET1_LO_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x80) -/* SYS_TIMER_TARGET1_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET1_HI_RO 0x000FFFFF -#define SYS_TIMER_TARGET1_HI_RO_M ((SYS_TIMER_TARGET1_HI_RO_V)<<(SYS_TIMER_TARGET1_HI_RO_S)) -#define SYS_TIMER_TARGET1_HI_RO_V 0xFFFFF -#define SYS_TIMER_TARGET1_HI_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x84) -/* SYS_TIMER_TARGET2_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET2_LO_RO 0xFFFFFFFF -#define SYS_TIMER_TARGET2_LO_RO_M ((SYS_TIMER_TARGET2_LO_RO_V)<<(SYS_TIMER_TARGET2_LO_RO_S)) -#define SYS_TIMER_TARGET2_LO_RO_V 0xFFFFFFFF -#define SYS_TIMER_TARGET2_LO_RO_S 0 - -#define SYS_TIMER_SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x88) -/* SYS_TIMER_TARGET2_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */ -/*description: .*/ -#define SYS_TIMER_TARGET2_HI_RO 0x000FFFFF -#define SYS_TIMER_TARGET2_HI_RO_M ((SYS_TIMER_TARGET2_HI_RO_V)<<(SYS_TIMER_TARGET2_HI_RO_S)) -#define SYS_TIMER_TARGET2_HI_RO_V 0xFFFFF -#define SYS_TIMER_TARGET2_HI_RO_S 0 - -#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0xFC) -/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */ -/*description: .*/ -#define SYS_TIMER_DATE 0xFFFFFFFF -#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S)) -#define SYS_TIMER_DATE_V 0xFFFFFFFF -#define SYS_TIMER_DATE_S 0 - - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SYS_TIMER_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/sys_timer_struct.h b/components/soc/esp32s3/include/soc/sys_timer_struct.h deleted file mode 100644 index 1641f7e44c..0000000000 --- a/components/soc/esp32s3/include/soc/sys_timer_struct.h +++ /dev/null @@ -1,271 +0,0 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SYS_TIMER_STRUCT_H_ -#define _SOC_SYS_TIMER_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include - -typedef volatile struct { - union { - struct { - uint32_t systimer_clk_fo : 1; /*systimer clock force on*/ - uint32_t reserved1 : 21; - uint32_t target2_work_en : 1; /*target2 work enable*/ - uint32_t target1_work_en : 1; /*target1 work enable*/ - uint32_t target0_work_en : 1; /*target0 work enable*/ - uint32_t timer_unit1_core1_stall_en : 1; /*If timer unit1 is stalled when core1 stalled*/ - uint32_t timer_unit1_core0_stall_en : 1; /*If timer unit1 is stalled when core0 stalled*/ - uint32_t timer_unit0_core1_stall_en : 1; /*If timer unit0 is stalled when core1 stalled*/ - uint32_t timer_unit0_core0_stall_en : 1; /*If timer unit0 is stalled when core0 stalled*/ - uint32_t timer_unit1_work_en : 1; /*timer unit1 work enable*/ - uint32_t timer_unit0_work_en : 1; /*timer unit0 work enable*/ - uint32_t clk_en : 1; /*register file clk gating*/ - }; - uint32_t val; - } systimer_conf; - union { - struct { - uint32_t reserved0 : 29; - uint32_t timer_unit0_value_valid : 1; - uint32_t timer_unit0_update : 1; /*update timer_unit0*/ - uint32_t reserved31 : 1; - }; - uint32_t val; - } systimer_unit0_op; - union { - struct { - uint32_t reserved0 : 29; - uint32_t timer_unit1_value_valid : 1; /*timer value is sync and valid*/ - uint32_t timer_unit1_update : 1; /*update timer unit1*/ - uint32_t reserved31 : 1; - }; - uint32_t val; - } systimer_unit1_op; - union { - struct { - uint32_t timer_unit0_load_hi : 20; /*timer unit0 load high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit0_load_hi; - uint32_t systimer_unit0_load_lo; - union { - struct { - uint32_t timer_unit1_load_hi : 20; /*timer unit1 load high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit1_load_hi; - uint32_t systimer_unit1_load_lo; - union { - struct { - uint32_t timer_target0_hi : 20; /*timer taget0 high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_target0_hi; - uint32_t systimer_target0_lo; - union { - struct { - uint32_t timer_target1_hi : 20; /*timer taget1 high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_target1_hi; - uint32_t systimer_target1_lo; - union { - struct { - uint32_t timer_target2_hi : 20; /*timer taget2 high 32 bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_target2_hi; - uint32_t systimer_target2_lo; - union { - struct { - uint32_t target0_period : 26; /*target0 period*/ - uint32_t reserved26 : 4; - uint32_t target0_period_mode : 1; /*Set target0 to period mode*/ - uint32_t target0_timer_unit_sel : 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target0_conf; - union { - struct { - uint32_t target1_period : 26; /*target1 period*/ - uint32_t reserved26 : 4; - uint32_t target1_period_mode : 1; /*Set target1 to period mode*/ - uint32_t target1_timer_unit_sel : 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target1_conf; - union { - struct { - uint32_t target2_period : 26; /*target2 period*/ - uint32_t reserved26 : 4; - uint32_t target2_period_mode : 1; /*Set target2 to period mode*/ - uint32_t target2_timer_unit_sel : 1; /*select which unit to compare*/ - }; - uint32_t val; - } systimer_target2_conf; - union { - struct { - uint32_t timer_unit0_value_hi : 20; /*timer read value high 32bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit0_value_hi; - uint32_t systimer_unit0_value_lo; - union { - struct { - uint32_t timer_unit1_value_hi : 20; /*timer read value high 32bit*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_unit1_value_hi; - uint32_t systimer_unit1_value_lo; - union { - struct { - uint32_t timer_comp0_load : 1; /*timer comp0 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_comp0_load; - union { - struct { - uint32_t timer_comp1_load : 1; /*timer comp1 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_comp1_load; - union { - struct { - uint32_t timer_comp2_load : 1; /*timer comp2 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_comp2_load; - union { - struct { - uint32_t timer_unit0_load : 1; /*timer unit0 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_unit0_load; - union { - struct { - uint32_t timer_unit1_load : 1; /*timer unit1 load value*/ - uint32_t reserved1 : 31; - }; - uint32_t val; - } systimer_unit1_load; - union { - struct { - uint32_t target0 : 1; /*interupt0 enable*/ - uint32_t target1 : 1; /*interupt1 enable*/ - uint32_t target2 : 1; /*interupt2 enable*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_ena; - union { - struct { - uint32_t target0 : 1; /*interupt0 raw*/ - uint32_t target1 : 1; /*interupt1 raw*/ - uint32_t target2 : 1; /*interupt2 raw*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_raw; - union { - struct { - uint32_t target0 : 1; /*interupt0 clear*/ - uint32_t target1 : 1; /*interupt1 clear*/ - uint32_t target2 : 1; /*interupt2 clear*/ - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_clr; - union { - struct { - uint32_t target0 : 1; - uint32_t target1 : 1; - uint32_t target2 : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } systimer_int_st; - uint32_t systimer_real_target0_lo; - union { - struct { - uint32_t target0_hi_ro : 20; - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_real_target0_hi; - uint32_t systimer_real_target1_lo; - union { - struct { - uint32_t target1_hi_ro : 20; - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_real_target1_hi; - uint32_t systimer_real_target2_lo; - union { - struct { - uint32_t target2_hi_ro : 20; - uint32_t reserved20 : 12; - }; - uint32_t val; - } systimer_real_target2_hi; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t systimer_date; -} sys_timer_dev_t; -extern sys_timer_dev_t SYS_TIMER; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_SYS_TIMER_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/systimer_caps.h b/components/soc/esp32s3/include/soc/systimer_caps.h deleted file mode 100644 index 37683122ba..0000000000 --- a/components/soc/esp32s3/include/soc/systimer_caps.h +++ /dev/null @@ -1,22 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units - -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt diff --git a/components/soc/esp32s3/include/soc/systimer_reg.h b/components/soc/esp32s3/include/soc/systimer_reg.h new file mode 100644 index 0000000000..869012065b --- /dev/null +++ b/components/soc/esp32s3/include/soc/systimer_reg.h @@ -0,0 +1,639 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTIMER_CONF_REG register + * Configure system timer clock + */ +#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) +/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ +#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) +#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 +#define SYSTIMER_SYSTIMER_CLK_FO_S 0 +/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ +#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) +#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) +#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET2_WORK_EN_S 22 +/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ +#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) +#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) +#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET1_WORK_EN_S 23 +/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ +#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) +#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) +#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 +#define SYSTIMER_TARGET0_WORK_EN_S 24 +/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ +#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 +/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ +#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) +#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 +/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ +#define SYSTIMER_CLK_EN (BIT(31)) +#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) +#define SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTIMER_CLK_EN_S 31 + +/** SYSTIMER_UNIT0_OP_REG register + * system timer unit0 value update register + */ +#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) +/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ +#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) +#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 + +/** SYSTIMER_UNIT1_OP_REG register + * system timer unit1 value update register + */ +#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) +/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; + * timer value is sync and valid + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 +/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; + * update timer unit1 + */ +#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) +#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 + +/** SYSTIMER_UNIT0_LOAD_HI_REG register + * system timer unit0 value high load register + */ +#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) +/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit0 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 + +/** SYSTIMER_UNIT0_LOAD_LO_REG register + * system timer unit0 value low load register + */ +#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) +/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit0 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 + +/** SYSTIMER_UNIT1_LOAD_HI_REG register + * system timer unit1 value high load register + */ +#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) +/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; + * timer unit1 load high 20 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 + +/** SYSTIMER_UNIT1_LOAD_LO_REG register + * system timer unit1 value low load register + */ +#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) +/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * timer unit1 load low 32 bits + */ +#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 + +/** SYSTIMER_TARGET0_HI_REG register + * system timer comp0 value high register + */ +#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) +/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget0 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) +#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET0_HI_S 0 + +/** SYSTIMER_TARGET0_LO_REG register + * system timer comp0 value low register + */ +#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) +/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget0 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) +#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET0_LO_S 0 + +/** SYSTIMER_TARGET1_HI_REG register + * system timer comp1 value high register + */ +#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) +/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget1 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) +#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET1_HI_S 0 + +/** SYSTIMER_TARGET1_LO_REG register + * system timer comp1 value low register + */ +#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) +/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget1 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) +#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET1_LO_S 0 + +/** SYSTIMER_TARGET2_HI_REG register + * system timer comp2 value high register + */ +#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) +/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; + * timer taget2 high 20 bits + */ +#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) +#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_TARGET2_HI_S 0 + +/** SYSTIMER_TARGET2_LO_REG register + * system timer comp2 value low register + */ +#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) +/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; + * timer taget2 low 32 bits + */ +#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) +#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_TARGET2_LO_S 0 + +/** SYSTIMER_TARGET0_CONF_REG register + * system timer comp0 target mode register + */ +#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) +/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target0 period + */ +#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) +#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET0_PERIOD_S 0 +/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target0 to period mode + */ +#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) +#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET1_CONF_REG register + * system timer comp1 target mode register + */ +#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) +/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target1 period + */ +#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) +#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET1_PERIOD_S 0 +/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target1 to period mode + */ +#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) +#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_TARGET2_CONF_REG register + * system timer comp2 target mode register + */ +#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) +/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; + * target2 period + */ +#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) +#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF +#define SYSTIMER_TARGET2_PERIOD_S 0 +/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; + * Set target2 to period mode + */ +#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) +#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 +#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 +/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 +#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 + +/** SYSTIMER_UNIT0_VALUE_HI_REG register + * system timer unit0 value high register + */ +#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) +/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 + +/** SYSTIMER_UNIT0_VALUE_LO_REG register + * system timer unit0 value low register + */ +#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) +/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 + +/** SYSTIMER_UNIT1_VALUE_HI_REG register + * system timer unit1 value high register + */ +#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) +/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 + +/** SYSTIMER_UNIT1_VALUE_LO_REG register + * system timer unit1 value low register + */ +#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) +/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bits + */ +#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 + +/** SYSTIMER_COMP0_LOAD_REG register + * system timer comp0 conf sync register + */ +#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) +/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; + * timer comp0 sync enable signal + */ +#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) +#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP0_LOAD_S 0 + +/** SYSTIMER_COMP1_LOAD_REG register + * system timer comp1 conf sync register + */ +#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) +/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; + * timer comp1 sync enable signal + */ +#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) +#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP1_LOAD_S 0 + +/** SYSTIMER_COMP2_LOAD_REG register + * system timer comp2 conf sync register + */ +#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) +/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; + * timer comp2 sync enable signal + */ +#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) +#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_COMP2_LOAD_S 0 + +/** SYSTIMER_UNIT0_LOAD_REG register + * system timer unit0 conf sync register + */ +#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) +/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; + * timer unit0 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) +#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 + +/** SYSTIMER_UNIT1_LOAD_REG register + * system timer unit1 conf sync register + */ +#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) +/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; + * timer unit1 sync enable signal + */ +#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) +#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 +#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 + +/** SYSTIMER_INT_ENA_REG register + * systimer interrupt enable register + */ +#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) +/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ +#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) +#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) +#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ENA_S 0 +/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ +#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) +#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) +#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ENA_S 1 +/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ +#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) +#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) +#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ENA_S 2 + +/** SYSTIMER_INT_RAW_REG register + * systimer interrupt raw register + */ +#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) +/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ +#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) +#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) +#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET0_INT_RAW_S 0 +/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ +#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) +#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) +#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET1_INT_RAW_S 1 +/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ +#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) +#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) +#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 +#define SYSTIMER_TARGET2_INT_RAW_S 2 + +/** SYSTIMER_INT_CLR_REG register + * systimer interrupt clear register + */ +#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) +/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ +#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) +#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) +#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET0_INT_CLR_S 0 +/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ +#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) +#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) +#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET1_INT_CLR_S 1 +/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ +#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) +#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) +#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 +#define SYSTIMER_TARGET2_INT_CLR_S 2 + +/** SYSTIMER_INT_ST_REG register + * systimer interrupt status register + */ +#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) +/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; + * interupt0 status + */ +#define SYSTIMER_TARGET0_INT_ST (BIT(0)) +#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) +#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET0_INT_ST_S 0 +/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; + * interupt1 status + */ +#define SYSTIMER_TARGET1_INT_ST (BIT(1)) +#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) +#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET1_INT_ST_S 1 +/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; + * interupt2 status + */ +#define SYSTIMER_TARGET2_INT_ST (BIT(2)) +#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) +#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 +#define SYSTIMER_TARGET2_INT_ST_S 2 + +/** SYSTIMER_REAL_TARGET0_LO_REG register + * system timer comp0 actual target value low register + */ +#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) +/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFF +#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) +#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFF +#define SYSTIMER_TARGET0_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET0_HI_REG register + * system timer comp0 actual target value high register + */ +#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) +/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET0_HI_RO 0x000FFFFF +#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) +#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFF +#define SYSTIMER_TARGET0_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_LO_REG register + * system timer comp1 actual target value low register + */ +#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) +/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFF +#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) +#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFF +#define SYSTIMER_TARGET1_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET1_HI_REG register + * system timer comp1 actual target value high register + */ +#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) +/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET1_HI_RO 0x000FFFFF +#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) +#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFF +#define SYSTIMER_TARGET1_HI_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_LO_REG register + * system timer comp2 actual target value low register + */ +#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) +/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ +#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFF +#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) +#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFF +#define SYSTIMER_TARGET2_LO_RO_S 0 + +/** SYSTIMER_REAL_TARGET2_HI_REG register + * system timer comp2 actual target value high register + */ +#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) +/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ +#define SYSTIMER_TARGET2_HI_RO 0x000FFFFF +#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) +#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFF +#define SYSTIMER_TARGET2_HI_RO_S 0 + +/** SYSTIMER_DATE_REG register + * system timer version control register + */ +#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) +/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753; + * systimer register version + */ +#define SYSTIMER_DATE 0xFFFFFFFF +#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) +#define SYSTIMER_DATE_V 0xFFFFFFFF +#define SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/systimer_struct.h b/components/soc/esp32s3/include/soc/systimer_struct.h new file mode 100644 index 0000000000..30d3f7e7d5 --- /dev/null +++ b/components/soc/esp32s3/include/soc/systimer_struct.h @@ -0,0 +1,397 @@ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** SYSTEM TIMER CLK CONTROL REGISTER */ +/** Type of conf register + * Configure system timer clock + */ +typedef union { + struct { + /** systimer_clk_fo : R/W; bitpos: [0]; default: 0; + * systimer clock force on + */ + uint32_t systimer_clk_fo: 1; + uint32_t reserved_1: 21; + /** target2_work_en : R/W; bitpos: [22]; default: 0; + * target2 work enable + */ + uint32_t target2_work_en: 1; + /** target1_work_en : R/W; bitpos: [23]; default: 0; + * target1 work enable + */ + uint32_t target1_work_en: 1; + /** target0_work_en : R/W; bitpos: [24]; default: 0; + * target0 work enable + */ + uint32_t target0_work_en: 1; + /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1; + * If timer unit1 is stalled when core1 stalled + */ + uint32_t timer_unit1_core1_stall_en: 1; + /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1; + * If timer unit1 is stalled when core0 stalled + */ + uint32_t timer_unit1_core0_stall_en: 1; + /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0; + * If timer unit0 is stalled when core1 stalled + */ + uint32_t timer_unit0_core1_stall_en: 1; + /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0; + * If timer unit0 is stalled when core0 stalled + */ + uint32_t timer_unit0_core0_stall_en: 1; + /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0; + * timer unit1 work enable + */ + uint32_t timer_unit1_work_en: 1; + /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1; + * timer unit0 work enable + */ + uint32_t timer_unit0_work_en: 1; + /** clk_en : R/W; bitpos: [31]; default: 0; + * register file clk gating + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} systimer_conf_reg_t; + + +/** Type of unit_op register + * SYSTIMER_UNIT_OP. + */ +typedef union { + struct { + uint32_t reserved_0: 29; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + * reg_timer_unit0_value_valid + */ + uint32_t timer_unit_value_valid: 1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; + * update timer_unit0 + */ + uint32_t timer_unit_update: 1; + }; + uint32_t val; +} systimer_unit_op_reg_t; + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD + */ +typedef struct { + union { + struct { + /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0; + * timer unit load high 32 bit + */ + uint32_t timer_unit_load_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bit + */ + uint32_t timer_unit_load_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_load_val_reg_t; + + +/** Type of target register + * SYSTIMER_TARGET. + */ +typedef struct { + union { + struct { + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; + * timer target high 32 bit + */ + uint32_t timer_target_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bit + */ + uint32_t timer_target_lo: 32; + }; + uint32_t val; + } lo; +} systimer_target_val_reg_t; + + +/** Type of target_conf register + * SYSTIMER_TARGET_CONF. + */ +typedef union { + struct { + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period + */ + uint32_t target_period: 26; + uint32_t reserved_26: 4; + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode + */ + uint32_t target_period_mode: 1; + /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0; + * select which unit to compare + */ + uint32_t target_timer_unit_sel: 1; + }; + uint32_t val; +} systimer_target_conf_reg_t; + + +/** Type of unit_value_hi register + * SYSTIMER_UNIT_VALUE_HI. + */ +typedef struct { + union { + struct { + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; + * timer read value high 20bit + */ + uint32_t timer_unit_value_hi: 20; + }; + uint32_t val; + } hi; + union { + struct { + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; + * timer read value low 32bit + */ + uint32_t timer_unit_value_lo: 32; + }; + uint32_t val; + } lo; +} systimer_unit_value_reg_t; + + +/** Type of comp_load register + * SYSTIMER_COMP_LOAD. + */ +typedef union { + struct { + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp load value + */ + uint32_t timer_comp_load: 1; + }; + uint32_t val; +} systimer_comp_load_reg_t; + + +/** Type of unit_load register + * SYSTIMER_UNIT_LOAD. + */ +typedef union { + struct { + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit load value + */ + uint32_t timer_unit_load: 1; + }; + uint32_t val; +} systimer_unit_load_reg_t; + + +/** SYSTEM TIMER INTERRUPT REGISTER */ +/** Type of int_ena register + * systimer interrupt enable register + */ +typedef union { + struct { + /** target0_int_ena : R/W; bitpos: [0]; default: 0; + * interupt0 enable + */ + uint32_t target0_int_ena: 1; + /** target1_int_ena : R/W; bitpos: [1]; default: 0; + * interupt1 enable + */ + uint32_t target1_int_ena: 1; + /** target2_int_ena : R/W; bitpos: [2]; default: 0; + * interupt2 enable + */ + uint32_t target2_int_ena: 1; + }; + uint32_t val; +} systimer_int_ena_reg_t; + +/** Type of int_raw register + * systimer interrupt raw register + */ +typedef union { + struct { + /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * interupt0 raw + */ + uint32_t target0_int_raw: 1; + /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * interupt1 raw + */ + uint32_t target1_int_raw: 1; + /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * interupt2 raw + */ + uint32_t target2_int_raw: 1; + }; + uint32_t val; +} systimer_int_raw_reg_t; + +/** Type of int_clr register + * systimer interrupt clear register + */ +typedef union { + struct { + /** target0_int_clr : WT; bitpos: [0]; default: 0; + * interupt0 clear + */ + uint32_t target0_int_clr: 1; + /** target1_int_clr : WT; bitpos: [1]; default: 0; + * interupt1 clear + */ + uint32_t target1_int_clr: 1; + /** target2_int_clr : WT; bitpos: [2]; default: 0; + * interupt2 clear + */ + uint32_t target2_int_clr: 1; + }; + uint32_t val; +} systimer_int_clr_reg_t; + +/** Type of int_st register + * systimer interrupt status register + */ +typedef union { + struct { + /** target0_int_st : RO; bitpos: [0]; default: 0; + * interupt0 status + */ + uint32_t target0_int_st: 1; + /** target1_int_st : RO; bitpos: [1]; default: 0; + * interupt1 status + */ + uint32_t target1_int_st: 1; + /** target2_int_st : RO; bitpos: [2]; default: 0; + * interupt2 status + */ + uint32_t target2_int_st: 1; + }; + uint32_t val; +} systimer_int_st_reg_t; + + +/** SYSTEM TIMER COMP STATUS REGISTER + * systimer comp actual target value low register + */ +typedef struct { + union { + struct { + /** target_lo_ro : RO; bitpos: [31:0]; default: 0; + * actual target value value low 32bits + */ + uint32_t target_lo_ro: 32; + }; + uint32_t val; + } lo; + union { + struct { + /** target_hi_ro : RO; bitpos: [19:0]; default: 0; + * actual target value value high 20bits + */ + uint32_t target_hi_ro: 20; + }; + uint32_t val; + } hi; +} systimer_real_target_val_reg_t; + + +/** VERSION REGISTER */ +/** Type of date register + * system timer version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 33628753; + * systimer register version + */ + uint32_t date: 32; + }; + uint32_t val; +} systimer_date_reg_t; + + +typedef struct { + volatile systimer_conf_reg_t conf; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; + volatile systimer_int_ena_reg_t int_ena; + volatile systimer_int_raw_reg_t int_raw; + volatile systimer_int_clr_reg_t int_clr; + volatile systimer_int_st_reg_t int_st; + volatile systimer_real_target_val_reg_t real_target_val[3]; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile systimer_date_reg_t date; +} systimer_dev_t; + +extern systimer_dev_t SYSTIMER; + +#ifdef __cplusplus +} +#endif From ec898b771eb9c0c2991348198a8c86b5b69b4b46 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 2 Apr 2021 12:41:21 +0800 Subject: [PATCH 3/3] systimer: strip hal driver --- .../esp_timer/src/esp_timer_impl_systimer.c | 47 +++-- components/freertos/port/riscv/port.c | 29 +-- components/hal/CMakeLists.txt | 12 +- components/hal/component.mk | 2 +- .../hal/esp32c3/include/hal/systimer_ll.h | 135 +++++++------ components/hal/esp32c3/systimer_hal.c | 128 ------------ .../hal/esp32s2/include/hal/systimer_ll.h | 138 ++++++++----- components/hal/esp32s2/systimer_hal.c | 148 -------------- .../hal/esp32s3/include/hal/systimer_ll.h | 138 +++++++------ components/hal/esp32s3/systimer_hal.c | 123 ------------ components/hal/include/hal/systimer_hal.h | 125 ++++++------ components/hal/systimer_hal.c | 188 ++++++++++++++++++ 12 files changed, 541 insertions(+), 672 deletions(-) delete mode 100644 components/hal/esp32c3/systimer_hal.c delete mode 100644 components/hal/esp32s2/systimer_hal.c delete mode 100644 components/hal/esp32s3/systimer_hal.c create mode 100644 components/hal/systimer_hal.c diff --git a/components/esp_timer/src/esp_timer_impl_systimer.c b/components/esp_timer/src/esp_timer_impl_systimer.c index f67ea1a0a6..19c963110b 100644 --- a/components/esp_timer/src/esp_timer_impl_systimer.c +++ b/components/esp_timer/src/esp_timer_impl_systimer.c @@ -19,7 +19,10 @@ #include "esp_attr.h" #include "esp_intr_alloc.h" #include "esp_log.h" +#include "esp_compiler.h" #include "soc/periph_defs.h" +#include "soc/soc_caps.h" +#include "soc/rtc.h" #include "freertos/FreeRTOS.h" #include "hal/systimer_ll.h" #include "hal/systimer_types.h" @@ -46,6 +49,9 @@ static intr_handle_t s_timer_interrupt_handle; */ static intr_handler_t s_alarm_handler = NULL; +/* Systimer HAL layer object */ +static systimer_hal_context_t systimer_hal; + /* Spinlock used to protect access to the hardware registers. */ portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED; @@ -61,15 +67,15 @@ void esp_timer_impl_unlock(void) uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void) { - return systimer_hal_get_counter_value(SYSTIMER_COUNTER_0); + return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK); } int64_t IRAM_ATTR esp_timer_impl_get_time(void) { - if (s_alarm_handler == NULL) { + if (unlikely(s_alarm_handler == NULL)) { return 0; } - return systimer_hal_get_time(SYSTIMER_COUNTER_0); + return systimer_hal_get_time(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK); } int64_t esp_timer_get_time(void) __attribute__((alias("esp_timer_impl_get_time"))); @@ -81,7 +87,7 @@ void IRAM_ATTR esp_timer_impl_set_alarm_id(uint64_t timestamp, unsigned alarm_id timestamp_id[alarm_id] = timestamp; timestamp = MIN(timestamp_id[0], timestamp_id[1]); if (timestamp != UINT64_MAX) { - systimer_hal_set_alarm_target(SYSTIMER_ALARM_2, timestamp); + systimer_hal_set_alarm_target(&systimer_hal, SYSTIMER_LL_ALARM_CLOCK, timestamp); } portEXIT_CRITICAL_SAFE(&s_time_update_lock); } @@ -94,20 +100,22 @@ void IRAM_ATTR esp_timer_impl_set_alarm(uint64_t timestamp) static void IRAM_ATTR timer_alarm_isr(void *arg) { // clear the interrupt - systimer_ll_clear_alarm_int(SYSTIMER_ALARM_2); + systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_CLOCK); /* Call the upper layer handler */ (*s_alarm_handler)(arg); } void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us) { - systimer_hal_on_apb_freq_update(apb_ticks_per_us); +#if !SOC_SYSTIMER_FIXED_TICKS_US + systimer_hal_on_apb_freq_update(&systimer_hal, apb_ticks_per_us); +#endif } void esp_timer_impl_advance(int64_t time_us) { portENTER_CRITICAL_SAFE(&s_time_update_lock); - systimer_hal_counter_value_advance(SYSTIMER_COUNTER_0, time_us); + systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK, time_us); portEXIT_CRITICAL_SAFE(&s_time_update_lock); } @@ -129,16 +137,21 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler) goto err_intr_alloc; } - systimer_hal_init(); - systimer_hal_enable_counter(SYSTIMER_COUNTER_0); - systimer_hal_select_alarm_mode(SYSTIMER_ALARM_2, SYSTIMER_ALARM_MODE_ONESHOT); - systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_2, SYSTIMER_COUNTER_0); + systimer_hal_init(&systimer_hal); +#if !SOC_SYSTIMER_FIXED_TICKS_US + assert(rtc_clk_xtal_freq_get() == 40 && "update the step for xtal to support other XTAL:APB frequency ratios"); + systimer_hal_set_steps_per_tick(&systimer_hal, 0, 2); // for xtal + systimer_hal_set_steps_per_tick(&systimer_hal, 1, 1); // for pll +#endif + systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK); + systimer_hal_select_alarm_mode(&systimer_hal, SYSTIMER_LL_ALARM_CLOCK, SYSTIMER_ALARM_MODE_ONESHOT); + systimer_hal_connect_alarm_counter(&systimer_hal, SYSTIMER_LL_ALARM_CLOCK, SYSTIMER_LL_COUNTER_CLOCK); /* TODO: if SYSTIMER is used for anything else, access to SYSTIMER_INT_ENA_REG has to be * protected by a shared spinlock. Since this code runs as part of early startup, this * is practically not an issue. */ - systimer_hal_enable_alarm_int(SYSTIMER_ALARM_2); + systimer_hal_enable_alarm_int(&systimer_hal, SYSTIMER_LL_ALARM_CLOCK); err = esp_intr_enable(s_timer_interrupt_handle); if (err != ESP_OK) { @@ -148,9 +161,9 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler) return ESP_OK; err_intr_en: - systimer_ll_disable_alarm(SYSTIMER_ALARM_2); + systimer_ll_enable_alarm(systimer_hal.dev, SYSTIMER_LL_ALARM_CLOCK, false); /* TODO: may need a spinlock, see the note related to SYSTIMER_INT_ENA_REG in systimer_hal_init */ - systimer_ll_disable_alarm_int(SYSTIMER_ALARM_2); + systimer_ll_enable_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_CLOCK, false); esp_intr_free(s_timer_interrupt_handle); err_intr_alloc: s_alarm_handler = NULL; @@ -160,9 +173,9 @@ err_intr_alloc: void esp_timer_impl_deinit(void) { esp_intr_disable(s_timer_interrupt_handle); - systimer_ll_disable_alarm(SYSTIMER_ALARM_2); + systimer_ll_enable_alarm(systimer_hal.dev, SYSTIMER_LL_ALARM_CLOCK, false); /* TODO: may need a spinlock, see the note related to SYSTIMER_INT_ENA_REG in systimer_hal_init */ - systimer_ll_disable_alarm_int(SYSTIMER_ALARM_2); + systimer_ll_enable_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_CLOCK, false); esp_intr_free(s_timer_interrupt_handle); s_timer_interrupt_handle = NULL; s_alarm_handler = NULL; @@ -176,7 +189,7 @@ uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void) uint64_t esp_timer_impl_get_alarm_reg(void) { portENTER_CRITICAL_SAFE(&s_time_update_lock); - uint64_t val = systimer_hal_get_alarm_value(SYSTIMER_ALARM_2); + uint64_t val = systimer_hal_get_alarm_value(&systimer_hal, SYSTIMER_LL_ALARM_CLOCK); portEXIT_CRITICAL_SAFE(&s_time_update_lock); return val; } diff --git a/components/freertos/port/riscv/port.c b/components/freertos/port/riscv/port.c index 0ea7ce0d33..1af1eb8a82 100644 --- a/components/freertos/port/riscv/port.c +++ b/components/freertos/port/riscv/port.c @@ -147,17 +147,19 @@ void vPortExitCritical(void) */ void vPortSetupTimer(void) { + /* Systimer HAL layer object */ + static systimer_hal_context_t systimer_hal; /* set system timer interrupt vector */ - ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, ESP_INTR_FLAG_IRAM, vPortSysTickHandler, NULL, NULL)); + ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, ESP_INTR_FLAG_IRAM, vPortSysTickHandler, &systimer_hal, NULL)); /* configure the timer */ - systimer_hal_init(); - systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_0, SYSTIMER_COUNTER_1); - systimer_hal_enable_counter(SYSTIMER_COUNTER_1); - systimer_hal_counter_can_stall_by_cpu(SYSTIMER_COUNTER_1, 0, true); - systimer_hal_set_alarm_period(SYSTIMER_ALARM_0, 1000000UL / CONFIG_FREERTOS_HZ); - systimer_hal_select_alarm_mode(SYSTIMER_ALARM_0, SYSTIMER_ALARM_MODE_PERIOD); - systimer_hal_enable_alarm_int(SYSTIMER_ALARM_0); + systimer_hal_init(&systimer_hal); + systimer_hal_connect_alarm_counter(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_LL_COUNTER_OS_TICK); + systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK); + systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 0, true); + systimer_hal_set_alarm_period(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, 1000000UL / CONFIG_FREERTOS_HZ); + systimer_hal_select_alarm_mode(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_ALARM_MODE_PERIOD); + systimer_hal_enable_alarm_int(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0); } void prvTaskExitError(void) @@ -227,7 +229,7 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC extern char _thread_local_start, _thread_local_end, _flash_rodata_start; /* Byte pointer, so that subsequent calculations don't depend on sizeof(StackType_t). */ - uint8_t* sp = (uint8_t*) pxTopOfStack; + uint8_t *sp = (uint8_t *) pxTopOfStack; /* Set up TLS area. * The following diagram illustrates the layout of link-time and run-time @@ -293,9 +295,9 @@ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxC IRAM_ATTR void vPortSysTickHandler(void *arg) { - (void)arg; + systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg; - systimer_ll_clear_alarm_int(SYSTIMER_ALARM_0); + systimer_ll_clear_alarm_int(systimer_hal->dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0); #ifdef CONFIG_PM_TRACE ESP_PM_TRACE_ENTER(TICK, xPortGetCoreID()); @@ -380,8 +382,9 @@ void vPortSetStackWatchpoint(void *pxStackStart) esp_cpu_set_watchpoint(STACK_WATCH_POINT_NUMBER, (char *)addr, STACK_WATCH_AREA_SIZE, ESP_WATCHPOINT_STORE); } -uint32_t xPortGetTickRateHz(void) { - return (uint32_t)configTICK_RATE_HZ; +uint32_t xPortGetTickRateHz(void) +{ + return (uint32_t)configTICK_RATE_HZ; } BaseType_t xPortInIsrContext(void) diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index e709ee1397..e9948d81bb 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -56,11 +56,11 @@ if(NOT BOOTLOADER_BUILD) "pcnt_hal.c" "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" + "systimer_hal.c" "touch_sensor_hal.c" "esp32s2/adc_hal.c" "esp32s2/brownout_hal.c" "esp32s2/cp_dma_hal.c" - "esp32s2/systimer_hal.c" "esp32s2/touch_sensor_hal.c" "esp32s2/dac_hal.c" "esp32s2/interrupt_descriptor_table.c" @@ -75,10 +75,10 @@ if(NOT BOOTLOADER_BUILD) "pcnt_hal.c" "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" + "systimer_hal.c" "touch_sensor_hal.c" "esp32s3/brownout_hal.c" "esp32s3/interrupt_descriptor_table.c" - "esp32s3/systimer_hal.c" "esp32s3/touch_sensor_hal.c") endif() @@ -86,12 +86,12 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "ds_hal.c" "gdma_hal.c" - "esp32c3/adc_hal.c" - "esp32c3/brownout_hal.c" - "esp32c3/systimer_hal.c" - "esp32c3/hmac_hal.c" "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" + "systimer_hal.c" + "esp32c3/adc_hal.c" + "esp32c3/brownout_hal.c" + "esp32c3/hmac_hal.c" "esp32c3/rtc_cntl_hal.c") endif() endif() diff --git a/components/hal/component.mk b/components/hal/component.mk index da3d6456b9..7dbf48b048 100644 --- a/components/hal/component.mk +++ b/components/hal/component.mk @@ -2,7 +2,7 @@ COMPONENT_SRCDIRS := . esp32 COMPONENT_ADD_INCLUDEDIRS := esp32/include include COMPONENT_ADD_LDFRAGMENTS += linker.lf -COMPONENT_OBJEXCLUDE += ./spi_slave_hd_hal.o ./spi_flash_hal_gpspi.o ./spi_slave_hd_hal.o ./ds_hal.o ./gdma_hal.o ./lcd_hal.o +COMPONENT_OBJEXCLUDE += ./spi_slave_hd_hal.o ./spi_flash_hal_gpspi.o ./spi_slave_hd_hal.o ./ds_hal.o ./gdma_hal.o ./lcd_hal.o ./systimer_hal.o ifndef CONFIG_ETH_USE_ESP32_EMAC COMPONENT_OBJEXCLUDE += esp32/emac_hal.o diff --git a/components/hal/esp32c3/include/hal/systimer_ll.h b/components/hal/esp32c3/include/hal/systimer_ll.h index f0dab94c5f..e7d50778ab 100644 --- a/components/hal/esp32c3/include/hal/systimer_ll.h +++ b/components/hal/esp32c3/include/hal/systimer_ll.h @@ -13,139 +13,148 @@ // limitations under the License. #pragma once +#include +#include +#include +#include "soc/systimer_struct.h" + +#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time +#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick +#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0 +#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time + #ifdef __cplusplus extern "C" { #endif -#include -#include -#include "soc/soc.h" -#include "soc/systimer_reg.h" - // All these functions get invoked either from ISR or HAL that linked to IRAM. // Always inline these functions even no gcc optimization is applied. -/*******************counter*************************/ +/******************* Clock *************************/ -__attribute__((always_inline)) static inline void systimer_ll_enable_clock(void) +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, SYS_TIMER_CLK_EN); + dev->conf.clk_en = en; } -__attribute__((always_inline)) static inline void systimer_ll_enable_counter(uint32_t counter_id) -{ - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (30 - counter_id)); -} +/******************* Counter *************************/ -__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can) +__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) { - if (can) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id)); + if (en) { + dev->conf.val |= 1 << (30 - counter_id); } else { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id)); + dev->conf.val &= ~(1 << (30 - counter_id)); } } -__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 30); + if (can) { + dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id); + } else { + dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id)); + } } -__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) { - return REG_GET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 29); + dev->unit_op[counter_id].timer_unit_update = 1; } -__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(uint32_t counter_id, uint64_t value) +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) { - REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG + 8 * counter_id, value & 0xFFFFFFFF); - REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG, (value >> 32) & 0xFFFFF); + return dev->unit_op[counter_id].timer_unit_value_valid; } -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) { - return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG + 8 * counter_id); + dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32; + dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF; } -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(uint32_t counter_id) +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) { - return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG + 8 * counter_id); + return dev->unit_val[counter_id].lo.timer_unit_value_lo; } -__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(uint32_t counter_id) +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG + 4 * counter_id, SYS_TIMER_TIMER_UNIT0_LOAD); + return dev->unit_val[counter_id].hi.timer_unit_value_hi; } -/*******************alarm*************************/ - -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(uint32_t alarm_id, uint64_t value) +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) { - REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF); - REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value >> 32) & 0xFFFFF); + dev->unit_load[counter_id].val = 0x01; } -__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(uint32_t alarm_id) +/******************* Alarm *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) { - return ((uint64_t) REG_READ(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8) << 32) \ - | REG_READ(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8); + dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; + dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF; } -__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(uint32_t alarm_id, uint32_t counter_id) +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + 4 * alarm_id, SYS_TIMER_TARGET0_TIMER_UNIT_SEL, counter_id); + return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE); + dev->target_conf[alarm_id].target_timer_unit_sel = counter_id; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE); + dev->target_conf[alarm_id].target_period_mode = 0; } -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD, period); + dev->target_conf[alarm_id].target_period_mode = 1; } -__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_COMP0_LOAD_REG + alarm_id * 4, SYS_TIMER_TIMER_COMP0_LOAD); + assert(period < (1 << 26)); + dev->target_conf[alarm_id].target_period = period; } -__attribute__((always_inline)) static inline void systimer_ll_disable_alarm(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id)); + dev->comp_load[alarm_id].val = 0x01; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id)); + if (en) { + dev->conf.val |= 1 << (24 - alarm_id); + } else { + dev->conf.val &= ~(1 << (24 - alarm_id)); + } } -/*******************interrupt*************************/ +/******************* Interrupt *************************/ -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, 1 << alarm_id); + if (en) { + dev->int_ena.val |= 1 << alarm_id; + } else { + dev->int_ena.val &= ~(1 << alarm_id); + } } -__attribute__((always_inline)) static inline void systimer_ll_disable_alarm_int(uint32_t alarm_id) +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, 1 << alarm_id); + return dev->int_st.val & (1 << alarm_id); } -__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) { - return REG_GET_BIT(SYS_TIMER_SYSTIMER_INT_RAW_REG, 1 << alarm_id); -} - -__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(uint32_t alarm_id) -{ - REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_CLR_REG, 1 << alarm_id); + dev->int_clr.val |= 1 << alarm_id; } #ifdef __cplusplus diff --git a/components/hal/esp32c3/systimer_hal.c b/components/hal/esp32c3/systimer_hal.c deleted file mode 100644 index c01ff909ac..0000000000 --- a/components/hal/esp32c3/systimer_hal.c +++ /dev/null @@ -1,128 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include "hal/systimer_hal.h" -#include "hal/systimer_ll.h" -#include "hal/systimer_types.h" -#include "soc/systimer_caps.h" -#include "hal/clk_gate_ll.h" - -#define SYSTIMER_TICKS_PER_US (16) // Systimer clock source is fixed to 16MHz - -uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id) -{ - uint32_t lo, lo_start, hi; - /* Set the "update" bit and wait for acknowledgment */ - systimer_ll_counter_snapshot(counter_id); - while (!systimer_ll_is_counter_value_valid(counter_id)); - /* Read LO, HI, then LO again, check that LO returns the same value. - * This accounts for the case when an interrupt may happen between reading - * HI and LO values, and this function may get called from the ISR. - * In this case, the repeated read will return consistent values. - */ - lo_start = systimer_ll_get_counter_value_low(counter_id); - do { - lo = lo_start; - hi = systimer_ll_get_counter_value_high(counter_id); - lo_start = systimer_ll_get_counter_value_low(counter_id); - } while (lo_start != lo); - - systimer_counter_value_t result = { - .lo = lo, - .hi = hi - }; - - return result.val; -} - -uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id) -{ - return systimer_hal_get_counter_value(counter_id) / SYSTIMER_TICKS_PER_US; -} - -void systimer_hal_set_alarm_target(systimer_alarm_id_t alarm_id, uint64_t target) -{ - systimer_counter_value_t alarm = { .val = target * SYSTIMER_TICKS_PER_US}; - systimer_ll_disable_alarm(alarm_id); - systimer_ll_set_alarm_target(alarm_id, alarm.val); - systimer_ll_apply_alarm_value(alarm_id); - systimer_ll_enable_alarm(alarm_id); -} - -void systimer_hal_set_alarm_period(systimer_alarm_id_t alarm_id, uint32_t period) -{ - systimer_ll_disable_alarm(alarm_id); - systimer_ll_set_alarm_period(alarm_id, period * SYSTIMER_TICKS_PER_US); - systimer_ll_apply_alarm_value(alarm_id); - systimer_ll_enable_alarm(alarm_id); -} - -uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id) -{ - return systimer_ll_get_alarm_target(alarm_id); -} - -void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id) -{ - systimer_ll_enable_alarm_int(alarm_id); -} - -void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us) -{ - /* Nothing to do here, SYSTIMER clock is independent of APB clock */ - (void)apb_ticks_per_us; -} - -void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us) -{ - systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(counter_id) + time_us * SYSTIMER_TICKS_PER_US }; - systimer_ll_set_counter_value(counter_id, new_count.val); - systimer_ll_apply_counter_value(counter_id); -} - -void systimer_hal_enable_counter(systimer_counter_id_t counter_id) -{ - systimer_ll_enable_counter(counter_id); -} - -void systimer_hal_init(void) -{ - periph_ll_enable_clk_clear_rst(PERIPH_SYSTIMER_MODULE); - systimer_ll_enable_clock(); -} - -void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode) -{ - switch (mode) { - case SYSTIMER_ALARM_MODE_ONESHOT: - systimer_ll_enable_alarm_oneshot(alarm_id); - break; - case SYSTIMER_ALARM_MODE_PERIOD: - systimer_ll_enable_alarm_period(alarm_id); - break; - default: - break; - } -} - -void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id) -{ - systimer_ll_connect_alarm_counter(alarm_id, counter_id); -} - -void systimer_hal_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can) -{ - systimer_ll_counter_can_stall_by_cpu(counter_id, cpu_id, can); -} diff --git a/components/hal/esp32s2/include/hal/systimer_ll.h b/components/hal/esp32s2/include/hal/systimer_ll.h index 752ad2dd24..388f00580f 100644 --- a/components/hal/esp32s2/include/hal/systimer_ll.h +++ b/components/hal/esp32s2/include/hal/systimer_ll.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,124 +13,156 @@ // limitations under the License. #pragma once +#include +#include +#include +#include "soc/systimer_struct.h" + +#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time +#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time + #ifdef __cplusplus extern "C" { #endif -#include -#include -#include "soc/soc.h" -#include "soc/systimer_reg.h" - // All these functions get invoked either from ISR or HAL that linked to IRAM. // Always inline these functions even no gcc optimization is applied. -/*******************counter*************************/ +/******************* Clock *************************/ -__attribute__((always_inline)) static inline void systimer_ll_enable_clock(void) +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) { - REG_SET_BIT(SYSTIMER_CONF_REG, SYSTIMER_CLK_EN); + dev->conf.clk_en = en; } -__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(void) +/******************* Counter *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) { - REG_SET_BIT(SYSTIMER_LOAD_REG, SYSTIMER_TIMER_LOAD); + // ESP32-S2 only has one counter in systimer group + (void)dev; + (void)counter_id; } -__attribute__((always_inline)) static inline void systimer_ll_load_counter_value(uint64_t value) +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) { - REG_WRITE(SYSTIMER_LOAD_LO_REG, value & 0xFFFFFFFF); - REG_WRITE(SYSTIMER_LOAD_HI_REG, (value & 0xFFFFFFFF00000000) >> 32); + (void)dev; + (void)counter_id; + (void)cpu_id; + (void)can; } -__attribute__((always_inline)) static inline void systimer_ll_set_step_for_pll(uint32_t step) +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) { - REG_SET_FIELD(SYSTIMER_STEP_REG, SYSTIMER_TIMER_PLL_STEP, step); + (void)counter_id; + dev->update.timer_update = 1; } -__attribute__((always_inline)) static inline void systimer_ll_set_step_for_xtal(uint32_t step) +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) { - REG_SET_FIELD(SYSTIMER_STEP_REG, SYSTIMER_TIMER_XTAL_STEP, step); + (void)counter_id; + return dev->update.timer_value_valid; } -__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(void) +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) { - REG_WRITE(SYSTIMER_UPDATE_REG, SYSTIMER_TIMER_UPDATE); + (void)counter_id; + dev->load_hi.timer_load_hi = value >> 32; + dev->load_lo.timer_load_lo = value; } -__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(void) +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) { - return REG_GET_BIT(SYSTIMER_UPDATE_REG, SYSTIMER_TIMER_VALUE_VALID); + return dev->value_lo.timer_value_lo; } -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(void) +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) { - return REG_READ(SYSTIMER_VALUE_LO_REG); + return dev->value_hi.timer_value_hi; } -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(void) +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) { - return REG_READ(SYSTIMER_VALUE_HI_REG); + dev->load.timer_load = 1; } -/*******************alarm*************************/ - -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_value(uint32_t alarm_id, uint64_t value) +__attribute__((always_inline)) static inline void systimer_ll_set_step_for_pll(systimer_dev_t *dev, uint32_t step) { - REG_WRITE(SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF); - REG_WRITE(SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value & 0xFFFFFFFF00000000) >> 32); + dev->step.timer_pll_step = step; } -__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_value(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_set_step_for_xtal(systimer_dev_t *dev, uint32_t step) { - return (uint64_t)REG_READ(SYSTIMER_TARGET0_HI_REG + alarm_id * 8) << 32 | REG_READ(SYSTIMER_TARGET0_LO_REG + alarm_id * 8); + dev->step.timer_xtal_step = step; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(uint32_t alarm_id) +/******************* Alarm *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) { - REG_SET_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(31)); + dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; + dev->target_val[alarm_id].lo.timer_target_lo = value; } -__attribute__((always_inline)) static inline void systimer_ll_disable_alarm(uint32_t alarm_id) +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) { - REG_CLR_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(31)); + return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) { - REG_CLR_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(30)); + // On esp32-s2, counter int the systimer is fixed connectred to other three alarm comparators + (void)dev; + (void)alarm_id; + (void)counter_id; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_BIT(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, BIT(30)); + dev->target_conf[alarm_id].target_period_mode = 0; } -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_FIELD(SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYSTIMER_TARGET0_PERIOD, period); + dev->target_conf[alarm_id].target_period_mode = 1; } -/*******************interrupt*************************/ - -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) { - REG_SET_BIT(SYSTIMER_INT_ENA_REG, 1 << alarm_id); + assert(period < (1 << 30)); + dev->target_conf[alarm_id].target_period = period; } -__attribute__((always_inline)) static inline void systimer_ll_disable_alarm_int(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) { - REG_CLR_BIT(SYSTIMER_INT_ENA_REG, 1 << alarm_id); + (void)dev; + (void)alarm_id; } -__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) { - return REG_GET_BIT(SYSTIMER_INT_RAW_REG, 1 << alarm_id); + dev->target_conf[alarm_id].target_work_en = en; } -__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(uint32_t alarm_id) +/******************* Interrupt *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) { - REG_SET_BIT(SYSTIMER_INT_CLR_REG, 1 << alarm_id); + if (en) { + dev->int_ena.val |= 1 << alarm_id; + } else { + dev->int_ena.val &= ~(1 << alarm_id); + } +} + +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) +{ + return dev->int_raw.val & (1 << alarm_id); +} + +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) +{ + dev->int_clr.val |= 1 << alarm_id; } #ifdef __cplusplus diff --git a/components/hal/esp32s2/systimer_hal.c b/components/hal/esp32s2/systimer_hal.c deleted file mode 100644 index 9124c32814..0000000000 --- a/components/hal/esp32s2/systimer_hal.c +++ /dev/null @@ -1,148 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include -#include "soc/soc_caps.h" -#include "hal/systimer_hal.h" -#include "hal/systimer_ll.h" -#include "hal/systimer_types.h" -#include "soc/rtc.h" - -#define SYSTIMER_TICKS_PER_US (80) // Number of timer ticks per microsecond - -uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id) -{ - uint32_t lo, lo_start, hi; - /* Set the "update" bit and wait for acknowledgment */ - systimer_ll_counter_snapshot(); - while (!systimer_ll_is_counter_value_valid()); - /* Read LO, HI, then LO again, check that LO returns the same value. - * This accounts for the case when an interrupt may happen between reading - * HI and LO values, and this function may get called from the ISR. - * In this case, the repeated read will return consistent values. - */ - lo_start = systimer_ll_get_counter_value_low(); - do { - lo = lo_start; - hi = systimer_ll_get_counter_value_high(); - lo_start = systimer_ll_get_counter_value_low(); - } while (lo_start != lo); - - systimer_counter_value_t result = { - .lo = lo, - .hi = hi - }; - - return result.val; -} - -uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id) -{ - return systimer_hal_get_counter_value(counter_id) / SYSTIMER_TICKS_PER_US; -} - -void systimer_hal_set_alarm_target(systimer_alarm_id_t alarm_id, uint64_t timestamp) -{ - int64_t offset = SYSTIMER_TICKS_PER_US * 2; - uint64_t now_time = systimer_hal_get_counter_value(SYSTIMER_COUNTER_0); - systimer_counter_value_t alarm = { .val = MAX(timestamp * SYSTIMER_TICKS_PER_US, now_time + offset) }; - do { - systimer_ll_disable_alarm(alarm_id); - systimer_ll_set_alarm_value(alarm_id, alarm.val); - systimer_ll_enable_alarm(alarm_id); - now_time = systimer_hal_get_counter_value(SYSTIMER_COUNTER_0); - int64_t delta = (int64_t)alarm.val - (int64_t)now_time; - if (delta <= 0 && !systimer_ll_is_alarm_int_fired(alarm_id)) { - // new alarm is less than the counter and the interrupt flag is not set - offset += -1 * delta + SYSTIMER_TICKS_PER_US * 2; - alarm.val = now_time + offset; - } else { - // finish if either (alarm > counter) or the interrupt flag is already set. - break; - } - } while (1); -} - -uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id) -{ - return systimer_ll_get_alarm_value(alarm_id); -} - -void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id) -{ - systimer_ll_enable_alarm_int(alarm_id); -} - -void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us) -{ - /* If this function was called when switching APB clock to PLL, don't need - * do anything: the SYSTIMER_TIMER_PLL_STEP is already correct. - * If this was called when switching APB clock to XTAL, need to adjust - * XTAL_STEP value accordingly. - */ - if (apb_ticks_per_us != SYSTIMER_TICKS_PER_US) { - assert((SYSTIMER_TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)"); - systimer_ll_set_step_for_xtal(SYSTIMER_TICKS_PER_US / apb_ticks_per_us); - } -} - -void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us) -{ - systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(counter_id) + time_us * SYSTIMER_TICKS_PER_US }; - systimer_ll_load_counter_value(new_count.val); - systimer_ll_apply_counter_value(); -} - -void systimer_hal_enable_counter(systimer_counter_id_t counter_id) -{ - (void)counter_id; -} - -void systimer_hal_init(void) -{ - assert(rtc_clk_xtal_freq_get() == 40 && "update the step for xtal to support other XTAL:APB frequency ratios"); - systimer_ll_enable_clock(); - /* Configure the counter: - * - increment by 1 when running from PLL (80 ticks per microsecond), - * - increment by 2 when running from XTAL (40 ticks per microsecond). - * Note that if the APB frequency is derived from XTAL with divider != 1, - * XTAL_STEP needs to be adjusted accordingly. For example, if - * the APB frequency is XTAL/4 = 10 MHz, then XTAL_STEP should be set to 8. - * This is handled in systimer_hal_on_apb_freq_update function. - */ - systimer_ll_set_step_for_pll(1); - systimer_ll_set_step_for_xtal(2); -} - -void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode) -{ - switch (mode) { - case SYSTIMER_ALARM_MODE_ONESHOT: - systimer_ll_enable_alarm_oneshot(alarm_id); - break; - case SYSTIMER_ALARM_MODE_PERIOD: - systimer_ll_enable_alarm_period(alarm_id); - break; - default: - break; - } -} - -void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id) -{ - // esp32s2 only has one counter, so there's no need to connect alarm unit to counter - (void)alarm_id; - (void)counter_id; -} diff --git a/components/hal/esp32s3/include/hal/systimer_ll.h b/components/hal/esp32s3/include/hal/systimer_ll.h index a277771bb3..ba07f4658b 100644 --- a/components/hal/esp32s3/include/hal/systimer_ll.h +++ b/components/hal/esp32s3/include/hal/systimer_ll.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2021 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,139 +13,149 @@ // limitations under the License. #pragma once +#include +#include +#include +#include "soc/systimer_struct.h" + +#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time +#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick +#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0 +#define SYSTIMER_LL_ALARM_OS_TICK_CORE1 (1) // Alarm used for OS tick of CPU core 1 +#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time + #ifdef __cplusplus extern "C" { #endif -#include -#include -#include "soc/soc.h" -#include "soc/sys_timer_reg.h" - // All these functions get invoked either from ISR or HAL that linked to IRAM. // Always inline these functions even no gcc optimization is applied. -/*******************counter*************************/ +/******************* Clock *************************/ -__attribute__((always_inline)) static inline void systimer_ll_enable_clock(void) +__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, SYS_TIMER_CLK_EN); + dev->conf.clk_en = en; } -__attribute__((always_inline)) static inline void systimer_ll_enable_counter(uint32_t counter_id) -{ - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (30 - counter_id)); -} +/******************* Counter *************************/ -__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can) +__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en) { - if (can) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id)); + if (en) { + dev->conf.val |= 1 << (30 - counter_id); } else { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id)); + dev->conf.val &= ~(1 << (30 - counter_id)); } } -__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 30); + if (can) { + dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id); + } else { + dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id)); + } } -__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id) { - return REG_GET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 29); + dev->unit_op[counter_id].timer_unit_update = 1; } -__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(uint32_t counter_id, uint64_t value) +__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id) { - REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG + 8 * counter_id, value & 0xFFFFFFFF); - REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG, (value >> 32) & 0xFFFFF); + return dev->unit_op[counter_id].timer_unit_value_valid; } -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(uint32_t counter_id) +__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value) { - return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG + 8 * counter_id); + dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32; + dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF; } -__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(uint32_t counter_id) +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id) { - return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG + 8 * counter_id); + return dev->unit_val[counter_id].lo.timer_unit_value_lo; } -__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(uint32_t counter_id) +__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG + 4 * counter_id, SYS_TIMER_TIMER_UNIT0_LOAD); + return dev->unit_val[counter_id].hi.timer_unit_value_hi; } -/*******************alarm*************************/ - -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(uint32_t alarm_id, uint64_t value) +__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id) { - REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF); - REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value >> 32) & 0xFFFFF); + dev->unit_load[counter_id].val = 0x01; } -__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(uint32_t alarm_id) +/******************* Alarm *************************/ + +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value) { - return ((uint64_t) REG_READ(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8) << 32) \ - | REG_READ(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8); + dev->target_val[alarm_id].hi.timer_target_hi = value >> 32; + dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF; } -__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(uint32_t alarm_id, uint32_t counter_id) +__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + 4 * alarm_id, SYS_TIMER_TARGET0_TIMER_UNIT_SEL, counter_id); + return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id) { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE); + dev->target_conf[alarm_id].target_timer_unit_sel = counter_id; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE); + dev->target_conf[alarm_id].target_period_mode = 0; } -__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id) { - REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD, period); + dev->target_conf[alarm_id].target_period_mode = 1; } -__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_COMP0_LOAD_REG + alarm_id * 4, SYS_TIMER_TIMER_COMP0_LOAD); + assert(period < (1 << 26)); + dev->target_conf[alarm_id].target_period = period; } -__attribute__((always_inline)) static inline void systimer_ll_disable_alarm(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id) { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id)); + dev->comp_load[alarm_id].val = 0x01; } -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id)); + if (en) { + dev->conf.val |= 1 << (24 - alarm_id); + } else { + dev->conf.val &= ~(1 << (24 - alarm_id)); + } } -/*******************interrupt*************************/ +/******************* Interrupt *************************/ -__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en) { - REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, 1 << alarm_id); + if (en) { + dev->int_ena.val |= 1 << alarm_id; + } else { + dev->int_ena.val &= ~(1 << alarm_id); + } } -__attribute__((always_inline)) static inline void systimer_ll_disable_alarm_int(uint32_t alarm_id) +__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id) { - REG_CLR_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, 1 << alarm_id); + return dev->int_st.val & (1 << alarm_id); } -__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(uint32_t alarm_id) +__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id) { - return REG_GET_BIT(SYS_TIMER_SYSTIMER_INT_RAW_REG, 1 << alarm_id); -} - -__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(uint32_t alarm_id) -{ - REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_CLR_REG, 1 << alarm_id); + dev->int_clr.val |= 1 << alarm_id; } #ifdef __cplusplus diff --git a/components/hal/esp32s3/systimer_hal.c b/components/hal/esp32s3/systimer_hal.c deleted file mode 100644 index 1ac1696052..0000000000 --- a/components/hal/esp32s3/systimer_hal.c +++ /dev/null @@ -1,123 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include "soc/soc_caps.h" -#include "hal/systimer_hal.h" -#include "hal/systimer_ll.h" -#include "hal/systimer_types.h" -#include "hal/clk_gate_ll.h" - -#define SYSTIMER_TICKS_PER_US (16) // Systimer clock source is fixed to 16MHz - -uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id) -{ - uint32_t lo, lo_start, hi; - /* Set the "update" bit and wait for acknowledgment */ - systimer_ll_counter_snapshot(counter_id); - while (!systimer_ll_is_counter_value_valid(counter_id)); - /* Read LO, HI, then LO again, check that LO returns the same value. - * This accounts for the case when an interrupt may happen between reading - * HI and LO values, and this function may get called from the ISR. - * In this case, the repeated read will return consistent values. - */ - lo_start = systimer_ll_get_counter_value_low(counter_id); - do { - lo = lo_start; - hi = systimer_ll_get_counter_value_high(counter_id); - lo_start = systimer_ll_get_counter_value_low(counter_id); - } while (lo_start != lo); - - systimer_counter_value_t result = { - .lo = lo, - .hi = hi - }; - - return result.val; -} - -uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id) -{ - return systimer_hal_get_counter_value(counter_id) / SYSTIMER_TICKS_PER_US; -} - -void systimer_hal_set_alarm_target(systimer_alarm_id_t alarm_id, uint64_t target) -{ - systimer_counter_value_t alarm = { .val = target * SYSTIMER_TICKS_PER_US}; - systimer_ll_disable_alarm(alarm_id); - systimer_ll_set_alarm_target(alarm_id, alarm.val); - systimer_ll_apply_alarm_value(alarm_id); - systimer_ll_enable_alarm(alarm_id); -} - -void systimer_hal_set_alarm_period(systimer_alarm_id_t alarm_id, uint32_t period) -{ - systimer_ll_disable_alarm(alarm_id); - systimer_ll_set_alarm_period(alarm_id, period * SYSTIMER_TICKS_PER_US); - systimer_ll_apply_alarm_value(alarm_id); - systimer_ll_enable_alarm(alarm_id); -} - -uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id) -{ - return systimer_ll_get_alarm_target(alarm_id); -} - -void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id) -{ - systimer_ll_enable_alarm_int(alarm_id); -} - -void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us) -{ - /* Nothing to do here, SYSTIMER clock is independent of APB clock */ - (void)apb_ticks_per_us; -} - -void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us) -{ - systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(counter_id) + time_us * SYSTIMER_TICKS_PER_US }; - systimer_ll_set_counter_value(counter_id, new_count.val); - systimer_ll_apply_counter_value(counter_id); -} - -void systimer_hal_enable_counter(systimer_counter_id_t counter_id) -{ - systimer_ll_enable_counter(counter_id); -} - -void systimer_hal_init(void) -{ - periph_ll_enable_clk_clear_rst(PERIPH_SYSTIMER_MODULE); - systimer_ll_enable_clock(); -} - -void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode) -{ - switch (mode) { - case SYSTIMER_ALARM_MODE_ONESHOT: - systimer_ll_enable_alarm_oneshot(alarm_id); - break; - case SYSTIMER_ALARM_MODE_PERIOD: - systimer_ll_enable_alarm_period(alarm_id); - break; - default: - break; - } -} - -void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id) -{ - systimer_ll_connect_alarm_counter(alarm_id, counter_id); -} diff --git a/components/hal/include/hal/systimer_hal.h b/components/hal/include/hal/systimer_hal.h index 1f4eb5c488..9ac3262fa8 100644 --- a/components/hal/include/hal/systimer_hal.h +++ b/components/hal/include/hal/systimer_hal.h @@ -14,78 +14,91 @@ #pragma once +#include +#include +#include "soc/soc_caps.h" +#include "soc/systimer_struct.h" +#include "hal/systimer_types.h" + #ifdef __cplusplus extern "C" { #endif -#include -#include -#include "hal/systimer_types.h" - -/** - * @brief enable systimer counter - */ -void systimer_hal_enable_counter(systimer_counter_id_t counter_id); - -/** - * @brief get current counter value - */ -uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id); - -/** - * @brief get current time (in microseconds) - */ -uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id); - -/* - * @brief set alarm target value (used in one-shot mode) - */ -void systimer_hal_set_alarm_target(systimer_alarm_id_t alarm_id, uint64_t target); - -/** - * @brief set alarm period value (used in period mode) - */ -void systimer_hal_set_alarm_period(systimer_alarm_id_t alarm_id, uint32_t period); - -/** - * @brief get alarm time - */ -uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id); - -/** - * @brief enable alarm interrupt - */ -void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id); - -/** - * @brief select alarm mode - */ -void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode); - -/** - * @brief update systimer step when apb clock gets changed - */ -void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us); - -/** - * @brief move systimer counter value forward or backward - */ -void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us); +typedef struct { + systimer_dev_t *dev; +} systimer_hal_context_t; /** * @brief initialize systimer in HAL layer */ -void systimer_hal_init(void); +void systimer_hal_init(systimer_hal_context_t *hal); + +/** + * @brief enable systimer counter + */ +void systimer_hal_enable_counter(systimer_hal_context_t *hal, uint32_t counter_id); + +/** + * @brief get current counter value + */ +uint64_t systimer_hal_get_counter_value(systimer_hal_context_t *hal, uint32_t counter_id); + +/** + * @brief get current time (in microseconds) + */ +uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id); + +/* + * @brief set alarm target value (used in one-shot mode) + */ +void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target); + +/** + * @brief set alarm period value (used in period mode) + */ +void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period); + +/** + * @brief get alarm time + */ +uint64_t systimer_hal_get_alarm_value(systimer_hal_context_t *hal, uint32_t alarm_id); + +/** + * @brief enable alarm interrupt + */ +void systimer_hal_enable_alarm_int(systimer_hal_context_t *hal, uint32_t alarm_id); + +/** + * @brief select alarm mode + */ +void systimer_hal_select_alarm_mode(systimer_hal_context_t *hal, uint32_t alarm_id, systimer_alarm_mode_t mode); + +/** + * @brief update systimer step when apb clock gets changed + */ +void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_ticks_per_us); + +/** + * @brief move systimer counter value forward or backward + */ +void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t counter_id, int64_t time_us); /** * @brief connect alarm unit to selected counter */ -void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id); +void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t counter_id); /** * @brief set if a counter should be stalled when CPU is halted by the debugger */ -void systimer_hal_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can); +void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can); + +#if !SOC_SYSTIMER_FIXED_TICKS_US +/** + * @brief set increase steps for systimer counter on different clock source + */ +void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps); +#endif #ifdef __cplusplus } diff --git a/components/hal/systimer_hal.c b/components/hal/systimer_hal.c new file mode 100644 index 0000000000..2521060308 --- /dev/null +++ b/components/hal/systimer_hal.c @@ -0,0 +1,188 @@ +// Copyright 2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "soc/soc_caps.h" +#include "hal/systimer_hal.h" +#include "hal/systimer_ll.h" +#include "hal/systimer_types.h" +#include "hal/clk_gate_ll.h" + +// Number of timer ticks per microsecond +#if SOC_SYSTIMER_FIXED_TICKS_US +#define SYSTIMER_TICKS_PER_US (SOC_SYSTIMER_FIXED_TICKS_US) +#else +#define SYSTIMER_TICKS_PER_US (80) +#endif + +void systimer_hal_init(systimer_hal_context_t *hal) +{ + hal->dev = &SYSTIMER; + periph_ll_enable_clk_clear_rst(PERIPH_SYSTIMER_MODULE); + systimer_ll_enable_clock(hal->dev, true); +} + +uint64_t systimer_hal_get_counter_value(systimer_hal_context_t *hal, uint32_t counter_id) +{ + uint32_t lo, lo_start, hi; + /* Set the "update" bit and wait for acknowledgment */ + systimer_ll_counter_snapshot(hal->dev, counter_id); + while (!systimer_ll_is_counter_value_valid(hal->dev, counter_id)); + /* Read LO, HI, then LO again, check that LO returns the same value. + * This accounts for the case when an interrupt may happen between reading + * HI and LO values, and this function may get called from the ISR. + * In this case, the repeated read will return consistent values. + */ + lo_start = systimer_ll_get_counter_value_low(hal->dev, counter_id); + do { + lo = lo_start; + hi = systimer_ll_get_counter_value_high(hal->dev, counter_id); + lo_start = systimer_ll_get_counter_value_low(hal->dev, counter_id); + } while (lo_start != lo); + + systimer_counter_value_t result = { + .lo = lo, + .hi = hi + }; + + return result.val; +} + +uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id) +{ + return systimer_hal_get_counter_value(hal, counter_id) / SYSTIMER_TICKS_PER_US; +} + +#if SOC_SYSTIMER_ALARM_MISS_COMPENSATE +void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target) +{ + systimer_counter_value_t alarm = { .val = target * SYSTIMER_TICKS_PER_US}; + systimer_ll_enable_alarm(hal->dev, alarm_id, false); + systimer_ll_set_alarm_target(hal->dev, alarm_id, alarm.val); + systimer_ll_apply_alarm_value(hal->dev, alarm_id); + systimer_ll_enable_alarm(hal->dev, alarm_id, true); +} +#else +void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t timestamp) +{ + int64_t offset = SYSTIMER_TICKS_PER_US * 2; + uint64_t now_time = systimer_hal_get_counter_value(hal, 0); + systimer_counter_value_t alarm = { .val = MAX(timestamp * SYSTIMER_TICKS_PER_US, now_time + offset) }; + do { + systimer_ll_enable_alarm(hal->dev, alarm_id, false); + systimer_ll_set_alarm_target(hal->dev, alarm_id, alarm.val); + systimer_ll_enable_alarm(hal->dev, alarm_id, true); + now_time = systimer_hal_get_counter_value(hal, 0); + int64_t delta = (int64_t)alarm.val - (int64_t)now_time; + if (delta <= 0 && !systimer_ll_is_alarm_int_fired(hal->dev, alarm_id)) { + // new alarm is less than the counter and the interrupt flag is not set + offset += -1 * delta + SYSTIMER_TICKS_PER_US * 2; + alarm.val = now_time + offset; + } else { + // finish if either (alarm > counter) or the interrupt flag is already set. + break; + } + } while (1); +} +#endif + +void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period) +{ + systimer_ll_enable_alarm(hal->dev, alarm_id, false); + systimer_ll_set_alarm_period(hal->dev, alarm_id, period * SYSTIMER_TICKS_PER_US); + systimer_ll_apply_alarm_value(hal->dev, alarm_id); + systimer_ll_enable_alarm(hal->dev, alarm_id, true); +} + +uint64_t systimer_hal_get_alarm_value(systimer_hal_context_t *hal, uint32_t alarm_id) +{ + return systimer_ll_get_alarm_target(hal->dev, alarm_id); +} + +void systimer_hal_enable_alarm_int(systimer_hal_context_t *hal, uint32_t alarm_id) +{ + systimer_ll_enable_alarm_int(hal->dev, alarm_id, true); +} + +void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t counter_id, int64_t time_us) +{ + systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(hal, counter_id) + time_us * SYSTIMER_TICKS_PER_US }; + systimer_ll_set_counter_value(hal->dev, counter_id, new_count.val); + systimer_ll_apply_counter_value(hal->dev, counter_id); +} + +void systimer_hal_enable_counter(systimer_hal_context_t *hal, uint32_t counter_id) +{ + systimer_ll_enable_counter(hal->dev, counter_id, true); +} + +void systimer_hal_select_alarm_mode(systimer_hal_context_t *hal, uint32_t alarm_id, systimer_alarm_mode_t mode) +{ + switch (mode) { + case SYSTIMER_ALARM_MODE_ONESHOT: + systimer_ll_enable_alarm_oneshot(hal->dev, alarm_id); + break; + case SYSTIMER_ALARM_MODE_PERIOD: + systimer_ll_enable_alarm_period(hal->dev, alarm_id); + break; + default: + break; + } +} + +void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t counter_id) +{ + systimer_ll_connect_alarm_counter(hal->dev, alarm_id, counter_id); +} + +void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can) +{ + systimer_ll_counter_can_stall_by_cpu(hal->dev, counter_id, cpu_id, can); +} + +#if !SOC_SYSTIMER_FIXED_TICKS_US +void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps) +{ + /* Configure the counter: + * - increment by 1 when running from PLL (80 ticks per microsecond), + * - increment by 2 when running from XTAL (40 ticks per microsecond). + * Note that if the APB frequency is derived from XTAL with divider != 1, + * XTAL_STEP needs to be adjusted accordingly. For example, if + * the APB frequency is XTAL/4 = 10 MHz, then XTAL_STEP should be set to 8. + * This is handled in systimer_hal_on_apb_freq_update function. + */ + switch (clock_source) { + case 0: + systimer_ll_set_step_for_xtal(hal->dev, steps); + break; + case 1: + systimer_ll_set_step_for_pll(hal->dev, steps); + default: + break; + } +} + +void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_ticks_per_us) +{ + /* If this function was called when switching APB clock to PLL, don't need + * do anything: the SYSTIMER_TIMER_PLL_STEP is already correct. + * If this was called when switching APB clock to XTAL, need to adjust + * XTAL_STEP value accordingly. + */ + if (apb_ticks_per_us != SYSTIMER_TICKS_PER_US) { + assert((SYSTIMER_TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)"); + systimer_ll_set_step_for_xtal(hal->dev, SYSTIMER_TICKS_PER_US / apb_ticks_per_us); + } +} +#endif