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refactor(brownout): correct names comments in the LL driver

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This commit is contained in:
morris
2024-08-06 13:15:30 +08:00
parent e62133ad8e
commit 9716d9e5ca
27 changed files with 214 additions and 219 deletions
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11
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -42,6 +42,7 @@
#include "hal/cache_hal.h"
#include "hal/efuse_hal.h"
#include "hal/rwdt_ll.h"
#include "hal/brownout_ll.h"
static const char *TAG = "boot.esp32c3";
@@ -106,18 +107,18 @@ static inline void bootloader_ana_reset_config(void)
case 0:
case 1:
//Disable BOD and GLITCH reset
bootloader_ana_bod_reset_config(false);
brownout_ll_ana_reset_enable(false);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 2:
//Enable BOD reset. Disable GLITCH reset
bootloader_ana_bod_reset_config(true);
brownout_ll_ana_reset_enable(true);
bootloader_ana_clock_glitch_reset_config(false);
break;
case 3:
default:
//Enable BOD, and GLITCH reset
bootloader_ana_bod_reset_config(true);
brownout_ll_ana_reset_enable(true);
bootloader_ana_clock_glitch_reset_config(true);
break;
}
@@ -182,7 +183,7 @@ esp_err_t bootloader_init(void)
}
#endif //#if !CONFIG_APP_BUILD_TYPE_RAM
// check whether a WDT reset happend
// check whether a WDT reset happened
bootloader_check_wdt_reset();
// config WDT
bootloader_config_wdt();

13
components/bootloader_support/src/esp32c3/bootloader_soc.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,17 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
}
}
void bootloader_ana_bod_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
} else {
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
}
}
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);