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Merge branch 'bugfix/fix_some_wifi_coexist_issue_v5.0' into 'release/v5.0'

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bugfix/fix some wifi coexist issue v5.0

See merge request espressif/esp-idf!29911
This commit is contained in:
Jiang Jiang Jian
2024-04-01 14:31:56 +08:00
parent ad8111253a 3a0cf2c03a
commit 987752fcff
11 changed files with 26 additions and 16 deletions
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10
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
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@@ -1474,7 +1474,7 @@ ebuf_list_remove = 0x40001adc;
GetAccess = 0x40001aec; GetAccess = 0x40001aec;
hal_mac_is_low_rate_enabled = 0x40001af0; hal_mac_is_low_rate_enabled = 0x40001af0;
hal_mac_tx_get_blockack = 0x40001af4; hal_mac_tx_get_blockack = 0x40001af4;
hal_mac_tx_set_ppdu = 0x40001af8; /*hal_mac_tx_set_ppdu = 0x40001af8;*/
ic_get_trc = 0x40001afc; ic_get_trc = 0x40001afc;
/* ic_mac_deinit = 0x40001b00; */ /* ic_mac_deinit = 0x40001b00; */
ic_mac_init = 0x40001b04; ic_mac_init = 0x40001b04;
@@ -1561,7 +1561,7 @@ ppTask = 0x40001c44;
ppTxPkt = 0x40001c48; ppTxPkt = 0x40001c48;
ppTxProtoProc = 0x40001c4c; ppTxProtoProc = 0x40001c4c;
ppTxqUpdateBitmap = 0x40001c50; ppTxqUpdateBitmap = 0x40001c50;
pp_coex_tx_request = 0x40001c54; /*pp_coex_tx_request = 0x40001c54;*/
pp_hdrsize = 0x40001c58; pp_hdrsize = 0x40001c58;
pp_post = 0x40001c5c; pp_post = 0x40001c5c;
pp_process_hmac_waiting_txq = 0x40001c60; pp_process_hmac_waiting_txq = 0x40001c60;
@@ -1715,7 +1715,7 @@ rcGetHighestRateIdx = 0x40001eac;
/* pm_tx_null_data_done_process = 0x40001eb0; */ /* pm_tx_null_data_done_process = 0x40001eb0; */
/* pm_tx_data_process = 0x40001eb4; */ /* pm_tx_data_process = 0x40001eb4; */
/* pm_attach = 0x40001eb8;*/ /* pm_attach = 0x40001eb8;*/
pm_coex_schm_process = 0x40001ebc; /* pm_coex_schm_process = 0x40001ebc; */
ppInitTxq = 0x40001ec0; ppInitTxq = 0x40001ec0;
pp_attach = 0x40001ec4; pp_attach = 0x40001ec4;
pp_deattach = 0x40001ec8; pp_deattach = 0x40001ec8;
@@ -1975,12 +1975,12 @@ esp_coex_rom_version_get = 0x40002168;
coex_bt_release = 0x4000216c; coex_bt_release = 0x4000216c;
coex_bt_request = 0x40002170; coex_bt_request = 0x40002170;
coex_core_ble_conn_dyn_prio_get = 0x40002174; coex_core_ble_conn_dyn_prio_get = 0x40002174;
coex_core_event_duration_get = 0x40002178; /* coex_core_event_duration_get = 0x40002178; */
coex_core_pti_get = 0x4000217c; coex_core_pti_get = 0x4000217c;
coex_core_release = 0x40002180; coex_core_release = 0x40002180;
coex_core_request = 0x40002184; coex_core_request = 0x40002184;
coex_core_status_get = 0x40002188; coex_core_status_get = 0x40002188;
coex_core_timer_idx_get = 0x4000218c; /* coex_core_timer_idx_get = 0x4000218c; */
coex_event_duration_get = 0x40002190; coex_event_duration_get = 0x40002190;
coex_hw_timer_disable = 0x40002194; coex_hw_timer_disable = 0x40002194;
coex_hw_timer_enable = 0x40002198; coex_hw_timer_enable = 0x40002198;

4
components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
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@@ -6,7 +6,7 @@
esf_buf_alloc = 0x400015bc; esf_buf_alloc = 0x400015bc;
esf_buf_alloc_dynamic = 0x400015c0; esf_buf_alloc_dynamic = 0x400015c0;
esf_buf_recycle = 0x400015c4; esf_buf_recycle = 0x400015c4;
hal_mac_tx_set_ppdu = 0x400015d4; /*hal_mac_tx_set_ppdu = 0x400015d4;*/
ic_mac_deinit = 0x400015dc; ic_mac_deinit = 0x400015dc;
lmacDiscardMSDU = 0x400015f4; lmacDiscardMSDU = 0x400015f4;
/*lmacSetTxFrame = 0x40001628;*/ /*lmacSetTxFrame = 0x40001628;*/
@@ -39,7 +39,7 @@ ieee80211_encap_esfbuf = 0x4000185c;
/*sta_input = 0x40001870;*/ /*sta_input = 0x40001870;*/
ieee80211_crypto_decap = 0x4000189c; ieee80211_crypto_decap = 0x4000189c;
ieee80211_decap = 0x400018a0; ieee80211_decap = 0x400018a0;
coex_core_timer_idx_get = 0x400018d0; /*coex_core_timer_idx_get = 0x400018d0;*/
rom1_chip_i2c_readReg = 0x40001924; rom1_chip_i2c_readReg = 0x40001924;
rom1_chip_i2c_writeReg = 0x40001928; rom1_chip_i2c_writeReg = 0x40001928;
rom_index_to_txbbgain = 0x40001964; rom_index_to_txbbgain = 0x40001964;

4
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
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@@ -1591,7 +1591,7 @@ ppTask = 0x40001720;
ppTxPkt = 0x40001724; ppTxPkt = 0x40001724;
ppTxProtoProc = 0x40001728; ppTxProtoProc = 0x40001728;
ppTxqUpdateBitmap = 0x4000172c; ppTxqUpdateBitmap = 0x4000172c;
pp_coex_tx_request = 0x40001730; /*pp_coex_tx_request = 0x40001730;*/
pp_hdrsize = 0x40001734; pp_hdrsize = 0x40001734;
pp_post = 0x40001738; pp_post = 0x40001738;
pp_process_hmac_waiting_txq = 0x4000173c; pp_process_hmac_waiting_txq = 0x4000173c;
@@ -1760,7 +1760,7 @@ esp_coex_rom_version_get = 0x400018ac;
coex_bt_release = 0x400018b0; coex_bt_release = 0x400018b0;
coex_bt_request = 0x400018b4; coex_bt_request = 0x400018b4;
coex_core_ble_conn_dyn_prio_get = 0x400018b8; coex_core_ble_conn_dyn_prio_get = 0x400018b8;
coex_core_event_duration_get = 0x400018bc; /*coex_core_event_duration_get = 0x400018bc;*/
coex_core_pti_get = 0x400018c0; coex_core_pti_get = 0x400018c0;
coex_core_release = 0x400018c4; coex_core_release = 0x400018c4;
coex_core_request = 0x400018c8; coex_core_request = 0x400018c8;

4
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
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@@ -1894,7 +1894,7 @@ ppSubFromAMPDU = 0x40005694;
ppTxPkt = 0x400056ac; ppTxPkt = 0x400056ac;
ppTxProtoProc = 0x400056b8; ppTxProtoProc = 0x400056b8;
ppTxqUpdateBitmap = 0x400056c4; ppTxqUpdateBitmap = 0x400056c4;
pp_coex_tx_request = 0x400056d0; /*pp_coex_tx_request = 0x400056d0;*/
pp_hdrsize = 0x400056dc; pp_hdrsize = 0x400056dc;
pp_post = 0x400056e8; pp_post = 0x400056e8;
pp_process_hmac_waiting_txq = 0x400056f4; pp_process_hmac_waiting_txq = 0x400056f4;
@@ -2069,7 +2069,7 @@ esp_coex_rom_version_get = 0x40005b68;
coex_bt_release = 0x40005b74; coex_bt_release = 0x40005b74;
coex_bt_request = 0x40005b80; coex_bt_request = 0x40005b80;
coex_core_ble_conn_dyn_prio_get = 0x40005b8c; coex_core_ble_conn_dyn_prio_get = 0x40005b8c;
coex_core_event_duration_get = 0x40005b98; /* coex_core_event_duration_get = 0x40005b98; */
coex_core_pti_get = 0x40005ba4; coex_core_pti_get = 0x40005ba4;
coex_core_release = 0x40005bb0; coex_core_release = 0x40005bb0;
coex_core_request = 0x40005bbc; coex_core_request = 0x40005bbc;

2
components/esp_system/port/soc/esp32c2/clk.c
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@@ -246,7 +246,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32c3/clk.c
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@@ -290,7 +290,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_system/port/soc/esp32s2/clk.c
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@@ -306,7 +306,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0); DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M); DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL32K | DPORT_LPCLK_SEL_XTAL | DPORT_LPCLK_SEL_8M | DPORT_LPCLK_SEL_RTC_SLOW);
DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW); DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);

2
components/esp_system/port/soc/esp32s3/clk.c
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@@ -309,7 +309,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */ /* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */ /* Enable RNG clock. */

2
components/esp_wifi/lib

Submodule components/esp_wifi/lib updated: 3fdca7e317...36c5c4cb9d

5
examples/mesh/manual_networking/partitions.csv Normal file
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@@ -0,0 +1,5 @@
# Name, Type, SubType, Offset, Size, Flags
# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
nvs, data, nvs, 0x9000, 0x6000,
phy_init, data, phy, 0xf000, 0x1000,
factory, app, factory, 0x10000, 1200K,
1 # Name, Type, SubType, Offset, Size, Flags
2 # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
3 nvs, data, nvs, 0x9000, 0x6000,
4 phy_init, data, phy, 0xf000, 0x1000,
5 factory, app, factory, 0x10000, 1200K,

5
examples/mesh/manual_networking/sdkconfig.defaults Normal file
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@@ -0,0 +1,5 @@
CONFIG_PARTITION_TABLE_CUSTOM=y
CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
CONFIG_PARTITION_TABLE_OFFSET=0x8000
CONFIG_PARTITION_TABLE_MD5=y